<s> <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } if ( std :: binary_search ( <ISA_LIT>16IntrinsicHelper , array_endof ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ) { const <ISA_LIT>16IntrinsicHelperType * h = ( std :: find ( <ISA_LIT>16IntrinsicHelper , array_endof ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ) ; <ISA_LIT>16HelperFunction = h -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . Args , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( )


<s> OperandMatchResultTy parseGRX32 ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> } else { basereg = stack_pointer_rtx ; delta = cfun -> machine -> reg_offset ; } for ( i = <NUM_LIT> ; i < CSKY_LR_REGNUM ; i ++ ) if ( reg_mask & ( <NUM_LIT> << i ) ) delta += <NUM_LIT> ; if ( ( CSKY_TARGET_ARCH ( CK801 ) && delta >= CSKY_LD16_MAX_OFFSET ( Pmode ) ) || delta >= CSKY_LD32_MAX_OFFSET ( Pmode ) ) { emit_insn ( gen_movsi ( scratch , GEN_INT ( delta )


<s> void <ISA_LIT>TargetELFStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { setAttributeItem ( Attribute ,


<s> GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Val ) ; if ( ! GA ) return false ; const GlobalVariable * GV = dyn_cast_or_null < GlobalVariable > ( GA -> getGlobal ( ) ) ; if ( ! GV ) return false ; if ( ! GV -> hasAttribute ( <STR_LIT> ) ) return false ; assert ( PointerSize == <NUM_LIT> && <STR_LIT> <STR_LIT>


<s> int ParitySrc [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned Size = Mask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( M % Size ) != i ) return false ; int Src = M / Size ; if ( ParitySrc [ i % <NUM_LIT> ] >= <NUM_LIT> && ParitySrc [ i % <NUM_LIT> ] != Src ) return false ; ParitySrc [ i % <NUM_LIT> ] = Src ; } if ( ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] == ParitySrc [ <NUM_LIT> ] ) return false ; Op0Even = ParitySrc [ <NUM_LIT>


<s> } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; } else { LHS = CCVal ; RHS = DAG . getConstant ( <NUM_LIT> , DL , CCVal . getValueType ( ) ) ; CC =


<s> Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( )


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR2 ( ( v8qi ) mm


<s> break ; case <STR_LIT> : IsSelected = selectAddCarry ( N ) ; break ; case <STR_LIT> : IsSelected = selectSubCarry ( N ) ; break ; case <STR_LIT> : { Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ; ReplaceNode ( N , CurDAG -> getRegister ( GP , N -> getValueType ( <NUM_LIT> ) ) . getNode ( ) ) ; IsSelected = true ; break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant (


<s> return REGNO_REG_SET_P ( ENTRY_BLOCK_PTR -> il . rtl


<s> if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } aarch64_emit_sve_pred_move ( dest , ptrue , src


<s> break ; } } } } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) { if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; } I -> dropAllReferences ( ) ; Dead . insert ( I


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isFPXX ( ) ) return


<s> void <ISA_LIT>32CompilationCallback ( ) { llvm_unreachable ( <STR_LIT> )


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasZ10Insts ( false ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF )

|| MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ;


<s> else { update_base_p = true ; base_reg = XEXP ( XEXP ( base_addr , <NUM_LIT> ) , <NUM_LIT> ) ; } const char * update_base = update_base_p ? <STR_LIT> : <STR_LIT> ; regno = REGNO ( operands [ <NUM_LIT> ] ) ; otherops [ <NUM_LIT> ] = base_reg ; otherops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; if ( regno >= <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno ) ; sprintf ( buff , <STR_LIT> , update_base ,


<s> if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( create<ISA_LIT>CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( create<ISA_LIT>StorePairSuppressPass ( ) ) ; addPass ( create<ISA_LIT>SIMDInstrOptPass ( )


<s> if ( GET_CODE ( op ) == CONST_VECTOR ) { int half_units = GET_MODE_NUNITS ( GET_MODE ( op ) ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < half_units ; ++ i ) { rtx temp = CONST_VECTOR_ELT ( op , i ) ; CONST_VECTOR_ELT ( op , i ) = CONST_VECTOR_ELT ( op , i + half_units ) ; CONST_VECTOR_ELT ( op , i + half_units )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FOp = <STR_LIT> ; MOp = <STR_LIT> ; break ; case <STR_LIT> : FOp = <STR_LIT> ; MOp = <STR_LIT> ; break ; } const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ValOpIdx = <STR_LIT> ; unsigned VSrc = MI . getOperand ( ValOpIdx ) . getReg ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { MachineOperand & Operand = MI . getOperand ( i ) ; if ( Operand . isReg ( ) ) Operand . setIsKill ( false ) ; MIB . add ( Operand ) ; } MachineInstr * FOpMI = MIB ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; MIB . addReg ( FOpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return


<s> bool isLegalMaskedScatter ( Type * Ty , MaybeAlign


<s> return new <ISA_LIT>PostLegalizerCombiner ( IsOptNone )


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p && IN_RANGE ( fcode , ARM_BUILTIN_VFP_BASE , ARM_BUILTIN_ACLE_BASE - <NUM_LIT> ) ) snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , prefix , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , prefix , d -> name ) ; fndecl = add_builtin_function ( namebuf , ftype , fcode , BUILT_IN_MD ,


<s> static inline void desc_mem_stack_v ( unw_word t


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const llvm :: Function & ) const override { return &


<s> return __builtin_mve_vcaddq_rot270_sv4si ( __a ,


<s> if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS ,


<s> void printlea32mem ( const MCInst * MI , unsigned OpNo ) { printLeaMemReference ( MI , OpNo )


<s> void get_ppc476_thunk_name ( char name [ <NUM_LIT> ] ) { gcc_assert (


<s> break ; case ( <STR_LIT> ) : cond = loadN ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadN , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadV ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadV , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> and_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> or_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadN , loadV ) ; break ; case ( <STR_LIT> ) : cond = ctx -> neq ( <NUM_LIT> , loadN , loadV ) ; break ; case ( <STR_LIT> ) : cond = ctx -> and_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadN , loadV ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> or_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> neq ( <NUM_LIT> , loadN , loadV ) ) ; break ; case (


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned SizeEncoding = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; return SizeEncoding - <NUM_LIT>


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ?


<s> static tree aarch64_embedded_comparison_type ( stmt_vec_info stmt_info ) { if ( auto * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ) if ( gimple_assign_rhs_code ( assign ) == COND_EXPR ) { tree cond = gimple_assign_rhs1 (


<s> const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( VT . isFloatingPoint ( ) ) { assert ( VT != <STR_LIT> ) ; if ( VT == <STR_LIT> && ! FullFP16 ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; VT = <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; } unsigned Opcode = <STR_LIT> ; if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } else if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS ) && ! isUnsignedIntSetCC ( CC ) ) { Opcode = <STR_LIT> ; RHS = LHS . getOperand


<s> void <ISA_LIT>InstPrinter :: printGPRPairOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg


<s> if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI


<s> switch ( Family ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : switch ( Model ) { case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } case <NUM_LIT> : switch ( Model ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } case <NUM_LIT> : { switch ( Model ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return ( Em64T ) ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . isLikeA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; return true


<s> assert ( Kind == k_Memory && <STR_LIT> ) ; return AlignmentLoc


<s> case 'i' : mmix_output_shiftvalue_op_from_str ( stream , <STR_LIT> , ( uint64_t ) mmix_intval ( x ) ) ; return ; case 'o' : mmix_output_shiftvalue_op_from_str ( stream , <STR_LIT> , ( uint64_t ) mmix_intval ( x ) ) ; return ; case 's' : mmix_output_shiftvalue_op_from_str ( stream , <STR_LIT> , ( uint64_t ) mmix_intval ( x ) ) ; return ; case 'd' : case 'D' : mmix_output_condition ( stream , x , ( code == 'D' ) ) ; return ; case 'e' : if ( TARGET_FCMP_EPSILON ) fprintf ( stream , <STR_LIT> ) ; return ; case 'm' : if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , <STR_LIT> PRId64 , ( int64_t ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( int64_t ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( int64_t ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ; case <NUM_LIT>


<s> if ( Vector ) { if ( ST -> hasAVX512 ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( ) ) return <NUM_LIT> ; if ( ST -> hasSSE1


<s> static void x86_print_call_or_nop ( FILE * file , const


<s> ShuffleMask . push_back ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) ShuffleMask . push_back ( IsLoad ? static_cast <


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 && unaligned_access && ! BYTES_BIG_ENDIAN ) mode = V16QImode ; else mode = V8QImode ; nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , <NUM_LIT> ) ) ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_const_vec_duplicate ( mode , gen_int_mode ( value , QImode ) ) ; emit_move_insn ( reg , val_vec ) ; i = <NUM_LIT> ; if ( mode == V16QImode ) { mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; i += nelt_mode ; if ( i + nelt_v8 < length && i + nelt_v16 > length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - nelt_mode ) ) ) ; offset += length - nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ; else if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align


<s> Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; unsigned ZMask = Zeroable . to_ulong ( ) ; unsigned InsertPSMask = EltMaskIdx << <NUM_LIT> | EltIdx << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; SDLoc DL ( Op


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set (


<s> a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmplt (


<s> static SDValue LowerANY_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType


<s> static std :: pair < OutputIt1 , OutputIt2 > copy_if_else ( InputIt First , InputIt

Last , OutputIt1 d1 , OutputIt2 d2 , UnaryPredicate Predicate ) {


<s> static SDValue combinePMULH ( SDValue Src , EVT VT , const SDLoc & DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Src . getOpcode ( ) != <STR_LIT> || Src . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> || VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; EVT InVT = Src . getValueType ( ) ; if ( InVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; APInt ShiftAmt ; if ( ! <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) , ShiftAmt ) || ShiftAmt != <NUM_LIT> ) return SDValue ( ) ; SDValue LHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = LHS . getOpcode ( ) ; if ( ( ExtOpc != <STR_LIT> && ExtOpc != <STR_LIT> ) || RHS . getOpcode ( ) != ExtOpc ) return SDValue ( ) ; LHS = LHS . getOperand ( <NUM_LIT>


<s> void <ISA_LIT>InstructionSelector :: renderLogicalImm32 ( MachineInstrBuilder & MIB , const MachineInstr & I ) const { assert ( I . getOpcode ( ) == TargetOpcode


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { return new <ISA_LIT>AsmBackend ( T , MRI , TT , CPU


<s> vtrnq_s32 ( int32x4_t a , int32x4_t b ) { return ( int32x4x2_t ) { vtrn1q_s32 ( a , b ) , vtrn2q_s32 ( a ,


<s> if ( Arg . getOpcode ( ) != <STR_LIT> ) { Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; Mask |= ( Val - <NUM_LIT> ) ; } if ( i != <NUM_LIT> ) Mask <<= <NUM_LIT> ; } return Mask


<s> bool useCheriCapTable ( ) const { return getABI ( ) .


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < N > ( Imm ) ) ) ; return MCDisassembler ::


<s> unsigned calcLiveInMask ( MachineBasicBlock * MBB ) { unsigned Mask = <NUM_LIT> ; for ( MachineBasicBlock :: livein_iterator I = MBB -> livein_begin ( ) , E = MBB -> livein_end ( ) ; I != E ; ++ I ) { unsigned Reg = * I - <STR_LIT> ; if ( Reg < <NUM_LIT> )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG (


<s> const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB (


<s> } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >=

<NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ;


<s> case MEM : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ; if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode || GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode ) return false ; return true


<s> static unsigned getFixedObjectSize ( const MachineFunction & MF , const <ISA_LIT>FunctionInfo * AFI , bool IsWin64 , bool IsFunclet ) { if ( ! IsWin64 || IsFunclet ) { return AFI -> getTailCallReservedStack ( ) ; } else { if ( AFI -> getTailCallReservedStack ( ) != <NUM_LIT> ) report_fatal_error


<s> unsigned ShiftOp = MI -> getOperand ( OpNum ) . getImm ( ) ; bool isASR = ( ShiftOp & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ; unsigned Amt = ShiftOp & <NUM_LIT> ; if ( isASR ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << ( Amt == <NUM_LIT> ? <NUM_LIT> : Amt ) << markup ( <STR_LIT> ) ; } else if


<s> <ISA_LIT>FunctionInfo * FuncInfo = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRSize ( ) > <NUM_LIT> ? FuncInfo -> getVarArgsGPRIndex ( ) : FuncInfo -> getVarArgsStackIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR ,

Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * SplitTy , DL ) ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } for ( unsigned i = <NUM_LIT> ; i < Offsets . size ( ) ; ++ i ) PerformArgSplit ( SplitArgs [ FirstRegIdx +

i ] . Reg , Offsets [ i ] * <NUM_LIT> ) ;


<s> return ! Is64Bit && IsTailCall && getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget ->


<s> static void or1k_print_operand_address ( FILE * file , machine_mode , rtx addr ) { rtx offset ; switch ( GET_CODE ( addr ) ) { case REG : fputc ( '0' , file ) ; break ; case PLUS : offset = XEXP ( addr , <NUM_LIT> ) ; addr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( CONST_INT_P ( offset ) ) ; if ( GET_CODE ( addr ) == LO_SUM ) { print_reloc ( file , XEXP ( addr , <NUM_LIT> ) , INTVAL ( offset ) , RKIND_LO ) ; addr = XEXP ( addr , <NUM_LIT> ) ; } else output_addr_const ( file , offset


<s> static DecodeStatus DecodePPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void


<s> if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_pass_big_vectors = false ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; if ( ! warned_for_pass_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; warned_for_pass_big_vectors = true ; } return <NUM_LIT> ; } return


<s> if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 ) ; else pat = GEN_FCN ( icode ) ( op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn (


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AndResult ) . addReg ( ValReg , getKillRegState ( ValIsKill ) ) . addImm ( <NUM_LIT> ) ; ValReg = AndResult ; } case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE2 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE2 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT>


<s> const MVT ValVT = VA . getValVT ( ) ; return ( ValVT == <STR_LIT> || ValVT == <STR_LIT> ) ? LLT ( ValVT ) : LLT (


<s> const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . hasFusion ( ) ) DAG

-> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ;


<s> int i , nunits = GET_MODE_NUNITS ( mode ) ; if ( GET_CODE ( op ) != CONST_VECTOR || nunits != CONST_VECTOR_NUNITS ( op ) ) return false ; for ( i = <NUM_LIT> ; i < nunits ; i += <NUM_LIT> ) if ( CONST_VECTOR_ELT ( op , i ) != CONST_VECTOR_ELT ( op , i + <NUM_LIT> )


<s> bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + <NUM_LIT> ) ; bitmap_clear ( components


<s> extern_symbol * p = VEC_safe_push ( extern_symbol , gc , extern_symbols , NULL ) ; gcc_assert ( file == asm_out_file ) ; p -> decl = decl ; p -> name


<s> SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = <NUM_LIT> ; DECL_ARTIFICIAL ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; DECL_UNINLINABLE ( decl ) = <NUM_LIT> ; DECL_EXTERNAL ( decl ) = <NUM_LIT> ; DECL_EXTERNAL ( dispatch_decl ) = <NUM_LIT> ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( dispatch_decl ) = <NUM_LIT> ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t


<s> unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( <NUM_LIT> ) ; OutChains . push_back ( Store


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CodeModel :: Medium , OL ) , isLittle ( isLittle

) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) {


<s> case E_V8HImode : case E_V4HImode : gen = gen_neon_vrev32 ; break ; case E_V4SImode : case E_V2SImode : case E_V4SFmode : case E_V2SFmode : gen = gen_neon_vrev64 ; break ; default : return false ; } break ; default : return false ; } for ( i = <NUM_LIT> ; i < nelt ; i += diff + <NUM_LIT> ) for ( j = <NUM_LIT> ; j <= diff ; j += <NUM_LIT> ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] !=


<s> void setROPProtectionHashSaveIndex ( int Idx )


<s> O << <STR_LIT> << MI -> getOperand ( OpNum )


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> :


<s> const MCOperand & ImmMO = MI . getOperand ( OpIdx + <NUM_LIT> ) ; assert ( ImmMO . getImm ( ) >= <NUM_LIT> ) ; Bits |= ( getMachineOpValue ( MI , RegMO , Fixups


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX2 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTbl , ISD , MTy )


<s> ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregxiv2di (


<s> if ( VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> ) { if ( VT == <STR_LIT> ) return std :: make_pair (


<s> } else { unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm (


<s> for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; if ( Opc == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } if ( Opc == <STR_LIT> && ! hasV8Ops ( ) ) { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresV8 ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return Match_RequiresV8 ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( isThumb ( ) && ! hasV8Ops ( ) ) ) return Match_InvalidOperand ; break ; default : break ; } for ( unsigned I = <NUM_LIT> ; I < MCID . NumOperands ; ++ I ) if ( MCID . OpInfo [ I ] .


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ]


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM


<s> if ( ! decl || DECL_EXTERNAL ( decl ) || DECL_WEAK ( decl ) || ! ( * targetm . binds_local_p ) ( decl ) ) return false ; if ( rs6000_fndecl_pcrel_p ( decl ) ) return false ; return true ; } if ( DEFAULT_ABI != ABI_V4 || ( TARGET_SECURE_PLT && flag_pic && ( ! decl || ! ( ( * targetm . binds_local_p ) ( decl ) ) ) ) ) return false ; return


<s> bool hasLegalDstDomain ( ) const { return LegalDstDomains .


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState


<s> if ( ( InputVector . getOpcode ( ) == <STR_LIT> || InputVector . getOpcode ( ) == <STR_LIT> ) && InputVector . getOperand ( <NUM_LIT> ) == EltIdx ) { assert ( SrcVT == InputVector . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Scl = InputVector . getOperand ( <NUM_LIT> ) ; Scl = DAG . getNode ( <STR_LIT> , dl , SrcVT . getScalarType ( ) , Scl ) ; return DAG . getZExtOrTrunc ( Scl , dl , VT ) ; } return SDValue ( ) ; } if ( SDValue NewOp = XFormVExtractWithShuffleIntoLoad ( N , DAG , DCI ) ) return NewOp ; if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineHorizontalMinMaxResult ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = combineReductionToHorizontal ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = scalarizeExtEltFP ( N , DAG ) ) return V ; if ( CIdx && SrcVT . getScalarType ( ) == <STR_LIT> ) { SmallVector < SDNode * , <NUM_LIT> > BoolExtracts ; auto IsBoolExtract = [ & BoolExtracts ] ( SDNode * Use ) { if ( Use -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Use -> getOperand (

<NUM_LIT> ) ) && Use -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) {


<s> static void xstormy16_asm_out_constructor ( rtx symbol , int priority ) { const char * section = <STR_LIT> ; char buf [ <NUM_LIT>


<s> bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args .


<s> return getReg ( isGP64 ( ) ? <STR_LIT>


<s> bool hasCmpxchg16b ( ) const { return HasCmpxchg16b &&


<s> assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> || Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success


<s> bool <ISA_LIT>AsmParser :: ParseIntelDotOperator ( const MCExpr * Disp , const MCExpr * & NewDisp ) { const AsmToken & Tok = Parser . getTok ( ) ; int64_t OrigDispVal , DotDispVal ; if ( const MCConstantExpr * OrigDisp = dyn_cast < MCConstantExpr > ( Disp ) ) OrigDispVal = OrigDisp -> getValue ( ) ; else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; DotDispVal = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { unsigned DotDisp ; std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , DotDisp ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; DotDispVal = DotDisp ; } else return Error ( Tok . getLoc ( ) ,


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , poly_int64 offset ) { HOST_WIDE_INT


<s> TextSections . insert ( TLOFMacho . getTextSection ( ) ) ; for ( Module :: iterator F = M . begin ( ) , e = M . end ( ) ; F != e ; ++ F ) if ( ! F -> isDeclaration ( ) && ! F -> hasAvailableExternallyLinkage ( ) ) TextSections . insert ( TLOFMacho . SectionForGlobal ( F , * Mang , TM ) ) ; TextSections . insert ( TLOFMacho . getTextCoalSection ( ) ) ; TextSections . insert ( TLOFMacho . getConstTextCoalSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = TextSections . size ( ) ; i != e ; ++ i ) OutStreamer . SwitchSection ( TextSections [ i ] ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } const MCSection * StaticInitSect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_REGULAR | MachO :: S_ATTR_PURE_INSTRUCTIONS , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( StaticInitSect ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( ) . getCStringSection ( ) ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SyntaxUnified ) ; if ( Subtarget -> isTargetELF ( ) ) emitAttributes ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { std :: string str ; raw_string_ostream OS ( str ) ; EmitSFIHeaders ( OS


<s> unsigned int compression_flags , nocompression_flags ; compression_flags = mips_get_compress_on_flags ( * attributes ) ; nocompression_flags = mips_get_compress_off_flags ( * attributes ) ; if ( TREE_CODE ( decl ) != FUNCTION_DECL ) { if ( nocompression_flags ) error ( <STR_LIT> , mips_get_compress_off_name ( nocompression_flags ) ) ; if ( compression_flags ) error ( <STR_LIT> , mips_get_compress_on_name ( nocompression_flags ) ) ; } else { compression_flags |= mips_get_compress_on_flags ( DECL_ATTRIBUTES ( decl ) ) ; nocompression_flags |= mips_get_compress_off_flags ( DECL_ATTRIBUTES ( decl ) ) ; if ( compression_flags && nocompression_flags ) error ( <STR_LIT> , DECL_NAME ( decl ) , mips_get_compress_on_name ( compression_flags ) , mips_get_compress_off_name ( nocompression_flags ) ) ; if ( compression_flags & MASK_MIPS16 && compression_flags & MASK_MICROMIPS ) error ( <STR_LIT> , DECL_NAME ( decl ) , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_FLIP_MIPS16 && ! DECL_ARTIFICIAL ( decl ) && compression_flags == <NUM_LIT> && nocompression_flags == <NUM_LIT> ) { name = mflip_mips16_use_mips16_p ( decl ) ? <STR_LIT> : <STR_LIT> ; * attributes = tree_cons ( get_identifier ( name ) , NULL


<s> void Emitter < CodeEmitter > :: emitVEXOpcodePrefix ( uint64_t TSFlags , int MemOperand , const MachineInstr & MI , const MCInstrDesc * Desc ) const { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasVEX_4VOp3 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned char VEX_R = <NUM_LIT> ; unsigned char VEX_X = <NUM_LIT> ; unsigned char VEX_B = <NUM_LIT> ; unsigned char VEX_W = <NUM_LIT> ; unsigned char XOP = <NUM_LIT> ; unsigned char VEX_5M = <NUM_LIT> ; unsigned char VEX_4V = <NUM_LIT> ; unsigned char VEX_L = <NUM_LIT> ; unsigned char VEX_PP = <NUM_LIT> ; if ( TSFlags & <STR_LIT> ) VEX_PP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_W = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) XOP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_L = <NUM_LIT> ; switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } unsigned NumOps = Desc -> getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc -> getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Register ResultReg = createResultReg ( RC ) ; Op0 = constrainOperandRegClass ( II , Op0 , II . getNumDefs ( ) ) ; Op1 = constrainOperandRegClass ( II , Op1 , II . getNumDefs ( ) + <NUM_LIT> ) ; Op2 = constrainOperandRegClass ( II , Op2 , II . getNumDefs ( ) + <NUM_LIT> ) ; Op3 = constrainOperandRegClass ( II , Op3 , II . getNumDefs ( ) +


<s> return ( TARGET_EXT_PERF && ( one_bit_count ==


<s> assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; return ! ( BitSize == <NUM_LIT> ||


<s> <ISA_LIT>ELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer (


<s> if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val > - <NUM_LIT> &&


<s> lshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; shmask = vec_cmplt ( lshift , shmax ) ; result = vec_sl ( ( __v4su ) __A , lshift ) ; result = vec_sel ( ( __v4su )


<s> const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym ) ; EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; OutStreamer -> EmitLabel ( EmittedInitSym ) ; EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV


<s> if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF

( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , <STR_LIT> ) ;


<s> if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO .


<s> if ( ! isDoubleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> && VectorList .


<s> int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_allocate +=


<s> LHS = DAG . getBitcast ( <STR_LIT> , LHS ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , LHS , RHS ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && RHS . hasOneUse ( ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && RHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N ) ; RHS = DAG . getVectorShuffle ( <STR_LIT> , dl , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; RHS = DAG . getBitcast ( <STR_LIT> , RHS ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT>


<s> unsigned getPrefetchDistance ( ) const override


<s> S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler ( )


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; return LT . first


<s> SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasInt256 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasBWI ( ) ) ) { if ( matchShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> == EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ; return true ; } } if ( ( EltSizeInBits % V1 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> && ( EltSizeInBits % V2 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> ) { bool IsBlend = true ; unsigned NumV1Elts = V1 . getValueType ( ) . getVectorNumElements ( ) ; unsigned NumV2Elts = V2 . getValueType ( ) . getVectorNumElements ( ) ; unsigned Scale1 = NumV1Elts / NumMaskElts ; unsigned Scale2 = NumV2Elts / NumMaskElts ; APInt DemandedZeroV1 = APInt :: getNullValue ( NumV1Elts ) ; APInt DemandedZeroV2 = APInt :: getNullValue ( NumV2Elts ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; if ( M == SM_SentinelZero ) { DemandedZeroV1 . setBits ( i * Scale1 , ( i + <NUM_LIT> ) * Scale1 ) ; DemandedZeroV2 . setBits ( i * Scale2 , ( i + <NUM_LIT> ) * Scale2 ) ; continue ; } if ( M == ( int ) i ) { DemandedZeroV2 . setBits ( i * Scale2 , ( i + <NUM_LIT> ) * Scale2 ) ; continue ; } if ( M == ( int ) ( i + NumMaskElts ) ) { DemandedZeroV1 . setBits ( i * Scale1 , (


<s> rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset


<s> } return false ; case <STR_LIT> : if ( ForcedDispEncoding == DispEncoding_Disp32 ) { Inst . setOpcode ( is16BitMode ( ) ? <STR_LIT> : <STR_LIT> ) ; return true ; } return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ForcedVEXEncoding == VEXEncoding_VEX3 || MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> || MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) return false ; unsigned NewOpc ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ;


<s> if ( TARGET_FDPIC && ! flag_pic ) flag_pic = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! VALID_REGISTER_P ( regno ) ) sh_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; for ( regno = <NUM_LIT> ; regno < ADDREGNAMES_SIZE ; regno ++ ) if ( ! VALID_REGISTER_P ( ADDREGNAMES_REGNO ( regno ) ) ) sh_additional_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; if ( flag_pic && ! TARGET_PREFERGOT ) flag_no_function_cse = <NUM_LIT> ; if ( targetm . small_register_classes_for_mode_p ( VOIDmode ) ) { if ( ! TARGET_HARD_SH4 || flag_pic ) flag_schedule_insns = <NUM_LIT> ; else if ( flag_exceptions ) { if ( flag_schedule_insns && global_options_set . x_flag_schedule_insns ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; flag_schedule_insns = <NUM_LIT> ; } else if ( flag_schedule_insns && ! global_options_set . x_flag_schedule_insns ) flag_schedule_insns = <NUM_LIT> ; } if ( ( flag_unwind_tables || flag_asynchronous_unwind_tables || flag_exceptions || flag_non_call_exceptions ) && flag_omit_frame_pointer && !


<s> if ( ResVT . isScalableVector ( ) ) return SDValue ( ) ; assert ( ( N0 . getValueType ( ) == <STR_LIT> || N0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) return SDValue ( ) ; int NumMaskElts = ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ; if ( ! ResVT . isVector ( ) || NumMaskElts == <NUM_LIT> ) return SDValue ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , NumMaskElts ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; if ( CCVT . getSizeInBits ( ) != ResVT . getSizeInBits ( ) ) return SDValue ( ) ; assert ( DCI . isBeforeLegalize ( ) || DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SrcVT ) ) ; SDLoc DL ( N0 ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand


<s> } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt32Immediate ( RHS , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( ( int ) SImm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ,

Xor , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) && shouldTransformMulToShiftsAddsSubs ( C -> getAPIntValue ( ) , VT , DAG , Subtarget ) ) return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy (

DAG . getDataLayout ( ) , VT ) , DAG ) ;


<s> bool hasFRSQRTES ( ) const { return HasFRSQRTES


<s> void <ISA_LIT>ConstantIslands :: updateForInsertedWaterBlock ( MachineBasicBlock * NewBB ) { NewBB -> getParent ( ) -> RenumberBlocks ( NewBB ) ; BBUtils -> insert ( NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = llvm :: lower_bound ( WaterList , NewBB , CompareMBBNumbers ) ; WaterList . insert ( IP


<s> bool MVEVPTBlock :: InsertVPTBlocks ( MachineBasicBlock & Block ) { bool Modified = false ; MachineBasicBlock :: instr_iterator MBIter = Block . instr_begin ( ) ; MachineBasicBlock :: instr_iterator EndIter = Block . instr_end ( ) ; while ( MBIter != EndIter ) { MachineInstr * MI = & * MBIter ; unsigned PredReg = <NUM_LIT> ; DebugLoc dl = MI -> getDebugLoc ( ) ; <STR_LIT> Pred = getVPTInstrPredicate ( * MI , PredReg ) ; assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ) ; int VPTInstCnt = <NUM_LIT> ; <STR_LIT> NextPred ; ++ MBIter ; while ( MBIter != EndIter && VPTInstCnt < <NUM_LIT> ) { NextPred = getVPTInstrPredicate ( * MBIter , PredReg ) ; assert ( NextPred != <STR_LIT> && <STR_LIT> ) ; if ( NextPred != Pred ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MBIter -> dump ( ) ) ; ++ VPTInstCnt ; ++ MBIter ; } ; unsigned BlockMask = <NUM_LIT> ; switch ( VPTInstCnt ) { case <NUM_LIT> : BlockMask = VPTMaskValue :: T ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TT ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TTT ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TTTT ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ; if ( VCMP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( BlockMask ) ; MIBuilder . add ( VCMP ->


<s> if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << ( inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) return Error ( IDLoc , <STR_LIT> ) ; break ; } } if ( has<ISA_LIT>32r6 ( ) && Inst . getOpcode ( ) == <STR_LIT> ) { std :: string ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; Warning ( IDLoc , <STR_LIT> + ISA + <STR_LIT> <STR_LIT> ) ; } if ( MCID . hasDelaySlot ( ) && AssemblerOptions . back ( ) -> isReorder ( ) ) { Instructions . push_back ( Inst ) ; MCInst NopInst ; if ( hasShortDelaySlot ( Inst . getOpcode ( ) ) ) { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; } Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - <NUM_LIT>


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: csky > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> static bool pa_print_operand_punct_valid_p ( unsigned char code ) { if ( code == '@' || code == '#' || code == '*' ||


<s> unsigned RR = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT


<s> return BaseT :: getGatherScatterOpCost ( Opcode , SrcVTy , Ptr , VariableMask , Alignment , CostKind , I ) ; } assert ( SrcVTy -> isVectorTy ( ) && <STR_LIT> ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( cast < VectorType > ( Ptr -> getType ( ) ) -> getElementType ( ) ) ; assert ( PtrTy &&


<s> SDValue Val = DAG . getNode ( Op . getOpcode ( ) , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , SrcVal } ) ; return DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Val . getValue ( <NUM_LIT> ) , Val . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) } ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , SrcVal ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( SrcVal . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getValueType ( ) != <STR_LIT> ) return Op ; return SDValue ( )


<s> assert ( isValidVectorKind ( Name ) ) ; ElementKind = Name . lower ( ) [ Name . size ( ) - <NUM_LIT> ] ; NumElements = <NUM_LIT> ; if ( Name . size ( ) == <NUM_LIT>


<s> if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; if ( ! TM . getDataSections ( ) || GV -> hasSection ( ) ) { OutStreamer -> emitLabel ( EmittedInitSym ) ; } llvm :: for_each ( GOAliasMap [ GV ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getSymbol ( Alias ) ) ; } ) ; emitGlobalConstant ( GV -> getParent ( ) -> getDataLayout (


<s> if ( ! std :: count ( BusyRegs . begin ( ) , BusyRegs . end ( ) , Reg ) ) return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ITBlock . instrInITBlock ( ) && ! ITBlock . instrLastInITBlock ( ) ) S = SoftFail ; break ; default : break ; } unsigned CC ; CC = ITBlock . getITCC ( ) ; if ( CC == <NUM_LIT> ) CC = <STR_LIT> ; if ( ITBlock . instrInITBlock ( ) ) ITBlock . advanceITState ( ) ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator I = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( I == MI . end ( ) ) break ; if ( OpInfo [ i ] . isPredicate ( ) ) { if ( CC != <STR_LIT> && ! <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , SoftFail ) ; I = MI . insert ( I , MCOperand :: createImm ( CC )


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg (


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && !


<s> auto Op = make_unique < <ISA_LIT>Operand > ( KindImmTLS , StartLoc , EndLoc ) ; Op -> ImmTLS . Imm = Imm ; Op -> ImmTLS .


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ReplaceBITCASTResults ( N , Results , DAG ) ; return ; case


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum


<s> return ( VT . getVectorNumElements ( ) == <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M

, VT ) || isPSHUFLWMask ( M , VT ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ;


<s> unsigned MaskTySize = MaskTy -> getPrimitiveSizeInBits ( ) ; ( void ) MaskTySize ; assert ( Width == <NUM_LIT> && Width >= MaskTySize && <STR_LIT> ) ; APInt UndefElts ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , <NUM_LIT> , UndefElts , RawMask ) ) return ; unsigned NumElts = Width / <NUM_LIT> ; assert ( NumElts == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( <STR_LIT> ) ; else Reserved . reset ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ )


<s> return __builtin_mve_vrev32q_sv16qi (


<s> return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize (

) ) && ! MFI -> hasVarSizedObjects ( ) ;


<s> GVSym -> setContainingCsect ( CSect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Align ) ; else OutStreamer -> EmitCommonSymbol ( GVSym , Size , Align


<s> bool flushCacheLineSWAP ( ) const { return FlushCacheLineSWAP


<s> bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl ,

TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ;


<s> static void ATTRIBUTE_UNUSED ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl ,


<s> cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> extra_size = extra_size ; cfun -> machine -> gp_reg_size = gp_reg_size ; cfun -> machine -> fp_reg_size = fp_reg_size ; cfun -> machine -> mask = mask ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> num_gp = gp_reg_size / UNITS_PER_WORD ; if ( mask ) { unsigned long offset ; offset = ( args_size + extra_size + var_size + gp_reg_size - GET_MODE_SIZE ( gpr_mode ) ) ; cfun -> machine -> gp_sp_offset = offset ; cfun -> machine -> gp_save_offset = offset - total_size ; } else { cfun -> machine -> gp_sp_offset = <NUM_LIT> ; cfun -> machine -> gp_save_offset = <NUM_LIT> ; } cfun -> machine -> fp_sp_offset = <NUM_LIT> ; cfun -> machine -> fp_save_offset =


<s> return ( __m256i ) __builtin_ia32_psllqi256 ( ( __v4di


<s> set_block_for_insn ( insn , bb ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; start_sequence ( ) ; emit_insn ( gen_blockage ( ) ) ; fntype = TREE_TYPE ( MEM_EXPR ( address ) ) ; arm_init_cumulative_args ( & args_so_far_v , fntype , NULL_RTX , NULL_TREE ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; machine_mode arg_mode = TYPE_MODE ( arg_type ) ; if ( VOID_TYPE_P ( arg_type ) ) continue ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg_mode , arg_type , true ) ; arg_rtx = arm_function_arg ( args_so_far , arg_mode , arg_type , true ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_mask &= ~ compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , padding_bits_to_clear_ptr ) ; first_param = false ; } cleared_reg = XEXP ( address , <NUM_LIT> ) ; reg = gen_rtx_REG ( SImode , IP_REGNUM ) ; using_r4 = false ; for ( regno = R0_REGNUM ; regno < NUM_ARG_REGS ; regno ++ ) { if ( padding_bits_to_clear [ regno ] == <NUM_LIT> ) continue ; if ( TARGET_THUMB1 && ! using_r4 ) { using_r4 = true ; reg = cleared_reg ; emit_move_insn ( gen_rtx_REG ( SImode , IP_REGNUM ) , reg ) ; } tmp = GEN_INT ( ( ( ( ~ padding_bits_to_clear [ regno ] ) << <NUM_LIT> ) >> <NUM_LIT> ) ) ; emit_move_insn ( reg , tmp ) ; if ( ( ( ~ padding_bits_to_clear [ regno ] ) >> <NUM_LIT> ) > <NUM_LIT> ) { tmp = GEN_INT ( ( ~ padding_bits_to_clear [ regno ] ) >> <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( gen_rtx_ZERO_EXTRACT ( SImode , reg , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , tmp ) ) ; } emit_insn ( gen_andsi3 ( gen_rtx_REG ( SImode , regno ) , gen_rtx_REG ( SImode , regno ) , reg ) ) ; } if ( using_r4 ) emit_move_insn ( cleared_reg , gen_rtx_REG ( SImode , IP_REGNUM ) ) ; tmp = gen_rtx_LSHIFTRT ( SImode , cleared_reg , const1_rtx ) ; emit_insn ( gen_rtx_SET ( cleared_reg , tmp ) ) ; tmp = gen_rtx_ASHIFT ( SImode , cleared_reg , const1_rtx ) ; emit_insn ( gen_rtx_SET ( cleared_reg , tmp ) ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( ! ( to_clear_mask & ( <NUM_LIT> << regno ) ) ) continue ; if ( IS_VFP_REGNUM ( regno ) ) { if ( TARGET_VFP_DOUBLE && VFP_REGNO_OK_FOR_DOUBLE ( regno ) && to_clear_mask & ( <NUM_LIT> << ( regno + <NUM_LIT> ) ) ) emit_move_insn ( gen_rtx_REG ( DFmode , regno ++ ) , CONST0_RTX ( DFmode ) ) ; else emit_move_insn ( gen_rtx_REG ( SFmode , regno )


<s> if ( pOri_width == <NUM_LIT> ) return pVal ; uint64_t mask = ( ~ ( ( uint64_t ) <NUM_LIT> ) ) >> ( <NUM_LIT> - pOri_width ) ; pVal &= mask ; uint64_t sign_bit = <NUM_LIT> << ( pOri_width - <NUM_LIT> ) ; return ( pVal ^ sign_bit ) -


<s> PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple :: Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = nullptr ; UseIntegratedAssembler =


<s> AU . addPreserved < DominatorTreeWrapperPass


<s> for ( auto Ty : { s8 , s16 , s32 , s64 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , s64 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar


<s> rtx sel0 = const0_rtx ; rtx sel1 = const1_rtx ; rtx ( * fn ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) = gen_binary_sf_op ; rtx op = gen_rtx_fmt_ee ( code , SFmode , op1 , op2 ) ; emit_insn ( ( * fn ) ( op0 , op1 , op2 , op , sel0 , sel0 , sel0 , sel1 ) ) ; emit_insn ( ( * fn ) ( op0 , op1 , op2 , op , sel1 , sel1


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None , bool MatchingInlineAsm = false ) { if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg ,


<s> return __builtin_aarch64_smaxpv8qi ( a ,


<s> static const char * detect_processor_freebsd


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ,


<s> SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! Concat0Op1 . isUndef ( ) || ! Concat1Op1 . isUndef ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ;


<s> void * <ISA_LIT>JITInfo :: emitGlobalValueIndirectSym ( const GlobalValue * GV , void * ptr , JITCodeEmitter & JCE ) { const unsigned Alignment = <NUM_LIT> ; uint8_t Buffer [ <NUM_LIT> ] ; uint8_t * Cur = Buffer ; MachineCodeEmitter :: emitWordLEInto ( Cur , ( unsigned ) ( intptr_t ) ptr ) ; MachineCodeEmitter :: emitWordLEInto ( Cur , ( unsigned ) ( ( ( intptr_t ) ptr ) >> <NUM_LIT> ) ) ; const unsigned Alignment = <NUM_LIT> ; uint8_t Buffer [ <NUM_LIT> ] ; uint8_t * Cur = Buffer ; MachineCodeEmitter :: emitWordLEInto ( Cur , ( intptr_t ) ptr ) ; return JCE . allocIndirectGV ( GV , Buffer , sizeof (


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; MachineInstr * FoldCmp = tryFoldIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( FoldCmp ) return { FoldCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; unsigned CmpOpc = <NUM_LIT> ; Register ZReg ; LLT CmpTy = MRI . getType ( LHS . getReg ( ) ) ; assert ( ( CmpTy . isScalar ( ) || CmpTy . isPointer ( ) ) && <STR_LIT> ) ; if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) || CmpTy . isPointer ( ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else { return { nullptr , CmpInst :: Predicate :: BAD_ICMP_PREDICATE } ; } MachineInstr * ImmedCmp = tryOptArithImmedIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( ImmedCmp ) return { ImmedCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; MachineInstr * ShiftedCmp = tryOptArithShiftedCompare ( LHS , RHS , MIRBuilder ) ; if ( ShiftedCmp ) return { ShiftedCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; auto CmpMI = MIRBuilder . buildInstr ( CmpOpc , { ZReg } , { LHS . getReg ( ) , RHS .


<s> tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ; if ( INTEGRAL_TYPE_P ( t ) &&

INTEGRAL_TYPE_P ( builtin_type ) ) return true ;


<s> unsigned <ISA_LIT>CodeEmitter :: getHA16Encoding ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ) ; MCE . addRelocation ( GetRelocation ( MO , <STR_LIT> ) ) ; return <NUM_LIT>


<s> } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return nullptr ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return


<s> static inline uint64_t ror ( uint64_t elt


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { <ISA_LIT>SSELevel = NoSSE ; <ISA_LIT>3DNowLevel = NoThreeDNow ; HasCMov = false ; HasMMX = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; stackAlignment =


<s> temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_subs ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c ,


<s> ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ; size_directive_output = <NUM_LIT> ; if ( ! flag_inhibit_size_directive && DECL_SIZE ( decl ) ) { HOST_WIDE_INT size ; size_directive_output = <NUM_LIT>


<s> DigitalTargetMachine :: DigitalTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < DigitalTargetObjectFile > ( ) ) , ABI ( DigitalABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) { initAsmInfo (


<s> rtx tmp ; if ( ! INSN_P ( x ) || ! INSN_P ( y ) ) return <NUM_LIT> ; tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX


<s> void MandarinAsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ,


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine >


<s> if ( load_store_pendulum != <NUM_LIT> ) { load_store_pendulum = <NUM_LIT> ; return cached_can_issue_more ; } if ( TARGET_P10_FUSION && is_fusable_store ( last_scheduled_insn , & mem1 ) ) { int pos = lastpos ; while ( pos >= <NUM_LIT> ) { rtx mem2 ; if ( is_fusable_store ( ready [ pos ] , & mem2 ) && ( ( INTEGRAL_MODE_P ( GET_MODE ( mem1 ) ) && adjacent_mem_locations ( mem1 , mem2 ) ) || ( FLOAT_MODE_P ( GET_MODE ( mem1 ) ) && ( adjacent_mem_locations ( mem1 ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Shuffle = PerformTargetShuffleCombine ( SDValue ( N , <NUM_LIT> ) , DAG , DCI , Subtarget ) ; if ( Shuffle . getNode ( ) ) return


<s> static bool loongarch_legitimate_address_p ( machine_mode mode , rtx x ,


<s> SDValue Lo , Hi ; DAG . getTargetLoweringInfo ( ) . expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ; return DAG . getMergeValues ( { Lo , Hi } ,


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O


<s> static void ShortenMemoryRef ( MCInst * Inst , unsigned IndexOpPosition ) { unsigned ImmOpPosition = IndexOpPosition - <NUM_LIT> ; unsigned BaseOpPosition = IndexOpPosition - <NUM_LIT> ; unsigned IndexReg = Inst -> getOperand ( IndexOpPosition ) . getReg ( ) ; if ( Inst -> getOperand ( ImmOpPosition ) . getImm ( ) == <NUM_LIT> && Inst -> getOperand ( BaseOpPosition ) . getReg ( ) == <NUM_LIT> ) { Inst -> getOperand ( BaseOpPosition ) . setReg ( IndexReg ) ; Inst -> getOperand ( IndexOpPosition ) . setReg


<s> bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Latency += <NUM_LIT> ; break ; } } return Latency


<s> const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenDestReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenSrcReg ) ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> << * MI ; if ( DestDReg


<s> OperandMatchResultTy parseBDAddr64 ( OperandVector & Operands


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , cookie ) ; n = <NUM_LIT> ; if ( TARGET_SECURE_PLT && flag_pic && GET_CODE ( func_addr ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( func_addr ) ) call [ n ++ ] = gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ; call [ n ++ ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n ,


<s> for ( i = <NUM_LIT> ; i < MAX_VECT_LEN ; ++ i ) XVECEXP ( x , <NUM_LIT> , i ) = const0_rtx ; x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) , x ) ; x = gen_rtx_SET ( VOIDmode , const0_rtx ,


<s> const char * <ISA_LIT>Subtarget :: getBZeroEntry ( )


<s> rtx result = gen_reg_rtx ( TImode ) ; if ( TARGET_SSE2 ) { rtx temp = force_reg ( V2DImode , gen_lowpart ( V2DImode , x ) ) ; rtx lo = gen_lowpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( lo , temp , const0_rtx ) ) ; rtx hi = gen_highpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( hi , temp , const1_rtx ) ) ; } else emit_move_insn ( result , gen_lowpart (


<s> if ( mode != TFmode && FLOAT128_IBM_P ( TFmode ) ) set_conv_libfunc ( trunc_optab , TFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , SDmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , <STR_LIT> ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( TARGET_PPC_GPOPT ) set_optab_libfunc ( sqrt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , <STR_LIT>


<s> assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; if ( VReg ) { assert ( Val -> getType ( ) -> isIntegerTy ( ) && <STR_LIT> ) ; unsigned Size = Val -> getType ( ) -> getPrimitiveSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ResReg = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIRBuilder . setInstr ( * Return , true ) ; MachineInstr * Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , ResReg , VReg ) ; ( void ) Copy ; assert ( Copy -> getNextNode ( ) == Return


<s> case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE (


<s> SmallSet < SDNode * , <NUM_LIT> > LoadRoots ; SmallVector < SDNode * , <NUM_LIT> > Queue ( <NUM_LIT> , Chain . getNode ( ) ) ; SmallSet < SDNode * , <NUM_LIT> > Visited ; while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) . second ) continue ; if ( MemSDNode * ChainLD = dyn_cast < MemSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ; } else LoadRoots . insert