<s> NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; unsigned CallOpc = <STR_LIT> ; bool needIndirectCall = true ; if ( ! isSVR4ABI || ! is<ISA_LIT>64 ) if ( SDNode * Dest = isBLACompatibleAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; needIndirectCall = false ; } if ( isFunctionGlobalAddress ( Callee ) ) { GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Callee ) ; unsigned OpFlags = <NUM_LIT> ; if ( ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( Subtarget . getTargetTriple ( ) . isMacOSX ( ) && Subtarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) && ! G -> getGlobal ( ) -> isStrongDefinitionForLinker ( ) ) || ( Subtarget . isTargetELF ( ) && ! is<ISA_LIT>64 && ! G -> getGlobal ( ) -> hasLocalLinkage ( ) && DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , Callee . getValueType ( ) , <NUM_LIT> , OpFlags ) ; needIndirectCall = false ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( Subtarget . getTargetTriple ( ) . isMacOSX ( ) && Subtarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) || ( Subtarget . isTargetELF ( ) && ! is<ISA_LIT>64 && DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( IsPatchPoint ) { needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain ,


<s> offset = cfun -> machine -> frame . arg_pointer_offset ; break ; default : gcc_unreachable ( ) ; } if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> frame


<s> else if ( POINTER_TYPE_P ( fromtype ) && POINTER_TYPE_P ( totype ) ) { frommode = TYPE_MODE ( TREE_TYPE ( fromtype ) ) ; tomode = TYPE_MODE ( TREE_TYPE ( totype ) ) ; if ( frommode != tomode && frommode != VOIDmode && tomode != VOIDmode ) { if ( frommode == XOmode ) return N_ ( <STR_LIT> ) ; if ( tomode == XOmode ) return N_ ( <STR_LIT> ) ; if ( frommode == OOmode ) return N_ ( <STR_LIT> ) ; if ( tomode == OOmode ) return N_ ( <STR_LIT> ) ; } } return NULL


<s> } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget -> isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> == <NUM_LIT> ) ; Reg >>= <NUM_LIT> ; } } else if ( Prefix == <STR_LIT> ) RC = TRI -> getRegClass ( <STR_LIT> ) ; else if ( Prefix == <STR_LIT> ) { RC = getRegClassFor ( ( VT == <STR_LIT> )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode


<s> return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + Twine

( MF . getFunctionNumber ( ) ) + <STR_LIT> ) ;


<s> return Op ; } else if ( DstVT == <STR_LIT> && SrcVT == <STR_LIT> ) { return ( Subtarget -> is64Bit ( ) ) ? Op : SDValue ( ) ; } else if ( DstVT == <STR_LIT> && SrcVT == <STR_LIT> ) { return ( Subtarget -> is64Bit ( ) )


<s> static void free_bundle_state ( struct


<s> bool isTargetWin64 ( ) const { return Is64Bit && ( TargetType == isMingw || TargetType


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << ( Op . getImm ( ) * <NUM_LIT> ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; } else


<s> bool IsNakedFunction = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; TS . emitDirectiveSetNoReorder ( ) ; TS . emitDirectiveSetNoMacro (


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ]


<s> fprintf ( file , <STR_LIT> , start , processor_target_table [ rs6000_tune_index ] . name ) ; start = <STR_LIT> ; } if ( PPC405_ERRATUM77 ) { fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; } switch ( rs6000_sdata ) { case SDATA_NONE : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_DATA : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n' , file ) ; } if ( ! ( rs6000_default_cpu && rs6000_default_cpu [ <NUM_LIT> ] ) && ! global_options_set . x_rs6000_cpu_index ) { fputs ( <STR_LIT> , asm_out_file ) ; if ( ( rs6000_isa_flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) fputs (


<s> bool targetSchedulesPostRAScheduling ( ) const override { return


<s> MCOperand Offset ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MCID . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Offset = Inst . getOperand ( <NUM_LIT> ) ; if ( ! Offset . isImm ( ) ) break ; if ( ! isIntN ( isMicro<ISA_LIT> ( ) ? <NUM_LIT> : <NUM_LIT> , Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << ( isMicro<ISA_LIT> ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) return Error ( IDLoc , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MCID . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Offset = Inst . getOperand ( <NUM_LIT> ) ; if ( ! Offset . isImm ( ) ) break ; if ( ! isIntN ( isMicro<ISA_LIT> ( ) ? <NUM_LIT> : <NUM_LIT> , Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << ( isMicro<ISA_LIT> ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) return Error ( IDLoc , <STR_LIT> ) ; break ; } } if ( MCID . hasDelaySlot ( ) && Options . isReorder ( ) ) { Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg (


<s> unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; if ( RegAreaSize ) FrameObjOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( ( CC . intArgRegs ( ) . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs


<s> MCSection * <ISA_LIT>ElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( isExecuteOnlyFunction ( GO , SK , TM ) )

SK = SectionKind :: getExecuteOnly ( ) ;


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int


<s> unsigned SrcVecNumElts = Extract . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) / CastedEltBitWidth ; CastVT = <STR_LIT> ( BitCast . getSimpleValueType ( ) . getScalarType ( ) , SrcVecNumElts ) ; return true ; } ; MVT CastVT ; if ( getScaledOffsetDup ( V , Lane , CastVT ) ) { V = DAG . getBitcast ( CastVT , V . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; } else if ( V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getValueType ( ) . is128BitVector ( ) ) { Lane += V . getConstantOperandVal ( <NUM_LIT> ) ; V = V . getOperand ( <NUM_LIT> ) ; } else if ( V . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = Lane >= ( int ) VT . getVectorNumElements ( ) / <NUM_LIT> ; Lane -= Idx * VT . getVectorNumElements ( ) / <NUM_LIT> ; V = WidenVector ( V . getOperand ( Idx ) , DAG


<s> static bool isRepeatedTargetShuffleMask ( unsigned LaneSizeInBits , MVT VT , ArrayRef < int > Mask , SmallVectorImpl


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = TFI -> getFPStackOffset ( ) ; int RAOffset = TFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) ; } int StackSize = ( int )


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm12 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { switch ( MI . getOpcode ( ) ) { default : break ; } assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; uint64_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; uint64_t OffBits = getMachineOpValue ( MI , MI . getOperand


<s> static void arm_override_options_after_change ( void )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFPLRX ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveFPLRX ( Offset ) ; return false


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorSETCC ( Op , DAG ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { assert ( LHS . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , VT ) , DAG . getConstant ( <NUM_LIT> , VT ) , A64cc ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC


<s> if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo +


<s> if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock & prologueMBB = MF . front ( ) ; MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( MachineBasicBlock :: livein_iterator I = prologueMBB . livein_begin ( ) , E = prologueMBB . livein_end ( ) ; I != E ; I ++ ) { stackCheckMBB -> addLiveIn ( * I ) ; incStackMBB -> addLiveIn ( * I ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; if ( Is64Bit ) { SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT> ; CMPop = <STR_LIT> ; CALLop = <STR_LIT> ; SPLimitOffset = <NUM_LIT> ; } else { SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT> ; CMPop = <STR_LIT> ; CALLop = <STR_LIT> ; SPLimitOffset =


<s> OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym ->


<s> SDValue Result = LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ; SDValue Lower = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; SDValue Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DL ) ) ) ; Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Upper ) ; Results . push_back ( Lower


<s> if ( FoldAsLoadDefReg == <NUM_LIT> ) return nullptr ; if ( MI . mayLoad ( ) ) { FoldAsLoadDefReg = <NUM_LIT> ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = <NUM_LIT> ; bool FoundSrcOperand = false ; for ( unsigned i = <NUM_LIT> , e = MI . getDesc ( ) . getNumOperands ( ) ; i != e


<s> default : break ; case Match_Success : { if ( processInstruction ( Inst , IDLoc , Instructions ) ) return true ; for ( unsigned i = <NUM_LIT> ; i < Instructions . size ( ) ; i ++ ) Out . EmitInstruction ( Instructions [ i ] ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> void <ISA_LIT>TargetLowering :: initVPUActions ( ) { for ( MVT LegalVecVT : AllVectorVTs ) { setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Legal ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Legal ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; } for ( MVT LegalPackedVT


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> || Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , <STR_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT>


<s> FOR_BB_INSNS ( bb , insn ) { rtx call , reg , symbol , second_call ; second_call = <NUM_LIT> ; call = mips_call_expr_from_insn ( insn , & second_call ) ; if ( ! call ) continue ; gcc_assert ( MEM_P ( XEXP ( call , <NUM_LIT> ) ) ) ; reg = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ! REG_P ( reg ) ) continue ; symbol = mips_find_pic_call_symbol ( insn , reg , true ) ; if ( symbol ) { mips_annotate_pic_call_expr ( call , symbol ) ; if ( second_call ) mips_annotate_pic_call_expr ( second_call


<s> MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I


<s> rtx pset ; if ( ! live && ( pset = single_set ( insn ) ) && reg_overlap_mentioned_p ( r0_reg , SET_DEST ( pset ) ) && ! find_regno_note ( insn , REG_UNUSED , R0_REG ) ) { set ++ ; live = true ; } } if ( insn == end )


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ==


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; AccOp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , AccOp , Zero ) ; SDValue Rdx = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Pg , AccOp , VecOp ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> if ( ST != <STR_LIT> ) return false ; uint64_t Val = <STR_LIT> ( Shifter . Val ) ; return ( Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val


<s> SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( )


<s> if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m -> fs . cfa_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode


<s> rtx rs6000_longcall_ref ( rtx call_ref ) { const char * call_name ; tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , <NUM_LIT> ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } return force_reg ( Pmode ,


<s> return ( uint16x8_t ) __builtin_aarch64_uaddl2v16qi ( ( int8x16_t ) __a ,


<s> static bool isCalleeLoad ( SDValue Callee , SDValue & Chain , bool HasCallSeq ) { if ( Callee . getNode ( ) == Chain . getNode ( ) || ! Callee . hasOneUse ( ) ) return false ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Callee . getNode ( ) ) ; if ( ! LD || ! LD -> isSimple ( ) || LD -> getAddressingMode ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> ) return false ; while ( HasCallSeq && Chain . getOpcode ( ) != <STR_LIT> ) { if ( ! Chain . hasOneUse ( ) ) return false ; Chain = Chain . getOperand ( <NUM_LIT> ) ; } if ( ! Chain . getNumOperands ( ) )


<s> bool <ISA_LIT>LoadStoreOpt :: tryToPairLdStInst ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator E = MI . getParent ( ) -> end ( ) ; if ( ! TII -> isCandidateToMergeOrPair ( MI ) ) return false ; bool IsUnscaled = TII -> isUnscaledLdSt ( MI ) ; int Offset = getLdStOffsetOp ( MI ) . getImm ( ) ; int OffsetStride = IsUnscaled ? getMemScale ( MI ) : <NUM_LIT> ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , LdStLimit , false ) ; if ( Paired != E ) { ++ NumPairCreated ; if ( TII -> isUnscaledLdSt ( MI ) ) ++ NumUnscaledPairCreated ; MBBI = mergePairedInsns ( MBBI ,


<s> bool csky_tls_referenced_p ( rtx x ) { if ( ! TARGET_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; } return false


<s> Inst . addOperand ( MCOperand :: createImm ( getPrefetch ( )


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Subtarget . hasXOP ( ) || useVPTERNLOG ( Subtarget , VT ) || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ; APInt UndefElts0 , UndefElts1


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getVecShiftR32OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> - MO . getImm


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t _OSABI , StringRef CPU ) : <ISA_LIT>AsmBackend ( T , CPU ) , OSABI ( _OSABI ) { HasReliableSymbolDifference =


<s> Address ( ) : Kind ( RegBase ) , Offset ( <NUM_LIT> ) { Base . Reg


<s> return __builtin_aarch64_reduc_plus_scal_v2sf (


<s> if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == <STR_LIT> || VT == <STR_LIT> ||


<s> MCAsmBackend * llvm :: create<ISA_LIT>leAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU , const MCTargetOptions & Options ) { if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , MRI ) ; if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T ,


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { Offset = N . getOperand


<s> int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) { rtx sub = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getTarget ( ) . getSubtarget < TargetSubtargetInfo > ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ; for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I -> getBlock ( ) ) ) Changed = true ; return Changed


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg (


<s> static int mips_register_priority ( int hard_regno ) { if ( TARGET_MIPS16 && TEST_HARD_REG_BIT ( reg_class_contents [ M16_REGS ]


<s> return buildAUTIA ( MBB , DL , MI ) . addReg ( Ptr , RegState :: Define ) . addUse (


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable


<s> } return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } case AsmToken :: Integer : { StringRef ErrMsg ; if ( isParsingInlineAsm ( ) && SM . getAddImmPrefix ( ) ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Tok . getLoc ( ) ) ) ; SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal ( ) ; End = consumeToken ( ) ; UpdateLocLex = false ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { StringRef IDVal = getTok ( ) . getString ( ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { MCSymbol * Sym = getContext ( ) . GetDirectionalLocalSymbol ( IntVal , IDVal == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ; const MCExpr * Val = MCSymbolRefExpr :: Create ( Sym , Variant , getContext ( ) ) ; if ( IDVal == <STR_LIT> && Sym -> isUndefined ( ) ) return Error ( Loc , <STR_LIT> ) ; StringRef Identifier = Sym -> getName ( ) ; SM . onIdentifierExpr ( Val , Identifier ) ; End = consumeToken ( ) ; } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } break ; } case AsmToken :: Plus : SM . onPlus ( ) ; break ; case AsmToken :: Minus : SM . onMinus ( ) ; break ; case AsmToken :: Star : SM . onStar ( ) ; break ; case AsmToken :: Slash : SM . onDivide ( ) ; break ; case AsmToken :: Pipe : SM . onOr ( ) ; break ; case AsmToken :: Amp : SM . onAnd ( ) ; break ; case AsmToken :: LessLess : SM . onLShift ( ) ; break ; case AsmToken :: GreaterGreater : SM . onRShift ( ) ; break ; case AsmToken :: LBrac : SM . onLBrac ( ) ; break ; case AsmToken :: RBrac : SM . onRBrac ( ) ; break ; case AsmToken :: LParen : SM . onLParen ( )


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Commute = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( N1 ) && ( ! Commute || ! isa < ConstantSDNode > ( N0 ) || ( Op . getOpcode ( ) != <STR_LIT> && IsFoldableRMW ( N1 , Op ) ) ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ( Commute && ! isa < ConstantSDNode > ( N1 ) ) || ( Op . getOpcode ( ) != <STR_LIT> && IsFoldableRMW ( N0 , Op ) ) ) ) return false ; if ( IsFoldableAtomicRMW ( N0 , Op ) || ( Commute && IsFoldableAtomicRMW ( N1 , Op ) ) ) return false ; } } PVT = <STR_LIT> ; return true


<s> Value * <ISA_LIT>IREmitter :: visitWrapperPIC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_DISP ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF


<s> Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType


<s> auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const auto & RhsSym = cast < MCSymbolELF > ( static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ) ; unsigned Other = Symbol -> getOther (


<s> SmallString < <NUM_LIT> > NameStr ( magic_label ) ; MCSymbol * magic_symbol = TLOF -> getContext ( ) . getOrCreateSymbol ( NameStr ) ; OutStreamer -> EmitLabel ( magic_symbol ) ; OutStreamer -> emitFill ( <NUM_LIT> , <NUM_LIT> ) ; } AsmPrinter :: EmitFunctionEntryLabel


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) ||

F -> hasFnAttribute ( Attribute :: StackAlignment ) ) ;


<s> assert ( ( ZeroMask | UndefMask | LoadMask ) . count ( ) == NumElems && <STR_LIT> ) ; if ( UndefMask . count ( ) == NumElems ) return DAG . getUNDEF ( VT ) ; if ( ( ZeroMask | UndefMask ) . count ( ) == NumElems ) return VT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , DL , VT ) : DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; int FirstLoadedElt = LoadMask . find_first ( ) ; SDValue EltBase = peekThroughBitcasts ( Elts [ FirstLoadedElt ] ) ; LoadSDNode * LDBase = cast < LoadSDNode > ( EltBase ) ; EVT LDBaseVT = EltBase . getValueType ( ) ; bool IsConsecutiveLoad = true ; bool IsConsecutiveLoadWithZeros = true ; for ( int i = FirstLoadedElt + <NUM_LIT> ; i <= LastLoadedElt ; ++ i ) { if ( LoadMask [ i ] ) { SDValue Elt = peekThroughBitcasts ( Elts [ i ] ) ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . areNonVolatileConsecutiveLoads ( LD , LDBase , Elt . getValueType ( ) . getStoreSizeInBits ( ) / <NUM_LIT> , i - FirstLoadedElt ) ) { IsConsecutiveLoad = false ; IsConsecutiveLoadWithZeros = false ; break ; } } else if ( ZeroMask [ i ] ) { IsConsecutiveLoad = false ; } } auto CreateLoad = [ & DAG , & DL ] ( EVT VT , LoadSDNode * LDBase ) { auto MMOFlags = LDBase -> getMemOperand ( ) -> getFlags ( ) ; assert ( ! ( MMOFlags & MachineMemOperand :: MOVolatile ) && <STR_LIT> ) ; SDValue NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , MMOFlags ) ; DAG . makeEquivalentMemoryOrdering ( LDBase , NewLd ) ; return NewLd ; } ; if ( FirstLoadedElt == <NUM_LIT> && LastLoadedElt == ( int ) ( NumElems - <NUM_LIT> ) && ( IsConsecutiveLoad || IsConsecutiveLoadWithZeros ) ) { assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType


<s> return acle_vector_types [ <NUM_LIT> ] [ mode_suffix ( ) . base_vector_type


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { if ( Count % <NUM_LIT> != <NUM_LIT> ) return


<s> Binary |= encodeNEONRd ( MI , <NUM_LIT> ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Op = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Cmode = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Imm3 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Imm4 = Imm & <NUM_LIT> ; Binary |= ( I << <NUM_LIT> ) | ( Imm3 << <NUM_LIT> ) | ( Cmode << <NUM_LIT> ) | ( Op << <NUM_LIT> ) | Imm4 ; if ( IsThumb ) Binary = convertNEONDataProcToThumb ( Binary


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isInteger ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; RxSBGOperands RISBG ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> && RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return false ; if ( Count == <NUM_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; if ( RISBG . Rotate == <NUM_LIT> ) { bool PreferAnd = false ; if ( VT == <STR_LIT> ) PreferAnd = true ; else if ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) PreferAnd = true ; else if ( auto * Load = dyn_cast < LoadSDNode > ( RISBG . Input ) ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New . getNode ( ) ; } SelectCode ( N ) ; return true ; } } unsigned Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) ) { Opcode =


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true


<s> static inline void desc_spill_base ( unw_word pspoff , struct unw_state_record * sr ) { sr -> spill_offset = <NUM_LIT>


<s> switch ( CM ) { default : break ; case CodeModel :: Default : case CodeModel :: JITDefault : CM = CodeModel ::


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue TheBit = Op . getOperand ( <NUM_LIT> ) ; SDValue IfTrue = Op . getOperand ( <NUM_LIT> ) ; SDValue IfFalse = Op . getOperand ( <NUM_LIT> ) ; TheBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue A64CMP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , TheBit

. getValueType ( ) ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s8 , s16 , s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; setAction ( { G_ZEXT , s32 } , Legal ) ; setAction ( { G_SEXT , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) { setAction ( { G_ZEXT , <NUM_LIT> , Ty


<s> if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } if ( Subtarget -> useMovt ( )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __bextri_u32 ( unsigned int __X , const unsigned int __I ) { return __builtin_ia32_bextri_u32 ( __X ,


<s> void addExternalFunction ( MCSymbol * Symbol ) { Externals . insert (


<s> void <ISA_LIT>FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU )


<s> if ( INTVAL ( locality ) <= <NUM_LIT> ) return GEN_INT ( INTVAL ( write ) + <NUM_LIT> ) ; if ( INTVAL ( locality ) <=


<s> void encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const override { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; switch ( Size ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( IsLittleEndian ) { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } break ; case <NUM_LIT> : if ( IsLittleEndian ) { uint64_t Swapped = ( Bits << <NUM_LIT> ) | ( Bits >> <NUM_LIT> ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint64_t > ( Swapped ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint64_t > ( Bits ) ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; } ++


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get

( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ;


<s> CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForNode ( CallConv , true , isVarArg


<s> if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnes ( NumBits )

, DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) /


<s> bool isGPRZeroAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_GPR && RegIdx .


<s> if ( FenceCallAndRet ) return ; mergePredStateIntoSP ( MBB , InsertPt , Loc , PS ->

SSA . GetValueAtEndOfBlock ( & MBB ) ) ;


<s> } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; const char * IntrMemName = isa < MemCpyInst > ( I ) ?


<s> if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT . getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ; return


<s> mips_lo_relocs [ SYMBOL_64_MID ] = <STR_LIT> ; mips_split_p [ SYMBOL_64_LOW ] = true ; mips_hi_relocs [ SYMBOL_64_LOW ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_64_LOW ] = <STR_LIT> ; mips_split_p [ SYMBOL_ABSOLUTE ] = true ; mips_lo_relocs [ SYMBOL_ABSOLUTE ] = <STR_LIT> ; } } else { if ( TARGET_EXPLICIT_RELOCS || mips_split_addresses_p ( ) || TARGET_MIPS16 ) { mips_split_p [ SYMBOL_ABSOLUTE ] = true ; mips_hi_relocs [ SYMBOL_ABSOLUTE ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_ABSOLUTE ] = <STR_LIT> ; } } } if ( TARGET_MIPS16 ) { mips_split_p [ SYMBOL_GP_RELATIVE ] = true ; mips_lo_relocs [ SYMBOL_GP_RELATIVE ] = <STR_LIT> ; } else if ( TARGET_EXPLICIT_RELOCS ) mips_lo_relocs [ SYMBOL_GP_RELATIVE ] = <STR_LIT> ; if ( TARGET_EXPLICIT_RELOCS ) { mips_split_p [ SYMBOL_GOT_PAGE_OFST ] = true ; if ( TARGET_NEWABI ) { mips_lo_relocs [ SYMBOL_GOTOFF_PAGE ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_GOT_PAGE_OFST ] = <STR_LIT> ; } else { mips_lo_relocs [ SYMBOL_GOTOFF_PAGE ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_GOT_PAGE_OFST ] = <STR_LIT> ; } if ( TARGET_MIPS16 ) mips_split_hi_p [ SYMBOL_GOT_PAGE_OFST ] = true ; if ( TARGET_XGOT ) { mips_split_p [ SYMBOL_GOT_DISP ] = true ; mips_split_p [ SYMBOL_GOTOFF_DISP ] = true ; mips_hi_relocs [ SYMBOL_GOTOFF_DISP ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_GOTOFF_DISP ] = <STR_LIT> ; mips_split_p [ SYMBOL_GOTOFF_CALL ] = true ; mips_hi_relocs [ SYMBOL_GOTOFF_CALL ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_GOTOFF_CALL ] = <STR_LIT> ; } else { if ( TARGET_NEWABI ) mips_lo_relocs [ SYMBOL_GOTOFF_DISP ] = <STR_LIT> ; else mips_lo_relocs [ SYMBOL_GOTOFF_DISP ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_GOTOFF_CALL ] = <STR_LIT> ; if ( TARGET_MIPS16 ) mips_split_p [ SYMBOL_GOT_DISP ] = true ; } } if ( TARGET_NEWABI ) { mips_split_p [ SYMBOL_GOTOFF_LOADGP ] = true ; mips_hi_relocs [ SYMBOL_GOTOFF_LOADGP ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_GOTOFF_LOADGP ] = <STR_LIT> ; } mips_lo_relocs [ SYMBOL_TLSGD ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_TLSLDM ] = <STR_LIT> ; if ( TARGET_MIPS16_PCREL_LOADS ) { mips_use_pcrel_pool_p [ SYMBOL_DTPREL ] = true ; mips_use_pcrel_pool_p [ SYMBOL_TPREL ] = true ; } else { mips_split_p [ SYMBOL_DTPREL ] = true ; mips_hi_relocs [ SYMBOL_DTPREL ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_DTPREL ] = <STR_LIT> ; mips_split_p [ SYMBOL_TPREL ] = true ; mips_hi_relocs [ SYMBOL_TPREL ] = <STR_LIT> ; mips_lo_relocs [ SYMBOL_TPREL ] =


<s> bool isTargetDarwin ( ) const { return TargetType ==


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl


<s> SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Mask = MGT -> getMask ( ) ; SDValue BasePtr = MGT -> getBasePtr ( ) ; <STR_LIT> ExtTy = MGT -> getExtensionType ( ) ; <STR_LIT> IndexType = MGT -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IdxNeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; bool ResNeedsSignExtend = ExtTy == <STR_LIT> || ExtTy == <STR_LIT> ; EVT VT = PassThru . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { VT = VT . changeVectorElementTypeToInteger ( ) ; ElementCount EC = VT . getVectorElementCount ( ) ; auto ScalarIntVT = <STR_LIT> ( <STR_LIT> / EC . getKnownMinValue ( ) ) ; PassThru = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ScalarIntVT , EC ) , PassThru ) ; InputVT = DAG . getValueType ( MemVT

. changeVectorElementTypeToInteger ( ) ) ;


<s> if ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) return ( uint64_t ) ( ( INT64_C ( <NUM_LIT> ) << <NUM_LIT> ) >> ( Val & <NUM_LIT> ) ) ; return ( ( uint64_t ) INT64_C ( - <NUM_LIT> ) >> ( Val & <NUM_LIT>


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; } } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitVSHLI ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn


<s> Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && parseParenSuffix ( Name , Operands ) ) return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; return false


<s> ParseMemory ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S , E ; assert ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) && <STR_LIT> ) ; S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & BaseRegTok = Parser . getTok ( ) ; if ( BaseRegTok . isNot ( AsmToken :: Identifier ) ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return true ; } int BaseRegNum = TryParseRegister ( ) ; if ( BaseRegNum == - <NUM_LIT> ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return true ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Comma ) && ! Tok . is ( AsmToken :: RBrac ) ) return true ; bool Preindexed = false ; bool Postindexed = false ; bool OffsetIsReg =


<s> bool isImm0_7 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> return ( __m128i ) __builtin_ia32_pmovsqd128_mask ( ( __v2di ) __A , ( __v4si ) _mm_undefined_si128 ( ) ,


<s> push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> && REG_MODE_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , mode ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> && ! ALTIVEC_VECTOR_MODE ( mode ) && GET_MODE_SIZE ( mode ) >= UNITS_PER_WORD && TARGET_POWERPC64 ) { x = gen_rtx_PLUS ( GET_MODE ( x ) , x , GEN_INT ( <NUM_LIT> ) ) ; push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( x , <NUM_LIT> ) ) < FIRST_PSEUDO_REGISTER && REG_MODE_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , mode ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ! SPE_VECTOR_MODE ( mode ) && ! ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DImode ) ) && ! ALTIVEC_VECTOR_MODE ( mode ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; HOST_WIDE_INT low = ( ( val & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; HOST_WIDE_INT high = ( ( ( val - low ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( high + low != val ) { * win = <NUM_LIT> ; return x ; } x = gen_rtx_PLUS ( GET_MODE ( x ) , gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high ) ) , GEN_INT ( low ) ) ; push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == SYMBOL_REF && ! ALTIVEC_VECTOR_MODE ( mode ) && DEFAULT_ABI == ABI_DARWIN && ( flag_pic || MACHO_DYNAMIC_NO_PIC_P ) && DEFAULT_ABI == ABI_V4 && ! flag_pic && mode != TFmode && ( mode != DImode || TARGET_POWERPC64 ) ) { if ( flag_pic ) { rtx offset = gen_rtx_CONST ( Pmode , gen_rtx_MINUS (

Pmode , x , machopic_function_base_sym ( ) ) ) ;


<s> return Kind == k_Register && Reg . Kind == RegKind :: SVEVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> static DecodeStatus DecodeThumbBLXOffset ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder

) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> inline vector signed int vec_sr ( vector signed


<s> DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection = <STR_LIT> ; DwarfMacInfoSection = <STR_LIT> ; SupportsExceptionHandling = true ; AbsoluteEHSectionOffsets = false ; DwarfEHFrameSection = <STR_LIT> ; DwarfExceptionSection = <STR_LIT> ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLinux ( ) ) NonexecutableStackDirective


<s> if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= <NUM_LIT> ) return false ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , <NUM_LIT> , XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ) ; if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , <NUM_LIT> ) ) ) return true ; } if ( GET_CODE ( pat ) !=


<s> return ( __m512i ) __builtin_ia32_cvtps2qq512_mask ( ( __v8sf ) __A , ( __v8di ) _mm512_setzero_si512 ( )

, ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> static bool classof ( const <ISA_LIT>MCExpr *


<s> if ( ! DestEVT . isSimple ( ) ) return <NUM_LIT> ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | OpFlags ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | OpFlags ) . addImm ( <NUM_LIT> ) ; } return ResultReg


<s> if ( isTargetELF ( ) && TM . isPositionIndependent ( ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( TargetMachine & TM ) : TargetLowering ( TM , new TargetLoweringObjectFileELF ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( )


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { switch ( static_cast < <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) . GetEnumValue ( ) ) { case <ISA_LIT>ABIInfo :: <STR_LIT> : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: <STR_LIT> : return


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return true ; else if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) )


<s> FunctionPass * llvm :: create<ISA_LIT>BranchRelaxation


<s> virtual void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst


<s> mcld :: ResolveInfo * resolveInfo = pModule . getNamePool ( ) . createSymbol ( <STR_LIT> , false , mcld :: ResolveInfo :: Section , mcld :: ResolveInfo :: Define , mcld :: ResolveInfo :: Local , <NUM_LIT> , mcld :: ResolveInfo :: Hidden ) ; if ( resolveInfo == nullptr ) { return nullptr ; } mcld :: LDSymbol * inputSym = mcld :: LDSymbol :: Create


<s> static SDValue PerformShiftCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformSRACombine ( N , DCI ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT ,


<s> UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto NewTBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( OldBranchCode == BranchCode && TBB == NewTBB ) continue ; if ( TBB == NewTBB && ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) ) { BranchCode = <STR_LIT> ; } else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) { if ( NewTBB != ( FBB ? FBB : getFallThroughMBB


<s> return ( __m128 ) __builtin_ia32_movss ( ( __v4sf ) __A , ( __v4sf )


<s> static unsigned getStoreRegOpcode ( unsigned SrcReg , const TargetRegisterClass * RC , bool isStackAligned , TargetMachine & TM ) { unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( isHReg ( SrcReg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return NULL ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm <


<s> } if ( len >= <NUM_LIT> ) { emit_insn ( gen_cpymem8b ( out , in , out , in ) ) ; len -= <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= <NUM_LIT> ; offset += <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( Pmode


<s> return __builtin_mve_vldrwq_gather_base_uv4si ( __addr ,


<s> FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_NE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_NE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SGT } , { RTLIB :: OLT_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_UEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: ICMP_EQ } , { RTLIB :: UO_F32 , CmpInst :: ICMP_NE } } ; FCmp64Libcalls . resize ( CmpInst :: LAST_FCMP_PREDICATE + <NUM_LIT> ) ; FCmp64Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F64 , CmpInst :: ICMP_SGE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F64 , CmpInst :: ICMP_SGT } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F64 , CmpInst :: ICMP_SLE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F64 , CmpInst :: ICMP_SLT } } ; FCmp64Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB


<s> return ( ( qword ) ( vec_xor ( ( vec_uchar16 ) ( a ) , vec_splat

( ( vec_uchar16 ) ( si_from_uchar ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> fprintf ( asm_out_file , <STR_LIT> , directive


<s> static <ISA_LIT>Operand * CreateCCOut ( unsigned RegNum , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand (


<s> unsigned int max_common_align ; max_common_align = TARGET_64BIT ? <NUM_LIT> : ( size >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( align > max_common_align ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , align /

BITS_PER_UNIT , name , max_common_align / BITS_PER_UNIT ) ;


<s> SDValue LoadLinkSP = DAG . getLoad ( PtrVT , dl , Chain , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( LoadLinkSP . getValue ( <NUM_LIT> ) , dl , SP , SaveSP ) ; return DAG . getStore ( Chain , dl , LoadLinkSP , StackPtr ,


<s> unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned UserOffset = getUserOffset ( U ) ; int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createPICLabelUId ( ) ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP , CloserWater ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } const Align Alignment = isThumb ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; if ( NewMBB -> getAlignment ( ) < Alignment ) NewMBB -> setAlignment ( Alignment ) ; if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . add ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPEAlign ( U . CPEMI ) ) ; BBUtils -> adjustBBSize ( NewIsland , Size ) ; BBUtils -> adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex (


<s> if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> )

return splitVectorIntBinary ( Op , DAG ) ;


<s> auto MBBStart = MBB -> rend ( ) ; for ( int i = <NUM_LIT> ; ( i < SearchBound ) && ( MI != MBBStart ) ; ++ i , ++ MI ) for ( auto & Op : MI -> implicit_operands ( ) ) if ( ( Op . getReg ( ) == <STR_LIT> ) && ( Op


<s> __o = __builtin_aarch64_ld2rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; return


<s> static bool finishStackBlock ( SmallVectorImpl < CCValAssign > & PendingMembers , MVT LocVT , <STR_LIT> & ArgFlags , CCState & State , unsigned SlotAlign ) { unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackAlign = State . getMachineFunction ( ) . getSubtarget ( ) . getDataLayout ( ) -> getStackAlignment ( ) ; unsigned Align = std :: min ( ArgFlags . getOrigAlign ( ) , StackAlign ) ; for ( auto & It : PendingMembers ) { It . convertToMem ( State . AllocateStack ( Size , std :: max ( Align ,


<s> ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi


<s> static long ppc_linux_aux_vector ( long which ) { extern long * __libc_stack_end ; long argc ; char * * argv ; char * * envp ; struct auxv { long a_type ; long a_val ; } * auxp ; argc = __libc_stack_end [ <NUM_LIT> ] ; argv = ( char * * ) __libc_stack_end + <NUM_LIT> ; envp = argv + argc + <NUM_LIT> ; while ( * envp ++ ) continue ; for ( auxp = ( struct auxv * ) envp ; auxp -> a_type != <NUM_LIT> ; ++ auxp ) if ( auxp -> a_type == which ) return auxp -> a_val ; return


<s> static DecodeStatus DecodeBaseAddSubImm ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned S = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned ShifterVal = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned ImmVal = Imm & <NUM_LIT> ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( ShifterVal != <NUM_LIT> && ShifterVal != <NUM_LIT>


<s> bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( SrcReg != <STR_LIT> ) { const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( SrcReg ) ; unsigned CopyOpc = ( RC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , dl , TII -> get ( CopyOpc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; } unsigned OpOpc = <NUM_LIT> ; bool NeedPred = false , NeedCC = false , NeedOp3 = false ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; NeedCC = true ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; NeedCC = true ; NeedOp3 = true ; break ; } MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( OpOpc ) , <STR_LIT> ) ; if ( OpOpc == <STR_LIT> ) AddDefaultT1CC ( MIB ) ; MIB . addReg ( <STR_LIT> ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NeedOp3 ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NeedPred ) AddDefaultPred ( MIB ) ; if ( NeedCC ) AddDefaultCC


<s> <ISA_LIT>TTI ( ) : ImmutablePass ( ID ) , TM ( <NUM_LIT> ) , ST ( <NUM_LIT> ) , TLI ( <NUM_LIT> ) { llvm_unreachable ( <STR_LIT>


<s> if ( d -> testing_p ) return true ; for ( i = mask = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask |= ( d -> perm [ i ] & <NUM_LIT> ) << ( i * <NUM_LIT> ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ <NUM_LIT> ] ; t0 = gen_reg_rtx ( V4HImode


<s> if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( DataTy -> isVectorTy ( ) ) { unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != <NUM_LIT> ) return


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> static rtx rs6000_emit_vector_compare_inner ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx mask ; machine_mode mode = GET_MODE ( op0 ) ; switch ( code ) { default : break ; case GE : if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) return NULL_RTX ; case EQ : case GT : case GTU : case ORDERED : case UNORDERED : case UNEQ : case LTGT : mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask ; } return


<s> assert ( hasFP ( MF ) && <STR_LIT> ) ; UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) UseFP = true ; } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void ) Subtarget ; assert ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) && <STR_LIT> ) ; UseFP = true ; } else { if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; StackOffset FPOffset = { ObjectOffset , <STR_LIT> } ; StackOffset SPOffset = SVEStackSize + StackOffset ( ObjectOffset , <STR_LIT> ) + StackOffset ( OffsetToSVEArea , <STR_LIT> ) ; if ( hasFP ( MF ) && ( SPOffset . getBytes ( ) || FPOffset . getScalableBytes ( ) < SPOffset . getScalableBytes ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR ) ) ScalableOffset = - SVEStackSize ; if ( ! UseFP && ( isFixed || isCSR ) ) ScalableOffset = SVEStackSize ; if ( UseFP )


<s> static SDValue LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue Op5 = Op . getOperand ( <NUM_LIT> ) ; bool isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) -> getZExtValue ( ) != <NUM_LIT> ; unsigned isLL = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue


<s> bool <ISA_LIT>TargetLowering :: isLegalT2ScaledAddressingMode ( const AddrMode & AM , EVT VT ) const { int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale == <NUM_LIT> ) return true ; Scale = Scale


<s> return ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST ||


<s> return ( poly8x8x2_t ) { vtrn1_p8 ( a , b


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr >

( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ;


<s> void addGPR32AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> cum -> words = <NUM_LIT> ; cum -> prototype_p = fntype && TYPE_ARG_TYPES ( fntype ) ; cum -> libcall_p = fntype


<s> unsigned int regno ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_MMX_REG ; else if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 ) regno = FIRST_FLOAT_REG ; else regno = AX_REG ; if ( mode == HFmode || mode == BFmode ) regno = FIRST_SSE_REG ; if ( mode == HCmode ) { rtx ret = gen_rtx_PARALLEL ( mode , rtvec_alloc (


<s> unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( BaseOffset + Offset , DL , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo . getWithOffset ( Offset ) , Alignment , St . getMemOperand ( ) -> getFlags ( ) ) ; Offset += EltOffset ; } return NewST1


<s> static DecodeStatus DecodeCRBITRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const


<s> void InstrumentMemOperandEpilogue ( const RegisterContext & RegCtx , MCContext & Ctx , MCStreamer & Out ) override { unsigned LocalFrameReg = RegCtx . ChooseFrameReg ( <NUM_LIT> ) ; assert ( LocalFrameReg != <STR_LIT> ) ; RestoreFlags ( Out ) ; if ( RegCtx . ScratchReg ( <NUM_LIT> ) != <STR_LIT> ) RestoreReg

( Out , RegCtx . ScratchReg ( <NUM_LIT> ) ) ;


<s> Instruction * SVEExpandLibCall :: CreateLastB ( Value * GP , Value * Vec ) { SmallVector < Value * , <NUM_LIT> > Args { GP , Vec } ; <STR_LIT> IntID = <STR_LIT> ; auto * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , Vec -> getType ( ) ) ; return CallInst :: Create ( Intr -> getFunctionType ( ) , Intr ,


<s> int group_count = <NUM_LIT> ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more )


<s> MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == <NUM_LIT> ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true


<s> bool <ISA_LIT>FunctionInfo :: isLiveInSExt ( unsigned VReg ) const { for ( const std :: pair < unsigned , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return


<s> if ( gt_p ) lab = gen_label_rtx ( ) ; xstormy16_emit_cbranch ( unsigned_p ? LTU : LT , gt_p ? lab : loc ) ; xstormy16_emit_cbranch ( gt_p ? NE : EQ , loc ) ; if ( gt_p ) emit_label ( lab ) ; return ; } else if ( mode == SImode && ( code == NE || code == EQ ) && op1 != const0_rtx ) { rtx lab = NULL_RTX ; int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; if ( code == EQ ) lab = gen_label_rtx ( ) ; for ( i = <NUM_LIT> ; i < num_words - <NUM_LIT> ; i ++ ) { xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( NE , code == EQ ? lab : loc ) ; } xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp ; tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , op0 ) ; op0 = tmp ; } condition_rtx = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ; cy_clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( BImode ) ) ; if ( mode == HImode ) vec = gen_rtvec ( <NUM_LIT> , branch , cy_clobber ) ; else if ( code == NE || code == EQ ) vec = gen_rtvec ( <NUM_LIT> , branch , gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; else { rtx sub ; sub = gen_rtx_SET ( VOIDmode , op0 , gen_rtx_MINUS ( SImode , op0 , op1 ) ) ; sub = gen_rtx_CLOBBER ( SImode , op0 ) ; vec = gen_rtvec ( <NUM_LIT> , branch , sub , cy_clobber ) ; } emit_jump_insn ( gen_rtx_PARALLEL ( VOIDmode


<s> if ( Opnd0 . getOpcode ( ) != <STR_LIT> || ! Opnd0 -> hasNUsesOfValue ( ExpectedUses , <NUM_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return false ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; bool AllowFusion = ( Options . AllowFPOpFusion == FPOpFusion ::


<s> continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else return true ; Cond [ <NUM_LIT> ] . setImm ( BranchCode ) ; } return


<s> CurDAG -> computeKnownBits ( Op , KnownZero , KnownOne ) ; uint64_t NonZeroBits = ( ~ KnownZero ) . getZExtValue ( ) ; uint64_t AndImm ; if ( isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , AndImm ) ) { assert ( ( ~ APInt ( BitWidth , AndImm ) & ~ KnownZero ) == <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } uint64_t ShlImm ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShlImm ) ) return false ; Op = Op .


<s> const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - <NUM_LIT> || size >


<s> inline static bool isPostOp ( unsigned AluOp


<s> } rx_get_stack_layout ( & low , & high , & register_mask , & frame_size , & stack_size ) ; total_size = frame_size + stack_size ; regs_size = ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ; if ( is_sibcall || is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) || register_mask ) { if ( total_size ) gen_safe_add ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( total_size ) , false ) ; if ( MUST_SAVE_ACC_REGISTER ) { unsigned int acc_low , acc_high ; if ( register_mask ) { acc_low = acc_high = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) if ( register_mask & ( <NUM_LIT> << reg ) ) { if ( acc_low == <NUM_LIT> ) acc_low = reg ; else { acc_high = reg ; break ; } } emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , acc_high ) ) ) ; emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , acc_low ) ) ) ; } else { acc_low = low ; acc_high = low + <NUM_LIT> ; emit_insn ( gen_stack_popm ( GEN_INT ( <NUM_LIT> * UNITS_PER_WORD ) , gen_rx_popm_vector ( acc_low , acc_high )


<s> unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackUp ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { MVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I ,


<s> if ( Relocs . size ( ) < <NUM_LIT> ) return ; llvm :: sort ( Relocs . begin ( ) , Relocs . end ( ) , [ ] ( const ELFRelocationEntry & A , const ELFRelocationEntry & B ) { return A . Offset < B . Offset ; } ) ; std :: list < <ISA_LIT>RelocationEntry > Sorted ; std :: list < ELFRelocationEntry > Remainder ; LLVM_DEBUG ( dumpRelocs ( <STR_LIT> , Relocs ) ) ; copy_if_else ( Relocs . begin ( ) , Relocs . end ( ) , std :: back_inserter ( Remainder ) , std :: back_inserter ( Sorted ) , [ ] ( const ELFRelocationEntry & Reloc ) { return getMatchingLoType ( Reloc ) != ELF :: R_MIPS_NONE ; } ) ; for ( auto & R : Remainder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << R << <STR_LIT> ) ; unsigned MatchingType = getMatchingLoType ( R ) ; assert ( MatchingType != ELF :: R_MIPS_NONE && <STR_LIT> ) ; auto InsertionPoint = find_best ( Sorted . begin ( ) , Sorted . end ( ) , [ & R , & MatchingType ] ( const <ISA_LIT>RelocationEntry & X ) { return isMatchingReloc ( X , R , MatchingType ) ; } , compareMatchingRelocs ) ; if ( InsertionPoint != Sorted . end ( ) ) InsertionPoint


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 : case FK_Data_4 : return <NUM_LIT> ; case FK_PCRel_8 : case FK_SecRel_8


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isDereferenceableInvariantLoad ( AA ) ) { Register BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) { if ( ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) return true ; Register BaseReg = MI . getOperand ( <NUM_LIT>


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; unsigned EncodedVal = ( RegWidth - CE -> getValue ( ) ) % RegWidth ; Inst . addOperand ( MCOperand :: CreateImm (


<s> MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> ,


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmfaa ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( HasFP ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( NumBytes > <NUM_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( NumBytes ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr :: FrameSetup ) ; if ( STI . isTargetELF ( ) && HasFP ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( RegInfo -> needsStackRealignment ( MF )


<s> static SDValue lowerVectorShuffleWithUNPCK ( SDLoc DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { int NumElts = VT . getVectorNumElements ( ) ; bool Unpckl = true ; bool Unpckh = true ; bool UnpcklSwapped = true ; bool UnpckhSwapped = true ; int NumEltsInLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned LaneStart = ( i / NumEltsInLane ) * NumEltsInLane ; int LoPos = ( i % NumEltsInLane ) / <NUM_LIT> + LaneStart + NumElts * ( i % <NUM_LIT> ) ; int HiPos = LoPos + NumEltsInLane / <NUM_LIT> ; int LoPosSwapped = ( LoPos + NumElts ) % ( NumElts * <NUM_LIT> ) ; int HiPosSwapped = ( HiPos + NumElts ) % ( NumElts * <NUM_LIT> ) ; if ( Mask [ i ] == - <NUM_LIT> ) continue ; if ( Mask [ i ] != LoPos


<s> if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; KnownBits Known ; DAG . computeKnownBits ( SubusLHS , Known ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc ( SubusLHS


<s> fntype = TREE_TYPE ( * node ) ; if ( TREE_CODE ( * node ) == VAR_DECL || TREE_CODE ( * node ) == TYPE_DECL ) decl = * node ; } else fntype = * node ; while ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) fntype = TREE_TYPE ( fntype ) ; if ( ( DECL_P ( * node ) && ! decl ) || TREE_CODE ( fntype ) != FUNCTION_TYPE ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } * no_add_attrs |= cmse_func_args_or_return_in_stack ( NULL , name , fntype ) ; if ( * no_add_attrs ) return NULL_TREE ; if ( decl ) { type = build_distinct_type_copy ( TREE_TYPE ( decl ) ) ; TREE_TYPE ( decl ) = type ; } else { type = build_distinct_type_copy ( * node ) ; * node = type ; } fntype = type ; while ( TREE_CODE ( fntype ) != FUNCTION_TYPE ) { type = fntype


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T , OSABI , STI ) ; return new ELF<ISA_LIT>_32AsmBackend ( T , OSABI


<s> return __builtin_aarch64_sminpv2df ( a , b


<s> rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , <NUM_LIT> ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; enum machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , <NUM_LIT> ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , <NUM_LIT> ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode ,


<s> DefMI = MRI -> getVRegDef ( InTileReg ) ; if ( InMBB != & MBB || ! DefMI -> isPHI ( ) ) continue ; InMO = & PHI -> getOperand ( I ) ; break ; } if ( ! InMO ) continue ; Register DefTileReg ; for ( unsigned I = <NUM_LIT> , E = DefMI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { MachineBasicBlock * InMBB = PHI -> getOperand ( I + <NUM_LIT> ) . getMBB ( ) ; if ( InMBB != & MBB )


<s> inline vector signed char vec_vmaxsb ( vector signed char a1 , vector signed char


<s> static bool isEndChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ; return isMask_64 (


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned >