<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += <NUM_LIT> ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( <NUM_LIT> ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = <NUM_LIT> , e = CSI . size ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool isVecListThreeDHWordIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> &&


<s> unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < <NUM_LIT> ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , <ISA_LIT>FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize


<s> MF -> insert ( MBBI , NewBB ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> replaceSuccessor ( BB , NewBB ) ; ++ NumJTInserted


<s> void addSImm7s16Operands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( N00 . getOpcode ( ) == <STR_LIT> && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = true ; } else if ( ( N00 . getOpcode ( ) == <STR_LIT> || N00 . getOpcode ( ) == <STR_LIT> ) && N00 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { MaskOK = Mask . isIntN ( N00 . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) ; } if ( MaskOK && Mask != <NUM_LIT> ) { SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant (


<s> FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : { if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , <ISA_LIT>Expr , MCFixupKind ( FixupKind


<s> sum_a = ( vec_ushort8 ) vec_sum4s ( ( vec_uchar16 ) ( a ) , zero ) ; sum_b = ( vec_ushort8 ) vec_sum4s ( ( vec_uchar16 ) ( b ) , zero ) ; return ( ( qword ) ( vec_perm ( sum_a , sum_b , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> rs6000_gen_builtins fcode = ( rs6000_gen_builtins ) code ; if ( fcode >= RS6000_OVLD_MAX ) return error_mark_node ; return rs6000_builtin_decls [ code


<s> MachineMemOperand * MMO = cast < LoadSDNode > ( Origin ) -> getMemOperand ( ) ; if ( ! Subtarget . hasP9Vector ( ) && MMO -> getSize ( ) <= <NUM_LIT> ) return true ; for ( SDNode :: use_iterator UI = Origin -> use_begin ( ) ,


<s> } else if ( SignedVal >= INT32_MIN && SignedVal <= INT32_MAX ) { Extension = <STR_LIT> ; MemType = <STR_LIT> ; } else { Extension = <STR_LIT> ; MemType = <STR_LIT> ; } Constant * CV = ConstantInt :: get ( Type :: getIntNTy ( * CurDAG -> getContext ( ) , MemType . getSizeInBits ( ) ) , UnsignedVal ) ; SDValue PoolAddr ; unsigned Alignment = TLI . getDataLayout ( ) -> getABITypeAlignment ( CV -> getType ( ) ) ; PoolAddr = CurDAG -> getNode ( <STR_LIT> , DL , PtrVT , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getConstant ( Alignment , <STR_LIT> ) ) ; return CurDAG -> getExtLoad ( Extension , DL , DestType , CurDAG -> getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool

( ) , MemType , false , false , Alignment ) . getNode ( ) ;


<s> void <ISA_LIT>RegisterInfo :: lowerCRRestore ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2div16qi


<s> Value * <ISA_LIT>IREmitter :: visitVDUP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> return createMachOStreamer ( Ctx , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter


<s> void <ISA_LIT>AsmPrinter :: emitAsanReportError ( Module & M , unsigned Reg , const ASanAccessInfo & AccessInfo , MCSubtargetInfo & STI ) { std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; MCSymbol * ReportError = OutContext . getOrCreateSymbol ( <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT>


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO .


<s> if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) return Error ( L , <STR_LIT> ) ; bool WasThumb = isThumb ( ) ; MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , CPU , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; FixModeAfterArchChange ( WasThumb ,


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; EVT VVT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VVT . getVectorElementType ( ) . getSizeInBits ( ) >> <NUM_LIT> ; int Val = <NUM_LIT> ; unsigned i , e ; for ( i = <NUM_LIT> , e = VVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Val = SVOp -> getMaskElt ( i


<s> unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> static MCStreamer * createWinCOFFStreamer ( MCContext & Ctx , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter

, bool RelaxAll , bool IncrementalLinkerCompatible ) {


<s> inline int vec_all_nlt ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgtfp_p ( __CR6_EQ , a2


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo


<s> assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i :


<s> if ( OpNum < <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Inst . setOpcode ( NewOpcode


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second .


<s> ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VSPLTISW0 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW1 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW2 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW3 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSLDOI4 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( ) , DAG , dl ) ; case OP_VSLDOI8 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( ) , DAG , dl ) ; case OP_VSLDOI12 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( ) ,


<s> } else if ( auto val = getIConstantVRegVal ( CarryInReg , MRI ) ) { if ( * val != <NUM_LIT> ) return false ; Opcode = <STR_LIT> ; } else return false ; MachineInstr & AddInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) , DstReg ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , CarryOutReg ) . addReg ( <STR_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( AddInst , TII , TRI , RBI ) || ! RBI . constrainGenericRegister ( CarryOutReg , <STR_LIT> , MRI ) ) return false ; I . eraseFromParent ( ) ; return


<s> unsigned getNumLocalDynamicTLSAccesses ( ) const { return NumLocalDynamics


<s> bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; bool CallConv = MF . getFunction ( ) . getCallingConv ( )


<s> cbranch_trace ( rtx_insn * insn ) : cbranch_insn ( insn ) , condition_rtx_in_insn ( NULL ) , cbranch_type (

unknown_branch_condition ) , setcc ( ) {


<s> if ( n_uses < <NUM_LIT> ) return false ; best_new_reg = find_rename_reg ( head , super_class , unavailable , reg , false ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , reg_names [ reg ] , INSN_UID ( head -> first -> insn ) ) ; if ( head -> need_caller_save_reg ) fprintf ( dump_file , <STR_LIT> ) ; } if ( best_new_reg == reg ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; return false ; } if ( regrename_do_replace ( head ,


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None

) addPass ( create<ISA_LIT>CTRLoopsVerify ( ) ) ;


<s> MCAsmBackend * llvm :: createThumbLEAsmBackend ( const Target & T , const MCRegisterInfo &


<s> bool hasXSAVES ( ) const { return HasXSAVES


<s> OS << <STR_LIT> ; LastInst -> print ( OS , NULL , true ) ; if ( KillInst ) { OS << <STR_LIT> ; KillInst -> print ( OS , NULL , true ) ; OS << <STR_LIT> ; } OS << <STR_LIT>


<s> Size = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * <NUM_LIT>

) , ValVReg ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> MachineBasicBlock * OrigBB = MI -> getParent ( ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MF -> insert ( ++ OrigBB -> getIterator ( ) , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; BlockInfo . insert ( BlockInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; computeBlockSize ( * OrigBB ) ; computeBlockSize ( * NewBB ) ; adjustBlockOffsets ( * OrigBB ) ; ++


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return <STR_LIT>


<s> if ( code >= RS6000_BUILTIN_COUNT ) return error_mark_node ; fnmask = rs6000_builtin_info [ code ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; } return rs6000_builtin_decls [


<s> return ( isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ) || ( isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( )


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> )

) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm (


<s> Darwin<ISA_LIT>_64AsmBackend ( const Target & T , StringRef CPU ) : Darwin<ISA_LIT>AsmBackend


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ; assert ( MO . isImm ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get


__artificial__ ) ) _mm_clflush ( void const * __A ) {


<s> return new <ISA_LIT>BlockPlacement ( )


<s> SmallVectorImpl < CCValAssign > & PendingHAMembers = State . getPendingLocs ( ) ; assert ( PendingHAMembers . size ( ) < <NUM_LIT> ) ; if ( PendingHAMembers . size ( ) > <NUM_LIT> ) assert ( PendingHAMembers [ <NUM_LIT> ] . getLocVT ( ) == LocVT ) ; PendingHAMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ArgFlags . isInConsecutiveRegsLast ( ) ) { assert ( PendingHAMembers . size ( ) > <NUM_LIT> && PendingHAMembers . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; ArrayRef < uint16_t > RegList ; switch ( LocVT . SimpleTy ) { case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingHAMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingHAMembers . begin ( ) ; It != PendingHAMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingHAMembers . clear ( ) ; return true ; } for ( unsigned regNo = <NUM_LIT> ; regNo < <NUM_LIT> ; ++ regNo ) State . AllocateReg ( SRegList [ regNo ] ) ; unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned Align = std :: min ( Size , <NUM_LIT> ) ; for ( auto It : PendingHAMembers ) { It . convertToMem ( State . AllocateStack ( Size , Align ) ) ; State . addLoc (


<s> const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; } else { O << * Op . getExpr


<s> if ( TT . isOSBinFormatELF ( ) ) return llvm :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) || TT . isWindowsCoreCLREnvironment ( ) ) return llvm :: make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return llvm :: make_unique < TargetLoweringObjectFileCOFF >


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> return ( <NUM_LIT> - i / <NUM_LIT> ) * <NUM_LIT> + i


<s> for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents [ i ] . Tag == Attribute ) return & Contents [ i ] ; return nullptr


<s> ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; return ret


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printOperand ( MI , OpNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNum , O ) ; O <<


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return lowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return Fail ; DecodeZPRRegisterClass ( Inst , Zdn , Addr , Decoder ) ; if ( Inst . getOpcode ( ) != <STR_LIT> ) DecodeZPRRegisterClass ( Inst , Zdn


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectConcatVector ( SDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) || N -> getNumOperands ( ) != <NUM_LIT> ) llvm_unreachable


<s> case SYMBOL_REF : case CLOBBER : case REG : return <NUM_LIT> ; case VEC_CONCAT : case ASM_INPUT : case ASM_OPERANDS : return <NUM_LIT> ; case CONST_VECTOR : { * special = SH_CONST_VECTOR ; return <NUM_LIT> ; } case VEC_DUPLICATE : if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( op ) ) == GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == TRUNCATE && REG_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( op ) ) == GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_SELECT ) return rtx_is_swappable_p ( XEXP ( op , <NUM_LIT> ) , special ) ; else return <NUM_LIT> ; case VEC_SELECT : if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && GET_MODE_INNER ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) == GET_MODE ( op ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && GET_CODE ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) == CONST_INT ) { * special = SH_EXTRACT ; return <NUM_LIT> ; } else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_CONCAT && ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DFmode || GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DImode ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && GET_CODE ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) == CONST_INT && GET_CODE ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) == CONST_INT ) { * special = SH_XXPERMDI ; return <NUM_LIT> ; } else if ( v2df_reduction_p ( op ) ) return <NUM_LIT> ; else return <NUM_LIT> ; case UNSPEC : { int val = XINT ( op , <NUM_LIT> ) ; switch ( val ) { default : break ; case UNSPEC_VBPERMQ : case UNSPEC_VMRGH_DIRECT : case UNSPEC_VMRGL_DIRECT : case UNSPEC_VPACK_SIGN_SIGN_SAT : case UNSPEC_VPACK_SIGN_UNS_SAT : case UNSPEC_VPACK_UNS_UNS_MOD : case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT : case UNSPEC_VPACK_UNS_UNS_SAT : case UNSPEC_VPERM : case UNSPEC_VPERM_UNS : case UNSPEC_VPERMHI : case UNSPEC_VPERMSI : case UNSPEC_VPERMXOR : case UNSPEC_VPKPX : case UNSPEC_VSLDOI : case UNSPEC_VSLO : case UNSPEC_VSRO : case UNSPEC_VSUM2SWS : case UNSPEC_VSUM4S : case UNSPEC_VSUM4UBS : case UNSPEC_VSUMSWS : case UNSPEC_VSUMSWS_DIRECT : case UNSPEC_VSX_CONCAT


<s> inline static unsigned makePostOp ( unsigned AluOp ) { assert ( ! isPreOp ( AluOp ) &&


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; Triple T ( TT ) ; bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( RM == Reloc :: Default ) { if ( T . isOSDarwin ( ) ) { if ( is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: DynamicNoPIC ; } else if ( T . isOSWindows ( ) && is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: Static ; } if ( RM == Reloc


<s> free_bundle_state_chain = NULL ; allocated_bundle_states_chain = NULL


<s> case <STR_LIT> : if ( FramePtr == Reg && ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) ) return true ; break ; case <STR_LIT> : return STI . isR9Reserved (


<s> __v8hu rshift = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v8hi result ; if ( __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) rshift = ( __v8hu ) vec_splat_s16 ( __B ) ; else rshift = vec_splats ( ( unsigned short ) __B ) ; } result = vec_sra ( ( __v8hi ) __A , rshift ) ; return ( __m128i


<s> output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } } else { output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_SOM || ! TARGET_GAS ) { operands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> ,


<s> for ( Target * T : { & The<ISA_LIT>32Target , & The<ISA_LIT>64Target , & The<ISA_LIT>64LETarget } ) { RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( * T , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( *


<s> unsigned Tmp1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Tmp2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Tmp1 ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Tmp2 ) . addReg ( Tmp1 ) . addReg ( Hi ) . addImm ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Dest ) . addReg ( Tmp2 ) . addReg (


<s> void <ISA_LIT>16InstrInfo :: ExpandFEXT_CCRX16_ins ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SltOpc ) const { unsigned CC = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get (

SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) ) { assert ( MAI . doesSetDirectiveSuppressReloc ( ) ) ; MCSymbol * Label = Ctx . createTempSymbol ( ) ; AsmPrinter . OutStreamer -> EmitAssignment ( Label , Expr ) ; Expr = MCSymbolRefExpr :: create ( Label , Ctx ) ; } break ; } if ( ! Expr ) Expr = MCSymbolRefExpr :: create ( Sym , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr ( Expr


<s> _Unwind_Reason_Code __aeabi_unwind_cpp_pr0 ( _Unwind_State state , _Unwind_Control_Block * ucbp , _Unwind_Context * context ) { return __gnu_unwind_pr_common ( state , ucbp ,


<s> if ( left ) return IN_RANGE ( INTVAL ( x ) , <NUM_LIT> , bit_width - <NUM_LIT> ) ; else return IN_RANGE ( INTVAL ( x


<s> FunctionPass * create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>TargetMachine &


<s> if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ; else gcc_unreachable ( )


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum


<s> int <ISA_LIT>AsmParser :: matchMSA128CtrlRegisterName ( StringRef Name ) { int CC ; CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> )

. Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( MRI -> use_nodbg_empty ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) )


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS


<s> void <ISA_LIT>AsmParser :: warnIfAssemblerTemporary ( int RegIndex , SMLoc Loc ) { if ( ( RegIndex != <NUM_LIT> ) && ( ( int ) AssemblerOptions . back ( ) -> getATRegNum ( ) == RegIndex ) ) { if ( RegIndex == <NUM_LIT> ) Warning ( Loc , <STR_LIT>


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F )


<s> ptr -> x_ix86_cmodel = CM_SMALL_PIC ; break ; case CM_MEDIUM : ptr -> x_ix86_cmodel = CM_MEDIUM_PIC ; break ; case CM_LARGE : ptr -> x_ix86_cmodel = CM_LARGE_PIC ; break ; case CM_KERNEL : error ( <STR_LIT> , <STR_LIT> ) ; break ; default : break ; } else switch ( ptr -> x_ix86_cmodel ) { case CM_SMALL_PIC : ptr -> x_ix86_cmodel = CM_SMALL ; break ; case CM_MEDIUM_PIC : ptr -> x_ix86_cmodel = CM_MEDIUM ; break ; case CM_LARGE_PIC : ptr -> x_ix86_cmodel


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CodePointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; } else { WinEHEncodingType = WinEH :: EncodingType :: <ISA_LIT> ; } ExceptionsType = ExceptionHandling


<s> } } } bool returnsFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; if ( returnsFPReg ) assert ( STI -> hasFPRegs ( ) && <STR_LIT> ) ; for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder VLLDM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( STI -> fixCMSE_CVE_2021_35465 ( ) ) { auto Bundler = MIBundleBuilder ( MBB , VLLDM ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; if ( STI -> hasFPRegs ( ) ) Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ) ; else Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addImm ( InlineAsm :: Extra_HasSideEffects ) ) ; finalizeBundle ( MBB , Bundler . begin ( ) , Bundler . end ( ) ) ; } for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1


<s> else if ( ! strcmp ( value , <STR_LIT> ) ) * flag = <NUM_LIT> ; else if ( ! strcmp ( value , <STR_LIT> ) ) * flag = <NUM_LIT> ; else error ( <STR_LIT> , name


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_altivec_lvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> static unsigned int rx_function_arg_boundary ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED ) { if ( TARGET_GCC_ABI ) return STACK_BOUNDARY ; if ( type ) { if ( DECL_P ( type ) ) return DECL_ALIGN ( type ) ; return TYPE_ALIGN ( type ) ; } return PARM_BOUNDARY


<s> rtx_insn * top ; rtx reg ; rtx_insn * insn ; if ( cfun -> is_thunk ) return <NUM_LIT> ; if ( cfun -> machine -> lr_save_state ) return cfun -> machine -> lr_save_state - <NUM_LIT> ; push_topmost_sequence ( ) ; top = get_insns ( ) ; pop_topmost_sequence ( ) ; reg = gen_rtx_REG ( Pmode , LR_REGNO ) ; for ( insn = NEXT_INSN ( top ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) { if ( ! SIBLING_CALL_P ( insn ) ) return <NUM_LIT> ; } else if ( find_regno_note ( insn , REG_INC , LR_REGNO ) ) return <NUM_LIT> ; else if ( set_of ( reg , insn ) != NULL_RTX && ! prologue_epilogue_contains ( insn )


<s> if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { ELFFileFormat * file_format = getOutputFormat ( ) ; LDSection & got = file_format -> getGOT ( ) ; m_pGOT = new <ISA_LIT>_64GOT ( got ) ; LDSection & gotplt = file_format -> getGOTPLT ( ) ; m_pGOTPLT = new <ISA_LIT>_64GOTPLT ( gotplt ) ; LDSection & plt = file_format -> getPLT ( ) ; plt . setAlign ( <NUM_LIT> ) ; m_pPLT = new <ISA_LIT>_64PLT ( plt , * m_pGOTPLT , config ( ) ) ; LDSection & relplt = file_format ->


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getMemRI34PCRelEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; uint64_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; assert ( RegBits == <NUM_LIT> && <STR_LIT> ) ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( ! MO . isExpr ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) ) & <NUM_LIT> ) | RegBits ; const MCExpr * Expr = MO . getExpr ( ) ; switch ( Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> rtx in , out , outsub , val ; out = operands [ <NUM_LIT> ] ; in = operands [ <NUM_LIT> ] ; val = operands [ <NUM_LIT> ] ; if ( xstormy16_onebit_set_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_iorqi3_internal ( out , in , val ) ) ; if ( out != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , out ) ; return ; } if ( ! REG_P ( in ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! REG_P ( val ) && ! CONST_INT_P ( val ) ) val = copy_to_mode_reg ( QImode , val ) ; if ( ! REG_P ( out ) ) out = gen_reg_rtx


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectShiftA_32 ( const MachineOperand & Root ) const { auto MaybeImmed = getImmedFromMO ( Root ) ; if ( MaybeImmed == None || * MaybeImmed > <NUM_LIT> ) return None ; uint64_t Enc = ( <NUM_LIT> - * MaybeImmed )


<s> if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack


<s> return ! reg_classes_intersect_p ( FP_REGS , rclass


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo (


<s> break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; unsigned Alignment = DAG . getEVTAlignment ( Tmp . getValueType ( ) ) ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; Alignment = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Alignment ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , Alignment ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr ; RLI . MPI = MPI ; RLI . Alignment


<s> if ( ! TREE_CONSTANT ( decl ) ) readonly = <NUM_LIT> ; break ; default : break ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) encoding = name [ <NUM_LIT> ] ; else encoding = <NUM_LIT> ; if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) mep_unique_section ( decl , <NUM_LIT> ) ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) { if ( encoding == 'f' ) return vftext_section ; else return vtext_section ; } else if ( encoding == 'f' ) return ftext_section ; else return text_section ; } if ( TREE_CODE ( decl ) == VAR_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) switch ( name [ <NUM_LIT> ] ) { case 'b' : return based_section ; case 't' : if ( readonly ) return srodata_section ; if ( DECL_INITIAL ( decl ) ) return sdata_section ; return tinybss_section ; case 'f' : if ( readonly ) return frodata_section ; return far_section ; case 'i' : case 'I' : error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT>


<s> SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; }


<s> TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; unsigned Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset


<s> if ( eax == <NUM_LIT> ) return ; asm volatile ( <STR_LIT> : <STR_LIT> ( eax ) , <STR_LIT> ( ebx ) , <STR_LIT> ( ecx ) , <STR_LIT> ( edx ) : <STR_LIT> ( <NUM_LIT> ) ) ; if ( edx & SSE ) { unsigned int mxcsr = __builtin_ia32_stmxcsr ( ) ; mxcsr |= MXCSR_FTZ ; if ( edx & FXSAVE ) { struct { unsigned short int cwd ; unsigned short int swd ; unsigned short int twd ; unsigned short int fop ; long int fip ; long int


<s> unsigned getCommonDomains ( unsigned mask ) const { return AvailableDomains &


<s> FunctionPass * llvm :: create<ISA_LIT>MulMulBugPass ( ) { return new <ISA_LIT>MulMulBugFix


<s> MVT MaskVT = Mask . getSimpleValueType ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; if ( MaskVT . getVectorElementType ( ) != <STR_LIT> ) { if ( PassThru . isUndef ( ) || <STR_LIT> ( PassThru . getNode ( ) ) ) return Op ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getOffset ( ) , Mask , getZeroVector ( VT , Subtarget , DAG , dl ) , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getAddressingMode ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Select = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Select , NewLoad . getValue ( <NUM_LIT> ) } , dl ) ; } assert ( ( ! N -> isExpandingLoad ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isExpandingLoad ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; PassThru = ExtendToType ( PassThru , WideDataVT , DAG ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getOffset ( ) , Mask , PassThru , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getAddressingMode ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Exract , NewLoad


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; StackAlignment = getPlatformStackAlignment ( ) ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel (


<s> if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode2 ) ) op0 = copy_to_mode_reg ( mode2 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode1 ) ) op2 = copy_to_mode_reg ( mode1 , op2 ) ; pat = GEN_FCN ( icode ) ( op1 , op2 , op0 ) ; if ( pat ) emit_insn ( pat ) ; return


<s> int64_t TgtAddress = MBBInfos [ TgtMBB -> getNumber ( ) ] . Address ; unsigned BalTgtMBBSize = <NUM_LIT> ; int64_t Offset = TgtAddress - ( I . Address + I . Size - BalTgtMBBSize * <NUM_LIT> ) ; int64_t Lo = SignExtend64 < <NUM_LIT> > ( Offset & <NUM_LIT> ) ; int64_t Hi = SignExtend64 < <NUM_LIT> > ( ( ( Offset + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ) ; if ( ABI != <ISA_LIT>Subtarget :: N64 ) { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Hi ) -> setIsInsideBundle ( ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Lo ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) -> setIsInsideBundle ( ) ; } else { int64_t Higher = SignExtend64 < <NUM_LIT> > ( ( ( Offset + <NUM_LIT> )


<s> void <ISA_LIT>GOT :: finalizeScanning ( OutputRelocSection & pRelDyn ) { for ( MultipartListType :: iterator it = m_MultipartList . begin ( ) ; it != m_MultipartList . end ( ) ; ++ it ) { reserveHeader ( ) ; it -> m_pLastLocal = & m_SectionData -> back ( ) ; reserve ( it -> m_LocalNum ) ; it -> m_pLastGlobal = & m_SectionData -> back


<s> int <ISA_LIT>AsmParser :: getATReg ( ) { int AT = Options . getATRegNum ( ) ; if ( AT == <NUM_LIT>


<s> } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor (


<s> if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Basic ; return <NUM_LIT> * TTI :: TCC_Basic ; } return <NUM_LIT> * TTI


<s> unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; bool IsGPRC = RC -> hasSuperClassEq ( & <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addImm ( Imm ) ; else if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , TmpReg ) . addImm ( Hi ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> )

, ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ;


<s> return Opcode ; } CC = <STR_LIT> ( CC , Mode == CmpMode :: Int ) ; if ( unsigned Opcode = getVectorComparison ( CC , Mode ) ) { Invert =


<s> if ( isa < ConstantFPSDNode > ( Src ) && N -> getSimpleValueType ( <NUM_LIT> ) == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) return bitcastConstantFPToInt ( cast < ConstantFPSDNode > ( Src ) , dl , DCI . DAG ) ; return SDValue


<s> return Kind == k_VectorList && VectorList . Count == NumRegs


<s> return ! Subtarget -> useSVEForFixedLengthVectors


<s> return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB


<s> if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) from = to ; if ( from == FLOAT_REGS || from == ALTIVEC_REGS ) return ( rs6000_memory_move_cost ( mode , from , <NUM_LIT> ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , <NUM_LIT> ) ) ; else if ( from == CR_REGS ) return <NUM_LIT> ; else return <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; } else if ( reg_classes_intersect_p ( to , from ) ) return

mode == TFmode ? <NUM_LIT> : <NUM_LIT> ;


<s> return ( __m64 ) __builtin_ia32_psrlq ( ( long long )


<s> if ( generate ) { emit_insn ( gen_rtx_SET ( dest , GEN_INT ( val & <NUM_LIT> ) ) ) ; if ( mode == SImode ) emit_insn ( gen_insv_immsi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; else emit_insn ( gen_insv_immdi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } mask = <NUM_LIT> ; zero_match = ( ( val & mask ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; one_match = ( ( ~ val & mask ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; if ( zero_match != <NUM_LIT> && one_match != <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> , mask <<= <NUM_LIT> ) { val2 = val & ~ mask ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; val2 = val | mask ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; val2 = val2 & ~ mask ; val2 = val2 | ( ( ( val2 >> <NUM_LIT> ) | ( val2 << <NUM_LIT> ) ) & mask ) ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; } if ( i != <NUM_LIT> ) { if ( generate ) { emit_insn ( gen_rtx_SET ( dest , GEN_INT ( val2 ) ) ) ; emit_insn ( gen_insv_immdi ( dest , GEN_INT ( i ) , GEN_INT ( ( val >> i ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } } num_insns = <NUM_LIT> ; mask = <NUM_LIT> ; val2 = one_match > zero_match ? ~ val : val ; i = ( val2 & mask ) != <NUM_LIT> ? <NUM_LIT> : ( val2 & ( mask


<s> <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC , DAG ) ) return getSETCC ( CC , Flags , DL , DAG ) ; return SDValue


<s> return Kind == Immediate && isUInt < <NUM_LIT> > (


<s> unsigned <ISA_LIT>TTI :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) const { return TargetTransformInfo :: getCmpSelInstrCost ( Opcode , ValTy


<s> case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op


<s> const uint8_t * <ISA_LIT>LA25Stub :: getContent


<s> static char buffer [ <NUM_LIT> ] ; aarch64_svprfop prfop = ( aarch64_svprfop ) INTVAL ( prfop_rtx ) ; unsigned int written = snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , mnemonic , svprfop_token ( prfop ) , suffix ) ; gcc_assert ( written < sizeof ( buffer ) ) ; return buffer


<s> static SDValue getVZextMovL ( MVT VT , EVT OpVT , SDValue SrcOp , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget , SDLoc dl ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) { LoadSDNode * LD = NULL ; if ( ! isScalarLoadToVector ( SrcOp . getNode ( ) , & LD ) ) LD = dyn_cast < LoadSDNode > ( SrcOp ) ; if ( ! LD ) { MVT ExtVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ( ExtVT != <STR_LIT> || Subtarget -> is64Bit ( ) ) && SrcOp . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == ExtVT ) { OpVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , OpVT , DAG .

getNode ( <STR_LIT> , dl , OpVT , SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ) ;


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( LO10 ( Offset ) ) ; return ; } BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( HIX22 ( Offset ) ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LOX10 ( Offset ) ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg (


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [


<s> SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; } SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm


<s> static bool ia64_attribute_takes_identifier_p ( const_tree attr_id ) { if ( is_attribute_p ( <STR_LIT> , attr_id ) ) return true ; if ( is_attribute_p ( <STR_LIT> ,


<s> if ( SubregToRegMI ) Imm &= <NUM_LIT> ; unsigned Opcode ; if ( auto R = SplitAndOpc ( Imm , RegSize , Imm0 , Imm1 ) ) Opcode = R . getValue ( ) ; else return false ; MachineFunction * MF = MI . getMF ( ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TII -> get ( Opcode ) , <NUM_LIT> , TRI , * MF ) ; const TargetRegisterClass * ORC = TII -> getRegClass ( TII -> get ( Opcode ) , <NUM_LIT> , TRI , * MF ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewTmpReg = MRI -> createVirtualRegister ( RC ) ; Register NewDstReg = MRI -> createVirtualRegister ( RC ) ; MRI -> constrainRegClass ( SrcReg , RC ) ; MRI -> constrainRegClass ( NewTmpReg , ORC ) ; MRI -> constrainRegClass ( NewDstReg , MRI -> getRegClass ( DstReg ) ) ; BuildInstr ( MI , Opcode , Imm0 ,

Imm1 , SrcReg , NewTmpReg , NewDstReg ) ;


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineRegisterInfo & RegInfo = MF


<s> uint64_t MinOffset = - <NUM_LIT> ; for ( SDNode * N : GN -> uses ( ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; MinOffset = std :: min ( MinOffset , C ->


<s> Value * <ISA_LIT>TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget . isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy (

IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ;


<s> if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; void * Decl = nullptr ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_EnumVal ) ) return ErrorOperand ( Start , <STR_LIT> ) ; else if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) Decl = Info . Var . Decl ; InstInfo -> AsmRewrites -> emplace_back ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ; bool Parse32 = is32BitMode ( ) ||


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: expandSelectCC ( MachineInstr & MI , MachineBasicBlock * BB , unsigned BROpcode ) const { const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , IfFalseMBB ) ; F -> insert ( It , SinkMBB ) ; SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( IfFalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; BuildMI ( ThisMBB , dl , TII . get ( BROpcode ) ) . addMBB ( SinkMBB ) .


<s> if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) PrevAddc = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) PrevAddc = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( PrevAddc == nullptr ) return AddCombineTo64bitMLAL ( AddcNode , DCI , Subtarget ) ; SDValue MLAL = AddCombineTo64bitMLAL ( PrevAddc , DCI , Subtarget ) ; if ( MLAL != SDValue ( PrevAddc , <NUM_LIT> ) ) return AddCombineTo64bitMLAL ( AddcNode , DCI , Subtarget ) ; SDNode * UmlalNode = nullptr ; SDValue AddHi ; if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } auto * Zero = dyn_cast < ConstantSDNode > ( UmlalNode -> getOperand ( <NUM_LIT> ) ) ; if ( ! Zero || Zero -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( AddcNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( ! AddeNode ) return


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [


<s> static <ISA_LIT>Operand * CreateFGRReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S

, SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops


<s> struct machine_function * m = cfun -> machine ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset


<s> if ( extra < <NUM_LIT> ) extra = <NUM_LIT> ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; return offset + <NUM_LIT> <


<s> else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) return compute_movmem_length ( insn ) - <NUM_LIT> ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) return compute_clrmem_length ( insn ) - <NUM_LIT> ; else if ( GET_CODE ( insn ) == JUMP_INSN && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length ==

<NUM_LIT> && ! forward_branch_p ( insn ) ) return <NUM_LIT> ;


<s> RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; return RegNo == <STR_LIT>


<s> modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , lb ) ; append_to_statement_list ( modify , stmts ) ; lhs = build1 ( INDIRECT_REF , pointer_sized_int_node , build2 ( POINTER_PLUS_EXPR , bnd_ptr , var_p , TYPE_SIZE_UNIT ( pointer_sized_int_node ) ) ) ; modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs ,


<s> static inline int getFP32Imm ( const APFloat & FPImm ) { return getFP32Imm ( FPImm .


<s> MCInst TmpInst ; MCInstLowering . Lower ( MI


<s> FunctionPass * llvm :: create<ISA_LIT>CondBrFolding ( ) { return new <ISA_LIT>CondBrFoldingPass


<s> static MCTargetStreamer * createObjectTargetStreamer ( MCStreamer & S ,


<s> MCSymbol * PCSym = Context . createTempSymbol ( ) ; Streamer . emitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create


<s> default : break ; case 'q' : if ( Subtarget -> is64Bit ( ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } case 'Q' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || ! Subtarget -> is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'R' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || ! Subtarget -> is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> && ! isScalarFPTypeInSSEReg ( VT ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && ! isScalarFPTypeInSSEReg ( VT ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : if ( ! Subtarget -> hasMMX ( ) ) break ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'Y' : if ( ! Subtarget -> hasSSE2 ( ) ) break ; case 'x' : if ( ! Subtarget -> hasSSE1 ( ) ) break ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT>


<s> return ( t == TYPE_FMACS ) || ( t ==

TYPE_FMACD ) || ( t == TYPE_NEON_FP_MLA_S ) ;


<s> unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , <NUM_LIT> ) , false ) ) return true ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( TARGET_MACHO && GET_CODE ( addr ) == LO_SUM ) return darwin_rs6000_legitimate_lo_sum_const_p ( XEXP ( addr , <NUM_LIT> )


<s> MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . emitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: createSub ( Res , PC , getContext ( )


<s> else if ( VT == <STR_LIT> ) { std :: string mask = <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask += <STR_LIT> ; SDValue Mask = b . Constant ( mask , <STR_LIT> ) ; MVT DoubleVT = <STR_LIT> ; SDValue Ah = b . AND ( Mask , b . BITCAST ( Op0 , <STR_LIT> ) ) ; SDValue Bh = b . AND ( Mask , b . BITCAST ( Op1 , <STR_LIT> ) ) ; SDValue R = b . DoOp ( DoubleVT , b . AND ( b . BITCAST ( Op0 , <STR_LIT> ) , b . NOT ( Ah ) ) , b .

AND ( b . BITCAST ( Op1 , <STR_LIT> ) , b . NOT ( Bh ) ) ) ;


<s> static unsigned encodeNEONRd ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD >> <NUM_LIT> ) & <NUM_LIT>


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolution >


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N , SDValue & Offset , SDValue


<s> break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : align = <NUM_LIT> ; break ; default : return MCDisassembler ::


<s> x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , popc ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; insn = emit_insn ( x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_jump_insn ( gen_simple_return_indirect_internal ( ecx ) )


<s> } else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16 ( ) ; else TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym ) ; OutStreamer -> EmitLabel (


<s> SDValue IfTrue = N -> getOperand ( <NUM_LIT> ) ; SDValue IfFalse = N -> getOperand ( <NUM_LIT> ) ; SDValue SetCC = DAG . getSetCC ( SDLoc ( N ) , CmpVT . changeVectorElementTypeToInteger ( ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , cast < CondCodeSDNode > ( N0 . getOperand


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != <STR_LIT> ) return RegisterVT ; } if ( VT == <STR_LIT> && Subtarget . hasFP16 ( ) ) return <STR_LIT> ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT


<s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Medium ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return


<s> void addT2SOImmNotOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm (


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> return ( __m512d ) __builtin_ia32_vfnmaddpd512_mask3 ( ( __v8df ) __A , ( __v8df ) __B , (


<s> expand_operand ops [ <NUM_LIT> ] ; machine_mode mode = GET_MODE ( dest ) ; create_output_operand ( & ops [ <NUM_LIT> ] , dest , mode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , pred , GET_MODE ( pred ) ) ; create_input_operand ( & ops [ <NUM_LIT> ] , src , mode ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) , <NUM_LIT> , ops


<s> } <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Base ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( ) ; MBB . erase ( PrevMBBI ) ; return true ; } else if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Base ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( ) ; MBB . erase ( PrevMBBI ) ; return true ; } } if ( MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Base ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Base ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase (


<s> MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; OffsetInBytes += LoadSizeInBytes ; TotalBytesLoaded += LoadSizeInBytes ; Alignment = std :: min ( Alignment , LoadSizeInBytes ) ; } unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , Val ) ) ; return ; } } unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes ; SDValue Src = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , PtrTy , StackPtr , DAG .

getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ;


<s> unsigned MaxCountRemainder = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < ( unsigned ) Form ; j ++ ) if ( ( RemainderOffsetInfo . find ( j ) != RemainderOffsetInfo . end ( ) ) && RemainderOffsetInfo [ j ] . second > RemainderOffsetInfo [ MaxCountRemainder ] . second ) MaxCountRemainder = j ; if ( RemainderOffsetInfo [ MaxCountRemainder ] . second < DispFormPrepMinThreshold ) return false ; if ( MaxCountRemainder == <NUM_LIT> ) return true ; const SCEV * Offset = BucketChain . Elements [ RemainderOffsetInfo [ MaxCountRemainder ] . first ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain . Elements


<s> void <ISA_LIT>ConstantIslands :: doInitialPlacement ( std :: vector < MachineInstr * > & CPEMIs ) { MachineBasicBlock * BB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : <NUM_LIT> ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back (


<s> if ( x == const0_rtx ) x = CONST0_RTX ( mode


<s> return ( __m128d ) __builtin_ia32_cvtsi642sd ( ( __v2df


<s> rtx reg_addend = NULL_RTX ; rtx const_addend = NULL_RTX ; rtx result = NULL_RTX ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == Pmode && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) { rtx x2 = XVECEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , x2 ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_GOTPCREL || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) && ( MEM_P ( orig_x ) || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) ) { x = XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_MODE ( orig_x ) != GET_MODE ( x ) && MEM_P ( orig_x ) ) { x = simplify_gen_subreg ( GET_MODE ( orig_x ) , x , GET_MODE ( x ) , <NUM_LIT> ) ; if ( x == NULL_RTX ) return orig_x ; } return x ; } if ( ix86_cmodel != CM_MEDIUM_PIC && ix86_cmodel != CM_LARGE_PIC ) return ix86_delegitimize_tls_address ( orig_x ) ; } if ( GET_CODE ( x ) != PLUS || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST ) return ix86_delegitimize_tls_address ( orig_x ) ; if ( ix86_pic_register_p ( XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { reg_addend = XEXP ( x , <NUM_LIT> ) ; if ( ix86_pic_register_p ( XEXP ( reg_addend , <NUM_LIT> ) ) ) reg_addend = XEXP ( reg_addend , <NUM_LIT> ) ; else if ( ix86_pic_register_p ( XEXP ( reg_addend , <NUM_LIT> ) ) ) reg_addend = XEXP ( reg_addend , <NUM_LIT> ) ; else { reg_addend = NULL_RTX ; addend = XEXP ( x , <NUM_LIT> ) ; } } else addend = XEXP ( x , <NUM_LIT>


<s> Size = ( Suffix == 'n' ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned II = <NUM_LIT> , IE = Size ; II != IE ; II = II + <NUM_LIT> ) { const unsigned I0 = LittleEndian ? II + <NUM_LIT> : II + <NUM_LIT> ; const unsigned I1 = LittleEndian ? II + <NUM_LIT> : II + <NUM_LIT> ; Buffer [ Size - II - <NUM_LIT> ] = uint8_t ( Inst >> I0 * CHAR_BIT ) ; Buffer [ Size - II - <NUM_LIT> ] = uint8_t ( Inst >> I1 * CHAR_BIT ) ; } break ; default : llvm_unreachable ( <STR_LIT> )


<s> Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT>


<s> getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> )


<s> if ( gt_p ) lab = gen_label_rtx ( ) ; xstormy16_emit_cbranch ( unsigned_p ? LTU : LT , gt_p ? lab : loc ) ; xstormy16_emit_cbranch ( gt_p ? NE : EQ , loc ) ; if ( gt_p ) emit_label ( lab ) ; return ; } else if ( mode == SImode && ( code == NE || code == EQ ) && op1 != const0_rtx ) { rtx lab = NULL_RTX ; int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; if ( code == EQ ) lab = gen_label_rtx ( ) ; for ( i = <NUM_LIT> ; i < num_words - <NUM_LIT> ; i ++ ) { xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( NE , code == EQ ? lab : loc ) ; } xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp


<s> if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; } break ; } return weight


<s> storeRegToStack ( MBB , MBBI , SrcReg , isKill


<s> return true ; } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { if ( matchShuffleWithSHUFPD ( MaskVT , V1 , V2 , PermuteImm , Mask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; return true ; } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( isRepeatedTargetShuffleMask ( <NUM_LIT> , MaskVT , Mask , RepeatedMask ) ) { auto MatchHalf = [ & ] ( unsigned Offset , int & S0 , int & S1 ) { int M0 = RepeatedMask [ Offset ] ; int M1 = RepeatedMask [ Offset + <NUM_LIT> ] ; if ( isUndefInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { return DAG . getUNDEF ( MaskVT ) ; } else if ( isUndefOrZeroInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : <NUM_LIT> ) ; return getZeroVector ( MaskVT , Subtarget , DAG , DL ) ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V1 ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V2 ; } return SDValue ( ) ; } ; int ShufMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Lo = MatchHalf ( <NUM_LIT> , ShufMask [ <NUM_LIT> ] , ShufMask [ <NUM_LIT> ] ) ; SDValue Hi = MatchHalf ( <NUM_LIT> , ShufMask [ <NUM_LIT> ] , ShufMask [ <NUM_LIT> ] ) ; if ( Lo && Hi ) { V1 = Lo ; V2 = Hi ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( ShufMask ) ; return true ; } } } return


<s> assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( getMemDisp (


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( is64Bit ) CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = nullptr ; CommentString = <STR_LIT>


<s> unsigned FrameReg = getFrameRegister ( MF ) ; if ( Subtarget . isTarget64BitILP32 ( ) ) FrameReg = get<ISA_LIT>SubSuperRegister ( FrameReg , <STR_LIT> , false ) ; return FrameReg


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM


<s> UNW_DEC_EPILOGUE ( B3 , t , ecount , arg ) ; } else if ( ( code & <NUM_LIT> ) == <NUM_LIT> ) { label = unw_decode_uleb128 ( & dp ) ; if ( ( code & <NUM_LIT> ) != <NUM_LIT> ) UNW_DEC_COPY_STATE ( B4 , label , arg ) ; else UNW_DEC_LABEL_STATE ( B4 , label , arg ) ; } else switch ( code & <NUM_LIT> ) { case <NUM_LIT> : return unw_decode_x1 ( dp , code ,


<s> if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( VALID_AVX256_REG_OR_OI_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; if ( TARGET_SSE2 && mode == HImode ) return true ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL )