<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON

( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , IsLittleEndian ( LittleEndian ) {


<s> if ( SrcReg == <NUM_LIT> ) return false ; if ( Subtarget -> hasSPE ( ) ) { unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg ) ; return true ; } if ( ! IsSigned && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT ,


<s> switch ( TF ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CloseParen = false ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand ::


<s> bool <ISA_LIT>16RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF )


<s> bool <ISA_LIT>FastISel :: computeAddress ( const Value * Obj , Address & Addr ) { if ( isa < Instruction > ( Obj ) ) return false ; else if ( isa < ConstantExpr > ( Obj ) ) return false ; Addr . setReg ( getRegForValue ( Obj ) ) ; return Addr . getReg ( ) !=


<s> SDLoc dl ( N ) ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RTB = DAG . getNode ( <STR_LIT> , dl , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RTB ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT ==


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } InstructionCost Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; } case <STR_LIT> : if ( LT . second != <STR_LIT> || isWideningInstruction ( Ty , Opcode , Args ) ) return LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LT . first ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return <NUM_LIT>


<s> return ( __m128d ) __builtin_ia32_cvtsi2sd ( ( __v2df ) __A ,


<s> case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case


<s> rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , <NUM_LIT> , & tmpconst , & tmpwidth ) ; if ( retval == - <NUM_LIT> ) return <NUM_LIT> ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return <NUM_LIT>


<s> loongarch_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; loongarch_block_move_straight ( dest , src , bytes_per_iter ) ; loongarch_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; loongarch_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test ,


<s> if ( ! Subtarget -> hasVFP2Base ( ) || ! Subtarget -> hasFP64 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; Register Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; Register Result = createResultReg


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( has<ISA_LIT>64 ( ) ?


<s> else return ( GET_MODE_SIZE ( mode ) +


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> printAddrRegExtendOperand ( MI , OpNum , O ,


<s> if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { if ( ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; if ( ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return std :: max ( BaseT :: getVectorInstrCost ( Opcode ,


<s> if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) )


<s> } if ( Subtarget -> hasDSPR2 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget -> hasMSA ( ) ) { addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; } if ( ! Subtarget -> mipsSEUsesSoftFloat ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( ! Subtarget -> isSingleFloat ( ) ) { if ( Subtarget -> isFP64bit ( ) ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Has<ISA_LIT>64 ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( NoDPLoadStore ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } computeRegisterProperties ( )


<s> } } else if ( VRI . Repl32 != BG . Repl32 ) { return false ; } return VRI . RLAmt == EffRLAmt ; } ; for ( auto & BG : BitGroups ) { if ( ! MatchingBG ( BG ) ) continue ; if ( BG . StartIdx <= BG . EndIdx ) { for ( unsigned i = BG . StartIdx ; i <= BG . EndIdx ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; } else { for ( unsigned i = BG . StartIdx ; i < Bits . size ( ) ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; for ( unsigned i = <NUM_LIT> ; i <= BG . EndIdx ; ++ i ) Mask |= ( UINT64_C ( <NUM_LIT> ) << i ) ; } } bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; bool NeedsRotate = VRI . RLAmt || ( VRI . Repl32 && ! isUInt < <NUM_LIT> > ( Mask ) ) ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( bool ) Res ; if ( Use32BitInsts ) NumAndInsts += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> &&


<s> static int sh_mode_after ( int entity ATTRIBUTE_UNUSED , int mode , rtx_insn * insn ) { if ( TARGET_HITACHI && recog_memoized ( insn ) >= <NUM_LIT> && get_attr_fp_set ( insn )

!= FP_SET_NONE ) return ( int ) get_attr_fp_set ( insn ) ;


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty


<s> assert ( ( isShiftedInt < Width , Shift > ( Value ) ) ) ; return ( ( unsigned ) Value


<s> break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue (


<s> vmovn_high_u32 ( uint16x4_t a , uint32x4_t b ) { uint16x8_t result = vcombine_u16 ( a , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> static SDValue PerformANDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result

= CombineANDShift ( N , DCI , Subtarget ) ) return Result ;


<s> unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT ) , Mask ) ; SAD = DAG . getNode ( <STR_LIT> , DL , SadVT , SAD , Shuffle ) ; } } unsigned ExtractSizeInBits = ExtractVT . getSizeInBits ( ) ; EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtractVT , SadVT . getSizeInBits ( ) / ExtractSizeInBits ) ; SAD = DAG . getBitcast ( ResVT ,


<s> MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr


<s> DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; if ( cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) == <STR_LIT> ) <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8Base ( ) && ! ( isFloatingPointZero ( RHS ) && TrueVal . getValueType ( ) != <STR_LIT> ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel (


<s> return ( aarch64_tune_params . extra_tuning_flags

& AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS ) ;


<s> inline SDValue getI8Imm ( unsigned Imm , const SDLoc & DL ) { return CurDAG -> getTargetConstant ( Imm


<s> if ( ( GET_CODE ( x ) == PRE_MODIFY && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) x = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( x ) && REGNO_OK_FOR_BASE_P ( REGNO ( x ) ) && ( ! strict || REGNO ( x

) < FIRST_PSEUDO_REGISTER ) ) return true ;


<s> SDValue <ISA_LIT>TargetLowering :: withTargetFlags ( SDValue Op , unsigned TF , SelectionDAG & DAG ) const { if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) ,

SDLoc ( GA ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , TF ) ;


<s> if ( ctx != NULL_TREE && ! TRANSLATION_UNIT_WARN_EMPTY_P ( ctx ) ) return ; if ( int_size_in_bytes ( type ) == <NUM_LIT> ) return ; warning ( OPT_Wabi , <STR_LIT> <STR_LIT> ,


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { llvm_unreachable ( <STR_LIT> )


<s> void addImmShiftOperands ( MCInst & Inst ,


<s> for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed =


<s> costs -> vec_flags = aarch64_classify_vector_mode (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ; default : break ; } assert ( ! MI . mayLoad ( ) && <STR_LIT> ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return ; auto & TargetOp = MI . getOperand ( <NUM_LIT> ) ; Register OldTargetReg = TargetOp . getReg


<s> for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return


<s> uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) - <NUM_LIT> ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > (


<s> EVT PtrVT = getPointerTy ( ) ; SDLoc DL ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) ) ; } SDValue Hi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; SDValue Lo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> ,


<s> return ( uint16x8_t ) __builtin_aarch64_subhn2v4si ( ( int16x4_t ) __a , ( int32x4_t ) __b , (


<s> int getAddressOfCalleeRegister ( ) { return


<s> return decodeBDAddr20Operand ( Inst ,


<s> return ++ MachineBasicBlock :: iterator (


<s> void addMRSOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> int getTailCallSPDelta ( ) const { return TailCallSPDelta


<s> unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; } AddOptionalDefs ( MIB


<s> void <ISA_LIT>FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = TRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = RoundUpToAlignment ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout &


<s> return isDomainMVE ( & MI ) || isVectorPredicate ( & MI


<s> rtx addr = plus_constant ( Pmode , XEXP ( mem


<s> if ( State -> getCallingConv ( ) != CallingConv :: Fast ) { unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; const ArrayRef < MCPhysReg > IntArgRegs = Subtarget . getABI ( ) . GetByValArgRegs ( ) ; const MCPhysReg * ShadowRegs = Subtarget . isABI_O32 ( ) ? IntArgRegs . data ( ) : <ISA_LIT>64DPRegs ; assert ( ! ( Align % RegSizeInBytes ) && <STR_LIT> <STR_LIT> ) ; FirstReg = State -> getFirstUnallocated ( IntArgRegs . data ( ) , IntArgRegs . size ( ) ) ; if ( ( Align > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg ] ) ; ++ FirstReg ; } Size = RoundUpToAlignment ( Size , RegSizeInBytes ) ; for ( unsigned I = FirstReg ; Size > <NUM_LIT> && ( I < IntArgRegs . size ( ) ) ; Size -= RegSizeInBytes , ++ I , ++ NumRegs ) State -> AllocateReg ( IntArgRegs


<s> void printf32mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O


<s> unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive


<s> if ( <STR_LIT> . contains ( Src ) ) return std :: make_pair ( ( unsigned ) <STR_LIT> , ( unsigned ) <STR_LIT> ) ; if ( <STR_LIT> . contains ( Src ) ) return std :: make_pair ( ( unsigned )


<s> void <ISA_LIT>MCCodeEmitter :: emitRegModRMByte ( const MCOperand & ModRMReg ,

unsigned RegOpcodeFld , raw_ostream & OS ) const {


<s> if ( cfun -> machine -> no_caller_saved_registers ) { rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = REG_NREGS ( reg ) ; while ( nregs -- > <NUM_LIT> ) if ( ( i + nregs ) == regno ) return false ; } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = <NUM_LIT> ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO


<s> cfun -> machine -> strict_aligned_p =


<s> bool SelectAddrModeIndexed7S128 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeIndexed7S ( N , <NUM_LIT>


<s> if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( MF , SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ; if ( UnsignedFixup ) { SDValue FistOps [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getMemIntrinsicNode ( Opc , DL , DAG . getVTList ( <STR_LIT> ) , FistOps , DstTy , MMO ) ; SDValue Low32 = DAG . getLoad ( <STR_LIT> , DL , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackSlot , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue High32 = DAG . getLoad ( <STR_LIT> , DL , FIST , HighAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; High32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High32 , Adjust ) ; if ( Subtarget -> is64Bit ( ) ) { Low32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low32 ) ; High32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High32 ) ; High32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High32 , Low32 ) ; return std :: make_pair ( Result , SDValue ( ) ) ; } SDValue ResultOps [ ] = {


<s> x = strip_salt ( x ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT>


<s> static bool rs6000_use_blocks_for_constant_p ( machine_mode mode , const_rtx


<s> if ( ! ( Op . first == IC_IMM || Op . first == IC_REGISTER ) )


<s> static DecodeStatus DecodeBranchImmInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; return S


<s> return ( AMSubMode ) ( ( AM5Opc >> <NUM_LIT> )


<s> if ( GV -> isThreadLocal ( ) ) return true ; auto & TM = ST -> getTargetLowering ( ) -> getTargetMachine ( ) ; unsigned OpFlags = ST -> ClassifyGlobalReference ( GV , TM ) ; if ( OpFlags & <STR_LIT> ) return true ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { } ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; if ( OpFlags & <STR_LIT> ) { ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; } MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags


<s> MI -> addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState ::

Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; } return ( Kind == k_Register && Reg . Kind == RK ) && <ISA_LIT>MCRegisterClasses


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ObjSizeScaled = ObjSize / <NUM_LIT> ; SDValue TagSrc = Ptr ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Ptr ) -> getIndex ( ) ; Ptr = DAG . getTargetFrameIndex ( FI , <STR_LIT> ) ; TagSrc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } const unsigned OpCode1 = ZeroData ? <STR_LIT> : <STR_LIT> ; const unsigned OpCode2 = ZeroData ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > OutChains ; unsigned OffsetScaled = <NUM_LIT> ; while ( OffsetScaled < ObjSizeScaled ) { if ( ObjSizeScaled - OffsetScaled >= <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , OffsetScaled


<s> assert ( ! RegInfo -> needsStackRealignment ( MF ) && <STR_LIT> ) ; return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken (


<s> case Others : break ; case CortexA35 : break ; case CortexA53 : PrefFunctionAlignment = <NUM_LIT> ; break ; case CortexA55 : break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead =


<s> if ( mep_general_reg ( x ) ) return NO_REGS ; if ( mep_general_copro_reg ( x ) ) { if ( mep_have_copro_copro_moves_p ) return NO_REGS ; if ( mep_have_core_copro_moves_p ) return GENERAL_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , LOADABLE_CR_REGS ) && constraint_satisfied_p ( x , CONSTRAINT_U )


<s> bool avx_upper_reg_found = false ; note_stores ( insn , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode


<s> __attribute__ ( ( __always_inline__ ) )


<s> void printymmwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI ,


<s> static rtx pa_internal_arg_pointer ( void ) { if ( TARGET_64BIT ) return copy_to_reg ( virtual_incoming_args_rtx ) ; else return


<s> assert ( C && <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType (


<s> for ( unsigned i = <NUM_LIT> , e = RegInfo -> getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RegInfo -> getRegClass ( Reg ) == & <STR_LIT> ) { HasVectorVReg = true ; break ; } } if ( ! HasVectorVReg ) return ; unsigned InVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; unsigned UpdatedVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & EntryBB = * Fn . begin ( ) ; DebugLoc dl ; MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get

( <STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> return __a * __aarch64_vget_lane_any (


<s> void addBarrierOperands ( MCInst & Inst , unsigned N )


( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { abort (


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return


<s> assert ( ( ValueVT != <STR_LIT> || ( ( NumParts == <NUM_LIT> && PartVT == <STR_LIT> ) || ( NumParts == <NUM_LIT> && PartVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; if ( ValueVT == <STR_LIT> && NumParts == <NUM_LIT> ) { Parts [ <NUM_LIT> ] = lowerI128ToGR128 ( DAG , Val ) ; return


<s> unsigned <ISA_LIT>TargetAsmInfo :: SectionFlagsForGlobal ( const GlobalValue * GV , const char * Name ) const { unsigned Flags = ELFTargetAsmInfo :: SectionFlagsForGlobal ( GV , Name ) ; return ( Flags & ( ~ SectionFlags


<s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( <NUM_LIT> ) , Attr ) ) return SDValue ( N , <NUM_LIT> ) ; assert ( ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) && <STR_LIT> ) ; if ( ! Subtarget . hasCMov ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , <STR_LIT> ,


<s> if ( last && recog_memoized ( last ) >= <NUM_LIT> ) return <NUM_LIT> ; for ( ; last != NULL && ! NOTE_INSN_BASIC_BLOCK_P ( last ) && ! stops_p [


<s> static const <ISA_LIT>MCExpr * CreateABS_G3 ( const MCExpr *


<s> bool <ISA_LIT>GOT :: isGOTFull ( ) const { uint64_t gotCount = <ISA_LIT>GOT0Num + m_MultipartList . back ( ) . m_LocalNum + m_MultipartList . back ( ) . m_GlobalNum ; gotCount += <NUM_LIT>


<s> static bool sh_return_in_memory ( const_tree type , const_tree fndecl ) { if ( TARGET_SH5 ) { if ( TYPE_MODE ( type ) == BLKmode ) return ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) ) > <NUM_LIT> ; else return GET_MODE_SIZE ( TYPE_MODE (


<s> assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = CountTrailingOnes_32 ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return NULL ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT>


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; unsigned Size = VT . getSizeInBits ( ) ; APInt MinAmnt ; if ( VT . isVector ( ) && N1 . getOpcode ( ) == <STR_LIT> && SupportedVectorVarShift ( VT . getSimpleVT ( ) , Subtarget , <STR_LIT> ) && <STR_LIT> ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) , MinAmnt ) && MinAmnt == VT . getScalarSizeInBits ( ) - <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N1 . getOperand ( <NUM_LIT> ) ) ; } if ( SDValue V = combineShiftToPMULH ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) ->


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F )


<s> void addHWRegsAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned temp = Reg1 ; Reg1 = Reg2 ; Reg2 = temp ; } EmitInstrRegReg ( MovOpc , Reg1 ,


<s> return N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( )

== <STR_LIT> || isExtendedBUILD_VECTOR ( N , DAG , false ) ;


<s> MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( AddrReg ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addReg ( DesiredLoReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addReg ( DesiredHiReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( StatusReg , RegState :: Kill ) . addUse ( StatusReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addUse ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( DoneBB ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( NewLoReg ) . addReg ( NewHiReg ) . addReg ( AddrReg ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( LoadCmpBB ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * DoneBB ) ; computeAndAddLiveIns ( LiveRegs , * StoreBB ) ; computeAndAddLiveIns ( LiveRegs , *


<s> if ( argtype == error_mark_node || VOID_TYPE_P ( argtype ) ) break ; if ( TYPE_EMPTY_P ( argtype ) ) seen_empty_type = true ; else if ( seen_empty_type ) { cum -> warn_empty =


<s> unsigned getRedZoneSize ( ) const { return isDarwinABI ( ) ? <NUM_LIT> : ( is<ISA_LIT>64


<s> ExTab = NULL ; FnStart = NULL ; Personality = NULL


<s> MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = ShAmt == <NUM_LIT> ? <NUM_LIT> : RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = ShAmt == <NUM_LIT> ? <NUM_LIT> : RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( III . ZeroIsSpecialNew ) { Register RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( Register :: isVirtualRegister ( RegToModify ) ) { const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify , NewRC ) ; } } } if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill ( DefMI , MI ,


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal , <STR_LIT>


<s> if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( d -> vmode ) ; t1 = gen_reg_rtx ( d -> vmode ) ; switch ( d -> vmode ) { case V4HImode : emit_insn ( gen_loongson_punpckhhw ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklhw ( t1 , d -> op0 , d -> op1 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target


<s> uint32_t encodeStackAdjustment ( uint32_t StackSize ) const { return ( StackSize / <NUM_LIT> )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) return false ; bool IsEVEX_V128 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) ; bool IsEVEX_V256 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ( Desc . TSFlags & <STR_LIT> ) ) ; unsigned NewOpc = <NUM_LIT> ; if ( IsEVEX_V256 ) { auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode


<s> static void aarch64_emit_sve_invert_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( pred ) ; rtx tmp = gen_reg_rtx


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int

FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override {


<s> if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == XER_REGNO ) return <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ; if ( regno == VSCR_REGNO ) return <NUM_LIT> ; if ( regno == SPE_ACC_REGNO ) return <NUM_LIT> ; if ( regno == SPEFSCR_REGNO


<s> static bool MayFoldVectorLoad ( SDValue V ) { if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> && V . getNumOperands ( ) == <NUM_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( V ) ) return true ; return


<s> thumb1_const_print t ( asm_out_file , REGNO ( dst )


<s> return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( false ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return false


<s> if ( Subtarget . isThumb2 ( ) ) { unsigned Bit24 = EncodedValue & <NUM_LIT> ; unsigned Bit28 = Bit24 <<


<s> if ( UI . getUse ( ) . getResNo ( ) != Flags . getResNo ( ) ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> || cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; <STR_LIT> CC = getCondFromNode ( * FlagUI ) ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : continue ; default : return false


<s> const char * <ISA_LIT>DarwinTargetAsmInfo :: getEHGlobalPrefix ( ) const { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> getDarwinVers ( ) > <NUM_LIT>


<s> return ( uint16x8_t ) __builtin_neon_vcaltv8hf


<s> if ( Imm == <NUM_LIT> ) return ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> ; switch ( Imm ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; } O << markup (


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getOrdering ( ) ) ) return SDValue ( ) ; return Op


<s> bool hasAVXVNNI ( ) const { return HasAVXVNNI


<s> bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && I -> getNumOperands ( ) > <NUM_LIT> && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I


<s> <STR_LIT> ST = getShiftExtendType ( ) ; if ( ST != <STR_LIT> ) return false ; uint64_t Val = getShiftExtendAmount


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int Off = Offset ; unsigned i = <NUM_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done


<s> if ( V . getValueSizeInBits ( ) == <NUM_LIT> ) return V ; assert ( V . getValueSizeInBits ( ) == <NUM_LIT> ) ; SDValue SubRegIdx = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , V , SubRegIdx ) , <NUM_LIT> ) ; return


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> )


<s> return Optional < <STR_LIT> > ( ) ; case CmpInst :: FCMP_OEQ : case CmpInst :: ICMP_EQ : return <STR_LIT> ; case CmpInst :: FCMP_OGT : case CmpInst :: ICMP_UGT : case CmpInst :: ICMP_SGT : return <STR_LIT> ; case CmpInst :: FCMP_OGE : case CmpInst :: ICMP_UGE : case CmpInst :: ICMP_SGE : return <STR_LIT> ; case CmpInst :: FCMP_OLT


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_VectorListIndexed ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . LaneIndex = Index ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc


<s> inline bool isImmZExtu32u8Value ( uint64_t


<s> static inline uint8_t encodeAdvSIMDModImmType5 (


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( )


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel , true ) ) ; } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! GuaranteedTailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = <NUM_LIT> ; i != Ins . size ( ) ; i ++ ) { <STR_LIT> Flags = Ins [ i ]


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; Ret +=


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isMem ( BDLMem ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Mem . Base ) ) ; addExpr ( Inst , Mem . Disp )


<s> bool Is64BitTarget ( ) { return Is64Bit


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT>


<s> switch ( Opc ) { default : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return Opc


<s> O << <STR_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) O . write_hex ( ( Value &


<s> assert ( isRegNumber ( ) && <STR_LIT>


<s> if ( MEM_P ( SET_SRC ( body ) ) ) return <NUM_LIT> ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( pattern_is_rotate64 ( body ) && MEM_P ( XEXP ( SET_SRC (


<s> } if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; int FrameIndex = MFI -> CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd ; ++ Reg , ++ i ) { unsigned VReg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back (


<s> unsigned FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ; return


) __iocsrwr_b ( unsigned char _1 , unsigned int _2 ) {


<s> case <STR_LIT> : case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGE21 ) ; return true ; } return true ; case <STR_LIT> : case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; RelocType = unsigned ( MachO ::


<s> unsigned Opcode = Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( Opcode != Op -> getOperand ( i ) . getOpcode ( ) ) return SDValue ( ) ; switch ( Opcode ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode , VT )


<s> Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , dl , OpVT ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , dl , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> ,


<s> if ( ExtIdx % IndexDivisor != <NUM_LIT> ) return SDValue ( ) ; ExtIdx /= IndexDivisor ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NarrowingFactor = WideVT . getSizeInBits ( ) / VT . getSizeInBits ( ) ; unsigned NarrowElts = SelElts / NarrowingFactor ; MVT NarrowSelVT = <STR_LIT> ( SelVT . getVectorElementType ( ) , NarrowElts ) ; SDLoc DL ( Ext ) ; SDValue ExtCond = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue ExtT = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue ExtF = extract128BitVector ( Sel . getOperand ( <NUM_LIT> ) , ExtIdx , DAG , DL ) ; SDValue NarrowSel = DAG . getSelect ( DL , NarrowSelVT , ExtCond , ExtT , ExtF ) ; return DAG . getBitcast ( VT , NarrowSel


<s> getBranchTargetOpValueLsl2MMR6 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * FixupExpression = MCBinaryExpr :: createAdd ( MO . getExpr ( ) , MCConstantExpr :: create ( - <NUM_LIT> , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , FixupExpression , MCFixupKind ( <STR_LIT> ) ) ) ; return


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn ) ) ) ; return MCDisassembler ::


<s> MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = getRegTy ( SrcReg , MF ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( MVT ( getRegTy ( SrcReg , MF ) ) . isFatPointer ( ) ) DstReg


<s> int * reg = & pcum -> reg ; machine_mode mode = arg . mode ; int param_size = csky_num_arg_regs ( mode , arg . type


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode


<s> for ( IntrinsicInst * ConvertToUse : ConvertToUses ) { for ( User * User : ConvertToUse -> users ( ) ) { auto * IntrUser = dyn_cast < IntrinsicInst > ( User ) ; if ( IntrUser && IntrUser -> getIntrinsicID ( ) == <STR_LIT> ) { const auto * IntrUserVTy = cast < ScalableVectorType > ( IntrUser -> getType ( ) ) ; if ( IntrUserVTy -> getElementCount ( ) . getKnownMinValue ( ) > PTrueVTy -> getElementCount ( ) .


<s> SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT>


<s> std :: string TT = M . getTargetTriple ( ) ; if ( TT . size ( ) >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'x' && TT [ <NUM_LIT> ] == '8' && TT [ <NUM_LIT> ] == '6' && TT [ <NUM_LIT> ] == '_' && TT [ <NUM_LIT> ] == '6' && TT [ <NUM_LIT> ] == '4' && TT [ <NUM_LIT> ] == '-' ) return <NUM_LIT> ; if ( TT . size ( ) >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'a' && TT [ <NUM_LIT> ] == 'm' && TT [ <NUM_LIT> ] == 'd' && TT [ <NUM_LIT> ] == '6' && TT [ <NUM_LIT> ] == '4' && TT [ <NUM_LIT> ] == '-' ) return <NUM_LIT> ; if ( ! TT . empty ( ) )


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> rtx fun = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; cfun -> machine -> set_mcount_arg_insn = emit_move_insn ( a1 , ra ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , a1 ,


<s> return ( VT . getVectorNumElements ( ) == <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3orAVX ( ) ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2

( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ;


<s> return sparc_function_arg_1 ( cum , arg , false


<s> return ( __m512i ) __builtin_ia32_pandnq512_mask ( ( __v8di ) __A , ( __v8di ) __B , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 )


<s> } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresDifferentSrcAndDst : return Error ( IDLoc , <STR_LIT> ) ; case Match_Immz : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm1_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm3_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ; int Adj = DefAdj +


<s> else gcc_unreachable ( ) ; emit_insn_after ( gen_move_insn ( XEXP ( set_rtx , <NUM_LIT> ) , gen_lowpart ( GET_MODE ( set_src ) , r ) ) , i0 ) ; set_insn_deleted ( insn ) ; return r ; } else { rtx extension_dst = XEXP ( set_rtx , <NUM_LIT> ) ; if ( GET_MODE ( extension_dst ) != SImode ) extension_dst = simplify_gen_subreg ( SImode , extension_dst , GET_MODE ( extension_dst ) , <NUM_LIT> ) ; if ( modified_between_p ( extension_dst , insn , use_at_insn ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , REGNO ( extension_dst ) , INSN_UID ( insn ) ) ; rtx r = gen_reg_rtx ( SImode ) ; emit_insn_after ( gen_move_insn ( r , extension_dst ) , insn


<s> int Size = Ty . isSized ( ) ? Ty . getSizeInBits ( ) : <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MI . getNumOperands ( ) ; ++ Idx ) Mapping . setOperandMapping (


<s> unsigned RegOp = IsStore ? <NUM_LIT> : <NUM_LIT> ; unsigned AddrOp = AddrBase + <NUM_LIT> ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( RegOp ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isImm ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && ( Inst . getOperand ( AddrOp ) . isExpr ( ) || Inst . getOperand ( AddrOp ) . isImm ( ) ) && <STR_LIT> ) ; unsigned Reg = Inst . getOperand ( RegOp ) . getReg ( ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) return ; bool Absolute = true ; if ( Inst . getOperand ( AddrOp ) .


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) { MVT GRLenVT = Subtarget . getGRLenVT ( ) ; addRegisterClass ( GRLenVT , & <STR_LIT> ) ; computeRegisterProperties ( STI . getRegisterInfo


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg )

. addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT>


<s> if ( DAG . SignBitIsZero ( N0 ) ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , N0 ) ; MVT SrcVT = N0 . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { if ( Op . getValueType ( ) != <STR_LIT> || ! <ISA_LIT>ScalarSSEf64 ) return SDValue ( ) ; return LowerUINT_TO_FP_i64 ( Op , DAG ) ; } else if ( SrcVT ==


<s> bool is<ISA_LIT>SOImm ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value )


<s> if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction (


<s> if ( I ) { Opcode = I -> getOpcode ( ) ; U = I ; InMBB = I -> getParent ( ) == FuncInfo . MBB -> getBasicBlock ( ) ; } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else { AM . GVOpFlags = Subtarget -> classifyLocalReference ( nullptr ) ; } return true


<s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT>


<s> int no_ready = number_in_ready ( ) ; fprintf ( stdout , <STR_LIT> , no_ready


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & Ops [ <NUM_LIT> ] ,

Ops . size ( ) , false , SDLoc ( Op ) ) . first ;


<s> return __builtin_mve_vmovlbq_sv16qi (


<s> break ; } switch ( code ) { case GE : break ; case LE : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case ORDERED : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_ABS ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case EQ : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , gen_rtx_ABS ( compare_mode , op0 ) ) ) ) ; op0 = temp ; break ; case UNGE : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; false_cond = true_cond ; true_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case GT : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; true_cond = false_cond ; false_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; return


<s> void addLiveInAttr ( Register VReg , <STR_LIT> Flags


<s> zero_or_two31 = operands [ <NUM_LIT> ] ; input = operands [ <NUM_LIT> ] ; two31 = operands [ <NUM_LIT> ] ; vecmode = GET_MODE ( large ) ; value = gen_rtx_REG ( vecmode , REGNO ( operands [ <NUM_LIT> ] ) ) ; if ( MEM_P ( input ) ) { if ( vecmode == V4SFmode ) emit_insn ( gen_vec_setv4sf_0 ( value , CONST0_RTX ( V4SFmode ) , input ) ) ; else emit_insn ( gen_sse2_loadlpd ( value , CONST0_RTX ( V2DFmode ) , input ) ) ; } else { input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss ( value , value


_mm256_loadu_epi32 ( void const * __P ) {


<s> GPR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; AFGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; MSA128BRegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; COP2RegClass = & ( TRI -> getRegClass ( <STR_LIT> )


<s> for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry


<s> isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , ReturnRegsCount ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> )

, GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , NumAlignedDPRCS2Regs ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> SDValue Cond = DAG . getNode ( <STR_LIT> , DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( )

, Ty ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static int classify_argument ( machine_mode mode , const_tree type , enum x86_64_reg_class classes [ MAX_CLASSES ] , int bit_offset ) { int zero_width_bitfields = <NUM_LIT> ; static bool warned = false ; int n = classify_argument ( mode , type , classes , bit_offset , zero_width_bitfields ) ; if ( ! zero_width_bitfields || warned || !


<s> default : llvm_unreachable ( <STR_LIT> ) ; return ; case <STR_LIT> : Results . push_back ( ExpandBIT_CONVERT ( N , DAG ) ) ; return ; case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeBranchTarget21MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { return true


<s> else if ( ( mode == V4SImode ) || ( mode == V4SFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V2DImode ) || ( mode == V2DFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else { gcc_unreachable ( ) ; } if ( ! REG_P ( XEXP ( new_mem , <NUM_LIT> ) ) ) { rtx base_reg = force_reg ( Pmode , XEXP ( new_mem , <NUM_LIT> ) ) ; XEXP ( new_mem , <NUM_LIT> ) = base_reg ; rtx_insn * force_insn = get_last_insn ( ) ; remove_insn ( force_insn ) ; rtx_insn * before_load_insn = PREV_INSN ( load_insn ) ; add_insn_after ( force_insn , before_load_insn , BLOCK_FOR_INSN ( load_insn ) ) ; df_insn_rescan ( before_load_insn


<s> SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( ! SelectAddr ( Node , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return NULL ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand


<s> static SDValue LowerScalarVariableShift ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned <ISA_LIT>OpcV = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , Subtarget , DAG ) ; } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue


<s> unsigned Opcode = FirstMI -> getOpcode ( ) ; bool isNotVFP = isi32Load ( Opcode ) || isi32Store ( Opcode ) ; unsigned Size = getLSMultipleTransferSize ( FirstMI ) ; unsigned SIndex = <NUM_LIT> ; unsigned EIndex = MemOps . size ( ) ; do { const MachineInstr * MI = MemOps [ SIndex ] . MI ; int Offset = MemOps [ SIndex ] . Offset ; const MachineOperand & PMO = getLoadStoreRegOp ( * MI ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( PReg ) ; unsigned Latest = SIndex ; unsigned Earliest = SIndex ; unsigned Count = <NUM_LIT> ; bool CanMergeToLSDouble = STI -> isThumb2 ( ) && isNotVFP && isValidLSDoubleOffset ( Offset ) ; if ( STI -> isCortexM3 ( ) && isi32Load ( Opcode ) && PReg == getLoadStoreBaseOp ( * MI ) . getReg ( ) ) CanMergeToLSDouble = false ; bool CanMergeToLSMulti = true ; if ( STI -> isSwift ( ) && ! isNotVFP && ( PRegNum % <NUM_LIT> ) == <NUM_LIT> ) CanMergeToLSMulti = false ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) CanMergeToLSMulti = CanMergeToLSDouble = false ; for ( unsigned I = SIndex + <NUM_LIT> ; I < EIndex ; ++ I , ++ Count ) { int NewOffset = MemOps [ I ] . Offset ; if ( NewOffset != Offset + ( int ) Size ) break ; const MachineOperand & MO = getLoadStoreRegOp ( * MemOps [ I ] . MI ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) break ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; bool PartOfLSMulti = CanMergeToLSMulti ; if ( PartOfLSMulti ) { if ( RegNum <= PRegNum ) PartOfLSMulti = false ; else if ( ! isNotVFP && RegNum != PRegNum + <NUM_LIT> ) PartOfLSMulti = false ; } bool PartOfLSDouble = CanMergeToLSDouble && Count <= <NUM_LIT> ; if ( ! PartOfLSMulti && ! PartOfLSDouble ) break ; CanMergeToLSMulti &= PartOfLSMulti ; CanMergeToLSDouble &= PartOfLSDouble ; unsigned Position = MemOps [ I ] .


<s> long int <ISA_LIT>ELFWriterInfo :: getDefaultAddendForRelTy ( unsigned RelTy , long int Modifier ) const { llvm_unreachable ( <STR_LIT> <STR_LIT>


<s> <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters (


<s> if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( * MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) { int SecondScratchReg = BV . find_next ( * SR1 ) ; if ( SecondScratchReg != - <NUM_LIT> ) * SR2


<s> static DecodeStatus DecodeVecShiftR32Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm ,


<s> sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; sigemptyset ( & sact . sa_mask ) ; sact . sa_flags = SA_ONSTACK | SA_SIGINFO ; sact . sa_sigaction =


<s> case <STR_LIT> : if ( ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { if ( Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg , true , false , false , isDead ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } break ; case <STR_LIT> : case <STR_LIT> : if ( ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { const TargetRegisterClass * RC = RI . getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned StoreOpc , LoadOpc ; if ( RC == <STR_LIT> ) { LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } else assert ( <NUM_LIT> && <STR_LIT> ) ; if ( Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( StoreOpc ) ) . addReg ( SrcReg , false , false , isKill ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( LoadOpc ) ) . addReg ( DstReg , true , false , false , isDead ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } break ; } return NewMI


<s> static void arm_set_current_function ( tree fndecl ) { if ( ! fndecl || fndecl == arm_previous_fndecl ) return ; tree old_tree = ( arm_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( arm_previous_fndecl ) : NULL_TREE ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! new_tree && old_tree ) new_tree = target_option_default_node ; if ( old_tree == new_tree ) return ; arm_previous_fndecl = fndecl ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; save_restore_target_globals ( new_tree ) ; arm_override_options_after_change_1 ( & global_options , & global_options_set


<s> static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) && <STR_LIT> ) ; Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; Cond . push_back ( LastInst . getOperand (


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc DL = Op . getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; case CodeModel :: Large


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> return ( __m512d ) __builtin_ia32_movddup512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8


<s> PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; assert ( CCMask > <NUM_LIT> && CCMask < <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = MI -> getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( )


<s> } RTLIB :: Libcall LC ; if ( IsSigned ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model


<s> HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; DeprecatedMFTB = false


<s> assert ( ( Kind == k_Memory ) && <STR_LIT> ) ; return Mem .


<s> return ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( ) ; } MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , false , false , isKill ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst ; bool Res = compressInst ( CInst , Inst ,

* Subtarget , OutStreamer -> getContext ( ) ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getValueType ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , GetGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT ( ) , false ,


<s> bool nds32_can_use_bclr_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == <NUM_LIT>


<s> } case G_STORE : case G_LOAD : { const unsigned DestReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DestRegBank = RBI . getRegBank ( DestReg , MRI , TRI ) -> getID ( ) ; const unsigned OpSize = MRI . getType ( DestReg ) . getSizeInBits ( ) ; if ( DestRegBank != <STR_LIT> || OpSize != <NUM_LIT> ) return false ; const unsigned NewOpc = I . getOpcode ( ) == G_STORE ? <STR_LIT> : <STR_LIT> ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( * I . memoperands_begin ( ) ) ; break ; } case G_CONSTANT : { int Imm = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getValue ( ) . getLimitedValue ( ) ; unsigned LUiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LUi , * ORi ; LUi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( LUiReg ) . addImm ( Imm >> <NUM_LIT> ) ; ORi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg (

) ) . addUse ( LUiReg ) . addImm ( Imm & <NUM_LIT> ) ;


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( MBB , MBBI , TII ,


<s> if ( ! ATReg ) return ; unsigned LoOffset = Offset & <NUM_LIT> ; unsigned HiOffset = ( Offset & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset ++ ; emitRI ( <STR_LIT> , ATReg , HiOffset , IDLoc , STI ) ; if ( BaseReg != <STR_LIT> ) emitRRR ( <STR_LIT> , ATReg , ATReg ,


<s> auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return nullptr ; } else if ( hasMFENCE ( * Subtarget ) ) { Function * MFence = llvm :: <STR_LIT> ( M ,


<s> static SDValue LowerToHorizontalOp ( const BuildVectorSDNode * BV , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { unsigned NumNonUndefs = count_if ( BV -> op_values ( ) , [ ] ( SDValue V ) { return ! V . isUndef ( ) ; } ) ; if ( NumNonUndefs < <NUM_LIT> ) return SDValue ( ) ; MVT VT = BV -> getSimpleValueType ( <NUM_LIT> ) ; if ( ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE3 ( ) ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX ( ) ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX2 ( ) ) ) { unsigned HOpcode ; SDValue V0 , V1 ; if ( isHopBuildVector ( BV , DAG , HOpcode , V0 , V1 ) ) return getHopForBuildVector ( BV , DAG , HOpcode , V0 , V1 ) ; } if ( ! Subtarget . hasAVX ( ) || ! VT . is256BitVector ( ) ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned Half = NumElts / <NUM_LIT> ; unsigned NumUndefsLO = <NUM_LIT> ; unsigned NumUndefsHI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Half ; i != e ; ++ i ) if ( BV -> getOperand ( i ) -> isUndef ( ) ) NumUndefsLO ++ ; for ( unsigned i = Half , e = NumElts ; i != e ; ++ i ) if ( BV -> getOperand ( i ) -> isUndef ( ) ) NumUndefsHI ++ ; SDLoc DL (


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc


<s> } ) != To -> getParent ( ) -> rend ( ) ) ; for ( -- To ; To != From ; -- To ) { const MachineInstr & Instr = * To ; if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck & AK_Read ) && Instr . readsRegister ( <STR_LIT>


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) { if ( Is64Bit ) return


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo (


<s> static SDValue RewriteAsNarrowerShuffle ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , DebugLoc dl ) { EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned NewWidth = ( NumElems == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT NewVT ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; } int Scale = NumElems /