<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int size = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int fbits = size - ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , decodeVFPRd ( insn , SP ) ) ) ) ; assert ( TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; assert ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( fbits ) ) ; NumOpsAdded = <NUM_LIT> ; } else { unsigned d , m ; if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { d = decodeVFPRd ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B ,


<s> addr2 = XEXP ( mem2 , <NUM_LIT> ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr1 , <NUM_LIT> ) ) ) return <NUM_LIT> ; else { reg1 = REGNO ( XEXP ( addr1 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( addr1 , <NUM_LIT> ) ) ) return <NUM_LIT> ; offset1 = INTVAL ( XEXP ( addr1 , <NUM_LIT> ) ) ; } } else if ( ! REG_P ( addr1 ) ) return <NUM_LIT> ; else { reg1 = REGNO ( addr1 ) ; offset1 = <NUM_LIT> ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr2 , <NUM_LIT> ) ) ) return <NUM_LIT> ; else { reg2 = REGNO ( XEXP ( addr2 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( addr2 , <NUM_LIT> ) ) ) return <NUM_LIT> ; offset2 = INTVAL ( XEXP ( addr2 , <NUM_LIT> ) ) ; } } else if ( ! REG_P ( addr2 ) ) return <NUM_LIT> ; else { reg2 = REGNO ( addr2 ) ; offset2 =


( ( Opcode >> ( <NUM_LIT> * I ) ) & <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> <<


<s> } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> ) { RHSC /= Scale ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } } Base = N . getOperand


<s> state_reset ( curr_state ) ; targetm . sched . init ( <NUM_LIT> , false , <NUM_LIT> ) ; advance_state ( curr_state )


<s> if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr


<s> int64_t Value = ConstExpr -> getValue ( ) ; return ( Value % <NUM_LIT> == <NUM_LIT> ) && ( Value >= <NUM_LIT> ) && ( Value <= <NUM_LIT> ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Op . getImm ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Op . getImm ( ) ) ) { const <ISA_LIT>MCExpr * LHSSymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS (


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Token , Parser ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> void <ISA_LIT>InstrInfo :: decomposeStackOffsetForDwarfOffsets ( const StackOffset & Offset , int64_t & ByteSized , int64_t & VGSized ) { assert ( Offset . getScalable ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; ByteSized = Offset . getFixed ( ) ; VGSized = Offset . getScalable (


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return ; <ISA_LIT>FunctionInfo * PFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; PFI -> setIsSplitCSR (


<s> O << TAI -> getLCOMMDirective ( ) << name << ',' << Size << ',' << Align ; } else if ( ! GVar -> hasCommonLinkage ( ) ) { O << <STR_LIT> << name << '\n' << TAI -> getWeakDefDirective ( ) << name << '\n' ; EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; } O << '\n' ; EmitGlobalConstant ( C ) ; return ; } else { O << <STR_LIT> << name << ',' << Size ; if ( Subtarget . isDarwin9 ( ) ) O << ',' << Align ; } if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; O << <STR_LIT> ; } O << '\n' ; return ; } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: CommonLinkage : O << <STR_LIT> << name << '\n' << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue ::


<s> Op -> Expr . CRVal = EvaluateCRExpr ( Val ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 = Is<ISA_LIT>64 ; return


<s> uint32_t Mask = ( ( <NUM_LIT> << ( From - To + <NUM_LIT> ) ) - <NUM_LIT> ) ; Bits &= ~ ( Mask << To ) ; Bits |= ( Val &


<s> void <ISA_LIT>AsmParser :: getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne (


<s> inline int vec_any_nge ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgefp_p ( __CR6_LT_REV , a1 , a2


<s> unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT>


<s> static DecodeStatus DecodeVST1LN ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT>


<s> ModulePass * llvm :: create<ISA_LIT>16HardFloat ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>16HardFloat (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemSrcValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Bits


<s> BBI . Size = <NUM_LIT> ; for ( const MachineInstr & MI : * MBB ) BBI

. Size += TII -> GetInstSizeInBytes ( MI ) ;


<s> return ( ( REG_P ( recog_data . operand [ <NUM_LIT> ] ) && REGNO ( recog_data . operand [ <NUM_LIT> ] ) == reg ) || ( recog_data . n_operands == <NUM_LIT> && REG_P ( recog_data . operand [ <NUM_LIT> ] )

&& REGNO ( recog_data . operand [ <NUM_LIT> ] ) == reg ) ) ;


<s> bool isSVEVectorIndexB ( ) const { return Kind == k_VectorIndex &&


<s> return ( __m512i ) __builtin_ia32_punpcklqdq512_mask ( ( __v8di ) __A , ( __v8di ) __B , ( __v8di ) _mm512_setzero_si512 ( ) , (


<s> static SExpr * t_addrmode_rr_customALF ( const MachineInstr & MI , ALFStatementGroup & alfbb , ALFContext * ctx , string label ) { const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string Reg = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string RegOff = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * offset = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , RegOff ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * bytes_to_bits = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , Reg ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * add = ctx -> add ( <NUM_LIT> , bytes_to_bits , offset , <NUM_LIT> ) ; return ctx -> list ( <STR_LIT> ) -> append ( <NUM_LIT> ) -> append

( ctx -> fref ( <STR_LIT> ) ) -> append ( add ) ;


<s> vpmaxnmq_f64 ( float64x2_t a , float64x2_t b ) { return __builtin_aarch64_smaxpv2df ( a ,


<s> void emitTCEntry ( const MCSymbol & S ) override { Streamer . EmitSymbolValue ( & S


<s> return isSingleSpacedVectorList ( ) && VectorList . Count == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> static SDValue extract256BitVector ( SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , SDLoc


<s> SDValue Value = SN -> getValue ( ) ; if ( Value . getValueType ( ) == <STR_LIT> || Value . getValueType ( ) == <STR_LIT> ) { EVT MemVT = SN -> getMemoryVT ( ) ; unsigned Alignment = SN -> getAlignment ( ) ; if ( Alignment >= MemVT . getStoreSize ( ) ) return Op ; EVT ScalarVT = Value . getValueType ( ) . getScalarType ( ) , ScalarMemVT = MemVT . getScalarType ( ) ; unsigned Stride = ScalarMemVT . getStoreSize ( ) ; SDValue Stores [ <NUM_LIT> ] ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { SDValue Ex = DAG . getNode ( <STR_LIT> , dl , ScalarVT , Value , DAG . getConstant ( Idx , dl , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Store ; if ( ScalarVT != ScalarMemVT ) Store = DAG . getTruncStore ( StoreChain , dl , Ex , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , ScalarMemVT , MinAlign ( Alignment , Idx * Stride ) , SN -> getMemOperand ( ) -> getFlags ( ) , SN -> getAAInfo ( ) ) ; else Store = DAG . getStore ( StoreChain , dl , Ex , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , MinAlign ( Alignment , Idx * Stride ) , SN -> getMemOperand ( ) -> getFlags ( ) , SN -> getAAInfo ( ) ) ; if ( Idx == <NUM_LIT> && SN -> isIndexed ( ) ) { assert ( SN -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; Store = DAG . getIndexedStore ( Store , dl , BasePtr , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( Stride , dl , BasePtr . getValueType ( ) ) ) ; Stores [ Idx ]


<s> vec_uint4 nan_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uchar16 hihi_promote = ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 biteq ; vec_uint4 aabs ; vec_uint4 babs ; vec_uint4 a_gt ; vec_uint4 ahi_inf ; vec_uint4 anan ; vec_uint4 result ; union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; aabs = vec_and ( ( vec_uint4 ) a , sign_mask ) ; babs = vec_and ( ( vec_uint4 ) b , sign_mask ) ; biteq = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) aabs , ( vec_uint4 ) babs ) ; biteq = vec_and ( biteq , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) biteq , x . v ) ) ; a_gt = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; ahi_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; anan = ( vec_uint4 ) vec_or ( a_gt , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_gt , x . v ) , ahi_inf ) ) ; result = vec_andc ( biteq , anan ) ; return ( ( qword ) ( vec_perm ( ( vec_uchar16 )

result , ( vec_uchar16 ) result , hihi_promote ) ) ) ;


<s> ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregoiv2di_pss ( __o , <NUM_LIT> ) ; return


<s> char * aof_data_section ( ) { static char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> , arm_data_section_count ++ ) ; return buf


<s> } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } SDLoc DL ( N ) ; SDValue NewMul ; if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ; } else if ( ! Subtarget . slowLEA ( ) ) NewMul = combineMulSpecial ( MulAmt , N , DAG , VT , DL ) ; if ( ! NewMul ) { assert ( MulAmt != <NUM_LIT> && MulAmt != ( VT == <STR_LIT> ?


<s> void <ISA_LIT>MCExpr :: AddValueSymbols ( MCAssembler * Asm ) const { AddValueSymbolsImpl ( getSubExpr ( ) , Asm


<s> return new <ISA_LIT>TargetELFStreamer ( S


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB , AddrReg ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , DL . getPointerSize ( ) , Align ) ; MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return ResultReg ; } addConstantPoolReference ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , CPI , PICBase , OpFlag ) ; return


<s> MachineInstr * PHIInput = MRI -> getVRegDef ( RegOp ) ; unsigned Opcode = PHIInput -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { assert ( MRI -> getRegClass ( PHIInput -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == & <STR_LIT> && <STR_LIT> ) ; PHIOps . push_back ( { PHIInput -> getOperand ( <NUM_LIT> ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { Register AccReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * PHIInput -> getParent ( ) , PHIInput , PHIInput -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , AccReg ) ; PHIOps . push_back ( { MachineOperand :: CreateReg ( AccReg , false ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { assert ( ChangedPHIMap . count ( PHIInput ) == <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return <NUM_LIT>


<s> if ( ! ShouldUseImm && Pred && IsEqualityPred ( * Pred ) ) { const ConstantFP * LHSImm = getConstantFPVRegVal ( LHS , MRI ) ; if ( LHSImm && ( LHSImm -> isZero ( ) && ! LHSImm -> isNegative ( ) ) ) { ShouldUseImm = true ; std :: swap ( LHS , RHS ) ; } } unsigned CmpOpcTbl [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned CmpOpc = CmpOpcTbl [ ShouldUseImm ] [ OpSize == <NUM_LIT> ] ; auto CmpMI = MIRBuilder . buildInstr ( CmpOpc ) . addUse ( LHS ) ; CmpMI . setMIFlags ( MachineInstr :: NoFPExcept ) ; if ( ! ShouldUseImm ) CmpMI . addUse ( RHS


<s> Val = DAG . getNode ( <STR_LIT> , DL , VT , Val ) ; Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = getSVESafeBitCast ( CvtVT , Val , DAG ) ; Val = DAG . getNode ( Opcode , DL , ContainerDstVT , Pg , Val , DAG . getUNDEF ( ContainerDstVT ) ) ; return convertFromScalableVector ( DAG , VT , Val ) ; } else { EVT CvtVT = ContainerSrcVT . changeTypeToInteger ( ) ; SDValue Pg = getPredicateForVector ( DAG , DL , CvtVT ) ; Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = DAG . getNode ( Opcode , DL , CvtVT , Pg , Val , DAG . getUNDEF (


<s> ( out_mode == SImode && out_n == C \ && in_mode == SFmode && in_n == C ) ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## v2sfv2si , false ) \ : ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## v4sfv4si , false ) \ : NULL_TREE ) ) ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## uv2sfv2si , false ) \ : ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## uv4sfv4si , false ) \ : NULL_TREE ) ) CASE_CFN_LROUND : return ( out_unsigned_p ? ARM_FIND_VCVTU_VARIANT ( vcvta ) : ARM_FIND_VCVT_VARIANT ( vcvta ) ) ; CASE_CFN_LCEIL : return ( out_unsigned_p ? ARM_FIND_VCVTU_VARIANT ( vcvtp ) : ARM_FIND_VCVT_VARIANT ( vcvtp ) ) ; CASE_CFN_LFLOOR : return ( out_unsigned_p ? ARM_FIND_VCVTU_VARIANT ( vcvtm ) : ARM_FIND_VCVT_VARIANT ( vcvtm ) ) ; ( out_mode == N ## mode && out_n == C \ && in_mode == N ## mode && in_n == C ) case CFN_BUILT_IN_BSWAP16 : if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , HI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv4hi , false ) ; else if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , HI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv8hi , false ) ; else return NULL_TREE ; case CFN_BUILT_IN_BSWAP32 : if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , SI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv2si , false ) ; else if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , SI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv4si , false ) ; else return NULL_TREE ; case CFN_BUILT_IN_BSWAP64 : if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , DI ) )

return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv2di , false ) ;


<s> unsigned sign1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( sign1 != sign2 ) return MCDisassembler :: Fail ; unsigned Val = fieldFromInstruction ( Insn


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , Subtarget , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , Subtarget . abiUsesSoftFloat ( ) , MF . getFunction ( ) -> getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue (


<s> bool isUImm8 ( ) const { return isUImm < <NUM_LIT> >


<s> SDValue Chain ; Align Alignment ( DAG . getEVTAlign ( Tmp . getValueType ( ) ) ) ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; Alignment = Align ( <NUM_LIT> ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Alignment ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , Alignment ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr ; RLI . MPI


<s> else return false ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; for ( -- I ; I != E ; -- I ) { const MachineInstr & Instr = * I ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case LPCC :: ICC_EQ : case LPCC :: ICC_NE : case LPCC :: ICC_MI : case LPCC :: ICC_PL : case LPCC :: ICC_F : case LPCC :: ICC_T : break ; case LPCC :: ICC_CS : case LPCC :: ICC_CC : case LPCC :: ICC_VS : case LPCC :: ICC_VC : case LPCC :: ICC_HI : case LPCC :: ICC_LS : case LPCC :: ICC_GE : case LPCC :: ICC_LT : case LPCC


<s> if ( P < <NUM_LIT> ) return <NUM_LIT> + ( P - <NUM_LIT> ) * <NUM_LIT> ; if ( P <= <NUM_LIT> ) return <NUM_LIT> + ( P - <NUM_LIT> ) ; if ( P < <NUM_LIT> ) return <NUM_LIT> + ( P - <NUM_LIT> ) * <NUM_LIT> ; return <NUM_LIT> + ( P - <NUM_LIT>


<s> assert ( N == <NUM_LIT> && isMemModeRegThumb ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBaseRegNum ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemOffsetRegNum


<s> break ; case <NUM_LIT> : type = TYPE_MOFFS16 ; break ; case <NUM_LIT> : type = TYPE_MOFFS32 ; break ; case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_MOFFS8 : case TYPE_REL8 : if ( immediate & <NUM_LIT> ) immediate


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getSubtarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; unsigned TotalSkipped = <NUM_LIT> ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg ( ) ; int64_t Offset = MFI -> getObjectOffset ( Info . getFrameIdx ( ) ) - getOffsetOfLocalArea ( ) + saveAreaOffset ; if ( HasFP && ( FramePtr == Reg || Reg == <STR_LIT> ) ) { TotalSkipped +=


<s> if ( ! aarch64_composite_type_p ( valtype , TYPE_MODE ( valtype ) ) || int_size_in_bytes ( valtype ) <= <NUM_LIT> || int_size_in_bytes ( valtype ) > <NUM_LIT> ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( valtype ) , valtype , & dummy_mode , & dummy_int


<s> unsigned NumOfVarIndices = <NUM_LIT> ; Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( IndxTy -> isVectorTy ( ) ) IndxTy = IndxTy -> getVectorElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int SplitFactor = std :: max ( IdxsLT . first , SrcLT . first ) ; if ( SplitFactor > <NUM_LIT> ) { Type * SplitSrcTy = VectorType :: get ( SrcVTy ->

getScalarType ( ) , VF / SplitFactor ) ;


<s> bool isELFv2ABI ( ) const { return is<ISA_LIT>64 ( )

&& isSVR4ABI ( ) && isLittleEndian ( ) ; }


<s> else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( AddrOp . getOpcode ( ) == <STR_LIT> ) return isIntS16Immediate ( AddrOp . getOperand ( <NUM_LIT> ) , Imm ) && ! ( Imm % Val ) ; return AddrOp . getOpcode (


<s> int NumBytes = MFI -> getStackSize ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; uint64_t ArgumentPopSize = <NUM_LIT> ; if ( IsTailCallReturn ) { MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; ArgumentPopSize = StackAdjust . getImm ( ) ; } else { ArgumentPopSize = AFI -> getArgumentStackToRestore ( ) ; } MachineBasicBlock :: iterator LastPopI = MBB . getFirstTerminator ( ) ; MachineBasicBlock :: iterator Begin = MBB . begin ( ) ; while ( LastPopI != Begin ) { -- LastPopI ; if ( ! LastPopI -> getFlag ( MachineInstr :: FrameDestroy ) ) { ++ LastPopI ; break ; } } NumBytes -= AFI -> getCalleeSavedStackSize ( ) ; assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP ( MF ) ) { bool RedZone = canUseRedZone ( MF ) ; if ( RedZone && ArgumentPopSize == <NUM_LIT> ) return ; bool NoCalleeSaveRestore = AFI -> getCalleeSavedStackSize ( ) == <NUM_LIT> ; int StackRestoreBytes = RedZone ? <NUM_LIT> : NumBytes ; if ( NoCalleeSaveRestore ) StackRestoreBytes += ArgumentPopSize ; emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , StackRestoreBytes , TII , MachineInstr :: FrameDestroy ) ; if ( NoCalleeSaveRestore || ArgumentPopSize == <NUM_LIT> )


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue OutVal = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : OutVal = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , OutVal ) ; break ; case CCValAssign :: ZExt : OutVal = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , OutVal ) ; break ; case CCValAssign :: AExt : OutVal = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , OutVal ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) { OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( i + <NUM_LIT> < RVLocs . size ( ) && RVLocs [ i + <NUM_LIT> ] . getLocReg ( ) == VA . getLocReg ( ) ) { SDValue NV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVals [ i + <NUM_LIT> ] ) ; OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , NV ) ; ++ i ; } } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVal , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return false


<s> if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) ) return true ; unsigned Reg = RS . FindUnusedReg ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ScratchRegister ) * ScratchRegister = Reg ; return true


<s> void rs6000_cpu_cpp_builtins ( cpp_reader * pfile ) { rs6000_target_modify_macros ( true , rs6000_isa_flags , rs6000_builtin_mask_calculate ( ) ) ; if ( TARGET_FRE ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FRES ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FRSQRTE ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FRSQRTES ) builtin_define ( <STR_LIT> ) ; if ( TARGET_EXTRA_BUILTINS && cpp_get_options ( pfile ) -> lang != CLK_ASM ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; if ( ! flag_iso ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; init_vector_keywords ( ) ; cpp_get_callbacks ( pfile ) -> macro_to_expand = rs6000_macro_to_expand ; } } if ( ( ! ( TARGET_HARD_FLOAT && ( TARGET_FPRS || TARGET_E500_DOUBLE ) ) ) || ( TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_DOUBLE_FLOAT ) ) builtin_define ( <STR_LIT> ) ; if ( rs6000_cpu == PROCESSOR_PPC405 ) builtin_define ( <STR_LIT> ) ; if ( TARGET_NO_LWSYNC ) builtin_define ( <STR_LIT> ) ; if ( TARGET_EXTRA_BUILTINS ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } builtin_define ( <STR_LIT> ) ; RS6000_CPU_CPP_ENDIAN_BUILTINS ( ) ; if ( TARGET_LONG_DOUBLE_128 ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } switch ( TARGET_CMODEL ) { case CMODEL_MEDIUM : builtin_define ( <STR_LIT> ) ; break ; case CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } switch ( rs6000_current_abi ) { case ABI_V4 : builtin_define ( <STR_LIT> ) ; break ; case ABI_AIX : builtin_define ( <STR_LIT> )


<s> int Idx = ShuffV [ i ] ; if ( ( Idx >= <NUM_LIT> && Idx < LHSMaxIdx ) || ( Idx >= RHSMinIdx && Idx < RHSMaxIdx ) ) ShuffV [ i ] += Subtarget

. isLittleEndian ( ) ? HalfVec : HalfVec - ValidLaneWidth ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) || isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; APInt C2Int = C2 -> getAPIntValue ( ) ; APInt C1Int = C1ShlC2 -> getAPIntValue ( ) ; APInt Mask = APInt :: getHighBitsSet ( C2Int . getBitWidth ( ) , C2Int . getBitWidth ( ) - C2 -> getZExtValue ( ) ) ; if ( ( C1Int & Mask ) != C1Int ) return SDValue ( ) ; C1Int . lshrInPlace ( C2Int ) ; auto LargeImm = [ ] ( const APInt & Imm ) { unsigned Zeros = Imm . countLeadingZeros ( ) + Imm . countTrailingZeros ( ) ; return Imm . getBitWidth ( ) - Zeros > <NUM_LIT> ; } ; if ( LargeImm ( C1Int ) || LargeImm ( C2Int ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI


<s> MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta , true ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ; const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; int FrameIdx = MFI -> CreateFixedObject ( SlotSize , - ( int ) SlotSize +

TFI . getOffsetOfLocalArea ( ) + TailCallReturnAddrDelta , true ) ;


<s> NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128HRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128WRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128DRegisterClass ; } else llvm_unreachable ( <STR_LIT> ) ; assert ( NSize != <NUM_LIT> && RegDecoder != nullptr ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , NSize ) ; MI . addOperand ( MCOperand :: createImm ( tmp ) ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return


<s> SDValue Glued = emitIntrinsicWithGlue ( DAG , Op , Opcode ) ; SDValue CC = getCCResult ( DAG , Glued . getNode ( ) ) ; if ( Op -> getNumValues ( ) == <NUM_LIT> ) return CC ; assert ( Op -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op -> getVTList ( ) , Glued , CC ) ; } unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id ) { case <STR_LIT> : return lowerThreadPointer ( SDLoc ( Op ) , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case


<s> <ISA_LIT>_64GOTEntry * got = <NUM_LIT> ; unsigned int EntrySize = <STR_LIT> ; uint64_t RegionSize = <NUM_LIT> ; for ( <STR_LIT> it = m_pGOT -> begin ( ) , ie = m_pGOT -> end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>_64GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint64_t > ( got -> getValue (


<s> MachineOperand NewMO = MO ; NewMO . setImplicit ( ) ; return


<s> void <ISA_LIT>ConstantPoolMBB :: print ( raw_ostream & O ) const { O << printMBBReference ( * MBB


<s> AsmToken Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement (


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand (


<s> static DecodeStatus DecodeZPR2RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZZDecoderTable [ RegNo


<s> void \ sbss_section ( void ) \ { \ if ( in_section != in_sbss ) \ { \ in_section =

in_sbss ; \ fprintf ( asm_out_file , <STR_LIT> , SBSS_SECTION_ASM_OP ) ; \ } \ }


<s> else if ( auto * ZExt = dyn_cast < ZExtInst > ( V ) ) return isa < LoadInst > ( ZExt -> getOperand ( <NUM_LIT> ) ) && ZExt -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ; else if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr (


<s> bool isImm0_508s4 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue


<s> EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > <NUM_LIT> ; -- i ) { SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , <STR_LIT> ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = <NUM_LIT> ; return Estimate ; } return SDValue


<s> static rtx arm_find_shift_sub_rtx ( rtx pattern ) { return arm_find_sub_rtx_with_code ( pattern , ASHIFT


<s>
int
co
=
<NUM_LIT>
;
int
io
=
<NUM_LIT>
;
for
(
io
=
<NUM_LIT>
,
co
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<NUM_LIT>
;
io
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(
<NUM_LIT>
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size
i
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;
io
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{
register
unsigned
int
c
=
(
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char
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p
[
i
+
io
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;
if
(
c
==
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c
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)
partial_output
[
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=
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if
(
c
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partial_output
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else
{
unsigned
int
hexd
;
partial_output
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=
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partial_output
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<NUM_LIT>
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if
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hexd


<s> if ( ! CI -> isTailCall ( ) ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true


<s> case k_CondCode : CC = o . CC ; break ; case k_ITCondMask : ITMask = o . ITMask ; break ; case k_Token : Tok = o . Tok ; break ; case k_CCOut : case k_Register : Reg = o . Reg ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : Registers = o . Registers ; break ; case k_VectorList : case k_VectorListAllLanes : VectorList = o . VectorList ; break ; case k_CoprocNum : case k_CoprocReg : Cop = o . Cop ; break ; case k_CoprocOption : CoprocOption = o . CoprocOption ; break ; case k_Immediate : Imm = o . Imm ; break ; case k_FPImmediate : FPImm = o . FPImm ; break ; case k_MemBarrierOpt : MBOpt = o . MBOpt ; break ; case k_Memory : Memory = o . Memory ; break ; case k_PostIndexRegister : PostIdxReg = o . PostIdxReg ; break ; case k_MSRMask : MMask = o . MMask ; break ; case k_ProcIFlags : IFlags = o . IFlags ; break ; case


<s> mem = or1k_adjust_atomic_subword ( mem , & shift , & mask ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; oldval = expand_binop ( SImode , ashl_optab , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } if ( newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_binop ( SImode , ashl_optab , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; scratch = gen_reg_rtx ( SImode ) ; emit_load_locked ( SImode , scratch , mem ) ; retval = expand_binop ( SImode , and_optab , scratch , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , xor_optab , scratch , retval , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_compare ( EQ , retval , oldval ) ; emit_unlikely_jump ( EQ


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const


<s> if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++

i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ;


<s> InstructionCost Cost = getVectorIntrinsicInstrCost ( ICA . getID ( ) , ICA . getReturnType ( ) ) ; if ( Cost != - <NUM_LIT>


<s> unsigned JTOpIdx = NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( MachineBasicBlock * MBB :


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) ->


<s> __builtin_ia32_storedqu ( ( char * ) __P , ( __v16qi )


<s> } SmallVector < int , <NUM_LIT> > ShuffV ( Mask . begin ( ) , Mask . end ( ) ) ; SDValue SToVLHS = isScalarToVec ( LHS ) ; SDValue SToVRHS = isScalarToVec ( RHS ) ; if ( SToVLHS || SToVRHS ) { int NumEltsIn = SToVLHS ? SToVLHS . getValueType ( ) . getVectorNumElements ( ) : SToVRHS . getValueType ( ) . getVectorNumElements ( ) ; int NumEltsOut = ShuffV . size ( ) ; int LHSMaxIdx = - <NUM_LIT> ; int RHSMinIdx = - <NUM_LIT> ; int RHSMaxIdx = - <NUM_LIT> ; int HalfVec = LHS . getValueType ( ) . getVectorNumElements ( ) / <NUM_LIT> ; if ( SToVLHS ) { LHSMaxIdx = NumEltsOut / NumEltsIn ; SToVLHS = getSToVPermuted ( SToVLHS , DAG ) ; if ( SToVLHS . getValueType ( ) != LHS . getValueType ( ) ) SToVLHS = DAG . getBitcast ( LHS . getValueType ( ) , SToVLHS ) ; LHS = SToVLHS ; } if ( SToVRHS ) { RHSMinIdx = NumEltsOut ; RHSMaxIdx = NumEltsOut / NumEltsIn + RHSMinIdx ; SToVRHS = getSToVPermuted ( SToVRHS , DAG ) ; if ( SToVRHS . getValueType ( ) != RHS . getValueType ( ) ) SToVRHS = DAG . getBitcast ( RHS . getValueType ( ) , SToVRHS ) ; RHS = SToVRHS ; } fixupShuffleMaskForPermutedSToV ( ShuffV , LHSMaxIdx , RHSMinIdx , RHSMaxIdx


<s> unsigned ScratchReg ( unsigned Size ) const { return convReg ( BusyRegs [ REG_OFFSET_SCRATCH ] , Size


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , Out ) . addReg ( Reg1 ) . addImm (

<STR_LIT> ) . addReg ( Reg2 ) . addImm ( <STR_LIT> ) ;


<s> APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) , false ) ; return getTargetVShiftByConstNode ( <ISA_LIT>Opc , SDLoc ( N ) , VT . getSimpleVT ( ) , N0 , EltBits [ <NUM_LIT> ] . getZExtValue ( ) , DAG ) ; } APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG


<s> bool <ISA_LIT>LoadStoreOpt :: findMatchingStore ( MachineBasicBlock :: iterator I , unsigned Limit , MachineBasicBlock :: iterator & StoreI ) { MachineBasicBlock :: iterator B = I -> getParent ( ) -> begin ( ) ; MachineBasicBlock :: iterator MBBI = I ; MachineInstr & LoadMI = * I ; unsigned BaseReg = getLdStBaseOp ( LoadMI ) . getReg ( ) ; if ( MBBI == B ) return false ; ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) { StoreI = MBBI ; return


<s> MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst ) ) return false ; } MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ; if ( ! select ( CopyInst ) ) return false ; I . eraseFromParent (


<s> bool targetHandlesStackFrameRounding (


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI ->

getCallPreservedMask ( MF , CallerCC ) ;


<s> bool <ISA_LIT>FastISel :: selectCmp ( const Instruction * I ) { const CmpInst * CI = cast < CmpInst > ( I ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate ( CI ) ; unsigned ResultReg = <NUM_LIT> ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_FALSE : ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) ; break ; case CmpInst :: FCMP_TRUE : ResultReg = fastEmit_i ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; break ; } if ( ResultReg ) { updateValueMap ( I , ResultReg ) ; return true ; } if ( ! emitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; static unsigned CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned * CondCodes = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_UEQ : CondCodes = & CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_ONE : CondCodes = & CondCodeTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } if ( CondCodes ) { unsigned TmpReg1 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg1 ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg1 , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC = getCompareCC ( Predicate ) ; assert ( ( CC !=


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) ==

<NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ;


<s> static bool hasVariantSymbol ( const MCInst & MI ) { for ( auto & Operand : MI ) { if ( ! Operand . isExpr (


<s> if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n *


<s> Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> , ACPV -> getModifier ( ) ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlignment ( ) ) ; return PCLabelId


<s> const StringRef & Mnemonic = Op0 . getToken ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { Inst = MCInst ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; return false ; } return


<s> return ( int8x8_t ) __builtin_aarch64_rsubhnv8hi (


<s> case CortexX1C : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case CortexA510 : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case CortexA710 : case CortexX2 : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return


<s> if ( ANY_QI_REG_P ( low [ <NUM_LIT> ] ) && ANY_QI_REG_P ( high [ <NUM_LIT> ] ) ) { rtx s , d , flags = gen_rtx_REG ( CCZmode , FLAGS_REG ) ; ix86_expand_clear ( low [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; emit_insn ( gen_testqi_ccz_1 ( operands [ <NUM_LIT> ] , GEN_INT ( half_width ) ) ) ; d = gen_lowpart ( QImode , low [ <NUM_LIT> ] ) ; d = gen_rtx_STRICT_LOW_PART ( VOIDmode , d ) ; s = gen_rtx_EQ ( QImode , flags , const0_rtx ) ; emit_insn ( gen_rtx_SET ( d , s ) ) ; d = gen_lowpart ( QImode , high [ <NUM_LIT> ] ) ; d = gen_rtx_STRICT_LOW_PART ( VOIDmode , d ) ; s = gen_rtx_NE ( QImode , flags , const0_rtx ) ; emit_insn ( gen_rtx_SET ( d , s ) ) ; } else { rtx ( * gen_lshr3 ) ( rtx , rtx , rtx ) ; rtx ( * gen_and3 ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor3 ) ( rtx , rtx , rtx ) ; HOST_WIDE_INT bits ; rtx x ; if ( mode == DImode ) { gen_lshr3 = gen_lshrsi3 ; gen_and3 = gen_andsi3 ; gen_xor3 = gen_xorsi3 ; bits = <NUM_LIT> ; } else { gen_lshr3 = gen_lshrdi3 ; gen_and3 = gen_anddi3 ; gen_xor3 = gen_xordi3 ; bits = <NUM_LIT> ; } if ( TARGET_PARTIAL_REG_STALL && ! optimize_insn_for_size_p ( ) ) x = gen_rtx_ZERO_EXTEND ( half_mode , operands [ <NUM_LIT> ] ) ; else x = gen_lowpart ( half_mode , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( high [ <NUM_LIT> ] , x ) ) ; emit_insn ( gen_lshr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( bits ) ) ) ; emit_insn ( gen_and3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , const1_rtx ) ) ; emit_move_insn ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ) ; emit_insn ( gen_xor3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , const1_rtx ) ) ; } emit_insn ( gen_ashl3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_ashl3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return ; } if ( operands [ <NUM_LIT> ] == constm1_rtx ) { emit_move_insn ( low [ <NUM_LIT> ] ,


<s> for ( unsigned i = <NUM_LIT> ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value ==


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) .


<s> bool mayNeedRelaxation ( const MCInst &


<s> MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>WinCOFFAsmBackend ( T , TT ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT


<s> int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ( TARGET_HARD_FLOAT && TARGET_FPRS && ! is_complex_IBM_long_double ( mode ) && FLOAT128_2REG_P ( mode ) ) ) ) return <NUM_LIT> ; else if ( FLOAT128_VECTOR_P ( mode ) ) return <NUM_LIT> ; else if ( SPE_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> && int_size_in_bytes ( type ) < <NUM_LIT> ) ) return <NUM_LIT> ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( elt_mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) || DEFAULT_ABI == ABI_ELFv2 ) && type && TYPE_ALIGN ( type ) > <NUM_LIT> ) { bool aggregate_p = ( AGGREGATE_TYPE_P ( type ) && ! SCALAR_FLOAT_MODE_P ( elt_mode ) ) ; if ( aggregate_p != ( mode == BLKmode ) ) { static bool warned ; if ( ! warned && warn_psabi


<s> case <STR_LIT> : if ( ! Is64Bit ) return false ; break ; default : return false ; } if ( MRI -> isSSA ( ) ) { CanErase = ! SrcMI -> hasImplicitDef ( ) && MRI -> hasOneNonDBGUse ( FoldingReg ) ; } else { CanErase = ! OtherIntermediateUse && MI . getOperand ( <NUM_LIT> ) . isKill ( ) && ! SrcMI -> hasImplicitDef ( ) ; if ( ! CanErase && SrcMI -> definesRegister ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; } assert ( ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && SrcMI -> getOperand ( <NUM_LIT> ) . isImm ( ) && SrcMI -> getOperand ( <NUM_LIT> ) . isImm ( ) && SrcMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && <STR_LIT> ) ; uint64_t SHSrc = SrcMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t SHMI = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t MBSrc = SrcMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t MBMI = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t MESrc = SrcMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t MEMI = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( MEMI < <NUM_LIT> && MESrc < <NUM_LIT> && MBMI < <NUM_LIT> && MBSrc < <NUM_LIT> ) && <STR_LIT> ) ; bool SrcMaskFull = ( MBSrc - MESrc == <NUM_LIT> ) || ( MBSrc == <NUM_LIT> && MESrc == <NUM_LIT> ) ; if ( ( MBMI > MEMI ) && ! SrcMaskFull ) return false ; APInt MaskMI = APInt :: getBitsSetWithWrap ( <NUM_LIT> , <NUM_LIT> - MEMI - <NUM_LIT> , <NUM_LIT> - MBMI ) ; APInt MaskSrc = APInt :: getBitsSetWithWrap ( <NUM_LIT> , <NUM_LIT> - MESrc - <NUM_LIT> , <NUM_LIT> - MBSrc ) ; APInt RotatedSrcMask = MaskSrc . rotl ( SHMI ) ; APInt FinalMask = RotatedSrcMask & MaskMI ; uint32_t NewMB , NewME ; bool Simplified = false ; if ( FinalMask . isNullValue ( ) ) { Simplified = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . setDesc ( get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; } else { MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) .


<s> static DecodeStatus DecodeBankedReg ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned R = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! R ) { if ( SysM == <NUM_LIT> || SysM == <NUM_LIT> || SysM == <NUM_LIT> || SysM == <NUM_LIT> || SysM == <NUM_LIT> || SysM == <NUM_LIT> ) return MCDisassembler :: SoftFail ; } else { if ( SysM != <NUM_LIT> && SysM != <NUM_LIT> && SysM != <NUM_LIT> && SysM != <NUM_LIT> && SysM != <NUM_LIT> && SysM != <NUM_LIT> && SysM != <NUM_LIT> ) return MCDisassembler :: SoftFail ; } Inst . addOperand ( MCOperand :: createImm ( Val )


<s> LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( Op , DAG ) ; return getAddrLocal ( Op , DAG ,


<s> } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = isUnscaledLdSt ( LoadI ) ; assert ( IsUnscaled == isUnscaledLdSt ( StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( LoadI ) . getImm ( ) : getLdStOffsetOp ( LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( StoreI ) . getImm ( ) : getLdStOffsetOp ( StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( Immr ) . addImm ( Imms ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( BitExtMI ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetAt (


<s> return getSTI ( ) . getFeatureBits ( )


<s> return __builtin_aarch64_sqrshlv4hi ( __a ,


<s> bool <ISA_LIT>TargetLowering :: hasSPE ( ) const { return Subtarget . hasSPE ( )


<s> __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return ( __m128i ) vec_vmsumshm ( ( __v8hi ) __A , (


<s> return ( uint8x16_t ) __builtin_neon_vqsubuv16qi ( ( int8x16_t )


<s> fn = gen_store_conditionalqi ; break ; case E_HImode : fn = gen_store_conditionalhi ; break ; case E_SImode : fn = gen_store_conditionalsi ; break ; case E_DImode : fn = gen_store_conditionaldi ; break ; case E_TImode : fn = gen_store_conditionalti ; break ; default : gcc_unreachable ( ) ; } if ( PPC405_ERRATUM77 ) emit_insn ( gen_hwsync ( ) ) ; emit_insn ( fn ( res , mem ,


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT>


<s> break ; case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> . contains ( R . first ) ) return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , <STR_LIT> , & <STR_LIT> ) , & <STR_LIT> ) ; if ( ! R . second && StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) { R . first = <STR_LIT>


<s> continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; for ( int I = <NUM_LIT> , E = Desc . getNumDefs ( ) ; I != E ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) || ( ! MO . isDead ( ) && ! MRI -> use_nodbg_empty ( Reg ) ) ) continue ; assert ( ! MO . isImplicit ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ; MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const TargetRegisterClass * RC = TII -> getRegClass ( Desc , I , TRI , MF ) ; unsigned NewReg ; if ( RC == nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MO . setReg ( NewReg ) ; MO . setIsDead ( ) ; LLVM_DEBUG ( MI . print ( dbgs (


<s> static inline uint64_t ror ( uint64_t elt , unsigned size


<s> static void getReadTimeStampCounter ( SDNode * N , SDLoc DL , unsigned Opcode , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget , SmallVectorImpl < SDValue > & Results ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue rd = DAG . getNode ( Opcode , DL , Tys , N -> getOperand ( <NUM_LIT> ) ) ; SDValue LO , HI ; if ( Subtarget -> is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } SDValue Chain = HI . getValue ( <NUM_LIT> ) ; if ( Opcode ==


<s> SDValue Ptr2 = DAG . getMemBasePlusOffset ( Ptr1 , HalfAlign , dl ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr1 , Ld -> getPointerInfo ( ) , Alignment , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr2 , Ld -> getPointerInfo ( ) . getWithOffset ( HalfAlign ) , MinAlign ( Alignment , HalfAlign ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , RegVT , Load1 , Load2 ) ; return DCI . CombineTo ( N , NewVec


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned SrcReg ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SrcReg = GPR32ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : SrcReg = GPR64ArgRegs [ GPRIdx ++ ] ; break ; case <STR_LIT> : LLVM_FALLTHROUGH ; case <STR_LIT> : SrcReg = XMMArgRegs [ FPRIdx ++ ] ; break ; } unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & Arg , ResultReg ) ; } return


<s> __v4si mask = __extension__ ( __v4si ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> } ; return ( __m128i ) __builtin_ia32_gatherdiv4si ( src , base , ( __v2di ) index , mask


<s> static int rs6000_use_sched_lookahead ( void )


<s> void addBarrierOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> rtx_insn * i = emit_insn ( gen_rtx_SET ( VOIDmode , m_ccreg , gen_rtx_fmt_ee ( XOR , GET_MODE ( m_ccreg )


<s> x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != LO_SUM ) return false ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> )


<s> if ( DoBothBroadcast ( ) ) return lowerShuffleAsDecomposedShuffleMerge ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ; int LaneCount = VT . getSizeInBits ( ) / <NUM_LIT> ; int LaneSize = Size / LaneCount ; SmallBitVector LaneInputs [ <NUM_LIT> ] ; LaneInputs [ <NUM_LIT> ] . resize ( LaneCount , false ) ; LaneInputs [ <NUM_LIT> ] . resize ( LaneCount , false ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneInputs [ Mask [ i ] / Size ] [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( LaneInputs [ <NUM_LIT> ] . count ( ) <= <NUM_LIT> && LaneInputs [ <NUM_LIT> ] . count ( ) <= <NUM_LIT> ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; return lowerShuffleAsDecomposedShuffleMerge ( DL , VT , V1 , V2 , Mask , Subtarget


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG ) ) return RV ; if ( Subtarget -> hasCMov ( ) ) if ( SDValue RV = performIntegerAbsCombine ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; return SDValue


<s> static void ReplaceCMP_SWAP_64Results ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , createGPRPairNode ( DAG , N -> getOperand ( <NUM_LIT> ) ) , createGPRPairNode ( DAG , N -> getOperand ( <NUM_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDValue Lo = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; SDValue Hi = DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Lo ,


<s> return false ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { auto MMO = * MI . memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI . getMF ( ) -> getSubtarget ( ) ) ; if ( ! isPowerOf2_64 ( MMO -> getSize ( ) ) )


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI ,


<s> switch ( VectorKind ) { case RegKind :: NeonVector : Res = StringSwitch < std :: pair < int , int >> ( Suffix . lower ( ) ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Default ( { - <NUM_LIT> , - <NUM_LIT> } ) ; break ; case RegKind :: SVEPredicateVector : case RegKind :: SVEDataVector


<s> else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; RetOps . insert ( RetOps . begin ( ) + <NUM_LIT> , DAG . getConstant ( LROffset , DL , <STR_LIT> ,


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrsAVX2 ) ; i != e ; ++ i ) if ( ReplaceableInstrsAVX2 [ i ] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrsAVX2 [ i ] ; return <NUM_LIT>


<s> assert ( Name == <STR_LIT> && <STR_LIT> ) ; return


<s> InsertSub = true ; } if ( InsertSub ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , Base ) ) . addReg ( Base , getKillRegState ( true ) ) . addImm ( WordOffset * <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) ; return ; } } if ( MBBI -> killsRegister ( Base ) ) return ; } if ( MBB . succ_size ( ) > <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , -- MBBI , dl , TII -> get ( <STR_LIT> ) , Base ) ) . addReg ( Base , getKillRegState ( true )


<s> return __builtin_mve_vqabsq_sv16qi ( __a )


<s> if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal !=


<s> int M = Mask [ Lane + Elt ] ; if ( M < <NUM_LIT> ) continue ; if ( M < NumElts ) { Blend1 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range1 . first = std :: min ( Range1 . first , M ) ; Range1 . second = std :: max ( Range1 . second , M ) ; } else { M -= NumElts ; Blend2 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range2 . first = std :: min ( Range2 . first , M ) ; Range2 . second = std :: max ( Range2 . second , M ) ; } } } if ( ! ( <NUM_LIT> <= Range1 . first && Range1 . second < NumEltsPerLane ) || ! ( <NUM_LIT> <= Range2 . first && Range2 . second < NumEltsPerLane ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> && ( Blend1 || Blend2 ) ) return SDValue ( ) ; auto RotateAndPermute = [ & ] ( SDValue Lo , SDValue Hi , int RotAmt , int Ofs ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) /


<s> static unsigned matchSVEVectorRegName ( StringRef Name ) { return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT>

) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> void <ISA_LIT>GNUInfo :: setElfFlags ( uint64_t


<s> const GlobalValue * getGlobalValue (


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>_32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>_64Target ( ) ) ; PassRegistry & PR = * PassRegistry ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( JIT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , isLittle ( isLittle ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( TT , CPU , Options . MCOptions ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this , Options . StackAlignmentOverride ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this , Options . StackAlignmentOverride ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this , Options . StackAlignmentOverride ) { Subtarget = & DefaultSubtarget ; initAsmInfo (


<s> rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode


<s> emit_insn ( gen_divxf3 ( e1 , e2 , e1 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn


<s> const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveRegSave ( SMLoc L , bool IsVector ) { if ( ! UC . hasFnStart ( ) ) return Error ( L , <STR_LIT> ) ; if ( UC . hasHandlerData ( ) ) return Error ( L , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; if ( parseRegisterList ( Operands ) || parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; <ISA_LIT>Operand & Op = ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ; if ( ! IsVector && ! Op . isRegList ( ) ) return Error ( L , <STR_LIT> ) ; if ( IsVector && ! Op . isDPRRegList ( ) ) return Error ( L , <STR_LIT> ) ; getTargetStreamer ( ) . emitRegSave ( Op


<s> PrintPICBaseSymbol ( ) ; O << '\n' ; PrintPICBaseSymbol (


<s> MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint ,


<s> void <ISA_LIT>MCAsmStreamer :: EmitBytes ( StringRef Data ) { for ( unsigned i = <NUM_LIT> , e = Data . size ( ) ; i != e ; ++ i ) { EmitValue ( MCConstantExpr :: create ( ( unsigned char ) Data [ i ]


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig >


<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveFRegX ( unsigned


<s> return ( uint16x4_t ) ( vabs_f16 ( __a )


<s> static SDValue performANDCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return SDValue ( ) ; SDValue ShiftRight = N -> getOperand ( <NUM_LIT> ) , Mask = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftRightOpc = ShiftRight . getOpcode ( ) ; if ( ShiftRightOpc != <STR_LIT> && ShiftRightOpc != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode *


<s> bool <ISA_LIT>Subtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel


<s> return ( __mmask64 ) __builtin_ia32_kxordi ( ( __mmask64 )


<s> Register MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; Register MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AtomicOp = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Register Scratch = RegInfo . createVirtualRegister ( RC ) ; Register Scratch2 = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( exitMBB , BranchProbability :: getOne ( ) ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) , MaskLSB2 ) . addReg ( ABI . GetNullPtr ( ) ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr , <NUM_LIT> , ArePtrs64bit ? <STR_LIT> : <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { Register Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) .


<s> void printi512mem ( const MCInst * MI , unsigned OpNo , raw_ostream &


<s> InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget >


<s> if ( isVarArg && ! Outs . empty ( ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; <ISA_LIT>CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) , Call ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CalleeCC , true , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; <ISA_LIT>CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs2 , * DAG . getContext ( ) , Call ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallerCC , true , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [


<s> if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; SMLoc End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; const MCExpr * RndModeOp = MCConstantExpr :: create ( rndMode , Parser . getContext ( ) ) ; return <STR_LIT> ( RndModeOp , Start , End ) ; } if ( Tok . getIdentifier ( ) . equals ( <STR_LIT> ) ) { Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ErrorOperand ( Tok . getLoc


<s> if ( ( Imm & <NUM_LIT> ) == <NUM_LIT> ) FlagSet |= <STR_LIT> ; if ( ( Imm & <NUM_LIT> ) == <NUM_LIT> ) FlagSet |= <STR_LIT> ; } ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { const APInt & ConstImm = CN -> getAPIntValue ( ) ; if ( ConstImm . isSignedIntN ( <NUM_LIT> ) ) { FlagSet |= <STR_LIT> ; SetAlignFlagsForImm ( ConstImm . getZExtValue ( ) ) ; setAlignFlagsForFI ( N , FlagSet , DAG ) ; } if ( ConstImm . isSignedIntN ( <NUM_LIT> ) ) FlagSet |= <STR_LIT> ; else FlagSet |= <STR_LIT> ; } else if ( N . getOpcode ( ) == <STR_LIT> || provablyDisjointOr ( DAG , N ) ) { SDValue RHS = N . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( RHS ) ) { const APInt & ConstImm = CN ->


<s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DestIsHigh = isHighReg ( DestReg ) ; bool SrcIsHigh = isHighReg ( SrcReg ) ; if ( ! DestIsHigh && ! SrcIsHigh ) MI . setDesc ( get ( LowOpcodeK ) ) ; else { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ; MI . setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; MI . tieOperands ( <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine


<s> case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case