<s> else this = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { emit_move_insn ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this , this , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , this ) ) ; addr = mips_add_offset ( temp2 , temp1 , vcall_offset ) ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this , this , temp1 ) ) ; } fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS ) { if ( TARGET_ABICALLS && ! mips_dangerous_for_la25_p ( fnaddr ) ) temp1 = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; mips_load_call_address ( temp1 , fnaddr ,


<s> PerformSDIVReplace = false ; InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 )


<s> const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( ! FullFP16 && LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp2 . getNode ( )


<s> if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( ( isJumpTableBranchOpcode ( SecondLastOpc ) || isIndirectBranchOpcode ( SecondLastOpc ) ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return


<s> return ( __m128i ) __builtin_ia32_pmovzxwd128_mask ( ( __v8hi ) __A , ( __v4si ) _mm_setzero_si128 ( ) ,


<s> void <ISA_LIT>MCExpr :: PrintImpl ( raw_ostream & OS ) const { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_HA16 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_LO16 : OS << <STR_LIT>


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ; char regIdx = '0' + ( intVal % <NUM_LIT> ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , <NUM_LIT> } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint


<s> for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { const auto & DI = MI . getDebugLoc ( ) ; if ( ! DI ) continue ; Location Loc = diToLocation ( DI ) ; MemOpDiscriminators [ Loc ] = std :: max ( MemOpDiscriminators [ Loc ] , DI -> getBaseDiscriminator ( ) ) ; } } DenseMap < Location , DenseSet < unsigned >> Seen ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( <STR_LIT> ( MI . getDesc ( ) . TSFlags ) < <NUM_LIT> ) continue ; const DILocation * DI = MI . getDebugLoc ( ) ; if ( ! DI ) { DI = ReferenceDI ; } DenseSet < unsigned > & Set = Seen [ diToLocation ( DI ) ] ; const std :: pair < DenseSet < unsigned > :: iterator , bool > TryInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; if ( ! TryInsert . second ) { DI = DI -> setBaseDiscriminator ( ++ MemOpDiscriminators [ diToLocation ( DI ) ] ) ; updateDebugInfo ( & MI , DI ) ; Changed = true ; const std :: pair < DenseSet < unsigned > :: iterator , bool > MustInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; if ( ! MustInsert . second ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << DI -> getFilename ( ) << <STR_LIT> << DI -> getLine

( ) << <STR_LIT> << DI -> getColumn ( ) << <STR_LIT> ) ;


<s> Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) &&


<s> return ; } if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) && ! AM . IndexReg . getNode ( ) ) { AM . IndexReg = AM . Base_Reg ; AM . setBaseReg ( SDValue ( ) ) ; } if ( ! AM . IndexReg . getNode ( ) ) return ; bool HasSymbolic = AM . hasSymbolicDisplacement ( ) ; bool NeedsFixing1 = HasSymbolic || ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && AM . Disp > <NUM_LIT> ) ; bool NeedsFixing2 = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) && AM . Base_Reg . getNode ( ) ; if ( ! NeedsFixing1 && ! NeedsFixing2 ) return ; static const unsigned LogTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; assert ( AM . Scale < sizeof ( LogTable ) / sizeof ( LogTable [ <NUM_LIT> ] ) ) ; unsigned ScaleLog = LogTable [ AM . Scale ] ; assert ( ScaleLog <= <NUM_LIT> ) ; SmallVector < SDNode * , <NUM_LIT> > NewNodes ; SDValue NewIndex = AM . IndexReg ; if ( ScaleLog > <NUM_LIT> ) { SDValue ShlCount = CurDAG -> getConstant ( ScaleLog , <STR_LIT> ) ; NewNodes . push_back ( ShlCount . getNode ( ) ) ; SDValue ShlNode = CurDAG -> getNode ( <STR_LIT> , dl , N . getValueType ( ) , NewIndex , ShlCount ) ; NewNodes . push_back ( ShlNode . getNode ( ) ) ; NewIndex = ShlNode ; } if ( AM . Disp > <NUM_LIT> || HasSymbolic ) { SDValue Base , Scale , Index , Disp , Segment ; getAddressOperands ( AM , Base , Scale , Index , Disp , Segment ) ; SDValue DispNode


<s> AddInst = RI . getUniqueVRegDef ( vreg ) ; if ( AddInst == <NUM_LIT> ) return false ; unsigned reg ; int64_t off ; switch ( AddInst -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! AddInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; reg = AddInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; off = AddInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; default : return false


<s> case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLD ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MCSymbol * sym = MCInstLowering . GetSymbolFromOperand ( MI . getOperand ( <NUM_LIT> ) ) ; const MCSymbolRefExpr * symRef = MCSymbolRefExpr :: Create ( sym , SRVK , context ) ; MCInst LEA ; if ( is64Bits ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } OutStreamer . EmitInstruction ( LEA ) ; if ( needsPadding ) { OutStreamer . EmitInstruction ( MCInstBuilder (


<s> Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine


<s> void MLxExpansion :: ExpandFPMLxInstruction ( MachineBasicBlock & MBB , MachineInstr * MI , unsigned MulOpc , unsigned AddSubOpc , bool NegAcc , bool HasLane ) { Register DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; Register AccReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; Register PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const MCInstrDesc & MCID1 = TII -> get ( MulOpc ) ; const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; Register TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg ( PredReg ) ; MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID2 ) . addReg ( DstReg , getDefRegState ( true ) | getDeadRegState ( DstDead ) ) ; if ( NegAcc ) { bool AccKill = MRI -> hasOneNonDBGUse ( AccReg ) ; MIB . addReg ( TmpReg , getKillRegState ( true ) ) . addReg ( AccReg , getKillRegState ( AccKill ) ) ; } else { MIB . addReg ( AccReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; } MIB . addImm ( Pred ) .


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string target = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string source = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * load = ctx -> load ( <NUM_LIT> , source ) ; SExpr * stor = ctx -> store ( ctx -> address ( target ) , load ) ; alfbb . addStatement ( label , TII -> getName (


<s> if ( ArgRegsSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - ArgRegsSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) GPRCS2Size += <NUM_LIT> ; else GPRCS1Size += <NUM_LIT> ; break ; default : if ( Reg == <STR_LIT> ) D8SpillFI = FI ; if ( Reg < <STR_LIT> || Reg >= <STR_LIT> + AFI -> getNumAlignedDPRCS2Regs ( ) ) DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( HasFP ) { int FramePtrOffset = MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size ; emitRegPlusImmediate ( ! AFI -> isThumbFunction ( ) , MBB , MBBI , dl , TII , FramePtr , <STR_LIT> , FramePtrOffset , MachineInstr :: FrameSetup ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getNumAlignedDPRCS2Regs ( ) > <NUM_LIT> ) { MBBI = skipAlignedDPRCS2Spills ( MBBI , AFI


<s> static bool HasSecRelSymbolRef ( const MCExpr * Expr ) { if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr *


<s> void <ISA_LIT>TargetLowering :: computeMaskedBitsForTargetNode ( const SDValue Op , const APInt & Mask , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; KnownZero = KnownOne = APInt ( Mask . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) { OriginalArgWasF128 . push_back ( originalTypeIsF128 ( MF . getFunction ( ) -> getReturnType ( )


<s> void emitARM64WinCFISaveFPLR ( int Offset )


<s> if ( reg ) { cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != <NUM_LIT> ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; label2 = pc_rtx ; if ( invert


<s> else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT>

|| SecondOpcode == <STR_LIT> ) ) return true ;


<s> ErratumSequence code ; pFragRef . memcpy ( & code , <ISA_LIT>InsnHelpers :: InsnSize * <NUM_LIT> , <NUM_LIT> ) ; if ( isErratum843419Sequence ( code . insns [ <NUM_LIT> ] , code . insns [ <NUM_LIT> ] , code . insns [ <NUM_LIT> ] ) ) { return true ; } return


<s> static void mips_set_tune ( const struct mips_cpu_info * info ) { if ( info != <NUM_LIT> ) { mips_tune_info = info ; mips_tune = info


<s> unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( LoadSDN -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ; EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ; SDVTList SDTys = DAG . getVTList ( Tys ) ; unsigned NewOp = IsLaneOp ? <STR_LIT> : <STR_LIT> ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOp , SDLoc ( N ) , SDTys , Ops , MemVT , LoadSDN -> getMemOperand ( ) ) ; SDValue NewResults [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) } ; DCI . CombineTo ( LD , NewResults ) ; DCI . CombineTo ( N , SDValue ( UpdN


<s> bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> )


<s> unsigned getExpandedImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { static_assert ( shift <= <NUM_LIT> , <STR_LIT>


<s> if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) { return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } AtomicRMWInst :: BinOp Op = AI -> getOperation ( ) ; switch ( Op ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst


<s> rtx value4doubleword = gen_reg_rtx ( DImode ) ; nds32_gen_dup_4_byte_to_word_value_aux ( value , nds32_di_low_part_subreg ( value4doubleword ) ) ; emit_move_insn ( nds32_di_high_part_subreg ( value4doubleword ) , nds32_di_low_part_subreg ( value4doubleword ) ) ; return


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , AFI ( nullptr ) , MCP ( nullptr ) , InConstantPool ( false ) { Subtarget = & TM . getSubtarget <


<s> case BUILT_IN_TANF : case BUILT_IN_TANHF : bdecl = builtin_decl_implicit ( fn ) ; suffix = <STR_LIT> ; if ( el_mode != SFmode || n != <NUM_LIT> || ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } } else return NULL_TREE ; gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) =


<s> const char * addend = ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; switch ( which ) { case RS6000_PLTSEQ_TOCSAVE : sprintf ( str , <STR_LIT> <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , tls , rel64 ) ; break ; case RS6000_PLTSEQ_PLT16_HA : if ( DEFAULT_ABI == ABI_V4 && ! flag_pic ) sprintf ( str , <STR_LIT> <STR_LIT> , tls , off , rel64 ) ; else sprintf ( str , <STR_LIT> <STR_LIT> , tls , off , rel64 , addend ) ; break ; case RS6000_PLTSEQ_PLT16_LO : sprintf ( str , <STR_LIT> <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , tls , off , rel64 , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , addend ) ; break ; case RS6000_PLTSEQ_MTCTR : sprintf ( str , <STR_LIT> <STR_LIT> , tls , rel64 , addend ) ; break ; case RS6000_PLTSEQ_PLT_PCREL34 : sprintf ( str , <STR_LIT> <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , tls ,


<s> std :: pair < SDNode * , SDNode * > <ISA_LIT>SEDAGToDAGISel :: selectMULT ( SDNode * N , unsigned Opc , DebugLoc DL , EVT Ty , bool HasLo , bool HasHi ) { SDNode * Lo = <NUM_LIT> , * Hi = <NUM_LIT> ; SDNode * Mul = CurDAG -> getMachineNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { unsigned Opcode = ( Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Lo = CurDAG -> getMachineNode ( Opcode , DL , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) { unsigned Opcode = ( Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Hi = CurDAG -> getMachineNode ( Opcode , DL , Ty , InFlag ) ; } return std :: make_pair (


<s> SDValue CPI = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; return Lo


<s> float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT>


<s> return ( int16x8_t ) __builtin_neon_vqrdmulhv8hi ( __a ,


<s> switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal = <NUM_LIT> ; } if ( ! FlagVal || ( Mask & FlagVal ) ) return - <NUM_LIT> ; Mask |= FlagVal


<s> unsigned char TargetFlag ; unsigned Opcode ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { TargetFlag = <STR_LIT> ; Opcode = <STR_LIT> ; } else { return LowerToTLSExecCall ( GA , DAG , PtrVT , model ,


<s> return ( vector unsigned short ) __builtin_altivec_vsrah ( ( vector signed short ) a1 ,


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII


<s> } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget -> hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget -> hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements


<s> void addImmSExt8Operands ( MCInst & Inst , unsigned N )


<s> assert ( Index < <STR_LIT> :: NUM_PERSONALITY_INDEX && <STR_LIT> ) ; return ( Twine ( <STR_LIT> ) + Twine ( Index )


<s> else if ( Addr . getOpcode ( ) == <STR_LIT> && expandAdjDynAlloc ( AM , true , SDValue ( ) ) ) ; else while ( expandAddress ( AM , true ) || ( AM . Index . getNode ( ) && expandAddress ( AM , false ) ) ) continue ; if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc


<s> if ( update_base_reg_p ) { * src_base_reg = new_base_reg ; * src_mem = gen_rtx_MEM ( SImode , * src_base_reg ) ; } emit_insn ( nds32_expand_store_multiple ( base_regno , count , * dst_base_reg , * dst_mem , update_base_reg_p , & new_base_reg ) ) ; if ( update_base_reg_p )


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: mergePredStateIntoSP ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt , DebugLoc Loc , unsigned PredStateReg ) { unsigned TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( PredStateReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI )


<s> return ! isTargetDarwin ( ) && hasVFP4Base


<s> dlog_t LoggerFn = logger ; if ( & VStream == & nulls ( ) ) LoggerFn = nullptr ; Region R ( Bytes , Address ) ; int Ret = decodeInstruction ( & InternalInstr , regionReader , ( const void * ) & R , LoggerFn , ( void * ) & VStream , ( const void * ) MII . get ( ) , Address , fMode ) ; if ( Ret ) { Size = InternalInstr . readerCursor


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = get<ISA_LIT>RegisterNumbering ( MO . getReg


<s> MachineInstr * VCMP = VCMPOpcodeToVPT ( Divergent -> getOpcode ( ) ) != <NUM_LIT> ? Divergent : nullptr ; if ( DivergentNextIsPredicated ) { if ( ! VCMP ) { MachineInstrBuilder MIB = BuildMI ( * Divergent -> getParent ( ) , Divergent , Divergent -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else { ReplaceVCMPWithVPT ( VCMP , VCMP ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert ( VPST ) ; } else if ( Block . containsVCTP ( ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( Block . size ( ) == <NUM_LIT> ) { assert ( VPST -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; LoLoop . ToRemove . insert ( VPST ) ; } else LoLoop . BlockMasksToRecompute . insert ( VPST ) ; } else if ( Insts . front ( ) -> getOpcode ( ) == <STR_LIT> ) { MachineInstr * VPST = Insts . front ( ) ; auto Next = ++ MachineBasicBlock :: iterator ( VPST ) ; assert ( getVPTInstrPredicate ( * Next ) != <STR_LIT> && <STR_LIT> ) ; ( void ) Next ; MachineInstr * VprDef = RDA -> getUniqueReachingMIDef ( VPST , <STR_LIT> ) ; if ( VprDef && VCMPOpcodeToVPT ( VprDef -> getOpcode ( ) ) && ! LoLoop . ToRemove . contains ( VprDef ) ) { MachineInstr * VCMP = VprDef ; if ( ! std :: any_of ( ++ MachineBasicBlock :: iterator ( VCMP ) , MachineBasicBlock :: iterator ( VPST ) , hasVPRUse ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReplaceVCMPWithVPT ( VCMP , VPST ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; } return Location


<s> A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , NULL ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { if ( Subtarget . getRelocationModel ( ) != Reloc :: PIC_ ) { Function * F_ = CI -> getCalledFunction ( ) ; if ( F_ && needsFPHelperFromSig ( * F_ ) ) { assureFPCallStub ( * F_ , M , Subtarget


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> const TargetFrameLowering * getFrameLowering (


<s> static DecodeStatus DecodeModImmTiedInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT>


<s> MachineBasicBlock :: iterator Loc = MemOps [ <NUM_LIT> ] . MBBI ; unsigned Position = MemOps [ <NUM_LIT> ] . Position ; for ( unsigned i = <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { if ( MemOps [ i ] . Position <


<s> return MIB . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) .


<s> case GE : return GEU ; case ORDERED : case UNORDERED : return code ; break ; case UNEQ : return EQ ; break ; case UNLT : return LTU ; break ; case UNLE : return LEU ; break ; case LTGT : return NE


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( C ) return


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 (

) ) return getFrameIndexReference ( MF , FI , FrameReg ) ;


<s> vst1q_u64 ( uint64_t * a , uint64x2_t b ) { __builtin_aarch64_st1v2di ( ( __builtin_aarch64_simd_di * ) a , (


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 .


<s> unsigned Hint = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ; return MCDisassembler


<s> if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) ) return hard_reg ; else return gen_frame_mem ( Pmode , return_address_pointer_rtx )


<s> SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = DAG . getNode ( <STR_LIT> , DL , Op -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , EFLAGS ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , cpOut ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , Success ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , EFLAGS . getValue


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Frame = DAG . getRegister ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ; unsigned StoreAddrReg = ( Subtarget -> is64Bit ( ) ? <STR_LIT>


<s> unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , dl , VT , Ops , <NUM_LIT> ) ; SDNode * AddCarry = CurDAG -> getMachineNode ( <STR_LIT> , dl , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( NodeTy == <STR_LIT> ) MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; else MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; std :: pair < SDNode * , SDNode * > LoHi = SelectMULT ( Node , MultOpc , dl , NodeTy , true , true ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . first , <NUM_LIT> ) ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . second , <NUM_LIT> ) ) ; return NULL ; } case <STR_LIT> : { if ( Subtarget . has<ISA_LIT>32 ( ) && NodeTy == <STR_LIT> ) break ; return SelectMULT ( Node , NodeTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , NodeTy , true , false ) . first ; } case <STR_LIT> : case <STR_LIT> : { if ( NodeTy == <STR_LIT> ) MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; else MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ; } case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : { ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( Node ) ; if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && CN -> isExactlyValue (


<s> const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> base = emit_adjust_base_to_offset ( base , offset ) ; offset = <NUM_LIT> ; } offset = emit_save_or_restore_regs ( <NUM_LIT> , <NUM_LIT> , base , offset , <NUM_LIT> , save_global_or_fp_reg_p , action , SORR_NONE ) ; emit_save_or_restore_regs ( <NUM_LIT> , TARGET_V9 ? <NUM_LIT> : <NUM_LIT> , base , offset , <NUM_LIT> , save_global_or_fp_reg_p , action


<s> MachineFunctionProperties getRequiredProperties (


<s> return Kind == Memory && ( ! Mem . Size || Mem . Size


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg1 ) ) ; TmpInst . addOperand ( MCOperand ::


<s> if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node

) restore_target_globals ( & default_target_globals ) ;


<s> int64_t SecondOffset = IsLargeOffset ? <NUM_LIT> : OffsetValue ; if ( isLittle ( ) ) std :: swap ( FirstOffset , SecondOffset ) ; if ( IsLargeOffset ) { TOut . emitRRI ( <STR_LIT> , DstReg , ATReg , FirstOffset , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , ATReg , SecondOffset , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , DstReg , ATReg , IDLoc , STI ) ; } else { TOut . emitRRI ( <STR_LIT> , DstReg , SrcReg , FirstOffset , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , SrcReg , SecondOffset , IDLoc ,


<s> if ( CModel == CodeModel :: Small ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg

( <STR_LIT> ) . addGlobalAddress ( GV ) ;


<s> MachineOperand & MO = MI . getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) || ( ! MO . isDead ( ) && ! MRI -> use_nodbg_empty ( Reg ) ) ) continue ; assert ( ! MO . isImplicit ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ; MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const TargetRegisterClass * RC = TII -> getRegClass ( Desc , I , TRI , MF ) ; unsigned NewReg ; if ( RC == nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> bool DblSpaced = false ; if ( Name . find ( <STR_LIT> ) != std :: string :: npos ) { if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; } else { if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) )


<s> int OperandToKeep = LII . SetCR ? <NUM_LIT> : <NUM_LIT> ; for ( int i = MI . getNumOperands ( ) - <NUM_LIT> ; i > OperandToKeep ; i -- ) MI . RemoveOperand ( i ) ; if ( LII . SetCR ) { MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII . Imm ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return ; } else MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> :


<s> int length = get_attr_length ( insn ) ; if ( branch_to_delay_slot_p ( insn ) ) { if ( which_alternative == <NUM_LIT> ) return <STR_LIT> ; else if ( which_alternative == <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else { output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } } if ( which_alternative == <NUM_LIT> ) { int nullify = INSN_ANNULLED_BRANCH_P ( insn ) ; int xdelay ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; switch ( length ) { case <NUM_LIT> : if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) return <STR_LIT> ; else return <STR_LIT> ; } else return <STR_LIT> ; case <NUM_LIT>


<s> APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( Op , Mask17 ) ) return Op ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op , DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> && VT . getSizeInBits ( ) <= <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; if ( Src . getScalarValueSizeInBits ( ) < <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) { EVT ExtVT = VT . changeVectorElementType ( <STR_LIT> ) ; Src = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , ExtVT , Src ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } } if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && Op . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ; } ; SDValue ZeroN0 = GetZeroableOp ( N0 ) ; SDValue ZeroN1 = GetZeroableOp ( N1 ) ; if ( ! ZeroN0 && ! ZeroN1


<s> rtx table ; if ( GET_CODE ( insn ) == JUMP_INSN && JUMP_LABEL ( insn ) != NULL && ( ( table = next_real_insn ( JUMP_LABEL ( insn ) ) ) == next_real_insn ( insn ) ) && table != NULL && GET_CODE ( table ) == JUMP_INSN && ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC || GET_CODE ( PATTERN ( table ) ) == ADDR_DIFF_VEC ) ) return table ; return


<s> return DecodeMVE_MEM_pre ( Inst , Val , Address , Decoder , fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) , DecodetGPRRegisterClass , DecodeTAddrModeImm7 <


<s> auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeFPR32RegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR32DecoderTable [ Ry + Imm5 ] ) ) ; return MCDisassembler ::


<s> StringRef getPassName ( ) const override { return


<s> DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! NeverUseSaveRestore ) { if ( isUInt < <NUM_LIT> > ( FrameSize ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; else { int Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Base ) ; if ( isInt < <NUM_LIT> > ( - Remainder ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( - Remainder ) ; else adjustStackPtrBig ( SP , - Remainder , MBB , I , <STR_LIT> , <STR_LIT> ) ; } } else { MachineInstrBuilder MIB1 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB1 . addReg ( <STR_LIT> ) ; MIB1 . addImm ( - <NUM_LIT> ) ; MachineInstrBuilder MIB2 = BuildMI ( MBB , I , DL , get (


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; if ( OpIdx == TID . getNumOperands ( ) || TID . OpInfo [ OpIdx ] . isPredicate ( ) || TID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { Binary |= getMachineOpValue ( MI , MO ) ; emitWordLE ( Binary ) ; return ; } Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand (


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op


<s> assert ( ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF .


<s> if ( BitSize == <NUM_LIT> ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue


<s> SDValue <ISA_LIT>TargetLowering :: lowerThreadPointer ( const SDLoc & DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName

( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned LR = getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MF . getRegInfo ( ) . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsSVR4ABI = Subtarget . isSVR4ABI ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) && IsSVR4ABI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( PerformTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MF . getFrameInfo ( ) -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta ) ; } if ( EnableRegisterScavenging ) if ( needsFP ( MF ) || spillsCR ( MF ) ) { const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = Is<ISA_LIT>64 ? G8RC : GPRC ; RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( OpNum == <NUM_LIT> ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } break ; case <STR_LIT> : isFloat = true ; case <STR_LIT> : if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? <STR_LIT> : <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , false , false , isKill ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg

, true , false , false , isDead ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> MCSymbol * <ISA_LIT>FunctionInfo :: getGlobalEPSymbol ( MachineFunction & MF ) const { const DataLayout & DL = MF .


<s> unsigned Ry = MI . getOperand ( Idx ) . getReg ( ) ; unsigned Rz = MI . getOperand ( Idx + <NUM_LIT> ) . getImm ( ) ; unsigned Imm = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Rz ) - Ctx . getRegisterInfo ( ) -> getEncodingValue (


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > (


<s> if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } if ( Constraint [ <NUM_LIT> ] == '{' ) { if ( Constraint [ <NUM_LIT> ] == 'r' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'f' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT>


<s> static bool isZeroExtended ( SDNode *


<s> OperandMatchResultTy parseBDLAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , BDLMem , <STR_LIT> ,


<s> ArrayRef < int > GoodInputs = MoveToLo ? LoInputs : HiInputs ; ArrayRef < int > BadInputs = MoveToLo ? HiInputs : LoInputs ; if ( BadInputs . empty ( ) ) return V ; int MoveMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int MoveOffset = MoveToLo ? <NUM_LIT> : <NUM_LIT> ; if ( GoodInputs . empty ( ) ) { for ( int BadInput : BadInputs ) { MoveMask [ Mask [ BadInput ] % <NUM_LIT> + MoveOffset ] = Mask [ BadInput ] - MaskOffset ; Mask [ BadInput ] = Mask [ BadInput ] % <NUM_LIT> + MoveOffset + MaskOffset ; } } else { if ( GoodInputs . size ( ) == <NUM_LIT> ) { MoveMask [ Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset ] = Mask [ GoodInputs [ <NUM_LIT> ] ] - MaskOffset ; MoveMask [ Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset ] = Mask [ GoodInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ GoodInputs [ <NUM_LIT> ] ] = Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset + MaskOffset ; Mask [ GoodInputs [ <NUM_LIT> ] ] = Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset + MaskOffset ; } else { for ( int GoodInput : GoodInputs ) MoveMask [ Mask [ GoodInput ] - MaskOffset ] = Mask [ GoodInput ] - MaskOffset ; } int MoveMaskIdx = std :: find ( std :: begin ( MoveMask ) + MoveOffset , std :: end ( MoveMask ) , - <NUM_LIT> ) - std :: begin ( MoveMask ) ; assert ( MoveMaskIdx >= MoveOffset && <STR_LIT> ) ; if ( BadInputs . size ( ) == <NUM_LIT> ) { assert ( MoveMask [ MoveMaskIdx ] == - <NUM_LIT> && <STR_LIT> ) ; assert ( MoveMask [ MoveMaskIdx + <NUM_LIT> ] == - <NUM_LIT> && <STR_LIT> ) ; MoveMask [ MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; MoveMask [ MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MaskOffset ; } else { assert ( BadInputs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MoveMask [ MoveMaskIdx ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + MaskOffset ; } } return DAG . getVectorShuffle ( <STR_LIT> , DL , V

, DAG . getUNDEF ( <STR_LIT> ) , MoveMask ) ;


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , dl , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , dl , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; S -> EmitBundleAlignMode (


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> ) , Subtarget -> has64BitPointers ( )

? <NUM_LIT> : <NUM_LIT> , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>CondCodeToString ( CC


<s> const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; bool CloseParen = false ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } switch ( MO . getType


<s> RegisterReqs . erase ( getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Lex ( ) ; return parseToken ( AsmToken ::


<s> if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . isScalableVector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } else { PredicateConstraint PC = parsePredicateConstraint ( Constraint ) ; if ( PC != PredicateConstraint :: Invalid ) { assert ( VT . isScalableVector ( ) ) ; bool restricted = ( PC == PredicateConstraint :: Upl ) ; return restricted ? std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) : std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 'v' && Constraint [ Size - <NUM_LIT> ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( <NUM_LIT> , Size - <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , RegNo ) ; if ( ! Failed && RegNo >= <NUM_LIT> && RegNo <= <NUM_LIT> ) { if ( VT != <STR_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) { Res . first = <STR_LIT> . getRegister ( RegNo ) ; Res . second = & <STR_LIT> ; } else { Res . first = <STR_LIT> . getRegister ( RegNo ) ; Res . second = & <STR_LIT> ; } } } } if ( Res . second && ! Subtarget -> hasFPARMv8 ( ) && ! <STR_LIT> . hasSubClassEq ( Res . second ) && ! <STR_LIT>

. hasSubClassEq ( Res . second ) ) return std :: make_pair ( <NUM_LIT> , nullptr ) ;


<s> vld1q_dup_s8 ( const int8_t * __a ) { return vdupq_n_s8 ( * __a )


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; auto Ty = MRI . getType ( LHS . getReg ( ) ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; bool Is32Bit = Size


<s> if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N


<s> default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( Operands ) != MatchOperand_NoMatch ) return false ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E , * this ) ) ; return false ; } case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: Tilde : case AsmToken :: String : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; return ResTy != MatchOperand_Success ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) )


<s> if ( ! targetm . have_tls ) return false ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (


<s> bool is64bit = VT == <STR_LIT> ; if ( TLI . isFPImmLegal ( Val , VT ) ) { int Imm ; unsigned Opc ; if ( is64bit ) { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } else { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc )


<s> unsigned i = <NUM_LIT> ; for ( auto & Arg : Info . OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; ArgInfos . push_back ( Arg ) ; OrigArgIndices . push_back ( i ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; bool IsCalleeVarArg = false ; if ( Info . Callee . isGlobal ( ) ) { const Function * CF = static_cast < const Function * > ( Info . Callee . getGlobal ( ) ) ; IsCalleeVarArg = CF -> isVarArg ( ) ; } <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , IsCalleeVarArg , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , Align ( <NUM_LIT> ) ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; if ( IsCalleeGlobalPIC ) { MIRBuilder . buildCopy ( Register ( <STR_LIT> ) , MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseRegForGlobalISel ( MF ) ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( MIB -> getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; MIB . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > OrigRetIndices ; splitToValueTypes ( DL , Info . OrigRet , <NUM_LIT> , ArgInfos , OrigRetIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigRetIndices , Ins ) ; SmallVector < CCValAssign ,


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , FS


<s> REVB = DAG . getNode ( <STR_LIT> , DL , VST , Op . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { VST = <STR_LIT> ; REVB = DAG . getNode ( <STR_LIT> , DL , VST , Op . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { VST = <STR_LIT> ; REVB = DAG . getNode ( <STR_LIT> , DL , VST , Op . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT>


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc =


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; int dest_uid


<s> bool DestIsHigh = isHighReg ( DestReg ) ; bool SrcIsHigh = isHighReg ( SrcReg ) ; if ( ! DestIsHigh && ! SrcIsHigh ) MI . setDesc ( get


<s> if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : case CCValAssign :: ZExt : Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; break ; case CCValAssign :: AExtUpper : assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; break ; } if ( RegsUsed . count ( VA . getLocReg ( ) ) ) { SDValue & Bits = llvm :: find_if ( RetVals , [ = ] ( const std :: pair < unsigned , SDValue > & Elt ) { return Elt . first == VA . getLocReg ( ) ; } ) -> second ; Bits = DAG . getNode ( <STR_LIT> , DL , Bits . getValueType ( ) , Bits , Arg ) ; } else { RetVals . emplace_back ( VA . getLocReg ( ) , Arg ) ; RegsUsed . insert ( VA . getLocReg ( ) ) ; } } SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( auto & RetVal : RetVals ) { Chain = DAG . getCopyToReg ( Chain , DL , RetVal . first , RetVal . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetVal . first , RetVal . second . getValueType ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( RetOps [ <NUM_LIT> ] , DL , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RetValReg , Val ,


<s> CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true , OpFlags


<s> unsigned CC = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = whichOp8u_or_16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT>


<s> MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , is64Bit ? <STR_LIT> : <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; I -> eraseFromParent (


<s> return ( __m256i ) __builtin_ia32_vcvtph2uw256_mask ( __A , ( __v16hi ) _mm256_setzero_si256 ( ) , ( __mmask16 )


<s> MachineInstrBuilder VPUSH = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( int Reg = <STR_LIT> ; Reg <= <STR_LIT> ; ++ Reg ) VPUSH . addReg ( Reg ) ; ( void ) CMSEClearFPRegsV81 ( MBB , MBBI , ClearRegs ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> )


<s> setISAExtensionFromPredicates ( P , ABI ) ; setASESetFromPredicates ( P ) ; setFpAbiFromPredicates ( P ) ; OddSPReg = P . useOddSPReg


<s> RegisterAsmParser < <ISA_LIT>AsmParser > Y


<s> unsigned LoadOpc = <STR_LIT> ; if ( SrcVT == <STR_LIT> ) { if ( ! IsSigned ) { LoadOpc = <STR_LIT> ; Addr . Offset = <NUM_LIT> ; } else if ( <ISA_LIT>SubTarget . hasLFIWAX ( ) ) { LoadOpc = <STR_LIT> ; Addr . Offset = <NUM_LIT> ; } } const TargetRegisterClass * RC = & <STR_LIT> ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( <STR_LIT> , ResultReg , Addr , RC , ! IsSigned , LoadOpc ) ) return <NUM_LIT> ; return ResultReg


<s> if ( ! MO . isReg ( ) ) continue ; unsigned R = MO . getReg ( ) - <STR_LIT> ; if ( R < <NUM_LIT> ) { if ( MF -> getFunction ( ) -> getCallingConv ( ) != CallingConv :: <ISA_LIT>_RegCall ) { assert ( MO . isDef ( ) && MO . isImplicit ( ) ) ; } STReturns |= <NUM_LIT> << R ; } } unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <=


<s> if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32


<s> bool aarch64_sve_bitmask_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && aarch64_bitmask_imm ( INTVAL

( elt ) , GET_MODE_INNER ( GET_MODE ( x ) ) ) ) ;


<s> O << ( uint32_t ) MI -> getOperand ( OpNum


<s> if ( ! TARGET_HAVE_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS )


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF (


<s> unsigned WideSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT NarrowTy = <STR_LIT> ( EltTy , WideSize / <NUM_LIT>


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm


<s> fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file ,


<s> SDValue getAddrLocal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , bool IsN32OrN64 ) const { unsigned GOTFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } FPUTopSavedRegOff = FPUBitmask ? ( HasAFGR64Reg ? - AFGR64RegSize : - FGR32RegSize ) : <NUM_LIT> ; CPUTopSavedRegOff = CPUBitmask ? - CSFPRegsSize - CPURegSize : <NUM_LIT> ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O ) ; O << ',' << CPUTopSavedRegOff << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask , O ) ; O << <STR_LIT> <<


<s> static unsigned HOST_WIDE_INT aarch64_asan_shadow_offset ( void ) { if ( TARGET_ILP32 ) return


<s> SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back (


<s> return new <ISA_LIT>PassConfig ( * this ,


<s> Offset = <NUM_LIT> ; Addr = MaskedOp -> getBasePtr ( ) ; if ( TrueMaskElt != <NUM_LIT> ) { Offset = TrueMaskElt * EltVT . getStoreSize ( ) ; Addr = DAG . getMemBasePlusOffset ( Addr , TypeSize :: Fixed ( Offset ) , SDLoc ( MaskedOp ) ) ; } Index = DAG . getIntPtrConstant ( TrueMaskElt , SDLoc ( MaskedOp ) ) ; Alignment = commonAlignment ( MaskedOp -> getOriginalAlign ( ) , EltVT . getStoreSize (


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addImm ( NumBytes ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } else if ( ( NumBytes & <NUM_LIT> ) == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != -


<s> bool hasAndNotCompare ( SDValue ) const


<s> return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNo<ISA_LIT>16 ( ) ; Parser . Lex ( ) ; return false


<s> bool isITCondCodeRestrictedFP ( ) const { if ( ! isITCondCode ( ) ) return false ; <STR_LIT> CC = getCondCode ( ) ; return CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ||


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass *

RC , const TargetRegisterInfo * TRI ) const {


<s> const MCInstrDesc & Mtc1Tdd = get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( FP64 ) { BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( HiReg ) . addReg ( DstReg , RegState :: Implicit ) ; } else BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg

( DstReg , <STR_LIT> ) ) . addReg ( HiReg ) ;


<s> d -> perm . rotate_inputs ( <NUM_LIT> ) ; std :: swap ( d -> op0 , d -> op1 ) ; } if ( ( d -> vec_flags == VEC_ADVSIMD || d -> vec_flags == VEC_SVE_DATA || d -> vec_flags == VEC_SVE_PRED ) && known_gt ( nelt , <NUM_LIT> ) ) { if ( aarch64_evpc_rev_local ( d ) ) return true ; else if ( aarch64_evpc_rev_global ( d ) ) return true ; else if ( aarch64_evpc_ext ( d ) ) return true ; else if ( aarch64_evpc_dup ( d ) ) return true ; else if ( aarch64_evpc_zip ( d ) ) return true ; else if ( aarch64_evpc_uzp ( d


<s> EDInstInfo * ThumbDisassembler :: getEDInfo ( ) const { return instInfo<ISA_LIT>


<s> unsigned CSSize = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize


<s> if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ! ByteOk && ! HalfWordOk ) continue ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; CPUser & User = CPUsers [ JumpTableUserIndices [ JTI ] ] ; unsigned DeadSize = <NUM_LIT> ; bool CanDeleteLEA = false ; bool BaseRegKill = false ; bool PreservedBaseReg = preserveBaseRegister ( MI , User . MI , DeadSize , CanDeleteLEA , BaseRegKill ) ; if ( ! jumpTableFollowsTB ( MI , User . CPEMI ) && ! PreservedBaseReg ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstr * CPEMI = User . CPEMI ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock :: iterator MI_JT = MI ; MachineInstr * NewJTMI = BuildMI ( * MBB , MI_JT , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( User . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getKillRegState ( BaseRegKill ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ; unsigned JTOpc = ByteOk ? <STR_LIT> : <STR_LIT> ; CPEMI -> setDesc ( TII -> get ( JTOpc ) ) ; if ( jumpTableFollowsTB ( MI , User . CPEMI ) ) { NewJTMI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; NewJTMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; if ( CanDeleteLEA ) { User . MI -> eraseFromParent


<s> Streamer . visitUsedExpr ( * getSubExpr (


<s> SDValue PassThru = ExtendToType ( N -> getPassThru ( ) , WideDataVT , DAG ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , PassThru , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Exract , NewLoad .


<s> <ISA_LIT>TargetStreamer & <ISA_LIT>AsmPrinter :: getTargetStreamer (


<s> return ( __m128d ) __builtin_ia32_cmpgtpd ( ( __v2df ) __A , ( __v2df )


<s> if ( ( REGNO ( reg ) % <NUM_LIT> ) == <NUM_LIT> && mem_min_alignment

( mem , <NUM_LIT> ) ) return <NUM_LIT> ;


<s> if ( getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) return F

-> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> ;


<s> Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; if ( NewOp == <STR_LIT> ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG .


<s> inline unsigned getThumbImmValShift ( unsigned Imm ) { if ( ( Imm & ~ <NUM_LIT> )


<s> Type = ELF :: R_<ISA_LIT>_THM_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS8 ; break ; } break ; case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS16 ; break ; } break ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr


<s> LastCMOV = & * NextMIIt ; ++ NextMIIt ; } } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FalseMBB -> addSuccessor ( SinkMBB ) ; unsigned Opc = <STR_LIT>


<s> static unsigned getDUPLANEOp ( EVT EltType ) { if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> || EltType


<s> if ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? <NUM_LIT> : <NUM_LIT> ; booth_unit_size = <NUM_LIT> ; for ( j = <NUM_LIT> ; i && j < <NUM_LIT> ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS (


<s> addDirectMem ( BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( ReturnReg ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( OffsetReg ) . addReg ( OffsetReg , RegState :: Undef ) . addReg ( OffsetReg , RegState :: Undef ) ; addSegmentedMem ( BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) , <STR_LIT> , OffsetReg ) . addImm ( <NUM_LIT> ) ; addSegmentedMem ( BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) )

. addDef ( OffsetReg ) , <STR_LIT> , OffsetReg ) ;


<s> assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg ( ) ) ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( Subtarget . hasMTHC1 ( ) ) { BuildMI ( MBB , I , dl , get ( isMicro<ISA_LIT> ? ( FP64 ? <STR_LIT> : <STR_LIT> ) : ( FP64 ? <STR_LIT> : <STR_LIT> ) ) , DstReg ) .


<s> TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm1 ) ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm2 ) ) ; TmpInst . setLoc ( IDLoc ) ; getStreamer ( ) . emitInstruction ( TmpInst


<s> std :: string Name = getRegisterName ( Reg ) ; Name [ <NUM_LIT> ] = 'v' ; O <<


<s> else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else return false ; unsigned DefReg = SrcReg ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) { DefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , DefReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } MachineInstr & AndInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( AndOpc ) , DstReg ) . addReg ( DefReg ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( AndInst , TII , TRI


<s> } else { set_optab_libfunc ( sdivmod_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( udivmod_optab , DImode , <STR_LIT> ) ; } darwin_rename_builtins (


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BaseRegister = FP ? <STR_LIT> : <STR_LIT> ; MI . getOperand ( i ) . ChangeToRegister ( BaseRegister , false ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += MF . getFrameInfo ( ) ->


<s> gcc_checking_assert ( n_extra_regs <= MAX_EXTRA_REGS ) ; gcc_assert ( stub < XLOGUE_STUB_COUNT ) ; gcc_assert ( crtl -> stack_realign_finalized ) ; return gen_rtx_SYMBOL_REF ( Pmode , get_stub_name ( stub , n_extra_regs )


<s> static DecodeStatus DecodeUImmWithOffset ( MCInst & Inst , unsigned Value

, uint64_t Address , const MCDisassembler * Decoder ) {


<s> if ( ! rs6000_store_data_bypass_p ( dep_insn , insn ) ) return get_attr_var_shift ( dep_insn ) == VAR_SHIFT_YES ? <NUM_LIT> : <NUM_LIT> ; break ; } case TYPE_INTEGER : case TYPE_ADD : case TYPE_LOGICAL : case TYPE_EXTS : case TYPE_INSERT : { if ( ! rs6000_store_data_bypass_p ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_STORE : case TYPE_FPLOAD : case TYPE_FPSTORE : { if ( get_attr_update ( dep_insn ) == UPDATE_YES && ! rs6000_store_data_bypass_p ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_MUL : { if ( ! rs6000_store_data_bypass_p ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_DIV : { if ( ! rs6000_store_data_bypass_p ( dep_insn , insn ) ) return get_attr_size ( dep_insn ) == SIZE_32 ? <NUM_LIT> : <NUM_LIT> ; break ; } default : break ; } } break ; case TYPE_LOAD : if ( ( rs6000_tune == PROCESSOR_POWER6 ) && recog_memoized ( dep_insn ) && ( INSN_CODE ( dep_insn ) >= <NUM_LIT> ) ) { switch ( get_attr_type ( dep_insn ) ) { case TYPE_LOAD : case TYPE_CNTLZ : { if ( set_to_load_agen ( dep_insn , insn ) ) return get_attr_sign_extend ( dep_insn ) == SIGN_EXTEND_YES ? <NUM_LIT> : <NUM_LIT> ; break ; } case TYPE_SHIFT : { if ( set_to_load_agen ( dep_insn , insn ) ) return get_attr_var_shift ( dep_insn ) == VAR_SHIFT_YES ? <NUM_LIT> : <NUM_LIT> ; break ; } case TYPE_INTEGER : case TYPE_ADD : case TYPE_LOGICAL : case TYPE_EXTS : case TYPE_INSERT : { if ( set_to_load_agen ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_STORE : case TYPE_FPLOAD : case TYPE_FPSTORE : { if ( get_attr_update ( dep_insn ) == UPDATE_YES && set_to_load_agen ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_MUL : { if ( set_to_load_agen ( dep_insn , insn ) ) return <NUM_LIT> ; break ; } case TYPE_DIV : { if ( set_to_load_agen ( dep_insn , insn ) ) return get_attr_size ( dep_insn ) == SIZE_32 ? <NUM_LIT> : <NUM_LIT> ; break ; } default : break ; } } break ; default : break ; } } break ; case REG_DEP_OUTPUT : if ( ( rs6000_tune == PROCESSOR_POWER6 ) && recog_memoized ( dep_insn ) && ( INSN_CODE ( dep_insn ) >= <NUM_LIT> ) ) { attr_type = get_attr_type (


<s> else dst = gen_reg_rtx ( mode ) ; } if ( GET_CODE ( src1 ) == MEM && GET_CODE ( src2 ) == MEM ) { if ( matching_memory != <NUM_LIT> ) src2 = force_reg ( mode , src2 ) ; else src1 = force_reg ( mode , src1 ) ; } if ( ( CONSTANT_P ( src1 ) || ( ! matching_memory && GET_CODE ( src1 ) == MEM ) ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) src1 = force_reg ( mode , src1 ) ; src1 = operands [


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitSignExtendToI32InReg ( MachineInstr * MI , MachineBasicBlock * BB , unsigned Size , unsigned DstReg , unsigned SrcReg ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size ==


<s> if ( Kind != k_Register || Reg . Kind != RegKind :: SVEDataVector ) return DiagnosticPredicateTy :: NoMatch ; if ( isSVEVectorReg < Class > ( ) && ( ElementWidth == <NUM_LIT> || Reg . ElementWidth == ElementWidth ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy :: NearMatch


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy


<s> OriginalMCID = & TII -> get ( I . OrigOpc ) ; for ( auto & Repl : I . ReplOpc ) ReplInstrMCID . push_back ( & TII -> get ( Repl ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) { InterlEarlyExit [ Subtarget ] = false ; return false ; } ReplInstrMCID . clear ( ) ; } InterlEarlyExit [ Subtarget ]


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo ,


<s> MCSymbolData & Data = getStreamer ( ) .


<s> ShuffleMask = cast < ShuffleVectorSDNode > ( VecShuffle ) -> getMask ( ) ; } BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( RHS . getNode ( ) ) ; if ( ! BVN ) return SDValue ( ) ; APInt APSplatValue , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BVN -> isConstantSplat ( APSplatValue , APSplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittleEndian ( ) ) || SplatBitSize > <NUM_LIT> ) return SDValue ( ) ; SDValue Index ; bool IsLE = Subtarget . isLittleEndian ( ) ; if ( ( ShuffleMask [ <NUM_LIT> ] == <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] == <NUM_LIT> ) && ( ShuffleMask [ <NUM_LIT> ] % <NUM_LIT> == <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] % <NUM_LIT> == <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] > <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] > <NUM_LIT> ) ) Index = DAG . getTargetConstant ( IsLE ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; else if ( ( ShuffleMask [ <NUM_LIT> ] == <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] == <NUM_LIT> ) && ( ShuffleMask [ <NUM_LIT> ] % <NUM_LIT> == <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] % <NUM_LIT> == <NUM_LIT> && ShuffleMask [ <NUM_LIT> ] > <NUM_LIT> && ShuffleMask [ <NUM_LIT> ]


<s> if ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects ( ) ) return true ; return


<s> void <ISA_LIT>AsmPrinter :: EmitBasicBlockEnd ( const MachineBasicBlock & MBB ) { <ISA_LIT>TargetStreamer & TS =


<s> return __builtin_loongson_pcmpeqb_s ( s , t )


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr


<s> unsigned internalKnownBits ( ) const


<s> if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; if ( III . SignedImm ) { APInt ActualValue ( <NUM_LIT> , Imm , true ) ; if ( ! ActualValue . isSignedIntN ( III . ImmWidth ) ) return false ; } else { uint64_t UnsignedMax = ( <NUM_LIT> << III . ImmWidth ) - <NUM_LIT> ; if ( ( uint64_t ) Imm > UnsignedMax ) return


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t

) <STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> SDValue Arg = OutVals [ RealResIdx ] ; if ( Subtarget . isAIXABI ( ) && ( VA . getLocVT ( ) . isVector ( ) || VA . getValVT ( ) . isVector ( ) ) ) report_fatal_error ( <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( Subtarget . hasSPE ( ) && VA . getLocVT ( ) == <STR_LIT> ) { bool isLittleEndian = Subtarget . isLittleEndian ( ) ; SDValue SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) ,