<s> SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; Opcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , VT , ExOp ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ; unsigned NumSubElts = SplitSize / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; unsigned IROpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , SplitSize ) ; SrcVec = DAG . getNode ( IROpc , DL , SubVT , SrcVec ) ; Opnds . push_back ( SrcVec ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Opnds ) ; } ; if ( ! Subtarget . hasAVX ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) return SplitAndExtendInReg ( <NUM_LIT> ) ; if ( ! Subtarget . useAVX512Regs ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) )


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> (


<s> Loop * L = LI -> getLoopFor ( I -> getParent ( ) ) ; if ( L == nullptr ) return nullptr ; GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; Value * Offsets ; Value * BasePtr = decomposeGEP ( Offsets , Ty , GEP , Builder ) ; if ( ! BasePtr ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; int TypeScale = computeScale ( DL -> getTypeSizeInBits ( GEP -> getOperand ( <NUM_LIT> ) -> getType ( ) ) , DL -> getTypeSizeInBits ( GEP -> getType ( ) ) / cast < FixedVectorType > ( GEP -> getType ( ) ) -> getNumElements ( ) ) ; if ( TypeScale == - <NUM_LIT> )


<s> static int arm_cortex_m_branch_cost ( bool


<s> temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2v2sf ( ( __builtin_aarch64_simd_sf * )


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum ,


<s> if ( gr_saved > <NUM_LIT> ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > <NUM_LIT> ) { machine_mode mode = TImode ; int off , i , vr_start ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; vr_start = V0_REGNUM +


<s> if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == <NUM_LIT> ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , to_parse , len ) == <NUM_LIT> ) { unsigned long isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT Op1VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ResVT = Val . getValueType ( ) ; if ( ! isTypeLegal ( ResVT ) ) return SDValue ( ) ; bool ValidTypeForStoreFltAsInt = ( Op1VT == <STR_LIT> || Op1VT == <STR_LIT> || ( Subtarget . hasP9Vector ( ) && ( Op1VT == <STR_LIT> || Op1VT == <STR_LIT> ) ) ) ; if ( ResVT == <STR_LIT> || ! Subtarget . hasP8Vector ( ) || cast < StoreSDNode > ( N

) -> isTruncatingStore ( ) || ! ValidTypeForStoreFltAsInt ) return SDValue ( ) ;


<s> unsigned NEONThumb2DataIPostEncoder ( const MachineInstr & MI ,


<s> FunctionPass * llvm :: create<ISA_LIT>JITCodeEmitterPass ( <ISA_LIT>BaseTargetMachine & TM , JITCodeEmitter & JCE ) { return new Emitter < JITCodeEmitter > (


<s> const SubOperator * Sub = dyn_cast < SubOperator > ( CE ) ; if ( ! Sub ) return nullptr ; const PtrToIntOperator * SubLHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; const PtrToIntOperator * SubRHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! SubLHS || ! SubRHS ) return nullptr ; if ( SubLHS -> getPointerAddressSpace ( ) != <NUM_LIT> || SubRHS -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; const auto * GOLHS = dyn_cast < GlobalObject > ( SubLHS -> getPointerOperand ( ) ) ; const auto * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ; if ( ! GOLHS || ! GVRHS ) return nullptr ; if ( GVRHS -> isThreadLocal ( ) || GVRHS -> getName ( ) != <STR_LIT> || ! GVRHS -> hasExternalLinkage ( ) || GVRHS -> hasInitializer ( ) || GVRHS -> hasSection ( ) ) return nullptr ; if ( GOLHS -> isThreadLocal ( ) ) return nullptr ; return MCSymbolRefExpr :: Create ( TM . getSymbol ( GOLHS , Mang )

, MCSymbolRefExpr :: VK_COFF_IMGREL32 , getContext ( ) ) ;


<s> assert ( m_CurrentGOTPart < m_MultipartList . size ( ) && <STR_LIT> ) ; if ( m_MultipartList [ m_CurrentGOTPart ] . isConsumed


<s> unsigned StackPtr = RegInfo . getStackRegister ( ) ; unsigned FrameDestroyOpcode = TII -> getCallFrameDestroyOpcode ( ) ; assert ( I -> getOpcode ( ) == TII -> getCallFrameSetupOpcode ( ) ) ; MachineBasicBlock :: iterator FrameSetup = I ++ ; unsigned int MaxAdjust = FrameSetup -> getOperand ( <NUM_LIT> ) . getImm ( ) / <NUM_LIT> ; if ( ! MaxAdjust ) { Context . NoStackParams = true ; return ; } while ( I -> getOpcode ( ) == <STR_LIT> ) ++ I ; if ( ! I -> isCopy ( ) || ! I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return ; Context . SPCopy = I ++ ; StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MaxAdjust > <NUM_LIT> ) Context . MovVector . resize ( MaxAdjust , nullptr ) ; InstClassification Classification ; DenseSet < unsigned int > UsedRegs ; while ( ( Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ) != Exit ) { if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp % <NUM_LIT> ) return ; StackDisp /= <NUM_LIT> ; assert ( ( size_t ) StackDisp < Context . MovVector . size ( ) && <STR_LIT> ) ; if ( Context . MovVector [ StackDisp ] != nullptr ) return ; Context . MovVector [ StackDisp


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> addMemoryWritebackIndexedOperands ( Inst , N


<s> if ( PassThru -> isUndef ( ) || isZerosVector ( PassThru . getNode ( ) ) ) return Op ; SDValue Load = DAG . getMaskedLoad ( VT , DL , LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) , LoadNode -> getOffset ( ) , Mask , DAG . getUNDEF ( VT ) , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) , LoadNode -> getAddressingMode ( ) , LoadNode -> getExtensionType ( ) ) ; SDValue Result = DAG . getSelect ( DL , VT , Mask , Load , PassThru ) ; return DAG . getMergeValues ( { Result , Load . getValue


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) , N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N1


<s> rtx rot = SET_SRC ( pat ) ; if ( GET_CODE ( rot ) == ROTATE && CONST_INT_P ( XEXP ( rot , <NUM_LIT> ) ) && INTVAL ( XEXP ( rot , <NUM_LIT> ) ) == <NUM_LIT> ) return true ; return false


<s> case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> ) { unsigned NumConstants = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned Cost = <ISA_LIT>TTI :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TCC_Basic ) ? static_cast < unsigned > ( TCC_Free ) : Cost ; } break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt

< <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ;


<s> return ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 )

|| ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf32 ) ;


<s> case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; return true ; case MachineOperand :: MO_BlockAddress : OutMO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; return true ; case MachineOperand ::


<s> const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel

( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ;


<s> continue ; } if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true


<s> if ( SDValue NewOp = combineExtractWithShuffle ( N , DAG , DCI , Subtarget ) ) return NewOp ; if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( SDValue NewOp = XFormVExtractWithShuffleIntoLoad ( N , DAG , DCI ) ) return NewOp ; SDValue InputVector = N -> getOperand ( <NUM_LIT> ) ; SDValue EltIdx = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = InputVector . getValueType ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( InputVector ) ; if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode (


<s> void setShift ( unsigned S ) { Shift =


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> return isMemDisp20 ( ADDR32Reg , false


<s> if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { mips_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false


<s> SDValue RetOps [ ] = { TF , Stores [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ; } return TF ; } assert ( SN -> isUnindexed ( ) && <STR_LIT> ) ; assert ( Value . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Ops [ ] = { StoreChain , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value , FIdx } ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; StoreChain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , <STR_LIT> , PtrInfo ) ; SDValue Loads [ <NUM_LIT> ] , LoadChains [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned Offset = <NUM_LIT> * i ; SDValue Idx = DAG . getConstant ( Offset , dl , FIdx . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , FIdx . getValueType ( ) , FIdx , Idx ) ; Loads [ i ] = DAG . getLoad ( <STR_LIT> , dl , StoreChain , Idx , PtrInfo . getWithOffset ( Offset ) ) ; LoadChains [ i ] = Loads [ i ] . getValue ( <NUM_LIT>


<s> if ( flag_stack_clash_protection ) interval = stack_clash_probe_interval ; else interval = PROBE_INTERVAL ; gcc_assert ( aarch64_uimm12_shift ( interval ) ) ; xops [ <NUM_LIT> ] = GEN_INT ( interval ) ; output_asm_insn ( <STR_LIT> , xops ) ; if ( flag_stack_clash_protection ) xops [ <NUM_LIT> ] = GEN_INT ( STACK_CLASH_CALLER_GUARD ) ; else xops [ <NUM_LIT> ] = CONST0_RTX ( GET_MODE ( xops [ <NUM_LIT> ] ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file )


<s> return __builtin_mve_vrshlq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b ,


<s> void <ISA_LIT>InstPrinter :: printCPSIMod ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand


<s> if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> SDValue <ISA_LIT>TargetLowering :: LowerSINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { MVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SrcVT . isVector ( ) ) { if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode (

<STR_LIT> , dl , IntegerVT , Op . getOperand ( <NUM_LIT> ) ) ) ;


<s> case <STR_LIT> : ConvOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( isLegalAddressImm ( ConvOpcode , OldOffset - Offset , TII ) && <STR_LIT> ) ; const MCInstrDesc & MCID = TII -> get ( ConvOpcode ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , MCID ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( OldOffset - Offset ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . cloneMemRefs ( * MI ) ; MI -> eraseFromParent


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isValidForTie ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ) ) return Match_Success ; return Match_RequiresSameSrcAndDst


<s> SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; SDValue VMask = getMaskNode ( MaskNode , <STR_LIT> ( <STR_LIT> , NumElts ) , Subtarget , DAG , DL ) ; SDValue ZeroVector = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue ExpandedVector = IsLeftZeroSide ? V2 : V1 ; return DAG . getNode ( <STR_LIT> , DL , VT , VMask , DAG . getNode

( <STR_LIT> , DL , VT , ExpandedVector ) , ZeroVector ) ;


<s> MF -> insert ( ++ MBB -> getIterator ( ) , ContBB ) ; ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( TrapBB ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TrapBB ) ; AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) .


<s> virtual const char * getPassName ( ) const { return


<s> void <ISA_LIT>_32Relocator :: convertTLSIEtoLE ( Relocation & pReloc , LDSection & pSection ) { assert ( pReloc . type ( ) == llvm :: ELF :: R_386_TLS_IE ) ; assert ( pReloc . targetRef ( ) . frag ( ) != NULL ) ; Relocation * reloc = Relocation :: Create ( <ISA_LIT>_32Relocator :: R_386_TLS_OPT , * FragmentRef :: Create ( * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) - <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( pReloc . symInfo ( ) ) ; uint8_t * op = ( reinterpret_cast < uint8_t * > ( & reloc -> target ( ) ) ) ; if ( op [ <NUM_LIT> ] == <NUM_LIT> ) { op [ <NUM_LIT> ] = <NUM_LIT> ; } else { reloc = Relocation :: Create ( <ISA_LIT>_32Relocator :: R_386_TLS_OPT , * FragmentRef :: Create ( * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) - <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( pReloc . symInfo ( ) ) ; op = ( reinterpret_cast < uint8_t * > ( & reloc -> target ( ) ) ) ; switch ( op [ <NUM_LIT> ] ) { case <NUM_LIT> : assert ( ( op [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT> ) ; op [ <NUM_LIT> ] = <NUM_LIT> ; op [ <NUM_LIT> ] = <NUM_LIT> | ( ( op [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ) ; break ; case <NUM_LIT> : assert ( ( op [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT>


<s> if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] )


<s> unsigned llvm :: get<ISA_LIT>SubSuperRegister ( unsigned Reg , unsigned Size , bool High ) { unsigned Res = get<ISA_LIT>SubSuperRegisterOrZero ( Reg , Size , High ) ; assert ( Res != <NUM_LIT> && <STR_LIT> ) ; return Res


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg

, getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ;


<s> SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , SrcVT ) ) , DAG . getConstant ( BytesLeft , SizeVT ) , Align

, isVolatile , AlwaysInline , DstSV , DstSVOff + Offset , SrcSV , SrcSVOff + Offset ) ) ;


<s> void <ISA_LIT>MCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i < Size ; ++ i


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiv16qi ( ( int8x16_t )


] , const __m128i __B [ <NUM_LIT> ] , const void * __P ) {


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( IgnoreSPUpdates ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg =


<s> else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconsthalf ) ) asm_fprintf ( f


<s> return ; } if ( mips16_cfun_returns_in_fpr_p ( ) ) mips16_copy_fpr_return_value ( ) ; frame = & cfun -> machine -> frame ; step1 = frame -> total_size ; step2 = <NUM_LIT> ; if ( ! frame_pointer_needed ) base = stack_pointer_rtx ; else { base = hard_frame_pointer_rtx ; step1 -= frame -> hard_frame_pointer_offset ; } mips_epilogue . cfa_reg = base ; mips_epilogue . cfa_offset = step1 ; mips_epilogue . cfa_restores = NULL_RTX ; if ( ( frame -> mask | frame -> fmask | frame -> acc_mask ) != <NUM_LIT> || frame -> num_cop0_regs > <NUM_LIT> ) { step2 = MIN ( step1 , MIPS_MAX_FIRST_STACK_STEP ) ; step1 -= step2 ; } adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { mips_emit_move ( MIPS_EPILOGUE_TEMP ( Pmode ) , adjust ) ; adjust = MIPS_EPILOGUE_TEMP ( Pmode ) ; } mips_deallocate_stack ( base , adjust , step2 ) ; if ( TARGET_CALL_SAVED_GP && ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; mips_epilogue . cfa_restore_sp_offset = step2 ; if ( GENERATE_MIPS16E_SAVE_RESTORE && frame -> mask != <NUM_LIT> ) { unsigned int regno , mask ; HOST_WIDE_INT offset ; rtx restore ; mask = frame -> mask ; restore = mips16e_build_save_restore ( true , & mask , & offset , <NUM_LIT> , step2 ) ; for ( regno = GP_REG_FIRST ; regno < GP_REG_LAST ; regno ++ ) if ( BITSET_P ( mask , regno - GP_REG_FIRST ) ) { offset -= UNITS_PER_WORD ; mips_save_restore_reg ( word_mode , regno , offset , mips_restore_reg ) ; } mips_frame_barrier ( ) ; emit_insn ( restore ) ; mips_epilogue_set_cfa ( stack_pointer_rtx , <NUM_LIT> ) ; } else { mips_for_each_saved_acc ( frame -> total_size - step2 , mips_restore_reg ) ; mips_for_each_saved_gpr_and_fpr ( frame -> total_size - step2 , mips_restore_reg ) ; if ( cfun -> machine -> interrupt_handler_p ) { HOST_WIDE_INT offset ; rtx mem ; offset = frame -> cop0_sp_offset - ( frame -> total_size - step2 ) ; if ( ! cfun -> machine -> keep_interrupts_masked_p ) { mem = gen_frame_mem ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; mips_emit_move ( gen_rtx_REG ( word_mode , K0_REG_NUM ) , mem ) ; offset -= UNITS_PER_WORD ; emit_insn ( gen_cop0_move ( gen_rtx_REG ( SImode , COP0_EPC_REG_NUM ) , gen_rtx_REG ( SImode


<s> bool aarch64_move_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( aarch64_movw_imm ( val , mode ) || aarch64_movw_imm (


<s> unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ,

Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ;


<s> MVT VT = Op0 . getSimpleValueType ( ) ; if ( ! ( Subtarget . hasAVX512 ( ) && VT == <STR_LIT> ) && ! ( Subtarget . hasDQI ( ) && VT == <STR_LIT> ) && ! ( Subtarget . hasBWI ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> <ISA_LIT>CC ; if ( isNullConstant ( Op1 ) ) { <ISA_LIT>CC = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( isAllOnesConstant ( Op1


<s> unsigned AdjStackDown = TM . getRegisterInfo ( ) -> getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( VA . getLocVT ( ) . isVector ( ) && VA . getLocVT ( ) . getSizeInBits ( ) > <NUM_LIT> ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { bool Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; assert ( Emitted && <STR_LIT> ) ; Emitted = Emitted ; Emitted = true ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: ZExt : { bool Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; assert ( Emitted && <STR_LIT> ) ; Emitted = Emitted ; Emitted = true ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign ::


<s> * Fast = true ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit


<s> unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSORegMemOperand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred ,


% <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ;


<s> MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , N -> getOffset ( ) , Mask , N -> getMemoryVT ( )

, N -> getMemOperand ( ) , N -> getAddressingMode ( ) , N -> isTruncatingStore ( ) , N -> isCompressingStore ( ) ) ;


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> ,


<s> bool Carry = ( Value & <NUM_LIT> ) ; Value = ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) + Carry ; if ( Value & <NUM_LIT> ) Value = Value &


<s> } int64_t Value = CE -> getValue ( ) ; MCSymbol * Sym = Ctx . createTempSymbol ( ) ; Out . emitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: createAdd ( Base , Expr , Ctx ) ; } if ( const auto * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) if ( isOutOfRangeConstant ( BE -> getLHS ( ) ) || isOutOfRangeConstant ( BE -> getRHS ( ) ) ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * Sym = nullptr ; if ( AllowTLS && getLexer ( ) . is ( AsmToken :: Colon ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; StringRef Name = Parser . getTok ( ) . getString ( ) ; if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSGD ; else if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSLDM ; else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root ,


<s> static DecodeStatus DecodesGPRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler *


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG , SDLoc dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl ,


<s> for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = I -> first ; if ( is<ISA_LIT>64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , <NUM_LIT> ) ; } } return AsmPrinter :: doFinalization ( M


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << MO2 . getImm ( ) ; } O <<


<s> MachineInstr & MI = * NextI ; bool ZeroData ; int64_t Size , Offset ; if ( isMergeableStackTaggingInstruction ( MI , Offset , Size , ZeroData ) ) { if ( ZeroData != FirstZeroData ) break ; Instrs . emplace_back ( & MI , Offset , Size ) ; continue ; } if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) break ; if ( MI . mayLoadOrStore ( ) || MI . hasUnmodeledSideEffects ( ) ) break ; } MachineBasicBlock :: iterator InsertI = Instrs . back ( ) . MI ; InsertI ++ ; llvm :: stable_sort ( Instrs , [ ] ( const TagStoreInstr & Left , const TagStoreInstr & Right ) { return Left . Offset < Right . Offset ; } ) ; int64_t CurOffset = Instrs [ <NUM_LIT> ] . Offset ; for ( auto & Instr : Instrs ) { if ( CurOffset > Instr . Offset ) return NextI ; CurOffset = Instr . Offset + Instr


<s> NumBits = <NUM_LIT> ; } else { NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned PredReg ; if ( Offset == <NUM_LIT> && getInstrPredicate ( & MI , PredReg ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; return true ; } unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( ( Offset / Scale ) & ~ Mask ) == <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Offset / Scale ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset / Scale ) ; } return true ; } unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Bytes = ( Offset > <NUM_LIT> ) ? Offset : - Offset ; unsigned NumMIs = calcNumMI ( Opcode , <NUM_LIT> , Bytes , NumBits , Scale ) ; if ( NumMIs > <NUM_LIT> ) { emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } if ( Offset > <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { MI . setDesc ( TII . get ( Opcode ) ) ; removeOperands ( MI , FrameRegIdx ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Mask ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Mask ) ; } Offset = ( Offset - Mask * Scale ) ; MachineBasicBlock :: iterator NII = llvm :: next ( II ) ; emitThumbRegPlusImmediate ( MBB , NII , dl , DestReg , DestReg ,


<s> const TargetRegisterInfo & getRegisterInfo


<s> Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Coef + <NUM_LIT> ) ; Elements . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg < <NUM_LIT> ) return None ; else if ( dwarfReg < <NUM_LIT> ) Elements . push_back ( dwarf :: DW_OP_reg0 + dwarfReg ) ; else { Elements . push_back ( dwarf :: DW_OP_regx ) ; Elements . push_back ( dwarfReg ) ; } } else if ( ! Op ) { assert ( Op2 . getReg ( ) != <STR_LIT> ) ; Op = & Op2 ; } if ( Coef > <NUM_LIT> ) { assert ( Op2 . getReg ( ) != <STR_LIT> ) ; Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Coef ) ; Elements . push_back ( dwarf :: DW_OP_mul ) ; } if ( ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) || Op1 . isFI ( ) ) && Op2 . getReg ( ) != <STR_LIT> ) { Elements . push_back ( dwarf :: DW_OP_plus ) ; } } if ( Offset < <NUM_LIT> ) { Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( - Offset ) ; Elements . push_back ( dwarf :: DW_OP_minus ) ; } else if ( Offset > <NUM_LIT> ) { Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Offset ) ; Elements . push_back ( dwarf :: DW_OP_plus ) ; } Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , Elements ) ; return ParamLoadedValue ( Op , Expr


<s> DomainValue * SSEDomainFixPass :: Alloc ( int domain ) { DomainValue * dv = Avail . empty ( ) ? new ( Allocator . Allocate ( ) ) DomainValue : Avail . pop_back_val ( ) ; dv -> Dist = Distance ; if ( domain >= <NUM_LIT> )


<s> switch ( insn . eaBase ) { case EA_BASE_NONE : llvm_unreachable ( <STR_LIT> ) ; break ; ALL_EA_BASES llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case EA_REG_ ## x : \ mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; ALL_REGS default : llvm_unreachable ( <STR_LIT>


<s> case <STR_LIT> : Cmp = IRB -> CreateICmpSGE ( LHS , RHS ) ; break ; case <STR_LIT> : Cmp = IRB -> CreateICmpSLT ( LHS , RHS ) ; break ; case <STR_LIT> : Cmp = IRB -> CreateICmpSGT ( LHS , RHS ) ; break ; case <STR_LIT> : Cmp = IRB -> CreateICmpSLE ( LHS , RHS ) ; break ; } ( dyn_cast < Instruction > ( Cmp ) ) -> setDebugLoc ( N -> getOperand ( <NUM_LIT> ) -> getDebugLoc ( ) ) ; BasicBlock * NextBB = NULL ; Function :: iterator BI = F -> begin ( ) , BE = F -> end ( ) ; while ( BI != BE && BI -> getName ( ) != CurBB -> getName ( ) ) ++ BI ; ++ BI ; if ( BI == BE ) { NextBB = Dec -> getOrCreateBasicBlock ( <STR_LIT> , F ) ; } else { NextBB = & ( * BI ) ; } Instruction * Br = IRB -> CreateCondBr ( Cmp , BBTgt , NextBB ) ; Br -> setDebugLoc ( N -> getDebugLoc ( ) ) ; return Br


<s> for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return


<s> static SDValue performSVEAndCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Src -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { SDValue UnpkOp = Src -> getOperand ( <NUM_LIT> ) ; SDValue Dup = N -> getOperand ( <NUM_LIT> ) ; if ( Dup . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Dup -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t ExtVal = C -> getZExtValue ( ) ; EVT EltTy = UnpkOp -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ; Dup = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Mask . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , UnpkOp , Dup ) ; return DAG . getNode ( Opc , DL , N -> getValueType ( <NUM_LIT> ) , And ) ; } if ( ! EnableCombineMGatherIntrinsics ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; default : return SDValue ( ) ; } if ( isConstantSplatVectorMaskForType ( Mask . getNode ( ) , MemVT ) ) return Src ; return SDValue ( )


elt_mode ( elt_mode_in ) , insn ( PTRUE ) {


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &


<s> return __builtin_mve_vhsubq_n_sv8hi ( __a ,


<s> ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ; if ( ZextOffs ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; FixedVectorType * OffsetType = cast < FixedVectorType > ( Offsets -> getType ( ) ) ; if ( ! ZextOffs || cast < FixedVectorType > ( ZextOffs -> getDestTy ( ) ) -> getElementType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) if ( ! checkOffsetSize ( Offsets , OffsetsElemCount ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getElementType ( ) -> getScalarSizeInBits ( ) < OffsetType -> getElementType ( ) -> getScalarSizeInBits ( ) ) ) { Offsets = Builder . CreateTrunc


<s> MInstToMCSymbol :: iterator LabelIt = LOHInstToLabel . find ( MI ) ; assert ( LabelIt != LOHInstToLabel . end ( ) && <STR_LIT> ) ; MCArgs . push_back ( LabelIt -> second ) ; } OutStreamer -> emitLOHDirective ( D . getKind (


<s> Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; unsigned LoadOpc = <STR_LIT> ; if ( SrcVT == <STR_LIT> ) { if ( ! IsSigned ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( Subtarget -> hasLFIWAX ( ) ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; } } const TargetRegisterClass * RC


<s> static void aarch64_conditional_register_usage ( void ) { int i ; if ( ! TARGET_FLOAT ) { for ( i = V0_REGNUM ; i <= V31_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ]


<s> CondReg = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , CondReg ) ; CondReg = DAG . getCopyFromReg ( CondReg , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CondReg , Cst ) ; Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Xor = DAG . getNode ( <STR_LIT> , dl


<s> <ISA_LIT>PostLegalizerCombiner :: <ISA_LIT>PostLegalizerCombiner ( bool IsOptNone ) : MachineFunctionPass ( ID ) , IsOptNone ( IsOptNone


<s> static bool matchShuffleWithSHUFPD ( MVT VT , SDValue & V1 , SDValue & V2 , unsigned & ShuffleImm , ArrayRef < int > Mask ) { int NumElts = VT . getVectorNumElements ( ) ; assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; ShuffleImm = <NUM_LIT> ; bool ShufpdMask = true ; bool CommutableMask = true ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( Mask [ i ] == SM_SentinelUndef ) continue ; if ( Mask [ i ] < <NUM_LIT> ) return false ; int Val = ( i & <NUM_LIT> ) + NumElts * ( i & <NUM_LIT> ) ; int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i ] > Val + <NUM_LIT> ) ShufpdMask = false ; if ( Mask [ i ] < CommutVal || Mask [ i ] > CommutVal + <NUM_LIT> )


<s> return rs6000_mode_dependent_address_ptr ( addr


<s> SignBits [ i ] = DAG . ComputeNumSignBits ( Opd ) ; IsPositive [ i ] = DAG . SignBitIsZero ( Opd ) ; } bool AllPositive = IsPositive [ <NUM_LIT> ] && IsPositive [ <NUM_LIT> ] ; unsigned MinSignBits = std :: min ( SignBits [ <NUM_LIT> ] , SignBits [ <NUM_LIT> ] ) ; if ( MinSignBits >= <NUM_LIT> )


<s> if ( isZExtFree ( VT1 , VT2 ) ) { return true ; } if ( Val . getOpcode ( ) != <STR_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ; unsigned NumSubElts = SplitSize / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT ,


<s> AddPromotedToType ( <STR_LIT> , VT , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , <STR_LIT> ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT ,


<s> return ( ! Is64BitMode || TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) && TM

. getSubtarget < <ISA_LIT>Subtarget > ( ) . GVRequiresExtraLoad ( GV , TM , false ) ;


<s> for ( i = <NUM_LIT> ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ <NUM_LIT> ] ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; high = l [ WORDS_BIG_ENDIAN == <NUM_LIT> ] ; low = l [ WORDS_BIG_ENDIAN != <NUM_LIT> ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high )


<s> OptForMinSize = MF -> getFunction ( ) -> optForMinSize ( ) ; assert ( ( ! OptForMinSize || OptForSize ) && <STR_LIT> ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || ! getTargetMachine ( ) . isPositionIndependent ( ) ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT>


<s> if ( TREE_CODE ( TREE_TYPE ( node ) ) == METHOD_TYPE && ( DECL_CONSTRUCTOR_P ( node ) || DECL_DESTRUCTOR_P ( node ) ) ) { tree overload ; for ( overload = OVL_CHAIN ( node ) ; overload ; overload = OVL_CHAIN ( overload ) ) { tree node_args ; tree func_args ; tree function = OVL_CURRENT ( overload ) ; if ( ! function || ! DECL_P ( function ) || ( DECL_CONSTRUCTOR_P ( node ) && ! DECL_CONSTRUCTOR_P ( function ) ) || ( DECL_DESTRUCTOR_P ( node ) && ! DECL_DESTRUCTOR_P ( function ) ) ) continue ; for ( node_args = DECL_ARGUMENTS ( node ) , func_args = DECL_ARGUMENTS ( function ) ; node_args && func_args ; node_args = TREE_CHAIN ( node_args ) , func_args = TREE_CHAIN ( func_args ) ) if ( TREE_TYPE ( node_args ) != TREE_TYPE ( func_args ) ) break ; if ( node_args || func_args ) { if ( ( node_args == NULL_TREE || func_args != NULL_TREE ) && strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( node ) ) , <STR_LIT> ) != <NUM_LIT> ) continue ; } symbian_add_attribute ( function , attr ) ; for ( thunk = DECL_THUNKS ( function ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) if ( TREE_CODE ( thunk ) == FUNCTION_DECL ) symbian_add_attribute ( thunk , attr ) ; } } if ( TREE_CODE ( node ) == FUNCTION_DECL && DECL_VIRTUAL_P ( node ) ) { for ( thunk = DECL_THUNKS ( node ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) if ( TREE_CODE ( thunk ) == FUNCTION_DECL ) symbian_add_attribute ( thunk , attr ) ; } if ( ! TREE_PUBLIC ( node ) && ( TREE_CODE ( node ) == VAR_DECL || TREE_CODE ( node ) == FUNCTION_DECL ) ) { error ( <STR_LIT> , node , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true


<s> vld1q_p16 ( const poly16_t * __a ) { return ( poly16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi * )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } else if ( Name . equals_insensitive ( <STR_LIT> ) ) { SM . onAnd ( ) ; } else if ( Name . equals_insensitive ( <STR_LIT> ) ) { SM . onMod ( ) ; } else if ( Name . equals_insensitive ( <STR_LIT> ) ) { SMLoc OffsetLoc = getTok ( ) . getLoc ( ) ; const MCExpr * Val = nullptr ; StringRef ID ; InlineAsmIdentifierInfo Info ; ParseError = ParseIntelOffsetOperator ( Val , ID , Info , End ) ; if ( ParseError ) return true ; StringRef ErrMsg ; ParseError = SM . onOffset ( Val , OffsetLoc , ID , Info , isParsingMSInlineAsm ( ) , ErrMsg ) ; if ( ParseError ) return Error ( SMLoc :: getFromPointer ( Name . data ( ) ) , ErrMsg ) ; } else { return false ; } if ( ! Name . equals_insensitive ( <STR_LIT> ) ) End = consumeToken (


<s> Value * <ISA_LIT>IREmitter :: visitFOR ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( UseCycle < <NUM_LIT> ) UseCycle = <NUM_LIT> ; UseCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { UseCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || UseAlign < <NUM_LIT> ) ++ UseCycle ; }


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; return getAddr ( N


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> SDValue Pg = getPredicateForVector ( DAG , DL , RoundVT ) ; Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , RoundVT , Pg , Val , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( RoundVT ) ) ; Val = getSVESafeBitCast ( ContainerSrcVT . changeTypeToInteger ( ) , Val , DAG ) ; Val = convertFromScalableVector ( DAG , SrcVT . changeTypeToInteger ( ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Val ) ; return DAG . getNode ( <STR_LIT> , DL , VT


create<ISA_LIT>AvoidTrailingCallPass ( ) {


<s> Type * VecEltTy = MaskTy -> getVectorElementType ( ) ; if ( ! VecEltTy -> isIntegerTy ( ) ) return ; unsigned EltTySize = VecEltTy -> getIntegerBitWidth ( ) ; if ( EltTySize < <NUM_LIT> || EltTySize > ElSize ) return ; unsigned NumElements = MaskTySize / ElSize ; assert ( ( NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> ) && <STR_LIT> ) ; ShuffleMask . reserve ( NumElements ) ; unsigned NumElementsPerLane = <NUM_LIT> / ElSize ; unsigned Factor = ElSize / EltTySize ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { Constant * COp = C -> getAggregateElement ( i * Factor ) ; if ( ! COp ) { ShuffleMask . clear ( ) ; return ; } else if ( isa < UndefValue > (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthVectorIntDivideToSVE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; bool Signed = Op . getOpcode ( ) == <STR_LIT> ; unsigned PredOpcode = Signed ? <STR_LIT> : <STR_LIT> ; bool Negated ; uint64_t SplatVal ; if ( Signed && isPow2Splat ( Op . getOperand ( <NUM_LIT> ) , SplatVal , Negated ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getTargetConstant ( Log2_64 ( SplatVal ) , dl , <STR_LIT> ) ; SDValue Pg = getPredicateForFixedLengthVector ( DAG , dl , VT ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , ContainerVT , Pg , Op1 , Op2 ) ; if ( Negated ) Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , Res ) ; return convertFromScalableVector ( DAG , VT , Res ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return LowerToPredicatedOp ( Op , DAG , PredOpcode , true ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT FixedWidenedVT = HalfVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; EVT ScalableWidenedVT = getContainerForFixedLengthVector ( DAG , FixedWidenedVT ) ; EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT


<s> if ( ( flags & ( ISA_2_6_MASKS_SERVER & ~ ISA_2_5_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_5_MASKS_SERVER & ~ ISA_2_4_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_4_MASKS & ~ ISA_2_1_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ISA_2_1_MASKS ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & OPTION_MASK_POWERPC64 ) != <NUM_LIT> ) return <STR_LIT> ; return


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> ,

<STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> unsigned <STR_LIT> ( SDNode * N , unsigned EltSize , SelectionDAG & DAG ) { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode


<s> return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) )


<s> { assert ( ! TRI -> hasBasePointer ( MF ) && <STR_LIT> ) ; int TailCallReturnAddrDelta = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) ; assert ( ! ( TailCallReturnAddrDelta <


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT>


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , true ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HADDBuilder ) ; } if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT


<s> if ( ! Val ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm (


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU


<s> return __builtin_ia32_mulph512_mask_round ( __A , __B , _mm512_setzero_ph ( ) , (


<s> bool isConstantImm ( ) const { int64_t


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val


<s> bool <ISA_LIT>SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < <NUM_LIT> > ( MFI . getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && !


<s> static void rs6000_free_sched_context ( void * _sc ) { gcc_assert ( _sc !=


<s> MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Base . isReg ( ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( Base ) ; return Reg ; } Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> )

, Reg ) . add ( Base ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> data . regbase = regbase ; data . nregs = <NUM_LIT> ; data . intoffset = <NUM_LIT> ; data . stack = false ; traverse_record_type < assign_data_t , count_registers > ( type , named , & data ) ; if ( compute_int_layout ( size * BITS_PER_UNIT , & data , & nregs ) ) data . nregs += nregs ; nregs = data . nregs ; if ( nregs == <NUM_LIT> ) { if ( size <= <NUM_LIT> ) { return gen_rtx_REG ( mode , regbase ) ; } nregs = CEIL_NWORDS ( size ) ; if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs > <NUM_LIT> ) ; data . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( data . stack + nregs ) ) ; if ( data . stack ) XVECEXP ( data . ret , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; data . nregs = <NUM_LIT> ; data . intoffset = <NUM_LIT> ; traverse_record_type < assign_data_t , assign_registers > ( type , named , & data ) ; assign_int_registers ( size * BITS_PER_UNIT , & data ) ; gcc_assert ( data . nregs == nregs ) ; return data .


<s> BaseReg = ScratchReg ; BaseRegOffsetBytes = <NUM_LIT> ; } MachineInstr * LastI = nullptr ; while ( Size ) { int64_t InstrSize = ( Size > <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Opcode = InstrSize == <NUM_LIT> ? ( ZeroData ? <STR_LIT> : <STR_LIT> ) : ( ZeroData ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * I = BuildMI ( * MBB , InsertI , DL , TII -> get ( Opcode ) ) . addReg ( <STR_LIT> ) . addReg ( BaseReg ) . addImm ( BaseRegOffsetBytes / <NUM_LIT> ) . setMemRefs ( CombinedMemRefs ) ; if ( BaseRegOffsetBytes == <NUM_LIT> ) LastI = I ; BaseRegOffsetBytes += InstrSize


<s> static bool IsVUZPShuffleNode ( SDNode * N ) { if ( N -> getOpcode ( ) == <STR_LIT> ) return


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI ->


<s> MachineFunction * MF = C . getMF ( ) ; const TargetRegisterInfo & TRI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( & TRI ) ; for ( unsigned Reg : <STR_LIT> ) { if ( ! ARI -> isReservedReg ( * MF , Reg ) && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && C . isAvailableAcrossAndOutOfSeq ( Reg , TRI ) && C . isAvailableInsideSeq ( Reg ,


<s> int <ISA_LIT>TTIImpl :: getScatterOverhead ( )


<s> void <ISA_LIT>InstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) const { switch ( Pattern ) { case MachineCombinerPattern :: REASSOC_XY_AMM_BMM : case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM


<s> const Align NewAlignment = max ( MaybeAlign ( Info . AI -> getAlign ( ) ) , kTagGranuleSize ) ; Info . AI -> setAlignment ( NewAlignment ) ; uint64_t Size = Info . AI -> getAllocationSizeInBits ( * DL ) . getValue ( ) / <NUM_LIT> ; uint64_t AlignedSize = alignTo ( Size , kTagGranuleSize ) ; if ( Size == AlignedSize ) return ; Type * AllocatedType = Info . AI -> isArrayAllocation ( ) ? ArrayType :: get ( Info . AI -> getAllocatedType ( ) , cast < ConstantInt > ( Info . AI -> getArraySize ( ) ) -> getZExtValue ( ) ) : Info . AI -> getAllocatedType ( ) ; Type * PaddingType = ArrayType :: get ( Type :: getInt8Ty ( F -> getContext ( ) ) , AlignedSize - Size ) ; Type * TypeWithPadding = StructType :: get ( AllocatedType , PaddingType ) ; auto * NewAI = new AllocaInst ( TypeWithPadding , Info . AI -> getType ( ) -> getAddressSpace ( ) , nullptr , <STR_LIT> , Info . AI ) ; NewAI -> takeName ( Info . AI


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; assert ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> && Offset < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( - Offset ) ; } else if ( Offset < <NUM_LIT> ) { MI . setDesc ( TII -> get ( getRegOpForImmOpVariant ( MI . getOpcode ( ) ) ) ) ; unsigned Reg = MRI . createVirtualRegister ( &


<s> AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; AddDefaultPred ( MIB ) ; if ( DestReg == <STR_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT>

) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ; } while ( I -> isDebugValue ( ) ) ; ITBlockMIs [ ITBlockSize - <NUM_LIT> - i ] = & * I ; } } if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; Stalls = <NUM_LIT> ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> void addImm0_65535Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> )


<s> const <ISA_LIT>Subtarget & getSubTarget (


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int32_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta , true ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ; const TargetFrameLowering & TFI = * MF . getTarget ( ) . getFrameLowering ( ) ; int FrameIdx = MFI -> CreateFixedObject ( SlotSize , - ( int ) SlotSize + TFI . getOffsetOfLocalArea ( ) + TailCallReturnAddrDelta , true ) ; assert ( FrameIdx == MFI ->

getObjectIndexBegin ( ) && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned TF = MO . getTargetFlags ( ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : if ( TF == <STR_LIT> ) O << <STR_LIT> << * Mang -> getSymbol ( MO . getGlobal ( ) ) << <STR_LIT> ; else O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ExternalSymbol : if ( TF == <STR_LIT> ) O << <STR_LIT> << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) << <STR_LIT> ; else O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; default : llvm_unreachable ( <STR_LIT>


<s> virtual unsigned getTTypeEncoding ( ) const { return DW_EH_PE_indirect | DW_EH_PE_pcrel |


<s> if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { if ( ! MBB . isLiveIn ( ABI . GetEhDataReg ( I ) ) ) MBB . addLiveIn ( ABI . GetEhDataReg ( I ) ) ; TII . storeRegToStackSlot ( MBB , MBBI , ABI . GetEhDataReg ( I ) , false , <ISA_LIT>FI -> getEhDataRegFI ( I ) , RC , & RegInfo ) ; } for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( <ISA_LIT>FI -> getEhDataRegFI ( I ) ) ; unsigned Reg = MRI -> getDwarfRegNum ( ABI . GetEhDataReg ( I ) , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MOVE ) , FP ) . addReg ( SP ) . addReg ( ZERO ) . setMIFlag ( MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , MRI -> getDwarfRegNum ( FP , true ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( RegInfo . needsStackRealignment ( MF ) ) { unsigned VR = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( isInt < <NUM_LIT> > ( MFI . getMaxAlignment ( ) ) && <STR_LIT> ) ; int MaxAlign = - ( int ) MFI . getMaxAlignment ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , VR ) . addReg ( ZERO ) . addImm ( MaxAlign ) ; BuildMI ( MBB , MBBI , dl , TII . get ( AND ) , SP ) . addReg (


<s> tree cur_tree , new_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , <NUM_LIT> , sizeof ( func_options_set )


<s> return ( __m512i ) __builtin_ia32_cvtps2dq512_mask ( ( __v16sf ) __A , ( __v16si ) _mm512_undefined_si512 ( ) , ( __mmask16 )


<s> Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_Shuffle ( m_Instruction ( Insert ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElt ( m_Undef ( ) , m_Instruction ( BECount


<s> MachineInstr * CPEMI = U . CPEMI ; unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * NewMBB ; unsigned UserOffset = GetOffsetOf ( UserMI ) + ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = MF . CreateMachineBasicBlock ( ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland


<s> if ( Pmode != ptr_mode ) mem = gen_rtx_SIGN_EXTEND (


<s> aapcs_cp_arg_layout [ pcum -> aapcs_cprc_slot ] . advance ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = - <NUM_LIT> ; } pcum -> aapcs_arg_processed = false ; pcum -> aapcs_ncrn = pcum -> aapcs_next_ncrn ; pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_partial = <NUM_LIT> ; } else { pcum -> nargs += <NUM_LIT> ; if ( arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs && TARGET_IWMMXT_ABI ) pcum -> iwmmxt_nregs += <NUM_LIT> ; else pcum -> nregs += ARM_NUM_REGS2


<s> bool isAddrMode2 ( ) const { if ( ! isMem ( ) || Memory . Alignment !=


<s> static inline __ev64_opaque__ __internal_ev_mwhgssfaa ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhssf ( a , b ) ; return __ev_mwsmiaa ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> }


<s> return ( int64x1_t ) __builtin_neon_vreinterpretdidi (


<s> sysctlbyname ( <STR_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; l1_sizekb = <NUM_LIT>


<s> struct ix86_frame & frame = cfun -> machine -> frame ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM

) return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ;


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer )


<s> assert ( HintNum != <NUM_LIT> && <STR_LIT> ) ; auto MBBI = MBB . begin ( ) ; if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) return ; BuildMI ( MBB , MBB . begin ( ) , MBB . findDebugLoc ( MBB . begin ( ) ) , TII -> get ( <STR_LIT> )


<s> inline const MachineInstrBuilder & addRegOffset ( const MachineInstrBuilder & MIB , unsigned Reg ,


<s> void addMemoryIndexed16Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && isMemoryIndexed16 ( ) &&


<s> do_range = true ; } else if ( type == CPP_NAME || type == CPP_STRING ) { const char * str ; unsigned int regno , i ; if ( TREE_CODE ( val ) == IDENTIFIER_NODE ) str = IDENTIFIER_POINTER ( val ) ; else if ( TREE_CODE ( val ) == STRING_CST ) str = TREE_STRING_POINTER ( val ) ; else gcc_unreachable ( ) ; regno = parse_cr_reg ( str ) ; if ( regno == INVALID_REGNUM ) { error ( <STR_LIT> , val ) ; return false ; } if ( do_range ) { if ( last_regno > regno ) i = regno ,


<s> static unsigned getReg ( const void * D ,


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectVSplat ( SDNode * N , APInt & Imm ) const { if ( ! Subtarget . hasMSA ( ) ) return false ; BuildVectorSDNode * Node = dyn_cast < BuildVectorSDNode > ( N ) ; if ( Node == NULL ) return false ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) ) return false ; if ( ! SplatValue . isIntN ( <NUM_LIT> ) ) return false ; Imm = SplatValue ; return


<s> VectorType * SubVecTy = VectorType :: get ( EltTy , LaneLen ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = dyn_cast < VectorType > ( Op0 -> getType ( ) ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ]


<s> RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , array_lengthof ( PopTable ) , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> ) I -> RemoveOperand ( <NUM_LIT> ) ; } else


<s> if ( ! C ) return false ; return AllOnes ? C -> isAllOnesValue ( ) : C -> isNullValue (


<s> } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; O <<


<s> return __builtin_aarch64_lroundusfsi ( __a )


<s> SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueOp = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseOp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; unsigned CCValid , CCMask ; SDValue Flags = emitCmp ( TM , DAG , DL , CmpOp0 , CmpOp1 , CC , CCValid , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCValid , <STR_LIT> ) ) ; Ops . push_back ( DAG . getConstant ( CCMask , <STR_LIT> ) ) ; Ops . push_back ( Flags ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( )


<s> N -> getMask ( M ) ; return :: isPSHUFHWMask ( M , N ->


<s> static SDValue detectAVX512USatPattern ( SDValue In , EVT VT , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! isSATValidOnAVX512Subtarget ( In . getValueType ( ) , VT , Subtarget


<s> case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS ) ; SDValue SetCC = getSETCC ( <STR_LIT> , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) , DL , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Sum , SetCC ) ; } } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; SDValue SetCC = getSETCC ( Cond , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) , DL , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList


<s> void printU16ImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CommentString =


<s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ,


<s> EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty ,


<s> HasADX = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PostRAScheduler = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG =


<s> uint64_t SlotSize = TD -> getPointerSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy (


<s> if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } ++ FilledSlots ; Changed = true ; continue ; } } if ( ( InMicro<ISA_LIT>Mode || ( STI . has<ISA_LIT>32r6 ( ) && <ISA_LIT>CompactBranchPolicy != CB_Never ) ) && TII -> getEquivalentCompactForm ( I ) ) { I = replaceWithCompactBranch ( MBB , I , I -> getDebugLoc ( ) ) ; Changed = true ; continue ; } LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE << <STR_LIT> ; I -> dump ( ) ) ; TII -> insertNop ( MBB , std :: next ( I ) , I -> getDebugLoc (


<s> fprintf ( asm_out_file , <STR_LIT> ) ; need_copy_state = <NUM_LIT> ; } fprintf ( asm_out_file , <STR_LIT>


<s> tree fntype = rs6000_builtin_info [ inst -> bifid ] . fntype ; tree parmtype0 = TREE_VALUE ( TYPE_ARG_TYPES ( fntype ) ) ; tree parmtype1 = TREE_VALUE ( TREE_CHAIN ( TYPE_ARG_TYPES ( fntype ) ) ) ; if ( rs6000_builtin_type_compatible ( types [ <NUM_LIT> ] , parmtype0 ) && rs6000_builtin_type_compatible (


<s> if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( ! SrcOpMap . empty ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt EltCount = APInt :: getNullValue ( NumElts ) ; M = SrcOpMap . insert ( std :: make_pair ( Src , EltCount ) ) . first ; SrcOps . push_back ( Src ) ; } unsigned CIdx = Idx -> getZExtValue ( ) ; if ( M -> second [ CIdx ] ) return false ; M -> second . setBit ( CIdx ) ; } if ( SrcMask ) { for ( SDValue & SrcOp : SrcOps ) SrcMask -> push_back ( SrcOpMap [ SrcOp ] ) ; } else { for ( DenseMap < SDValue , APInt > :: const_iterator I = SrcOpMap . begin ( ) , E = SrcOpMap . end ( ) ; I != E ; ++ I ) { if ( ! I -> second . isAllOnesValue


<s> return __builtin_neon_vrecpsv8hf ( __a ,


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7F ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ; } if ( TheTriple . isOSBinFormatCOFF ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT )


<s> bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; if ( ! NoNanDirective ) STI . isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t Reserved<ISA_LIT>Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I <

array_lengthof ( Reserved<ISA_LIT>Regs ) ; ++ I ) {


<s> if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> setScavengingFrameIndex (


<s> unsigned uid = TYPE_UID ( TYPE_MAIN_VARIANT ( type ) ) ; int alt ; if ( ! silent_p && warn_psabi && warn_psabi_flags && uid != last_reported_type_uid && ( ( alt = aapcs_vfp_sub_candidate ( type , & new_mode , NULL ) ) != ag_count ) ) { const char * url = CHANGES_ROOT_URL <STR_LIT> ; gcc_assert ( alt == - <NUM_LIT> ) ; last_reported_type_uid = uid ; if ( warn_psabi_flags & WARN_PSABI_NO_UNIQUE_ADDRESS ) inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url ) ; else if ( warn_psabi_flags & WARN_PSABI_EMPTY_CXX17_BASE ) inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url ) ; } if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; } else return false ; } else return false ; gcc_assert ( ! aarch64_sve_mode_p ( new_mode ) ) ; * base_mode =


<s> ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) ==


<s> Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OpCode = ( JMP64r << <NUM_LIT> ) | REX_WB ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; unsigned char ModRM = N86R11 | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( ModRM , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; } else { const Function * Func = cast < Function > ( cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) ; CallingConv :: ID CC = Func -> getCallingConv ( ) ; unsigned NestReg ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: <ISA_LIT>_StdCall : { NestReg = <STR_LIT> ; FunctionType * FTy = Func -> getFunctionType ( ) ; const AttributeSet & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount


<s> return __builtin_loongson_packsshb ( s


<s> __builtin_mve_vstrbq_p_sv4si ( ( __builtin_neon_qi * ) __addr ,


<s> static rtx ia64_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return ia64_function_arg_1 ( cum , arg ,


<s> switch ( MI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l'


<s> static bool isPostIncrementForm ( const MCInst * MI , int AddOffset ) { unsigned AluCode = MI -> getOperand ( <NUM_LIT> )


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> : if ( Subtarget -> hasV6T2Ops ( ) ) emitMOVi32immInstruction ( MI ) ; else emitMOVi2piecesInstruction ( MI ) ; break ; case <STR_LIT> : emitLEApcrelJTInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitPseudoMoveInstruction ( MI )


<s> static void emitNonLazySymbolPointer ( MCStreamer & OutStreamer , MCSymbol * StubLabel , MachineModuleInfoImpl :: StubValueTy & MCSym ) { OutStreamer . emitLabel ( StubLabel ) ; OutStreamer . emitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . emitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) ,

OutStreamer . getContext ( ) ) , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetStreamer :: emitInst ( uint32_t Inst ) { char Buffer [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I


<s> if ( ShiftVal . uge ( Tmp ) ) return <NUM_LIT> ; return Tmp - ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p = strchr (

p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \ RS6000_OUTPUT_BASENAME ( FILE , buffer ) ; \ putc ( '\n' , FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI


<s> static int mips_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( mips_cost -> memory_latency + memory_move_secondary_cost ( mode


<s> static SDValue getBuildVectorSplat ( EVT VecTy , SDValue SplatValue , bool BigEndian , SelectionDAG & DAG ) { EVT ViaVecTy = VecTy ; SDValue SplatValueA = SplatValue ; SDValue SplatValueB = SplatValue ; SDLoc DL ( SplatValue ) ; if ( VecTy == <STR_LIT> ) { ViaVecTy = <STR_LIT> ; SplatValueA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValueB ) ; } if ( BigEndian ) std :: swap ( SplatValueA , SplatValueB ) ; SDValue Ops [ <NUM_LIT> ] = { SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , Ops , ViaVecTy . getVectorNumElements (


<s> if ( ! isMem ( ) || Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; assert ( CE && <STR_LIT> ) ; int64_t Value = CE -> getValue ( ) ; return ( ( Value % <NUM_LIT> ) == <NUM_LIT> ) && Value


<s> arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_simd_floatHF_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; enum machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; arm_simd_intOI_type_node = AARCH_BUILD_SIGNED_TYPE ( OImode ) ; arm_simd_intEI_type_node = AARCH_BUILD_SIGNED_TYPE ( EImode ) ; arm_simd_intCI_type_node = AARCH_BUILD_SIGNED_TYPE ( CImode ) ; arm_simd_intXI_type_node = AARCH_BUILD_SIGNED_TYPE ( XImode ) ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intEI_type_node ) ; TYPE_NAME ( arm_simd_intEI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intOI_type_node ) ; TYPE_NAME ( arm_simd_intOI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intCI_type_node ) ; TYPE_NAME ( arm_simd_intCI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intXI_type_node ) ; TYPE_NAME ( arm_simd_intXI_type_node ) =


<s> static SDValue getLegalSplat ( SelectionDAG & DAG , SDValue V , int EltNo ) { MVT VT = V . getSimpleValueType ( ) ; SDLoc dl ( V ) ; if ( VT . is128BitVector ( ) ) { V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else if ( VT . is256BitVector ( ) ) { int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> } ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT>


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI


<s> bool <ISA_LIT>RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int &


<s> unsigned TaggedReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int FI = I -> getOperand ( <NUM_LIT> ) . getIndex


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer (

MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ;