<s> assert ( Target . getSymA ( ) -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP && ! is64Bit ( ) && <STR_LIT> ) ; unsigned Log2Size = getFixupKindLog2Size ( Fixup . getKind ( ) ) ; uint32_t Value = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = <NUM_LIT> ; if ( Target . getSymB ( ) ) { uint32_t FixupAddress = Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) ; IsPCRel = <NUM_LIT> ; FixedValue = FixupAddress - Writer -> getSymbolAddress ( Target . getSymB ( ) -> getSymbol ( ) , Layout ) + Target . getConstant ( ) ; FixedValue += <NUM_LIT> << Log2Size ; } else { FixedValue = <NUM_LIT> ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = Value ; MRE . r_word1 = ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT>

) | ( MachO :: GENERIC_RELOC_TLV << <NUM_LIT> ) ;


<s> OS << <STR_LIT> << Reg << <STR_LIT> <<


<s> return <NUM_LIT> ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( GET_CODE ( y ) != REG ) break ; if ( REGNO ( y ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return <NUM_LIT> ; } case SET : return regs_used ( SET_SRC ( x ) , <NUM_LIT> ) | regs_used ( SET_DEST ( x ) , <NUM_LIT> ) ; case RETURN : return <NUM_LIT> ; case CLOBBER : is_dest = <NUM_LIT> ; break ; case MEM


<s> bool applyAdjustICmpImmAndPred ( MachineInstr & MI , std :: pair < uint64_t , CmpInst :: Predicate > & MatchInfo , MachineIRBuilder & MIB , GISelChangeObserver & Observer ) { MIB . setInstrAndDebugLoc ( MI ) ; MachineOperand & RHS = MI . getOperand ( <NUM_LIT> ) ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; auto Cst = MIB . buildConstant ( MRI . cloneVirtualRegister ( RHS . getReg ( ) ) , MatchInfo . first ) ; Observer . changingInstr ( MI ) ; RHS . setReg ( Cst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( MatchInfo . second ) ; Observer . changedInstr ( MI


<s> inline SDValue getSmallIPtrImm ( unsigned Imm


<s> fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT>


<s> static unsigned getInt64Count ( int64_t Imm ) { unsigned Count = getInt64CountDirect ( Imm ) ; if ( Count == <NUM_LIT> ) return Count ; for ( unsigned r = <NUM_LIT> ; r < <NUM_LIT> ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = getInt64CountDirect ( RImm ) + <NUM_LIT> ; Count = std :: min


<s> bool isU10Imm ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > (


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , false ) , DataLayout ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> : ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( )


<s> inline void <ISA_LIT>EncodeLiteralsPass :: buildXor ( MachineInstr & MI , unsigned Index , uint64_t Operand ) { MachineBasicBlock * PMBB = MI . getParent ( ) ; MachineBasicBlock :: instr_iterator Iter = skip ( PMBB , Index ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned XOROpc = getXorOpc ( MI ) ; addRegOffset ( BuildMI ( * PMBB , Iter , MI . getDebugLoc ( ) , TII -> get ( XOROpc ) )

, <STR_LIT> , true , Offset ) . addImm ( Operand ) ;


<s> inline static <STR_LIT> A64StringToCondCode ( StringRef CondStr ) { return StringSwitch < <STR_LIT> > ( CondStr . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT>

, <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> case CmpInst :: ICMP_UGE : case CmpInst :: ICMP_ULT : case CmpInst


<s> DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue LHS , RHS ; if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * Op010C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) if ( Op010C -> getZExtValue ( ) == <NUM_LIT> ) { LHS = Op0 . getOperand ( <NUM_LIT> ) ; RHS = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } } else if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * Op000C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) if ( Op000C -> getZExtValue ( ) == <NUM_LIT> ) { LHS = Op0 . getOperand ( <NUM_LIT> ) ; RHS = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } } else if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ; SDValue AndLHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( AndRHS -> getZExtValue ( ) == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & TheTriple ) { if ( ( TheTriple . getArch ( ) == Triple :: armeb ) || ( TheTriple . getArch ( )

== Triple :: thumbeb ) ) IsLittleEndian = false ;


<s> return ( __m256d ) __builtin_ia32_vpermilpd256_mask ( ( __v4df ) __X , __C , ( __v4df ) _mm256_setzero_pd ( ) ,


<s> auto PTy = cast < PointerType > ( LI -> getPointerOperand ( ) -> getType ( ) ) ; return needsCmpXchgNb ( PTy ->


<s> return isRegIdx ( ) && RegIdx . Kind

& RegKind_CheriHWRegs && RegIdx . Index <= <NUM_LIT> ;


<s> int64_t getExprCRVal ( ) const { assert ( Kind == Expression && <STR_LIT> ) ; return Expr .


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: CreateUpper16 ( Expr , OutContext ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_<ISA_LIT>_PLT , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr

, MCConstantExpr :: Create ( MO . getOffset ( ) , OutContext ) , OutContext ) ;


<s> Asm -> getOrCreateSymbolData ( * Symbol


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return <ISA_LIT>CondCodeToVal ( static_cast < <STR_LIT> > ( getMachineOpValue (


<s> } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; NewMI -> copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , * MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 ( ) || STI -> isTargetNaCl64 ( ) ; unsigned StackPtr = TRI -> getStackRegister ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstrBuilder MIB ; if ( StackAdj == <NUM_LIT> ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; } else if ( isUInt < <NUM_LIT> > ( StackAdj ) ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) . addImm ( StackAdj ) ; }


<s> int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , * A , FixedValue ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue


<s> return ( __m256i ) __builtin_ia32_vpdpbssds256 ( ( __v8si ) __W ,


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) { FrameReg =


<s> } unsigned Reg = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; uint32_t Binary ; Binary = Imm12 & <NUM_LIT> ; if ( Imm12 >= <NUM_LIT> ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg << <NUM_LIT>


<s> Error ( Tok . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT>


<s> SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>CC2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT ,

Result , TrueVal , <ISA_LIT>CC2 , CCR , Cmp2 ) ;


<s> SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( VT . getScalarType ( ) == <STR_LIT> ) { assert ( VT . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ; } else llvm_unreachable ( <STR_LIT> )


<s> EVT TargetVT = Extend -> getValueType ( <NUM_LIT> ) ; unsigned ExtendOpcode = Extend -> getOpcode ( ) ; SDLoc DL ( Extend ) ; EVT VT = CMovN . getValueType ( ) ; SDValue CMovOp0 = CMovN . getOperand ( <NUM_LIT> ) ; SDValue CMovOp1 = CMovN . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( CMovOp0 . getNode ( ) ) || ! isa < ConstantSDNode > ( CMovOp1 . getNode ( ) ) ) return SDValue ( ) ; if ( TargetVT != <STR_LIT> && TargetVT != <STR_LIT> ) return SDValue ( ) ; if ( VT != <STR_LIT> && ! ( ExtendOpcode == <STR_LIT> && VT == <STR_LIT> ) ) return SDValue ( ) ; EVT ExtendVT = TargetVT ; if ( TargetVT == <STR_LIT> && ExtendOpcode != <STR_LIT> ) ExtendVT = <STR_LIT> ; CMovOp0 = DAG . getNode ( ExtendOpcode , DL , ExtendVT , CMovOp0 ) ; CMovOp1 = DAG . getNode ( ExtendOpcode , DL , ExtendVT , CMovOp1 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , ExtendVT , CMovOp0 , CMovOp1 , CMovN . getOperand ( <NUM_LIT> ) , CMovN . getOperand ( <NUM_LIT> ) ) ; if ( ExtendVT != TargetVT ) Res = DAG . getNode ( ExtendOpcode , DL ,


<s> static inline uint32_t helper_reencode_branch_offset_26 ( uint32_t pInst , uint32_t pOff ) { return ( pInst & ~ get_mask ( <NUM_LIT> ) ) | ( pOff & get_mask ( <NUM_LIT>


<s> <STR_LIT> CC = <STR_LIT> ( MI ) ; if ( CC == <STR_LIT> ) return JumpKind :: Invalid ; switch ( CC ) { default : return JumpKind :: Invalid ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return JumpKind :: ELG ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return JumpKind :: AB ; case <STR_LIT> : case


<s> if ( Memory . BaseRegNum == <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ; } return


<s> void <ISA_LIT>RegisterInfo :: lowerVRSAVERestore ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) &&


<s> if ( getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) && MatchRegisterName ( Parser . getTok ( ) . getString ( ) ) ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; if ( ParseRegister ( RegNo , StartLoc , EndLoc


<s> void <ISA_LIT>AsmParser :: cvtVSTwbRegister ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAlignedMemoryOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addVecListOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> const MCExpr * AdjExpr = MCConstantExpr :: Create ( PCAdjustment , Ctx ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , AdjExpr , Ctx ) ; } const MachineOperand & MOImm = MI -> getOperand ( ImmIndex ) ; MCOperand SymOp ; bool DidLower = AP . lowerOperand ( MOImm , SymOp ) ; assert ( DidLower && <STR_LIT> ) ; const MCExpr * Expr = SymOp . getExpr ( ) ; <ISA_LIT>MCExpr :: VariantKind TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( Expr -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * TargetExpr = cast <


<s> static std :: string computeDataLayout ( const Triple & TT ) { return <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT>


<s> if ( decl == NULL ) return true ; return targetm . binds_local_p ( decl )


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; SDLoc DL ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned Flag = ( model == TLSModel :: LocalDynamic ) ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , Flag ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; unsigned PtrSize = PtrVT . getSizeInBits ( ) ; IntegerType * PtrTy = Type :: getIntNTy ( * DAG . getContext ( ) , PtrSize ) ; SDValue TlsGetAddr = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = PtrTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , PtrTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , TlsGetAddr , Args , DAG , DL ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT


<s> bool isUImm8Shift16 ( ) { return isUImm < <NUM_LIT> , <NUM_LIT>


<s> bool threewayBranchProfitable ( ) const { return ThreewayBranchProfitable


<s> return __builtin_ia32_vcvtph2psx512_mask_round ( __B , _mm512_setzero_ps ( ) ,


<s> if ( sh == <NUM_LIT> ) code = ROTATE ; if ( code == ROTATE && sh >= <NUM_LIT> && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= <NUM_LIT> && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> ) ; if ( ne > nb ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> && ! ( code == LSHIFTRT

&& nb >= <NUM_LIT> - sh ) ) return true ;


<s> MachineInstr * MI1 = Arguments -> MI ; MachineInstr * MI2 = & * NextMII ; Register RegDstMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegSrcMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! IsMovepSrcRegister ( RegSrcMI1 ) ) return false ; if ( ! IsMovepDestinationReg ( RegDstMI1 ) ) return false ; if ( MI2 -> getOpcode ( ) != Entry


<s> if ( DisableMemAluCombiner ) return false ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) { Modified |= combineMemAluInBasicBlock ( & * MFI


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; break ; } return false


<s> branch_island bi = { function_name ,


<s> emit_insn ( gen_rtx_SET ( VOIDmode , tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ <NUM_LIT> ] , tmp , operands [ <NUM_LIT> ] ) ) ; return true ; } xops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xops [ <NUM_LIT> ] = xops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xops [ <NUM_LIT> ] = xops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ <NUM_LIT> ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ia64_expand_vecint_cmov (


<s> static SDValue GetTLSADDR ( SelectionDAG & DAG , SDValue Chain , GlobalAddressSDNode * GA , SDValue * InFlag , const EVT PtrVT , unsigned ReturnReg , unsigned char OperandFlags , bool LocalDynamic = false ) { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } MFI -> setAdjustsStack ( true ) ; MFI -> setHasCalls (


<s> case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ I ] . OrigArgIndex ; assert ( Ins [ I ] . PartOffset == <NUM_LIT> ) ; while ( I + <NUM_LIT> != E && Ins [ I + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ I + <NUM_LIT> ] ; unsigned PartOffset = Ins [ I + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ I ; } } else InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = - <STR_LIT> + TFL -> getRegSpillOffset ( MF , <STR_LIT> ) - <NUM_LIT> ; unsigned RegSaveIndex = MFI . CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> && ! useSoftFloat ( ) ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( MF , <STR_LIT> [ I ] ) ; int FI = MFI . CreateFixedObject ( <NUM_LIT> , - <STR_LIT> + Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout


<s> static SDValue combineSelectOfTwoConstants ( SDNode * N , SelectionDAG & DAG ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( LHS ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! TrueC || ! FalseC ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Cond . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt & TrueVal = TrueC -> getAPIntValue ( ) ; const APInt & FalseVal = FalseC -> getAPIntValue ( ) ; bool OV ; APInt Diff = TrueVal . ssub_ov ( FalseVal , OV ) ; if ( OV ) return SDValue ( ) ; APInt AbsDiff = Diff . abs ( ) ; if ( AbsDiff . isPowerOf2 ( ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ( AbsDiff == <NUM_LIT> || AbsDiff == <NUM_LIT> || AbsDiff == <NUM_LIT> ) ) ) { if ( TrueVal . slt ( FalseVal ) ) { Cond = DAG . getNOT ( DL , Cond , <STR_LIT> ) ; std :: swap ( TrueC , FalseC ) ; } SDValue R = DAG . getNode ( <STR_LIT> , DL , VT , Cond ) ; if ( ! AbsDiff . isOne ( ) ) R = DAG . getNode ( <STR_LIT> , DL , VT , R , DAG . getConstant


<s> DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg


<s> rtx legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx orig_x = x ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) , XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( x != orig_x && legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) ) x


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return createMachOStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return createWinCOFFStreamer

( Ctx , MAB , * _Emitter , _OS , RelaxAll ) ;


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Tok = Parser . getTok ( ) . getIdentifier ( ) ; if ( Tok [ <NUM_LIT> ] != 'c' && Tok [ <NUM_LIT> ] != 'C' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> )


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI -> getRegClass (

Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ;


<s> EVT VT = getPointerTy ( ) ; OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , NULL , <NUM_LIT>


<s> STI . setDefaultFeatures ( <STR_LIT> , ( <STR_LIT> + <STR_LIT> ( ID ) ) . str ( ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; FixModeAfterArchChange ( WasThumb , L ) ; getTargetStreamer ( ) . emitArch (


<s> uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI . getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset +


<s> return <NUM_LIT> ; } else if ( FBB == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( int i = <NUM_LIT> , e = Cond . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Cond [ i ] ) ; MIB . addMBB ( TBB ) ; return <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( int i = <NUM_LIT> , e = Cond . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Cond [ i ] ) ; MIB . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) .


<s> uint32_t RemainingSize = Flags . getByValSize ( ) ; unsigned ByValAlign = Flags . getByValAlign ( ) ; for ( ; RemainingSize >= <NUM_LIT> && LocMemOffset < <NUM_LIT> * <NUM_LIT> ; Offset += <NUM_LIT> , RemainingSize -= <NUM_LIT> , LocMemOffset += <NUM_LIT> ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; SDValue LoadVal = DAG . getLoad ( <STR_LIT> , dl , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned DstReg = O32IntRegs [ LocMemOffset / <NUM_LIT> ] ; RegsToPass . push_back ( std :: make_pair ( DstReg , LoadVal ) ) ; } if ( RemainingSize == <NUM_LIT> ) return ; if ( LocMemOffset < <NUM_LIT> * <NUM_LIT> ) { assert ( RemainingSize <= <NUM_LIT> && RemainingSize >= <NUM_LIT> && <STR_LIT> ) ; unsigned LoadSize = ( RemainingSize == <NUM_LIT> ? <NUM_LIT> : RemainingSize ) ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Alignment = std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; if ( ! isLittle ) LoadVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant ( <NUM_LIT> - LoadSize * <NUM_LIT> , <STR_LIT> ) ) ; Offset += LoadSize ; RemainingSize -= LoadSize ; if ( RemainingSize !=


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 <


<s> uint64_t HalfTySize = HalfTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) / <NUM_LIT> ; Align Alignment = std :: min ( Lo -> getAlign ( ) , Align ( HalfTySize ) ) ; Builder . CreateAlignedStore ( Lo , HalfPtr , Alignment , ST -> isVolatile ( ) ) ; HalfPtr = Builder . CreateGEP ( HalfTy , HalfPtr , Builder . getInt32 ( <NUM_LIT> ) ) ; Builder . CreateAlignedStore ( Hi , HalfPtr , Alignment , ST ->


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> if ( ! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5 ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( TARGET_SHMEDIA ) n_floatregs = <NUM_LIT> ; bufsize = ( n_intregs * UNITS_PER_WORD ) + ( n_floatregs * UNITS_PER_WORD ) ; if ( TARGET_SHMEDIA ) regbuf = gen_frame_mem ( BLKmode , gen_rtx_REG ( Pmode , ARG_POINTER_REGNUM ) ) ; else if ( n_floatregs & <NUM_LIT> ) { rtx addr ; regbuf = assign_stack_local ( BLKmode , bufsize + UNITS_PER_WORD , <NUM_LIT> ) ; addr = copy_to_mode_reg ( Pmode , XEXP ( regbuf , <NUM_LIT> ) ) ; emit_insn ( gen_iorsi3 ( addr , addr , GEN_INT ( UNITS_PER_WORD ) ) ) ; regbuf = change_address ( regbuf , BLKmode , addr ) ; } else if ( STACK_BOUNDARY < <NUM_LIT> && TARGET_FPU_DOUBLE && n_floatregs ) { rtx addr , mask ; regbuf = assign_stack_local ( BLKmode , bufsize + UNITS_PER_WORD , <NUM_LIT> ) ; addr = copy_to_mode_reg ( Pmode , plus_constant ( XEXP ( regbuf , <NUM_LIT> ) , <NUM_LIT> ) ) ; mask = copy_to_mode_reg ( Pmode , GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( addr , addr , mask ) ) ; regbuf = change_address ( regbuf , BLKmode , addr ) ; } else regbuf = assign_stack_local ( BLKmode , bufsize , TARGET_FPU_DOUBLE ? <NUM_LIT> : <NUM_LIT> ) ; alias_set = get_varargs_alias_set ( ) ; set_mem_alias_set ( regbuf , alias_set ) ; if ( n_intregs > <NUM_LIT> ) move_block_from_reg ( BASE_ARG_REG ( SImode ) + first_intreg , adjust_address ( regbuf , BLKmode , n_floatregs * UNITS_PER_WORD ) , n_intregs ) ; if ( TARGET_SHMEDIA ) return XEXP (


<s> static SDValue LowerPredicateLoad ( SDValue Op , SelectionDAG & DAG ) { LoadSDNode * LD = cast < LoadSDNode > ( Op . getNode ( ) ) ; EVT MemVT = LD -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == Op . getValueType ( ) ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG .

getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ;


<s> O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ; O << <STR_LIT> << getFunctionNumber (


<s> } switch_to_section ( bss_section ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , MAX ( size ,


<s> if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return getGlobalBaseReg (


<s> tgt <<= <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( tgt + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: createImm ( tgt ) ) ; return MCDisassembler


<s> JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastMI ) ) ; createPHIsForSelects ( MIItBegin , MIItEnd , StartMBB ,


<s> const TargetMachine & TM = MF . getTarget ( ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ( Subtarget . isABI_FPXX ( ) && ! Subtarget . hasMTHC1 ( ) ) || ( FP64 && ! Subtarget . useOddSPReg ( ) ) ) { const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & TRI = * static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; const TargetRegisterClass * RC2 = FP64 ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC2 ) ; TII . storeRegToStack ( MBB , I , LoReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . storeRegToStack ( MBB , I , HiReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg ,


<s> if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , WordSize ) ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC


<s> if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode ( I -> getOpcode ( ) ) : getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB ; if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } ( void )


<s> bool <ISA_LIT>MachineFunctionInfo :: globalBaseRegSet


<s> APInt Mask = WidenedDemandedElts . getBitsSet ( NumElts , I , I + Scale ) ; APInt MaskedDE = Mask & WidenedDemandedElts ; unsigned Population = MaskedDE . countPopulation ( ) ; Cost += ( Population > <NUM_LIT> && Population != Scale && I % LT . second . getVectorNumElements ( ) != <NUM_LIT> ) ; Cost += Population > <NUM_LIT> ; } Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == <STR_LIT> ) for ( unsigned i = <NUM_LIT> , e = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; i < e ; i += <NUM_LIT> ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( cast < FixedVectorType > (


<s> else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( ( CONST_INT_P ( xop1 ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> __o = __builtin_aarch64_ld2rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregoiv16qi (


<s> uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) & <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( encoding


<s> lowerBRCOND ( SDValue Op , SelectionDAG


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>MCAsmStreamer :: EmitValueWithAlignment ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { const char * Directive = nullptr ; switch ( Size ) { default : break ; case <NUM_LIT> : Directive = MAI -> getData8bitsDirective ( ) ; break ; case <NUM_LIT> : Directive = MAI -> getData16bitsDirective (


<s> Inst . addOperand ( MCOperand :: CreateReg ( FGR32RegsTable [ RegNo ] ) ) ; return MCDisassembler :: Success


<s> assert ( ( Compare . getOpcode ( ) == <STR_LIT> || Compare . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( Compare . getOpcode ( ) == <STR_LIT> ) && ! allUsesExtend ( Compare , CurDAG ) ) return SDValue ( ) ; SDValue LHS = Compare . getOperand ( <NUM_LIT> ) ; SDValue RHS = Compare . getOperand ( <NUM_LIT> ) ; int CCOpNum = Compare . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> CC = cast < CondCodeSDNode > ( Compare . getOperand ( CCOpNum ) ) -> get ( ) ; EVT InputVT = LHS . getValueType ( ) ; if ( InputVT != <STR_LIT> && InputVT != <STR_LIT> )


<s> const MCSymbolRefExpr & refExp = cast < MCSymbolRefExpr > ( * MO . getExpr ( ) ) ; switch ( refExp . getKind ( ) ) { case MCSymbolRefExpr :: VK_TLSGD : O << <STR_LIT> ; break ; case MCSymbolRefExpr


<s> return ( ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) ||

( Op . isImm ( ) && Op . getImm ( ) == <NUM_LIT> ) ) ;


<s> if ( ! tryAddingSymbolicOperand ( Insn + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: createImm ( Insn ) ) ; return MCDisassembler :: Success


<s> Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S


<s> const uint16_t * table = lookup ( MI . getOpcode ( ) , dom ) ; if ( ! table ) { assert ( ( Subtarget . hasAVX2 ( ) || Domain < <NUM_LIT> ) &&


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( )


<s> bool hasNEON ( ) const { return HasNEON


<s> Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value . getValue ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Value = Value . getValue ( <NUM_LIT> ) ; break ; case <STR_LIT> : <ISA_LIT>cc = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op . getValueType ( ) , Op . getValueType ( ) ) , LHS , RHS ) ; OverflowCmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value . getValue ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( )

, Value . getValue ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ) ;


<s> return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc =


<s> if ( code == PRE_MODIFY || code == POST_MODIFY ) * offset = addr . offset ; else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= <NUM_LIT> ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ; * offset = addr


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MBBI ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; llvm :: finalizeBundle ( MBB , NewMI , *


<s> rtx gen_pop ( rtx arg ) { if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( arg , gen_rtx_MEM ( word_mode , gen_rtx_POST_INC ( Pmode ,


<s> return __builtin_mve_vcmpeqq_n_v4si ( __a ,


<s> bool <ISA_LIT>Subtarget :: isAAPCS_ABI ( ) const { assert ( TM . TargetABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_UNKNOWN ) ; return TM . TargetABI ==


<s> int <ISA_LIT>BaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const { if ( ! DefNode -> isMachineOpcode ( ) ) return <NUM_LIT> ; const TargetInstrDesc & DefTID = get ( DefNode -> getMachineOpcode ( ) ) ; if ( isZeroCost ( DefTID . Opcode ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; else return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } return Latency


<s> unsigned xorv = ( i >= nelt / <NUM_LIT> && i < <NUM_LIT> * nelt / <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ which ] [ ( i * eltsz + j ) ^ xorv ] = GEN_INT ( e * eltsz + j ) ; rperm [ <NUM_LIT> - which ] [ ( i * eltsz + j ) ^ xorv ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( l , op , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; h = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op1


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG ,


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( )


<s> if ( Nd . getMemoryVT ( ) != <STR_LIT> || ! NoDPLoadStore ) return <ISA_LIT>TargetLowering :: lowerSTORE ( Op , DAG ) ; SDLoc DL ( Op ) ; SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,

Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( SDValue BlendOp = lowerVSELECTtoVectorShuffle ( Op , Subtarget , DAG ) ) return BlendOp ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) return Op ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX (


<s> MCContext & Ctx = AP . OutContext ; bool isDarwin = TM . getTargetTriple ( ) . isOSDarwin ( ) ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym .


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat (


<s> const char * getPassName ( ) const override { return


<s> if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB , AddrReg ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getPointerSize ( ) , Align ) ; MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return ResultReg ; } addConstantPoolReference ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg )


<s> BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MI -> eraseFromParent ( ) ; MadeChange = true ; } } return


<s> bool readTPHard ( ) const { return ReadTPHard


<s> if ( ! I . isPHI ( ) ) break ; unsigned HeadReg = <NUM_LIT> , CmpBBReg = <NUM_LIT> ; for ( unsigned oi = <NUM_LIT> , oe = I . getNumOperands ( ) ; oi != oe ; oi += <NUM_LIT> ) { MachineBasicBlock * MBB = I . getOperand ( oi + <NUM_LIT> ) . getMBB ( ) ; unsigned Reg = I . getOperand ( oi ) . getReg ( ) ; if ( MBB == Head ) { assert ( ( ! HeadReg || HeadReg == Reg ) && <STR_LIT> ) ; HeadReg = Reg ; } if ( MBB ==


<s> if ( ThisRLAmt == LastRLAmt && ThisValue == LastValue ) continue ; if ( LastValue . getNode ( ) ) BitGroups . push_back ( BitGroup ( LastValue , LastRLAmt , LastGroupStartIdx , i - <NUM_LIT> ) ) ; LastRLAmt = ThisRLAmt ; LastValue = ThisValue ; LastGroupStartIdx = i ; } if ( LastValue . getNode ( ) ) BitGroups . push_back ( BitGroup ( LastValue , LastRLAmt , LastGroupStartIdx , Bits . size ( ) - <NUM_LIT> ) ) ; if ( BitGroups . empty ( ) ) return ; if ( BitGroups . size ( ) > <NUM_LIT> ) { if ( BitGroups [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . EndIdx == Bits . size ( ) - <NUM_LIT> && BitGroups [ <NUM_LIT> ] . V == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . V && BitGroups [ <NUM_LIT> ] . RLAmt == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . RLAmt ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] .

EndIdx = BitGroups [ <NUM_LIT> ] . EndIdx ;


<s> for ( unsigned I = <NUM_LIT> , E = Filler -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = Filler -> getOperand ( I ) ; unsigned R ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! ( R = MO . getReg ( ) ) ) continue ; const MachineFunction & MF = * MBB . getParent (


<s> } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; Module * M = MF . getFunction ( ) . getParent ( ) ; const GlobalValue * GV = cast < GlobalValue > ( M -> getNamedValue ( ThunkIt -> Name ) ) ; MachineInstr * BL = isThumb ? BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( IndirectCall . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( IndirectCall . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addGlobalAddress ( GV ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( GV ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> removeOperand ( FirstOpIdxToRemove ) ; BL -> removeOperand


<s> static __inline __m64 _mm_addbhusm_pu8 ( __m64 a , __m64 b ) { return ( __m64 ) __builtin_arm_waddbhusm ( ( __v4hi ) a ,


<s> unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm (

( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && C ) return Op ; if ( Subtarget . hasP9Vector ( ) ) { if ( ( VT == <STR_LIT> ) && ( V2 . getValueType ( ) == <STR_LIT> ) && ( isa < LoadSDNode > ( V2 ) ) ) { SDValue BitcastVector = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue BitcastLoad = DAG . getBitcast (


<s> addMemoryRegisterOffsetOperands ( Inst , N , Mem . ShiftVal


<s> SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 ; if ( ! SelectAddr ( In1 , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 ) ) return NULL ; SDValue LSI = Node -> getOperand


<s> NumElts = RegVT . getVectorNumElements ( ) ; SubregIdx = ( Lane < NumElts ) ? <STR_LIT> : <STR_LIT> ; } unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( MemUpdate ) ; Ops . push_back ( MemOpc ) ; Ops . push_back ( Align ) ; unsigned Opc = <NUM_LIT> ; if ( is64BitVector ) { Opc = DOpcodes [ OpcodeIndex ] ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( N -> getOperand ( Vec + <NUM_LIT> ) ) ; } else { if ( Lane < NumElts ) { Opc = QOpcodes0 [ OpcodeIndex ] ; } else { Lane -= NumElts ; Opc = QOpcodes1 [ OpcodeIndex ] ; } for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( CurDAG -> getTargetExtractSubreg ( SubregIdx , dl , RegVT , N -> getOperand ( Vec + <NUM_LIT> ) ) ) ; } Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( PredReg ) ; Ops . push_back ( Chain ) ; if ( ! IsLoad ) return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , NumVecs + <NUM_LIT> ) ; std :: vector < EVT > ResTys ( NumVecs , RegVT ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , NumVecs + <NUM_LIT> ) ; if ( is64BitVector ) return VLdLn ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) { SDValue QuadVec = CurDAG -> getTargetInsertSubreg ( SubregIdx , dl , VT , N ->

getOperand ( Vec + <NUM_LIT> ) , SDValue ( VLdLn , Vec ) ) ;


<s> if ( getSubtarget ( ) . hasV8Ops ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> )


<s> static bool isVectorAllOnes ( SDValue N ) { if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N ) ; if ( ! BVN )


<s> static const int INSTR_DISTANCE_THRESHOLD = <NUM_LIT> ; CurInst = I ; bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I != CurInst ) { if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD ) break ; if ( usesRegister ( p , CurInst ) == RU_Write ) { return CurInst ; } InstrDistance += TII -> getInstrLatency ( MF -> getSubtarget ( ) . getInstrItineraryData (


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; MVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( DestVT . bitsGT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ; } return


<s> if ( MBB . succ_empty ( ) && Probability < BranchProbability ( <NUM_LIT>


<s> const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask ,


<s> if ( Kind == k_Register ) return Reg


<s> O << <STR_LIT> ; printSuffixedName ( p , <STR_LIT> ) ; O << <STR_LIT> ; } else O << <STR_LIT> ; SwitchToDataSection ( <STR_LIT> , <NUM_LIT> ) ; printSuffixedName ( p , <STR_LIT> ) ; O << <STR_LIT> ; O << <STR_LIT> << p << <STR_LIT> ; O << <STR_LIT> ; } O << <STR_LIT> ; if ( ! GVNonLazyPtrs . empty ( ) ) { SwitchToDataSection ( <STR_LIT> , <NUM_LIT> ) ; for ( StringSet < > :: iterator i = GVNonLazyPtrs . begin ( ) , e = GVNonLazyPtrs . end ( ) ; i != e ; ++ i ) { const char * p = i -> getKeyData ( ) ; printSuffixedName ( p , <STR_LIT> ) ; O << <STR_LIT> ; O << <STR_LIT> << p << <STR_LIT> ; O << <STR_LIT> ; } } if ( ! HiddenGVNonLazyPtrs . empty ( ) ) { SwitchToSection ( TAI -> getDataSection ( ) ) ; for ( StringSet < > :: iterator i = HiddenGVNonLazyPtrs . begin ( ) , e = HiddenGVNonLazyPtrs . end ( ) ; i !=


<s> const MachineOperand * BaseOp ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , OffsetIsScalable , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect


<s> emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes


<s> CodeModel :: Model CM = TM . getCodeModel ( ) ; if ( CM != CodeModel :: Large && ! Subtarget -> useSmallAddressing ( ) ) return false ; if ( CM == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing ( ) ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( )


<s> prescanForConstants ( ) ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; return true


<s> switch ( Directive ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> || ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else return Error ( Loc , <STR_LIT> ) ; Parser . Lex ( ) ; Amount = <NUM_LIT> ; if ( St != <STR_LIT> ) { Loc = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) && HashTok . isNot ( AsmToken :: Dollar ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * Expr ; if ( getParser ( ) . ParseExpression ( Expr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } if ( save_fp ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } if ( save_gp ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } if ( save_lp ) { reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } offset = - ( num_use_regs * <NUM_LIT> ) ; adjust_sp_rtx = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = <NUM_LIT> ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = <NUM_LIT>


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ) { EncodedValue &=


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , { } ) ; if ( DestReg == DescribedReg ) return ParamLoadedValue ( MachineOperand :: CreateReg ( SrcReg , false ) , Expr ) ; if ( unsigned SubRegIdx = TRI -> getSubRegIndex ( DestReg , DescribedReg ) ) { Register SrcSubReg = TRI -> getSubReg (


<s> Value * <ISA_LIT>IREmitter :: visitMOVDDUP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned NumLoBits = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; Known . Zero . setBitsFrom ( NumLoBits ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( SrcVT . getVectorNumElements ( ) , Op . getConstantOperandVal ( <NUM_LIT> ) ) ; DAG . computeKnownBits ( Src , Known , DemandedElt , Depth + <NUM_LIT> ) ; Known = Known . zextOrTrunc ( BitWidth ) ; Known . Zero . setBitsFrom ( SrcVT . getScalarSizeInBits ( ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) { Known . setAllZero ( ) ; break ; } DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , DemandedElts , Depth + <NUM_LIT> ) ; unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; if ( Opc == <STR_LIT> ) { Known . Zero <<= ShAmt ; Known . One <<= ShAmt ; Known . Zero . setLowBits ( ShAmt ) ; } else { Known . Zero . lshrInPlace ( ShAmt ) ; Known . One . lshrInPlace


<s> void thumb_expand_epilogue ( ) { HOST_WIDE_INT amount = ( get_frame_size ( ) + current_function_outgoing_args_size ) ; if ( IS_NAKED ( arm_current_func_type ( ) ) ) return ; if ( frame_pointer_needed ) emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; else if ( amount ) { amount = ROUND_UP ( amount ) ; if ( amount < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { rtx reg = gen_rtx ( REG , SImode , LAST_ARG_REGNUM ) ; emit_insn ( gen_movsi ( reg , GEN_INT ( amount ) ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx ,


<s> assert ( dv && <STR_LIT> ) ; dv -> clear (


<s> SMLoc getEndLoc ( ) const { return EndLoc


<s> break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA .


<s> if ( InSVT == <STR_LIT> ) return SDValue ( ) ; if ( InSVT == <STR_LIT> && ( OutSVT == <STR_LIT> || ! Subtarget . hasSSE41 ( ) || Subtarget . hasInt256 ( ) ) ) return SDValue ( ) ; } SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , DL , Subtarget , DAG ) ; return SDValue (


<s> void <ISA_LIT>TargetStreamer :: emitGPRestore ( int Offset , SMLoc IDLoc , const MCSubtargetInfo * STI ) { emitLoadWithImmOffset ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Offset ,


<s> int num_saves = XVECLEN ( parallel_op , <NUM_LIT> ) ; if ( TARGET_ARM ) return <NUM_LIT> ; if ( TARGET_THUMB1 ) return <NUM_LIT> ; regno = REGNO ( first_op ) ; hi_reg = ( REGNO_REG_CLASS ( regno ) == HI_REGS ) && ( regno != LR_REGNUM ) ; for ( i = <NUM_LIT> ; i < num_saves


<s> std :: for_each ( MBB . rbegin ( ) , ( MachineBasicBlock :: reverse_iterator ) CallInsertionPt , [ & LRU ] ( MachineInstr & MI ) { LRU . stepBackward ( MI ) ; } ) ; return LRU . available


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder ,


<s> SmallSet < unsigned , <NUM_LIT> > Defs ; for ( const MachineOperand & MO : CPSRDef -> operands ( ) ) { if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isUse ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> || Reg == <STR_LIT> ) continue ; Defs . insert ( Reg ) ; } for ( const MachineOperand & MO : Use -> operands ( )


<s> else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( addr ) == REG ) ; return addr


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , true


<s> int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base ; if ( isUndefInRange ( Mask , <NUM_LIT> , Idx ) ) { } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , <NUM_LIT> ) ) { Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else { continue ; } if ( ! Base ) Base = DAG . getUNDEF ( VT ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Base , Insert , DAG . getConstant ( BitLen ,


<s> if ( LoadInst * LMemI = dyn_cast < LoadInst > ( MemI ) ) { return LMemI -> getPointerOperand ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( MemI ) ) { return SMemI -> getPointerOperand ( ) ; } else if ( IntrinsicInst * IMemI = dyn_cast < IntrinsicInst > ( MemI ) ) { if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> || IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI -> getArgOperand ( <NUM_LIT> ) ; if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI -> getArgOperand (


<s> store_reg ( i , offset , HARD_FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } gr_saved ++ ; } else { offset = local_fsize - actual_fsize ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , regno , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( regno , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_or_fixed_reg_p ( i ) ) { if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , i , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } if ( merge_sp_adjust_with_store ) set_reg_plus_d ( STACK_POINTER_REGNUM , STACK_POINTER_REGNUM , actual_fsize , <NUM_LIT> ) ; } if ( flag_pic && actual_fsize != <NUM_LIT> && ! TARGET_64BIT ) { rtx addr = gen_rtx_PLUS ( word_mode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( word_mode , addr ) , pic_offset_table_rtx ) ; } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { rtx base ; if ( frame_pointer_needed ) { set_reg_plus_d ( <NUM_LIT> , HARD_FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = hard_frame_pointer_rtx ; } else { set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = stack_pointer_rtx ; } for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) { if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { rtx addr , reg ; rtx_insn * insn ; addr = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC ( word_mode , tmpreg ) ) ; reg = gen_rtx_REG ( DFmode , i ) ; insn = emit_move_insn ( addr , reg ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( TARGET_64BIT ) { rtx mem = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } else { rtx meml = gen_rtx_MEM ( SFmode , plus_constant ( Pmode ,


<s> BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , SubRegCopy ) . addUse ( CopyReg , <NUM_LIT> , SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( SubRegCopy ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * To , MRI ) ; return true


<s> if ( const Function * F = dyn_cast < Function > ( GO ) ) if ( TM . getSubtarget <

<ISA_LIT>Subtarget > ( * F ) . genExecuteOnly ( ) && SK . isText ( ) ) return true ;


<s> void add<ISA_LIT>SOImmNotOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr >


<s> void AnalyzeReturn ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn ) { PreAnalyzeReturn ( Outs , Fn )


<s> virtual void EmitValueImpl ( const MCExpr * Value , unsigned Size , const SMLoc & Loc ) { EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; unsigned OpIdx = <NUM_LIT> ; if ( MCID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI ,


<s> for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { llvm :: MachineBasicBlock :: iterator cmpInst = NULL ; llvm :: MachineBasicBlock :: iterator nextInst = NULL ; unsigned int reg1 = <NUM_LIT> ; unsigned int reg2 = <NUM_LIT> ; for ( llvm :: MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) { cmpInst = I ; nextInst = std :: next ( cmpInst ) ; if ( cmpInst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) reg1 = cmpInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( cmpInst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) reg2


<s> if ( ! STI . isThumb2 ( ) || ! STI . hasLOB ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; MRI = & Fn . getRegInfo ( ) ; MachineLoopInfo * MLI = & getAnalysis < MachineLoopInfo > ( ) ; MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineLoop * ML : MLI -> getBase ( ) . getLoopsInPreorder ( ) ) { Modified |= MergeLoopEnd ( ML ) ; Modified |= ConvertTailPredLoop ( ML


<s> ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> && Base != <STR_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return nullptr ; bool KillOldBase = BaseKill && ( ! isi32Store ( Opcode ) || ! ContainsReg ( Regs , Base ) ) ; if ( isThumb1 ) { if ( Base != NewBase && ( BaseOpc == <STR_LIT> || BaseOpc == <STR_LIT> ) ) { if ( is<ISA_LIT>LowRegister ( NewBase ) && is<ISA_LIT>LowRegister ( Base ) && ! STI -> hasV6Ops ( ) ) { if ( Pred != <STR_LIT> ) return nullptr ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . add ( predOps ( Pred , PredReg ) ) ; Base = NewBase ; KillOldBase = true ; } if ( BaseOpc == <STR_LIT> ) { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset / <NUM_LIT> ) . add ( predOps ( Pred , PredReg ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . add ( t1CondCodeOp ( true ) ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) ; } else { BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) ; } Base = NewBase ; BaseKill = true ; } bool isDef = isLoadSingle ( Opcode ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode , Mode ) ; if ( ! Opcode ) return nullptr ; if ( isThumb1 && ! SafeToClobberCPSR && Writeback && ! BaseKill ) return nullptr ; MachineInstrBuilder MIB ; if ( Writeback ) { assert ( isThumb1 && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { assert ( ! ( ContainsReg ( Regs , Base ) ) && <STR_LIT> ) ; Opcode = <STR_LIT> ; } MIB = BuildMI ( MBB , InsertBefore , DL


<s> if ( VT . isFloatingPoint ( ) ) { assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type :: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ; else Const = ConstantFP :: get ( Type :: getDoubleTy ( C ) , Val . bitsToDouble ( ) ) ; } else Const = Constant :: getIntegerValue ( Type ::


<s> BuildMI ( testMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( StackPtr ) . addReg ( FinalStackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( testMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; testMBB -> addSuccessor ( testMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; tailMBB -> splice ( tailMBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; tailMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( testMBB ) ; if ( Offset % StackProbeSize ) { BuildMI ( * tailMBB , tailMBB -> begin ( ) , DL , TII . get ( TargetOpcode :: COPY ) , StackPtr ) . addReg ( FinalStackPtr )


<s> bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( ( isHReg ( DestReg ) || isHReg ( SrcReg ) ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) { Opc = <STR_LIT> ; assert ( <STR_LIT> . contains ( SrcReg , DestReg ) && <STR_LIT> ) ; } else Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else Opc = CopyToFromAsymmetricReg ( DestReg , SrcReg , HasAVX ) ; if ( Opc ) { BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( SrcReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL ,


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; const uint16_t * SubReg = TM . getRegisterInfo ( ) -> getSubRegisters (


<s> static SDValue LowerBuildVectorv8i16 ( SDValue Op , unsigned NonZeros , unsigned NumNonZero , unsigned NumZero , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( NumNonZero > <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; return LowerBuildVectorAsInsert ( Op , NonZeros , NumNonZero , NumZero , DAG ,


<s> } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; return BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) . addImm ( <NUM_LIT> - Size

) . addImm ( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


<s> bool IsPop = isPopOpcode ( MI -> getOpcode ( ) ) ; bool IsPush = isPushOpcode ( MI -> getOpcode ( ) ) ; if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI


<s> case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetDsp ( ) ; break ; case <STR_LIT> : getTargetStreamer ( ) . emitDirectiveSetMicro<ISA_LIT> ( ) ; break ; case <STR_LIT> : getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>16 ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> ,


<s> bool isITMask ( ) const { return Kind == k_ITCondMask


<s> if ( MO . isGlobal ( ) ) return isGVStub ( MO . getGlobal ( ) , TM ) ; if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex ( ) ; return MFI . isFixedObjectIndex ( Idx ) && MFI . isImmutableObjectIndex ( Idx ) ; } } return false


<s> llvm_unreachable ( <STR_LIT> ) ; } return Res ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: Create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) && ( VK == MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI || VK == MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) ) { if ( VK == MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) return <ISA_LIT>MCExpr :: CreateHi ( Expr , getContext ( ) ) ; return <ISA_LIT>MCExpr :: CreateLo ( Expr , getContext ( ) ) ; } const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , RelocStr ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , RelocStr ) ; Res = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ; return Res ; } if ( const MCUnaryExpr * UN = dyn_cast < MCUnaryExpr > ( Expr ) ) { const MCExpr * UnExp = evaluateRelocExpr ( UN -> getSubExpr ( ) , RelocStr ) ; Res = MCUnaryExpr :: Create ( UN -> getOpcode ( ) , UnExp , getContext ( ) ) ; return


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; Register FPReg = <STR_LIT> ; Register SPReg = <STR_LIT> ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( hasFramePointer ) StackSize ++ ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFramePointer ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm (


<s> return ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl

) ) ? DECL_CONTEXT ( decl ) : NULL_TREE ) ;


<s> Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) MOs . push_back (


<s> case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) )


<s> switch ( mode ) { case QImode : return V16QImode ; case HImode : return V8HImode ; case SImode : return V4SImode ; case


<s> Align getStackAlignment ( ) const { return stackAlignment


<s> if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; else if ( REG_FUNCTION_VALUE_P ( DF_REF_REG ( mention ) ) ) insn_entry [ uid ] . is_live_out = <NUM_LIT> ; union_uses ( insn_entry , insn , mention ) ; } } if ( insn_entry [ uid ] . is_relevant ) { insn_entry [ uid ] . is_load = insn_is_load_p ( insn ) ; insn_entry [ uid ] . is_store = insn_is_store_p ( insn ) ; if ( insn_is_swap_p ( insn ) ) insn_entry [ uid ] . is_swap = <NUM_LIT> ; else { unsigned int special = SH_NONE ; insn_entry [ uid ] . is_swappable = insn_is_swappable_p ( insn_entry , insn , & special ) ; if ( special != SH_NONE && insn_entry [ uid ] . contains_subreg ) insn_entry [ uid ] . is_swappable = <NUM_LIT> ; else if ( special != SH_NONE ) insn_entry [