<s> int64_t Res ; if ( Expr -> evaluateAsAbsolute ( Res ) ) return Res ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Constant ) { return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ; } if ( Kind == MCExpr :: Binary ) { unsigned Res = getExprOpValue ( cast < MCBinaryExpr > ( Expr ) -> getLHS ( ) , Fixups , STI ) ; Res += getExprOpValue ( cast < MCBinaryExpr > ( Expr ) -> getRHS ( ) , Fixups , STI ) ; return Res ; } if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: MEK_None : case <ISA_LIT>MCExpr :: MEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL : return getExprOpValue ( <ISA_LIT>Expr -> getSubExpr ( ) , Fixups , STI ) ; case <ISA_LIT>MCExpr :: MEK_CALL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_CALL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT>


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ReplaceBITCASTResults ( N , Results , DAG ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceReductionResults ( N , Results , DAG , <STR_LIT> , <STR_LIT> ) ; return ; case <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_pmovsxwd256_mask ( ( __v8hi ) __A , ( __v8si ) __W , (


<s> fs -> regs . reg [ SH_DWARF_FRAME_MACH ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SH_DWARF_FRAME_MACH ] . loc . offset = ( long ) & ( sc -> sc_mach ) - new_cfa ; fs -> regs . reg [ SH_DWARF_FRAME_MACL ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SH_DWARF_FRAME_MACL ] . loc . offset = ( long ) & ( sc -> sc_macl ) - new_cfa ; r = SH_DWARF_FRAME_FP0 ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fs -> regs . reg [ r + i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ r + i ] . loc . offset = ( long ) & ( sc -> sc_fpregs [ i ] ) - new_cfa ; } r = SH_DWARF_FRAME_XD0 ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = ( long ) & ( sc -> sc_xfpregs [ <NUM_LIT> * i ] ) - new_cfa ; } fs -> regs . reg [ SH_DWARF_FRAME_FPUL ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SH_DWARF_FRAME_FPUL ] . loc . offset = ( long ) & ( sc -> sc_fpul ) - new_cfa ; fs -> regs . reg [ SH_DWARF_FRAME_FPSCR ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SH_DWARF_FRAME_FPSCR ] . loc . offset = ( long ) & ( sc -> sc_fpscr ) - new_cfa ; fs -> regs . reg [ SH_DWARF_FRAME_PC ] . how =


<s> return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short ( imm )


<s> case CmpInst :: FCMP_ONE : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: FCMP_ORD : Predicate = CmpInst :: FCMP_ORD ; break ; case CmpInst :: FCMP_UNO : Predicate = CmpInst :: FCMP_UNO ; break ; case CmpInst :: FCMP_UEQ : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: FCMP_UGT : Predicate = CmpInst :: FCMP_UNO ; break ; case CmpInst :: FCMP_UGE : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: FCMP_ULT : Predicate = CmpInst :: FCMP_UNO ; break ; case CmpInst :: FCMP_ULE : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: FCMP_UNE : Predicate = CmpInst :: FCMP_UNO ; break ; case CmpInst :: FCMP_TRUE : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: ICMP_EQ : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: ICMP_NE : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: ICMP_UGT : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: ICMP_UGE : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: ICMP_ULT : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: ICMP_ULE : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: ICMP_SGT : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: ICMP_SGE : Predicate = CmpInst :: FCMP_TRUE ; break ; case CmpInst :: ICMP_SLT : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: ICMP_SLE : Predicate = CmpInst :: FCMP_TRUE ; break ; } return


<s> if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , <STR_LIT> + <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; break ; case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; break ; default : break ; } EmitSegmentOverridePrefix ( TSFlags , CurByte , MemOperand , MI , OS ) ; unsigned char LastByte = VEX_PP | ( VEX_L << <NUM_LIT> ) | ( VEX_4V << <NUM_LIT> ) ; if ( VEX_B && VEX_X && ! VEX_W && ( VEX_5M == <NUM_LIT> ) ) { EmitByte ( <NUM_LIT> , CurByte , OS


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( Zeroable . countLeadingOnes ( ) < ( Mask . size ( ) - <NUM_LIT> ) ) return SDValue ( ) ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; V1 = DAG . getNode ( <STR_LIT> ,


<s> OperandFlags = isPIC ? <STR_LIT> : <STR_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) { if ( isPIC && ! is64Bit ) { Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ; } Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Changed = false ; TII = F . getSubtarget ( ) . getInstrInfo ( ) ; for ( auto & MBB


<s> return DecodeMem ( Inst , insn , Address

, Decoder , true , DecodeCPPairRegisterClass ) ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo


<s> MachineInstr & MI = * MBBI ; const bool UseZeroBasedSandbox = FlagUseZeroBasedSandbox ; if ( ! IsLoad ( MI ) && ! IsStore ( MI ) ) return false ; if ( IsPushPop ( MI ) ) return false ; unsigned MemOp ; if ( ! FindMemoryOperand ( MI , & MemOp ) ) return false ; assert ( isMem ( & MI , MemOp ) ) ; MachineOperand & BaseReg = MI . getOperand ( MemOp + <NUM_LIT> ) ; MachineOperand & Scale = MI . getOperand ( MemOp + <NUM_LIT> ) ; MachineOperand & IndexReg = MI . getOperand ( MemOp + <NUM_LIT> ) ; MachineOperand & SegmentReg = MI . getOperand ( MemOp + <NUM_LIT> ) ; if ( BaseReg . getReg ( ) == <STR_LIT> ) return false ; IndexReg . setReg ( PromoteRegTo64 ( IndexReg . getReg ( ) ) ) ; BaseReg . setReg ( PromoteRegTo64 ( BaseReg . getReg ( ) ) ) ; assert ( IndexReg . getSubReg ( ) == <NUM_LIT>


<s> else if ( rs6000_warn_altivec_long ) warning ( <NUM_LIT> , <STR_LIT> ) ; } else if ( type == long_long_unsigned_type_node || type == long_long_integer_type_node ) error ( <STR_LIT> ) ; else if ( type == double_type_node ) error ( <STR_LIT> ) ; else if ( type == long_double_type_node ) error ( <STR_LIT> ) ; else if ( type == boolean_type_node ) error ( <STR_LIT> ) ; else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) error ( <STR_LIT> ) ; switch ( altivec_type ) { case 'v' : unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case SFmode : result = V4SF_type_node ; break ; case V4SImode : case V8HImode : case V16QImode : case V4SFmode : result = type ; default : break ; } break ; case 'b' : switch ( mode ) { case SImode : case V4SImode : result = bool_V4SI_type_node ; break ; case HImode : case V8HImode : result = bool_V8HI_type_node ; break ; case QImode : case V16QImode : result


<s> assert ( LHSReg && RHSReg && <STR_LIT> ) ; assert ( LHSReg != <STR_LIT> && LHSReg != <STR_LIT> && RHSReg != <STR_LIT> && RHSReg != <STR_LIT> ) ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return <NUM_LIT> ; if ( ShiftImm >= <NUM_LIT> ) return <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = nullptr ; if ( SetFlags ) RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; else RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs (


<s> EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG ] ( SDValue & V ) { if ( SDValue NegVal = isFNEG ( DAG , V . getNode ( ) ) ) { V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { if ( SDValue NegVal = isFNEG ( DAG , V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { NegVal = DAG . getBitcast ( V . getOperand ( <NUM_LIT> ) . getValueType ( ) , NegVal ) ; V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegVal , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , NegA != NegB , NegC ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl

, VT , A , B , C , N -> getOperand ( <NUM_LIT> ) ) ;


<s> gen_shifty_op ( ASHIFTRT , operands ) ; break ; } operands [ <NUM_LIT> ] = GEN_INT ( shift2 ) ; gen_shifty_hi_op ( ASHIFT , operands ) ; } else if ( shift2 ) { operands [ <NUM_LIT> ] = GEN_INT ( - shift2 ) ; gen_shifty_hi_op ( LSHIFTRT , operands ) ; } emit_insn ( size <= <NUM_LIT> ? gen_extendqisi2 ( dest , gen_lowpart ( QImode , dest ) ) : gen_extendhisi2 ( dest , gen_lowpart ( HImode , dest ) ) ) ; } break ; } case <NUM_LIT> : { int i = <NUM_LIT> - size ; if ( ! currently_expanding_to_rtl && ! reload_in_progress && ! reload_completed ) emit_insn ( gen_shl_sext_ext ( dest , source , left_rtx , size_rtx ) ) ; else { operands [ <NUM_LIT> ] = dest ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - insize ) ; gen_shifty_hi_op ( ASHIFT , operands ) ; emit_insn ( gen_extendhisi2 ( dest , gen_lowpart ( HImode , dest ) ) ) ; } while ( -- i >= <NUM_LIT> ) gen_ashift ( ASHIFTRT , <NUM_LIT> , dest ) ; break ; } case <NUM_LIT> : case <NUM_LIT> : if ( ! currently_expanding_to_rtl && ! reload_in_progress && ! reload_completed ) { emit_insn ( gen_shl_sext_ext ( dest , source , left_rtx , size_rtx ) ) ; emit_insn ( gen_movsi ( dest , source ) ) ; break ; } emit_insn ( gen_andsi3 ( dest , source , GEN_INT (

( <NUM_LIT> << insize ) - <NUM_LIT> ) ) ) ;


<s> return Kind == k_TraceSyncBarrierOpt


<s> case NoOverride : return In<ISA_LIT>16Mode ; case <ISA_LIT>16Override : return true


<s> void <ISA_LIT>WinCOFFStreamer :: FinishImpl ( ) { EmitFrames ( nullptr , true ) ; EmitW64Tables ( ) ; MCWinCOFFStreamer :: FinishImpl ( )


<s> Value * <ISA_LIT>IREmitter :: visitFRSQRT ( const SDNode * N


<s> <STR_LIT> Branch ( getBranchInfo ( I ) ) ; if ( ! Branch . Target -> isMBB ( ) ) return true ; if ( Branch . Type != <STR_LIT> ) return true ; if ( Branch . CCMask == <STR_LIT> ) { if ( ! AllowModify ) { TBB = Branch . Target -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( Branch . Target -> getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = Branch . Target -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = Branch . Target -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Branch . CCValid ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( Branch


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ,


<s> for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( MachineOperand & MO : UserMI -> operands ( ) ) if ( MO . isCPI ( ) ) { MO . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ]


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return


<s> void \ readonly_data ( ) \ { \ if ( in_section != in_readonly_data ) \ { \ if ( flag_pic ) \ fprintf ( asm_out_file , <STR_LIT> , DATA_SECTION_ASM_OP ) ; \ else \ fprintf ( asm_out_file , <STR_LIT> , READONLY_DATA_ASM_OP ) ;

\ in_section = in_readonly_data ; \ } \ }


<s> } if ( NumCopies != <NUM_LIT> && NumCopies != <NUM_LIT> ) return false ; bool HasRet = false ; for ( unsigned i = <NUM_LIT> ; i < NumCopies ; ++ i ) { SDNode * Copy = Copies [ i ] ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { SDNode * Use = * UI ; if ( Use == Copies [ <NUM_LIT> ] || ( ( NumCopies == <NUM_LIT> ) && ( Use == Copies [ <NUM_LIT> ] ) ) ) continue ; return false ; } if ( UI -> getOpcode (


<s> MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1


<s> Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * I ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset (


<s> getParser ( ) . getStreamer ( ) . EmitGPRel64Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error

( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printMemBOption ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned val = MI -> getOperand ( OpNum ) .


<s> if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isGlobal ( ) || MI -> getOperand ( opNum + <NUM_LIT> ) . isCPI ( ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> ) ; O << <STR_LIT> ; } else


<s> case ESize8 : Imm64 = Imm8 ; break ; case ESize16 : Imm64 = Imm8 << <NUM_LIT> * ( cmode >> <NUM_LIT> & <NUM_LIT> ) ; break ; case ESize32 : { if ( cmode == <NUM_LIT> ) Imm64 = ( Imm8 << <NUM_LIT> ) | <NUM_LIT> ; else if ( cmode == <NUM_LIT> ) Imm64 = ( Imm8 << <NUM_LIT> ) | <NUM_LIT> ; else { Imm64 = Imm8 << <NUM_LIT> * ( cmode >> <NUM_LIT> & <NUM_LIT> ) ; } break ; } case ESize64


<s> ASSERT_RTL_DUMP_EQ ( <STR_LIT> , gen_raw_REG ( SImode , <NUM_LIT> ) ) ; ASSERT_RTL_DUMP_EQ ( <STR_LIT> , gen_raw_REG ( SImode ,


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return <STR_LIT> ; if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION

( type ) == <NUM_LIT> ) return <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns ,


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveNext (


<s> case TargetOpcode :: G_MEMCPY : case TargetOpcode :: G_MEMMOVE : case TargetOpcode :: G_MEMSET : { unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; if ( Helper . tryCombineMemCpyFamily ( MI , MaxLen ) ) return true ; if ( Opc == TargetOpcode :: G_MEMSET ) return llvm :: <ISA_LIT>GISelUtils :: tryEmitBZero ( MI , B , EnableMinSize ) ; return false


<s> static DecodeStatus DecodeIT ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mask = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) { pred = <NUM_LIT> ; S = MCDisassembler :: SoftFail ; } if ( ( mask & <NUM_LIT> ) == <NUM_LIT> ) { mask &= <NUM_LIT> ; mask |= <NUM_LIT> ; S = MCDisassembler :: SoftFail ; } Inst . addOperand ( MCOperand :: CreateImm ( pred ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mask ) ) ; return S


<s> bool sh_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return


<s> return ( __m128i ) vec_mergeh ( ( __v16qu )


<s> unsigned getReg ( ) const { assert ( ( Kind == k_Register ) &&


<s> if ( auto * P = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ) DT = & P -> getDomTree ( ) ; if ( DT == nullptr && ( NumInterestingAllocas > <NUM_LIT> || ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) ) { DeleteDT = std :: make_unique < DominatorTree > ( * F ) ; DT = DeleteDT . get ( ) ; } std :: unique_ptr < PostDominatorTree > DeletePDT ; PostDominatorTree * PDT = nullptr ; if ( auto * P = getAnalysisIfAvailable < PostDominatorTreeWrapperPass > ( ) ) PDT = & P -> getPostDomTree ( ) ; if ( PDT == nullptr && ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) { DeletePDT = std :: make_unique < PostDominatorTree > ( * F ) ; PDT = DeletePDT . get ( ) ; } SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = insertBaseTaggedPointer ( Allocas , DT ) ; for ( auto & I : Allocas ) { const AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( Info . Tag < <NUM_LIT> ) continue ; IRBuilder < > IRB ( Info . AI -> getNextNode ( ) ) ; Function * TagP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> , { Info . AI -> getType ( ) } ) ; Instruction * TagPCall = IRB . CreateCall ( TagP , { Constant :: getNullValue ( Info . AI -> getType ( ) ) , Base , ConstantInt :: get ( IRB . getInt64Ty ( ) , Info . Tag ) } ) ; if ( Info . AI -> hasName ( ) ) TagPCall -> setName ( Info . AI -> getName ( ) + <STR_LIT> ) ; Info . AI -> replaceAllUsesWith ( TagPCall ) ; TagPCall -> setOperand ( <NUM_LIT> , Info . AI ) ; if ( UnrecognizedLifetimes . empty ( ) && Info . LifetimeStart . size ( ) == <NUM_LIT> && Info . LifetimeEnd . size ( ) == <NUM_LIT> ) { IntrinsicInst * Start = Info . LifetimeStart [ <NUM_LIT> ] ; IntrinsicInst * End = Info . LifetimeEnd [ <NUM_LIT> ] ; uint64_t Size = dyn_cast < ConstantInt > ( Start -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Size = alignTo ( Size , kTagGranuleSize ) ; tagAlloca ( AI , Start -> getNextNode ( ) , Start -> getArgOperand ( <NUM_LIT> ) , Size ) ; if ( PDT != nullptr && postDominates ( PDT , End , Start ) ) { untagAlloca ( AI , End , Size ) ; } else { SmallVector < Instruction * , <NUM_LIT> > ReachableRetVec ; unsigned NumCoveredExits = <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool useConstPool ( ) const { return !


<s> static void addLiveInRegs ( Iter Filler , MachineBasicBlock & MBB ) { for ( unsigned I = <NUM_LIT> , E = Filler -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = Filler -> getOperand ( I ) ; unsigned R ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! ( R = MO . getReg ( ) ) ) continue ; const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getTarget ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getAllocatableSet ( MF ) . test ( R ) && <STR_LIT> <STR_LIT> ) ; if ( ! MBB . isLiveIn ( R ) ) MBB


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; } BaseOp = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT>


<s> SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F ,


<s> if ( ! OC ) return Error ( OpcodeLoc , <STR_LIT> ) ; const int64_t Opcode = OC -> getValue ( ) ; if ( Opcode & ~ <NUM_LIT> ) return Error ( OpcodeLoc , <STR_LIT> ) ; Opcodes . push_back ( uint8_t ( Opcode ) ) ; return false ; } ; SMLoc OpcodeLoc = getLexer ( ) . getLoc ( ) ; if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return Error ( OpcodeLoc , <STR_LIT> ) ; if ( parseMany ( parseOne ) ) return true ; getTargetStreamer ( ) . emitUnwindRaw ( StackOffset , Opcodes ) ; return false


] , SImode ) && aarch64_sve_ptrue_flag ( pred2 [ <NUM_LIT> ] , SImode ) ) ;


<s> return new <ISA_LIT>PassConfig ( this


<s> if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return cfun -> machine -> frame . total_size


<s> toc_initialized = <NUM_LIT> ; } else fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; } else if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { fprintf ( asm_out_file , <STR_LIT> , TOC_SECTION_ASM_OP ) ; if ( ! toc_initialized ) { ASM_OUTPUT_ALIGN ( asm_out_file , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; toc_initialized = <NUM_LIT> ; } } else { fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; if ( ! toc_initialized


<s> case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerExtendedLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMUL_LOHI ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static SDValue prepareTS1AM ( SDValue Op , SelectionDAG & DAG , SDValue & Flag , SDValue & Bits ) { SDLoc DL ( Op ) ; AtomicSDNode * N = cast < AtomicSDNode > ( Op ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = Ptr .


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo &


<s> SDValue <ISA_LIT>TargetLowering :: LowerFSINCOS ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetDarwin ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const Align StackAlign = DL . getPrefTypeAlign ( RetTy ) ; int FrameIdx = MFI . CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node =


<s> std :: pair < unsigned , unsigned > <ISA_LIT>InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF )


<s> uint64_t MaskedImm = Imm & ( <NUM_LIT> >> ( <NUM_LIT> - Size ) ) ; if ( ! MaskedImm ) return ; if ( RemSize <= <NUM_LIT> ) { AddInstr ( SeqLs , Inst ( ADDiu , MaskedImm ) ) ; return ; } if ( ! ( Imm & <NUM_LIT> ) ) { GetInstSeqLsSLL ( Imm , RemSize , SeqLs ) ; return ; } GetInstSeqLsADDiu ( Imm , RemSize , SeqLs ) ; if ( Imm & <NUM_LIT> ) { InstSeqLs SeqLsORi ; GetInstSeqLsORi ( Imm ,


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const TargetRegisterInfo * TRI = BB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MI -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( MI , BB , TRI ) ) { copy0MBB -> addLiveIn ( <STR_LIT> ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; } sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor (


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAlignedMemoryOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addVecListOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return


<s> static SDValue LowerVectorAllZero ( const SDLoc & DL , SDValue V , <STR_LIT> CC , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG , <STR_LIT> & <ISA_LIT>CC ) { EVT VT = V . getValueType ( ) ; assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; <ISA_LIT>CC = ( CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( VT . getSizeInBits ( ) < <NUM_LIT> ) { EVT IntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , VT . getSizeInBits ( ) ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( IntVT ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( IntVT ,

V ) , DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ) ;


<s> bool enableShrinkWrapping ( const MachineFunction & MF


<s> const MachineOperand & MO = getLoadStoreRegOp ( * MI ) ; unsigned Reg = MO . getReg ( ) ; bool IsKill = MO . isKill ( ) ; if ( IsKill ) KilledRegs . insert ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , IsKill ) ) ; UsedRegs . insert ( Reg ) ; if ( IsLoad ) { for ( const MachineOperand & MO : MI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isDead ( ) ) continue ; assert ( MO . isImplicit ( ) ) ; unsigned DefReg = MO . getReg ( ) ; if ( is_contained ( ImpDefs , DefReg ) ) continue ; if ( MI -> readsRegister ( DefReg ) ) continue ; ImpDefs . push_back ( DefReg ) ; } } } using iterator = MachineBasicBlock :: iterator ; MachineInstr * LatestMI = Cand . Instrs [ Cand . LatestMIIdx ] ; iterator InsertBefore = std :: next ( iterator ( LatestMI ) ) ; MachineBasicBlock & MBB = * LatestMI -> getParent ( ) ; unsigned Offset = getMemoryOpOffset ( * First ) ; unsigned Base = getLoadStoreBaseOp ( * First ) . getReg ( ) ; bool BaseKill = LatestMI -> killsRegister ( Base ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; }


<s> case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static SDValue combineSetCCAtomicArith ( SDValue Cmp , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! ( Cmp . getOpcode ( ) == <STR_LIT> || ( Cmp . getOpcode ( ) == <STR_LIT> && ! Cmp -> hasAnyUseOfValue ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; if ( ! Cmp . hasOneUse ( ) ) return SDValue ( ) ; SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC ) return SDValue ( ) ; APInt Comparison = CmpRHSC -> getAPIntValue ( ) ; if ( Comparison == - Addend ) { auto * AN = cast < AtomicSDNode > ( CmpLHS . getNode ( ) ) ; auto AtomicSub = DAG . getAtomic ( <STR_LIT> , SDLoc ( CmpLHS ) , CmpLHS . getValueType ( ) , CmpLHS . getOperand ( <NUM_LIT> ) , CmpLHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - Addend , SDLoc ( CmpRHS ) , CmpRHS . getValueType ( ) ) , AN -> getMemOperand ( ) ) ; bool NeedCF = false ; switch ( CC )


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( Func -> hasFnAttribute ( <STR_LIT> ) ) { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; SrcReg = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; SrcReg =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB


<s> ExitMBB -> splice ( ExitMBB -> begin ( ) , & MBB , std :: next ( MI . getIterator ( ) ) , MBB . end ( ) ) ; ExitMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( LoopCmpMBB ) ; MachineBasicBlock * CurrentMBB = LoopCmpMBB ; BuildMI ( CurrentMBB , DL , LL , Old ) . addReg ( RA ) . addReg ( RB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchLo ) . addReg ( OldLo ) . addReg ( CmpLo ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchHi ) . addReg ( OldHi ) . addReg ( CmpHi ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchLo ) . addReg ( ScratchLo ) . addReg ( ScratchHi ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( CmpFailMBB ) ; CurrentMBB -> addSuccessor ( CmpSuccMBB ) ; CurrentMBB -> addSuccessor ( CmpFailMBB ) ; CurrentMBB = CmpSuccMBB ; PairedCopy ( TII , * CurrentMBB , CurrentMBB -> end ( ) , DL , ScratchHi , ScratchLo , NewHi , NewLo ) ; BuildMI ( CurrentMBB , DL , SC ) . addReg ( Scratch ) . addReg ( RA ) . addReg ( RB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( LoopCmpMBB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ExitMBB ) ; CurrentMBB -> addSuccessor ( LoopCmpMBB ) ; CurrentMBB -> addSuccessor ( ExitMBB ) ; CurrentMBB = CmpFailMBB ; BuildMI ( CurrentMBB , DL , SC ) . addReg ( Old ) . addReg ( RA ) . addReg ( RB ) ; CurrentMBB -> addSuccessor ( ExitMBB ) ; recomputeLiveIns ( * LoopCmpMBB


<s> } else if ( ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( addr ) == <NUM_LIT> ) || ( TARGET_VXWORKS_RTP && GET_CODE ( addr ) == LABEL_REF ) ) { rtx tmp = legitimize_pe_coff_symbol ( addr , true ) ; if ( tmp ) return tmp ; if ( TARGET_64BIT && TARGET_PECOFF ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_PCREL ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; } else if ( TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_GOTPCREL ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; new_rtx = gen_const_mem ( Pmode , new_rtx ) ; set_mem_alias_set ( new_rtx , ix86_GOT_alias_set ( ) ) ; } else { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_GOT ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; if ( TARGET_64BIT ) new_rtx = copy_to_suggested_reg ( new_rtx , reg , Pmode ) ; if ( reg != <NUM_LIT> ) { gcc_assert ( REG_P ( reg ) ) ; new_rtx = expand_simple_binop ( Pmode , PLUS , pic_offset_table_rtx , new_rtx , reg , <NUM_LIT> , OPTAB_DIRECT ) ; } else new_rtx = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , new_rtx ) ; new_rtx = gen_const_mem ( Pmode , new_rtx ) ; set_mem_alias_set ( new_rtx , ix86_GOT_alias_set ( ) ) ; } new_rtx = copy_to_suggested_reg ( new_rtx , reg , Pmode ) ; } else { if ( CONST_INT_P ( addr ) && ! x86_64_immediate_operand ( addr , VOIDmode ) ) new_rtx = copy_to_suggested_reg ( addr , reg , Pmode ) ; else if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == UNSPEC || ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == UNSPEC ) ) return orig ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; } if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) , op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! TARGET_PECOFF && gotoff_operand ( op0 , Pmode ) && CONST_INT_P ( op1 ) ) { if ( ! TARGET_64BIT ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , op0 ) , UNSPEC_GOTOFF ) ; new_rtx = gen_rtx_PLUS ( Pmode , new_rtx , op1 ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; if ( reg != <NUM_LIT> ) { gcc_assert ( REG_P ( reg )


<s> static int matchVectorShuffleAsByteRotate ( MVT VT , SDValue & V1 , SDValue & V2 , ArrayRef < int > Mask ) { int NumElts = Mask . size ( ) ; int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; int NumLaneElts = NumElts / NumLanes ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { int M = Mask [ l + i ] ; if ( M == SM_SentinelUndef ) continue ; if ( M == SM_SentinelZero ) return - <NUM_LIT> ; assert ( <NUM_LIT> <= M && M < ( <NUM_LIT> * NumElts ) && <STR_LIT> ) ; int LaneIdx = ( M % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return - <NUM_LIT> ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> )


<s> bool slowLEA ( ) const { return SlowLEA


<s> void AnalyzeCallResult ( const SmallVectorImpl < <STR_LIT> > & Ins , CCAssignFn Fn , const Type * RetTy , const char


<s> CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = <NUM_LIT> ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = <NUM_LIT> ; return true ; } if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; return true


<s> return DAG -> getMergeValues ( Values ,


<s> BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return BB


<s> void Closure :: visitRegister ( unsigned Reg , SmallVectorImpl < unsigned > & Worklist ) { if ( EnclosedEdges . count ( Reg ) ) return ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return ; if ( ! MRI -> hasOneDef (


<s> else if ( ST . is64Bit ( ) || ST . isTargetDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! ST . is64Bit ( ) && ST . isOSWindows ( ) ) Ret +=


<s> void <ISA_LIT>MCAsmStreamer :: EmitThumbFunc ( MCSymbol * Func ) { llvm_unreachable ( <STR_LIT> )


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI . getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI . getNumOperands ( ) - Desc . getNumOperands


<s> EVT CCVT = N0 . getValueType ( ) ; SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) == <STR_LIT> && SetCC . getOperand ( <NUM_LIT> ) == DAG . getCondCode ( <STR_LIT> ) ) { SDValue CmpLHS = SetCC . getOperand ( <NUM_LIT> ) ; EVT VT = CmpLHS . getValueType ( ) ; SDNode * CmpRHS = SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * SplatLHS = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * SplatRHS = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; APInt SplatLHSVal ; if ( CmpLHS . getValueType ( ) == N -> getOperand ( <NUM_LIT> ) . getValueType ( ) && VT . isSimple ( ) && is_contained ( makeArrayRef ( { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , VT . getSimpleVT ( ) . SimpleTy ) && <STR_LIT> ( SplatLHS , SplatLHSVal ) && SplatLHSVal . isOne ( ) && <STR_LIT> ( CmpRHS ) && <STR_LIT> ( SplatRHS ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumElts , DAG . getConstant ( VT . getScalarSizeInBits ( ) - <NUM_LIT> , SDLoc ( N ) , VT . getScalarType


<s> SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ; if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getBitcast ( VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ] = <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; return


<s> return DecodeUImmWithOffsetAndScale < Bits , Offset , <NUM_LIT> >


<s> void <ISA_LIT>TargetLowering :: addQRTypeForNEON ( MVT VT ) { addRegisterClass ( VT ,


<s> if ( Subtarget . has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMSUB ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( )


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine


<s> Type * I64Ty = Builder . getInt64Ty ( ) ; Value * RSP = Builder . CreatePtrToInt ( StackPtr , I64Ty ) ; RSP = Builder . CreateAdd ( RSP , Builder . CreateZExtOrBitCast ( StackSize , I64Ty ) ) ; RSP = Builder . CreateSub ( RSP , Builder . getInt64 ( <NUM_LIT> ) ) ; Builder . CreateStore ( Builder . getInt ( APInt :: getAllOnesValue ( <NUM_LIT> ) ) , Builder . CreateIntToPtr ( RSP , I64Ty -> getPointerTo ( ) ) ) ; auto InitRegTo = [ & ] ( unsigned RegNo , Value * Val ) { unsigned RegLargestSuper = getTranslator ( ) . getRegSetDesc ( ) . RegLargestSupers [ RegNo ] ; assert ( RegLargestSuper == RegNo ) ; unsigned RegOffsetInSet = getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ RegLargestSuper ] ; Value * Idx [ ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( RegOffsetInSet ) } ; Builder . CreateStore ( Val , Builder .


<s> enum x86_64_reg_class regclass [ MAX_CLASSES ] ; int n = classify_argument ( mode , type , regclass , <NUM_LIT> ) ; * int_nregs = <NUM_LIT> ; * sse_nregs = <NUM_LIT> ; if ( ! n ) return true ; for ( n -- ; n >= <NUM_LIT> ; n -- ) switch ( regclass [ n ] ) { case X86_64_INTEGER_CLASS : case X86_64_INTEGERSI_CLASS : ( * int_nregs ) ++ ; break ; case X86_64_SSE_CLASS : case X86_64_SSEHF_CLASS


<s> static const unsigned CalleeSavedRegs [ ] = { <STR_LIT> , <NUM_LIT>


<s> case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; return new ELF<ISA_LIT>AsmBackend ( T , TheTriple . getOS ( ) , false


<s> static __inline qword si_lqd ( qword a , unsigned int imm ) { return ( ( qword ) ( vec_ld ( si_to_uint ( a ) & ~ <NUM_LIT> , ( vector unsigned char * ) ( imm


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU ,


<s> static int mips_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( mips_cost -> memory_latency + memory_move_secondary_cost ( mode , rclass ,


<s> } auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; Value * Val , * LHS , * RHS ; if ( match ( V , m_Trunc ( m_Value ( Val ) ) ) ) { if ( cast < TruncInst > ( I ) -> getDestTy ( ) -> getIntegerBitWidth ( ) == MaxBitWidth ) return IsNarrowSequence < MaxBitWidth > ( Val , VL ) ; } else if ( match ( V , m_Add ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) { return false ; } else if ( match ( V , m_ZExtOrSExt ( m_Value ( Val ) ) ) ) { if ( cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) != MaxBitWidth ) return false ; if ( match ( Val , m_Load ( m_Value ( )


<s> static void emitRegPlusImmediate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , unsigned DestReg , unsigned SrcReg , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII ,


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; if ( C . Opcode == <STR_LIT> && C . CCMask != <STR_LIT> && C . CCMask != <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( isAbsolute ( C . Op0 , TrueOp , FalseOp ) ) return getAbsolute ( DAG , DL , TrueOp , C . CCMask & <STR_LIT> ) ; if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp ,


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) { Inst . setOpcode ( <STR_LIT> ) ; } else { if ( ! isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitCMP ( const SDNode * N


<s> bool nds32_n7_last_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( post_update_insn_p ( producer ) ) return false ; rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; if ( last_def_reg == NULL_RTX ) return false ; gcc_assert ( REG_P ( last_def_reg ) || GET_CODE ( last_def_reg


<s> static MCDisassembler * create<ISA_LIT>64Disassembler ( const Target & T , const MCSubtargetInfo


<s> bool <ISA_LIT>16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! Subtarget -> in<ISA_LIT>16Mode


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < <NUM_LIT> ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) ,

std :: end ( LibCalls ) , CallSym , Comp ) ;


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>MCInstrAnalysis ( Info )


<s> auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; if ( STI . in<ISA_LIT>16Mode ( ) ) return <STR_LIT> ; if ( STI . inMicro<ISA_LIT>Mode ( ) ) return


<s> bool MVETailPredication :: runOnLoop ( Loop * L , LPPassManager & ) { if ( skipLoop ( L ) || ! EnableTailPredication ) return false ; MaskedInsts . clear ( ) ; Function & F = * L -> getHeader ( ) -> getParent ( ) ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( ) ) return false ; Setup = FindLoopIterations ( Preheader -> getSinglePredecessor ( ) ) ; if ( ! Setup ) return false ; } IntrinsicInst * Decrement


<s> return ( TARGET_ISA_V3 && ( ival < <NUM_LIT> ) && satisfies_constraint_Iu15 ( gen_int_mode (


<s> unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MFI .


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( )


<s> return ( __m256i ) __builtin_ia32_andnotsi256 ( ( __v4di ) __A , (


<s> if ( mode == DImode ) return ( ne == <NUM_LIT> || nb == <NUM_LIT> || ( nb < <NUM_LIT> && ne <= nb ) ) ; if ( mode == SImode ) return ( nb < <NUM_LIT> && ne < <NUM_LIT> ) ; return false


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; NumOpsAdded =


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> TM . getRegisterInfo ( ) -> getEncodingValue ( MO


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < <NUM_LIT> ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk


<s> int llvm :: getMatchingCondBranchOpcode ( int Opc ) { if ( Opc == <STR_LIT> ) return <STR_LIT> ; if ( Opc == <STR_LIT>


<s> if ( RelocM == Reloc :: PIC_ || RelocM == Reloc :: DynamicNoPIC ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; SetVector < const MCSection * , SmallVector < const MCSection * , <NUM_LIT> > , SmallPtrSet < const MCSection * , <NUM_LIT> > > TextSections ; TextSections . insert ( TLOFMacho . getTextSection ( ) ) ; for ( Module :: iterator F = M . begin ( ) , e = M . end ( ) ; F != e ; ++ F ) if ( !

F -> isDeclaration ( ) && ! F -> hasAvailableExternallyLinkage ( ) ) TextSections . insert ( TLOFMacho . SectionForGlobal ( F , Mang , TM ) ) ;


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int ) vec_cmpgt ( b , float_exp_mask ) ; c = vec_or ( c , d ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A ,


<s> assert ( & ( * MF . begin ( ) ) == & PrologueMBB && <STR_LIT> ) ; const unsigned HipeLeafWords = <NUM_LIT> ; const unsigned CCRegisteredArgs = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; const unsigned Guaranteed = HipeLeafWords * SlotSize ; unsigned CallerStkArity = MF . getFunction ( ) -> arg_size ( ) > CCRegisteredArgs ? MF . getFunction ( ) -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; unsigned MaxStack = MFI -> getStackSize ( ) + CallerStkArity * SlotSize + SlotSize ; assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( const auto & LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn ( LI ) ; incStackMBB -> addLiveIn ( LI ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; if ( Is64Bit ) { SPReg = <STR_LIT> ; PReg =


<s> if ( ! mustbelongordbl ) typedata -> base = BT_LONG ; else if ( ! strcmp ( mustbelongordbl , <STR_LIT> ) ) typedata -> base = BT_LONGLONG ; else if ( ! strcmp ( mustbelongordbl , <STR_LIT> ) ) typedata -> base = BT_LONGDOUBLE ; else { typedata -> base = BT_LONG ; pos = oldpos ; } } else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_FLOAT ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DOUBLE ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_INT128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_FLOAT128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_BOOL ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_STRING ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL32 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL64 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_IBM128 ; else { diag ( oldpos , <STR_LIT> ) ; return <NUM_LIT> ; } handle_pointer ( typedata


<s> EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = Op . getValueType ( ) ; assert ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) && Subtarget -> hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector ( ) ) return Op ; if ( DstVT == <STR_LIT> && SrcVT . isVector ( ) ) return Op ; if ( SrcVT . isVector ( ) && DstVT . isVector ( ) ) return Op ; return SDValue


<s> break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: createImm ( Code ) ) ; return MCDisassembler ::


<s> if ( any_of ( make_range ( std :: next ( FirstRealElt ) , M . end ( ) ) , [ & ExpectedElt ] ( int Elt ) { return Elt != ExpectedElt ++ && Elt >= <NUM_LIT> ; } ) ) return None ; uint64_t Imm = ExpectedElt . getZExtValue ( ) ; bool ReverseExt = false


<s> TII . storeRegToStackSlot ( MBB , MBBI , ABI . GetEhDataReg ( I ) , false , <ISA_LIT>FI -> getEhDataRegFI ( I ) , RC , & RegInfo ) ; } for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( <ISA_LIT>FI -> getEhDataRegFI ( I ) ) ; unsigned Reg = MRI -> getDwarfRegNum ( ABI . GetEhDataReg ( I ) , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MOVE ) , FP ) . addReg ( SP ) . addReg ( ZERO ) . setMIFlag ( MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , MRI -> getDwarfRegNum ( FP , true ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( RegInfo . needsStackRealignment ( MF ) ) { unsigned VR = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( isInt < <NUM_LIT> > ( MFI . getMaxAlignment ( ) ) && <STR_LIT> ) ; int MaxAlign = - ( int ) MFI . getMaxAlignment ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , VR ) . addReg ( ZERO ) . addImm ( MaxAlign ) ; BuildMI ( MBB , MBBI , dl , TII . get ( AND ) , SP ) . addReg ( SP ) . addReg ( VR ) ; if ( hasBP ( MF ) ) { unsigned BP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( MOVE ) , BP ) .


<s> unsigned getPointerSize ( ) const { return


<s> if ( MBB . empty ( ) ) return false ; switch ( MBB . back ( ) . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> EVT ExtraVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT VT = Op . getValueType ( ) ; if ( ! Subtarget -> hasSSE2 ( ) || ! VT . isVector ( ) ) return SDValue ( ) ; unsigned BitsDiff = VT . getScalarType ( ) . getSizeInBits ( ) - ExtraVT . getScalarType ( ) . getSizeInBits ( ) ; SDValue ShAmt = DAG . getConstant ( BitsDiff , <STR_LIT> ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op00 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue


<s> return any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) &


<s> int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /= <NUM_LIT> ; } DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * MergeMI } ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( )


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parsePCRel ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , int64_t MinVal , int64_t MaxVal ) { MCContext & Ctx = getContext ( ) ; MCStreamer & Out = getStreamer ( ) ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; return


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; assert ( Cond . getValueType ( ) . getScalarSizeInBits ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Cond , Cond ) ; return DAG . getSelect ( dl , VT , Mask , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } switch ( VT . SimpleTy ) { default : return Op ; case <STR_LIT>


<s> return ( TARGET_PERF_EXT && ( one_bit_count == <NUM_LIT> )


<s> <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * )


<s> return MatchOperand_Success ; } unsigned Reg = matchRegisterNameAlias ( Name , RegKind :: Matrix ) ; if ( ! Reg ) return MatchOperand_NoMatch ; size_t DotPosition = Name . find ( '.' ) ; assert ( DotPosition != StringRef :: npos && <STR_LIT> ) ; StringRef Head = Name . take_front ( DotPosition ) ; StringRef Tail = Name . drop_front ( DotPosition ) ; StringRef RowOrColumn = Head . take_back ( ) ; MatrixKind Kind = StringSwitch < MatrixKind > ( RowOrColumn ) . Case ( <STR_LIT> , MatrixKind :: Row ) . Case ( <STR_LIT> , MatrixKind :: Col ) . Default ( MatrixKind :: Tile ) ; const auto & KindRes = parseVectorKind ( Tail , RegKind :: Matrix ) ; if ( ! KindRes ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned ElementWidth = KindRes ->


<s> MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( EvenReg , TRC ) ; MRI -> constrainRegClass ( OddReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg , <STR_LIT> , EvenReg ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumMove


<s> static __inline__ float __fnmadds ( float x , float y


<s> if ( CanBeTailCall ) { OutlinedSize = SequenceSize + Occurrences ; } else { OutlinedSize = ( SequenceSize + <NUM_LIT> )


<s> unsigned int old = * mask , ret , new ; while ( <NUM_LIT> ) { if ( old == <NUM_LIT> ) return - <NUM_LIT> ; ret = old & - old ; new = old & ~ ret ; new = __sync_val_compare_and_swap ( mask , old , new ) ; if ( old ==


<s> void <ISA_LIT>InstPrinter :: printNEONModImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> (


<s> auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( )


<s> FunctionPass * llvm :: create<ISA_LIT>IndirectThunks


<s> if ( attrs != NULL_TREE ) { if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_CDECL ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_STDCALL ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_FASTCALL ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_THISCALL ; if ( ( ret & ( IX86_CALLCVT_THISCALL |

IX86_CALLCVT_FASTCALL ) ) == <NUM_LIT> ) {


<s> int regno ; if ( GET_CODE ( x ) != REG ) return false ; regno = REGNO ( x


<s> const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; LivePhysRegs UsedRegs ( TRI ) ; UsedRegs . addLiveOuts ( MBB ) ; const MCPhysReg * CSRegs = TRI . getCalleeSavedRegs ( & MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) UsedRegs . addReg ( CSRegs [ i ] ) ; DebugLoc dl = DebugLoc ( ) ; if ( MBBI != MBB . end ( ) ) { dl = MBBI -> getDebugLoc ( ) ; auto InstUpToMBBI = MBB . end ( ) ; while ( InstUpToMBBI != MBBI ) UsedRegs . stepBackward ( * -- InstUpToMBBI ) ; } unsigned PopReg = <NUM_LIT> ; unsigned TemporaryReg = <NUM_LIT> ; BitVector PopFriendly = TRI . getAllocatableSet ( MF , TRI . getRegClass ( <STR_LIT> ) ) ; if ( STI . useR7AsFramePointer ( ) ) PopFriendly . set ( <STR_LIT> ) ; assert ( PopFriendly . any ( ) && <STR_LIT> ) ; BitVector GPRsNoLRSP = TRI . getAllocatableSet ( MF , TRI . getRegClass ( <STR_LIT> ) ) ; GPRsNoLRSP |= PopFriendly ; GPRsNoLRSP . reset ( <STR_LIT> ) ; GPRsNoLRSP . reset ( <STR_LIT> ) ; GPRsNoLRSP . reset ( <STR_LIT> ) ; findTemporariesForLR ( GPRsNoLRSP , PopFriendly , UsedRegs , PopReg , TemporaryReg ) ; bool UseLDRSP = false ; if ( ! PopReg && MBBI != MBB . begin ( ) ) { auto PrevMBBI = MBBI ; PrevMBBI -- ; if ( PrevMBBI -> getOpcode ( ) == <STR_LIT> ) { UsedRegs . stepBackward ( * PrevMBBI ) ; findTemporariesForLR ( GPRsNoLRSP , PopFriendly , UsedRegs , PopReg , TemporaryReg ) ; if ( PopReg ) { MBBI = PrevMBBI ; UseLDRSP = true ; } } } if ( ! DoIt && ! PopReg && ! TemporaryReg ) return false ; assert ( ( PopReg || TemporaryReg ) && <STR_LIT> ) ; if ( UseLDRSP ) { assert ( PopReg && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( PopReg , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( MBBI -> getNumExplicitOperands ( ) - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( PopReg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; MBBI


<s> fma_root_node :: fma_root_node ( func_fma_steering * globals , du_chain * chain , int id ) : fma_node ( this , chain ) { this -> m_forest = new fma_forest ( globals


<s> static SDValue PerformVLDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; return CombineBaseUpdate ( N ,


<s> Triple TheTriple ( STI . getTargetTriple ( ) ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; IsDarwin = TheTriple . isMacOSX ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits


<s> } else { int V1Index = V2AdjIndex ; int BlendMask [ <NUM_LIT> ] = { Mask [ V2Index ] - <NUM_LIT> , <NUM_LIT> , Mask [ V1Index ] , <NUM_LIT> } ; V2 = DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; if ( V2Index < <NUM_LIT> ) { LowV = V2 ; HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } } return DAG . getNode ( <STR_LIT> , DL , VT , LowV , HighV

, getV4<ISA_LIT>ShuffleImm8ForMask ( NewMask , DL , DAG ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; switch ( CM ) { default :


<s> static SDValue performDSPShiftCombine ( unsigned Opc , SDNode * N , EVT Ty , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned EltSize = Ty . getScalarSizeInBits ( ) ; BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Subtarget . hasDSP ( ) ) return SDValue ( ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget . isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ; SDLoc DL ( N


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr ,


<s> set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( ! TARGET_HARD_FLOAT ) { set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT>


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; std :: unique_ptr < <ISA_LIT>Operand >


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT>


<s> return __builtin_ia32_vcvtdq2ph512_mask_round ( ( __v16si ) __A , _mm256_setzero_ph ( ) , ( __mmask16


<s> Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS ) { switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G3 : SignedValue = SignedValue >> <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : Value = Value >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : Value = Value >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G3 : Value = Value >> <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( RefKind & <ISA_LIT>MCExpr :: VK_NC ) { Value &= <NUM_LIT> ; } else if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS ) { if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( SignedValue < <NUM_LIT> ) SignedValue = ~ SignedValue ; Value = static_cast < uint64_t > ( SignedValue ) ; } else if ( Value > <NUM_LIT> ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; } return Value ; } case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case FK_NONE : case FK_Data_1 : case FK_Data_2


<s> return DisassembleNVdVnVmOptImm ( MI , Opcode , insn , NumOps , NumOpsAdded , N3V_VectorShift ,


<s> if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , <STR_LIT> ) , N0 , DAG . getConstant ( Log2_64


<s> unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; if ( ( Opcode == Instruction :: Load && ( ! isLegalMaskedGather ( SrcVTy , Align ( Alignment ) ) || forceScalarizeMaskedGather ( cast < VectorType > ( SrcVTy ) , Align ( Alignment ) ) ) ) || ( Opcode == Instruction :: Store && ( ! isLegalMaskedScatter ( SrcVTy , Align ( Alignment ) ) || forceScalarizeMaskedScatter ( cast < VectorType > ( SrcVTy ) , Align ( Alignment ) ) ) ) ) return getGSScalarCost

( Opcode , SrcVTy , VariableMask , Alignment , AddressSpace ) ;


<s> static void ix86_adjust_counter ( rtx countreg , HOST_WIDE_INT value ) { if ( GET_MODE ( countreg ) == DImode ) emit_insn ( gen_adddi3 ( countreg , countreg , GEN_INT ( - value ) ) ) ; else emit_insn ( gen_addsi3 ( countreg , countreg


<s> <ISA_LIT>InstrInfo :: BranchType <ISA_LIT>InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = <NUM_LIT> ; MachineInstr * SecondLastInst = nullptr ; if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> )


<s> SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> cast < MachineSDNode > ( Load ) -> setMemRefs ( MMOs . first , MMOs . second ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; BeforeOps . insert ( BeforeOps . end ( ) , AfterOps . begin ( ) , AfterOps . end ( ) ) ; SDNode * NewNode = DAG . getMachineNode ( Opc , dl , VTs , BeforeOps ) ; NewNodes . push_back ( NewNode ) ; if ( FoldedStore ) { AddrOps . pop_back ( ) ; AddrOps . push_back ( SDValue ( NewNode , <NUM_LIT> ) ) ; AddrOps . push_back ( Chain ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractStoreMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = RC -> getSize ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= Alignment ; SDNode * Store = DAG . getMachineNode ( getStoreRegOpcode ( <NUM_LIT> , DstRC , isAligned , Subtarget ) , dl , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Store ) ; cast < MachineSDNode > ( Store ) -> setMemRefs ( MMOs .


<s> SmallVectorImpl < MachineInstr * > & getInsts ( ) { return


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Error ( L ,