<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( SaveLocation ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( SaveLocation ) ) ; } getStreamer ( ) . EmitInstruction ( Inst ,


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned UnitSize , bool isUnary ) { if ( ! isUnary ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT>


<s> MachineFunction * F = MBB -> getParent ( ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = MBB -> getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> )

. getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ;


<s> if ( ! cfun -> machine -> has_gp_insn_p ) { rtx insn ; push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && ( get_attr_got ( insn ) != GOT_UNSET || small_data_pattern

( PATTERN ( insn ) , VOIDmode ) ) ) break ;


<s> static bool isVZIPMask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Idx = WhichResult * NumElts


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>LEAsmBackend ) ; } for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T ,


<s> if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; return ParseIntelSegmentOverride ( RegNo , Start


<s> if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , <NUM_LIT> ) ) ; regno = REGNO ( XEXP ( use , <NUM_LIT>


<s> void EmitAttribute ( unsigned Attribute , unsigned Value ) { Contents += Attribute ; Contents += Value


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned FrameReg = <STR_LIT> ; unsigned stackBias = Subtarget -> getStackPointerBias ( ) ; SDValue FrameAddr ; if ( depth == <NUM_LIT> ) { FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; if ( Subtarget -> is64Bit ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( stackBias , dl ) ) ; return FrameAddr ; } SDValue Chain = getFLUSHW ( Op , DAG ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? ( stackBias + <NUM_LIT> ) : <NUM_LIT> ; while ( depth -- ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; FrameAddr = DAG . getLoad ( VT , dl , Chain , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , dl


<s> } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = <NUM_LIT> , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this


<s> case <STR_LIT> : case <STR_LIT> : { unsigned Pred ; switch ( IntrinsicID ) { case <STR_LIT> : Pred = <STR_LIT> ; break ; case <STR_LIT> : Pred = <STR_LIT> ; break ; case <STR_LIT> : Pred = <STR_LIT> ; break ; case <STR_LIT> : Pred = <STR_LIT> ; break ; } return SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , { SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getTargetConstant ( Pred , dl , <STR_LIT> ) } ) , <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned CmprOpc = <STR_LIT> ; if ( IntrinsicID == <STR_LIT> ) CmprOpc = <STR_LIT> ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , { SDValue ( DAG . getMachineNode ( CmprOpc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ) , <NUM_LIT> ) ; } case <STR_LIT> : { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! Subtarget . hasVSX ( ) || ( ! Subtarget . hasFloat128 ( ) && VT == <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { RTLIB :: Libcall LC = IntrinsicID == <STR_LIT> ? RTLIB :: CONVERT_<ISA_LIT>F128_F128 : RTLIB :: CONVERT_F128_<ISA_LIT>F128 ; MakeLibCallOptions CallOptions ; std :: pair < SDValue , SDValue > Result = makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , dl , SDValue ( ) ) ; return Result . first ; } } int CompareOpc


<s> assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Out ) . addReg ( DReg ) . addReg ( ToInsert ) . addImm ( Lane ) ; return Out


<s> static __inline qword si_ahi ( qword a , short b ) { return ( ( qword ) ( vec_add ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case <STR_LIT> : expandRetRA ( MBB , MI ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned Opcode = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT SVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned EltSizeInBits = SVT . getSizeInBits ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT OpEltVT = OpVT . getVectorElementType ( ) ; unsigned OpEltSizeInBits = OpEltVT . getSizeInBits ( ) ; unsigned InputBits = OpEltSizeInBits * NumElts ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op , OpEltSizeInBits , UndefElts , EltBits ) ) { APInt Undefs ( NumElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > Vals ( NumElts , APInt ( EltSizeInBits , <NUM_LIT> ) ) ; bool IsZEXT = ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { Undefs . setBit ( i ) ; continue ; } Vals [ i ] = IsZEXT ? EltBits [ i ] . zextOrTrunc ( EltSizeInBits ) : EltBits [ i ] . sextOrTrunc ( EltSizeInBits ) ; } return getConstVector ( Vals , Undefs , VT , DAG , DL ) ; } SDValue V = peekThroughBitcasts ( Op


<s> static SDValue GetGlobalReg ( SelectionDAG & DAG , EVT Ty ) { <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return DAG . getRegister ( FI ->


<s> unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TmpReg = Inst . getOperand ( <NUM_LIT> ) .


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( )


<s> e = XVECEXP ( p , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( e ) == SET && MEM_P ( SET_DEST ( e ) ) && REG_P ( SET_SRC ( e ) ) ) ; reg = REGNO ( SET_SRC ( e ) ) ; gcc_assert ( reg >= lastreg ) ; if ( i != <NUM_LIT> ) fprintf ( out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( reg ) ) asm_fprintf ( out_file , <STR_LIT> , ( reg - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else if ( IS_PAC_REGNUM ( reg ) ) asm_fprintf ( asm_out_file , <STR_LIT> ) ; else asm_fprintf ( out_file , <STR_LIT> , reg ) ; if ( flag_checking ) { e = XEXP ( SET_DEST ( e ) , <NUM_LIT> ) ; if ( GET_CODE ( e ) == PLUS ) gcc_assert ( REG_P ( XEXP ( e , <NUM_LIT> ) ) && REGNO ( XEXP ( e , <NUM_LIT> ) ) == SP_REGNUM && CONST_INT_P ( XEXP ( e , <NUM_LIT> ) ) && offset == INTVAL ( XEXP ( e , <NUM_LIT> ) ) ) ; else gcc_assert ( i == <NUM_LIT> && REG_P ( e ) && REGNO ( e ) == SP_REGNUM ) ; offset +=


<s> return ( __m128i ) __builtin_ia32_vpcomgtb ( ( __v16qi ) __A , (


<s> Value * <ISA_LIT>IREmitter :: visitVST3_UPD ( const


<s> const uint8_t * <ISA_LIT>CA53ErratumStub :: getContent ( ) const { return reinterpret_cast < const uint8_t * > ( m_pData


<s> void \ toc_section ( ) \ { \ if ( TARGET_MINIMAL_TOC ) \ { \ \ if ( ! toc_initialized ) \ { \ fputs ( <STR_LIT> , asm_out_file ) ; \ fputs ( <STR_LIT> , asm_out_file ) ; \ toc_initialized = <NUM_LIT> ; \ } \ \ if ( in_section != toc ) \ fprintf ( asm_out_file , <STR_LIT> , \ ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> ) ) ; \ } \ else \ { \ if ( in_section != toc

) \ fputs ( <STR_LIT> , asm_out_file ) ; \ } \ in_section = toc ; \ }


<s> SetError ( SMLoc ( ) , <STR_LIT> ) ; return AsmToken ( AsmToken :: Error , <STR_LIT> , <NUM_LIT> ) ; } switch ( AsmInfo . getAssemblerDialect ( ) ) { default : SetError ( SMLoc ( ) , <STR_LIT> ) ; return AsmToken ( AsmToken :: Error , <STR_LIT> , <NUM_LIT> ) ; case <NUM_LIT> : return LexTokenATT ( )


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType


<s> void \ rdata_section ( ) \ { \ if ( in_section != in_rdata ) \ { \ if ( mips_abi != ABI_32 && mips_abi != ABI_O64 ) \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP_64 ) ; \ else \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP_32 ) ; \ in_section


<s> isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ; } return false


<s> case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << <STR_LIT> ; return false ; case MachineOperand :: MO_Register : O << '(' ; PrintOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } case 'c' : switch ( MO . getType ( ) ) { default : PrintOperand ( MI , OpNo , O ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , O ) ; break ; } return false ; case 'A' : if ( MO . isReg ( )


<s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( is64Bit ( ) ) Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT>


<s> label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_pic_add_dot_plus_eight ( reg


<s> const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ; int RegNodeSize = getSEHRegistrationNodeSize ( Fn ) ; SDValue RegNodeBase = DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP ,

DAG . getConstant ( RegNodeSize , dl , PtrVT ) ) ;


<s> static HOST_WIDE_INT arm_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { unsigned int factor = ( TARGET_THUMB || ! arm_tune_xscale ? <NUM_LIT> : <NUM_LIT> ) ; if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD * factor ) ; return align


<s> MachineBasicBlock * MBB = & * MFI ; if ( MBB -> getNumber ( ) > <NUM_LIT> ) { unsigned AlignExtra = GetAlignmentAdjustment ( * MBB , FuncSize ) ; auto & BS = BlockSizes [ MBB -> getNumber ( ) - <NUM_LIT> ] ; BS . first += AlignExtra ; BS . second = AlignExtra ; FuncSize += AlignExtra ; } unsigned BlockSize = <NUM_LIT> ; unsigned UnalignedBytesRemaining = <NUM_LIT> ; for ( MachineInstr & MI : * MBB ) { unsigned MINumBytes = TII -> getInstSizeInBytes ( MI ) ; if ( MI . isInlineAsm ( ) && ( FirstImpreciseBlock < <NUM_LIT> ) ) FirstImpreciseBlock = MBB -> getNumber ( ) ; if ( TII -> isPrefixed ( MI . getOpcode ( ) ) ) { NumPrefixed ++ ; if ( !


<s> return CallConv == CallingConv :: Fast


<s> else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; else if ( ConstraintCode == <STR_LIT> ) return


<s> case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , false ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , false ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ) ; case <NUM_LIT> : return combineMulMulAddOrSub ( false ) ; case <NUM_LIT> : return combineMulMulAddOrSub ( true ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulMulAddOrSub ( true ) ) ; case <NUM_LIT>


<s> } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) ,


<s> const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; } else { MIB . addOperand ( MO ) ; } } MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MBB -> insert ( InsertPt , NewMI ) ; return


<s> void <ISA_LIT>ExpandISEL :: initialize ( MachineFunction & MFParam ) { MF = & MFParam ; TII = MF -> getSubtarget ( ) . getInstrInfo


<s> TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T ,


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSORegMemOperand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler


<s> void addDispRIOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( isIntrinsic ) Cnt = -


<s> bool <ISA_LIT>16TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { return


<s> if ( GlobalAddressSDNode * N = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , Op . getDebugLoc ( ) , Ty , <NUM_LIT> , Flag ) ; if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) ,


<s> unsigned e = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ]


<s> unsigned SubSizeInBits = SrcVT . getSizeInBits ( ) ; SDValue Lo = extractSubVector ( MinPos , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( MinPos , NumSubElts , DAG , DL , SubSizeInBits ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , getZeroVector ( <STR_LIT> , Subtarget , DAG , DL ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LibCall = is64Bit ? <STR_LIT> : <STR_LIT> ; break ; } auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( LibCall , PtrVT ) ; Type * RetTy = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; ArgListTy Args ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = LowerF128_LibCallArg ( Chain , Args , LHS , DL , DAG ) ; Chain = LowerF128_LibCallArg ( Chain , Args , RHS , DL , DAG ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> ,


<s> return ( isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ) || ( isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_FLOAT128_TYPE ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } builtin_define ( <STR_LIT> ) ; RS6000_CPU_CPP_ENDIAN_BUILTINS ( ) ; if ( TARGET_LONG_DOUBLE_128 ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; if ( TARGET_IEEEQUAD ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } else builtin_define ( <STR_LIT> ) ; } switch ( TARGET_CMODEL ) { case CMODEL_MEDIUM : builtin_define ( <STR_LIT> ) ; break ; case CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } switch ( rs6000_current_abi ) { case ABI_V4 : builtin_define ( <STR_LIT> ) ; break ; case ABI_AIX : builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> )


<s> return slots - ( ia64_rse_slot_num ( bspstore )


<s> } } break ; } case <STR_LIT> : { KnownBits Known2 ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; if ( Known . countMinLeadingZeros ( ) < BitWidth ) Known . resetAll ( ) ; Known = Known . trunc ( BitWidth ) ; break ; } case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; EVT SrcVT = N0 . getValueType ( ) ; unsigned InNumElts = SrcVT . getVectorNumElements ( ) ; unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ; assert ( InNumElts >= NumElts && <STR_LIT> ) ; Known = KnownBits ( InBitWidth ) ; APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ; DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + <NUM_LIT> ) ; Known = Known . zext ( BitWidth ) ; Known . Zero . setBitsFrom ( InBitWidth ) ; break ; } case <STR_LIT> : { DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) break ; KnownBits Known2 ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } case <STR_LIT> : if ( Op . getResNo ( ) != <NUM_LIT> ) break ; Known . Zero . setBitsFrom ( <NUM_LIT> ) ; break ; } if ( isTargetShuffle ( Opc ) ) { bool IsUnary


<s> if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( <STR_LIT> ) ; else Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) && MF . getTarget ( ) . getRelocationModel (


<s> if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ; return new ELF<ISA_LIT>AsmBackend ( T , IsLittleEndian


<s> __vector float vf1 ; vc16 = ( __vector unsigned char ) ( __vector unsigned long long ) { __A , __A } ; vs8 = ( __vector unsigned short ) vec_mergel ( vc16 , zero ) ; vi4 = ( __vector unsigned int ) vec_mergeh ( vs8 ,


<s> static void adjustForSubtraction ( SelectionDAG & DAG , const SDLoc & DL , Comparison & C ) { if ( C . CCMask == <STR_LIT> || C . CCMask == <STR_LIT> ) { for ( auto I = C . Op0 -> use_begin ( ) , E = C . Op0


<s> rtx_mode_t val ( elt , int_mode ) ; wide_int pow2 = wi :: neg ( val ) ; if ( val != pow2 ) { if ( negate == ! wi :: neg_p ( val ) ) return NULL_RTX ; negate = wi :: neg_p ( val ) ; if ( ! negate ) pow2 = val ; } int shift = wi :: exact_log2 ( pow2 ) ; if ( shift < <NUM_LIT> ) return NULL_RTX ; builder . quick_push ( gen_int_mode ( shift , int_mode ) ) ; } if ( negate == - <NUM_LIT> ) code = PLUS ; else if ( negate == <NUM_LIT> ) code = code ==


<s> static DecodeStatus DecodeSimm19Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler *


<s> else move_vec = gen_rtvec ( <NUM_LIT> , src ) ; move_unspec = gen_rtx_UNSPEC ( V2DImode , move_vec , UNSPEC_IEEE128_MOVE ) ; emit_insn ( gen_rtx_SET ( tmp , move_unspec ) ) ; cvt_vec = gen_rtvec ( <NUM_LIT> , tmp ) ; cvt_unspec = gen_rtx_UNSPEC ( DImode , cvt_vec , UNSPEC_IEEE128_CONVERT ) ; cvt = gen_rtx_fmt_e ( code , GET_MODE ( dest )


<s> const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocReg ( Reg , S ) ) ; return


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( )


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RTB = DAG . getNode ( <STR_LIT> , dl , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RTB ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 (


<s> inline bool is_so_imm_not ( unsigned Imm ) const { return <STR_LIT> ( ~ Imm


<s> RegSizes [ <STR_LIT> ] = <NUM_LIT> ; RegSizes [ <STR_LIT> ] = <NUM_LIT> ; RegSizes [ <STR_LIT> ] =


<s> case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : case <STR_LIT> :: ARMV8_7A : case <STR_LIT> :: ARMV8R : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; } } else if ( NoCrypto ) { switch ( ArchKind ) { default : case <STR_LIT> :: ARMV8_1A : case <STR_LIT> :: ARMV8_2A : case <STR_LIT> :: ARMV8_3A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : case <STR_LIT> ::


<s> if ( regno == LO_REGNUM ) return LO_REGS ; if ( regno == HI_REGNUM ) return HI_REGS ; return NO_REGS


<s> ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( Op ) -> getMask ( ) ; if ( VT . getVectorElementType ( ) != V0 . getValueType ( ) . getVectorElementType ( ) || VT . getVectorElementType ( ) != V1 . getValueType ( ) . getVectorElementType ( ) ) return SDValue ( ) ; bool SplitV0 = V0 . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ; if ( ! isConcatMask ( Mask , VT , SplitV0 ) ) return SDValue ( ) ; EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; if ( SplitV0 ) { V0 = DAG . getNode ( <STR_LIT> , DL , CastVT , V0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( V1 . getValueType ( ) . getSizeInBits ( )


<s> assert ( TargetTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; return lowerSymbolOperandELF ( MO ,


<s> } unsigned int imm16 = val32 & <NUM_LIT> ; if ( imm16 == ( val32 >> <NUM_LIT> ) ) for ( unsigned int shift = <NUM_LIT> ; shift < <NUM_LIT> ; shift += <NUM_LIT> ) if ( ( imm16 & ( <NUM_LIT> << shift ) ) == imm16 ) { if ( info ) * info = simd_immediate_info ( HImode , imm16 >> shift , insn , simd_immediate_info :: LSL , shift ) ; return true ; } if ( which == AARCH64_CHECK_MOV ) for ( unsigned int shift = <NUM_LIT> ; shift < <NUM_LIT> ; shift += <NUM_LIT> ) { unsigned int low = ( <NUM_LIT> << shift ) - <NUM_LIT> ; if ( ( ( val32 & ( <NUM_LIT> << shift ) ) | low ) == val32 ) { if ( info ) * info = simd_immediate_info ( SImode , val32 >> shift , insn , simd_immediate_info :: MSL , shift ) ; return true ; } } return false


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , HOST_WIDE_INT val ) { rtx c = gen_int_mode ( val , GET_MODE_INNER (


<s> if ( ! ( ValVT . isFloatingPoint ( ) || ( ValVT . isVector ( ) && ValVT . getSizeInBits ( ) >= <NUM_LIT> ) ) ) { return false ; } if ( ArgFlags . isHva ( ) ) return true ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ; Op -> Imm . Val =


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned & ValNo , EVT & ValVT , EVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo


<s> break ; case CC_DLTmode : ne = AARCH64_LT ; eq = AARCH64_GE ; break ; case CC_DGTmode : ne = AARCH64_GT ; eq = AARCH64_LE ; break ; case CC_DLEmode : ne = AARCH64_LE ; eq = AARCH64_GT ; break ; case CC_DGEUmode : ne = AARCH64_CS ; eq = AARCH64_CC ; break ; case CC_DLTUmode : ne = AARCH64_CC ; eq = AARCH64_CS ; break ; case CC_DGTUmode : ne = AARCH64_HI ; eq = AARCH64_LS ; break ; case CC_DLEUmode : ne = AARCH64_LS ; eq = AARCH64_HI ; break ; case CCmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_GE ; case GT : return AARCH64_GT ; case LE : return AARCH64_LE ; case LT : return AARCH64_LT ; case GEU : return AARCH64_CS ; case GTU : return AARCH64_HI ; case LEU : return AARCH64_LS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case CC_SWPmode : case CC_ZESWPmode : case CC_SESWPmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_LE ; case GT : return AARCH64_LT ; case LE : return AARCH64_GE ; case LT : return AARCH64_GT ; case GEU : return AARCH64_LS ; case GTU : return AARCH64_CC ; case LEU : return AARCH64_CS ; case LTU : return AARCH64_HI ; default : return - <NUM_LIT> ; } break ; case CC_NZmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_PL ; case LT : return AARCH64_MI ; default : return


<s> return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset


<s> bool save_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( crtl -> calls_eh_return && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC

&& TARGET_MINIMAL_TOC ) ) ) return true ;


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode2Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ->

addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> ++ FilledSlots ; Changed = true ; InstrIter D ; if ( ! DisableDelaySlotFiller && ( TM . getOptLevel ( ) != CodeGenOpt :: None ) && findDelayInstr ( MBB , I , D ) ) { MBB . splice ( llvm :: next ( I ) , & MBB , D ) ; ++ UsefulSlots ; } else BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LastFiller = ++


<s> int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || Val == std :: numeric_limits


<s> vqdmulh_n_s32 ( int32x2_t a , int32_t b ) { int32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> if ( Subtarget . has<ISA_LIT>64 ( ) ) return Subtarget . has<ISA_LIT>64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . has<ISA_LIT>32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_CheriPureCap ( ) ) return CSR_Cheri_Purecap_SaveList ; if ( Subtarget . isCheri ( ) ) return CSR_N64_Cheri_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList


<s> return ( NoFramePointerElim || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( )

|| ( MMI && MMI -> callsUnwindInit ( ) ) ) ;


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > (


<s> if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } } for ( int Half = <NUM_LIT> ; Half < <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , HalfSize ,


<s> OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear (


<s> case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerDivRem ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFPOWI ( Op , * Subtarget ,


<s> unsigned DestReg = getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ; MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT>


<s> static void emit_unlikely_jump ( rtx insn ) { rtx_insn * jump = emit_jump_insn


<s> SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; <STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ; EVT CarryVT = Carry . getValueType ( ) ; APInt NegOne = APInt :: getAllOnesValue ( CarryVT . getScalarSizeInBits ( ) ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getConstant ( NegOne , DL , CarryVT ) ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry . getValue ( <NUM_LIT> ) ) ; SDValue SetCC = getSETCC ( CC , Cmp . getValue ( <NUM_LIT> ) , DL , DAG ) ; if ( Op . getSimpleValueType ( ) == <STR_LIT> ) return DAG . getNode

( <STR_LIT> , DL , <STR_LIT> , SetCC ) ;


<s> build_target . isa = sbitmap_alloc ( isa_num_bits ) ; arm_configure_build_target ( & build_target , targ_options , false ) ; if ( build_target . core_name && ! bitmap_bit_p ( build_target . isa , isa_bit_quirk_no_asmcpu ) ) { const char * truncated_name = arm_rewrite_selected_cpu ( build_target . core_name ) ; asm_fprintf ( stream , <STR_LIT> , truncated_name ) ; } const arch_option * arch = arm_parse_arch_option_name ( all_architectures , <STR_LIT> , build_target . arch_name ) ; auto_sbitmap opt_bits ( isa_num_bits ) ; gcc_assert ( arch ) ; if ( strcmp ( build_target . arch_name , <STR_LIT> ) == <NUM_LIT> ) { asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; } else asm_fprintf ( stream , <STR_LIT> , build_target . arch_name ) ; const char * fpu_name = ( TARGET_SOFT_FLOAT ? <STR_LIT> : arm_identify_fpu_from_isa ( build_target . isa ) ) ; asm_fprintf ( stream , <STR_LIT> , fpu_name ) ; if ( ! arch -> common . extensions ) return ; for ( const struct cpu_arch_extension * opt = arch -> common . extensions ; opt -> name != NULL ; opt ++ ) { if ( ! opt ->


<s> ptr += ( ( ( * ptr ) >> <NUM_LIT> ) & <NUM_LIT> ) + <NUM_LIT> ; return ptr


<s> const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= <NUM_LIT> && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses (

<STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ;


<s> } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , <STR_LIT> ) ; break ; } GlobalAddressSDNode * GA = <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; while ( <NUM_LIT> ) { if ( ( GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) ) { Offset += GA -> getOffset ( ) ; break ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += - C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ; } } return ; } if ( hasMemory ) Op = LowerGlobalAddress ( GA -> getGlobal ( ) , Op . getDebugLoc ( ) , Offset


<s> SDValue Operand = StoredVal . getOperand ( <NUM_LIT> ) ; auto * OperandC = dyn_cast < ConstantSDNode > ( Operand ) ; if ( ! OperandC ) return false ; auto OperandV = OperandC -> getAPIntValue ( ) ; if ( NegateOperand ) OperandV = - OperandV ; if ( OperandV . getMinSignedBits ( ) > <NUM_LIT> ) return false ; Operand = CurDAG -> getTargetConstant ( OperandV , DL , MemVT ) ; SDValue Base , Disp ; if ( ! selectBDAddr20Only ( StoreNode -> getBasePtr ( ) , Base , Disp ) ) return false ; SDValue Ops [ ] = { Base , Disp , Operand , InputChain } ; MachineSDNode * Result = CurDAG -> getMachineNode ( NewOpc , DL , <STR_LIT> , <STR_LIT> , Ops ) ; CurDAG -> setNodeMemRefs ( Result , { StoreNode -> getMemOperand ( ) , LoadNode -> getMemOperand ( ) } ) ; ReplaceUses ( SDValue ( StoreNode , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( StoredVal . getNode ( ) , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode (


<s> V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { if ( SDValue NegVal = isFNEG ( DAG , V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { NegVal = DAG . getBitcast ( V . getOperand ( <NUM_LIT> ) . getValueType ( ) , NegVal ) ; V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegVal , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , NegA != NegB ,


<s> SMLoc S , E ; assert ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) && <STR_LIT> ) ; S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & BaseRegTok = Parser . getTok ( ) ; int BaseRegNum = tryParseRegister ( ) ; if ( BaseRegNum == - <NUM_LIT> ) return Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Colon ) && ! Tok . is ( AsmToken :: Comma ) && ! Tok . is ( AsmToken :: RBrac ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; if ( Tok . is ( AsmToken :: RBrac ) ) { E = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , nullptr , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , false , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } assert ( ( Tok . is ( AsmToken :: Colon ) || Tok . is ( AsmToken :: Comma ) ) && <STR_LIT> ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . is ( AsmToken :: Colon ) ) { Parser . Lex ( ) ; E = Parser . getTok ( ) . getLoc ( ) ; SMLoc AlignmentLoc = Tok . getLoc ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE ) return Error ( E , <STR_LIT> ) ; unsigned Align = <NUM_LIT> ; switch ( CE -> getValue ( ) ) { default : return Error ( E , <STR_LIT> ) ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> static bool nds32_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x )


<s> if ( vcall_offset != <NUM_LIT> ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } rtx funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( long_call_p ) { emit_move_insn ( temp , funexp ) ; funexp = temp ; } funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; if (


<s> unsigned getFloatingPointParmsNum ( ) const { return


<s> static int aarch64_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; bool fp = false ; if ( vectype != NULL ) fp = FLOAT_TYPE_P ( vectype ) ; switch ( type_of_cost ) { case scalar_stmt : return fp ? costs -> scalar_fp_stmt_cost : costs -> scalar_int_stmt_cost ; case scalar_load : return costs -> scalar_load_cost ; case scalar_store : return costs -> scalar_store_cost ; case vector_stmt : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vector_load : return costs -> vec_align_load_cost ; case vector_store : return costs -> vec_store_cost ; case vec_to_scalar : return costs -> vec_to_scalar_cost ; case scalar_to_vec : return costs -> scalar_to_vec_cost ; case unaligned_load : case vector_gather_load : return costs -> vec_unalign_load_cost ; case unaligned_store : case vector_scatter_store : return costs -> vec_unalign_store_cost ; case cond_branch_taken : return costs -> cond_taken_branch_cost ; case cond_branch_not_taken : return costs -> cond_not_taken_branch_cost ; case vec_perm : return costs -> vec_permute_cost ; case vec_promote_demote : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vec_construct : elements = estimated_poly_value ( TYPE_VECTOR_SUBPARTS ( vectype ) ) ; return elements / <NUM_LIT> + <NUM_LIT> ; default : gcc_unreachable (


<s> sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = <NUM_LIT> ; } } if ( cfun -> machine -> naked_p ) return ; Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; en4_const = <NUM_LIT> ; if ( cfun -> machine -> fp_size ) en4_const += <NUM_LIT> ; if ( cfun -> machine -> gp_size ) en4_const += <NUM_LIT> ; if ( cfun -> machine -> lp_size ) en4_const += <NUM_LIT> ; if ( ! ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM && en4_const == <NUM_LIT> ) ) { nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( en4_const ) , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; fp_adjust_insn = gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_adjust ) ) ; fp_adjust_insn = emit_insn ( fp_adjust_insn ) ; RTX_FRAME_RELATED_P ( fp_adjust_insn ) = <NUM_LIT> ; } sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = nds32_force_addi_stack_int ( ( - <NUM_LIT> ) * sp_adjust ) ; if (


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> static SDValue LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue VAList = DAG . getLoad ( <STR_LIT> , dl , InChain , VAListPtr , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG . getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> ,


<s> if ( tls_symbolic_operand_type ( x ) == <NUM_LIT> ) { HOST_WIDE_INT addend = <NUM_LIT> ; rtx op = x ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { addend = INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; op = XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; } if ( any_offset_symbol_operand ( op , mode ) || function_operand ( op , mode ) ) return true ; if ( aligned_offset_symbol_operand ( op , mode ) ) return ( addend & <NUM_LIT> ) == <NUM_LIT> ; return false ; } return false ; case CONST_VECTOR : if ( mode == V2SFmode )


<s> int reloc = <NUM_LIT> ; switch ( TREE_CODE ( exp ) ) { case ADDR_EXPR : return <NUM_LIT> ; case POINTER_PLUS_EXPR : case PLUS_EXPR : case MINUS_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , <NUM_LIT> ) ) ; reloc |= pa_reloc_needed ( TREE_OPERAND ( exp , <NUM_LIT> ) ) ; break ; CASE_CONVERT : case NON_LVALUE_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , <NUM_LIT> ) ) ; break ; case CONSTRUCTOR


<s> NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit (


<s> return CurDAG -> getMachineNode ( Opcode , DL , ResTypes , Ops ) ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return nullptr ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return nullptr ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( Subtarget -> isMClass


<s> unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI ) ; MRI -> constrainRegClass ( EvenReg , TRC ) ; MRI -> constrainRegClass ( OddReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg , <STR_LIT> , EvenReg ) ; } else


<s> RegDefsUses RegDU ( TM ) ; NoMemInstr NM ; Iter Filler ; RegDU . setCallerSaved ( * Slot ) ; if ( ! searchRange ( MBB , std :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Filler , Slot ) ) return false ; MBB . splice ( std :: next ( Slot )


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> void <ISA_LIT>AsmPrinter :: LowerJumpTableDestSmall ( llvm :: MCStreamer & OutStreamer , const llvm :: MachineInstr & MI ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchRegW = STI -> getRegisterInfo ( ) -> getSubReg ( ScratchReg , <STR_LIT> ) ; Register TableReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register EntryReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int JTIdx = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool IsByteEntry = MI . getOpcode ( ) == <STR_LIT> ; auto Label = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getJumpTableEntryPCRelSymbol (


<s> } for ( auto & BG : BitGroups ) { if ( ! Res ) Res = SelectRotMask64 ( BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; else Res = SelectRotMaskIns64 ( Res , BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; } if ( LateMask ) { uint64_t Mask = getZerosMask ( ) ; bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += getInt64Count ( Mask ) + <NUM_LIT> ; SDValue MaskVal = SDValue ( getInt64 ( CurDAG , dl , Mask ) , <NUM_LIT> ) ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , MaskVal ) , <NUM_LIT> ) ; } } return Res .


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) { M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext (

) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ;


<s> if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; assert ( ! ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) && <STR_LIT> ) ; if ( isHiRegIdx ( Reg ) ) return


<s> Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . LookupSymbol ( Name ) ; if ( Sym ) return reportParseError ( <STR_LIT> ) ; Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; Sym -> setVariableValue ( Value ) ; return


<s> static bool is_adjacent_bb ( basic_block a , basic_block b ) { basic_block bb0 [ ] = { a , b } ; basic_block bb1 [ ] = { b , a } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) for ( edge_iterator ei = ei_start ( bb0 [


<s> int unspec = ( e . type_suffix ( <NUM_LIT> ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode


<s> if ( make_unique ) name_len += strlen ( unique_name ) + <NUM_LIT> ; global_var_name = XNEWVEC ( char , name_len ) ; if ( make_unique ) snprintf ( global_var_name , name_len , <STR_LIT> , name , unique_name , suffix ) ; else snprintf ( global_var_name , name_len , <STR_LIT> , name , suffix ) ; return global_var_name


<s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF


<s> ReduceEntryVector :: const_iterator Start = std :: begin ( ReduceTable ) ; ReduceEntryVector :: const_iterator End = std :: end ( ReduceTable ) ; std :: pair < ReduceEntryVector :: const_iterator , ReduceEntryVector :: const_iterator > Range = std :: equal_range ( Start , End , Opcode ) ; if ( Range . first == Range . second ) return false ; for ( ReduceEntryVector :: const_iterator Entry = Range . first ; Entry != Range . second ; ++ Entry ) { ReduceEntryFunArgs Arguments ( & ( * MII ) , * Entry , NextMII ) ; if ( ( ( * Entry ) . ReduceFunction ) ( & Arguments


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned Rm = CTX . getRegisterInfo ( ) . getEncodingValue ( MO1 . getReg ( ) ) ; unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ; bool isAdd = <STR_LIT> ( MO2 . getImm ( )


<s> Register DefDstReg = getSrcRegIgnoringCopies ( StoreMI . getValueReg ( ) , MRI ) ; if ( ! DefDstReg . isValid ( ) ) return false ; LLT DefDstTy = MRI . getType ( DefDstReg ) ; Register StoreSrcReg = StoreMI . getValueReg ( ) ; LLT StoreSrcTy = MRI . getType ( StoreSrcReg ) ; if ( ! DefDstTy . isValid ( ) ) return false ; if ( DefDstTy . getSizeInBits ( ) != StoreSrcTy . getSizeInBits ( ) ) return false ; if ( StoreSrcTy . getSizeInBits ( ) != StoreMI . getMemSizeInBits ( ) ) return false ; if ( RBI . getRegBank ( StoreSrcReg , MRI , TRI ) == RBI . getRegBank ( DefDstReg , MRI , TRI ) ) return false ; StoreMI . getOperand ( <NUM_LIT> ) . setReg ( DefDstReg ) ; return


<s> DebugLoc dl = Op . getDebugLoc ( ) ; AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( Subtarget -> hasXMMInt ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand (


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat ( )


<s> return ( int64x1_t ) { __builtin_aarch64_suqadddi_ssu ( __a [ <NUM_LIT> ] ,


<s> __builtin_ia32_pmovqw128mem_mask ( ( unsigned int * ) __P , ( __v2di ) __A ,


<s> if ( auto * Aliasee = dyn_cast < GlobalValue > ( GA -> getAliasee ( ) ) ) F = dyn_cast < Function > ( Aliasee ) ; } bool pagerandoBinTarget = F && F -> isPagerando ( ) ; if ( MF . getFunction ( ) . isPagerando ( ) || pagerandoBinTarget ) { return getPOT ( GN , DAG ) ; } if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , OpFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , OpFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { Result = getAddrTiny ( GN , DAG , OpFlags ) ; } else { Result = getAddr ( GN , DAG , OpFlags ) ; } EVT PtrVT = getPointerTy ( DAG


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckl ) ) UnpackOpcode = <STR_LIT> ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) UnpackOpcode = <STR_LIT> ; else return SDValue ( ) ; V1 = DAG . getVectorShuffle ( <STR_LIT> , DL , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getUNDEF ( <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getNode ( UnpackOpcode , DL , VT


<s> bool avoidQuadLdStPairs ( ) const { return AvoidQuadLdStPairs


<s> BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addMBB ( TargetMBB ) . addImm ( <NUM_LIT> ) ; return true ; } unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned char OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( OpFlags & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( )


<s> case PowerPCCC :: PL : return <STR_LIT> ; case PowerPCCC :: VS : return <STR_LIT> ; case PowerPCCC :: VC : return <STR_LIT> ; case PowerPCCC :: HI : return <STR_LIT> ; case PowerPCCC :: LS : return <STR_LIT> ; case PowerPCCC :: GE : return <STR_LIT> ; case PowerPCCC :: LT : return <STR_LIT> ; case PowerPCCC :: GT : return <STR_LIT> ; case PowerPCCC :: LE


<s> const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } if ( isSymbol ) { if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( StartInBrac , ErrMsg ) ; return nullptr ; } return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale , Start


<s> if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N .


<s> rewriteFrameIndex ( MachineInstr & MI , unsigned FrameRegIdx , unsigned FrameReg , int Offset , unsigned MOVOpc , unsigned ADDriOpc , unsigned SUBriOpc ) const { return <NUM_LIT>


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL_V2I64 ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO (


<s> static SDValue LowerMSCATTER ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; MaskedScatterSDNode * N = cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ; EVT VT = N -> getValue ( ) . getValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) { SDValue Index = N -> getIndex (


<s> bool MemDefsUses :: updateDefsUses ( ValueType V , bool MayStore ) { if ( MayStore ) return ! Defs . insert ( V ) . second || Uses . count ( V ) || SeenNoObjStore || SeenNoObjLoad ; Uses . insert ( V )


<s> unsigned llvm :: getBLXpredOpcode ( const MachineFunction & MF ) { return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ) ? <STR_LIT>


<s> unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeAddrMode7Operand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeGPRRegisterClass ( Inst , Val , Address , Decoder


<s> assert ( Kind == Memory && <STR_LIT>


<s> AFI -> setShouldRestoreSPFromFP ( true ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; Align MaxAlign = MF . getFrameInfo ( ) . getMaxAlign ( ) ; emitAligningInstructions ( MF , AFI , TII , MBB , MI , DL , <STR_LIT> , MaxAlign , true ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! isThumb ) MIB . add ( condCodeOp ( ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -=


<s> static SDValue combineTruncate ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( SDValue Avg = detectAVGPattern ( Src , VT , DAG , Subtarget , DL ) ) return Avg ; if ( Src . getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) { SDValue BCSrc = Src .


<s> unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( model == TLSModel :: InitialExec ) { if ( is64Bit ) { OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { OperandFlags = isPIC ? <STR_LIT> : <STR_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) { if ( isPIC &&


<s> const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; }


<s> void <ISA_LIT>DAGToDAGISel :: SelectPredicatedStore ( SDNode * N , unsigned NumVecs , const unsigned Opc_rr , const unsigned Opc_ri ) { SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = createZTuple ( Regs ) ; unsigned


<s> int64_t Value = CE -> getValue ( ) ; return Value >= MinValue && Value <= MaxValue ; } return false


<s> InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ) ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : ( is32BitMode ( ) ? <STR_LIT> : <STR_LIT> ) ; return <STR_LIT> ( RegNo , Start , End , true , OffsetOfLoc , Identifier , Info


<s> if ( code >= RX_BUILTIN_max ) return error_mark_node ; return rx_builtins [


<s> return ( vector signed char ) __builtin_altivec_vnor ( ( vector signed int ) a1 , ( vector signed int


<s> return STI . hasLoadStoreOnCond ( ) && getConditionalMove (


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u64 ( unsigned long long __X ) { return __builtin_ctzll ( __X


<s> bool isSibMem ( ) const { return isMem ( ) && Mem . BaseReg != <STR_LIT>


<s> if ( I -> getOpcode ( ) == <STR_LIT> && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! Dest ) { MBBStartOffset += TII -> getInstSizeInBytes ( * I ) ; continue ; } int BranchSize = computeBranchSize ( Fn , & MBB , Dest , MBBStartOffset ) ; if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr & OldBranch = * I ; DebugLoc dl = OldBranch . getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> Pred = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CRReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ( Pred ) ) . addReg ( CRReg ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { unsigned CRBit = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( CRBit ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { unsigned CRBit = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( CRBit ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get


<s> auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; bool Modified = false ; for ( Module :: iterator F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { if ( F -> hasFnAttribute ( <STR_LIT> ) && F -> hasFnAttribute ( <STR_LIT> ) ) { removeUseSoftFloat ( * F ) ; continue ; } if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) ||

F -> hasFnAttribute ( <STR_LIT> ) ) continue ;


<s> if ( mode == VOIDmode ) mode = DImode ; gcc_assert ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ; lowpart = gen_lowpart ( SImode , val ) ; highpart = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( CONST_INT_P ( lowpart ) ) ; gcc_assert ( CONST_INT_P (


<s> else if ( TREE_CODE ( TREE_VALUE ( args ) ) != STRING_CST ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( * this ) { Subtarget = static_cast < <ISA_LIT>TargetMachine & > ( TM )


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , false , Cnt ) ) { unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( VShiftOpc , dl , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; } EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ; unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( VShiftOpc , dl , VT , N -> getOperand (


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx ,


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Reg = <STR_LIT> ; MachineBasicBlock :: iterator MoveInstruction = BuildMI ( * BasicBlockIterator , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add (

MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_RegMask ; else return


<s> case SECCAT_DATA : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_BSS : sname = <STR_LIT> ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = <STR_LIT> ; flags = <NUM_LIT> ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS


<s> if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> ) O << <STR_LIT> << Imm ; else O << getRegisterName ( Reg ) ; } else assert ( <NUM_LIT>


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF , [ & ] ( Register Reg ) { llvm_unreachable ( <STR_LIT> ) ; } ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB


<s> else if ( Rs == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; HasRt = true ; } else if ( Rs == Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; HasRt = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; if ( HasRt ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success


<s> HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; stackAlignment = <NUM_LIT> ; MaxInlineSizeThreshold = <NUM_LIT>


<s> rtx_code_label * L_loop_byte = gen_label_rtx ( ) ; rtx_insn * jump ; rtx_code_label * L_loop_long = gen_label_rtx ( ) ; rtx_code_label * L_end_loop_long = gen_label_rtx ( ) ; int align = INTVAL ( operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( start_addr , current_addr ) ; if ( align < <NUM_LIT> ) { emit_insn ( gen_tstsi_t ( current_addr , GEN_INT ( <NUM_LIT> ) ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_move_insn ( tmp0 , operands [ <NUM_LIT> ] ) ; addr1 = adjust_automodify_address ( addr1 , SImode , current_addr , <NUM_LIT> ) ; emit_label ( L_loop_long ) ; emit_move_insn ( tmp1 , addr1 ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , <NUM_LIT> ) ) ; emit_insn ( gen_cmpstr_t ( tmp0 , tmp1 ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_long ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_end_loop_long ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , - <NUM_LIT> ) ) ; addr1 = adjust_address ( addr1 , QImode , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , <NUM_LIT> ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_true ( L_return ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_barrier_after ( jump ) ; emit_label ( L_loop_byte ) ; emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode


<s> bool <ISA_LIT>InstructionSelector :: selectVectorAshrLshr ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; bool IsASHR = I . getOpcode ( ) == TargetOpcode :: G_ASHR ; unsigned Opc = <NUM_LIT> ; unsigned NegOpc = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForTypeOnBank ( Ty , RBI . getRegBank ( <STR_LIT> ) , RBI ) ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT>


<s> char * newstr ; if ( DECL_WEAK ( decl ) && flag == SHORT_CALL_FLAG_CHAR ) return ; newstr = alloca ( len + <NUM_LIT> ) ; newstr [ <NUM_LIT> ] = flag ; strcpy ( newstr + <NUM_LIT> , str ) ; newstr = ( char * ) ggc_alloc_string ( newstr ,


<s> if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( Subtarget -> hasSSE2 ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op


<s> MCII ( mcii ) , Ctx ( Ctx_ ) , STI ( sti ) ,


<s> case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN


<s> static void ia64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; rtx this_rtx , funexp ; rtx_insn * insn ; unsigned int this_parmno ; unsigned int this_regno ; rtx delta_rtx ; reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT> ; last_scratch_gr_reg = <NUM_LIT> ; memset ( & current_frame_info , <NUM_LIT> , sizeof ( current_frame_info ) ) ; current_frame_info . spill_cfa_off = - <NUM_LIT> ; current_frame_info . n_input_regs = <NUM_LIT> ; current_frame_info . need_regstk = ( TARGET_REG_NAMES != <NUM_LIT> ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_parmno = ( ia64_struct_retval_addr_is_first_parm_p ( TREE_TYPE ( thunk ) ) ? <NUM_LIT> : <NUM_LIT> ) ; this_regno = IN_REG ( this_parmno ) ; if ( ! TARGET_REG_NAMES ) reg_names [ this_regno ] = ia64_reg_numbers [ this_parmno ] ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; delta_rtx = GEN_INT ( delta ) ; if ( TARGET_ILP32 ) { rtx tmp = gen_rtx_REG ( ptr_mode , this_regno ) ; REG_POINTER ( tmp ) = <NUM_LIT> ; if ( delta && satisfies_constraint_I ( delta_rtx ) ) { emit_insn ( gen_ptr_extend_plus_imm ( this_rtx , tmp , delta_rtx ) ) ; delta = <NUM_LIT> ; } else emit_insn ( gen_ptr_extend ( this_rtx , tmp ) ) ; } if ( delta ) { if ( ! satisfies_constraint_I ( delta_rtx ) ) { rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , delta_rtx ) ; delta_rtx = tmp ; } emit_insn ( gen_adddi3 ( this_rtx , this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( TARGET_ILP32 ) { rtx t = gen_rtx_REG ( ptr_mode , <NUM_LIT> ) ; REG_POINTER ( t ) = <NUM_LIT> ; emit_move_insn ( t , gen_rtx_MEM ( ptr_mode , this_rtx ) ) ; if ( satisfies_constraint_I ( vcall_offset_rtx ) ) { emit_insn ( gen_ptr_extend_plus_imm ( tmp , t , vcall_offset_rtx ) ) ; vcall_offset = <NUM_LIT> ; } else emit_insn ( gen_ptr_extend ( tmp , t ) ) ; } else emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( vcall_offset )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { expandLoadAddressSym ( DstRegOp , ImmOp , Is32BitImm , IDLoc , Instructions ) ; return false ; } if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ; return


<s> LocInfo = CCValAssign :: AExt ; if ( Offset % <NUM_LIT> == <NUM_LIT> ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return true


<s> if ( ! Fn -> hasPersonalityFn ( ) ) return EntryEBP ; int RegNodeSize = getSEHRegistrationNodeSize ( Fn ) ; MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: getRealLinkageName ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym ,


<s> if ( INSN_P ( insn ) ) replace_constant_pool_with_broadcast ( insn ) ; } timevar_pop (


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } SDNode * Result ; unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; if ( isInt < <NUM_LIT> > ( Imm ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Lo ) ) ; } else if ( Lo ) { unsigned OpC = Hi ? <STR_LIT> : <STR_LIT> ; Result = CurDAG -> getMachineNode ( OpC , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Lo ) ) ; } else { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm (


<s> __rv . __o = __builtin_neon_vld3_dupv8qi ( ( const __builtin_neon_qi * ) __a ) ; return __rv .


<s> void <ISA_LIT>RegisterSema :: updateEFLAGS ( Value * Def ) { LastEFLAGSChangingDef = <NUM_LIT> ; getReg ( <STR_LIT> ) ; LastEFLAGSChangingDef =


<s> return ( vector unsigned int ) __builtin_altivec_vsum4ubs ( ( vector signed char ) a1 , ( vector signed