<s> EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( ! IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> ) ; } else { JTI = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT


<s> if ( Opnd . getReg ( ) == DestReg ) { if ( Opnd . isDef ( ) || ! Opnd . isKill ( ) ) return MachineBasicBlock :: iterator ( ) ; unsigned AluOpcode = CurInst -> getOpcode ( ) ; if ( AluOpcode != AddOpcode && AluOpcode != SubOpcode ) return MachineBasicBlock :: iterator ( ) ; MachineOperand & Opnd2 = CurInst -> getOperand ( <NUM_LIT> - I ) ; MachineOperand AluDest = CurInst -> getOperand ( <NUM_LIT> ) ; if ( Opnd2 . getReg ( ) != AluDest . getReg ( ) ) return MachineBasicBlock :: iterator ( ) ; if ( ! CurInst -> registerDefIsDead ( <STR_LIT> , TRI ) ) return MachineBasicBlock :: iterator ( ) ; return


<s> SDValue _getGlobalCapBigImmediate ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , unsigned HiFlag , unsigned LoFlag , SDValue Chain , const MachinePointerInfo * PtrInfo , bool DoLoad , unsigned HiOpc ) const { SDValue Off = DAG . getNode ( HiOpc , DL , <STR_LIT> , getTargetNode ( N , <STR_LIT> , DAG , HiFlag ) ) ; Off = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Off , getTargetNode ( N , <STR_LIT> , DAG , LoFlag ) ) ; SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , CapType ,

getCapGlobalReg ( DAG , CapType ) , Off ) ;


<s> unsigned IsPCRelConstant = MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_Constant ; const static MCFixupKindInfo InfosLE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo


<s> return __builtin_mve_vld1q_uv16qi ( ( __builtin_neon_qi


<s> rtx cache = GEN_INT ( val ) ; for ( i = <NUM_LIT> ; i < nunits ; i


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> void ChangeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup (


<s> bool isSVEDataVectorReg ( ) const { return ( Kind == k_Register && Reg . Kind == RegKind :: SVEDataVector ) && <ISA_LIT>MCRegisterClasses [ Class ] . contains (


<s> return ; } assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue


<s> EmitMappingSymbol ( <STR_LIT> , EMS -> Loc , EMS -> F , EMS -> Offset ) ; EMS -> resetInfo (


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) if ( Mask [ i ] + <NUM_LIT> != Mask [ i + <NUM_LIT> ] ) return false ; return true


<s> case SFmode : case DFmode : case XFmode : case RFmode : return true ; case TFmode : return true


<s> } if ( flag_pic && CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { if ( pic_address_needs_scratch ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = sparc_legitimize_pic_address ( operands [ <NUM_LIT> ] , NULL_RTX ) ; if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == LABEL_REF && can_use_mov_pic_label_ref ( operands [ <NUM_LIT> ] ) ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && can_use_mov_pic_label_ref ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) { if ( mode == SImode ) { emit_insn ( gen_movsi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( mode == DImode ) { emit_insn ( gen_movdi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } } if ( symbolic_operand ( operands [ <NUM_LIT> ] , mode ) ) { operands [ <NUM_LIT> ] = sparc_legitimize_pic_address ( operands [ <NUM_LIT> ] , reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ; return false ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) && ( SPARC_FP_REG_P ( REGNO ( operands [ <NUM_LIT> ] ) ) || SCALAR_FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = CONST0_RTX ( mode ) ; if ( ( TARGET_VIS || REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG ) && ( const_zero_operand ( operands [ <NUM_LIT> ] , mode ) || const_all_ones_operand ( operands [ <NUM_LIT>


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; return false


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op ,


<s> else if ( isLoadAndTestAsCmp ( Compare ) ) reg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( reg


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass (


<s> } if ( ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } const RegisterBank * OpBank = RBI . getRegBank ( MO . getReg ( ) , MRI , TRI ) ; if ( ! OpBank ) { LLVM_DEBUG ( dbgs ( ) <<


<s> __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) val . val


<s> llvm :: reverse ( llvm :: make_range ( MBB . begin ( ) , TestPos ) ) ) { <STR_LIT> Cond = <STR_LIT> ( MI ) ; if ( Cond != <STR_LIT> && ! MI . mayStore ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) &&


<s> unsigned <ISA_LIT>CodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned opIdx


<s> bool AllIntFields = true ; for ( StringRef Field : Fields ) { unsigned IntField ; AllIntFields &= ! Field . trim ( <STR_LIT> ) . getAsInteger ( <NUM_LIT> , IntField ) ; Ops . push_back ( CurDAG -> getTargetConstant ( IntField , DL , <STR_LIT> ) ) ; } assert ( AllIntFields &&


<s> <ISA_LIT>TargetStreamer * XTS = static_cast < <ISA_LIT>TargetStreamer * > ( getTargetStreamer ( ) ) ; XTS -> emitFPOData ( ProcSym ,


<s> <STR_LIT> CondCode , CondCode2 ; if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( LHS , RHS ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>CC , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>CC = DAG . getConstant


<s> } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode (


<s> void <ISA_LIT>InstPrinter :: printS16ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << ( short ) MI -> getOperand


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction

( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> virtual <ISA_LIT>JITInfo * getJITInfo ( ) { return &


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLdDup ; if ( is64BitVector || NumVecs == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 ,


<s> if ( IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) ) fprintf (

file , HOST_WIDE_INT_PRINT_DEC , val ) ;


<s> SmallVector < RegDomain , <NUM_LIT> > getLegalDstDomains


<s> int <ISA_LIT>RegisterInfo :: getSEHRegNum ( unsigned i ) const { return getEncodingValue (


<s> return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) &


<s> bool isConstantSplat ( SDValue Op , APInt & SplatVal ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( <NUM_LIT> <= SplatIndex && EltBits [ i


<s> return CC == <STR_LIT> || CC == <STR_LIT> || CC ==


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS ) const { bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr


<s> void <ISA_LIT>IndirectBranchTrackingPass :: addENDBR ( MachineBasicBlock & MBB ) const { assert ( TII && <STR_LIT> ) ; assert ( ( <STR_LIT> == EndbrOpcode || <STR_LIT> == EndbrOpcode ) && <STR_LIT> ) ; auto MI = MBB . begin ( ) ; if ( MI == MBB . end ( ) || EndbrOpcode != MI -> getOpcode ( ) ) { BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , TII -> get ( EndbrOpcode ) ) ; NumEndBranchAdded ++


<s> void mips_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype ) { memset ( cum , <NUM_LIT> , sizeof ( * cum ) ) ; cum -> prototype = ( fntype && prototype_p ( fntype ) ) ; cum -> gp_reg_found = ( cum -> prototype && stdarg_p


<s> static AsmPrinter * create<ISA_LIT>AsmPrinterPass ( formatted_raw_ostream & o , TargetMachine & tm , MCStreamer & Streamer ) { const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isDarwin ( ) ) return new

<ISA_LIT>DarwinAsmPrinter ( o , tm , Streamer ) ;


<s> int32_t Imm = SignExtend32 < <NUM_LIT> > ( ( unsigned ) MI -> getOperand ( OpNo ) . getImm ( ) << <NUM_LIT> ) ; if ( Imm >= <NUM_LIT> ) O << <STR_LIT> ; O <<


<s> static unsigned AddLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { assert ( RC -> contains ( PReg ) && <STR_LIT> ) ; unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( Desc . TSFlags & <STR_LIT> ) return false ; static std :: atomic < bool > TableChecked ( false ) ; if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex128CompressTable ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI ) ) return false ; if ( usesDisp8Compression ( MI


<s> else gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_zext_2 : gen_divmodsi4_zext_2 ; } else gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_zext_1 : gen_divmodsi4_zext_1 ; break ; case E_DImode : gen_divmod4_1 = unsigned_p ? gen_udivmoddi4_1 : gen_divmoddi4_1 ; break ; default : gcc_unreachable ( ) ; } end_label = gen_label_rtx ( ) ; qimode_label = gen_label_rtx ( ) ; scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , operands [ <NUM_LIT> ] ) ; scratch = expand_simple_binop ( mode , IOR , scratch , operands [ <NUM_LIT> ] , scratch , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_test_ccno_1 ( mode , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp0 = gen_rtx_EQ ( VOIDmode , tmp0 , const0_rtx ) ; tmp0 = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp0 , gen_rtx_LABEL_REF ( VOIDmode , qimode_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp0 ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = qimode_label ; emit_insn ( gen_divmod4_1 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_jump_insn ( gen_jump ( end_label ) ) ; emit_barrier ( ) ; emit_label ( qimode_label


<s> static void aarch64_emit_sve_ptrue_op ( rtx target , rtx ptrue , rtx op ) { rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( <NUM_LIT> , ptrue , op ) ,


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm


<s> } else if ( MI -> isCopy ( ) ) { TileReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return getShape ( MRI , TileReg ) ; } assert ( MI -> isPHI ( )


<s> MulCandidate ( Instruction * I , ValueList & lhs , ValueList &


<s> if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isGP64 ( ) ) return DecodeGPR64RegisterClass ( Inst , RegNo ,


<s> void printMemOffs8 ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> <ISA_LIT>LegalizerInfo :: FCmpLibcallsList <ISA_LIT>LegalizerInfo :: getFCmpLibcalls ( CmpInst :: Predicate Predicate , unsigned Size ) const { assert ( CmpInst :: isFPPredicate ( Predicate


<s> static SDValue LowerMGATHER ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; MaskedGatherSDNode * N = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; EVT VT = Op . getValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Index = N -> getIndex ( ) ; if ( ! Subtarget -> hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getValueType ( ) . is512BitVector ( ) ) { Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ,

N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEven ( SMLoc L ) { const MCSection * Section = getStreamer ( ) . getCurrentSection ( ) . first ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ; return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; return false


<s> if ( Splat . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( Splat . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask || Mask -> getZExtValue ( ) != <NUM_LIT> ) return false ; return


<s> const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness ( ) const { return UseSubRegLiveness


<s> unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return


<s> static unsigned int nds32_function_arg_boundary ( machine_mode mode , const_tree type ) { return ( nds32_needs_double_word_align ( mode , type ) ? NDS32_DOUBLE_WORD_ALIGNMENT : PARM_BOUNDARY


<s> void setGPRSizeFromPredicates ( const PredicateLibrary & P


<s> return ShiftExtend . Amount == <NUM_LIT>


<s> static SDValue LowerFSINCOS ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( Subtarget . isTargetDarwin ( ) && Subtarget . is64Bit ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue CosVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult


<s> } else LLVMTargetMachine :: addAnalysisPasses ( PM ) ; DEBUG ( errs ( )


<s> inline SDValue getImm ( const SDNode * Node , uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm , Node -> getValueType (


<s> if ( Ty -> isVectorTy ( ) && SE ) { if ( ! BaseT :: isStridedAccess ( Ptr ) ) return NumVectorInstToHideOverhead ; if ( ! BaseT :: getConstantStrideStep ( SE , Ptr ) ) return <NUM_LIT> ; } return BaseT :: getAddressComputationCost ( Ty ,


<s> assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) { * ( unsigned char * ) ( RetAddr - <NUM_LIT> ) = <NUM_LIT> ; * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = diff & <NUM_LIT> ; } else { * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = NewVal ; ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] = ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; } sys :: ValgrindDiscardTranslations ( ( void * ) ( RetAddr - <NUM_LIT> ) , <NUM_LIT> ) ; ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ]


<s> unsigned SubRegIndex ; if ( RegSpc == EvenDblSpc ) { SubRegIndex = <STR_LIT> ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; SubRegIndex = <STR_LIT> ; } unsigned SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i !=


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg


<s> return ( __m512i ) __builtin_ia32_punpckhqdq512_mask ( ( __v8di ) __A , ( __v8di )


<s> static rtx gen_safe_SET64 ( rtx dest ,


<s> return nds32_address_cost_impl ( address , mode , as , speed


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , I . getFrameIdx ( ) , RC ,


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( IsPIC && ! GV -> hasLocalLinkage ( ) && ! GV -> hasHiddenVisibility ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) ) ; } uint8_t OpFlagHi = IsPIC ? <STR_LIT> : <STR_LIT> ; uint8_t OpFlagLo = IsPIC ? <STR_LIT> : <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , dl


<s> static bool sh_strict_argument_naming ( cumulative_args_t ca ATTRIBUTE_UNUSED ) { return false


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { bool NeedsWinCFI = needsWinCFI (


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> emitRI ( <STR_LIT> , TmpReg , HiOffset , IDLoc , STI ) ; if ( BaseReg != <STR_LIT> ) emitRRR ( <STR_LIT> , TmpReg , TmpReg , BaseReg , IDLoc , STI ) ; emitRRI ( Opcode , DstReg , TmpReg


<s> return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Value * GEPPtr = GEP -> getPointerOperand ( ) ; if ( GEPPtr -> getType ( ) -> isVectorTy ( ) ) { return nullptr ; } if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; Type * OffsType = VectorType :: getInteger ( cast < VectorType > ( Ty ) ) ; if ( OffsType != Offsets -> getType ( ) ) { if ( OffsType -> getScalarSizeInBits ( ) > Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Offsets = Builder . CreateZExt ( Offsets , OffsType , <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT>


<s> static DecodeStatus decodeBDXAddr64Disp12Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const MCDisassembler * Decoder ) { return decodeBDXAddr12Operand ( Inst , Field , <STR_LIT>


<s> return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( )


<s> void addMem16Operands ( MCInst & Inst , unsigned N ) const { addMemOperands ( Inst ,


<s> <ISA_LIT>AsmInstrumentation * llvm :: Create<ISA_LIT>AsmInstrumentation ( const MCTargetOptions & MCOptions , const MCContext & Ctx , const MCSubtargetInfo * & STI ) { Triple T ( STI -> getTargetTriple ( ) ) ; const bool hasCompilerRTSupport = T . isOSLinux ( ) ; if ( ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions . SanitizeAddress ) { if ( STI -> getFeatureBits ( ) [ <STR_LIT> ]

!= <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue ZeroVec = DAG . getUNDEF ( <STR_LIT> ) ; SDValue VecVal ; if ( VT == <STR_LIT> ) { VecVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; VecVal = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , ZeroVec , VecVal ) ; } else { VecVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; } SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecVal ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant


<s> bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i


<s> static DecodeStatus DecodeAdrInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT>


<s> case <STR_LIT> : { EVT T = N -> getValueType ( <NUM_LIT> ) ; assert ( T == <STR_LIT> && <STR_LIT> ) ; SDValue cpInL , cpInH ; cpInL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; cpInH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; cpInL = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> , cpInL , SDValue ( ) ) ; cpInH = DAG . getCopyToReg ( cpInL . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , cpInH , cpInL . getValue ( <NUM_LIT> ) ) ; SDValue swapInL , swapInH ; swapInL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; swapInH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; swapInL = DAG . getCopyToReg ( cpInH . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , swapInL , cpInH . getValue ( <NUM_LIT> ) ) ; swapInH = DAG . getCopyToReg ( swapInL . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , swapInH , swapInL . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { swapInH . getValue ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , swapInH . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; SDValue cpOutL = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , Result . getValue ( <NUM_LIT> ) ) ; SDValue cpOutH = DAG . getCopyFromReg ( cpOutL . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , cpOutL . getValue ( <NUM_LIT> ) ) ; SDValue OpsF [ ] = { cpOutL . getValue ( <NUM_LIT> ) , cpOutH . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( cpOutH . getValue ( <NUM_LIT> ) ) ; return ; } case <STR_LIT> : ReplaceATOMIC_BINARY_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT>


<s> assert ( Kind == k_CondCode && <STR_LIT> ) ; return CondCode


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) == <NUM_LIT>

&& INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return false ;


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , array_lengthof ( RetOps


<s> if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI


<s> return ( uint64x1_t ) __builtin_neon_vdup_ndi ( ( __builtin_neon_di )


<s> AsmTransCBE = arm_asm_table ; Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; bool Modified


<s> return ( __m128 ) __builtin_ia32_rangess128_mask_round ( ( __v4sf ) __A , ( __v4sf ) __B , __C , ( __v4sf ) _mm_setzero_ps ( ) , (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t


<s> auto new_elt_mode = int_mode_for_size ( new_elt_bits , false ) . require ( ) ; machine_mode new_mode = aarch64_simd_container_mode ( new_elt_mode , vec_bits ) ; if ( new_mode == word_mode ) return false ; nelt = d -> perm . length ( ) . to_constant ( ) ; vec_perm_builder newpermconst ; newpermconst . new_vector ( nelt / <NUM_LIT> , nelt / <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { poly_int64 elt0 = d -> perm [ i ] ; poly_int64 elt1 = d -> perm [ i + <NUM_LIT> ] ; poly_int64 newelt ; if ( ! multiple_p ( elt0 , <NUM_LIT> , & newelt ) || maybe_ne ( elt0 + <NUM_LIT> , elt1 ) ) return false ; newpermconst . quick_push ( newelt . to_constant ( ) ) ; } newpermconst . finalize ( ) ; newd . vmode = new_mode ; newd . vec_flags = VEC_ADVSIMD ; newd . target = d -> target ? gen_lowpart (


<s> return MatchOperand_NoMatch ; case AsmToken :: Identifier : { StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex (


<s> SmallVector < TailCallArgumentInfo , <NUM_LIT> > TailCallArguments ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; bool seenFloatArg = false ; for ( unsigned i = <NUM_LIT> , j = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { seenFloatArg |= VA . getLocVT ( ) . isFloatingPoint ( ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( isVarArg ) { SDVTList VTs = DAG . getVTList ( <STR_LIT>


<s> elpart = INTVAL ( el ) & ( ( <NUM_LIT> << el_prec ) - <NUM_LIT> ) ; unsigned index = BYTES_BIG_ENDIAN ? n_elts - i - <NUM_LIT> : i ; hi_val |= elpart << ( index * shift_c ) ; } return gen_int_mode ( hi_val


<s> bool <ISA_LIT>Subtarget :: useConstantIslands ( ) { DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_rf ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , const ConstantFP * FPImm ) { unsigned ResultReg = createResultReg ( RC ) ; const TargetInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , BaseReg , Off , TII ) ; } assert ( Done && <STR_LIT> ) ; ( void ) Done


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , N0 ) ; SDValue Ops [ ] = { N0 , Neg , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE41 ( ) ) { SDLoc DL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , Sub , Src ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) { assert ( VT . isInteger ( ) && <STR_LIT> ) ; return splitVectorIntUnary ( Op , DAG ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) return splitVectorIntUnary ( Op , DAG ) ; return SDValue ( )


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u64 ( unsigned long


<s> void <ISA_LIT>MCAsmStreamer :: EmitThumbFunc ( MCSymbol


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = <STR_LIT> ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isABI_N32 ( ) || isABI_N64 ( ) ) stackAlignment = <NUM_LIT> ; else { assert ( isABI_O32 ( ) && <STR_LIT> ) ; stackAlignment = <NUM_LIT>


<s> switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; } bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) .


<s> FOR_EACH_VEC_ELT ( mips_multi_members , i , member ) if ( member -> is_label_p ) fprintf ( asm_out_file , <STR_LIT> , member -> format ) ; else output_asm_insn ( member -> format ,


<s> SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : nullptr ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo


<s> <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; if ( NumDefs && ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx >= NumOps ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; } uint32_t mask = <NUM_LIT> ; if ( ! getBFCInvMask ( insn , mask ) ) return false ; MI . addOperand ( MCOperand :: CreateImm ( mask ) ) ; OpIdx += <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ) ) ; OpIdx += <NUM_LIT> ; return true ; } bool RmRn = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( ! isUnary ) { assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , RmRn ? decodeRm ( insn ) :


<s> if ( splitAddSubImm ( Imm , RegSize , Imm0 , Imm1 ) ) return PosOpc ; if ( splitAddSubImm ( - Imm , RegSize , Imm0 , Imm1 ) ) return NegOpc ; return None ; } , [ & TII = TII ] ( MachineInstr & MI , unsigned Opcode , unsigned Imm0 , unsigned Imm1 , Register SrcReg , Register NewTmpReg , Register NewDstReg ) { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode ) , NewTmpReg ) . addReg ( SrcReg )

. addImm ( Imm0 ) . addImm ( <NUM_LIT> ) ;


<s> return _mm512_insertf32x4 ( _mm512_setzero_ps ( ) , __A ,


<s> unsigned Val = ( MO . getImm ( ) & <NUM_LIT> ) ; assert ( Val == MO . getImm ( ) && <STR_LIT> ) ; unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ; O << '#' << Val ; if ( Shift != <NUM_LIT> ) printShifter ( MI , OpNum + <NUM_LIT> , O ) ; if ( CommentStream ) * CommentStream << '=' << ( Val << Shift ) << '\n' ; } else { assert ( MO . isExpr ( ) && <STR_LIT>


<s> * src = adjust_address ( * src , mode , <NUM_LIT> ) ; * dst = adjust_address ( * dst , mode , <NUM_LIT> ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg1 , * src , reg2 , aarch64_progress_pointer ( * src ) ) ) ; emit_insn ( aarch64_gen_store_pair ( mode , * dst , reg1 , aarch64_progress_pointer ( * dst ) , reg2 ) ) ; * src = aarch64_move_pointer ( * src , <NUM_LIT> ) ; * dst = aarch64_move_pointer ( * dst , <NUM_LIT> ) ; return ; } rtx reg = gen_reg_rtx ( mode ) ; * src = adjust_address ( * src , mode , <NUM_LIT> ) ; * dst = adjust_address ( * dst , mode , <NUM_LIT> ) ; emit_move_insn ( reg , * src ) ; emit_move_insn ( * dst , reg )


<s> } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) .


<s> InitMandarinMCSubtargetInfo ( X , TT , CPU , FS ) ; return


<s> } } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = FUNCTION_ARG ( args_so_far , VOIDmode , void_type_node , <NUM_LIT> ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx insn , pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; insn = emit_insn ( pattern ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , NULL_RTX , REG_NOTES ( insn ) ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; if ( TARGET_ABICALLS ) offset += tsize ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx ( PLUS , Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx ( MEM , gpr_mode , ptr ) , gen_rtx ( REG , gpr_mode , regno ) ) ; offset += GET_MODE_SIZE ( gpr_mode ) ; } } if ( mips_entry && ! mips_can_use_return_insn ( ) ) { if ( tsize > <NUM_LIT> && tsize <= <NUM_LIT> && frame_pointer_needed ) { rtx insn ; if ( TARGET_MIPS16 && current_function_outgoing_args_size != <NUM_LIT> ) { rtx incr = GEN_INT ( current_function_outgoing_args_size ) ; if ( Pmode == DImode ) insn = emit_insn ( gen_adddi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , incr ) ) ; else insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , incr ) ) ; } else if ( Pmode == DImode ) insn = emit_insn ( gen_movdi ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; else insn = emit_insn ( gen_movsi ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_MIPS16 && BITSET_P ( current_frame_info . mask , <NUM_LIT> ) ) { rtx reg_rtx = gen_rtx ( REG , gpr_mode , GP_REG_FIRST + <NUM_LIT> ) ; long gp_offset , base_offset ; gp_offset = current_frame_info . gp_sp_offset ; if ( BITSET_P ( current_frame_info . mask , <NUM_LIT> ) ) gp_offset -= UNITS_PER_WORD ; if ( BITSET_P ( current_frame_info . mask , <NUM_LIT> ) ) gp_offset -= UNITS_PER_WORD ; if ( BITSET_P ( current_frame_info . mask , <NUM_LIT> ) ) gp_offset -= UNITS_PER_WORD ; if ( tsize > <NUM_LIT> ) base_offset = tsize ; else base_offset = <NUM_LIT> ; start_sequence (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , RegSeq -> getValueType ( <NUM_LIT> ) , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand (

NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> if ( BBUtils -> isBBInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return fixupUnconditionalBr ( Br ) ; return fixupConditionalBr ( Br


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: expandSelectCC ( MachineInstr * MI , MachineBasicBlock * BB , unsigned BROpcode ) const { const TargetInstrInfo & TII = * getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) )


<s> <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCCodeEmitter :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( )


<s> if ( ! III . IsSummingOperands ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setReg ( RegMO -> getReg ( ) ) ; if ( RegMO -> isKill ( ) ) { MI . getOperand ( III . OpNoForForwarding ) . setIsKill ( true ) ; RegMO -> setIsKill ( false ) ; } MI . getOperand ( III . ImmOpNo ) . setImm ( Imm ) ; if ( DefMI . getParent ( ) == MI . getParent ( ) ) { auto IsKilledFor = [ & ] ( unsigned Reg ) { MachineBasicBlock :: const_reverse_iterator It = MI ; MachineBasicBlock :: const_reverse_iterator E = DefMI ; It ++ ; for ( ; It != E ; ++ It ) { if ( It -> killsRegister ( Reg ) ) return true ; } return false ; } ; if ( RegMO -> isKill ( ) || IsKilledFor ( RegMO -> getReg ( ) ) ) fixupIsDeadOrKill ( & DefMI , & MI , RegMO -> getReg ( ) ) ; if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill ( & DefMI , & MI , ForwardKilledOperandReg ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI .


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDValue * K = isa < ConstantSDNode > ( LHS ) ? & LHS : isa < ConstantSDNode > ( RHS ) ? & RHS : nullptr ; if ( ! K ) return false ; SDValue KTmp = isa < ConstantSDNode > ( TrueVal ) ? TrueVal : FalseVal ; V = ( KTmp == TrueVal ) ? FalseVal : TrueVal ; SDValue VTmp = ( K && * K == LHS ) ? RHS : LHS ; if ( * K != KTmp || V != VTmp ) return false ; if ( isLowerSaturate ( LHS , RHS , TrueVal , FalseVal , CC , * K ) ) { SatK = * K ; return true


<s> int NumEltsPerLane = NumElts / NumLanes ; SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; LaneMask [ i ] = ( SrcLane * NumEltsPerLane ) + ( i % NumEltsPerLane ) ; PermMask [ i ] = ( DstLane * NumEltsPerLane ) + ( M


<s> MachineBasicBlock :: iterator J ( RemovableAdd ) ; for ( ++ J ; & * J != JumpMI ; ++ J ) { for ( unsigned K = <NUM_LIT> , E = J -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = J -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == EntryReg ) return ; if ( MO . isUse ( ) && MO . getReg ( ) == EntryReg ) return ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * RemovableAdd ) ; RemovableAdd -> eraseFromParent ( ) ; DeadSize += <NUM_LIT>


<s> if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; len = INTVAL ( size ) ; pos = INTVAL ( position ) ; if ( len <= <NUM_LIT> || len >= GET_MODE_BITSIZE ( GET_MODE ( op ) ) || pos < <NUM_LIT> || pos + len > GET_MODE_BITSIZE ( GET_MODE ( op )


<s> auto Cst = getIConstantVRegValWithLookThrough ( UseInstr . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Cst ) return false ; MinOffset = std :: min ( MinOffset , Cst -> Value . getZExtValue ( ) ) ; } uint64_t CurrOffset = GlobalOp . getOffset ( ) ; uint64_t NewOffset = MinOffset + CurrOffset ; if ( NewOffset <= CurrOffset ) return false ; if ( NewOffset >= ( <NUM_LIT> << <NUM_LIT> ) ) return false ; Type * T = GV -> getValueType ( ) ; if ( ! T -> isSized ( ) || NewOffset > GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( T ) ) return false ; MatchInfo = std :: make_pair ( NewOffset , MinOffset ) ; return true


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int FPDiff , SDLoc dl ) { if ( ! FPDiff ) return


<s> MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( I ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const TargetRegisterClass * RC = TII -> getRegClass ( Desc , I , TRI , MF ) ; unsigned NewReg ; if ( RC == nullptr ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs (


, __m512i __index , double const * __addr , int __scale ) {


<s> Muls . push_back ( make_unique < BinOpChain > ( I , LHS ,


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return


<s> default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == <NUM_LIT> ) return false ; unsigned PairedPhys = <NUM_LIT> ; if ( Register :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg


<s> named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , arg . mode ) + CEIL ( arg . promoted_size_in_bytes (


<s> static void d30v_add_gc_roots ( ) { ggc_add_rtx_root ( & d30v_compare_op0


<s> if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * RHSC = dyn_cast < ConstantFP > ( RHS ) ; if ( RHSC && RHSC -> isNullValue ( ) ) RHS = LHS ; } static unsigned SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII

. get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ;


<s> ReuseLoadInfo RLI ; LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , false , false , RLI . IsInvariant , RLI . Alignment , RLI . AAInfo ,


<s> tree attrs ; if ( ! decl ) return TARGET_LONG_CALLS ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return false ; if ( ! flag_reorder_blocks_and_partition && TREE_CODE ( decl ) == FUNCTION_DECL && arm_function_in_section_p ( decl , current_function_section ( ) ) ) return false ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; return


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } } break ; case <STR_LIT>


<s> raw_svector_ostream ( Name ) << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; return OutContext . GetOrCreateSymbol ( Name . str (


<s> RegisterTarget < Triple :: cpu0el , true > Y ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT>


<s> aarch64_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; aarch64_simd_types [ Int64x1_t ] . eltype = intDI_type_node ; aarch64_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; aarch64_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; aarch64_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; aarch64_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; aarch64_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; aarch64_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint64x1_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Poly8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype = build_distinct_type_copy ( unsigned_intQI_type_node ) ; TYPE_STRING_FLAG ( aarch64_simd_types [ Poly8_t ] . eltype ) = false ; aarch64_simd_types [ Poly16_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype = build_distinct_type_copy ( unsigned_intHI_type_node ) ; aarch64_simd_types [ Poly64_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype = build_distinct_type_copy ( unsigned_intDI_type_node ) ; aarch64_simd_types [ Poly128_t ] . eltype = aarch64_simd_types [ Poly128_t ] . itype = build_distinct_type_copy ( unsigned_intTI_type_node ) ; aarch64_simd_types [ Poly8x8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly8x16_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly16x4_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly16x8_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly64x1_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Poly64x2_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Float16x4_t ] . eltype = aarch64_fp16_type_node ; aarch64_simd_types [ Float16x8_t ] . eltype = aarch64_fp16_type_node ; aarch64_simd_types [ Float32x2_t ] . eltype =


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand ::


<s> else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF


<s> } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT

, DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == <NUM_LIT> ) ) ;


<s> for ( int i = NumElems / <NUM_LIT> , j = <NUM_LIT> ; i < NumElems ; ++ i , ++ j ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , j ) || SVOp -> getMaskElt ( j )


<s> for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> unsigned Encoding ; const MCOperand Op1 = Inst . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand Op2 = Inst . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand AluOp = Inst . getOperand ( OpNo + <NUM_LIT> ) ; assert ( Op1 . isReg ( ) && <STR_LIT> ) ; assert ( ( Op2 . isImm ( ) || Op2 . isExpr ( ) ) && <STR_LIT> ) ; assert ( ( LPAC :: getAluOp ( AluOp . getImm ( ) ) == LPAC :: ADD ) && <STR_LIT> ) ; Encoding = ( get<ISA_LIT>RegisterNumbering ( Op1 . getReg ( ) ) << <NUM_LIT> ) ; if ( Op2 . isImm ( ) ) { assert ( isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) && <STR_LIT> ) ; Encoding |= ( Op2 . getImm ( ) & <NUM_LIT> ) ; if ( Op2 . getImm ( ) !=


<s> pcmpgth_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_pcmpgth_s ( s ,


<s> void <ISA_LIT>MCCodeEmitter :: emitSIBByte ( unsigned SS , unsigned Index , unsigned Base


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOperand ( ) { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is

( AsmToken :: Real ) || getLexer ( ) . is ( AsmToken :: Minus ) ) {


<s> const char * fpu_name ; fpu_name = ( ptr -> x_arm_fpu_index == TARGET_FPU_auto ? <STR_LIT> : all_fpus [ ptr -> x_arm_fpu_index ] . name ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , TARGET_THUMB2_P ( flags


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Arg = Mask . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; unsigned Idx = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Idx < NumElems ) { unsigned Opc = V1 . getNode ( ) -> getOpcode ( ) ; if ( Opc == <STR_LIT> || <STR_LIT> ( V1 . getNode ( ) ) ) continue ; if ( Opc != <STR_LIT> || ! isZeroNode ( V1 . getNode (

) -> getOperand ( Idx ) ) ) return false ;


<s> return ( TARGET_EXPLICIT_RELOCS && mips_symbolic_constant_p ( x , & symbol_type ) &&


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , ArchFS


<s> case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ,


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT IntVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; LegalizeAction Act = ( IntVT == <STR_LIT> ) ? Promote : Legal ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT FPVT : <STR_LIT> ( ) ) { setOperationAction ( <STR_LIT> , FPVT ,


<s> EVT NarrowVT = Narrow . getValueType ( ) ; if ( Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Narrow -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Narrow -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Narrow ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ; if ( ! RHSTrunc && ! <STR_LIT> ( N1 . getNode ( ) ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , VT ) ) return SDValue ( ) ; N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( RHSTrunc ) N1 = N1 . getOperand ( <NUM_LIT> ) ; else N1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , VT , N0 , N1 ) ; unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return Op


<s> return ( __m128i ) __builtin_ia32_packuswb128_mask ( ( __v8hi ) __A , ( __v8hi ) __B , (


<s> PM . add ( create<ISA_LIT>JITCodeEmitterPass ( *


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; unsigned Pos = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) Pos -= <NUM_LIT> ; assert ( ( Pos < <NUM_LIT> || ( Pos < <NUM_LIT> && MCID . Opcode != <STR_LIT> && MCID . Opcode != <STR_LIT> ) ) && <STR_LIT> ) ; Binary |= Pos << <NUM_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) { unsigned ShiftOp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Opc = <STR_LIT> ( ShiftOp ) ; if ( Opc == <STR_LIT> ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; unsigned ShiftAmt = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShiftAmt == <NUM_LIT> && Opc == <STR_LIT> ) ShiftAmt = <NUM_LIT> ; assert ( ShiftAmt < <NUM_LIT> && <STR_LIT>


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>SEInstrInfo ( const <ISA_LIT>Subtarget &


<s> if ( SetOrSelCC . getOpcode ( ) != <STR_LIT> && SetOrSelCC . getOpcode ( ) != <STR_LIT> ) return false ; if ( ! SetOrSelCC . hasOneUse ( ) || ( ! InnerIsSel && ! FalseRes . hasOneUse ( ) ) ) return false ; SDValue InnerLHS = SetOrSelCC . getOperand ( <NUM_LIT> ) ; SDValue InnerRHS = SetOrSelCC . getOperand ( <NUM_LIT> ) ; <STR_LIT> InnerCC = cast < CondCodeSDNode > ( SetOrSelCC . getOperand ( InnerIsSel ? <NUM_LIT> : <NUM_LIT> ) ) -> get ( ) ; if ( InnerIsSel ) { ConstantSDNode * SelCCTrueConst = dyn_cast < ConstantSDNode > ( SetOrSelCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SelCCFalseConst = dyn_cast < ConstantSDNode > ( SetOrSelCC . getOperand ( <NUM_LIT> ) ) ; if ( ! SelCCTrueConst || ! SelCCFalseConst ) return false ; int64_t SelCCTVal = SelCCTrueConst -> getSExtValue ( ) ; int64_t SelCCFVal = SelCCFalseConst -> getSExtValue ( ) ; if ( SelCCTVal == - <NUM_LIT> && SelCCFVal == <NUM_LIT> ) { std :: swap ( InnerLHS , InnerRHS ) ; } else if ( SelCCTVal != <NUM_LIT> || SelCCFVal != - <NUM_LIT> ) return false ; } if ( InnerCC == <STR_LIT> || InnerCC == <STR_LIT> ) { IsUnCmp = true ; InnerCC = ( InnerCC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } bool InnerSwapped = false ; if ( LHS == InnerRHS && RHS == InnerLHS ) InnerSwapped = true ; else if ( LHS != InnerLHS || RHS != InnerRHS ) return false ; switch ( CC ) { case <STR_LIT> : if ( ! InnerIsSel ) return false ; if ( InnerCC != <STR_LIT> && InnerCC != <STR_LIT> ) return false ; NeedSwapOps = ( InnerCC == <STR_LIT> ) ? InnerSwapped : ! InnerSwapped ; break ; case <STR_LIT> : if ( ! IsUnCmp && InnerCC != <STR_LIT> ) return false ; IsUnCmp = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( InnerCC == <STR_LIT> || ( InnerCC == <STR_LIT> && ! InnerSwapped ) || ( InnerCC == <STR_LIT> && InnerSwapped ) ) NeedSwapOps = ( TrueResVal == <NUM_LIT> ) ; else return false ; break ; case <STR_LIT> : if ( ! IsUnCmp && InnerCC !=


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_ADDR : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL : return <STR_LIT> ; case VK_<ISA_LIT>_GOT : return <STR_LIT> ; case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TPOFF : return <STR_LIT> ; case VK_<ISA_LIT>_TLSGD : return


<s> MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; V2 = RegInfo . createVirtualRegister (


<s> unsigned ZEROReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ATReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Offset , Size , true ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , TII . get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - <NUM_LIT> ; ++ Inst ) BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDu ) , ATReg ) . addReg ( FrameReg ) . addReg ( ATReg ) ; FrameReg = ATReg ; Offset = SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ; BuildMI ( MBB , ++ II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; } MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT>


<s> if ( NeedPlus ) O << <STR_LIT> ; printOp ( DispSpec , <STR_LIT> ) ; } else { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! BaseReg . getReg ( ) && ! IndexReg . getReg ( ) ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> ) O << <STR_LIT> ; else { O << <STR_LIT> ; DispVal = - DispVal ; } } O <<


<s> return DecodeGPRSeqPairsClassRegisterClass ( Inst , <STR_LIT> ,


<s> int64_t maxFwdBranchOffset ( ) const { return


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> return ( __m256d ) __builtin_ia32_blendmpd_256_mask ( ( __v4df ) __A , ( __v4df ) __W , (


<s> __builtin_sh_media_STLO_L ( ( char * ) p + s


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = <NUM_LIT> ; data -> cost [ vect_body ] = <NUM_LIT> ; data -> cost [ vect_epilogue ] = <NUM_LIT> ; rs6000_vect_nonmem =


<s> static DecodeStatus DecodeSimm23Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address


<s> return getTM < <ISA_LIT>TargetMachine


<s> assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( MF

. getTarget ( ) . getFrameLowering ( ) ) ;


<s> -- I ; } if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return


<s> void <ISA_LIT>TargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT>


<s> } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( <STR_LIT>


<s> if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; unsigned MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; Register DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; updateValueMap ( I ,


<s> for ( unsigned i = <NUM_LIT> , ie = ( unsigned ) SU -> Preds . size ( ) ; i != ie ; ++ i ) { const MCInstrDesc * PredMCID = DAG -> getInstrDesc ( SU -> Preds [ i ] . getSUnit ( ) ) ; if ( ! PredMCID || PredMCID -> getSchedClass ( ) != <STR_LIT> :: IIC_SprMTSPR ) continue ; if ( SU -> Preds [ i ] . isCtrl ( ) ) continue ; for ( unsigned j = <NUM_LIT> , je = CurGroup . size ( ) ; j != je ; ++ j ) if ( SU -> Preds [ i ] . getSUnit ( ) ==


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg .


<s> } if ( ! CountedExitBlock ) return MadeChange ; BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader || mightUseCTR ( TT , Preheader ) ) Preheader = InsertPreheaderForLoop ( L , this ) ; if ( ! Preheader ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ) ; MadeChange = true ; SCEVExpander SCEVE ( * SE , <STR_LIT> ) ; LLVMContext & C = SE -> getContext ( ) ; Type * CountType = TT . isArch64Bit ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; if ( ! ExitCount -> getType ( ) -> isPointerTy ( ) && ExitCount -> getType ( ) != CountType ) ExitCount = SE -> getZeroExtendExpr ( ExitCount , CountType ) ; ExitCount = SE -> getAddExpr ( ExitCount , SE -> getConstant ( CountType , <NUM_LIT> ) ) ; Value * ECValue = SCEVE . expandCodeFor ( ExitCount , CountType , Preheader -> getTerminator ( ) ) ; IRBuilder < > CountBuilder ( Preheader -> getTerminator ( ) ) ; Module * M = Preheader -> getParent ( ) -> getParent ( ) ; Value * MTCTRFunc = <STR_LIT> ( M , <STR_LIT> , CountType ) ; CountBuilder . CreateCall ( MTCTRFunc , ECValue ) ; IRBuilder < > CondBuilder ( CountedExitBranch ) ; Value * DecFunc = <STR_LIT> ( M , <STR_LIT> ) ; Value * NewCond = CondBuilder .


<s> case <STR_LIT> : Unsigned = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( ( ! Opc && SSECC == <NUM_LIT> ) || Opc == <STR_LIT> ) { SDValue A = peekThroughBitcasts ( Op0 ) ; if ( ( A . getOpcode ( ) == <STR_LIT> || A . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ( Op1 . getNode ( ) ) ) { MVT VT0 = Op0 . getSimpleValueType ( ) ; SDValue RHS = DAG . getBitcast ( VT0 , A . getOperand ( <NUM_LIT> ) ) ; SDValue LHS = DAG . getBitcast ( VT0 , A . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , VT , RHS , LHS ) ; } } if ( Opc ) return DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ; Opc = Unsigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC ,


<s> size_t SizeInWords = ( Size + <NUM_LIT> ) / <NUM_LIT> ; assert ( SizeInWords <= <NUM_LIT> && <STR_LIT> ) ; EmitByte ( static_cast < uint8_t > ( SizeInWords


<s> Hash = true ; } bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> && ! RealVal . isZero ( ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val ; if ( ! isNegative && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { Val = Tok . getIntVal


<s> } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HSUBBuilder ) ; } if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; if ( SDValue V = combineSubToSubus ( N , DAG , Subtarget ) ) return V ; return combineAddOrSubToADCOrSBB ( N


<s> return isMEMrri ( ) || isMEMrii ( ) || isMEMzri ( ) || isMEMzii ( ) ||


<s> static std :: unique_ptr < <ISA_LIT>Operand > createFGRReg ( unsigned Index , const MCRegisterInfo *

RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SRegHi , RegState :: Kill ) .


<s> size = build_int_cst ( sizetype , <NUM_LIT> ) ; return


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode


<s> IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; const MCExpr * Disp = nullptr ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: createAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( StartInBrac , ErrMsg ) ; return nullptr ; } return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( StringRef


<s> OutStreamer -> EmitLabel ( CurrentFnDescSym ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ; MCSymbol * TOCBaseSym = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( TOCBaseSym , OutContext


<s> __ev64_opaque__ t ; t = __ev_mwhumi ( a , b


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( Dest ) . addOperand ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static inline bool isUncondBranchOpcode ( int Opc ) { return Opc == <STR_LIT>


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } if ( Mnemonic . startswith ( <STR_LIT> ) ) { ITMask = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> && Value <=


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; B . addAttribute ( <STR_LIT> , <STR_LIT> ) ; F . removeAttributes ( AttributeList :: FunctionIndex , B ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; } F . addAttributes ( AttributeList ::


<s> Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const unsigned Option = MO . getTargetFlags


<s> if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT>

, DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> return MI . isCall ( ) || isLoopStart


<s> if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) return true ; auto AddendExpr = dyn_cast < MCConstantExpr > ( BE


<s> return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == <NUM_LIT> ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( )


<s> emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ <NUM_LIT> ] , halfmode , dest , <NUM_LIT> ) ; desthi = gen_rtx_REG_offset ( operands [ <NUM_LIT> ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( VOIDmode , destlo , operands [ <NUM_LIT> ] ) ; rtx y = gen_rtx_SET ( VOIDmode , desthi , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , x ,


<s> return std :: numeric_limits < unsigned > :: max


<s> SMLoc getEndLoc ( ) const override { return


<s> enum insn_code in_icode = ( enum insn_code ) INSN_CODE ( in_insn ) ; for ( i = <NUM_LIT> ; i < num_bypass ; i ++ ) { if ( out_icode == dspalu_bypass_table [ i ] [ <NUM_LIT> ] && in_icode == dspalu_bypass_table [ i ] [ <NUM_LIT> ] ) return true ; } return


<s> unsigned IntrinsicID = IntInst -> getIntrinsicID ( ) ; return ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID

== <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) ;


<s> const struct mips_cpu_info * p ; const char * s ; for ( s = cpu_string ; * s != <NUM_LIT> ; s ++ ) if ( ISUPPER ( * s ) ) { warning ( <NUM_LIT>