<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( Opc != <STR_LIT> ) assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) ; return ; } unsigned Scale ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT> ) ; OffsetOpnd . setImm ( OffsetOpnd . getImm ( ) + LocalStackSize / Scale ) ; if ( NeedsWinCFI ) { auto MBBI = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; assert ( MBBI != MI . getParent (


<s> __cpuidex ( registers , value , subleaf ) ; * rEAX = registers [ <NUM_LIT> ] ; * rEBX = registers [ <NUM_LIT> ] ; * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT> ] ; return false ; return true ; return true ; asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT>


<s> if ( Addr . BaseType == Address :: FrameIndexBase ) { int FI = Addr . Base . FI ; int Offset = Addr . Offset ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { signed Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT>


<s> break ; case Function :: DLLExportLinkage : case Function :: ExternalLinkage : EmitAlignment ( FnAlign , F ) ; O << <STR_LIT> << CurrentFnName << '\n' ; break ; case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : EmitAlignment ( FnAlign , F ) ; if ( Subtarget -> isTargetDarwin ( ) ) { O << <STR_LIT> << CurrentFnName << '\n' ; O << TAI -> getWeakDefDirective ( ) << CurrentFnName << '\n' ; } else if ( Subtarget -> isTargetCygMing ( ) ) { O << <STR_LIT> << CurrentFnName << <STR_LIT> <STR_LIT> ; } else { O << <STR_LIT> << CurrentFnName << '\n' ; } break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; if ( Subtarget -> isTargetELF ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> ; else if ( Subtarget -> isTargetCygMing ( ) ) { O << <STR_LIT> << CurrentFnName << <STR_LIT> << ( F -> hasInternalLinkage ( ) ? COFF :: C_STAT : COFF :: C_EXT

) << <STR_LIT> << ( COFF :: DT_FCN << COFF :: N_BTSHFT ) << <STR_LIT> ;


<s> static const TargetRegisterClass * getMinClassForRegBank ( const RegisterBank & RB , unsigned SizeInBits , bool GetAllRegSet = false ) { unsigned RegBankID = RB . getID ( ) ; if ( RegBankID == <STR_LIT> ) { if ( SizeInBits <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> :


<s> return MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addOperand ( Offset ) . addReg (


<s> return ( unsigned long long ) __builtin_ia32_vcvtss2usi64 ( ( __v4sf )


<s> return false ; } RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I32


<s> if ( optimize > <NUM_LIT> && selected_cpu -> tune -> max_case_values !=

<NUM_LIT> ) return selected_cpu -> tune -> max_case_values ;


<s> return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT>


<s> rtx arg2 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( arg1 ) ) return NULL_RTX ; if ( ! REG_P ( arg2 ) ) arg2 = force_reg ( SImode , arg2 ) ; if ( INTVAL ( arg1 ) == <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , ( int ) INTVAL ( arg1 ) ) ; arg1 = const0_rtx ; } emit_insn ( gen_mvtc ( arg1 , arg2 ) ) ; return NULL_RTX


<s> StringRef getPassName ( ) const override { return


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressDarwin ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) && RelocM != Reloc :: Static ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; } else { <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT>


<s> inline vector unsigned int vec_vupkhpx ( vector signed


<s> for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI


<s> unsigned LastRLAmt = RLAmt [ <NUM_LIT> ] ; SDValue LastValue = Bits [ <NUM_LIT> ] . hasValue ( ) ? Bits [ <NUM_LIT> ] . getValue ( ) : SDValue ( ) ; unsigned LastGroupStartIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) { unsigned ThisRLAmt = RLAmt [ i ] ; SDValue ThisValue = Bits [ i ] . hasValue ( ) ? Bits [ i ] . getValue ( ) : SDValue ( ) ; if ( LateMask && ! ThisValue ) { ThisValue = LastValue ; ThisRLAmt = LastRLAmt ; if ( BitGroups . empty ( ) ) LastGroupStartIdx = <NUM_LIT> ; } if ( ThisRLAmt == LastRLAmt && ThisValue == LastValue ) continue ; if ( LastValue . getNode ( ) ) BitGroups . push_back ( BitGroup (

LastValue , LastRLAmt , LastGroupStartIdx , i - <NUM_LIT> ) ) ;


<s> if ( align < <NUM_LIT> * sizeof ( void * ) ) align = <NUM_LIT> * sizeof ( void * ) ; malloc_ptr = malloc ( size + align ) ; if ( ! malloc_ptr ) return ( ( void * ) <NUM_LIT> ) ; aligned_ptr = ( void * ) ( ( ( size_t ) malloc_ptr + align ) & ~ ( (


<s> virtual const TargetFrameLowering * getFrameLowering ( )


<s> static DecodeStatus DecodeFCCRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> )


<s> if ( CPEs [ j ] . RefCount == <NUM_LIT> && CPEs [ j ] . CPEMI ) { removeDeadCPEMI ( CPEs [ j ] . CPEMI ) ; CPEs [ j ] . CPEMI = NULL ; MadeChange = true ; } } } return


<s> return __builtin_ia32_rcpph256_mask ( __A , _mm256_setzero_ph ( ) , (


<s> ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; return


<s> int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == <NUM_LIT> ) return false ; if ( sort_regs ) for ( i = <NUM_LIT> ; i < nops - <NUM_LIT> ; i ++ ) for ( j = i + <NUM_LIT>

; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) {


<s> else { error_p = true ; cpu_opt = q + <NUM_LIT> ; } } else if ( strncmp ( q , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { int tune_index = rs6000_cpu_name_lookup ( q + <NUM_LIT> ) ; if ( tune_index >= <NUM_LIT> ) rs6000_tune_index = tune_index ; else { error_p = true ; cpu_opt = q + <NUM_LIT> ; } } else { size_t i ; bool invert = false ; char * r = q ; error_p = true ; if ( strncmp ( r , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { invert = true ; r += <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_opt_masks ) ; i ++ ) if ( strcmp ( r , rs6000_opt_masks [ i ] . name ) == <NUM_LIT> ) { HOST_WIDE_INT mask = rs6000_opt_masks [ i ] . mask ; if ( ! rs6000_opt_masks [ i ] . valid_target ) not_valid_p = true ; else { error_p = false ; rs6000_isa_flags_explicit |= mask ; if ( ! invert ) { if ( mask == OPTION_MASK_VSX ) { mask |= OPTION_MASK_ALTIVEC ; TARGET_AVOID_XFORM = <NUM_LIT> ; } } if ( rs6000_opt_masks [ i ] . invert


<s> vec_uchar16 left , right ; left = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; right = vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , left ) ; return ( ( qword ) ( vec_or ( vec_slo ( ( vec_uchar16 ) ( a ) , left ) , vec_sro

( ( vec_uchar16 ) ( a ) , right ) ) ) ) ;


<s> if ( ! Ld0 || ! Ld1 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; if ( ! Ld0 -> hasOneUse ( ) || ! Ld1 -> hasOneUse ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> if ( ! has_hard_reg_initial_val ( Pmode , LINK_REGISTER_REGNUM ) || cfun -> machine -> ra_needs_full_frame ) return regs_ever_live [ LINK_REGISTER_REGNUM ] ; push_topmost_sequence ( ) ; top = get_insns ( ) ; pop_topmost_sequence ( ) ; return reg_set_between_p ( gen_rtx_REG ( Pmode , LINK_REGISTER_REGNUM ) , top


<s> sr_str = <STR_LIT> ; break ; case NDS32_PARTIAL_SAVE : sr_str = <STR_LIT> ; break ; } switch ( nds32_isr_vectors [ vector_id ] . nested_type ) { case NDS32_NESTED : nt_str = <STR_LIT> ; break ; case NDS32_NOT_NESTED : nt_str = <STR_LIT> ; break ; case NDS32_NESTED_READY : nt_str = <STR_LIT> ; break ; } vs_str = ( nds32_isr_vector_size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; snprintf ( first_level_handler_name , sizeof ( first_level_handler_name ) , <STR_LIT> , c_str , sr_str , nt_str , vs_str ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> , vector_id ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> , vector_id , vs_str ) ; nds32_emit_section_head_template ( section_name , symbol_name , floor_log2 ( nds32_isr_vector_size ) , false ) ; if ( nds32_isr_vector_size == <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> , first_level_handler_name ) ; } else { if ( TARGET_REDUCED_REGS ) { if ( nds32_isr_vectors [ vector_id ] . save_reg == NDS32_SAVE_ALL ) { fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file ,


<s> PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } else continue ; } else continue ; unsigned PtrAddrSpace = PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ; if ( PtrAddrSpace ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE -> getSCEVAtScope ( PtrValue , L ) ; const SCEVAddRecExpr * LARSCEV = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ; if ( ! LARSCEV || LARSCEV -> getLoop ( ) != L


<s> void <ISA_LIT>InstPrinter :: printAdrpLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << ( Op . getImm ( ) * ( <NUM_LIT> << <NUM_LIT>


<s> const char * output_add_immediate ( rtx * operands ) { HOST_WIDE_INT n = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( n != <NUM_LIT> || REGNO ( operands [ <NUM_LIT> ] ) != REGNO ( operands [ <NUM_LIT> ] ) ) { if ( n < <NUM_LIT> ) output_multi_immediate ( operands , <STR_LIT> , <STR_LIT> , <NUM_LIT>


<s> if ( ! GVA ) return false ; Type * Ty = GVA -> getValueType ( ) ; return IsInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize (


<s> bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register


<s> Value * <ISA_LIT>IREmitter :: visitVTRN ( const


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT>


<s> AND_HARD_REG_SET ( c , * b ) ; GO_IF_HARD_REG_SUBSET ( c , reg_class_contents [ ( int ) NO_REGS ] , lose ) ; return <NUM_LIT> ; lose : return


<s> MCSymbol * Sym = Mang -> getSymbol ( MO . getGlobal ( ) ) ; MCSymbol * & TOCEntry = TOC [ Sym ] ; if ( TOCEntry == <NUM_LIT> ) TOCEntry = OutContext . GetOrCreateSymbol ( StringRef ( MAI -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( LabelID ++ ) ) ; O << * TOCEntry <<


<s> StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode . first ) , NewTmpReg ) . addReg ( SrcReg ) . addImm ( Imm0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode . second ) , NewDstReg ) . addReg ( NewTmpReg ) . addImm ( Imm1 ) . addImm ( <NUM_LIT> ) ; }


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken (

) || TRI -> needsStackRealignment ( MF ) ;


<s> case ENCODING_REG : translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; CASE_ENCODING_RM : CASE_ENCODING_VSIB : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case


<s> mipsAbi . m_Ases = <NUM_LIT> ; if ( elfFlags & llvm :: ELF :: EF_MIPS_MICROMIPS ) mipsAbi . m_Ases |= llvm :: <STR_LIT> ; if ( elfFlags & llvm :: ELF :: EF_MIPS_ARCH_ASE_M16 ) mipsAbi . m_Ases |= llvm :: <STR_LIT> ; if ( elfFlags & llvm :: ELF :: EF_MIPS_ARCH_ASE_MDMX ) mipsAbi . m_Ases |= llvm :: <STR_LIT> ; mipsAbi . m_Flags1


<s> bool isTargetCOFF ( ) const { return ( TargetTriple . getEnvironment ( ) != Triple

:: ELF && TargetTriple . isOSBinFormatCOFF ( ) ) ;


<s> SDValue ResNode ; SDValue HiPart ; DebugLoc dl = Op . getDebugLoc ( ) ; bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; unsigned char OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( ! IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> ) ; } else HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> ,


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeList Attrs = MF . getFunction


<s> if ( is64Bit ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = false ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol =


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue ) ; assert ( FPImmEncoding != - <NUM_LIT> &&


<s> if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7s : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7 : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6t2 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6k : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6m : isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v5te : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple


<s> SDLoc DL ( N ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Op1 . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) ) { Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Op2 = DAG . getNode ( <STR_LIT> ,


<s> struct recog_data_d recog_data_save = recog_data ; for ( int i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) recog_data . operand [ i ] = copy_rtx ( recog_data . operand [ i ] ) ; temp = get_insn_template ( insn_code_number , insn ) ; recog_data = recog_data_save ; if ( get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ) warning_at ( location , OPT_mwarn_cell_microcode , <STR_LIT> , temp , insn_data [ INSN_CODE ( insn )


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; auto * CondBV = cast < BuildVectorSDNode > ( Cond ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> , Size = VT . getVectorNumElements ( ) ; i < Size ; ++ i ) { SDValue CondElt = CondBV -> getOperand ( i ) ; Mask . push_back ( isa < ConstantSDNode > ( CondElt ) ? i + ( isZero ( CondElt ) ? Size : <NUM_LIT> ) : - <NUM_LIT> ) ; } return DAG . getVectorShuffle ( VT , dl , LHS ,


<s> operands [ <NUM_LIT> ] = force_reg ( mode , op1 ) ; if ( ! REG_P ( operands [ <NUM_LIT> ] ) && ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) || ( mode == SImode && operands [ <NUM_LIT> ] != CONST0_RTX ( SImode ) && ( ( comparison != EQ && comparison != NE ) || ( REG_P ( op1 ) && REGNO (

op1 ) != R0_REG ) || ! satisfies_constraint_I08 ( operands [ <NUM_LIT> ] ) ) ) ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;


<s> else return CC_<ISA_LIT>_64_C ; } if ( CC == CallingConv :: <ISA_LIT>_FastCall ) return CC_<ISA_LIT>_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_<ISA_LIT>_32_FastCC ; else if ( CC == CallingConv :: GHC


<s> Address ( ) : BaseType ( RegBase ) ,


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = countPopulation ( I ) ; Pos = countTrailingZeros


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig (


<s> else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_LDBL128 ) == RS6000_BTM_LDBL128 ) { if ( ! TARGET_HARD_FLOAT ) error ( <STR_LIT> , name , <STR_LIT> ) ; else error ( <STR_LIT> , name , TARGET_IEEEQUAD ? <STR_LIT> : <STR_LIT> ) ; } else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT>


<s> return get_hard_reg_initial_val ( mode , regno


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( )


<s> static void getUsefulBitsFromUBFM ( SDValue Op , APInt & UsefulBits , unsigned Depth ) { uint64_t Imm = cast < const ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; uint64_t MSB = cast < const ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; getUsefulBitsFromBitfieldMoveOpd ( Op , UsefulBits , Imm , MSB , Depth


<s> return __builtin_ia32_subph512_mask_round ( __A , __B , _mm512_setzero_ph ( ) , ( __mmask32 )


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Size = Op . getValueSizeInBits ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; if ( InVT . isScalableVector ( ) ) { if ( Idx == <NUM_LIT> && isPackedVectorType ( InVT , DAG ) ) return Op ; return SDValue ( ) ; } if ( Idx == <NUM_LIT> && InVT . getSizeInBits ( ) <= <NUM_LIT> ) return Op ; if ( Size == <NUM_LIT> && Idx * InVT . getScalarSizeInBits ( ) == <NUM_LIT> && InVT . getSizeInBits ( )


<s> EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode ( <STR_LIT> , DL , Ty , Mult , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; if ( HasHi ) Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Mult , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! HasLo || ! HasHi ) return HasLo ? Lo : Hi ; SDValue Vals [ ] = { Lo , Hi } ; return DAG . getMergeValues ( Vals , <NUM_LIT>


<s> AlreadyInit = true ; const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass


<s> return ( Kind == k_Register && Reg . Kind


<s> MaskedLoadSDNode * LoadNode = cast < MaskedLoadSDNode > ( Op ) ; assert ( LoadNode && <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( VT , true ) ) return LowerFixedLengthVectorMLoadToSVE ( Op , DAG ) ; SDValue PassThru = LoadNode -> getPassThru ( ) ; SDValue Mask = LoadNode -> getMask ( ) ; if ( PassThru -> isUndef ( ) || isZerosVector ( PassThru . getNode ( ) ) ) return Op ; SDValue Load = DAG . getMaskedLoad ( VT , DL , LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) , LoadNode -> getOffset ( ) , Mask , DAG . getUNDEF ( VT ) , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) , LoadNode -> getAddressingMode ( ) , LoadNode -> getExtensionType ( ) ) ; SDValue Result = DAG . getSelect ( DL , VT , Mask , Load , PassThru ) ; return DAG . getMergeValues ( { Result , Load . getValue ( <NUM_LIT> ) } , DL


<s> if ( GET_CODE ( rot ) == ROTATE && CONST_INT_P ( XEXP ( rot , <NUM_LIT> ) ) && INTVAL ( XEXP ( rot , <NUM_LIT> ) )


<s> if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) != UNSPEC_GOTOFF ) return true ; if ( SYMBOL_REF_P ( x ) && strcmp ( XSTR ( x , <NUM_LIT> ) , GOT_SYMBOL_NAME ) == <NUM_LIT> ) return true ; return false


<s> static DecodeStatus DecodeMem ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder , bool isLoad , DecodeFunc DecodeSX ) { unsigned sx = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeASX ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success )


<s> inline tree function_instance :: tuple_type ( unsigned int i ) const { unsigned int num_vectors = vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - <NUM_LIT> ] [ type_suffix ( i


<s> if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { unsigned TCOpcode = ( RetOpcode == <STR_LIT> ) ? ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget

. getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ;


<s> DebugLoc DL ; MachineInstrBuilder MIB1 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , Reg1 ) ; MIB1 . addImm ( Amount ) . addImm ( - <NUM_LIT> ) ; MachineInstrBuilder MIB2 = BuildMI ( MBB , I , DL , get (


<s> ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregxiv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = (


<s> MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ; MI . dropDebugNumber ( ) ; if ( Op0 != Op1 && KillsOp1


<s> getTargetStreamer ( ) . emitARM64WinCFISaveNext ( ) ; return false


<s> bool OptForMinSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ; if ( Subtarget . hasSSE41 ( ) && ( OptForMinSize || ! Subtarget . isPMULLDSlow ( ) ) ) return SDValue ( ) ; ShrinkMode Mode ; if ( ! canReduceVMulWidth ( N , DAG , Mode ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ( NumElts % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; MVT OpsVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; if ( ExperimentalVectorWideningLegalization || NumElts >= OpsVT . getVectorNumElements ( ) ) { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) ) { Base = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; Offset = Addr ; return true ; } } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr


<s> unsigned llvm :: getBLXOpcode ( const


<s> const SDValue & getMask ( ) const { return getOperand ( <NUM_LIT>


<s> if ( MayFoldLoad && N2 -> getOpcode ( ) == <STR_LIT> && N2 -> hasOneUse ( ) && tryFoldVecLoad ( Node , N2 . getNode ( ) , N2 . getOperand ( <NUM_LIT> ) , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Load = N2 . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , Load . getOperand ( <NUM_LIT> ) , InFlag } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode (


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { Triple TheTriple (


<s> virtual const InstrItineraryData * getInstrItineraryData (


<s> unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags &


<s> assert ( MBB . getParent ( ) && <STR_LIT> ) ; if ( canUseLEAForSPInEpilogue ( * MBB . getParent


<s> int Elt = SV -> getMaskElt ( Index ) ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? SV -> getOperand ( <NUM_LIT> ) : SV -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getValueType ( ) . getSimpleVT ( ) ; unsigned NumElems = ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , ShuffleMask ,


<s> SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType (


<s> Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) :


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else if ( ! ( SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) ) assert ( false && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> return ( __m128 ) __builtin_ia32_addps ( ( __v4sf )


<s> std :: tie ( RHS1 , RHS2 ) = splitVector ( Op . getOperand ( <NUM_LIT> ) , DAG , dl ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , LoVT , LHS1 , RHS1 , CC ) , DAG . getNode ( <STR_LIT> ,


<s> if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } InstructionCost Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; } case <STR_LIT> : if ( LT . second != <STR_LIT> ) return LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LT .


<s> SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Const31 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Res ; SDValue X = ( TyX == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; SDValue Y = ( TyY == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasExtractInsert ) { SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 ,


<s> a = vec_splat ( __A , <NUM_LIT> ) ; c = vec_rsqrte ( a ) ; return ( vec_sel ( __A , c ,


<s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand ::


<s> if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT> ) return false ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; assert ( LSB + Width + <NUM_LIT> <= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } } if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , And_imm ) && isShiftedMask_32 ( And_imm ) ) { unsigned Srl_imm = <NUM_LIT> ; unsigned LSB = countTrailingZeros ( And_imm ) ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) && Srl_imm == LSB ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned MSB = <NUM_LIT> - countLeadingZeros ( And_imm ) ; unsigned Width = MSB - LSB ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; assert ( Srl_imm + Width + <NUM_LIT> <= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( Srl_imm , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } } if ( N -> getOpcode ( ) == <STR_LIT> ) { unsigned Width = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) ; unsigned LSB = <NUM_LIT>


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; if ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ==

<NUM_LIT> ) StubSym = MachineModuleInfoImpl ::


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( getSubtarget ( ) -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( getSubtarget ( ) -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath ) { if ( LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } else if ( LHS == FalseVal && RHS == TrueVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps


<s> unsigned HOST_WIDE_INT len ; HOST_WIDE_INT align ; rtx src , dst , base ; rtx reg0 ; bool src_aligned , dst_aligned ; bool src_volatile , dst_volatile ; gcc_assert ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) ; len = UINTVAL ( operands [ <NUM_LIT> ] ) ; if ( len > <NUM_LIT> ) return false ; align = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( ! unaligned_access ) && ( len >= <NUM_LIT> ) && ( ( align & <NUM_LIT> ) != <NUM_LIT> ) ) return false ; dst = operands [ <NUM_LIT> ] ; dst_volatile = MEM_VOLATILE_P ( dst ) ; dst_aligned = MEM_ALIGN ( dst ) >= BITS_PER_WORD ; base = copy_to_mode_reg ( SImode , XEXP ( dst , <NUM_LIT> ) ) ; dst = adjust_automodify_address ( dst , VOIDmode , base , <NUM_LIT> ) ; src = operands [ <NUM_LIT> ] ; src_volatile = MEM_VOLATILE_P ( src ) ; src_aligned = MEM_ALIGN ( src ) >= BITS_PER_WORD ; base = copy_to_mode_reg ( SImode , XEXP ( src , <NUM_LIT> ) ) ; src = adjust_automodify_address ( src , VOIDmode , base , <NUM_LIT> ) ; if ( ! unaligned_access && ! ( src_aligned && dst_aligned ) ) return false ; if ( src_volatile || dst_volatile ) return false ; if ( ! ( dst_aligned || src_aligned ) ) return arm_gen_cpymemqi ( operands ) ; src = adjust_address ( src , src_aligned ? DImode : SImode , <NUM_LIT> ) ; dst = adjust_address ( dst , dst_aligned ? DImode : SImode , <NUM_LIT> ) ; while ( len >= <NUM_LIT> ) { len -= <NUM_LIT>


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; const SMLoc S = getLoc ( ) ; const AsmToken & FPImmTok = Parser . getTok ( ) ; if ( FPImmTok . isNot ( AsmToken :: Real ) ) return MatchOperand_NoMatch ; bool Valid ; unsigned ValID = MapperClass ( ) . fromString ( FPImmTok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> MVT SrcVT = N0 . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { if ( Op . getValueType ( ) != <STR_LIT> || ! <ISA_LIT>ScalarSSEf64 ) return SDValue ( ) ; return LowerUINT_TO_FP_i64 ( Op , DAG ) ; } else if ( SrcVT == <STR_LIT> ) { return LowerUINT_TO_FP_i32 ( Op , DAG ) ; } assert ( <NUM_LIT> && <STR_LIT> )


<s> CCInfo . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallConv , true , isVarArg ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign VA = RVLocs [ i ] ; SDValue Val ; if ( VA . needsCustom ( ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( )


<s> Branch . setOpcode ( <STR_LIT> ) ; Branch . addOperand ( MCOperand :: CreateExpr


<s> SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; auto & TD = DAG . getDataLayout ( ) ; EVT PTy = getPointerTy ( TD ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , DL , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || ABI . IsN64 ( ) ) { Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Addr , getPICJumpTableRelocBase ( Table , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , LocVT , LocInfo ) ) ; return true


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken


<s> if ( Val == <NUM_LIT> ) { if ( ! hasThumb ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( ! isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } else { if ( ! has<ISA_LIT> ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( )


<s> return ( __m128d ) __builtin_ia32_gathersiv2df ( _mm_undefined_pd ( ) , base , ( __v4si ) index , mask ,


<s> IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly


<s> if ( Subtarget -> isDarwin ( ) ) return new <ISA_LIT>DarwinAsmPrinter ( o , tm , tai , verbose ) ; return new <ISA_LIT>LinuxAsmPrinter ( o , tm , tai , verbose


<s> if ( SPDiff ) { int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; const <ISA_LIT>FrameLowering * FL = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getFrameLowering ( ) ; int NewRetAddrLoc = SPDiff + FL -> getReturnSaveOffset ( ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewRetAddr ) , false , false , <NUM_LIT> ) ; if ( isDarwinABI ) { int NewFPLoc = SPDiff + FL -> getFramePointerSaveOffset ( ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setEmitNOAT ( ) ; uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op


<s> void <ISA_LIT>_MachoTargetObjectFile :: getNameWithPrefix ( SmallVectorImpl < char > & OutName , const GlobalValue * GV , const TargetMachine & TM ) const { getMangler ( ) . getNameWithPrefix ( OutName , GV


<s> EVT SrcEVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_8 : return <NUM_LIT> ; case <STR_LIT> : case


<s> SDValue <ISA_LIT>TargetLowering :: lowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> && Op1 . getOpcode ( ) != <STR_LIT> && Op1 . getOpcode ( ) != <STR_LIT> && Op2 . getOpcode ( ) == <STR_LIT> ) { uint64_t Index = dyn_cast < ConstantSDNode >


<s> static void aarch64_init_builtins ( ) { aarch64_general_init_builtins ( )


<s> break ; case <STR_LIT> : isFloat = true ; case <STR_LIT> : if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? <STR_LIT> : <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } break ; } return NewMI


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI )


<s> int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx , SPReg , true ) . getFixed ( ) ; assert ( Offset >= <NUM_LIT> && SPReg == TRI -> getStackRegister ( ) ) ; return static_cast < unsigned >


<s> if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( SubVecTy ) ) && <STR_LIT> ) ; auto Mask = SVI -> getShuffleMask ( ) ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { Int8Ptr , SubVecTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { if ( StoreCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , LaneLen * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI , false


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set (


<s> unsigned Opcode ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_UADDE ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CarryInReg ) ; if ( ! RBI . constrainGenericRegister ( CarryInReg , <STR_LIT> , MRI ) ) return false ; Opcode = <STR_LIT> ; } else if ( auto val = getConstantVRegVal ( CarryInReg , MRI ) ) { if ( * val != <NUM_LIT> ) return false ; Opcode = <STR_LIT> ; } else return false ; MachineInstr & AddInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) ,

DstReg ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ;


<s> if ( MJTI == <NUM_LIT> ) return false ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> , e = T2JumpTables . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = T2JumpTables [ i ] ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned NumOps = MCID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( MCID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP


<s> sparc_leaf_function_p = <NUM_LIT> ; int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST ; } else if ( flag_delayed_branch ) { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_INCOMING_INT_ARG_FIRST ; } else { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST ; } if ( TARGET_ARCH64 && aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , int_arg_first + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , int_arg_first ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! SPARC_SIMM13_P ( delta ) ) { rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( vcall_offset < <NUM_LIT> ) ; emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( SPARC_SIMM13_P ( vcall_offset ) ) ; else if ( ! fixed_regs [ <NUM_LIT> ]


<s> case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Res . setOpcode ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : unsigned opcode ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) opcode = Inst

. getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } int Input = Idx / NumElems ; Idx -= Input * NumElems ; SVOps . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SVOp -> getOperand ( Input ) , DAG . getIntPtrConstant ( Idx ) ) ) ; } Output [ l ] = DAG . getNode ( <STR_LIT> , dl , NVT , & SVOps [ <NUM_LIT> ] , SVOps . size ( ) ) ; } else if ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) { Output [ l ] = DAG . getUNDEF ( NVT ) ; } else { SDValue Op0 = Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; SDValue Op1 = ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) ? DAG . getUNDEF ( NVT ) : Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] %


<s> assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmOp64 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ImmOp64 = convertIntToDoubleImm ( ImmOp64 ) ; uint32_t LoImmOp64 = Lo_32 ( ImmOp64 ) ; uint32_t HiImmOp64 = Hi_32 ( ImmOp64 ) ; unsigned TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; if ( ( LoImmOp64 == <NUM_LIT> ) && ! ( ( HiImmOp64 & <NUM_LIT> ) && ( HiImmOp64 & <NUM_LIT> ) ) ) { if ( isABI_N32 ( ) || isABI_N64 ( ) ) { if ( loadImmediate ( ImmOp64 , TmpReg , <STR_LIT> , false , false , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } if ( loadImmediate ( HiImmOp64 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; if ( has<ISA_LIT>32r2 ( ) ) { TOut . emitRR ( <STR_LIT> , FirstReg , <STR_LIT> , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , FirstReg , FirstReg , TmpReg , IDLoc , STI ) ; } else { TOut . emitRR ( <STR_LIT> , nextReg ( FirstReg ) , TmpReg , IDLoc , STI ) ; TOut . emitRR ( <STR_LIT> , FirstReg , <STR_LIT> , IDLoc , STI ) ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym

, MCSymbolRefExpr :: VK_None , getContext ( ) ) ;


<s> int vfp3_const_double_for_bits ( rtx operand ) { REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( operand ) ) return <NUM_LIT> ; REAL_VALUE_FROM_CONST_DOUBLE ( r0 , operand ) ; if ( exact_real_truncate ( DFmode , & r0 ) ) { HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & <NUM_LIT> ; if ( ( value != <NUM_LIT> ) && ( ( value & ( value - <NUM_LIT> ) ) == <NUM_LIT> ) ) return


<s> static inline bool isLoopStart ( MachineInstr & MI


<s> if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; } return true


<s> if ( fcpu_info ) f = fopen ( fcpu_info , <STR_LIT> ) ; else f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) goto not_found ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) { if ( strncmp ( buf , <STR_LIT> , sizeof ( <STR_LIT> ) - <NUM_LIT> ) == <NUM_LIT> ) { int i ; for ( i = <NUM_LIT> ; vendors_table [ i ] . vendor_no != NULL ; i ++ ) if ( strstr ( buf , vendors_table [ i ] . vendor_no ) != NULL ) { cpu_table = vendors_table [ i ] . vendor_parts ; break ; } } if ( strncmp ( buf , <STR_LIT> , sizeof ( <STR_LIT> ) - <NUM_LIT> ) == <NUM_LIT> ) { int i ; if ( cpu_table == NULL ) goto not_found ; for ( i = <NUM_LIT> ; cpu_table [ i ] . part_no != NULL ; i ++ ) if ( strstr ( buf ,


<s> if ( FirstRegOp != SecondRegOp ) emitRRR ( <STR_LIT> , FirstRegOp , SecondRegOp , <STR_LIT> , IDLoc , Instructions ) ; else createNop ( false , IDLoc , Instructions ) ; emitRRR ( <STR_LIT> , FirstRegOp , <STR_LIT> , SecondRegOp , IDLoc , Instructions ) ; return false


<s> return ( ( vec_double2 ) ( si_rotqmby ( ( qword )


<s> EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 (


<s> return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn )


<s> return ( __m512i ) __builtin_ia32_cvtpd2qq512_mask ( ( __v8df ) __A , ( __v8di )


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount !=


<s> const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & <STR_LIT> ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState ::


<s> if ( SetFlags && ( RDA -> isRegUsedAfter ( MI , <STR_LIT> ) || ! RDA -> hasSameReachingDef ( MI , & MBB -> back ( ) , <STR_LIT> ) ) ) SetFlags = false ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ; if ( SetFlags ) { MIB . addReg ( <STR_LIT>


<s> static reg_class_t xstormy16_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == GENERAL_REGS && ( MEM_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_MODIFY ) ) return EIGHT_REGS ; return rclass


<s> unsigned char <ISA_LIT>Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( GV -> hasDLLImportLinkage ( ) ) return <STR_LIT> ; bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( isPICStyleRIPRel ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return <STR_LIT> ; if ( isTargetDarwin ( ) ) { if ( GV -> hasDefaultVisibility ( ) && ( isDecl || GV -> isWeakForLinker ( ) ) ) return <STR_LIT> ; } else if ( ! isTargetWin64 ( ) ) { assert ( isTargetELF ( ) && <STR_LIT> ) ; if ( ! GV -> hasLocalLinkage ( ) && GV -> hasDefaultVisibility ( ) ) return <STR_LIT> ; } return <STR_LIT> ; } if ( isPICStyleGOT ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( isPICStyleStubPIC ( ) ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return <STR_LIT> ; if ( ! GV -> hasHiddenVisibility ( ) ) return <STR_LIT> ; if ( isDecl || GV -> hasCommonLinkage ( ) ) { return <STR_LIT> ; } return <STR_LIT> ; } if ( isPICStyleStubNoDynamic ( ) ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return <STR_LIT> ; if ( ! GV -> hasHiddenVisibility ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> WideInstSize = DL . getTypeSizeInBits ( Inst -> getType ( ) ) ; if ( cast < LoadInst > ( Inst ) -> getPointerAddressSpace ( ) ) return false ; } else WideInstSize = DL . getTypeSizeInBits ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( ShuffleElemSize == <NUM_LIT> && WideInstSize == <NUM_LIT> && Factor == <NUM_LIT> ) return true ; if ( ShuffleElemSize == <NUM_LIT> && isa < StoreInst > ( Inst ) && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ; if ( ShuffleElemSize == <NUM_LIT> && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize


<s> return & getSubtargetImpl ( ) -> getInstrItineraryData (


<s> MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor (


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; else { <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool (


<s> ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ]


<s> unsigned int proc ; size_t len = <NUM_LIT> ; sysctlbyname ( <STR_LIT> , & proc , & len , NULL , <NUM_LIT> ) ; if ( len > <NUM_LIT> ) switch ( proc ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> Instruction * InsertAfter = Reduction . AccIntAdd ; for ( auto & Pair : Reduction . PMACPairs ) { BinOpChain * PMul0 = Pair . first ; BinOpChain * PMul1 = Pair . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * PMul0 -> Root << <STR_LIT> << <STR_LIT> << * PMul1 -> Root << <STR_LIT> ) ; Acc = CreateSMLADCall ( PMul0 -> VecLd , PMul1 -> VecLd , Acc , PMul1 -> Exchange , InsertAfter ) ; InsertAfter = Acc ; } if ( Acc != Reduction . Phi ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; Reduction . AccIntAdd -> replaceAllUsesWith ( Acc ) ; return true ; } return


<s> if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant *


<s> const MCInstrDesc & Desc = TII . get ( TargetOpcode :: COPY ) ; TII . loadRegFromStack ( MBB , I , VR0 , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , Desc , Lo ) . addReg ( VR0 , RegState :: Kill ) ; TII . loadRegFromStack ( MBB , I , VR1 , FI , RC , & RegInfo , RegSize ) ; BuildMI ( MBB , I , DL , Desc , Hi ) . addReg ( VR1 ,


<s> bool <ISA_LIT>ExpandPseudo :: ExpandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = llvm :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI ) ; MBBI =


<s> if ( isa < ConstantSDNode > ( Op ) ) return true ; if ( isa < ConstantFPSDNode > ( Op ) )


<s> regno = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) { rtx reg , mem ; HOST_WIDE_INT offset ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno


<s> int64_t getImmU16Context ( ) const { assert ( ( Kind == Immediate || Kind


<s> ELFSegmentFactory :: const_iterator tls_seg = pParent . getTarget ( ) . elfSegmentTable ( ) . find ( llvm :: ELF :: PT_TLS , llvm :: ELF :: PF_R , <NUM_LIT> ) ; assert ( tls_seg != pParent . getTarget ( ) . elfSegmentTable ( ) . end ( ) ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc


<s> return ScoreboardHazardRecognizer :: getHazardType (


<s> unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems / <NUM_LIT> , dl , <STR_LIT> ) ; if ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; SDValue Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec2 , ShiftBits ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , Vec2 ) ; } if ( IdxVal == <NUM_LIT> ) { SDValue Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec2 , ShiftBits ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl ,


<s> <ISA_LIT>LoadStoreOpt ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>LoadStoreOptPass ( * PassRegistry :: getPassRegistry ( )


<s> uint32_t Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; const uint8_t * Tables [ ] = { DecoderTable32 , DecoderTableFallback32 } ; for ( auto Table : Tables ) { DecodeStatus Result = decodeInstruction ( Table , MI , Insn , Address , this , STI ) ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MI . insert ( MI . begin ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; const MCOperand & Imm4Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Imm4Op . isImm ( ) && <STR_LIT> ) ; MI . addOperand ( Imm4Op ) ; break ; } case <STR_LIT> : case


<s> bool isFPCopy ( MachineInstr * MI ) { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> )


<s> bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , & global_options_set , existing_options ) ; } else cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( fndecl &&


<s> EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VecVT . isPow2VectorType ( ) || VecVT . getVectorNumElements ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Mul ) ; unsigned LegalLanes = <NUM_LIT> / ( ShftAmt + <NUM_LIT> ) ; EVT LegalVecVT = <STR_LIT> ( ScalarType , LegalLanes ) ; if ( VecVT . getSizeInBits ( ) < <NUM_LIT> ) { EVT ExtVecVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / VecVT . getVectorNumElements ( ) ) , VecVT . getVectorNumElements ( ) ) ; SDValue Inp0 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext0 . getOperand ( <NUM_LIT> ) ) ; SDValue Inp1 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext1 . getOperand ( <NUM_LIT> ) ) ; Inp0 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 ) ; Inp1 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp1 ) ; SDValue VQDMULH = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 , Inp1 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , VQDMULH ) ; Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Trunc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Trunc ) ; } assert ( VecVT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned NumParts = VecVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue > Parts ; for ( unsigned I = <NUM_LIT> ; I < NumParts ; ++ I ) { SDValue Inp0 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Ext0 . getOperand ( <NUM_LIT> ) , DAG . getVectorIdxConstant ( I * LegalLanes , DL ) ) ; SDValue Inp1 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Ext1 . getOperand ( <NUM_LIT> ) , DAG . getVectorIdxConstant ( I * LegalLanes , DL ) ) ; SDValue VQDMULH = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 , Inp1 ) ; Parts . push_back (


<s> const char * getPassName ( ) const override { return


<s> if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ; return std :: make_pair ( ExeGeneric ,


<s> lowerLongBranchLUi ( MI , OutMI ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> ) ; return true ; case


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return


<s> if ( ! MRI . getRegClassOrNull ( DstReg ) ) { const LLT DstTy = MRI . getType ( DstReg ) ; const TargetRegisterClass * RC = getRegClass ( DstTy , DstReg , MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false


<s> rtx lane_idx = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( lane_idx ) ) aarch64_simd_lane_bounds ( lane_idx , <NUM_LIT> , UINTVAL ( totalsize ) / UINTVAL ( elementsize ) , exp ) ; else error ( <STR_LIT> , exp ) ; } else error ( <STR_LIT> , exp ) ; return const0_rtx ; } aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_index ) args [ k ] = SIMD_ARG_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = SIMD_ARG_CONSTANT ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) { rtx arg = expand_normal ( CALL_EXPR_ARG ( exp , ( expr_args_k ) ) ) ; bool op_const_int_p = ( CONST_INT_P ( arg ) && ( * insn_data [ icode ] . operand [ operands_k ] . predicate ) ( arg , insn_data [ icode ] . operand [ operands_k ] . mode ) ) ; args [ k ] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG ; } else args [ k ] = SIMD_ARG_COPY_TO_REG ; } args [ k ] = SIMD_ARG_STOP ; return aarch64_simd_expand_args ( target , icode , ! is_void , exp , & args [


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned Immediate = <NUM_LIT> ; if ( ! matchVectorShuffleWithSHUFPD ( VT , V1 , V2 , Immediate ,


<s> if ( getRelaxedOpcodeBranch ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr (


<s> EmitMachineConstantPoolValue ( MachineConstantPoolValue * MCPV ) { int Size = TM . getDataLayout ( ) -> getTypeAllocSize ( MCPV -> getType ( ) ) ; <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPV ) ; MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; OS << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; MCSym = OutContext . GetOrCreateSymbol ( OS . str ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant


<s> __inline__ static void sh_media_FTRVSUB_S ( const void * mtrxg , const void * fvh , const void * fvi , void * fvf ) { sh_media_FTRV_S ( mtrxg , fvh , fvf ) ; sh_media_FVSUB_S ( fvf ,


<s> static inline bool isSVECpyImm ( int64_t Imm ) { int64_t Mask = ~ int64_t ( std :: numeric_limits < std :: make_unsigned_t < T >> :: max ( ) ) ; if ( ( Imm & Mask ) != <NUM_LIT> && ( Imm & Mask ) != Mask ) return false ; if ( Imm & <NUM_LIT> ) return int8_t ( Imm ) == T ( Imm ) ; if ( Imm & <NUM_LIT> ) return int16_t ( Imm ) == T


<s> if ( is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: DynamicNoPIC ; } else if ( T . isOSWindows ( ) && is64Bit ) RM = Reloc :: PIC_ ; else RM = Reloc :: Static ; } if ( RM == Reloc :: DynamicNoPIC ) { if ( is64Bit ) RM = Reloc :: PIC_ ; else if ( ! T . isOSDarwin ( ) ) RM = Reloc :: Static ; } if ( RM == Reloc :: Static && T . isOSDarwin ( ) && is64Bit ) RM = Reloc :: PIC_ ; if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = is64Bit ? CodeModel :: Large : CodeModel :: Small ; X -> InitMCCodeGenInfo ( RM , CM


<s> if ( ! Ops . empty ( ) ) { unsigned Opcode ; if ( Ops . size ( ) == <NUM_LIT> ) { Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; } else { assert ( Ops . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Opcode = IsThumb2 ? <STR_LIT> : <STR_LIT> ; SDValue WriteValue [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; Ops . insert ( Ops . begin ( ) + <NUM_LIT> , WriteValue , WriteValue + <NUM_LIT> ) ; } Ops . push_back ( getAL ( CurDAG , DL ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ; } std :: string SpecialReg = RegString -> getString ( ) . lower ( ) ; int BankedReg = getBankedRegisterMask ( SpecialReg ) ; if ( BankedReg != - <NUM_LIT> ) { Ops = { CurDAG -> getTargetConstant ( BankedReg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Ops ) ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return nullptr ; Ops = { N -> getOperand ( <NUM_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ; } SmallVector < StringRef , <NUM_LIT> > Fields


<s> MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; } return true ; } else if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } else { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> )


<s> else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! TT . isArch64Bit ( ) && TT . isOSWindows ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> bool simd_p = insn && CALL_P ( insn ) && aarch64_simd_call_p ( insn ) ; return FP_REGNUM_P ( regno ) && maybe_gt ( GET_MODE_SIZE ( mode ) ,


<s> if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue Op = lowerVectorShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Op ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } unsigned Scale , Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = isSVEScaledImmInstruction ( MI . getOpcode ( ) ) ; int64_t Offset = IsMulVL ? ( SOffset . getScalableBytes ( ) ) : ( SOffset . getBytes ( ) ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset


<s> code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << hard_regno_nregs ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( x ) + is_dest ) ) ; return <NUM_LIT> ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << hard_regno_nregs ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return <NUM_LIT> ; } case SET : return regs_used ( SET_SRC ( x ) , <NUM_LIT> ) | regs_used ( SET_DEST ( x ) , <NUM_LIT> ) ; case RETURN : return <NUM_LIT> ; case


<s> if ( Subtarget . isLittleEndian ( ) ) VectorIndex = <NUM_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getTargetConstant ( VectorIndex , dl , <STR_LIT> ) ) ; return


<s> static unsigned int aarch64_case_values_threshold ( void ) { if ( optimize > <NUM_LIT> && selected_cpu -> tune -> max_case_values !=


<s> if ( lsb > msb ) Check ( S , MCDisassembler :: SoftFail ) ; uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << ( msb + <NUM_LIT> ) ) - <NUM_LIT> ; uint32_t lsb_mask = ( <NUM_LIT> << lsb ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( ~ ( msb_mask ^ lsb_mask ) ) ) ; return


<s> SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> , Half = NumElems / <NUM_LIT> ; i != Half ; ++ i ) { Mask . push_back ( i + Half ) ; Mask . push_back ( i + NumElems + Half ) ; } return DAG . getVectorShuffle ( VT , dl , V1 , V2 , &


<s> if ( ! I -> getOperand ( i ) . isFI ( ) ) continue ; const TargetInstrDesc & Desc = TII . get ( I -> getOpcode ( ) ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) Limit = std :: min (

Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ;


<s> MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent


<s> return false ; } Tag = Ret . getValue ( ) ; Parser . Lex ( ) ; } else { const MCExpr * AttrExpr ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( AttrExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( AttrExpr ) ; if ( check ( ! CE , TagLoc , <STR_LIT> ) ) return true ; Tag = CE -> getValue ( ) ; } if ( Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; StringRef StringValue ; int64_t IntegerValue = <NUM_LIT> ; bool IsIntegerValue = ( ( Tag != <STR_LIT> ) && ( Tag != <STR_LIT> ) && ( Tag != <STR_LIT> ) ) ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( Tag != <STR_LIT> && Tag != <STR_LIT> ) getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; else { <STR_LIT> ID = ( Tag == <STR_LIT> ) ? <STR_LIT> ( StringValue ) : <STR_LIT> ( StringValue ) ; if ( ID == <STR_LIT> :: INVALID ) return Error ( ValueExprLoc , ( Tag == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue