<s> AU . addPreserved < MachineModuleInfoWrapperPass > ( ) ; AU . setPreservesAll ( ) ; ModulePass :: getAnalysisUsage (


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FI -> setCalleeSavedFrameSize ( CSI . size ( ) * SlotSize ) ; unsigned Opc = is64Bit ? <STR_LIT>


<s> if ( getParser ( ) . ParseExpression ( Val , End ) ) return ErrorOperand ( Start , <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ) ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT> ( RegNo , Start , End


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op .

getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> void printNamedImmOperand ( const MCInst * MI ,


<s> BuildMI ( MBB , InsertBefore , DebugLoc ( ) , MCID ) . addReg ( DestReg0 , RegState :: Define | getUndefRegState ( IsUndef ) , SubIdx0 ) . addReg ( DestReg1 , RegState :: Define | getUndefRegState ( IsUndef )

, SubIdx1 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , FIOperandNum , this


<s> return ( vector unsigned int ) __builtin_altivec_vsubcuw ( ( vector signed int ) a1 , ( vector


<s> bool ix86_check_no_addr_space ( rtx insn ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN


<s> SDValue <ISA_LIT>TargetLowering :: makeAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT PtrVT = Op . getValueType ( ) ; if ( isPositionIndependent ( ) ) { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setHasCalls ( true ) ; auto GlobalN = dyn_cast < GlobalAddressSDNode > ( Op ) ; if ( isa < ConstantPoolSDNode > ( Op ) || ( GlobalN && GlobalN -> getGlobal ( )


<s> gen_shift = gen_lshrv2si3 ; break ; case E_V8HImode : if ( ! TARGET_SSE4_1 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V4SImode ; gen_and = gen_andv4si3 ; gen_pack = gen_sse4_1_packusdw ; gen_shift = gen_lshrv4si3 ; break ; case E_V8QImode : c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V4HImode ; gen_and = gen_andv4hi3 ; gen_pack = gen_mmx_packuswb ; gen_shift = gen_lshrv4hi3 ; break ; case E_V16QImode : c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V8HImode ; gen_and = gen_andv8hi3 ; gen_pack = gen_sse2_packuswb ; gen_shift = gen_lshrv8hi3 ; break ; case E_V16HImode : if ( ! TARGET_AVX2 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V8SImode ; gen_and = gen_andv8si3 ; gen_pack = gen_avx2_packusdw ; gen_shift = gen_lshrv8si3 ; end_perm = true ; break ; case E_V32QImode : if ( ! TARGET_AVX2 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V16HImode ; gen_and = gen_andv16hi3 ; gen_pack = gen_avx2_packuswb ; gen_shift = gen_lshrv16hi3 ; end_perm = true ; break ; default : return false ; } odd = d -> perm [ <NUM_LIT> ] ; if ( odd > <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != <NUM_LIT> * i + odd ) return false ; if ( d -> testing_p ) return true ; dop0 = gen_reg_rtx ( half_mode ) ; dop1 = gen_reg_rtx ( half_mode ) ; if ( odd == <NUM_LIT> ) { t = gen_const_vec_duplicate ( half_mode , GEN_INT ( c ) ) ; t = force_reg ( half_mode , t ) ; emit_insn ( gen_and ( dop0 , t , gen_lowpart ( half_mode , d -> op0 ) ) ) ; emit_insn ( gen_and ( dop1 , t , gen_lowpart ( half_mode , d -> op1 ) ) ) ; } else { emit_insn ( gen_shift ( dop0 , gen_lowpart ( half_mode , d -> op0 ) , GEN_INT ( s ) ) ) ; emit_insn ( gen_shift ( dop1 , gen_lowpart ( half_mode , d -> op1 ) , GEN_INT ( s ) ) ) ; } if ( TARGET_AVX2 && end_perm ) { op = gen_reg_rtx ( d -> vmode ) ; t = gen_reg_rtx ( V4DImode ) ; emit_insn ( gen_pack ( op , dop0 , dop1 ) ) ; emit_insn ( gen_avx2_permv4di_1 ( t , gen_lowpart ( V4DImode , op ) , const0_rtx , const2_rtx ,

const1_rtx , GEN_INT ( <NUM_LIT> ) ) ) ;


<s> RegisterTarget < Triple :: fpga32 , false > X (


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; <STR_LIT> Branch ( getBranchInfo ( I ) ) ; if ( ! Branch . Target -> isMBB ( ) ) return true ; if ( Branch . Type != <STR_LIT> ) return true ; if ( Branch . CCMask == <STR_LIT> ) { if ( ! AllowModify ) { TBB = Branch . Target -> getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( Branch . Target -> getMBB (


<s> static SDValue combine<ISA_LIT>ShufflesConstants ( ArrayRef < SDValue > Ops , ArrayRef < int > Mask , SDValue Root , bool HasVariableMask , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Root . getSimpleValueType ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; unsigned NumMaskElts = Mask . size ( ) ; unsigned MaskSizeInBits = SizeInBits / NumMaskElts ; unsigned NumOps = Ops . size ( ) ; bool OneUseConstantOp = false ; SmallVector < APInt , <NUM_LIT> > UndefEltsOps ( NumOps ) ; SmallVector < SmallVector < APInt , <NUM_LIT> > , <NUM_LIT> > RawBitsOps ( NumOps ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { SDValue SrcOp = Ops [ i ] ; OneUseConstantOp |= SrcOp . hasOneUse ( ) ; if ( ! getTargetConstantBitsFromNode ( SrcOp , MaskSizeInBits , UndefEltsOps [ i ] , RawBitsOps [ i ] ) ) return SDValue ( ) ; } if ( ! OneUseConstantOp && ! HasVariableMask ) return SDValue ( ) ; APInt UndefElts ( NumMaskElts , <NUM_LIT> ) ; APInt ZeroElts ( NumMaskElts , <NUM_LIT>


<s> HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; stackAlignment =


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64


<s> return ( __m256i ) __builtin_ia32_pternlogq256_maskz ( ( __v4di ) __A , ( __v4di ) __B , (

__v4di ) __C , ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


) _mm_setzero_ph ( ) , ( __mmask8 ) __U ) ;


<s> SDValue BAHi = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue BALo = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue BAGOTOffset = DAG . getBlockAddress ( BA , ValTy , true , GOTFlag ) ; BAGOTOffset = DAG . getNode ( <STR_LIT> ,


<s> const <ISA_LIT>TargetLowering * getTLI


<s> if ( FnSecName != <STR_LIT> ) { EHSecName += FnSecName ; } const MCSectionELF * EHSection = nullptr ; if ( const MCSymbol * Group = FnSection . getGroup ( ) ) { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags | ELF :: SHF_GROUP , FnSection . getEntrySize ( ) , Group -> getName ( ) ) ; } else


<s> StackAlignment = <NUM_LIT> ; DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasPaired = false ; HasAltivec = false ; HasQPX = false ; HasVSX = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasLDBRX =


<s> } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget .


<s> else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return <NUM_LIT> ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic &&

symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ;


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> (


<s> inline unsigned char getAM3Offset ( unsigned AM3Opc ) { return AM3Opc &


<s> bool <ISA_LIT>FrameLowering :: twoUniqueScratchRegsRequired ( MachineBasicBlock * MBB ) const { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = * ( MBB -> getParent ( ) ) ; bool HasBP = RegInfo -> hasBasePointer


<s> } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ; } return true


<s> for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + WhichResult ) ) return false ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ; return true


<s> bool isGP64 ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP * <NUM_LIT> ; else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP * <NUM_LIT> ; if ( ! TARGET_SIMD ) return regmove_cost -> GP2FP + regmove_cost -> FP2GP + regmove_cost -> FP2FP ; return regmove_cost -> FP2FP ; } if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP ; else if ( to == GENERAL_REGS )


<s> static unsigned getLoadRegOpcode ( unsigned DestReg , const TargetRegisterClass * RC , bool isStackAligned , const TargetMachine & TM ) { return getLoadStoreRegOpcode ( DestReg , RC , isStackAligned


<s> return new <ISA_LIT>TargetWinCOFFStreamer (


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> if ( APF . isPosZero ( ) ) return SignBit ; APF . clearSign ( ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APF ) ; } else { CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getLowBitsSet ( SizeInBits , SizeInBits - <NUM_LIT> ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) , <NUM_LIT> ) ; SDValue Val = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( ! isa < ConstantFPSDNode > ( Op0 ) ) Val = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ,


<s> Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo ( )


<s> SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> bool isPostIdxReg ( ) const { return isPostIdxRegShifted ( ) &&


<s> size_rtx = XEXP ( set_src , <NUM_LIT> ) ; shl_sext_kind ( left_rtx , size_rtx , & cost ) ; return cost


<s> switch ( Opc ) { default : return false ; case <STR_LIT> : NegateOperand = true ; case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; case <STR_LIT> : NegateOperand = true ; case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; } LoadSDNode * LoadNode = nullptr ; SDValue InputChain ; if ( ! isFusableLoadOpStorePattern ( StoreNode , StoredVal , CurDAG , LoadNode , InputChain ) ) return false ; SDValue Operand = StoredVal . getOperand ( <NUM_LIT> ) ; auto * OperandC = dyn_cast < ConstantSDNode > ( Operand ) ; if ( ! OperandC ) return false ; auto OperandV = OperandC -> getAPIntValue ( ) ; if ( NegateOperand )


<s> if ( TARGET_HARD_FLOAT && TARGET_MAVERICK && IS_CIRRUS_REGNUM ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || ( mode == DImode ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return TRUE ; if ( mode == DFmode ) return ( ( regno -


<s> if ( low_n > <NUM_LIT> ) { n += <NUM_LIT> ; low_n -= <NUM_LIT> ; } } else { low_n = ( ( mode ) == TImode ? <NUM_LIT> : n >= <NUM_LIT> ? ( n & <NUM_LIT> ) : - ( ( - n ) & <NUM_LIT> ) ) ; n -= low_n ; } base_reg = gen_reg_rtx ( SImode ) ; val = force_operand ( gen_rtx_PLUS ( SImode , xop0 , GEN_INT ( n ) ) , NULL_RTX ) ; emit_move_insn ( base_reg , val ) ; x = ( low_n == <NUM_LIT> ? base_reg : gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( low_n ) ) ) ; } else if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ; if ( CONSTANT_P ( xop1 ) && ! symbol_mentioned_p ( xop1 ) ) xop1 = force_reg ( SImode , xop1 ) ; if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_MINUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == CONST_INT && optimize > <NUM_LIT> ) { unsigned int bits ; HOST_WIDE_INT mask , base , index ; rtx base_reg ; bits = ( mode == SImode ) ? <NUM_LIT> : <NUM_LIT> ; mask = ( <NUM_LIT> << bits ) - <NUM_LIT> ; base = INTVAL ( x ) & ~ mask ; index = INTVAL ( x ) & mask ; if ( bit_count ( base & <NUM_LIT> ) > ( <NUM_LIT> - bits ) / <NUM_LIT> ) { base |= mask ; index -= mask ; } base_reg = force_reg ( SImode , GEN_INT ( base ) ) ; x = gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( index


<s> return __builtin_aarch64_sqdmlal2_nv4si ( __a ,


<s> unsigned SubIdx = ( IsI64 ? <STR_LIT> : <STR_LIT> ) ; bool DstIsLarger , SrcIsLarger ; tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg ( SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , CvtDesc , DstReg ) .


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { return


<s> bool <ISA_LIT>AsmParser :: tryParseNeonVectorRegister ( OperandVector & Operands ) { if ( getTok ( ) . isNot ( AsmToken :: Identifier ) ) return true ; SMLoc S = getLoc ( ) ; StringRef Kind ; unsigned Reg ; OperandMatchResultTy Res = tryParseVectorRegister ( Reg , Kind , RegKind :: NeonVector ) ; if ( Res !=


<s> unsigned VecSize = NumElts * ScalarBits ; unsigned NumLanes = VecSize / <NUM_LIT> ; unsigned NumEltsPerLane = NumElts / NumLanes ; assert ( ( VecSize == <NUM_LIT> || VecSize == <NUM_LIT> || VecSize == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( ScalarBits == <NUM_LIT> || ScalarBits == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RawMask . size ( ) ; i < e ; ++ i ) { uint64_t M = RawMask [ i ] ; M = ( ScalarBits == <NUM_LIT> ? ( ( M >> <NUM_LIT> ) & <NUM_LIT> ) : ( M & <NUM_LIT> ) ) ; unsigned LaneOffset = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; ShuffleMask . push_back ( ( int ) ( LaneOffset


<s> return ( __mmask64 ) __builtin_ia32_vpshufbitqmb512_mask ( ( __v64qi ) __A , ( __v64qi )


<s> uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags & <STR_LIT> ; isCracked = TSFlags & <STR_LIT> ; return ( <STR_LIT> ) ( TSFlags


<s> else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par


( ) : default_external_stack_protect_fail ( ) ;


<s> int Offset = <NUM_LIT> ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI -> setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI -> setObjectZExt ( FI , true ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { MFI -> setObjectSExt ( FI , true ) ; } if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI -> setObjectOffset ( FI ,


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : ReplaceableInstrs ) if ( Row [ domain - <NUM_LIT> ] == opcode ) return Row ; return


<s> virtual void markPhysRegUsed ( unsigned PhysReg


<s> bool Thumb1InstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops ) const { if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNum == <NUM_LIT>


<s> assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Indices [ i ] , SubVecTy -> getVectorNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL .


<s> for ( i = nregs - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) emit_insn ( gen_rtx_SET ( VOIDmode , simplify_gen_subreg ( reg_mode , dst , mode , i * reg_mode_size ) , simplify_gen_subreg ( reg_mode , src , mode , i * reg_mode_size ) ) ) ; } else { int i ; int j = - <NUM_LIT> ; bool used_update = false ; if ( MEM_P ( src ) && INT_REGNO_P ( reg ) ) { rtx breg ; if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_DEC ) { rtx delta_rtx ; breg = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; delta_rtx = ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_INC ? GEN_INT ( GET_MODE_SIZE ( GET_MODE ( src ) ) ) : GEN_INT ( - GET_MODE_SIZE ( GET_MODE ( src ) ) ) ) ; emit_insn ( TARGET_32BIT ? gen_addsi3 ( breg , breg , delta_rtx ) : gen_adddi3 ( breg , breg , delta_rtx ) ) ; src = replace_equiv_address ( src , breg ) ; } else if ( ! offsettable_memref_p ( src ) ) { rtx basereg ; basereg = gen_rtx_REG ( Pmode , reg ) ; emit_insn ( gen_rtx_SET ( VOIDmode , basereg , XEXP ( src , <NUM_LIT> ) ) ) ; src = replace_equiv_address ( src , basereg ) ; } breg = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( breg ) == PLUS || GET_CODE ( breg ) == LO_SUM ) breg = XEXP ( breg , <NUM_LIT> ) ; if ( REG_P ( breg ) && REGNO ( breg ) >= REGNO ( dst ) && REGNO ( breg ) < REGNO ( dst ) + nregs ) j = REGNO ( breg ) - REGNO ( dst ) ; } if ( GET_CODE ( dst ) == MEM && INT_REGNO_P ( reg ) ) { rtx breg ; if ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( dst , <NUM_LIT> ) )


<s> void <ISA_LIT>AsmParser :: cvtStrdPre ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst ,


<s> set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode


<s> bool <ISA_LIT>InstructionSelector :: selectExtractElt ( MachineInstr & I , MachineRegisterInfo & MRI ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_EXTRACT_VECTOR_ELT && <STR_LIT> ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( DstReg ) ; const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( WideTy . getSizeInBits ( ) >= NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; assert ( NarrowTy . isScalar ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID (


<s> bool hasFastVariableCrossLaneShuffle ( )


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM , bool isRoot , unsigned Depth ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> && ! AM . isRIPRel ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false


<s> return getFP16Imm ( FPImm . bitcastToAPInt


<s> const <ISA_LIT>ABIInfo & getABI ( ) const { return ABI


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> int nbbs = loop -> num_nodes ; int vec_cost = data -> cost [ vect_body ] , not_vec_cost = <NUM_LIT> ; int i , density_pct ; for ( i = <NUM_LIT> ; i < nbbs ; i ++ ) { basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p (


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState (


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; return true ; } const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; assert ( ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <=

RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ;


<s> AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved <


<s> declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , <STR_LIT> ) ; } } addr = convert_memory_address ( Pmode , addr ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ; addr_reg = gen_reg_rtx ( Pmode ) ; emit_move_insn ( addr_reg , addr ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , addr_reg ) , gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight


<s> return ( __m512i ) __builtin_ia32_psrld512_mask ( ( __v16si ) __A , ( __v4si )


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> if ( ! N . hasOneUse ( ) ) return false ; return SelectImmShifterOperand ( N , A


<s> for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI ->


<s> if ( ! I -> isBranch ( ) ) break ; if ( ! getBranchInfo ( * I ) . Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ; return llvm :: getInstrPredicate (


<s> static void scaleShuffleMask ( int Scale , ArrayRef < int > Mask , SmallVectorImpl < int > & ScaledMask ) { assert ( <NUM_LIT> < Scale && <STR_LIT> ) ; int NumElts = Mask . size ( ) ; ScaledMask . assign ( static_cast < size_t > ( NumElts * Scale ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [


<s> Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI

. getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> case PLUS : arg1 = XEXP ( addr , <NUM_LIT> ) ; arg2 = XEXP ( addr , <NUM_LIT> ) ; if ( CONSTANT_P ( arg1 ) ) base = arg2 , offset = arg1 ; else base = arg1 , offset = arg2 ; gcc_assert ( REG_P ( base ) ) ; if ( REG_P ( offset ) ) { int reg_offset = REGNO ( offset ) ; int reg_base = REGNO ( base ) ; int reg_dest = REGNO ( operands [ <NUM_LIT> ] ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest + <NUM_LIT> , reg_base , reg_offset ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest , reg_dest + <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest + <NUM_LIT> , reg_dest + <NUM_LIT> ) ; } else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; if ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( base ) ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } } break ; case


<s> else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_X23_X24_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_X25_X26_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_X27_X28_PAIR ; else { Reg1 = getDRegFromBReg ( Reg1 ) ; Reg2 = getDRegFromBReg ( Reg2 ) ; if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_D8_D9_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_D10_D11_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_D12_D13_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_FRAME_D14_D15_PAIR ; else return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } break ; } } } if ( ! HasFP ) { if ( StackSize > <NUM_LIT> ) return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; CompactUnwindEncoding |= CU


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> ,


<s> MaskedLoadSDNode * Mld = cast < MaskedLoadSDNode > ( N ) ; if ( Mld -> getExtensionType ( ) == <STR_LIT> ) { if ( SDValue ScalarLoad = reduceMaskedLoadToScalarLoad ( Mld , DAG , DCI ) ) return ScalarLoad ; if ( ! Subtarget . hasAVX512 ( ) ) if ( SDValue Blend = combineMaskedLoadConstantMask ( Mld , DAG , DCI ) ) return Blend ; } if ( Mld -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = Mld -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT LdVT = Mld -> getMemoryVT ( ) ; SDLoc dl ( Mld ) ; assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned FromSz = LdVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i


<s> if ( tree attr = lookup_sve_type_attribute ( type ) ) if ( tree id = TREE_VALUE ( chain_index ( <NUM_LIT> , TREE_VALUE (

attr ) ) ) ) return IDENTIFIER_POINTER ( id ) ;


<s> BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BVN || ! BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElementBits ) || SplatBitSize > ElementBits ) return false ; Cnt = SplatBits . getSExtValue ( ) ; return


<s> StringRef name = Tok . getString ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: parseVariantKind ( name ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . getKind ( ) != AsmToken :: LParen ) return false ; Parser . Lex ( ) ; const MCExpr * subExpr ; if ( Parser . parseParenExpression ( subExpr , EndLoc ) ) return false ; EVal = adjustPICRelocation ( VK


<s> assert ( FPReg == <STR_LIT> && <STR_LIT> ) ; FlushPendingOffset ( ) ; FPReg = Reg ; FPOffset = SPOffset + Offset ; const MCRegisterInfo * MRI = getContext ( ) . getRegisterInfo ( ) ; UnwindOpAsm . EmitSetSP ( MRI -> getEncodingValue


<s> static void mips_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT bytes_per_iter ) { rtx_code_label * label ; rtx src_reg , dest_reg , final_src , test ; HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; mips_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; mips_adjust_block_mem ( dest , bytes_per_iter , & dest_reg ,


<s> gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . setOffset ( TmpOffset ) ; if ( ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . setKind ( Address :: FrameIndexBase ) ; Addr . setFI ( SI -> second ) ; return true ; } break ; } } if ( ! Addr . isValid ( ) ) Addr . setReg ( getRegForValue ( Obj ) ) ; return Addr .


<s> assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( TM -> getRelocationModel ( ) == Reloc :: Static


<s> return ( __m256d ) __builtin_ia32_roundpd256 ( ( __v4df )


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , Subtarget , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT>


<s> static void init_insn_group_barriers ( void ) { memset ( rws_sum , <NUM_LIT> , sizeof ( rws_sum ) ) ; first_instruction =


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT>


<s> else setAction ( { Op , s32 } , Libcall ) ; } for ( unsigned Op : { G_SEXT , G_ZEXT } ) { setAction ( { Op , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { Op , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_CONSTANT , s32 } , Legal ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { setAction ( { G_FADD , s32 } , Legal ) ; setAction ( { G_FADD , s64 } , Legal ) ; setAction ( { G_LOAD , s64


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl


<s> <ISA_LIT>MCAsmInfoMicrosoft :: <ISA_LIT>MCAsmInfoMicrosoft ( const Triple & Triple ) { if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT>


<s> bool isGRH32 ( ) const { return isReg ( GRH32Reg )


<s> bool hasLeonCycleCounter ( ) const { return HasLeonCycleCounter


<s> JCE . emitAlignment ( <NUM_LIT> ) ; void * Addr = ( void * ) ( JCE . getCurrentPCValue ( ) ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; intptr_t EmittedAddr ; if ( Fn != ( void * ) ( intptr_t ) <ISA_LIT>CompilationCallback ) EmittedAddr = ( intptr_t ) Fn ; else EmittedAddr = ( intptr_t ) <ISA_LIT>CompilationCallback ; int Hi = ( ( unsigned ) EmittedAddr & <NUM_LIT>


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) SumV2Indices += i ; else if ( Mask [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) return true ; if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( Mask [ i ] >= <NUM_LIT> ) NumV1OddIndices += i % <NUM_LIT> ; if ( NumV2OddIndices < NumV1OddIndices


<s> bool hasCMov ( ) const { return HasCMov || <ISA_LIT>SSELevel >= SSE1 ||


<s> else { machine_mode half_mode ; gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; half_mode = mode == DImode ? SImode : DImode ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_lshr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { ix86_expand_clear ( scratch ) ; emit_insn ( gen_x86_shift_adj_1 ( half_mode , low [ <NUM_LIT> ] , high [

<NUM_LIT> ] , operands [ <NUM_LIT> ] , scratch ) ) ;


<s> unsigned int nelts_per_vq = INTVAL ( cnt_pat [ <NUM_LIT> ] ) ; unsigned int factor = INTVAL ( cnt_pat [ <NUM_LIT> ] ) * nelts_per_vq ; return aarch64_output_sve_cnt_immediate ( prefix , operands , pattern , factor ,


<s> else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + NumElts + WhichResult ) ) return false ; } } if ( M . size ( ) ==

NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isMem ( BDMem


<s> bool isShuffleEquivalentImpl ( ArrayRef < int > Mask , ArrayRef < const int * > Args ) { if ( Mask . size ( ) != Args . size ( ) ) return false ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; ++ i ) { assert ( * Args [ i ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != * Args [ i ] ) return false ; } return


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } } Base = Addr


<s> CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CS . arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment (


<s> case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt ,


<s> rtx_insn * and_insn ; rtx and_operation = find_alignment_op ( insn , base_reg , & and_insn ) ; if ( and_operation != <NUM_LIT> ) { rtx src_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; df_ref src_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn


<s> Binary |= ( IsThumb ? <STR_LIT> : II -> getPredicate ( & MI ) ) << <STR_LIT> ; unsigned RegT = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; RegT = II -> getRegisterInfo (


<s> case ST : return <STR_LIT> ; case ISH : return <STR_LIT> ; case ISHST : return <STR_LIT> ; case NSH : return


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; <STR_LIT> Ty = getRegTy ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MF ) ; unsigned Reg = Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . getReg ( ) ==


<s> HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) return false ; if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ; * BI = HWLoopInfo . ExitBranch ; return


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } LLVM_FALLTHROUGH ; } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands , ! Mnemonic . startswith ( <STR_LIT> ) ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; auto AdjacentToken = getLexer ( ) . peekTok ( false ) ; bool ExpectIdentifier = Parser . getTok ( ) . is ( AsmToken :: Dollar ) && ( AdjacentToken . is ( AsmToken :: Identifier ) || AdjacentToken . is ( AsmToken :: Integer ) ) ; if ( ! ExpectIdentifier ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool IsNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( IsNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: create ( std :: numeric_limits < int32_t > :: min ( ) , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } LLVM_FALLTHROUGH ; } case AsmToken :: Colon : { S = Parser . getTok ( ) . getLoc ( ) ; <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: create ( RefKind , SubExprVal ,


<s> return __builtin_mve_vcmpltq_n_v4si ( __a ,


<s> StackOffset SPOffset = SVEStackSize + StackOffset :: get ( MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) , ObjectOffset ) ; if ( hasFP ( MF ) && ( SPOffset . getFixed ( ) || FPOffset . getScalable ( ) < SPOffset . getScalable ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR ) ) ScalableOffset = - SVEStackSize ; if ( ! UseFP && ( isFixed || isCSR ) ) ScalableOffset = SVEStackSize ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FPOffset ) + ScalableOffset ; } if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else { assert ( ! MFI . hasVarSizedObjects ( ) && <STR_LIT> ) ; FrameReg = <STR_LIT> ; if ( canUseRedZone ( MF ) ) Offset -= AFI ->


<s> return ( __m512i ) __builtin_ia32_vpermt2vard512_mask ( ( __v16si ) __I , ( __v16si ) __A , (


<s> if ( GET_CODE ( sym ) == LABEL_REF ) return gen_rtx_CONST ( GET_MODE ( sym ) , gen_rtx_UNSPEC ( GET_MODE ( sym ) , gen_rtvec ( <NUM_LIT>


<s>
O
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if
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{
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<s> for ( MachineBasicBlock & MBB : MF ) OutOffset [ & MBB ] = INT32_MAX ; ReversePostOrderTraversal < MachineFunction * > RPO ( & MF ) ; for ( MachineBasicBlock * MBB : RPO ) { int64_t Offset = - <NUM_LIT> ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) Offset = std :: max ( Offset , OutOffset [ Pred ] ) ; if ( Offset == - <NUM_LIT> ) Offset = INT32_MAX ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { int64_t Amount = getWinAllocaAmount ( & MI , MRI ) ; Lowering L = getLowering ( Offset , Amount ) ; Lowerings [ & MI ] = L ; switch ( L ) { case Sub : Offset += Amount ; break ; case TouchAndSub : Offset = Amount ; break ; case Probe : Offset = <NUM_LIT> ; break ; } } else if ( MI . isCall ( ) || isPushPop ( MI ) ) { Offset = <NUM_LIT>


<s> const MCExpr * TOCDeltaExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: CreateHa ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: CreateLo ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT>

) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ;


<s> bool NotRIPRel = IndexReg . getReg ( ) || BaseReg . getReg ( ) ; if ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) ) { printOperand ( MI , Op + <NUM_LIT> , <STR_LIT> , NotRIPRel ) ; } else { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { unsigned ScaleVal = MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; unsigned BaseRegOperand = <NUM_LIT> , IndexRegOperand = <NUM_LIT> ; if ( IndexReg . getReg ( ) == <STR_LIT> || IndexReg . getReg ( ) == <STR_LIT> ) { assert ( ScaleVal == <NUM_LIT> && <STR_LIT> ) ; std :: swap ( BaseReg , IndexReg ) ; std :: swap ( BaseRegOperand , IndexRegOperand ) ; } O <<


<s> static <ISA_LIT>Operand CreateToken ( StringRef Str ) { <ISA_LIT>Operand Res ; Res . Kind = Token ; Res . Tok . Data = Str . data ( ) ; Res . Tok . Length = Str .


<s> if ( MulImm >= <NUM_LIT> && MulImm <= Max ) { MulImm *= Scale ; Imm = CurDAG -> getTargetConstant ( MulImm , SDLoc ( N )


<s> return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv16qi ( ( int8x16_t )


<s> MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) ,


<s> size = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; if ( size < <NUM_LIT> ) return NULL_RTX ; rounded_size = rx_round_up ( size , UNITS_PER_WORD ) ; if ( rounded_size + bytes_so_far > MAX_NUM_ARG_BYTES ) return NULL_RTX ; if ( ! named ) return NULL_RTX ; if ( ( type == NULL || AGGREGATE_TYPE_P ( type ) ) && ( size % UNITS_PER_WORD ) != <NUM_LIT> )


<s> if ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && Op . hasOneUse ( ) && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && onlyZeroFlagUsed ( SDValue ( N , <NUM_LIT> ) ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; const APInt & ShAmt = Op . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ShAmt . ult ( BitWidth ) ) { unsigned MaskBits = BitWidth - ShAmt . getZExtValue ( ) ; APInt Mask = Op . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , MaskBits ) : APInt :: getLowBitsSet ( BitWidth , MaskBits ) ; if ( Mask . isSignedIntN ( <NUM_LIT> ) ) { Op = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } } if ( Op . getOpcode ( ) != <STR_LIT> || ! Op . hasOneUse ( ) ) return SDValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; unsigned NewOpc ; switch ( Op . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT>


<s> if ( Reg > <NUM_LIT> ) return false ; aTReg = Reg ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) { MVT PtrVT = Op . getValueType ( ) ; GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op ) ; GlobalValue * GV = GSDN -> getGlobal ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , PtrVT , GSDN -> getOffset ( ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = GSDN -> getDebugLoc ( ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( )


<s> SDValue <ISA_LIT>TargetLowering :: InsertBitToMaskVector ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Elt = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , Elt ) ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) ) { if ( IdxVal ) EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , EltInVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; return


<s> return isUndefInRange ( Mask , NumElts / <NUM_LIT> , NumElts /


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) return SDValue ( ) ; if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t MulAmt = C -> getZExtValue ( ) ; if ( isPowerOf2_64 ( MulAmt ) || MulAmt == <NUM_LIT> || MulAmt == <NUM_LIT> || MulAmt == <NUM_LIT> ) return SDValue ( ) ; uint64_t MulAmt1 = <NUM_LIT> ; uint64_t MulAmt2 = <NUM_LIT> ; if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { DebugLoc DL = N -> getDebugLoc ( ) ; if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; SDValue NewMul ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , VT ) ) ; DCI . CombineTo ( N , NewMul ,


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; MachineInstr * EarlierMI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg


<s> } Init -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Init ) ; } else BuildMov ( LoLoop . Preheader -> instr_back ( ) , DestReg , Copy . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Reduce . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Reduce . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reduce ) ; MachineInstr & VPSEL = Reduction -> VPSEL ; if ( VPSEL . getOperand ( <NUM_LIT> ) . getReg ( ) != DestReg ) BuildMov ( VPSEL , VPSEL . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Copy << <STR_LIT> << VPSEL << <STR_LIT> ) ; Copy . eraseFromParent ( ) ; VPSEL . eraseFromParent (


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << ( MO2 . getImm ( ) << <NUM_LIT> ) ; } O << <STR_LIT>


<s> } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND ->


<s> static void dispatch_forest ( fma_forest * forest ) { forest -> dispatch (


<s> if ( <STR_LIT> != RB . getID ( ) ) return TargetOpcode :: G_ADD ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { if ( STI . hasAVX512 ( ) && STI .


<s> unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegM ) ; RegM = get<ISA_LIT>RegisterNumbering ( RegM ) ; if ( ! isSPVFP ) Binary |= RegM ; else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT>


<s> static SDValue getVShift ( bool isLeft , EVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , SDLoc dl ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; MVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; MVT ScalarShiftTy = TLI . getScalarShiftAmountTy ( SrcOp . getValueType ( ) ) ; SDValue ShiftVal = DAG . getConstant (


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , IsO32 , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , getTargetMachine ( ) . Options . UseSoftFloat , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue


<s> return __builtin_ia32_comisdgt ( ( __v2df ) __A , ( __v2df )


<s> MVT VT = Vec0 . getSimpleValueType ( ) ; return DAG -> getVectorShuffle ( VT , dl , Vec0


<s> return MachinePointerInfo ( MF . getPSVManager (


<s> Type * OpPtrTy = PointerType :: getUnqual ( II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Value * Ptr = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , OpPtrTy ) ; return new StoreInst ( II . getArgOperand ( <NUM_LIT> ) , Ptr , false , Align ( <NUM_LIT> ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : { Type * OpPtrTy = PointerType :: getUnqual ( II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Value * Ptr = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , OpPtrTy ) ; return new StoreInst ( II . getArgOperand ( <NUM_LIT> ) , Ptr , false , Align ( <NUM_LIT> ) ) ; } case <STR_LIT> : if ( Constant * Mask = dyn_cast < Constant > ( II . getArgOperand ( <NUM_LIT> ) ) ) { assert ( cast < FixedVectorType > ( Mask -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; bool AllEltsOk = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Constant * Elt = Mask -> getAggregateElement ( i ) ; if ( ! Elt || ! ( isa < ConstantInt > ( Elt ) || isa < UndefValue > ( Elt ) ) ) { AllEltsOk = false ; break ; } } if ( AllEltsOk ) { Value * Op0 = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , Mask -> getType ( ) ) ; Value * Op1 = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , Mask -> getType ( ) ) ; Value * Result = UndefValue :: get ( Op0 -> getType ( ) ) ; Value * ExtractedElts [ <NUM_LIT> ] ; memset ( ExtractedElts , <NUM_LIT> , sizeof ( ExtractedElts ) ) ; for ( unsigned i = <NUM_LIT> ;


<s> unsigned AddReg = AddendMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned KilledProdReg = MI -> getOperand ( KilledProdOp ) . getReg ( ) ; unsigned OtherProdReg = MI -> getOperand ( OtherProdOp ) . getReg ( ) ; unsigned AddSubReg = AddendMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned KilledProdSubReg = MI -> getOperand ( KilledProdOp ) . getSubReg ( ) ; unsigned OtherProdSubReg = MI -> getOperand ( OtherProdOp ) . getSubReg ( ) ; bool AddRegKill = AddendMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool KilledProdRegKill = MI -> getOperand ( KilledProdOp ) . isKill ( ) ; bool OtherProdRegKill = MI -> getOperand ( OtherProdOp ) . isKill ( ) ; bool AddRegUndef = AddendMI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool KilledProdRegUndef = MI -> getOperand ( KilledProdOp ) . isUndef ( ) ; bool OtherProdRegUndef = MI -> getOperand ( OtherProdOp ) . isUndef ( ) ; unsigned OldFMAReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( OldFMAReg == KilledProdReg ) continue ; assert ( OldFMAReg == AddendMI -> getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ; ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( KilledProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( KilledProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( AddReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( OtherProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( KilledProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( KilledProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( AddSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( OtherProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( KilledProdRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( AddRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( OtherProdRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( KilledProdRegUndef ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( AddRegUndef ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( OtherProdRegUndef ) ; MI -> setDesc ( TII -> get ( AltOpc ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains2 [ <NUM_LIT> ] , MemOpChains2 . size ( ) ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true


<s> assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset

) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ;


<s> static rtx find_alignment_op ( rtx_insn * insn , rtx base_reg ) { df_ref base_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; rtx and_operation = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) break ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) break ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( and_operation != <NUM_LIT> ) break ; } return and_operation


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , IsThumb ( IsThumb

) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) {


<s> Value * <ISA_LIT>RegisterSema :: getSF ( <STR_LIT> SF ) { Value * SV = SFVals


<s> void <ISA_LIT>TargetStreamer :: emitSetFP ( unsigned FpReg , unsigned SpReg , int64_t Offset


<s> SMLoc S = getLoc ( ) ; Parser . Lex ( ) ; StringRef Kind ; int64_t FirstReg = tryMatchVectorRegister ( Kind , true ) ; if ( FirstReg == - <NUM_LIT> ) return true ; int64_t PrevReg = FirstReg ; unsigned Count = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; unsigned Space = ( PrevReg < Reg ) ? ( Reg - PrevReg ) : ( Reg + <NUM_LIT> - PrevReg ) ; if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { return Error ( Loc , <STR_LIT> ) ; } Count += Space ; } else { while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; PrevReg = Reg ; ++ Count ; } } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( Count > <NUM_LIT> ) return Error ( S , <STR_LIT> ) ; unsigned NumElements = <NUM_LIT> ; char ElementKind = <NUM_LIT> ; if ( ! Kind . empty ( ) ) parseValidVectorKind ( Kind , NumElements , ElementKind ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , NumElements , ElementKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT>


<s> uint32_t CPUType = cantFail ( MachO :: getCPUType ( TT ) ) ; uint32_t CPUSubType = cantFail ( MachO :: getCPUSubType ( TT ) ) ; return create<ISA_LIT>MachObjectWriter ( Is64Bit , CPUType ,


<s> return ! nds32_naked_function_p ( decl


<s> if ( SrcReg == <STR_LIT> ) { Warning ( IDLoc , <STR_LIT> ) ; if ( loadImmediate ( <NUM_LIT> , DstReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; return false ; } unsigned Opc ; if ( ImmValue > - <NUM_LIT> && ImmValue < <NUM_LIT> ) { ImmValue = - ImmValue ; Opc = isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opc = <STR_LIT> ; } if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( Opc , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return


<s> if ( ! InstrConverterBase :: isLegal ( MI , TII ) ) return false ; Register DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstReg . isPhysical ( ) && ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ) return false ; Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg . isPhysical ( ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) return false ; return true


<s> if ( arg . aggregate_type_p ( ) ) return true ; HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size < <NUM_LIT> ||


<s> void <ISA_LIT>BranchFixup :: adjustBBOffsetsAfter ( MachineBasicBlock * BB ) { unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF -> getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( LogAlign ) ; unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits == KnownBits ) break ; BBInfo [ i ] . Offset = Offset ; BBInfo [ i ] .


<s> AttributeItem item = Contents [ i ] ; switch ( item . Type ) { case AttributeItem :: HiddenAttribute : break ; case AttributeItem :: NumericAttribute : Result += getULEBSize ( item . Tag


<s> const <ISA_LIT>FrameLowering * getFrameLowering (


<s> } if ( IdxVal + SubVecNumElems == NumElems ) { SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( SubVecNumElems * <NUM_LIT> == NumElems ) { Vec = DAG . getNode ( <STR_LIT> , dl , SubVecVT , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , Vec , ZeroIdx ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getTargetConstant ( NumElems - IdxVal , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; } Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , SubVec ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } NumElems = WideOpVT . getVectorNumElements ( ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( ShiftRight , dl , <STR_LIT> ) ) ; unsigned LowShift = NumElems - IdxVal ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , DAG . getTargetConstant ( LowShift , dl , <STR_LIT> ) ) ; Low = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Low , DAG . getTargetConstant ( LowShift , dl , <STR_LIT> ) ) ; unsigned HighShift = IdxVal + SubVecNumElems ; SDValue High = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , DAG . getTargetConstant ( HighShift , dl , <STR_LIT> ) ) ; High = DAG . getNode ( <STR_LIT> , dl , WideOpVT , High , DAG . getTargetConstant ( HighShift


<s> bool A15SDOptimizer :: usesRegClass ( MachineOperand & MO , const TargetRegisterClass * TRC ) { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) return MRI ->

getRegClass ( Reg ) -> hasSuperClassEq ( TRC ) ;


<s> return hasVSX ( ) && isLittleEndian ( ) &&


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart


<s> return __builtin_mve_vmlsdavxq_p_sv4si ( __a ,


<s> return ( uint64x2_t ) ( __a <= <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>LongBranchPass ( <ISA_LIT>TargetMachine & tm ) { return new <ISA_LIT>LongBranch ( tm


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } case <NUM_LIT> : { switch ( Model ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return ( Em64T ) ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return ( Em64T ) ? <STR_LIT> : <STR_LIT> ; } } default : return <STR_LIT> ; } } else if ( memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { switch ( Family ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : switch ( Model ) { case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } case <NUM_LIT> : switch ( Model ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI


<s> for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + <NUM_LIT> , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > (


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Reg = <NUM_LIT> ; if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; return LoadRegFromStackSlot ( MF , DL , Reg , FrameIdx , & <STR_LIT> , NewMIs , NonRI , SpillsVRS ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( TM . getSubtargetImpl ( ) -> isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; SpillsVRS = true


<s> if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget ->


<s> __rv . __o = __builtin_neon_vld3v4hi ( ( const __builtin_neon_hi * ) __a ) ; return __rv .


<s> bool has<ISA_LIT>32r2 ( ) const { return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc


<s> unsigned ScaleDown = ( <NUM_LIT> - X . getSimpleValueType ( ) . getSizeInBits ( ) ) + ShiftAmt ; if ( MaskLZ < ScaleDown ) return true ; MaskLZ -= ScaleDown ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; KnownBits Known = DAG . computeKnownBits ( X ) ; if ( MaskedHighBits != Known . Zero ) return true ; MVT VT = N . getSimpleValueType


<s> enum machine_mode mode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( ! TARGET_SSE && ! warnedsse ) { if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) { warnedsse = true ; warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } } if ( ! TARGET_MMX && ! warnedmmx ) { if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode )


<s> static int unspec_fcmla ( int rot ) { switch ( rot ) { case <NUM_LIT> :


<s> bool isS17Imm ( ) const { switch ( Kind ) { case


<s> if ( ! isThumb ) BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; computeBlockSize ( UserMBB ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> GetInstSizeInBytes ( * UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = & * MI ; } -- MI ; if ( LastIT )


<s> bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return


<s> std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( CPEntry & CPE : CPEs ) { if ( CPE . CPEMI == CPEMI ) continue ; if ( CPE . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPE . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPE .


<s> case Expression : return true ; case Immediate : case ContextImmediate : return isInt < <NUM_LIT> > ( getImmS16Context ( ) ) ; default : return


<s> bool nds32_rtx_costs_impl ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( speed ) return rtx_cost_model . speed_prefer ( x ,


<s> const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS ,


<s> lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL

, IsN64 ? <STR_LIT> : <STR_LIT> , VT ) ;


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; FpFormatTy Format = getFpFormat ( ) ; if ( Format == FP_FORMAT_S || Format == FP_FORMAT_W ) return getReg ( <STR_LIT> , IntVal ) ; if ( Format == FP_FORMAT_D ) { if ( isFP64 ( ) ) { return getReg ( <STR_LIT> , IntVal ) ; } if ( ( IntVal > <NUM_LIT> ) || ( IntVal % <NUM_LIT> != <NUM_LIT> ) ) return - <NUM_LIT> ; return getReg ( <STR_LIT> , IntVal / <NUM_LIT> ) ; } } return -


<s> if ( ( Subtarget . isABI_FPXX ( ) && ! Subtarget . hasMTHC1 ( ) ) || ( FP64 && ! Subtarget . useOddSPReg ( ) ) ) { const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & TRI = * static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; const TargetRegisterClass * RC2 = FP64 ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC2 ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( LoReg , HiReg ) ; TII . storeRegToStack ( MBB , I , LoReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . storeRegToStack ( MBB , I , HiReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) ,


<s> static SDValue LowerMMXCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; EVT ResVT = Op . getValueType ( ) ; assert ( ResVT == <STR_LIT> || ResVT == <STR_LIT> || ResVT == <STR_LIT> || ResVT == <STR_LIT> ) ; int Mask [ <NUM_LIT> ] ; SDValue InVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue VecOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; InVec = Op . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp , InVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( NumElts / <NUM_LIT> + <NUM_LIT> ) ) ; } else { InVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; SDValue VecOp2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; Mask [ <NUM_LIT> ] = <NUM_LIT> ; Mask [ <NUM_LIT> ] = <NUM_LIT> ; VecOp = DAG . getVectorShuffle ( <STR_LIT> , dl , VecOp , VecOp2


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAreaOffset ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; bool OffsetFitsMnemonic = ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ? isUInt < <NUM_LIT> > ( Offset ) : isInt < <NUM_LIT> > ( Offset


<s> for ( unsigned Pos = NumTZ + <NUM_LIT> ; Pos <= <NUM_LIT> ; ++ Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) ITStates . push_back ( CCBits ) ; else ITStates . push_back (


<s> unsigned <ISA_LIT>TargetLowering :: GetAlignedArgumentStackSize ( const unsigned StackSize , SelectionDAG & DAG ) const { const Align StackAlignment = Subtarget . getFrameLowering ( ) -> getStackAlign ( ) ; const uint64_t SlotSize = Subtarget . getRegisterInfo ( ) -> getSlotSize ( ) ; assert ( StackSize % SlotSize


<s> Info . AI -> setAlignment ( NewAlignment ) ; uint64_t Size = Info . AI -> getAllocationSizeInBits ( * DL ) . getValue ( ) / <NUM_LIT> ; uint64_t AlignedSize = alignTo ( Size , kTagGranuleSize ) ; if ( Size == AlignedSize ) return ; Type * AllocatedType = Info . AI -> isArrayAllocation ( ) ? ArrayType :: get ( Info . AI -> getAllocatedType ( ) , cast < ConstantInt > ( Info . AI -> getArraySize ( ) ) -> getZExtValue ( ) ) : Info . AI -> getAllocatedType ( ) ; Type * PaddingType = ArrayType :: get ( Type :: getInt8Ty ( F -> getContext ( ) ) , AlignedSize - Size ) ; Type * TypeWithPadding = StructType :: get ( AllocatedType , PaddingType ) ; auto * NewAI = new AllocaInst ( TypeWithPadding , Info . AI -> getType ( ) -> getAddressSpace ( ) , nullptr , <STR_LIT>