<s> const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra )


<s> doPeepholeLoadStoreADDI ( ) ; doPeepholeBuildPairF64SplitF64 (


<s> selectMemRegAddr ( Op , Base , Offset ) ; OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false


<s> bool TailAgnostic = true ; bool UsesMaskPolicy = <STR_LIT> ( TSFlags ) ; bool MaskAgnostic = UsesMaskPolicy ; unsigned UseOpIdx ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; uint64_t Policy = Op . getImm ( ) ; assert ( Policy <= ( <STR_LIT> | <STR_LIT> ) && <STR_LIT> ) ; TailAgnostic = Policy & <STR_LIT> ; MaskAgnostic = Policy & <STR_LIT> ; } else if ( MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; if ( UsesMaskPolicy ) MaskAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) { TailAgnostic = true ; if ( UsesMaskPolicy ) MaskAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) TailAgnostic = true ; } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands


<s> assert ( hasStdExtV ( ) && <STR_LIT> ) ; assert ( RVVVectorLMULMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorLMULMax


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int div_factor = <NUM_LIT> ; emit_move_insn ( tmp , gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ) ; if ( BYTES_PER_RISCV_VECTOR . is_constant ( ) ) { gcc_assert ( value . is_constant ( ) ) ; riscv_emit_move ( dest , GEN_INT ( value . to_constant ( ) ) ) ; return ; } else if ( ( factor % vlenb ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( div_factor != <NUM_LIT> ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ; riscv_expand_mult_with_const_int ( mode , dest , tmp , factor / ( vlenb / div_factor ) ) ; HOST_WIDE_INT constant = offset - factor ; if ( constant == <NUM_LIT> ) return ; else if ( SMALL_OPERAND ( constant ) ) riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; else { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( constant ) , mode ) ; constant = CONST_LOW_PART ( constant ) ; riscv_emit_move ( tmp , high ) ; riscv_expand_op ( PLUS , mode , dest , tmp , dest ) ; riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant


<s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } } if ( NeedInsertVSETVLI ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } PrevVSETVLIMI =


<s> if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags


<s> switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind =


<s> <ISA_LIT>MCExpr :: VariantKind TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO12 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO12 ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , Ctx ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr ,


<s> case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS ) ) ; SMLoc S = getLoc (


<s> if ( info . dirty_p ( ) ) info . set_unknown ( ) ; else { const auto dem = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . local_dem ; gcc_assert ( dem == * m_vector_manager -> vector_exprs [ i ] ) ; insn_info * insn = dem . get_insn ( ) ; gcc_assert ( insn && insn -> rtl ( ) ) ; rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_vector_manager -> to_delete_vsetvls . add ( insn -> rtl ( ) ) ; continue ; } gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn -> rtl ( ) ) ; gcc_assert ( vector_config_insn_p ( PREV_INSN ( insn ->


<s> SDValue <ISA_LIT>TargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , One ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , XLenMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue HiFalse = DAG . getNode ( <STR_LIT> , DL , VT , Lo , ShamtMinusXLen ) ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , Zero ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC ,


<s> unsigned Res = MO . getImm ( ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return Res


<s> OS << '%' << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ; OS << <STR_LIT> ; OS << MI -> getOperand ( opNum + <NUM_LIT> )


<s> for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf


<s> assert ( OldValReg != MaskReg && <STR_LIT> ) ; assert ( ScratchReg != MaskReg && <STR_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( OldValReg ) . addReg ( NewValReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ,

DestReg ) . addReg ( OldValReg ) . addReg ( ScratchReg ) ;


<s> static int getLibCallID ( const MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI ) { const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) . id ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Identifier . size ( ) ) ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset


<s> bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; } else { return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr ::

VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ;


<s> const char * Sym = N -> getSymbol ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue GALo = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , GAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , GALo ) , <NUM_LIT> ) ; return MNLo


<s> int arg_offset = <NUM_LIT> ; if ( base -> use_mask_predication_p ( ) ) { if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; } if ( ! function_returns_void_p ( ) && base -> has_merge_operand_p ( ) ) { if ( use_real_merge_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_vundef_operand ( mode ) ; } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; if ( base -> apply_mask_policy_p ( ) ) add_input_operand

( Pmode , get_mask_policy_for_pred ( pred ) ) ;


<s> HOST_WIDE_INT offset ; bool interrupt_save_prologue_temp = false ; unsigned int regno , i , num_x_saved = <NUM_LIT> , num_f_saved = <NUM_LIT> ; frame = & cfun -> machine -> frame ; if ( cfun -> machine -> interrupt_handler_p ) { HOST_WIDE_INT step1 = riscv_first_stack_step ( frame ) ; if ( ! SMALL_OPERAND ( frame -> total_size - step1 ) ) interrupt_save_prologue_temp = true ; } memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; if ( ! cfun -> machine -> naked_p ) { for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) || ( interrupt_save_prologue_temp && ( regno == RISCV_PROLOGUE_TEMP_REGNUM ) ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; } offset = RISCV_STACK_ALIGN ( crtl -> outgoing_args_size ) ; offset += RISCV_STACK_ALIGN ( get_frame_size ( ) ) ; frame -> frame_pointer_offset = offset ; if ( frame -> fmask ) offset += RISCV_STACK_ALIGN ( num_f_saved * UNITS_PER_FP_REG ) ; frame -> fp_sp_offset = offset - UNITS_PER_FP_REG ; if ( frame -> mask ) { unsigned x_save_size = RISCV_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + riscv_save_libcall_count ( frame -> mask ) ; if ( RISCV_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) { if ( TARGET_RVE ) x_save_size = <NUM_LIT> * UNITS_PER_WORD ; frame -> save_libcall_adjustment = x_save_size ; } offset += x_save_size ; } frame -> gp_sp_offset = offset - UNITS_PER_WORD ; frame -> hard_frame_pointer_offset = offset ; offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; offset += RISCV_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; frame -> arg_pointer_offset = offset - crtl -> args .


<s> SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; return DAG . getStore ( Chain , DL , FI , Addr , MachinePointerInfo (


<s> GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; int64_t Offset = N -> getOffset ( ) ; const GlobalValue * GV = N -> getGlobal ( ) ; bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; SDValue Addr = getAddr ( N , Ty , DAG ,


<s> if ( ! valid_type ( sew , lmul_log2 , true ) ) return <STR_LIT> ; std :: stringstream mode ; mode << <STR_LIT> << sew << to_lmul ( lmul_log2 ) << <STR_LIT> ; return mode . str ( )


<s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , MaxVL ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addDef ( <STR_LIT> ) . addReg ( MaxVL , getKillRegState ( true ) ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addDef ( <STR_LIT> ) . addReg ( SavedVL , getKillRegState ( true ) ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> )


<s> if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF32 ) Reg = State . AllocateReg ( ArgFPR32s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s , ArgFPR32s ) ; else Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear (


<s> if ( * this == Other ) return * this ; return <STR_LIT> ( )


<s> void reset ( ) override { static_cast < <ISA_LIT>TargetStreamer * > ( getTargetStreamer ( ) ) -> reset (


<s> if ( Width == <NUM_LIT> ) return getLRForRMW8 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW16 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW32


<s> auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM )


<s> if ( ( Slct . getOpcode ( ) != <STR_LIT> && Slct . getOpcode ( ) != <STR_LIT> ) || ! Slct . hasOneUse ( ) ) return SDValue ( ) ; auto isZeroOrAllOnes = [ ] ( SDValue N , bool AllOnes ) { return AllOnes ? isAllOnesConstant ( N ) : isNullConstant ( N ) ; } ; bool SwapSelectOps ; unsigned OpOffset = Slct . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue TrueVal = Slct . getOperand ( <NUM_LIT> + OpOffset ) ; SDValue FalseVal = Slct . getOperand ( <NUM_LIT> + OpOffset ) ; SDValue NonConstantVal ; if ( isZeroOrAllOnes ( TrueVal , AllOnes ) ) { SwapSelectOps = false ; NonConstantVal = FalseVal ; } else if ( isZeroOrAllOnes ( FalseVal , AllOnes ) ) { SwapSelectOps = true ; NonConstantVal = TrueVal ; } else return SDValue (


<s> static rtx riscv_pass_fpr_single ( enum machine_mode type_mode , unsigned regno , enum machine_mode value_mode ) { rtx x = gen_rtx_REG (


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg (


<s> if ( NoAliases || ! printAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ; printAnnotation ( O ,


<s> unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | (


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = TFI -> getFrameIndexReference ( MF ,


<s> assert ( i < <STR_LIT> && <STR_LIT> ) ; return UserReservedRegister [


<s> return true ; } auto * BO = dyn_cast < BinaryOperator > ( Index ) ; if ( ! BO ) return false ; if ( BO -> getOpcode ( ) != Instruction :: Add && BO -> getOpcode ( ) != Instruction :: Or && BO -> getOpcode ( ) != Instruction :: Mul && BO -> getOpcode ( ) != Instruction :: Shl ) return false ; if ( BO -> getOpcode ( ) == Instruction :: Shl && ! isa < Constant > ( BO -> getOperand ( <NUM_LIT> ) ) ) return false ; if ( BO -> getOpcode ( ) == Instruction :: Or && ! haveNoCommonBitsSet ( BO -> getOperand ( <NUM_LIT> ) , BO -> getOperand ( <NUM_LIT> ) , * DL ) ) return false ; Value * OtherOp ; if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else { return false ; } if ( ! L -> isLoopInvariant ( OtherOp ) ) return false ; Value * SplatOp = getSplatValue ( OtherOp ) ; if ( ! SplatOp ) return false ; if ( ! matchStridedRecurrence ( Index , L , Stride , BasePtr , Inc , Builder ) ) return false ; unsigned StepIndex = Inc -> getOperand ( <NUM_LIT> ) == BasePtr ? <NUM_LIT> : <NUM_LIT> ; unsigned StartBlock = BasePtr -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; Value * Step = Inc -> getOperand ( StepIndex ) ; Value * Start = BasePtr ->


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return riscv_force_address (


<s> unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; Known . resetAll ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) break ; KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , Known2 ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT>


<s> bool selectShiftMask32 ( SDValue N , SDValue


<s> if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset + elt_size ; return <NUM_LIT> ; } return - <NUM_LIT> ; } default : if ( n < <NUM_LIT> && ( ( SCALAR_FLOAT_TYPE_P ( type ) && GET_MODE_SIZE ( TYPE_MODE ( type ) ) <= UNITS_PER_FP_ARG ) || ( INTEGRAL_TYPE_P ( type ) && GET_MODE_SIZE ( TYPE_MODE ( type ) ) <= UNITS_PER_WORD ) ) ) { fields [ n ]


<s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh (


<s> HandleSDNode Dummy ( CurDAG -> getRoot ( ) ) ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_end ( ) ; bool MadeChange = false ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * --


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Src = DAG . getFreeze ( Op . getOperand ( <NUM_LIT> ) ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; bool Ignored ; APFloat Point5Pred = APFloat ( <NUM_LIT> ) ; Point5Pred . convert ( FltSem , APFloat :: rmNearestTiesToEven , & Ignored ) ; Point5Pred . next ( true ) ; SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Abs , DAG . getConstantFP ( Point5Pred , DL , VT ) ) ; MVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Adjust ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem


<s> return log2LdstWidth ( Opcode ) == <NUM_LIT> ? isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset

) : isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction &


<s> static SDValue convertLocVTToValVT ( SelectionDAG & DAG , SDLoc DL , CCValAssign & VA , SDValue Chain , SDValue Value ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA


<s> if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( Fixup . getTargetKind ( ) ) { default : return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset <


<s> static void riscv_init_builtin_types ( void ) { if ( ! float16_type_node ) { riscv_float16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( riscv_float16_type_node )


<s> case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm12


<s> MachineInstr & Tail = * MRI -> use_begin ( DestReg ) -> getParent ( ) ; switch ( Tail . getOpcode ( ) ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; return false ; case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S , STI ) ; return new <ISA_LIT>TargetStreamer ( S


<s> if ( info1 . get_vlmul ( ) == info2 . get_vlmul ( ) && ! info2 . demand_p ( DEMAND_SEW ) && ! info2 . demand_p ( DEMAND_RATIO ) ) return false ; return true


<s> if ( CurInfo . isCompatible ( Require ) ) return false ; if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && Require . hasSameVTYPE ( CurInfo ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT>

|| DefMI -> getOpcode ( ) == <STR_LIT> ) {


<s> static void riscv_reorg ( void ) { if ( TARGET_SAVE_RESTORE )


<s> else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; return MIN ( STACK_BOUNDARY , MAX ( PARM_BOUNDARY


<s> static SDValue performADDCombine ( SDNode * N , SelectionDAG


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_None : if ( IsPCRel ) return getPCRelReloc ( Kind ) ; return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : llvm_unreachable (


<s> edge_iterator ei ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & local_dem = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . local_dem ; auto & reaching_out = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . reaching_out ; if ( e -> dest -> index == cfg_bb -> index ) continue ; if ( e -> flags & EDGE_COMPLEX ) continue ; if ( e -> dest -> index == EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> index ) continue ; if ( ! local_dem . valid_or_dirty_p ( ) ) continue ; if ( local_dem . available_p ( prop ) ) continue ; if ( ! local_dem . compatible_p ( prop ) ) continue ; if ( propagate_avl_across_demands_p ( prop , local_dem ) ) continue ; vector_insn_info new_info = local_dem . merge ( prop , GLOBAL_MERGE ) ; new_info . set_insn ( local_dem . get_insn ( ) ) ; if ( local_dem . dirty_p


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>InsertVSETVLIPass ( ) )


<s> unsigned getReg ( ) const override { assert ( Kind == KindReg && <STR_LIT> ) ; return Reg .


<s> const auto info = m_vector_manager -> vector_insn_infos [ INSN_UID ( rinsn ) ] ; emit_vsetvl_insn ( VSETVL_DISCARD_RESULT , EMIT_BEFORE , info , NULL_RTX ,


<s> CInst . setLoc ( IDLoc ) ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( ( Res ? CInst : Inst ) , getSTI ( ) ) ; return false ; } case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero


<s> static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) { return MCDisassembler ::


<s> bool isGuaranteedNotToTrap ( const MachineInstr & MI


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { auto & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; if ( Subtarget . hasStdExtV ( ) ) return CSR_XLEN_F32_VEC_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return CSR_ILP32F_LP64F_VEC_SaveList ; switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_SaveList ; case <STR_LIT> : case <STR_LIT> : return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectRORI ( SDValue N , SDValue & RS1 , SDValue & Shamt ) { MVT XLenVT = Subtarget -> getXLenVT ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( XLenVT == <STR_LIT> ) { uint64_t VC = N . getConstantOperandVal ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( ( <NUM_LIT> - VC ) , SDLoc ( N ) , N . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; RS1 = N . getOperand ( <NUM_LIT> ) ; return true ; } if ( XLenVT == <STR_LIT> ) { uint32_t VC = N . getConstantOperandVal ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( ( <NUM_LIT> - VC ) , SDLoc ( N ) , N . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; RS1 = N . getOperand ( <NUM_LIT> ) ; return


<s> switch ( Op . getOpcode ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( )


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , STI , O ) ) printInstruction ( NewMI , STI , O ) ; printAnnotation ( O , Annot


<s> case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIP ( SDValue Dest , SDValue & SRC1 , SDValue & SRC2 ) { return RI5CY_pclip_check ( CurDAG , Dest , SRC1 , SRC2 ,


<s> Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7_6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4_3 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit2_1 = ( Value


<s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD


<s> DEBUG_FUNCTION void debug ( const vector_infos_manager * info ) { info -> dump (


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( Subtarget . hasStdExtF ( ) && VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasStdExtD ( ) && VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; default : break ; } } if ( Subtarget . hasStdExtF ( ) || Subtarget . hasStdExtD ( ) ) { std :: pair < unsigned , unsigned > FReg = StringSwitch < std :: pair < unsigned , unsigned >> ( Constraint . lower ( ) ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case

( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Case ( <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) . Default ( { - <NUM_LIT> , - <NUM_LIT> } ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : case MachineOperand :: MO_Immediate : { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MC ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; <ISA_LIT>InstPrinter :: printOperand ( MC , O ) ; break ; } case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( MO . getTargetFlags (


<s> } if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return CSR_ILP32F_LP64F_VEC_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) return CSR_ILP32F_LP64F_RegMask ; switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return


<s> AsmPrinter :: emitFunctionEntryLabel ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer


<s> } MVT VT = N . getSimpleValueType ( ) ; if ( CurDAG -> ComputeNumSignBits ( N ) > ( VT . getSizeInBits ( ) - <NUM_LIT> ) ) { Val = N ; return true ; } return


<s> rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg , mem , insn ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; int offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - <NUM_LIT> ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { if ( regno == RETURN_ADDR_REGNUM ) offset = saved_size - UNITS_PER_WORD ; else if ( regno == S0_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else if ( regno == S1_REGNUM ) offset = saved_size - UNITS_PER_WORD * <NUM_LIT> ; else offset = saved_size - ( ( regno - S2_REGNUM + <NUM_LIT> ) * UNITS_PER_WORD ) ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode ,


<s> Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ; Op -> StartLoc = S


<s> if ( TARGET_SAVE_RESTORE ) return riscv_leaf_function_p (


<s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind ,


<s> Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; Register BPReg = <STR_LIT> ( ) ; DebugLoc DL ; emitSCSPrologue ( MF , MBB , MBBI , DL ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; determineFrameLayout ( MF ) ; if ( int LibCallRegs = getLibCallID ( MF , MFI . getCalleeSavedInfo ( ) ) + <NUM_LIT> ) { unsigned LibCallFrameSize = alignTo ( ( STI . getXLen ( ) / <NUM_LIT> ) * LibCallRegs , <NUM_LIT> ) ; RVFI -> setLibCallStackSize ( LibCallFrameSize ) ; } uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; if ( RealStackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; if ( STI . isRegisterReservedByUser ( SPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { StackSize = FirstSPAdjustAmount ; RealStackSize = FirstSPAdjustAmount ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , RealStackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , getNonLibcallCSI ( CSI ) . size ( ) ) ; for ( const auto & Entry : CSI ) { int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) ,


<s> bool supportsScalableVectors ( ) const { return ST -> hasStdExtV (


<s> SDValue Result ; if ( CP -> isMachineConstantPoolEntry ( ) ) Result = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) ) ; Reloc :: Model RM = DAG . getTarget ( ) .


<s> static unsigned get_sew ( machine_mode mode ) { unsigned int sew = GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? <NUM_LIT> : GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; return sew


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x )

+ GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef


<s> RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL (


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo &


<s> case Immediate : OS << * getImm ( ) ; break ; case Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case SystemRegister


<s> static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) ) ) { if ( startswith ( s -> named . name , <STR_LIT> ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ; sprintf ( name , <STR_LIT> , s -> named . name +


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; if ( hasFP ( MF ) ) adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize


<s> if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( NumOperands - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp


<s> } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown ) { errs ( ) << <STR_LIT> ; TargetABI = ABI_Unknown ; } if ( TargetABI != ABI_Unknown ) return TargetABI ; if ( IsRV32E ) return ABI_ILP32E ; if ( IsRV64 )


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler


<s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) )


<s> const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine & > (


<s> int max = <NUM_LIT> ; if ( ! IN_RANGE ( riscv_preferred_stack_boundary_arg , min , max ) ) error ( <STR_LIT> , riscv_preferred_stack_boundary_arg , min , max ) ; riscv_stack_boundary = <NUM_LIT> << riscv_preferred_stack_boundary_arg ; } if ( riscv_emit_attribute_p < <NUM_LIT> ) riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE ; riscv_emit_attribute_p = <NUM_LIT> ; if ( riscv_emit_attribute_p ) error ( <STR_LIT> <STR_LIT> ) ; if ( riscv_stack_protector_guard == SSP_GLOBAL && OPTION_SET_P ( riscv_stack_protector_guard_offset_str ) ) { error ( <STR_LIT> <STR_LIT> , riscv_stack_protector_guard_offset_str ) ; } if ( riscv_stack_protector_guard == SSP_TLS && ! ( OPTION_SET_P ( riscv_stack_protector_guard_offset_str ) && OPTION_SET_P ( riscv_stack_protector_guard_reg_str ) ) ) { error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; } if ( OPTION_SET_P ( riscv_stack_protector_guard_reg_str ) ) { const char * str = riscv_stack_protector_guard_reg_str ; int reg = decode_reg_name ( str ) ; if ( ! IN_RANGE ( reg , GP_REG_FIRST + <NUM_LIT> , GP_REG_LAST ) ) error (


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer


<s> case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : PI = <NUM_LIT> << <NUM_LIT> ; PO = <NUM_LIT> << <NUM_LIT> ; PR = <NUM_LIT> << <NUM_LIT> ; PW = <NUM_LIT> << <NUM_LIT> ; } switch ( Op . getConstantOperandVal ( <NUM_LIT> ) ) { case SingleThread : case CrossThread : SI = <NUM_LIT> << <NUM_LIT> ; SO = <NUM_LIT> << <NUM_LIT> ; SR = <NUM_LIT> <<


<s> function_table = new hash_table < registered_function_hasher > ( <NUM_LIT> ) ; function_builder builder ; for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( function_groups ) ; ++ i ) builder . register_function_group


<s> MCSection * <ISA_LIT>ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind

Kind , const Constant * C , Align & Alignment ) const {


<s> return <ISA_LIT>MaxBuildIntsCost == <NUM_LIT> ? getSchedModel ( ) . LoadLatency + <NUM_LIT> : std :: max

< unsigned > ( <NUM_LIT> , <ISA_LIT>MaxBuildIntsCost ) ;


<s> SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( IsVWMULSU || Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info ->


<s> static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable ( ) ; } void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! TARGET_HARD_FLOAT ) return ; tree frflags = GET_BUILTIN_DECL


<s> expand_insn ( icode , m_opno , m_ops ) ; } else expand_insn ( icode , m_opno , m_ops


<s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; } RVFI -> setCalleeSavedStackSize ( Size )


<s> if ( ( from == FP_REGS && to == GR_REGS ) || ( from == GR_REGS

&& to == FP_REGS ) ) return tune_param -> fmv_cost ;


<s> rtx riscv_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != <NUM_LIT>


<s> LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR16s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR32s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s ) ; else if ( ValVT . isScalableVector ( ) ) { const TargetRegisterClass * RC = TLI . getRegClassFor ( ValVT ) ; if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) { Reg = State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( ArgVRs ) ; } } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM2s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM4s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State .


<s> if ( DL . isFatPointer ( PointerTy ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) && ( isa < AtomicRMWInst > ( AI ) || isa < AtomicCmpXchgInst > ( AI ) ) ) return false ; return TargetLowering :: supportsAtomicOperation ( DL , AI , ValueTy , PointerTy


<s> Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableRVBC16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; Size =


<s> auto SysReg = <STR_LIT> ( Imm ) ; if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) O << SysReg -> Name ; else O


<s> llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> )


<s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros (


<s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU ,


<s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; MVT EltVT = N . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; if ( ! ValidateImm ( SplatImm ) )


<s> auto_vec < tree , <NUM_LIT> > argument_types ; function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos .

types [ vec_type_idx ] , group . preds [ pred_idx ] , & group . ops_infos ) ;


<s> unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear ( )


<s> getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( Name . consume_front ( <STR_LIT> ) ) { lmul = APInt ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( lmul != <NUM_LIT> && lmul != <NUM_LIT> && lmul != <NUM_LIT> && lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Operands . push_back ( <ISA_LIT>Operand :: createVTypeImm ( sew , lmul , ediv , S , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( Name . consume_front ( <STR_LIT> ) ) { ediv = APInt ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( ediv != <NUM_LIT> && ediv != <NUM_LIT> && ediv != <NUM_LIT> && ediv != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; return isLegalElementTypeForRVV ( DataType -> getScalarType ( )


<s> return riscv_emit_set ( dest , gen_rtx_fmt_ee ( code , GET_MODE ( dest ) , x


<s> assert ( ( IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> ) && <STR_LIT> ) ; bool VLMax = IntNo == <STR_LIT> || IntNo == <STR_LIT> ; unsigned Offset = IntNoOffset + ( VLMax ? <NUM_LIT> : <NUM_LIT> ) ; assert ( Node -> getNumOperands ( ) == Offset + <NUM_LIT> && <STR_LIT> ) ; unsigned SEW = <ISA_LIT>VType :: decodeVSEW ( Node -> getConstantOperandVal ( Offset ) & <NUM_LIT> ) ; <STR_LIT> VLMul = static_cast < <STR_LIT> > ( Node -> getConstantOperandVal ( Offset + <NUM_LIT> ) & <NUM_LIT> ) ; unsigned VTypeI = <ISA_LIT>VType :: encodeVTYPE ( VLMul , SEW , true , false ) ; SDValue VTypeIOp = CurDAG -> getTargetConstant ( VTypeI , DL , XLenVT ) ; SmallVector < EVT , <NUM_LIT> > VTs = { XLenVT } ; if ( HasChain ) VTs . push_back ( <STR_LIT> ) ; SDValue VLOperand ; unsigned Opcode = <STR_LIT> ; if ( VLMax ) { VLOperand = CurDAG -> getRegister ( <STR_LIT> ,


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ,


<s> default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS


<s> struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , mode , type ,


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm )


<s> int StartIdx = i - ( M % Size ) ; if ( StartIdx == <NUM_LIT> ) return - <NUM_LIT> ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : Size - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return - <NUM_LIT> ; int MaskSrc = M < Size ? <NUM_LIT> : <NUM_LIT> ; int & TargetSrc = StartIdx < <NUM_LIT> ? HiSrc : LoSrc ; if ( TargetSrc < <NUM_LIT> ) TargetSrc =


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT>


<s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> )

, VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ;


<s> bool isUImm20AUIPC ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) ,


<s> if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( (


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None

|| VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;


create<ISA_LIT>MergeBaseOffsetOptPass ( ) {


<s> bool isR5CY ( ) const { return IsR5CY


<s> rtx tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_ee ( GTU , Pmode , avl , const0_rtx ) ) ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MO . isReg ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) { printRegName ( O , <STR_LIT> ) ; return ; } } } if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg


<s> bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR16 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success


<s> bool isGuaranteedNotToTrap ( const MachineInstr


<s> unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT>


<s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 (


<s> bool <ISA_LIT>InsertVSETVLI :: needVSETVLIPHI ( const VSETVLIInfo & Require , const MachineBasicBlock & MBB ) { if ( DisableInsertVSETVLPHIOpt ) return true ; if ( ! Require . hasAVLReg ( ) ) return true ; Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp


<s> bool requiresRegisterScavenging ( const MachineFunction & MF


<s> bool requiresDiffExpressionRelocations ( ) const override { return STI . getFeatureBits ( ) [


<s> uint64_t getRVVStackSize ( ) const { return RVVStackSize


<s> EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( GlobalAddressSDNode * N = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , SDLoc ( Op ) , Ty , <NUM_LIT> , Flag ) ; if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT> , Flag ) ; if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( )

, Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ;


<s> SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; int64_t ImmValue = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SDValue DownOffset , UpOffset ; if ( ImmValue >= <NUM_LIT> ) { DownOffset = DAG . getConstant ( ImmValue , DL , XLenVT ) ; UpOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DownOffset ) ; } else { UpOffset = DAG . getConstant ( - ImmValue , DL , XLenVT ) ; DownOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , UpOffset ) ; } SDValue TrueMask = getAllOnesMask ( VecVT , VLMax , DL


<s> static SDValue combineGREVI_GORCI ( SDNode * N , SelectionDAG & DAG ) { unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) CombinedShAmt = ShAmt1 | ShAmt2 ; else CombinedShAmt =


<s> bool isCSRSystemRegister ( ) const { return isSystemRegister (


<s> <STR_LIT> Seq = <STR_LIT> ( Value , isRV64 ( ) ) ; MCRegister SrcReg = <STR_LIT> ; for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( )


<s> static RegImmPair getRegImmPairPreventingCompression ( const MachineInstr & MI ) { const unsigned Opcode = MI . getOpcode ( ) ; if ( isCompressibleLoad ( MI ) || isCompressibleStore ( MI ) ) { const MachineOperand & MOImm = MI . getOperand ( <NUM_LIT> ) ; if ( ! MOImm . isImm ( ) ) return RegImmPair ( <STR_LIT> , <NUM_LIT> ) ; int64_t Offset = MOImm . getImm ( ) ; int64_t NewBaseAdjust = getBaseAdjustForCompression ( Offset , Opcode ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Base ) ) { if ( ! compressibleSPOffset ( Offset , Opcode ) && NewBaseAdjust ) return RegImmPair ( Base , NewBaseAdjust ) ; } else { Register SrcDest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcDestCompressed = isCompressedReg ( SrcDest ) ; bool BaseCompressed = isCompressedReg ( Base ) ; if ( ( ! BaseCompressed || NewBaseAdjust ) && SrcDestCompressed ) return RegImmPair ( Base , NewBaseAdjust ) ; if ( isCompressibleStore ( MI ) )


<s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ; } case <STR_LIT> : { SDNode & Op = * N ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Fn . getFunction ( ) . getName ( ) << <STR_LIT> ) ; for ( MachineBasicBlock & MBB : Fn ) { for ( MachineInstr & Instr : MBB ) { if ( Instr . isCopy ( ) ) { const auto & CopyDest = Instr . getOperand ( <NUM_LIT> ) ; auto & CopySource = Instr . getOperand ( <NUM_LIT> ) ; const MachineInstr * MI = MRI . getVRegDef ( CopySource . getReg ( ) ) ; if ( ! MI ) { continue ; } if ( MI -> getOpcode ( ) == <STR_LIT> && ! isSameRegisterClass ( CopyDest . getReg ( ) , CopySource . getReg ( )


<s> unsigned Opc ; if ( VT == XLenVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , XLenVT , Src . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( FRM , DL , XLenVT ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> static inline VConstraintType getConstraint ( uint64_t TSFlags ) { return static_cast < VConstraintType > ( ( TSFlags & ConstraintMask ) >>


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ; return decodeUImmOperand < N > ( Inst ,


<s> extract_insn_cached ( rinsn ) ; int ma = get_attr_ma ( rinsn ) ; return ma == INVALID_ATTRIBUTE ? get_default_ma ( ) : IS_AGNOSTIC


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm

) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) || N -> getConstantOperandVal ( OffsetOpIdx ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CP -> getOffset ( ) , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( )


<s> StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success


<s> return ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT

== <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;


<s> return MachineFunctionProperties ( ) . set (

MachineFunctionProperties :: Property :: IsSSA ) ;


<s> if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT>


<s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } unsigned Reg = FPR64DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg


<s> bool isSImm5 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK =


<s> bool <ISA_LIT>TTIImpl :: shouldFavorPostInc


<s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return


<s> case Instruction :: Xor : case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) )


<s> static const MCPhysReg GPRList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( GPRList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> if ( can_create_pseudo_p ( ) && ! in_splitter ) return force_reg ( Pmode