<s> TmpInst . addOperand ( MCOperand :: createExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear


<s> for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; ++ i ) { ShuffleMask . push_back ( <NUM_LIT> * i


<s> if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true


<s> return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next ,


<s> static DecodeStatus DecodeLoadIntPair ( MCInst & Inst , unsigned insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder , true


<s> TailPaddingAmount <ISA_LIT>TargetLowering :: getTailPaddingForPreciseBounds ( uint64_t Size ) const { if ( ! Subtarget . isCheri ( ) )


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> bool isUnaryOperator ( InfixCalculatorTok Op ) const { return Op == IC_NEG || Op ==


<s> return __builtin_mve_vldrbq_z_uv4si ( ( __builtin_neon_qi * ) __base ,


<s> <ISA_LIT>TargetStreamer :: emitDirectiveCpRestore ( StoreInsts , Offset ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ; for ( const MCInst & Inst : StoreInsts ) getStreamer ( ) . EmitInstruction (


<s> Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> ) { RHSC /= Scale ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return


<s> unsigned EltNo ; if ( MI -> getOpcode ( ) == <STR_LIT> ) EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; else EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; EltNo = ( EltNo + NElts / <NUM_LIT> ) % NElts ; if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; else MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_XXPERMDI : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; bool IsKill1 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool IsKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( IsKill2 ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( IsKill1 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister (


<s> selectVSplatUimm1 ( SDValue N , SDValue & Imm ) const { return selectVSplatCommon ( N , Imm , false , <NUM_LIT>


<s> switch ( OpSize ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; } } ; return


<s> OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS )


<s> bool isGP32bit ( ) const { return ! IsGP64bit


<s> bool <ISA_LIT>LongBranch :: runOnMachineFunction ( MachineFunction & F ) { if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; bool IsPIC = ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; SmallVector < MBBInfo , <NUM_LIT> > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch ) { int64_t Offset = computeOffset ( I -> Br ) ; if ( ( I -> Br -> isConditionalBranch ( ) || IsPIC ) && isInt < <NUM_LIT> > ( Offset / <NUM_LIT> ) ) continue ; if ( I -> Br -> isUnconditionalBranch ( ) && ! IsPIC && isInt < <NUM_LIT> > ( Offset / <NUM_LIT> ) ) continue ; } expandToLongBranch ( * I ) ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( EverMadeChange ) MF -> RenumberBlocks


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( Op0 . getOpcode ( ) , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> && ( Subtarget . hasAVX2 ( ) || MayFoldLoad ( Op0 . getOperand ( <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && ( Subtarget . hasAVX2 ( ) || ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && MayFoldLoad ( Op0 . getOperand ( <NUM_LIT> ) ) ) ) && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT . getScalarType ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; } bool IsSplat = llvm :: all_of ( Ops , [ & Op0 ] ( SDValue Op ) { return Op == Op0 ; } ) ; if ( llvm :: all_of ( Ops , [ Op0 ] ( SDValue Op ) { return Op . getOpcode ( ) == Op0 . getOpcode ( ) ; } ) ) { unsigned NumOps = Ops . size ( ) ; switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! IsSplat && NumOps == <NUM_LIT> && VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) && Op0 . getOperand ( <NUM_LIT> ) == Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) { SmallVector < SDValue , <NUM_LIT> > Src ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) Src . push_back ( Ops [ i ] . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op0 . getOpcode ( ) , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Src ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! IsSplat && NumOps == <NUM_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX ( ) && Op0 . getOperand ( <NUM_LIT> ) == Ops [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) { SmallVector < SDValue , <NUM_LIT> > Src ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) Src . push_back ( DAG

. getBitcast ( <STR_LIT> , Ops [ i ] . getOperand ( <NUM_LIT> ) ) ) ;


<s> rtx ra = gen_rtx_REG ( Pmode , LP_REGNO ) ; emit_move_insn ( ra , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] =


<s> EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) Feat00Flags


<s> assert ( <NUM_LIT> < MaxStages && MaxStages <= <NUM_LIT> && ( BitSize << MaxStages ) <= <NUM_LIT> && <STR_LIT> ) ; auto MatchPACK = [ & ] ( SDValue N1 , SDValue N2 , MVT PackVT ) { unsigned NumSrcBits = PackVT . getScalarSizeInBits ( ) ; unsigned NumPackedBits = NumSrcBits - BitSize ; N1 = peekThroughBitcasts ( N1 ) ; N2 = peekThroughBitcasts ( N2 ) ; unsigned NumBits1 = N1 . getScalarValueSizeInBits ( ) ; unsigned NumBits2 = N2 . getScalarValueSizeInBits ( ) ; bool IsZero1 = llvm :: isNullOrNullSplat ( N1 , false ) ; bool IsZero2 = llvm :: isNullOrNullSplat ( N2 , false ) ; if ( ( ! N1 . isUndef ( ) && ! IsZero1 && NumBits1 != NumSrcBits ) || ( ! N2 . isUndef ( ) && ! IsZero2 && NumBits2 != NumSrcBits ) ) return false ; if ( Subtarget . hasSSE41 ( ) || BitSize == <NUM_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( NumSrcBits , NumPackedBits ) ; if ( ( N1 . isUndef ( ) || IsZero1 || DAG . MaskedValueIsZero ( N1 , ZeroMask ) ) && ( N2 . isUndef ( ) || IsZero2 || DAG . MaskedValueIsZero ( N2 , ZeroMask ) ) ) { V1 = N1 ; V2 = N2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } bool IsAllOnes1 = llvm :: isAllOnesOrAllOnesSplat ( N1 , false ) ; bool IsAllOnes2 = llvm :: isAllOnesOrAllOnesSplat ( N2 , false ) ; if ( ( N1 . isUndef ( ) || IsZero1 || IsAllOnes1 || DAG . ComputeNumSignBits ( N1 ) > NumPackedBits ) && ( N2 . isUndef ( ) || IsZero2 || IsAllOnes2 || DAG . ComputeNumSignBits ( N2 ) > NumPackedBits ) ) { V1 = N1 ; V2 = N2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } return false ; } ; for ( unsigned NumStages = <NUM_LIT> ; NumStages <= MaxStages ; ++ NumStages ) { MVT PackSVT = <STR_LIT> ( BitSize << NumStages ) ; MVT PackVT = <STR_LIT> ( PackSVT , NumElts >> NumStages ) ; SmallVector < int , <NUM_LIT> > BinaryMask ; createPackShuffleMask ( VT , BinaryMask , false , NumStages


<s> llvm :: Triple :: ArchType arch = pConfig . targets ( ) . triple ( ) . getArch ( ) ; assert ( arch == llvm :: Triple :: mipsel || arch == llvm :: Triple :: mips64el ) ; unsigned bitclass = arch == llvm :: Triple :: mipsel ? <NUM_LIT> : <NUM_LIT> ; pConfig . targets ( ) . setBitClass ( bitclass ) ; pConfig . attribute ( ) . constraint ( ) . enableWholeArchive ( ) ; pConfig . attribute ( ) . constraint ( ) .


<s> if ( MCOp . isReg ( ) ) return get<ISA_LIT>RegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) return static_cast < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < <ISA_LIT>MCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return


<s> assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin ,


<s> bool oclBiCall = false ; bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv (


<s> Encoding = ( get<ISA_LIT>RegisterNumbering ( Op1 . getReg ( ) ) << <NUM_LIT> ) ; assert ( Op2 . isReg ( ) && <STR_LIT> ) ; Encoding |= ( get<ISA_LIT>RegisterNumbering ( Op2 . getReg ( ) ) << <NUM_LIT> ) ; assert ( AluMCOp . isImm ( ) && <STR_LIT> ) ; unsigned AluOp = AluMCOp . getImm ( ) ; Encoding |= LPAC :: encode<ISA_LIT>AluCode ( AluOp ) << <NUM_LIT> ; if ( LPAC :: isPreOp ( AluOp ) ) Encoding |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( LPAC :: isPostOp ( AluOp ) ) Encoding |= ( <NUM_LIT>


<s> BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else return true ; Cond [ <NUM_LIT> ] . setImm ( BranchCode ) ; } return false


<s> if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return PR_REGNUM_P ( regno ) ; if ( PR_REGNUM_P ( regno ) ) return <NUM_LIT> ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return true ; if ( FP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_STRUCT ) return end_hard_regno ( mode , regno ) - <NUM_LIT> <= V31_REGNUM ; else return ! VECTOR_MODE_P ( mode ) || vec_flags != <NUM_LIT> ; } return


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { uint32_t Binary = getBinaryCodeForInstr (


<s> CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetELF ( ) ) OpFlag = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubNoDynamic (


<s> TargetTransformInfo :: getAnalysisUsage ( AU


<s> while ( ShadowBytes < NumNOPBytes ) { if ( MII == MBB . end ( ) || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ShadowBytes += TII -> getInstSizeInBytes ( * MII ) ; if ( MII -> isCall ( ) ) break ; ++ MII ; } while ( ShadowBytes < NumNOPBytes ) ShadowBytes += EmitNop ( OutContext , * OutStreamer , NumNOPBytes - ShadowBytes


<s> if ( ! Subtarget . hasInt256 ( ) || VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( VT . is512BitVector ( ) || Subtarget . hasVLX ( ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT .


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) { fixTCReturn ( MF , MBB ) ; return ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( ! MFI -> getPristineRegs ( MF ) . test ( <STR_LIT> )


<s> AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( Subtarget -> hasSSE2 ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: shouldFoldShiftPairToMask ( const SDNode * N , CombineLevel Level


<s> void <ISA_LIT>AsmPrinter :: printAddrMode2Operand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg


<s> static void transferMIFlag ( MachineInstr * OldMI , MachineInstr * NewMI


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; return ! RegInfo -> needsStackRealignment ( *


<s> for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; if ( RepeatedMask [ i % LaneSize ] == - <NUM_LIT> ) RepeatedMask [ i % LaneSize ] = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + Size ; else if ( RepeatedMask [ i % LaneSize ] + ( i / LaneSize ) * LaneSize != Mask [ i ] ) return false ; } return true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> if ( REGNO ( reg1 ) % <NUM_LIT> != <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_V9 && REGNO ( reg1 ) < <NUM_LIT> ) return <NUM_LIT> ; return ( REGNO ( reg1 ) == REGNO ( reg2


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , false ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , CPAddr ) ; } else { unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; } ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG .


<s> SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || Subtarget . isABI_N64 ( ) ) { Addr = DAG . getNode ( <STR_LIT> , DL , PTy ,

Addr , getPICJumpTableRelocBase ( Table , DAG ) ) ;


<s> return new <ISA_LIT>DagToDagISel ( tm , optLevel


<s> rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ) , gen_rx_store_vector ( low , high


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ||


<s> int DstLane ; std :: tie ( DstIsLeft , DstLane ) = * DstIsLeftAndDstLane ; Register Left = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Right = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstVec = DstIsLeft ? Left : Right ; Register SrcVec = Left ; int SrcLane = ShuffleMask [ DstLane ] ; if ( SrcLane >= NumElts ) { SrcVec = Right ; SrcLane -= NumElts ; } MatchInfo = std :: make_tuple ( DstVec , DstLane , SrcVec ,


<s> return ( __mmask16 ) __builtin_ia32_ptestmw256 ( ( __v16hi )


<s> TFL = STI -> getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI -> getRegisterInfo ( ) ) ; SlotSize = RegInfo . getSlotSize ( ) ; assert ( isPowerOf2_32 ( SlotSize ) && <STR_LIT> ) ; Log2SlotSize = Log2_32 ( SlotSize ) ; if ( skipFunction ( MF . getFunction ( ) ) || ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { Triple TheTriple ( TT


<s> static DecodeStatus decodeBDAddr12Operand ( MCInst & Inst , uint64_t Field , const unsigned * Regs ) { uint64_t Base = Field >> <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs


<s> const uint64_t Mask = <NUM_LIT> ; if ( Clear ) Imm &= ~ ( Mask << ( Idx * <NUM_LIT> ) ) ; else Imm |= Mask << ( Idx * <NUM_LIT> ) ; return Imm


<s> for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( RepeatedMask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( RepeatedMask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } } } if ( AllowIntDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { int ShiftAmt = matchShuffleAsShift ( ShuffleVT , Shuffle , MaskScalarSizeInBits , Mask


<s> return Value == <NUM_LIT> || isNEONBytesplat ( Value ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCFINegateRAState ( ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> )


<s> if ( getParser ( ) . ParseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond ) const { DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++


<s> static DecodeStatus decodeS16ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeSImmOperand < <NUM_LIT> > ( Inst , Imm


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( create<ISA_LIT>PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>AddressTypePromotionPass ( ) ) ; addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; return false


<s> unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( Target ) . addReg ( <STR_LIT>

, RegState :: ImplicitDefine | RegState :: Dead ) ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & >


<s> if ( Val & ( <NUM_LIT> << <NUM_LIT> )


<s> } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , <NUM_LIT> , TTI :: TCK_RecipThroughput ) ; } } unsigned const Max = ( NumStores ? ( <NUM_LIT> / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount


<s> if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = true_label ; LABEL_NUSES ( true_label )


<s> if ( isTargetShuffleEquivalent ( VT , TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } createUnpackShuffleMask ( VT , Unpckh , false , IsUnary ) ; if ( isTargetShuffleEquivalent ( VT , TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } if ( IsUnary && ( Zero1 || Zero2 ) ) { if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL


<s> bool <ISA_LIT>BaseInstrInfo :: ConvertToSetZeroFlag ( MachineInstr * MI , MachineInstr * CmpInstr ) const { if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr =


<s> static SetOfMachineInstr & getSet ( BlockToSetOfInstrsPerColor & sets , const MachineBasicBlock & MBB , unsigned reg , unsigned nbRegs ) { SetOfMachineInstr * result ; BlockToSetOfInstrsPerColor :: iterator it = sets . find ( & MBB


<s> bool supportPtrAuthBundles ( ) const


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode


<s> return gimple_build_assign ( lhs , build_zero_cst ( TREE_TYPE ( lhs ) )


<s> return ( __m128d ) __builtin_ia32_maxsd ( ( __v2df


<s> SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; <STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ; assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , DL , <STR_LIT> )


<s> } LLVMContext & Ctx = M . getContext ( ) ; auto Ty = F -> getFunctionType ( ) ; Function * Fn = Function :: Create ( Ty , GlobalValue :: WeakAnyLinkage , N , & M ) ; Fn -> setDoesNotReturn ( ) ; Fn -> setVisibility ( GlobalValue :: DefaultVisibility ) ; Fn -> setCallingConv ( CallingConv :: C ) ; Fn -> setSection ( <STR_LIT> ) ; Fn -> setIsMaterializable ( true ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; Fn -> addAttributes ( llvm :: AttributeList ::


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , CPAddr ) ; } else { unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; } ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; if ( MBBI -> isTerminator ( ) ) return ; int UnwindHelpFI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; DebugLoc DL ; RS -> enterBasicBlock ( MBB


<s> bool SelectAddrImmX34 ( SDValue N , SDValue & Disp , SDValue & Base


<s> rtx sfunc_uses_reg ( rtx_insn * insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( ! NONJUMP_INSN_P ( insn ) ) return NULL_RTX ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , <NUM_LIT> ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , <NUM_LIT> ) ; for ( int i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && REG_P ( SET_DEST ( part ) ) ) ? SET_SRC ( part ) : part ) ) ) return NULL_RTX ; } return


<s> if ( len != <NUM_LIT> && len != <NUM_LIT> && len != <NUM_LIT> && len != <NUM_LIT> ) return <NUM_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < len / <NUM_LIT> ; ++ i ) { rtx op = XVECEXP ( parallel , <NUM_LIT> , i ) ; if ( ! CONST_INT_P ( op ) || INTVAL ( op ) != len / <NUM_LIT> + i ) return <NUM_LIT> ; } for ( unsigned int i = len / <NUM_LIT> ; i < len ; ++ i ) { rtx op = XVECEXP ( parallel


<s> void <ISA_LIT>Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { if ( needsAggressiveScheduling (


<s> for ( auto & Val : SupportedValues ) { if ( Val . ValTy != Query . Types [ <NUM_LIT> ] ) continue ; if ( Val . PtrTy != Query . Types [ <NUM_LIT> ] ) continue ; if ( Val . MemSize != QueryMemSize )


<s> set_optab_libfunc ( le_optab , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , <STR_LIT> ) ; if ( TARGET_DOUBLE_FLOAT ) { set_optab_libfunc ( add_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab ,


<s> } assert ( ( Opcodes . size ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != Opcodes . size ( ) ; I += <NUM_LIT> ) { uint64_t Intval = Opcodes [ I ] | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> | Opcodes [


<s> ModulePass * llvm :: create<ISA_LIT>PromoteConstantPass (


<s> return ( TARGET_EXPLICIT_RELOCS && mips_symbolic_constant_p ( x , & symbol_type ) &&


<s> static int mips_symbol_insns ( enum mips_symbol_type type , machine_mode mode ) { return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ?


<s> Streamer . visitUsedExpr ( * getSubExpr


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { CPU = <STR_LIT> (


<s> } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS (


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( isa < ConstantInt > ( * RV ) ) { const Constant * C = cast < Constant > ( RV ) ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( C , <STR_LIT> , VA . getLocInfo ( ) == CCValAssign :: SExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; return isSEHInstruction (


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> hasPreallocatedCall ( ) ) return true ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; bool CantUseFP = needsStackRealignment ( MF ) ; return CantUseFP && CantUseSP


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins


<s> int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( MPO . getAddrSpace ( )

, <NUM_LIT> ) , FI ) . getReg ( <NUM_LIT> ) ;


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return <STR_LIT> ; if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O ) ; O << <STR_LIT>


<s> assert ( ! VT . isVector ( ) ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( SrcVT ) ; if ( ! IsSigned && UseSSEReg ) { if ( Subtarget . hasAVX512 ( ) ) return Op ; if ( VT == <STR_LIT> ) return SDValue ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } if ( ! Subtarget . hasSSE3 ( ) ) return SDValue ( ) ; } if ( VT == <STR_LIT> && ( UseSSEReg || SrcVT == <STR_LIT> ) ) { assert ( IsSigned && <STR_LIT> ) ; SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } if ( UseSSEReg && IsSigned ) return Op ; if ( SrcVT == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( IsSigned ) LC = RTLIB :: getFPTOSINT ( SrcVT , VT ) ; else LC = RTLIB :: getFPTOUINT ( SrcVT , VT ) ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; MakeLibCallOptions CallOptions ; std :: pair < SDValue , SDValue > Tmp = makeLibCall ( DAG , LC , VT , Src , CallOptions , SDLoc ( Op ) , Chain ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp


<s> gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp


<s> bool YMMUsed = false ; const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs (


<s> void <ISA_LIT>AsmParser :: cvtT2LdrdPre ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )


<s> MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType ( ) . getSizeInBits ( ) ) ; SDValue VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , SVT . getStoreSize ( ) , SVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getMaskedStore ( Chain , dl , DataToTruncate , Addr , VMask


<s> if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> || ( ( IntWidth == <NUM_LIT> || IntWidth


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; APInt BitImm = APInt ( ResTy . getScalarSizeInBits ( ) , <NUM_LIT> ) << cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; SDValue BitMask = DAG . getConstant ( ~ BitImm ,


<s> const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( XII -> getGlobalBaseReg ( MF ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB , Subtarget -> ClassifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } } else PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( MemOpndSlot + i )


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ,


<s> break ; case 'Y' : return const_zero_operand ( op , GET_MODE ( op ) ) ; default : return <NUM_LIT> ; } if ( GET_CODE ( op ) == MEM ) { reload_ok_mem = <NUM_LIT> ; if ( ( TARGET_ARCH64 || mem_min_alignment ( op , <NUM_LIT> ) ) && ( ! strict || strict_memory_address_p ( Pmode , XEXP ( op , <NUM_LIT> ) ) ) ) reload_ok_mem = <NUM_LIT> ; } else { reload_ok_mem = ( reload_in_progress && GET_CODE ( op ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER &&

reg_renumber [ REGNO ( op ) ] < <NUM_LIT> ) ;


<s> SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , SrcVal ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( SrcVal . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getValueType ( ) != <STR_LIT> ) return Op ; return SDValue ( )


<s> SDValue V2 = IsUnary ? V1 : N . getOperand ( <NUM_LIT> ) ; while ( V1 . getOpcode ( ) == <STR_LIT> ) V1 = V1 -> getOperand ( <NUM_LIT> ) ; while ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V2 -> getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i != Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue V = M < Size ? V1 : V2 ; if ( V . isUndef ( ) ) { Mask [ i ] = SM_SentinelUndef ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> || Size != ( int ) V . getNumOperands ( ) ) continue ; if ( ! <STR_LIT> ( V . getOperand ( M % Size ) ) ) continue ; Mask [ i ] = SM_SentinelZero ; } return


<s> auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame


<s> x . i [ <NUM_LIT> ] = count << <NUM_LIT> ; mask = ( count & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> )


<s> MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) )


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumedToken ) ) ; if ( std :: unique_ptr < <ISA_LIT>Operand > Op = ParseOperand ( ) ) { Operands . push_back ( std :: move ( Op ) ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || getLexer ( ) . getTok ( ) .

getIdentifier ( ) != <STR_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent (


<s> const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) )

) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ;


<s> getAddrMode6DupAddressOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & Reg = MI . getOperand ( Op ) ; const MCOperand & Imm = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ;


<s> SDValue TPOff ; EVT PtrVT = getPointerTy ( ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue ThreadBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue HiDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc ) ; DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DescAddr , LoDesc ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DTPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; DTPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , DTPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff , DTPOff ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue HiDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> ,


<s> void <ISA_LIT>AsmPrinter :: EmitTlsCall ( const MachineInstr * MI , MCSymbolRefExpr :: VariantKind VK ) { StringRef Name = <STR_LIT> ; MCSymbol * TlsGetAddr = OutContext . getOrCreateSymbol ( Name ) ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( ! Subtarget -> is<ISA_LIT>64 ( ) && ! Subtarget -> isDarwin ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCSymbolRefExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; const MachineOperand & MO = MI


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl


<s> const MCExpr * <ISA_LIT>AsmParser :: evaluateRelocExpr ( const MCExpr * Expr , StringRef RelocStr ) { <ISA_LIT>MCExpr :: VariantKind Kind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( RelocStr ) . Default

( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ;


<s> DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; KnownZero &= KnownZero2 ; KnownOne &= KnownOne2 ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT


<s> if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return


<s> unsigned <STR_LIT> ( unsigned Opcode , Type * Ty , OperandValueKind Op1Info , OperandValueKind Op2Info ) const { int ISDOpcode = TLI -> InstructionOpcodeToISD ( Opcode ) ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry < MVT > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx = - <NUM_LIT> ; if ( ST -> hasNEON ( ) ) Idx = CostTableLookup < MVT > ( CostTbl , array_lengthof ( CostTbl ) , ISDOpcode , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * CostTbl [ Idx ] . Cost ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty ,


<s> if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ]


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> unsigned Bytes = ( unsigned ) NumBytes ; if ( isSub ) Bytes = - NumBytes ; bool isMul4 = ( Bytes & <NUM_LIT> ) == <NUM_LIT> ; bool isTwoAddr = false ; bool DstNotEqBase = false ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int Opc = <NUM_LIT> ; int ExtraOpc = <NUM_LIT> ; bool NeedCC = false ; if ( DestReg == BaseReg && BaseReg == <STR_LIT> ) { assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; isTwoAddr = true ; } else if ( ! isSub && BaseReg == <STR_LIT> ) { if ( ! isMul4 ) { Bytes &= ~ <NUM_LIT> ; ExtraOpc = <STR_LIT> ; } DstNotEqBase = true ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = <STR_LIT> ; } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; if ( DestReg == <STR_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if (


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_HA : Type = ELF :: R_<ISA_LIT>64_TOC16_HA ; break ; case MCSymbolRefExpr :: VK_TPREL : Type = ELF :: R_<ISA_LIT>_TPREL16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : Type = ELF :: R_<ISA_LIT>_TPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : Type = ELF :: R_<ISA_LIT>_TPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA : Type = ELF :: R_<ISA_LIT>_TPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGH : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGH ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHA : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHER : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHERA : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHEST : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HIGHESTA : Type = ELF :: R_<ISA_LIT>64_TPREL16_HIGHESTA ; break ; case MCSymbolRefExpr :: VK_DTPREL : Type = ELF :: R_<ISA_LIT>64_DTPREL16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : Type = ELF :: R_<ISA_LIT>64_DTPREL16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGH : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGH ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHER : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHERA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHEST : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HIGHESTA : Type = ELF :: R_<ISA_LIT>64_DTPREL16_HIGHESTA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD : if ( is64Bit ( ) ) Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16 ; else Type = ELF :: R_<ISA_LIT>_GOT_TLSGD16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSGD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD : if ( is64Bit ( ) ) Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16 ; else Type = ELF :: R_<ISA_LIT>_GOT_TLSLD16 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_HA : Type = ELF :: R_<ISA_LIT>64_GOT_TLSLD16_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_LO : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_LO_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_HI : Type = ELF :: R_<ISA_LIT>64_GOT_TPREL16_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_DS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DTPREL_LO : Type = ELF :: R_<ISA_LIT>64_GOT_DTPREL16_LO_DS ; break ; case MCSymbolRefExpr ::


<s> return ( __m128i ) __builtin_ia32_vcvtph2dq128_mask ( __A , ( __v4si ) _mm_setzero_si128 ( ) , (


<s> rtx set = XVECEXP ( real , <NUM_LIT> , i ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return insn ; } if ( reg == reg2 ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; if ( reg == rreg ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; real = copy_rtx ( PATTERN ( insn ) ) ; if ( reg2 != NULL_RTX ) real = replace_rtx ( real , reg2 , rreg ) ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) gcc_checking_assert ( val == <NUM_LIT> ) ; else real = replace_rtx ( real , reg , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ) ; if ( GET_CODE ( real ) == SET ) { rtx set = real ; temp = simplify_rtx ( SET_SRC (


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isCPI ( ) ) return true ; if ( MO . isGlobal ( ) ) return isGlobalStubReference ( MO . getTargetFlags ( ) ) ; if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( )


<s> bool hasSoftFloat ( ) const { return HasSoftFloat


<s> MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , I . getFrameIdx ( ) ) ) ; } } else { if ( I . isSpilledToReg ( ) ) { unsigned Dst = I . getDstReg ( ) ; if ( Spilled [ Dst ] ) continue ; if ( VSRContainingGPRs [ Dst ] . second != <NUM_LIT> ) { assert ( Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; NumPESpillVSR += <NUM_LIT> ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( VSRContainingGPRs [ Dst ] . first , getKillRegState ( true ) ) . addReg ( VSRContainingGPRs [ Dst ] . second , getKillRegState ( true ) ) ; } else if ( VSRContainingGPRs [ Dst ] . second == <NUM_LIT> ) { assert ( Subtarget . hasP8Vector ( ) && <STR_LIT> ) ; ++ NumPESpillVSR ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , TRI -> getSubReg ( Dst , <STR_LIT> )

) . addReg ( VSRContainingGPRs [ Dst ] . first , getKillRegState ( true ) ) ;


<s> if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) , Op ) ; return


<s> return ( uint32x2_t ) __builtin_aarch64_lrounduv2sfv2si (


<s> O << <STR_LIT> << MI -> getOperand ( OpNum ) .


<s> SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsWinCFI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) { static const char CFIInst [ ] = { dwarf :: DW_CFA_val_expression , <NUM_LIT> , <NUM_LIT> , static_cast < char > ( unsigned ( dwarf :: DW_OP_breg18 ) ) , static_cast < char > ( - <NUM_LIT> ) & <NUM_LIT> , } ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createEscape ( nullptr , StringRef ( CFIInst , sizeof ( CFIInst ) ) ) ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size ; Align Alignment ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo :: FPR64 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Alignment = Align ( <NUM_LIT> ) ; break ; case RegPairInfo ::


<s> bool IsTailPredicationLegal ( ) const { return ! Revert && FoundAllComponents ( ) && ! VCTPs . empty ( ) && ! CannotTailPredicate && ML . getNumBlocks


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( ! setTargetShuffleZeroElements ( Op , Mask , Ops ) ) if ( ! getFauxShuffleMask ( Op , Mask , Ops ) ) return false ; int NumElts = Mask . size ( ) ; bool Op0InUse = any_of ( Mask , [ NumElts ] ( int Idx ) { return <NUM_LIT> <= Idx &&


<s> AddrOp ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI -> getIndex ( ) ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ; if ( AddrOp . getOpcode ( ) != <STR_LIT> ) return true ; } if ( AddrOp . getOpcode ( ) == <STR_LIT> ) return isIntS16Immediate ( AddrOp . getOperand ( <NUM_LIT> ) , Imm ) && ! ( Imm % Val ) ; return AddrOp . getOpcode ( ) ==


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; if ( ! MI . hasOneMemOperand ( ) ) return false ; const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; if ( MMO . isVolatile ( ) || MMO . isAtomic ( ) ) return false ; if ( MMO . getAlign ( ) < Align ( <NUM_LIT>


<s> return __builtin_mve_vcmpcsq_n_v4si ( __a ,


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) new_pat = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( COND_EXEC_TEST ( pat ) ) , new_pat ) ; return new_pat


<s> PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; AllowNameToStartWithDigit =


<s> static SDValue combineShuffleToAddSubOrFMAddSub ( SDNode * N , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue Opnd0 , Opnd1 ; if ( ! isAddSubOrSubAdd ( N , Subtarget , Opnd0 , Opnd1 ) ) return SDValue ( ) ; EVT VT = N -> getValueType


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE2 ( ) || Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg


<s> SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Imm = Node -> getOperand ( <NUM_LIT> ) ; const ConstantInt * Val = cast < ConstantSDNode > ( Imm ) -> getConstantIntValue ( ) ; Imm = CurDAG -> getTargetConstant ( * Val , SDLoc ( Node ) , Imm . getValueType ( ) ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( MayFoldLoad && tryFoldLoad ( Node , N1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , N1 . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs


<s> unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned Lo = RegInfo . getSubReg ( Src , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Src , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , VR0


<s> void <ISA_LIT>AsmPrinter :: EmitJump2Table ( const MachineInstr * MI ) { unsigned Opcode = MI -> getOpcode ( ) ; int OpNum = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT8 ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT16 ) ; } for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( OffsetWidth == <NUM_LIT> ) { OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MBBSymbolExpr ) . addImm ( <STR_LIT>


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ; return true


<s> break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return


<s> return type_suffixes [ type_suffix_ids [ i ]


<s> static unsigned calcLiveInMask ( MachineBasicBlock * MBB ) { unsigned Mask = <NUM_LIT> ; for ( const auto & LI : MBB -> liveins ( ) ) { if ( LI . PhysReg < <STR_LIT> || LI . PhysReg > <STR_LIT> ) continue ; Mask |= <NUM_LIT> << ( LI . PhysReg - <STR_LIT> ) ; } return Mask


<s> OS << <STR_LIT> ; StartInst -> print ( OS , true ) ; OS << <STR_LIT> ; LastInst -> print ( OS , true ) ; if ( KillInst ) { OS << <STR_LIT> ; KillInst -> print ( OS , true ) ; OS << <STR_LIT> ; } OS <<


<s> int <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , Type * ValTy , bool IsPairwiseForm ) { if ( IsPairwiseForm ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry CostTblNoPairwise [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( CostTblNoPairwise , ISD , MTy ) ) return


<s> static int mips_fpr_return_fields ( tree valtype , tree * fields ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return <NUM_LIT> ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return <NUM_LIT> ; i = <NUM_LIT> ; for ( field = TYPE_FIELDS ( valtype ) ; field != <NUM_LIT> ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( <STR_LIT> ( Value ) != - <NUM_LIT> || <STR_LIT> (


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( ! <ISA_LIT>SubTarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout


<s> old_label = JUMP_LABEL ( insn ) ; target = gen_rtx_LABEL_REF ( Pmode , old_label ) ; mips16_load_branch_target ( temp , target ) ; jump = emit_jump_insn ( PMODE_INSN ( gen_indirect_jump_and_restore , ( temp , temp , saved_temp ) ) ) ; JUMP_LABEL ( jump ) = old_label ; LABEL_NUSES ( old_label ) ++ ; mips16_lay_out_constants ( false ) ; if ( simplejump_p ( insn ) ) new_label = NULL ; else { new_label = gen_label_rtx ( ) ; emit_label ( new_label )


<s> Type * OffsType = VectorType :: getInteger ( cast < VectorType > ( Ty ) ) ; if ( OffsType != Offsets -> getType ( ) ) { if ( OffsType -> getScalarSizeInBits ( ) > Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Offsets = Builder . CreateZExt ( Offsets , OffsType , <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ; case Match_ConversionFail


<s> <STR_LIT> <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT>


<s> return ( int32x4_t ) __builtin_neon_vextv4si ( __a ,


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( isCyclone ( ) ) Policy


<s> return MatchOperand_NoMatch ; } unsigned SYSmvalue = Val & <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { auto TheReg = <STR_LIT> ( Mask . lower ( ) ) ; if ( ! TheReg || ! TheReg -> hasRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) return MatchOperand_NoMatch ; unsigned SYSmvalue = TheReg -> Encoding & <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next +


<s> bool <ISA_LIT>InterleavedAccessGroup :: isSupported ( ) const { VectorType * ShuffleVecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; uint64_t ShuffleVecSize = DL . getTypeSizeInBits ( ShuffleVecTy ) ; Type * ShuffleEltTy = ShuffleVecTy -> getVectorElementType ( ) ; uint64_t


<s> <ISA_LIT>RegSet CopyRegs ; for ( CalleeSavedInfo I : CSI ) { unsigned Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) { LoRegsToRestore [ Reg ] = true ; } else if ( <STR_LIT> . contains ( Reg ) && Reg != <STR_LIT> ) { HiRegsToRestore [ Reg ] = true ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( <STR_LIT> . contains ( Reg ) ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs [ Reg ] = true ; } auto Terminator = MBB . getFirstTerminator ( ) ; if ( Terminator != MBB . end ( ) && Terminator -> getOpcode ( ) == <STR_LIT> ) { CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; for ( auto Op : Terminator -> implicit_operands ( ) ) { if ( Op . isReg ( ) ) CopyRegs [ Op . getReg ( ) ] = false ; } } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; auto HiRegToRestore = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToRestore , AllHighRegsEnd ) ; while ( HiRegToRestore != AllHighRegsEnd ) { assert ( ! CopyRegs . none ( ) ) ; auto CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PopMIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; while ( HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { PopMIB . addReg ( * CopyReg , RegState :: Define ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( * HiRegToRestore , RegState :: Define ) . addReg ( * CopyReg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; CopyReg = findNextOrderedReg ( ++ CopyReg , CopyRegs , AllCopyRegsEnd ) ; HiRegToRestore = findNextOrderedReg ( ++ HiRegToRestore , HiRegsToRestore , AllHighRegsEnd ) ; } } MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; bool NeedsPop = false ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg


<s> case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned MSubOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; Register Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; Register Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register QuotReg = fastEmitInst_rr ( DivOpc , RC , Src0Reg , Src1Reg ) ; assert ( QuotReg && <STR_LIT> ) ; Register ResultReg = fastEmitInst_rrr ( MSubOpc , RC , QuotReg


<s> static bool r10k_simplified_address_p ( rtx x ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) x = XEXP ( x ,


<s> if ( mode == TImode ) emit_insn ( gen_aarch64_store_exclusive_pair ( bval , mem , operand_subword ( rval , <NUM_LIT> , <NUM_LIT> , TImode ) , operand_subword ( rval ,

<NUM_LIT> , <NUM_LIT> , TImode ) , model_rtx ) ) ;


<s> static __inline vec_double2 spu_slqwbytebc ( vec_double2 a , unsigned int count ) { return ( ( vec_double2 ) ( si_shlqbybi ( ( qword ) ( a ) , si_from_uint ( count


<s> SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , ShufMask1 ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , ShufMask2 ) ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT

. getVectorNumElements ( ) / <NUM_LIT> ) ;


<s> assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( Y , KnownZero , KnownOne ) ; if ( ( OrCI & KnownZero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> getAPIntValue ( ) . logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl ,


<s> getT2Imm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { int32_t Imm8 = MI . getOperand ( OpIdx ) . getImm


<s> if ( ! isa < ConstantSDNode > ( Lane ) ) return SDValue ( ) ; return Op


<s> void loongarch_output_external ( FILE * file , tree decl , const char * name ) { default_elf_asm_output_external ( file , decl , name ) ; if ( TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { if ( loongarch_in_small_data_p ( decl ) ) { fputs ( <STR_LIT> , file


<s> gcc_assert ( file == asm_out_file ) ; extern_symbol p = { decl ,


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; if ( ByteOffset ) O << MAI -> getData8bitsDirective ( ) ; else if ( HalfWordOffset ) O << MAI -> getData16bitsDirective ( ) ; if ( ByteOffset || HalfWordOffset ) O << '(' << * MBB -> getSymbol ( OutContext ) << <STR_LIT> << * JTISymbol << <STR_LIT> ; else O << <STR_LIT> << * MBB ->


<s> else { assert ( ! MFI -> getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( )


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( ShiftExtend . Amount % <NUM_LIT> != <NUM_LIT> || ShiftExtend .

Amount > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) { EnableTailMerge = ! get<ISA_LIT>Subtarget ( ) . enableLongBranchPass


<s> if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> )


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue (


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isA9 = STI -> isCortexA9 ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI


<s> bool A15SDOptimizer :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & STI = Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ( STI . isCortexA15 ( ) && STI . hasNEON ( ) ) ) return false ; TII = STI . getInstrInfo ( ) ; TRI = STI . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; bool Modified


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , ObjectCodeEmitter & OCE


<s> return new <ISA_LIT>SEFrameLowering (


<s> static const uint16_t * lookupAVX512 ( unsigned opcode , unsigned domain , ArrayRef < uint16_t [ <NUM_LIT> ] > Table ) { for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : Table ) if ( Row [ domain - <NUM_LIT>

] == opcode || ( domain == <NUM_LIT> && Row [ <NUM_LIT> ] == opcode ) ) return Row ;


<s> return Error ( IDLoc , <STR_LIT> ) ; } Inst . setOpcode ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; return false ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) return Error ( IDLoc , <STR_LIT> ) ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) return Error ( IDLoc , <STR_LIT> ) ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> || Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> ) return Error ( IDLoc , <STR_LIT> ) ; } Out . emitInstruction ( Inst , getSTI ( ) ) ; return false


<s> void i386_pe_end_function ( FILE * f ,


<s> if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO .


<s> bool <ISA_LIT>CodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { JTI = ( ( <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getInstrInfo ( ) ; TD = ( ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getTargetData ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin (


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperand (


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; if ( TII -> isRegLiveAtMI ( <STR_LIT> , MI , true ) || TII -> isRegLiveAtMI ( <STR_LIT> , MI , true ) || TII -> isRegLiveAtMI ( <STR_LIT> , MI , true ) || TII ->

isRegLiveAtMI ( <STR_LIT> , MI , true ) ) return true ;


<s> return parseAddress ( Operands , BDLMem


<s> b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmple ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A ,


<s> static machine_mode aarch64_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_SVE && aarch64_cmp_autovec_modes ( VNx16QImode , V16QImode ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; if ( TARGET_SIMD ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ; return


<s> int imm = Val & <NUM_LIT> ; if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( imm