<s> const bool HasSPE = <ISA_LIT>SubTarget -> hasSPE ( ) ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } unsigned CmpOpc ; bool NeedsExt = false ; auto RC = MRI . getRegClass ( SrcReg1 ) ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else { CmpOpc = <STR_LIT> ; if ( isVSSRCRegClass ( RC ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( SrcReg1 ) ; SrcReg1 = TmpReg ; } } break ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else if ( isVSFRCRegClass ( RC ) ) { CmpOpc = <STR_LIT> ; } else { CmpOpc = <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , ExtReg ,


<s> static DecodeStatus DecodeLOLoop ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return S ; unsigned Imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! Check ( S , DecodeBFLabelOperand < false , true , true , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Address , Decoder ) ) || ! Check ( S , DecodeBFLabelOperand < false , false , true , <NUM_LIT> > ( Inst , Imm , Address


<s> registered_function & rfn = * ( * registered_functions ) [ code ] ; return gimple_folder ( rfn . instance , rfn . decl , gsi , stmt


<s> FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> , DL ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , RSFIN , FIN , MachinePointerInfo ( SV , Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O


<s> SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex


<s> if ( TREE_TYPE ( function_type ) != void_type_node ) error ( <STR_LIT> ) ; if ( prototype_p ( function_type ) && ( TREE_VALUE ( TYPE_ARG_TYPES ( function_type ) ) != void_type_node || TREE_CHAIN ( TYPE_ARG_TYPES ( function_type ) ) != NULL_TREE ) ) error ( <STR_LIT> ) ; return NULL_TREE


<s> unsigned count = <NUM_LIT> ; while ( * p && isspace ( * p ) && * p != '\n' ) p ++ ; count ++ ; while ( * p && * p != '\n' && strncmp ( p , BaseTAI :: CommentString , strlen ( BaseTAI :: CommentString ) ) != <NUM_LIT> ) { if ( * p == ',' )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT>


<s> aarch64_simd_switcher simd ; for ( unsigned int i = <NUM_LIT> ; i < ARM_NEON_H_TYPES_LAST ; i ++ ) for ( unsigned int count = <NUM_LIT> ; count <= <NUM_LIT> ; ++ count ) if ( ! aarch64_scalar_builtin_type_p ( aarch64_simd_types [ i ] . type ) ) register_tuple_type ( count , i ) ; aarch64_init_simd_builtin_functions ( true )


) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return MCDisassembler ::


<s> const bool IsPurecap = TT . getEnvironment ( ) == Triple :: CheriPurecap || Options . ABIName == <STR_LIT> ; unsigned SP = MRI . getDwarfRegNum ( IsPurecap ? <STR_LIT> : <STR_LIT>


<s> return ( uint64x1_t ) __builtin_neon_vdup_ndi ( ( __builtin_neon_di


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> std :: string operand = <STR_LIT> ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; operand = <STR_LIT> + StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; } unsigned mfNum = MI -> getParent ( ) -> getParent ( ) -> getFunctionNumber ( ) ; unsigned bbNum = MI -> getParent ( ) -> getNumber ( ) ; O << '\n' << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> ; O << <STR_LIT> << mfNum << '_' << bbNum << '\n' ; O << <STR_LIT> << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> << operand << '\n' ; O << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> ; O << <STR_LIT> << operand << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> << operand << '\n' ; O << <STR_LIT> << operand << <STR_LIT> <<


<s> unsigned <ISA_LIT>ConstantIslands :: getOffsetOf ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: iterator I = MBB -> begin (


<s> const Constant * C = CN -> getConstVal ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetConstantPool ( C , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( C , PtrVT , <NUM_LIT>

, <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( CN -> getAlignment ( ) , <STR_LIT> ) ) ;


<s> int <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace , const Instruction * I ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT .


<s> unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } if ( NumBits > <NUM_LIT> ) { MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset = - ImmedOffset ; else ImmedOffset |= <NUM_LIT> << NumBits ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset = - ImmedOffset ; else ImmedOffset |= <NUM_LIT> << NumBits


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return


<s> std :: pair < Value * , Value * > <ISA_LIT>LowerAMXType :: getShape ( IntrinsicInst * II , unsigned OpNo ) { Value * Row = nullptr , * Col = nullptr ; switch ( II -> getIntrinsicID ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Row = II ->


<s> SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = FrameInfo -> CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty


<s> ARM_BUILTIN_CRYPTO_ ## U <STR_LIT> # L R ## _ftype_ ## A R ## _ftype_ ## A1 ## _ ## A2 R ## _ftype_ ## A1 ## _ ## A2 ## _ ## A3 arm_builtin_decls [ C ( U ) ] \ = add_builtin_function ( N ( L ) , FT1 ( R , A ) , \ C ( U ) , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ C ( U ) ] \ = add_builtin_function ( N ( L ) , FT2 ( R , A1 , A2 ) , \ C ( U ) , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ C ( U ) ] \ = add_builtin_function ( N ( L ) , FT3 ( R , A1

, A2 , A3 ) , \ C ( U ) , BUILT_IN_MD , NULL , NULL_TREE ) ;


<s> return ( float32x2_t ) __builtin_neon_vld1_lanev2sf ( ( const __builtin_neon_sf *


<s> case <NUM_LIT> : switch ( byte ) { case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_CS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_SS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_DS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_ES ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_FS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_GS ; break ; default : debug ( <STR_LIT> ) ; return - <NUM_LIT> ; } if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; hasOpSize = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; hasAdSize = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; default : isPrefix = FALSE ; break ; } if ( isPrefix ) dbgprintf ( insn , <STR_LIT> , byte ) ; } insn -> vexSize = <NUM_LIT> ; if ( byte == <NUM_LIT> ) { uint8_t byte1 ; if ( lookAtByte ( insn , & byte1 ) ) { dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( insn -> mode == MODE_64BIT || ( byte1 & <NUM_LIT> ) == <NUM_LIT> ) { insn -> vexSize = <NUM_LIT> ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } else { unconsumeByte ( insn ) ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } if ( insn -> vexSize == <NUM_LIT> ) { insn -> vexPrefix [ <NUM_LIT> ] = byte ; consumeByte ( insn , & insn -> vexPrefix [ <NUM_LIT> ] ) ; consumeByte ( insn , & insn -> vexPrefix [ <NUM_LIT> ] ) ; if ( insn -> mode == MODE_64BIT ) { insn -> rexPrefix = <NUM_LIT> | ( wFromVEX3of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | ( rFromVEX2of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | ( xFromVEX2of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | ( bFromVEX2of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) ; } switch ( ppFromVEX3of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) ) { default : break ; case VEX_PREFIX_66 : hasOpSize = TRUE


<s> Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) RegName = Parser . getTok ( ) . getString ( ) . lower ( ) ; else return MatchOperand_ParseFail ; int RegNum = matchMSA128RegisterName ( RegName ) ; if ( RegNum < <NUM_LIT> || RegNum > <NUM_LIT> ) return MatchOperand_ParseFail ; int RegVal = getReg ( regKindToRegClass ( Kind ) , RegNum ) ; if ( RegVal == - <NUM_LIT> ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * Op = <STR_LIT> ( RegVal , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( Kind ) ; Operands . push_back ( Op ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: LBrac ) ) return MatchOperand_Success ; <ISA_LIT>Operand * Mnemonic = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { <ISA_LIT>Operand * RegOp ; SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( <STR_LIT> ) ) ; if ( Reg == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegOp = <STR_LIT> ( Reg , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { int RegNum = - <NUM_LIT> ; std :: string RegName = Parser . getTok ( ) . getString ( ) . lower ( ) ; RegNum = matchCPURegisterName ( RegName ) ; if ( RegNum == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegNum = getReg ( regKindToRegClass ( <STR_LIT> ) , RegNum ) ; RegOp = <STR_LIT> ( RegNum , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else return MatchOperand_ParseFail ; RegOp -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( RegOp ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok


<s> MachineBasicBlock :: iterator J = I ; ++ J ; BuildMI ( MBB , J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; ++ FilledSlots ; Changed = true ; } return


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( Value == <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT>


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , IsN64 ? <STR_LIT> : <STR_LIT> , VT ) ; return FrameAddr


<s> static bool isUndefOrInRange ( int Val , int Low , int Hi


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredTLSAddr ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction & MF = * BB -> getParent ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get (

AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> } case <STR_LIT> : { EVT Ty = Op . getValueType ( ) ; if ( Ty == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; } else if ( Ty . isVector ( ) && Ty . isInteger ( ) && isTypeLegal ( Ty ) ) { return DAG . getNode ( <STR_LIT> , dl , Ty , Op . getOperand ( <NUM_LIT> ) ) ; } else { report_fatal_error ( <STR_LIT> ) ; } } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned Reg ; if ( RegInfo -> hasBasePointer ( MF ) ) Reg = RegInfo -> getBaseRegister ( ) ; else Reg = RegInfo -> getFrameRegister ( MF ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , Op . getSimpleValueType


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [


<s> assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned FromSz = LdVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ]


<s> if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( VT == <STR_LIT> && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: <ISA_LIT>_RegCall ) return <NUM_LIT> ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>PostSelectOptimize ( ) ) ; return


<s> return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) && MF . getFunction ( )

. getCallingConv ( ) != CallingConv :: SwiftTail ;


<s> static int arm_save_coproc_regs ( void ) { int saved_size = <NUM_LIT> ; unsigned reg ; unsigned start_reg ; rtx insn ; if ( TARGET_REALLY_IWMMXT ) for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( reg_needs_saving_p ( reg ) ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG (


<s> assert ( Root . getOperand ( <NUM_LIT> ) . isReg ( ) && Root . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULADDH_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULADDH_OP2 ) ; break ; case <STR_LIT> : assert ( Root . getOperand ( <NUM_LIT> ) . isReg ( ) && Root . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULADDS_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv1i32_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULADDS_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv1i32_indexed_OP2 ) ; break ; case <STR_LIT> : Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULADDD_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv1i64_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULADDD_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv1i64_indexed_OP2 ) ; break ; case <STR_LIT> : Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4i16_indexed_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4f16_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4i16_indexed_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4f16_OP2 ) ; break ; case <STR_LIT> : Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv8i16_indexed_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv8f16_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv8i16_indexed_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv8f16_OP2 ) ; break ; case <STR_LIT> : Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2i32_indexed_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2f32_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2i32_indexed_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2f32_OP2 ) ; break ; case <STR_LIT> : Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2i64_indexed_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2f64_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2i64_indexed_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv2f64_OP2 ) ; break ; case <STR_LIT> : Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4i32_indexed_OP1 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4f32_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4i32_indexed_OP2 ) || Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMLAv4f32_OP2 ) ; break ; case


<s> Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { unsigned Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt32Immediate ( RHS , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( ( int ) Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm >> <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt32Immediate ( RHS , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( ( int ) SImm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS


<s> return __builtin_mve_vcmpneq_sv16qi ( __a ,


<s> SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , DL , WideVT ) , BitShift ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , CmpVal , SwapVal , BitShift , NegBitShift , DAG . getConstant ( BitSize , DL , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList


<s> if ( ElfSym -> getOther ( ) & ELF :: STO_MIPS_MICROMIPS ) return true ; } return


<s> bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF , false ) ; int NegFrameSize = - FrameSize ; bool IsLargeFrame = ! isInt < <NUM_LIT> > ( NegFrameSize ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; bool HasRedZone = Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) ; return ( IsLargeFrame || ! HasRedZone ) && HasBP &&


<s> Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * SrcRC ; const TargetRegisterClass * DstRC ; std :: tie ( SrcRC , DstRC ) = getRegClassesForCopy ( I , TII , MRI , TRI , RBI ) ; if ( ! DstRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RBI . getSizeInBits ( DstReg , MRI , TRI ) << '\n' ) ; return false ; } bool KnownValid = false ; auto CheckCopy = [ & ] ( ) { assert ( ( I . isCopy ( ) || ( ! Register :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! Register :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) && <STR_LIT> ) ; assert ( KnownValid || isValidCopy ( I , DstRegBank , MRI , TRI , RBI ) ) ; ( void ) KnownValid ; return true ; } ; if ( I . isCopy ( ) ) { if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SrcSize = TRI . getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = TRI . getRegSizeInBits ( * DstRC ) ; if ( SrcSize > DstSize ) { const TargetRegisterClass * SubregRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; assert ( SubregRC && <STR_LIT> ) ; unsigned SubReg = <NUM_LIT> ; if ( ! getSubRegForClass ( DstRC , TRI , SubReg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Op0 . getOpcode ( ) ==


<s> if ( lowerLongBranch ( MI , OutMI ) ) return ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++


<s> unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , OrigDestSize , NewDestReg ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ; unsigned NumArgs = MI -> getNumOperands


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull (


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirective<ISA_LIT> ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnEnd ( DirectiveID . getLoc


<s> SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue (


<s> return StringSwitch < bool > ( Name . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true

) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> s = division ; if ( TARGET_FIX_R4000 || TARGET_FIX_R4400 ) { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } if ( TARGET_CHECK_ZERO_DIV ) { if ( TARGET_MIPS16 ) { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } else if ( GENERATE_DIVIDE_TRAPS ) { if ( TUNE_74K ) output_asm_insn ( <STR_LIT> , operands ) ; else { output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } } else { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( s ,


<s> EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) ) { unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT , FPLogic ) ; } if ( ! Subtarget . hasAVX ( ) || VT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; unsigned NumElts = <NUM_LIT> / N00Type . getSizeInBits ( ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , N00Type , NumElts ) ; EVT BoolVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue ZeroIndex = DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 . getOperand ( <NUM_LIT> ) ; SDValue Vec00 = DAG . getNode ( <STR_LIT> , DL , VecVT , N00 ) ; SDValue Vec01 = DAG . getNode ( <STR_LIT> , DL , VecVT , N01 ) ; SDValue Vec10 = DAG . getNode ( <STR_LIT> , DL , VecVT , N10 ) ; SDValue Vec11 = DAG . getNode ( <STR_LIT> , DL , VecVT , N11 ) ; SDValue Setcc0 = DAG . getSetCC ( DL , BoolVecVT , Vec00 , Vec01 , cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ->


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst1


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val ,


<s> case <STR_LIT> : case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : default : RegNum = matchCPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) ) ; break ; } if ( RegNum > - <NUM_LIT> ) RegNum = getReg ( regKindToRegClass ( Kind ) , RegNum ) ; } if ( RegNum > - <NUM_LIT> ) { Parser . Lex ( ) ; <ISA_LIT>Operand * op = <STR_LIT> ( RegNum , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( Kind ) ; Operands . push_back ( op ) ; return true


<s> if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , VT . getVectorNumElements ( ) ) ; Value = DAG . getBitcast ( CastVT , Value ) ; } SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , Value , VecIndex ) ; return DAG . getStore ( MS -> getChain ( ) , DL , Extract , Addr , MS -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment , MS ->


<s> BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT>

) . getReg ( ) ) . addReg ( <STR_LIT> ) ;


( ( warn_unused_result ) ) cmse_nonsecure_caller ( void ) {


<s> static SDValue LowerMLOAD ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MaskedLoadSDNode * N = cast < MaskedLoadSDNode > ( Op . getNode ( ) ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; SDValue Mask = N -> getMask ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; if ( MaskVT . getVectorElementType ( ) != <STR_LIT> ) { if ( PassThru . isUndef ( ) || <STR_LIT> ( PassThru . getNode ( ) ) ) return Op ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , getZeroVector ( VT , Subtarget , DAG , dl ) , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Select = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Select , NewLoad . getValue ( <NUM_LIT> ) } , dl ) ; } assert ( ( ! N -> isExpandingLoad ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isExpandingLoad ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT ==

<STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ;


<s> use_pblendvb : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = ( d -> perm [ i ] < nelt ? const0_rtx : constm1_rtx ) ; finish_pblendvb : vperm = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) emit_insn ( gen_sse4_1_pblendvb ( target , op0 , op1 , vperm ) ) ; else emit_insn ( gen_avx2_pblendvb ( target , op0 , op1 , vperm ) ) ; if ( target != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , target ) ) ; return true ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8HImode ; do_subreg : target = gen_reg_rtx ( vmode ) ; op0 = gen_lowpart ( vmode , op0 ) ; op1 = gen_lowpart ( vmode , op1 ) ; break ; case V32QImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) goto use_pblendvb ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) break ; if ( i < <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) goto use_pblendvb ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V16HImode ; goto do_subreg ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8SImode ; goto do_subreg ; case V16HImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) break ; if ( i < <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rperm [ i ] = ( d -> perm [ i / <NUM_LIT> ] < <NUM_LIT> ? const0_rtx : constm1_rtx ) ; vmode = V32QImode


<s> static MachineInstr * genFusedMultiplyIdxNeg ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg , unsigned IdxMulOpd , unsigned MaddOpc , unsigned MnegOpc , const TargetRegisterClass * RC ) { assert ( IdxMulOpd == <NUM_LIT> ) ; Register NewVR = genNeg ( MF , MRI , TII ,

Root , InsInstrs , InstrIdxForVirtReg , MnegOpc , RC ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlign (


<s> expand_cbranchsi4 ( operands , comparison , profile_probability :: uninitialized


<s> for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; if ( I -> readsRegister ( <STR_LIT> ) ) return nullptr ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShiftAmt = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } return & * I ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> machine_mode mode = ( machine_mode ) i ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_ANY_SVE ) bitmap_set_bit


<s> } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return


<s> __o = __builtin_aarch64_ld3rv2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t


<s> default : break ; case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; } if ( tlsOpNo != <NUM_LIT> ) { const MCOperand & MO = MI . getOperand ( tlsOpNo ) ; uint64_t op = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( op == <NUM_LIT> && <STR_LIT>


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target ,


<s> static bool blockEndIsUnreachable ( const MachineBasicBlock & MBB , MachineBasicBlock :: const_iterator MBBI ) { return std :: all_of ( MBB . succ_begin ( ) , MBB . succ_end ( ) , [ ] ( const MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) ; } ) && std :: all_of ( MBBI , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI . isMetaInstruction ( ) ; }


<s> for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . setOffset (


<s> isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePSBHint ( PSB -> Encoding , Tok . getString ( ) , S , getContext ( ) ) ) ; Lex ( ) ; return MatchOperand_Success


<s> imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; window [ num_insn ] . insn = insn ; window [ num_insn ] . byte_len = byte_len ; window [ num_insn ] . group = group ; window [ num_insn ] . path = path ; window [ num_insn ] . imm_bytes = imm_size ; window_list -> window_size += byte_len ; window_list -> num_insn = num_insn + <NUM_LIT> ; window_list -> num_uops = window_list -> num_uops + num_uops ; window_list -> imm_size += imm_size ; window_list -> num_imm += num_imm_operand ; window_list -> num_imm_32 +=


<s> SmallPtrSet < const GlobalVariable * , <NUM_LIT> > & getGlobalsPromotedToConstantPool ( ) { return PromotedGlobals


<s> return __extension__ ( __m128d ) { __F ,


<s> bool hasMessageSecurityAssist3 ( ) const { return


<s> if ( TARGET_ARCH64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , end_lab ) ; fputc ( '\n' , asm_out_file ) ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; if ( TARGET_ARCH64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab


<s> if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else return false ; unsigned DefReg = SrcReg ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) { DefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , DefReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } MachineInstr & AndInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( AndOpc ) , DstReg ) . addReg ( DefReg ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( AndInst , TII , TRI


<s> if ( MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true ; } return false


<s> if ( ! TARGET_64BIT ) return <NUM_LIT> ; if ( FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset = <NUM_LIT> ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) { Subtarget = & TM . getSubtarget <


<s> static DecodeStatus DecodeT2AddrModeImm0_1020s4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm (


<s> else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } assert ( LoLoop . Start -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( LoLoop . Dec != LoLoop . End ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA -> getReachingLocalUses ( LoLoop . Dec , MCRegister :: from ( <STR_LIT> ) , Uses ) ; if ( Uses . size ( ) > <NUM_LIT> || ! Uses .


<s> return id < <NUM_LIT> ? build_pointer_type


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false


<s> if ( class != R1_REGS && is_symbolic ) return R1_REGS ; return NO_REGS ; } static bool pa_pass_by_reference ( CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( TARGET_64BIT ) return size <= <NUM_LIT> ; else return size <= <NUM_LIT> || size > <NUM_LIT> ; } enum direction function_arg_padding ( enum machine_mode mode , tree type ) { if ( mode == BLKmode || ( TARGET_64BIT && type && AGGREGATE_TYPE_P ( type ) ) ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( int_size_in_bytes ( type ) * BITS_PER_UNIT ) % PARM_BOUNDARY == <NUM_LIT> ) return none ; if ( TARGET_64BIT ) return upward ; else return downward ; } if ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY ) return downward ; else return none ; } static rtx hppa_builtin_saveregs ( void ) { rtx offset , dest ; tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ) ? UNITS_PER_WORD : <NUM_LIT> ) ; if ( argadj ) offset = plus_constant ( current_function_arg_offset_rtx , argadj ) ; else offset = current_function_arg_offset_rtx ; if ( TARGET_64BIT ) { int i , off ; if ( argadj ) offset = plus_constant ( current_function_arg_offset_rtx , - argadj ) ; else offset =


<s> SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FirstInsertedMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FirstInsertedMBB -> addSuccessor ( SecondInsertedMBB ) ; FirstInsertedMBB -> addSuccessor ( SinkMBB ) ; SecondInsertedMBB -> addSuccessor ( SinkMBB ) ; <STR_LIT> FirstCC = <STR_LIT> ( FirstCMOV . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( ThisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( FirstCC ) ; <STR_LIT> SecondCC = <STR_LIT> ( SecondCascadedCMOV . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( FirstInsertedMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( SecondCC ) ; Register DestReg = FirstCMOV . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = FirstCMOV . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = FirstCMOV . getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>AIXAsmPrinter :: EmitFunctionDescriptor ( ) { const DataLayout & DL = getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSizeInBits ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > (

CurrentFnDescSym ) -> getContainingCsect ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG &


<s> DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP =


<s> unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI


<s> if ( RegNo > <NUM_LIT> || ( ! hasD32 && RegNo > <NUM_LIT> ) ) return MCDisassembler :: Fail ; unsigned Register = DPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler ::


<s> } } DenseMap < Location , DenseSet < unsigned >> Seen ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( <STR_LIT> ( MI . getDesc ( ) . TSFlags ) < <NUM_LIT> ) continue ; const DILocation * DI = MI . getDebugLoc ( ) ; if ( ! DI ) { DI = ReferenceDI ; } Location L = diToLocation ( DI ) ; DenseSet < unsigned > & Set = Seen [ L ] ; const std :: pair < DenseSet < unsigned > :: iterator , bool > TryInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; if ( ! TryInsert . second ) { unsigned BF , DF , CI = <NUM_LIT> ; DILocation :: decodeDiscriminator ( DI -> getDiscriminator ( ) , BF , DF , CI ) ; Optional < unsigned > EncodedDiscriminator = DILocation :: encodeDiscriminator ( MemOpDiscriminators [ L ] + <NUM_LIT> , DF , CI ) ; if ( ! EncodedDiscriminator ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << DI -> getFilename ( ) << <STR_LIT> << DI -> getLine ( ) << <STR_LIT> << DI -> getColumn ( ) << <STR_LIT> ) ; continue ; } ++ MemOpDiscriminators [


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM

, CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) {


<s> assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) , DL , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , Cmp . getValue ( <NUM_LIT>


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isThumb2 ( ) ) { EncodedValue &= <NUM_LIT> ; EncodedValue |= <NUM_LIT> ; } return


<s> if ( reg == <STR_LIT> ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; lastCheck -> insert ( CI


<s> BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( )


<s> DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) &&


<s> static void buildCallOperands ( SmallVectorImpl < SDValue > & Ops , <ISA_LIT>TargetLowering :: CallFlags CFlags , const SDLoc & dl , SelectionDAG & DAG , SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > & RegsToPass , SDValue Glue , SDValue Chain , SDValue & Callee , int SPDiff , const <ISA_LIT>Subtarget & Subtarget ) { const bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; const MVT RegVT = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; Ops . push_back ( Chain ) ; if ( ! CFlags . IsIndirect ) Ops . push_back ( Callee ) ; else { assert ( ! CFlags . IsPatchPoint && <STR_LIT> ) ; if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { const MCRegister StackPtrReg = Subtarget . getStackPointerRegister ( ) ; SDValue StackPtr = DAG . getRegister ( StackPtrReg , RegVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , StackPtr , TOCOff ) ; Ops . push_back ( AddTOC ) ; } if ( Subtarget . usesFunctionDescriptors ( ) && ! CFlags . HasNest ) Ops . push_back ( DAG .

getRegister ( Subtarget . getEnvironmentPointerRegister ( ) , RegVT ) ) ;


<s> bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI


<s> inline static bool MaskRegClassContains ( unsigned Reg ) { return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ||


<s> printOperand ( MI , opNum + <NUM_LIT> , O ) ; O <<


<s> const MCSection * FindAssociatedSection ( ) const


<s> inline unsigned getSizeOfImm ( uint64_t TSFlags ) { switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case


<s> if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( ! isTailCall && CS && CS -> isMustTailCall ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { if ( Subtarget . is<ISA_LIT>64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , IsPatchPoint , Outs , OutVals , Ins , dl , DAG , InVals , CS ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , IsPatchPoint , Outs ,


<s> return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> void <ISA_LIT>RegisterSema :: setSF ( <STR_LIT> SF , Value * Val ) { SFVals [ SF ] = Val ; if ( ! Val -> hasName ( ) ) Val -> setName ( ( Twine ( getSFName ( SF

) ) + <STR_LIT> + utostr ( SFAssignments [ SF ] ++ ) ) . str ( ) ) ;


<s> mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld :: The<ISA_LIT>Target , mcld :: create<ISA_LIT>LDBackend


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r'


<s> return __builtin_aarch64_popcountv8qi (


<s> EHSecName += FnSecName ; } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection


<s> bool has<ISA_LIT>32r6 ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> AsmToken RegTok = getLexer ( ) . peekTok ( ) ; SMRange RegRange = RegTok . getLocRange ( ) ; StringRef FixedName = StringSwitch < StringRef > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; assert ( FixedName != <STR_LIT> && <STR_LIT> ) ; printWarningWithFixIt ( <STR_LIT> , <STR_LIT> + FixedName + <STR_LIT> , RegRange ) ; } if ( <NUM_LIT> <= CC && CC <= <NUM_LIT> ) CC += <NUM_LIT> ; if ( CC == - <NUM_LIT> ) CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> ,

<NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , Opcode ) ) return false ; MI . setDesc ( TII -> get ( Opcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return


<s> case k_Barrier : { bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( getBarrier ( ) , Valid ) ; if ( Valid ) OS << <STR_LIT> << Name << <STR_LIT> ; else OS << <STR_LIT> << getBarrier ( ) << <STR_LIT> ; break ; } case k_Immediate : getImm ( ) -> print ( OS ) ; break ; case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; getShiftedImmVal ( ) -> print ( OS ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ; break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( )


<s> int <ISA_LIT>FrameLowering :: getFrameIndexOffsetFromSP ( const MachineFunction & MF , int FI ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI -> getStackSize (


<s> if ( ! flag_pic ) return true ; if ( decl ==


<s> void <ISA_LIT>DCBasicBlock :: materializeRegister ( unsigned


<s> O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) <<


<s> Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange = true ; } } return


<s> static bool splitBitmaskImm ( T Imm , unsigned RegSize , T & Imm1Enc , T & Imm2Enc ) { T UImm = static_cast < T > ( Imm ) ; if ( <STR_LIT> ( UImm , RegSize ) ) return false ; SmallVector < <ISA_LIT>_IMM :: ImmInsnModel , <NUM_LIT>


<s> int offset ; addr_space_t as = DEFAULT_TLS_SEG_REG ; rtx r ; gcc_assert ( flag_split_stack ) ; offset = TARGET_THREAD_SPLIT_STACK_OFFSET ; gcc_unreachable ( ) ; r = GEN_INT ( offset ) ; r = gen_const_mem ( Pmode , r ) ; set_mem_addr_space ( r , as ) ; return


<s> emit_label ( XEXP ( label , <NUM_LIT> ) ) ; before = scratch = gen_reg_rtx ( SImode ) ; emit_load_locked ( SImode , before , mem ) ; switch ( code ) { case IOR : case XOR : case AND : after = expand_simple_binop ( SImode , code , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = after ; break ; case PLUS : case MINUS : before = expand_binop ( SImode , and_optab , scratch , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , xor_optab , scratch , before , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_simple_binop ( SImode , code , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_binop ( SImode , and_optab , after , mask , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , ior_optab , scratch , after , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; break ; case MULT : after = expand_binop ( SImode , and_optab , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_binop ( SImode , xor_optab , after , mask , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = after ; break ; default : gcc_unreachable ( ) ; } emit_store_conditional ( SImode , mem , scratch ) ; emit_unlikely_jump ( EQ , label ) ; if ( orig_before ) or1k_finish_atomic_subword ( mode , orig_before , before , shift ) ; if ( orig_after ) or1k_finish_atomic_subword ( mode ,


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address


<s> return ( __m128d ) __builtin_ia32_cvtuqq2pd128_mask ( ( __v2di ) __A , ( __v2df ) _mm_setzero_pd ( ) ,


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( )


<s> } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE


<s> static bool i386_pe_dllexport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) return true ; if ( associated_type ( decl ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( associated_type ( decl ) )

) ) return i386_pe_type_dllexport_p ( decl ) ;


<s> TSTInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm ( ( int64_t ) <STR_LIT> ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm (


<s> while ( PredMBB ) { TargetMBBInfo * PredMBBInfo = getMBBInfo ( PredMBB ) ; if ( ! PredMBBInfo || PredMBBInfo -> SrcReg != MBBInfo -> SrcReg ) return false ; assert ( SaveMBB == PredMBBInfo -> TBB || SaveMBB == PredMBBInfo -> FBB ) ; bool IsFalseBranch = ( SaveMBB == PredMBBInfo -> FBB ) ; <STR_LIT> CC = PredMBBInfo -> BranchCode ; assert ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; int PredCmpValue = PredMBBInfo -> CmpValue ; bool ValueCmpTrue = ( ( CmpValue < PredCmpValue && CC == <STR_LIT> ) || ( CmpValue > PredCmpValue && CC == <STR_LIT> ) || ( CmpValue == PredCmpValue && CC == <STR_LIT> ) ) ; if ( ! ( ValueCmpTrue ^ IsFalseBranch ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BranchPath . push_back (


<s> unsigned long count = <NUM_LIT> ; while ( value ) { count


<s> vld3_dup_s32 ( const int32_t * __a ) { int32x2x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregciv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregciv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t )


<s> return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum


<s> } switch ( SVT ) { case <STR_LIT> : case <STR_LIT> : if ( Fast ) * Fast = true ; return true ; default : return


<s> if ( ( ( align & <NUM_LIT> ) != <NUM_LIT> || ( length & <NUM_LIT> ) != <NUM_LIT> ) && ( ! unaligned_access || BYTES_BIG_ENDIAN ) ) return false ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) return arm_block_set_aligned_vect ( dstbase , length , value , align ) ; else return arm_block_set_unaligned_vect ( dstbase , length , value ,


<s> static unsigned Get<ISA_LIT>RegNum ( const MCOperand & MO ) { return <ISA_LIT>_MC :: get<ISA_LIT>RegNum ( MO


<s> unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB


<s> return __ev_mwsmian ( t , ( ( __ev64_s32__ ) { <NUM_LIT>


<s> bool isMaskType ( EVT SomeVT ) { if ( ! SomeVT . isVector ( ) ) return false ; return SomeVT . getVectorElementType ( ) ==


<s> SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , MaskConst ) ; SDValue Res = DAG . getBitcast ( VT ,


<s> Inst . addOperand ( MCOperand :: createImm ( Imm + <NUM_LIT>


<s> size_t DashPosition = <NUM_LIT> ; StringRef TheTriple ; DashPosition = TT . find ( '-' ) ; if ( DashPosition == StringRef :: npos ) { TheTriple = TT . substr ( <NUM_LIT> ) ; } else { TheTriple = TT . substr ( <NUM_LIT> , DashPosition ) ; } if ( TheTriple == <STR_LIT> || TheTriple == <STR_LIT> ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( CPU == <STR_LIT>


<s> else if ( strcmp ( rs6000_tls_size_string , <STR_LIT> ) == <NUM_LIT> ) rs6000_tls_size = <NUM_LIT> ; else error ( <STR_LIT>


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target


<s> insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next )

) if ( NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION ) insn = next ;


<s> else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , false ,


<s> gcc_assert ( ! DECIMAL_FLOAT_MODE_P ( mode ) ) ; return CCFPmode ; } switch ( code ) { case EQ : case NE : return CCZmode ; case GEU : case LTU : rtx geu ; if ( GET_CODE ( op0 ) == PLUS && ( rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) || rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCCmode ; else if ( code == LTU && GET_CODE ( op0 ) == NEG && GET_CODE ( geu = XEXP ( op0 , <NUM_LIT> ) ) == GEU && REG_P ( XEXP ( geu , <NUM_LIT> ) ) && ( GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) == CCCmode || GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) == CCmode ) && REGNO ( XEXP ( geu , <NUM_LIT> ) ) == FLAGS_REG && XEXP ( geu , <NUM_LIT> ) == const0_rtx && GET_CODE ( op1 ) == LTU && REG_P ( XEXP ( op1 , <NUM_LIT> ) ) && GET_MODE ( XEXP ( op1 , <NUM_LIT> ) ) == GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) && REGNO ( XEXP ( op1 , <NUM_LIT> ) ) == FLAGS_REG && XEXP ( op1 , <NUM_LIT> ) == const0_rtx ) return CCCmode ; else return CCmode ; case GTU : case LEU : return CCmode


<s> unsigned getElementSize ( ) const { assert ( Predicated )


<s> bool IsPredicatedOn ( MachineInstr *


<s> MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; It = MBB . insert (


<s> __vector unsigned char a , b , c ; a = ( __vector unsigned char ) vec_splats ( __A ) ; b = ( __vector unsigned char ) vec_splats


<s> assert ( ( Kind == RegKind :: NeonVector || Kind == RegKind :: SVEDataVector || Kind == RegKind :: SVEPredicateVector ) && <STR_LIT> ) ; auto Op = CreateReg ( RegNum , Kind , S , E , Ctx , ExtTy , ShiftAmount , HasExplicitAmount ) ; Op -> Reg . ElementWidth = ElementWidth ; return Op


<s> void LLVMInitializeDcpu16Target ( ) { RegisterTargetMachine < Dcpu16TargetMachine > X (


<s> for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back ( NElts + i ) ; for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i )


<s> if ( ! set ) return <NUM_LIT> ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) ==


<s> EmitFrames ( nullptr ) ; EmitWindowsUnwindTables (


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; EVT VecVT = N -> getValueType ( <NUM_LIT> ) ; EVT ElVT = VecVT


<s> if ( sum == <NUM_LIT> || ( min_insn_size ( insn ) + sum ) >= <NUM_LIT> ) return true ; } num_restrict = count_num_restricted ( insn , window_list ) ; if ( num_restrict > num_allowable_groups [ group ] ) return false ; if ( window_list -> window_num == <NUM_LIT> ) { if ( path == path_double && ( window_list -> num_uops + <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent ( ) ; return NewMI


<s> bool isTargetWin32 ( ) const { return ! In64BitMode && ( isTargetCygMing (


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad ) ; return


<s> return parseSetFpDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetOddSPRegDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoOddSPRegDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPopDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPushDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>0Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString


<s> static MCOperand LowerSymbolOperand ( const MachineInstr * MI , const MachineOperand & MO , const MCSymbol * Symbol , AsmPrinter


<s> static int getCompactUnwindRegNum ( const unsigned * CURegs , unsigned Reg ) { for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs ==


<s> Mang -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( )


<s> insn = emit_move_insn ( reg , pic_ref ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable


<s> unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else Expr = getImm ( ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; return CE != nullptr && CE -> getValue ( ) < <NUM_LIT>


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i32gather_epi32 ( __m256i src , int const * base , __m256i index , __m256i mask , const int scale ) { return ( __m256i ) __builtin_ia32_gathersiv8si ( ( __v8si ) src , base , ( __v8si )


<s> static bool isMask ( const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) { return <STR_LIT> . hasSubClassEq ( RC


<s> if ( DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS && TREE_CODE ( decl ) == FUNCTION_DECL ) { static const char * const visibility_types [ ] = { NULL , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * name


<s> Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; auto getRemainingValueType = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } ; auto getRemainingSize = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { VT = getRemainingValueType ( BytesLeft ) ; VTSize = getRemainingSize ( BytesLeft ) ; Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { VT = getRemainingValueType ( BytesLeft ) ; VTSize = getRemainingSize ( BytesLeft ) ; TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) ) ; ++ i ; DstOff += VTSize ; BytesLeft -=


<s> return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ,


<s> obstack_1grow ( & m_string_obstack , <NUM_LIT> ) ; return ( char * ) obstack_finish (


<s> static const char * const CPUDirectives [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Directive = <STR_LIT> ; for ( const Function & F : M ) { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; unsigned FDir = STI . getDarwinDirective ( ) ; Directive = Directive > FDir ? FDir : STI . getDarwinDirective ( ) ; if ( STI . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; } assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; assert ( Directive < array_lengthof (


<s> __arm_ldc ( const unsigned int __coproc , const unsigned int __CRd , const void * __p ) { __builtin_arm_ldc ( __coproc , __CRd ,


<s> return decodeRegisterClass ( Inst , RegNo


<s> bool <ISA_LIT>BaseInstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> static DecodeStatus DecodeVecShiftR32ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> ,


<s> return current_tune -> fusible_ops & op


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter (


<s> const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( ! Subtarget -> isTargetDarwin ( ) && IsThreadLocal ) return <NUM_LIT> ; if ( Subtarget -> useMovt ( ) && Subtarget -> isTargetDarwin ( ) == ( RelocM != Reloc :: Static ) ) { unsigned Opc ; switch ( RelocM ) { case Reloc :: PIC_ : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case Reloc :: DynamicNoPIC : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; default : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) ,


<s> static void mmix_target_asm_function_epilogue (


) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( <NUM_LIT> - Val , getContext ( ) )


<s> return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNo<ISA_LIT>3D ( ) ; return false


<s> StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitPSHUFHW ( const SDNode *


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; } Inst . addOperand ( MCOperand :: CreateReg (


<s> bool <ISA_LIT>FastISel :: selectMul ( const Instruction * I ) { MVT VT ; if ( ! isTypeSupported ( I -> getType ( ) , VT , true ) ) return false ; if ( VT . isVector ( ) ) return selectBinaryOp ( I , <STR_LIT> ) ; const Value * Src0 = I -> getOperand ( <NUM_LIT> ) ; const Value * Src1 = I -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( Src0 ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( Src0 , Src1 ) ; if ( const auto * C = dyn_cast < ConstantInt > ( Src1 ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) { uint64_t ShiftVal = C -> getValue ( ) . logBase2 ( ) ; MVT SrcVT = VT ; bool IsZExt = true ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( Src0 ) ) { if ( ! isIntExtFree ( ZExt ) ) { MVT VT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , VT ) ) { SrcVT = VT ; IsZExt = true ; Src0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Src0 ) ) { if ( ! isIntExtFree ( SExt ) ) { MVT VT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , VT ) ) { SrcVT = VT ; IsZExt = false ; Src0 = SExt -> getOperand ( <NUM_LIT> ) ; } } } unsigned Src0Reg = getRegForValue ( Src0 ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( Src0 ) ; unsigned ResultReg = emitLSL_ri ( VT , SrcVT , Src0Reg , Src0IsKill , ShiftVal , IsZExt ) ; if ( ResultReg ) { updateValueMap ( I , ResultReg ) ; return true ; } } unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned ResultReg = emitMul_rr ( VT , Src0Reg , Src0IsKill , Src1Reg , Src1IsKill ) ; if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return


<s> if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! Disable<ISA_LIT>FastISel ) return new <ISA_LIT>FastISel