<s> VSETVLIInfo InInfo ; if ( MBB . pred_empty ( ) ) { InInfo . setUnknown ( ) ; } else { for ( MachineBasicBlock * P : MBB . predecessors ( ) ) InInfo = InInfo . intersect ( BlockInfo [ P -> getNumber ( ) ] . Exit ) ; } if ( ! InInfo . isValid ( ) ) return ; BBInfo . Pred = InInfo ; VSETVLIInfo TmpStatus = BBInfo . Pred . merge ( BBInfo . Change ) ; if ( BBInfo . Exit == TmpStatus ) return ; BBInfo . Exit = TmpStatus ; for ( MachineBasicBlock * S : MBB . successors ( ) ) if ( ! BlockInfo [ S -> getNumber

( ) ] . InQueue ) WorkList . push ( S ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( evaluateConstantImm ( getImm ( ) , Constant , VK ) ) { if ( Constant == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: createImm ( Constant ) ) ; return ; } llvm_unreachable ( <STR_LIT> ) ; } auto SE = cast < MCSymbolRefExpr > ( getImm ( ) ) ; unsigned Imm = <NUM_LIT> ; for ( char c : SE -> getSymbol ( ) . getName ( ) ) { switch ( c ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r'


<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; const GlobalValue * GV = N -> getGlobal ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( UseGOT ) { SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , TPReg ) ; } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue MNAdd = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , TPReg , AddrAdd )


<s> if ( ! Require . hasAVLReg ( ) ) return true ; Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [ PBB ->


<s> static rtx riscv_unspec_address_offset ( rtx base , rtx offset , enum riscv_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , base ) , UNSPEC_ADDRESS_FIRST +


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return splatPartsI64WithVL ( DL , VT , Lo


<s> gcc_assert ( valid_or_dirty_p ( ) && <STR_LIT> ) ; gcc_assert ( ! unknown_p ( ) && <STR_LIT> ) ; gcc_assert ( demand_p ( DEMAND_AVL ) && <STR_LIT> ) ; if ( ! demand_p ( DEMAND_AVL ) ) return true ; if ( demand_p ( DEMAND_NONZERO_AVL ) && other .


<s> void <ISA_LIT>MCCodeEmitter :: expandFunctionCall ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst ; MCOperand Func ; Register Ra ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> } if ( ! riscv_v_ext_vector_mode_p ( mode ) && mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) .


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override


<s> MCSymbol * TmpLabel = Ctx . createTempSymbol ( <STR_LIT> , true , false ) ; Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) . addOperand (

TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;


<s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == <NUM_LIT> ) { return MCDisassembler :: Fail ; } return DecodeGPRNoX0RegisterClass ( Inst , RegNo , Address , Decoder


<s> SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; { HandleSDNode Handle ( Upper ) ; SelectCode ( Upper . getNode ( ) ) ; Upper = Handle . getValue ( ) ; } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ; ReplaceUses ( Node , Or . getNode ( ) ) ; CurDAG -> RemoveDeadNode ( Node ) ; SelectCode ( Or . getNode ( )


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind )


<s> bool isPairFP64 ( ) const { return isReg (


<s> bool <ISA_LIT>InstrInfo :: isRVVSpill ( const MachineInstr & MI , bool CheckFIs ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( ! <STR_LIT> ( Opcode ) && ! isRVVWholeLoadStore ( Opcode ) && ! isRVVSpillForZvlsseg ( Opcode ) ) return false ; return ! CheckFIs || any_of ( MI . operands ( ) , [ ] ( const MachineOperand & MO ) { return MO .


<s> return ! MF . getSubtarget < <ISA_LIT>Subtarget > (

) . isRegisterReservedByUser ( PhysReg ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = N . getOperand ( <NUM_LIT>


<s> bool requiresRegisterScavenging ( const MachineFunction


<s> const GlobalValue * GV = N -> getGlobal ( ) ; unsigned Opcode = <STR_LIT> ( Subtarget . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( Opcode , DL , Ty , Addr ) , <NUM_LIT> ) ; ArgListTy Args ; ArgListEntry


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true


<s> static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { if ( Imm == <NUM_LIT> )


<s> if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst


<s> return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP ->


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm )

&& VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerSPLATVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VecVT = Op . getValueType ( ) ; assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ) ; } if ( SplatVal . getOpcode ( ) == <STR_LIT> && SplatVal . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , DL , VecVT , SplatVal . getOperand ( <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; if ( isNullConstant ( Hi ) ) return Lo ; Hi = DAG . getNode ( <STR_LIT> ,


<s> static bool real_insn_and_same_bb_p ( const insn_info * insn , const bb_info


<s> static bool available_occurrence_p ( const bb_info * bb , const vector_insn_info dem ) { insn_info * insn = dem . get_insn ( ) ; if ( dem . has_avl_reg ( ) ) { if ( ! vlmax_avl_p ( dem . get_avl ( ) ) ) { rtx dest = NULL_RTX ; if ( vsetvl_insn_p ( insn -> rtl ( ) ) ) dest = get_vl ( insn -> rtl ( ) ) ; for ( const insn_info * i = insn ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( read_vl_insn_p ( i -> rtl ( ) ) ) continue ; if ( find_access ( i -> defs ( ) , REGNO ( dem


<s> if ( Kind == TTI :: SK_Splice && isa < ScalableVectorType > ( Tp ) ) return getSpliceCost ( Tp , Index ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( Kind == TTI :: SK_Broadcast && isa < ScalableVectorType > ( Tp ) ) return LT . first * <NUM_LIT> ; return BaseT :: getShuffleCost ( Kind , Tp , Mask


<s> int64_t Imm = <NUM_LIT> ; bool IsConstant = false ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { IsConstant = RE -> evaluateAsConstant ( Imm ) ; } else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { IsConstant = true ; Imm = CE -> getValue ( ) ; } if ( IsConstant ) Inst . addOperand ( MCOperand


<s> const FeatureBitset & Features = STI . getFeatureBits ( ) ; auto & MAB = static_cast < <ISA_LIT>AsmBackend & > ( MCA . getBackend ( ) ) ; <STR_LIT> ABI = MAB . getTargetABI ( ) ; assert ( ABI != <STR_LIT> && <STR_LIT> ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ; switch ( ABI ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_SINGLE ; break ; case <STR_LIT> : case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_DOUBLE ; break ; case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_RVE ; break ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } MCA . setELFHeaderEFlags ( EFlags


<s> return ( ( DstReg - SrcReg ) & <NUM_LIT> )


<s> return decodeUImmOperand < N > ( Inst , Imm , Address


-> machine -> frame . fmask , regno - FP_REG_FIRST ) ) {


<s> if ( integer_zerop ( new_vl ) ) { return repl ; } tree tmp_var = create_tmp_var ( size_type_node , <STR_LIT> ) ; tree decl = get_read_vl_decl ( ) ; gimple * g = gimple_build_call ( decl , <NUM_LIT> ) ; gimple_call_set_lhs ( g , tmp_var ) ; tree indirect = fold_build2 ( MEM_REF , size_type_node , gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - <NUM_LIT> ) , build_int_cst ( build_pointer_type ( size_type_node ) , <NUM_LIT> ) ) ; gassign * assign = gimple_build_assign ( indirect , tmp_var ) ; gsi_insert_after ( f . gsi , assign , GSI_SAME_STMT


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Expr ,


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT>


<s> break ; case <STR_LIT> : InnerEndSymbol = MI -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; default : break ; } if ( InnerEndSymbol && InnerEndSymbol == MI -> getPreInstrSymbol ( ) ) { InnerHwlpEndOffset = Offset ; } unsigned Size = TII -> getInstSizeInBytes ( * MI ) ; if ( Size == <NUM_LIT> ) { Size = <NUM_LIT> ; } Offset += Size ; MachineInstr * Next = MI -> getNextNode ( ) ; if ( ! Next ) { Next = & MI -> getParent ( ) -> getNextNode ( ) -> front ( ) ; } MI = Next ; } assert ( isUInt < <NUM_LIT> > ( StartOffset ) && <STR_LIT> ) ; assert ( isUInt < <NUM_LIT> > ( EndOffset ) && <STR_LIT> ) ; MCSymbol * LastInstrSymbol = LastInstr -> getPreInstrSymbol ( ) ; if ( ! LastInstrSymbol ) { LastInstrSymbol = MF . getContext ( ) . createLinkerPrivateTempSymbol ( ) ; LastInstr -> setPreInstrSymbol ( MF , LastInstrSymbol ) ; } DebugLoc DL = HwlpSetup -> getDebugLoc ( ) ; int64_t LoopNum = Changed ? <NUM_LIT> : <NUM_LIT> ; if ( HwlpSetup -> getOpcode ( ) == <STR_LIT> ) { Register count = HwlpSetup -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( StartOffset == <NUM_LIT> ) { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) . addSym ( LastInstrSymbol ) ; } else { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) ; BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addMBB ( LoopHeader ) ; BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addSym ( LastInstrSymbol ) ; } } else { int64_t count = HwlpSetup -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( StartOffset == <NUM_LIT> && EndOffset < <NUM_LIT> ) { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addImm ( count ) . addSym ( LastInstrSymbol ) ; } else


<s> bool <ISA_LIT>ExpandPseudo :: expandLoadTLSGDAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipcInstPair ( MBB , MBBI , NextMBBI


<s> copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ; return false


<s> } else if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ; } else


<s> bool <ISA_LIT>TargetLowering :: signExtendConstant ( const ConstantInt *


<s> static void doAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Nand


<s> unsigned getMinVectorRegisterBitWidth ( )


<s> unsigned getMaxVLen ( ) const { return <NUM_LIT>


<s> if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT>


<s> BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT>


<s> return getSTI ( ) . getFeatureBits (


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI ,


<s> static bool real_insn_and_same_bb_p ( const insn_info * insn , const bb_info * bb ) { return insn != nullptr && insn -> is_real ( )


<s> is<ISA_LIT>Vector = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; is<ISA_LIT>Vector = true ; } else llvm_unreachable ( <STR_LIT> ) ; if ( is<ISA_LIT>Vector ) { RVFI -> setHasSpillVRs ( ) ; MFI . setStackID ( FI , TargetStackID :: <ISA_LIT>Vector ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) ; } else { BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) .


<s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo = MatchRegisterName ( Name ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createVecReg ( RegNo , S , E , isRV64


<s> Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) { RetOps . push_back ( Flag ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> SDValue Chain = Op -> getOperand ( <NUM_LIT> ) ; SDValue RMValue = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain


<s> case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , DL , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDNode * Op0 = Node -> getOperand ( <NUM_LIT> ) . getNode ( ) ; uint64_t Mask ; if ( isa < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) && isConstantMask ( Op0 , Mask ) ) { uint64_t ShAmt = Node ->


<s> BasicBlock * BB = L -> getHeader ( ) ; while ( BB ) { BasicBlock * Next = BB -> getSingleSuccessor ( ) ; for ( auto & I : BB -> instructionsWithoutDebug ( ) ) { InstrCount ++ ; const <ISA_LIT>TargetLowering * TLI = getTLI ( ) ; unsigned ISD = TLI -> InstructionOpcodeToISD ( I . getOpcode ( ) ) ; EVT VT = TLI -> getValueType ( DL , I . getType ( ) , true ) ; if ( TLI -> getOperationAction ( ISD , VT ) == TargetLowering :: LibCall ) { return false ; } if ( auto * Call = dyn_cast < CallInst > ( & I ) ) { if ( isa < IntrinsicInst > ( Call ) ) { if ( ! isLoweredToCall ( Call -> getCalledFunction ( ) ) ) { continue ; } } return false ; } if ( auto * Branch = dyn_cast < BranchInst > ( & I ) ) { if ( Branch -> isUnconditional ( ) || L -> isLoopLatch ( BB ) ) { InstrCount -- ; continue ; } else if ( auto * Cond = dyn_cast < IntrinsicInst > ( Branch -> getCondition


<s> bool hasSamePolicy ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other .


<s> case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return createM1Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> : return createM2Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> : return createM4Tuple ( CurDAG , Regs ,


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset +=


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction (


<s> } MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; MVT I1ContainerVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue CC = convertToScalableVector ( I1ContainerVT , Src , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF


<s> MCRegister getBPReg ( ) { return <STR_LIT>


<s> return TFI -> hasFP ( MF ) ? <STR_LIT>


<s> return ( REG_P ( x ) && riscv_regno_mode_ok_for_base_p ( REGNO ( x ) , mode ,


<s> static const char * getSpillLibCallName ( const MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI ) { static const char * const SpillLibCalls [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> bool IsIntegerValue = true ; if ( Tag % <NUM_LIT> ) IsIntegerValue = false ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( Tag != <STR_LIT> ) getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; else { StringRef Arch = StringValue ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( llvm :: <STR_LIT> ( Feature . Key ) ) clearFeatureBits ( Feature . Value , Feature . Key ) ; auto ParseResult = llvm :: <STR_LIT> ( StringValue , true , true ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << <STR_LIT> << Arch << <STR_LIT> << ErrMsg . getMessage ( ) ; } )


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> for ( int r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = <NUM_LIT> ; } if ( riscv_abi == ABI_ILP32E ) { for ( int r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) call_used_regs [ r ] = <NUM_LIT> ; } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ; } if ( ! TARGET_VECTOR


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET


<s> int64_t Offset = int64_t ( Value ) ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const

MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const {


<s> static unsigned getLRForRMW ( bool PtrIsCap , AtomicOrdering Ordering , int Width ) { if ( Width == <NUM_LIT> ) return getLRForRMW8 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW16 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW32 ( PtrIsCap , Ordering


<s> VSETVLIInfo InstrInfo ; unsigned NumOperands = MI . getNumExplicitOperands ( ) ; bool HasPolicy = <STR_LIT> ( TSFlags ) ; bool ForceTailAgnostic = <STR_LIT> ( TSFlags ) ; bool TailAgnostic = true ; if ( HasPolicy ) { const MachineOperand & Op = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Op . getImm ( ) & <NUM_LIT> ; } unsigned UseOpIdx ; if ( ! ( ForceTailAgnostic || ( HasPolicy && TailAgnostic ) ) && MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) ) { TailAgnostic = false ; const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ; MachineInstr * UseMI = MRI -> getVRegDef ( UseMO . getReg ( ) ) ; if ( UseMI ) { UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( HasPolicy ) -- NumOperands ; <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW


<s> static void riscv_file_start ( void ) { default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , (


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) ) return false ; if ( Imm . isNegZero ( ) )


<s> BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) || N -> getConstantOperandVal ( OffsetOpIdx ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstant ( Const -> getSExtValue ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , GA -> getOffset ( ) , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CP -> getOffset ( ) , CP -> getTargetFlags ( ) ) ; } else { continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Base -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( BaseOpIdx == <NUM_LIT> ) CurDAG -> UpdateNodeOperands ( N , Base . getOperand ( <NUM_LIT> ) , ImmOperand ,


<s> static int riscv_address_cost ( rtx addr , enum machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return riscv_address_insns ( addr ,


<s> int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF )


<s> static inline VConstraintType getConstraint ( uint64_t TSFlags ) { return static_cast < VConstraintType > ( ( TSFlags &


<s> bool <ISA_LIT>ExpandPseudo :: expandCapLoadGlobalCap ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { MachineFunction * MF = MBB .


<s> collectRedundancyVSETVLIInMF ( MachineFunction & MF ) { for ( auto & MBB : MF ) { collectRedundancyVSETVLIInMBB ( MBB )


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ; initialize<ISA_LIT>ExpandPseudoPass ( * PR


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( )


GORCI ) NODE_NAME_CASE ( GORCIW ) NODE_NAME_CASE ( VMV_X_S ) NODE_NAME_CASE ( SPLAT_VECTOR_I64 ) }


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue NegX = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero , X , Mask , VL ) ; SDValue Max = DAG . getNode ( <STR_LIT> , DL , ContainerVT


<s> if ( ! maybe_expand_insn ( icode , opno , m_ops ) ) { error ( <STR_LIT> ) ; return NULL_RTX ; } return function_returns_void_p ( ) ? const0_rtx : m_ops


<s> MVT <ISA_LIT>TargetLowering :: getVPExplicitVectorLengthTy


<s> if ( Kind == KindTy :: Immediate ) return isVTypeImm ( <NUM_LIT> ) ; return Kind ==


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ; auto PR = PassRegistry


<s> bool isPseudoJumpSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs


<s> if ( ! TLO . LegalOps ) return false ; EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; const APInt & Mask = C -> getAPIntValue ( ) ; APInt ShrunkMask = Mask & DemandedBits ; APInt ExpandedMask = Mask | ~ DemandedBits ; auto IsLegalMask = [ ShrunkMask , ExpandedMask ] ( const APInt & Mask ) -> bool { return ShrunkMask . isSubsetOf ( Mask ) && Mask . isSubsetOf ( ExpandedMask ) ; } ; auto UseMask = [ Mask , Op , VT , & TLO ] ( const APInt & NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL ,

VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ;


<s> if ( Subtarget . hasVInstructions ( ) && ( VT . isScalableVector ( ) || Subtarget . useRVVForFixedLengthVectors ( ) ) ) return EVT :: getVectorVT ( Context , <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger


<s> SDLoc DL ( N ) ; SDValue New0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C1 / C0 , DL , VT ) ) ; SDValue New1 = DAG . getNode ( <STR_LIT> , DL , VT , New0 , DAG . getConstant ( C0 , DL , VT ) ) ; if ( ( C1 % C0 ) == <NUM_LIT> ) return New1 ; return DAG . getNode ( <STR_LIT> , DL , VT , New1 , DAG . getConstant ( C1 % C0 , DL


<s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) { registered_function & rfn = * ( *


<s> static void doAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) .


<s> if ( ! BasePtr ) return false ; assert ( Stride != nullptr ) ; Builder . SetInsertPoint ( II ) ; CallInst * Call ; if ( II -> getIntrinsicID ( ) == <STR_LIT> ) Call = Builder . CreateIntrinsic ( <STR_LIT> , { DataType , BasePtr -> getType ( ) , Stride -> getType ( ) } , { II -> getArgOperand ( <NUM_LIT> ) , BasePtr , Stride , II -> getArgOperand ( <NUM_LIT> ) } ) ; else Call = Builder . CreateIntrinsic ( <STR_LIT> , { DataType , BasePtr -> getType ( ) , Stride -> getType ( ) } , { II -> getArgOperand ( <NUM_LIT> ) , BasePtr , Stride , II -> getArgOperand ( <NUM_LIT> ) } ) ; Call -> takeName ( II ) ; II -> replaceAllUsesWith ( Call


<s> MVT OpVT = ScalarOp . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpVT == XLenVT ) return SDValue ( ) ; if ( OpVT . bitsLT ( XLenVT ) ) { unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ; ScalarOp = DAG . getNode ( ExtOpc , DL , XLenVT , ScalarOp ) ; return DAG . getNode ( Op -> getOpcode ( ) , DL , Op -> getVTList ( ) , Operands ) ; } assert ( II -> SplatOperand > <NUM_LIT> && <STR_LIT> ) ; MVT VT = Op . getOperand ( SplatOp - <NUM_LIT> ) . getSimpleValueType ( ) ; assert ( XLenVT == <STR_LIT> && OpVT == <STR_LIT> && VT

. getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> if ( VTy -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; if ( ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> && ISD != <STR_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; InstructionCost BaseCost =


<s> SDValue <ISA_LIT>TargetLowering :: lowerVPREDUCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ResVT = ! VecVT . isInteger ( ) || VecEltVT . bitsGE (


<s> return get_avl ( ) == other . get_avl ( ) &&

get_avl_source ( ) == other . get_avl_source ( ) ;


<s> void riscv_expand_float_scc ( rtx target , enum rtx_code code , rtx op0 , rtx op1 ) { riscv_emit_float_compare ( & code , & op0 , & op1 ) ; rtx cmp = riscv_force_binary ( word_mode , code , op0


<s> SDValue MNAdd = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , TPReg , MNHi , AddrCIncOffset ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNAdd , AddrLo ) , <NUM_LIT> ) ; } if ( NotLocal ) { SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , TPReg ) ; } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue MNAdd = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , TPReg , AddrAdd ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNAdd


<s> void <ISA_LIT>DAGToDAGISel :: processFunctionAfterISel (


<s> } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ALIGN ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD64 ; case <STR_LIT>


<s> bool hasVInstructionsI64 ( ) const { return HasStdExtZve64x


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; if ( HaveVectorOp ) { for ( const MachineBasicBlock & MBB : MF ) { WorkList . push (


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount ,


<s> if ( vector_kill ) sbitmap_vector_free ( vector_kill ) ; if ( vector_antic ) sbitmap_vector_free ( vector_antic ) ; if ( vector_transp ) sbitmap_vector_free ( vector_transp ) ; if ( vector_comp ) sbitmap_vector_free ( vector_comp ) ; if ( vector_avin ) sbitmap_vector_free ( vector_avin ) ; if ( vector_avout ) sbitmap_vector_free ( vector_avout ) ; vector_edge_list = nullptr ; vector_kill =


<s> FunctionPass * llvm :: create<ISA_LIT>InsertVSETVLIPass ( ) { return new <ISA_LIT>InsertVSETVLI (


<s> switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case


<s> if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } } return true


<s> if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type )


<s> return VLen == <NUM_LIT> ? getMinVLen (


<s> auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . hasStdExtV ( ) ) return false ; return true


<s> if ( SDValue Result = combineSelectCCAndUse ( N , N0 , N1 , DAG , AllOnes ) ) return Result ; if ( SDValue Result = combineSelectCCAndUse ( N , N1 , N0 , DAG , AllOnes ) ) return Result ; return SDValue (


<s> return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL


<s> static bool incompatible_avl_p ( const vector_insn_info & info1 , const vector_insn_info &


<s> unsigned KnownSize = VT . getSizeInBits ( ) . getKnownMinValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) KnownSize *= <NUM_LIT> ; switch ( KnownSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F8 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F4 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F2 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_1 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_2 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_4 ; case <NUM_LIT> : return <STR_LIT> ::


<s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ; return Log2_32 ( SEW ) - <NUM_LIT>


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( Kind == VK_<ISA_LIT>_PCREL_LO && evaluatePCRelLo ( Res , Layout , Fixup ) ) return true ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO : case


<s> if ( isa < LoadInst > ( Inst ) && Ord == AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ; if ( isa < StoreInst > ( Inst ) && isReleaseOrStronger ( Ord ) ) return Builder . CreateFence


<s> unsigned <ISA_LIT>Subtarget :: getMaxELENForFixedLengthVectors ( ) const { assert ( hasStdExtV ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax ) && <STR_LIT> ) ; return PowerOf2Floor ( std :: max < unsigned > ( std :: min

< unsigned > ( RVVVectorELENMax , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> bool evaluateConstantImm ( int64_t & Imm , <ISA_LIT>MCExpr :: VariantKind & VK ) const { const MCExpr * Val = getImm ( ) ; bool Ret = false ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr >


<s> else IsValid = isUInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) , CurrentVendor ( <STR_LIT> ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; auto & MAB = static_cast < <ISA_LIT>AsmBackend & > ( MCA . getBackend ( ) ) ; <STR_LIT> ABI = MAB . getTargetABI ( ) ; assert ( ABI != <STR_LIT> && <STR_LIT> ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF


<s> DeadInstrs . insert ( & Tail ) ; MRI -> replaceRegWith ( Tail . getOperand ( <NUM_LIT> ) . getReg ( ) , LoADDI . getOperand (


<s> auto_vec < tree , <NUM_LIT> > argument_types ; function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos . types [ vec_type_idx ] , group . preds [ pred_idx ] , & group . ops_infos ) ; tree return_type = group . ops_infos . ret . get_tree_type ( group . ops_infos . types [ vec_type_idx ] . index ) ; b . allocate_argument_types ( function_instance


<s> bool <ISA_LIT>ExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandLoadLocalAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT> : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ; case <STR_LIT>


<s> BaseT :: getPeelingPreferences ( L , SE , PP


<s> if ( Fractional ) { Lmul = <NUM_LIT> - Lmul ; Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( MaskedoffAgnostic ) O << <STR_LIT> ; else O


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU


<s> if ( CPUName . empty ( ) ) { CPUName = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FS ) ; return *


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override { return & <STR_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , true , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT>


<s> copyPhysReg ( MBB , MBBI , DL , DstReg , SrcReg , KillSrc , MachineInstr ::


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm


<s> if ( SequenceMBBI -> hasUnmodeledSideEffects ( ) || SequenceMBBI -> mayLoadOrStore ( ) ) break ; if ( llvm :: any_of ( SequenceMBBI -> operands ( ) , [ & ] ( MachineOperand & MO ) { return MO . isReg ( ) && MO . isUse ( ) && SelectDests . count ( MO . getReg ( ) ) ; } ) ) break ; } } const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; BuildMI ( HeadMBB , DL , TII . getBrCond ( CC ) ) . addReg ( LHS ) . addReg ( RHS


<s> DEBUG ( F64Val -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; } } CurDAG -> RemoveDeadNodes (


<s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( std :: any_of ( std :: begin ( Regs ) , std :: end ( Regs ) , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ; } ) ) F . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { F , <STR_LIT>


<s> assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Imm = VT . getSizeInBits ( ) - <NUM_LIT> ; if ( Op . getOpcode ( ) == <STR_LIT> ) Imm &= ~ <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Imm , DL , Subtarget . getXLenVT ( ) ) ) ; } case <STR_LIT> : { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! VT . isVector ( ) ) return Op ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTrunc ( Op , DAG ) ; EVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; SDValue Result = Src ; LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = SrcVT . getVectorElementCount ( ) ; do { SrcEltVT = EVT :: getIntegerVT ( Context , SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT ResultVT = EVT :: getVectorVT ( Context , SrcEltVT , Count ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResultVT , Result ) ; } while ( SrcEltVT != DstEltVT ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , <NUM_LIT> ) ; case


<s> bool pass_vsetvl :: need_vsetvl ( const vector_insn_info & require , const vector_insn_info & curr_info ) const { if ( ! curr_info . valid_p ( ) || curr_info . unknown_p ( ) || curr_info . uninit_p ( ) ) return true ; if ( require . compatible_p ( static_cast < const vl_vtype_info & > ( curr_info ) ) )


<s> default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Dot : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Percent : return parseOperandWithModifier ( Operands


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) { auto TargetABI = <STR_LIT>


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU ,


<s> unsigned Ra = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Func . getExpr ( ) ; const MCExpr * CallExpr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL , Ctx ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg (


<s> b . append_name ( <STR_LIT> ) ; if ( ! overloaded_p ) { b . append_name ( operand_suffixes [ instance . op_info -> op ] ) ; b . append_name ( type_suffixes [ instance . type . index ] . vector ) ; } if ( overloaded_p && instance . pred == PRED_TYPE_m ) return b . finish_name ( ) ; b . append_name ( predication_suffixes [ instance . pred ] ) ; return b . finish_name (


<s> assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; return <STR_LIT> ( VT . getVectorElementType ( ) , <STR_LIT> / VT . getVectorElementType ( )


<s> MVT VT = Op . getSimpleValueType ( ) ; const auto * MemSD = cast < MemSDNode > ( Op ) ; EVT MemVT = MemSD -> getMemoryVT ( ) ; MachineMemOperand * MMO = MemSD -> getMemOperand ( ) ; SDValue Chain = MemSD -> getChain ( ) ; SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Mask , PassThru , VL ; if ( const auto * VPLoad = dyn_cast < VPLoadSDNode > ( Op ) ) { Mask = VPLoad -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPLoad -> getVectorLength ( ) ; } else { const auto * MLoad = cast < MaskedLoadSDNode > ( Op ) ; Mask = MLoad -> getMask ( ) ; PassThru = MLoad -> getPassThru ( ) ; } bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ?


<s> FunctionPass * llvm :: create<ISA_LIT>PulpHWLoopsPass ( ) { return new <ISA_LIT>PulpHWLoops (


<s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ; } return Val


<s> bool can_be_overloaded_p ( enum predication_type_index pred ) const override { return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum ||


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI


<s> adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ,

SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch +=


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT>


<s> static inline VConstraintType getConstraint


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopHeadMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( PtrIsCap , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( PtrIsCap , Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { assert ( ! PtrIsCap && <STR_LIT> ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( false , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg ,

DestReg , NewValReg , MaskReg , ScratchReg ) ;


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand


<s> return getRelaxedOpcode ( Inst . getOpcode ( ) )


<s> if ( ! getContext ( ) . getAsmInfo ( ) -> isCheriPurecapABI ( )


<s> case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7_6 = ( Value >> <NUM_LIT> ) &


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindReg , StartLoc , EndLoc ) ; Op -> Reg . Kind = Kind ; Op -> Reg . Num = Num ; return


<s> bool hasStdExtZfinx ( ) const { return


<s> void vector_infos_manager :: create_expr ( vector_insn_info & info ) { for ( size_t i = <NUM_LIT> ; i < vector_exprs . length ( ) ; i ++

) if ( * vector_exprs [ i ] == info ) return ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand (

<NUM_LIT> ) . isKill ( ) , FI , SrcRC , RI ) ;


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg ,


<s> StringRef getSysReg ( ) const { assert ( Kind == KindTy :: SystemRegister && <STR_LIT> ) ; return StringRef ( SysReg . Data , SysReg


<s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser ::


<s> riscv_move_integer ( dest , dest , INTVAL ( src ) , mode , FALSE ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src , FALSE ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base , FALSE ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode


<s> static void riscv_block_move_straight ( rtx dest , rtx src , unsigned HOST_WIDE_INT length ) { unsigned HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , <NUM_LIT> ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; riscv_emit_move ( regs [ i ] , adjust_address (


<s> bool has_non_zero_avl ( ) const { return m_avl .


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> ,


<s> SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) .


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } if ( MI . getNumOperands ( ) == <NUM_LIT> ) { TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg


<s> MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ; if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI


<s> return TYPE_MODE ( op_info -> args [ <NUM_LIT> ] . get_tree_type ( type .


<s> if ( lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; } switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ; AP . emitNops ( Num ) ; return true ; } break ; } case <STR_LIT> : OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> ) ->


<s> if ( ! Res . getNode ( ) ) return ; if ( N -> getNumValues ( ) == <NUM_LIT> ) { Results . push_back ( Res ) ; return ; } assert ( ( N -> getNumValues ( ) == Res -> getNumValues ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = N -> getNumValues ( ) ; I != E

; ++ I ) Results . push_back ( Res . getValue ( I ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MFI . hasVarSizedObjects ( ) && TRI ->


<s> MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == <NUM_LIT> && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return


<s> bool IsZeroExt = Op0 . getOpcode ( ) == <STR_LIT> ; bool IsVWMULSU = IsSignExt && Op1 . getOpcode ( ) == <STR_LIT> ; if ( ( ! IsSignExt && ! IsZeroExt ) || ! Op0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( IsVWMULSU || Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand


<s> void <ISA_LIT>AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode ; <ISA_LIT>MCExpr :: VariantKind VKHi ; if ( ParserOptions . IsPicEnabled ) { SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; VKHi = <ISA_LIT>MCExpr


<s> case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; } return MI . isAsCheapAsAMove


<s> Target & getThe<ISA_LIT>64Target ( ) { static Target The<ISA_LIT>64Target ; return


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef

< Register >> VRegs , FunctionLoweringInfo & FLI ) const {


<s> case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken ::


<s> if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ; if ( Op0 . getValueType ( ) != NarrowVT ) Op0 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op0 , Mask , VL ) ; ExtOpc = IsVWMULSU ? <STR_LIT> : ExtOpc ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL


<s> unsigned getVType ( ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; return VType .


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT>


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > (


<s> case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT : return riscv_pass_fpr_pair ( mode , fregno , GET_MODE_INNER ( mode ) , <NUM_LIT> , fregno + <NUM_LIT> , GET_MODE_INNER

( mode ) , GET_MODE_UNIT_SIZE ( mode ) ) ;


<s> if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset


<s> bool apply_mask_policy_p ( ) const override { return


<s> if ( MC . isReg ( ) ) O << getRegisterName ( MC . getReg ( ) ) ; else if ( MC . isImm ( ) ) O << MC . getImm ( ) ; else if ( MC . isExpr ( ) ) MC . getExpr ( ) -> print ( O


<s> StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , StoreVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ; bool IsMaskOp = VT . getVectorElementType ( ) == <STR_LIT> ; SDValue IntID = DAG . getTargetConstant ( IsMaskOp ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Store -> getChain ( ) , IntID , NewValue , Store -> getBasePtr ( ) , VL } , Store

-> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ;


<s> } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( - frame -> hard_frame_pointer_offset ) ; if ( ! SMALL_OPERAND ( INTVAL ( adjust ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , GEN_INT ( - frame -> hard_frame_pointer_offset ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } else if ( frame_pointer_needed ) { epilogue_cfa_sp_offset = step2 ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg , true , style == EXCEPTION_RETURN ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ; if ( step2 > <NUM_LIT> ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx ,


<s> static unsigned first_sew ( const vector_insn_info & info1 , const vector_insn_info &


<s> const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( HiReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; TII . loadRegFromStackSlot ( * BB , MI , DstReg , FI , DstRC , RI ) ; MI . eraseFromParent ( ) ; return


<s> if ( ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) ) { if ( TargetFlags != <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned Src1Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { unsigned MaskReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == MaskReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } else if ( TargetFlags == <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( DestReg == Src2Reg + <NUM_LIT> ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } else if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { unsigned MaskReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == MaskReg ) return Error (


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable (


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK ==


<s> IsCheriPurecapABI = ABI != <STR_LIT> && <STR_LIT> ( ABI ) ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> bool riscv_v_ext_vector_mode_p ( machine_mode mode ) { case MODE ## mode : \


<s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> unsigned ImmArgIdx = ~ <NUM_LIT> ; switch ( Opcode ) { case Instruction :: GetElementPtr : return TTI :: TCC_Free ; case Instruction :: Add : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( Imm . getMinSignedBits ( ) <= <NUM_LIT> && getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( ) ) ) { return TTI :: TCC_Free ; } } return getIntImmCost ( Imm , Ty ) ; } return TTI :: TCC_Free


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; if ( RI -> needsStackRealignment ( MF ) && MFI . hasVarSizedObjects ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry


<s> static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void *


<s> return convertFromScalableVector ( VecVT , Res , DAG , Subtarget ) ; } if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; } if ( Hi . getOpcode ( ) == <STR_LIT> && Hi . getOperand ( <NUM_LIT> ) == Lo && isa < ConstantSDNode > ( Hi . getOperand ( <NUM_LIT> ) ) && Hi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; return splatPartsI64ThroughStack ( DL , VecVT , Lo , Hi , DAG . getRegister ( <STR_LIT> ,


<s> static DecodeStatus DecodeVRRegisterClass ( MCInst & Inst , uint64_t RegNo

, uint64_t Address , const MCDisassembler * Decoder ) {


<s> std :: pair < unsigned , unsigned > <ISA_LIT>InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned


<s> for ( unsigned int i = <NUM_LIT> ; instance . op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i ) argument_types . quick_push ( instance . op_info -> args

[ i ] . get_tree_type ( instance . type . index ) ) ;


<s> assert ( CapSize == ( getContext ( ) . getTargetTriple ( ) . isArch64Bit ( )


<s> if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ) return <NUM_LIT> ; widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ; return wi :: umin ( min_size , <NUM_LIT>