<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec , VecIdx ) ; return


<s> if ( <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) && <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) && <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; SDValue BlendOp = lowerVSELECTtoBLENDI ( Op , Subtarget , DAG ) ; if ( BlendOp . getNode ( ) ) return BlendOp ; MVT VT = Op . getSimpleValueType


<s> offset = cfun -> machine -> frame . acc_sp_offset - sp_offset ; if ( BITSET_P ( cfun -> machine -> frame . acc_mask , <NUM_LIT> ) ) { mips_save_restore_reg ( word_mode , LO_REGNUM , offset , fn ) ; offset -= UNITS_PER_WORD ; mips_save_restore_reg ( word_mode , HI_REGNUM , offset ,


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv2di (


<s> return ; } int final_shift = number_of_first_bit_set ( val ) ; int leading_zeroes = clz_hwi ( val ) ; int number_of_bytes_needed = ( ( HOST_BITS_PER_WIDE_INT - <NUM_LIT> - leading_zeroes ) / BITS_PER_UNIT ) + <NUM_LIT> ; int number_of_bytes_needed2 = ( ( HOST_BITS_PER_WIDE_INT - <NUM_LIT> - leading_zeroes - final_shift ) / BITS_PER_UNIT ) + <NUM_LIT> ; if ( number_of_bytes_needed2 < number_of_bytes_needed ) val >>= final_shift ; else final_shift = <NUM_LIT> ; if ( val <= <NUM_LIT> ) { if ( val > <NUM_LIT> ) { unsigned HOST_WIDE_INT high = val - <NUM_LIT> ; dst . mov ( high ) ; dst . add ( <NUM_LIT> ) ; } else dst . mov ( val ) ; if ( final_shift > <NUM_LIT> ) dst . ashift ( final_shift ) ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned HOST_WIDE_INT byte = ( val >> ( <NUM_LIT> * ( <NUM_LIT> - i ) ) ) & <NUM_LIT> ; if (


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool IsSubWord = ( BitSize < <NUM_LIT> ) ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = earlyUseOperand ( MI . getOperand ( <NUM_LIT> ) ) ; int64_t Disp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand Src2 = earlyUseOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Register BitShift = IsSubWord ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; Register NegBitShift = IsSubWord ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; if ( IsSubWord ) BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; Register RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; Register RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = <STR_LIT> ( MI , MBB ) ; MachineBasicBlock * LoopMBB = <STR_LIT> ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB


<s> MachineInstr * MI = nullptr ; if ( MO . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) MI = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ; if ( ! MI || MI -> getParent ( ) != & MBB || ( unsigned ) MI -> getOpcode ( ) != CombineOpc ) return false ; if ( ! MRI . hasOneNonDBGUse ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( CheckZeroReg ) { assert ( MI -> getNumOperands ( ) >= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) !=


<s> public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind


<s> dbgs ( ) << <STR_LIT> ) ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( Is128Bit ? <STR_LIT> : <STR_LIT> ) , TmpReg ) . addReg ( VBStateReg ) . addReg ( OpReg ) ; ( void ) OrI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else if ( OpRC -> hasSuperClassEq ( & <STR_LIT> ) || OpRC -> hasSuperClassEq ( & <STR_LIT> ) || OpRC -> hasSuperClassEq ( & <STR_LIT> ) ) { assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; bool Is128Bit = OpRC -> hasSuperClassEq ( & <STR_LIT> ) ; bool Is256Bit = OpRC -> hasSuperClassEq ( & <STR_LIT> ) ; if ( Is128Bit || Is256Bit ) assert ( Subtarget -> hasVLX ( ) && <STR_LIT> ) ; Register VStateReg = MRI -> createVirtualRegister ( OpRC ) ; unsigned BroadcastOp = Is128Bit ? <STR_LIT> : Is256Bit ? <STR_LIT> : <STR_LIT> ; auto BroadcastI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( BroadcastOp ) , VStateReg ) . addReg ( StateReg ) ; ( void ) BroadcastI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BroadcastI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; unsigned OrOp = Is128Bit ? <STR_LIT> : Is256Bit ? <STR_LIT> : <STR_LIT> ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOp ) , TmpReg ) . addReg ( VStateReg ) . addReg ( OpReg ) ; ( void ) OrI ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { assert ( OpRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; if ( ! EFLAGSLive ) { auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( StateReg ) . addReg ( OpReg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ] = uint8_t ( Value


<s> case AsmToken :: Identifier : { if ( isCondCode ) return parseCondCode ( Operands , invertCondCode ) ; if ( ! parseRegister ( Operands ) ) return false ; OperandMatchResultTy GotShift = tryParseOptionalShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; const MCExpr * IdVal ; S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Integer : case AsmToken :: Real : case AsmToken :: Hash : { S = getLoc ( ) ; parseOptionalToken ( AsmToken :: Hash ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; if ( Parser . getLexer ( ) . peekTok ( ) . is ( AsmToken :: Real ) ) Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble ( ) , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; else if ( IntVal != <NUM_LIT> || isNegative ) return TokError (


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond


<s> Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } } else if ( VT . is256BitVector ( ) ) { if ( Subtarget -> hasInt256 ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { SDValue Cst = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget -> hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget -> hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! FirstMI ) return true ; switch ( FirstMI -> getOpcode ( ) ) { case <STR_LIT> : return ( SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ( RegNo & <NUM_LIT> ) || RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand ::


<s> } else return reportParseError ( <STR_LIT> ) ; } else Save = getGPR ( Save ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; StringRef Name ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; unsigned GPReg = getGPR ( matchCPURegisterName ( <STR_LIT> ) ) ; if ( ! isN32 ( ) && ! isN64 ( ) ) return false ; MCStreamer & TS = getStreamer ( ) ; MCInst Inst ; if ( SaveIsReg ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Save ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( GPReg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getGPR ( <NUM_LIT> ) ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( GPReg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getGPR ( matchCPURegisterName ( <STR_LIT> ) ) ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Save ) ) ; } TS . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym -> getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym -> getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , getContext ( ) ) ; Inst . setOpcode (


<s> int eligible_for_return_delay ( rtx trial ) { rtx pat ; if ( GET_CODE ( trial ) != INSN || GET_CODE ( PATTERN ( trial ) ) != SET ) return <NUM_LIT> ; if ( get_attr_length ( trial ) != <NUM_LIT> ) return <NUM_LIT> ; if ( num_gfregs ) return <NUM_LIT> ; if ( current_function_calls_eh_return ) return <NUM_LIT> ; if ( sparc_leaf_function_p ) return get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ; pat = PATTERN ( trial ) ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= <NUM_LIT> && REGNO ( SET_DEST ( pat ) ) < <NUM_LIT> ) ) return <NUM_LIT> ; if ( REGNO ( SET_DEST ( pat ) ) >= <NUM_LIT> ) return ( TARGET_V9 && ! epilogue_renumber ( & pat , <NUM_LIT> ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) ; return eligible_for_restore_insn ( trial ,


<s> if ( JUMP_P ( insn ) && ! flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) return false ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) return false ; else return true ; } return false


<s> OutMI . addOperand ( LowerOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand ( <NUM_LIT>


<s> SDValue BC = DAG . getBitcast ( BCVT , Op0 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , HalfVT , BC ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Trunc , DAG . getUNDEF ( HalfVT ) ) ; } } if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , X , Op1 ) ; } } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Z = Op1 . getOperand ( <NUM_LIT> ) .


<s> return ( ( qword ) ( vec_mulo ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) (


<s> if ( cfun -> machine -> global_pointer > <NUM_LIT> ) REGNO ( pic_offset_table_rtx ) = cfun -> machine -> global_pointer ; size = compute_frame_size ( get_frame_size ( ) ) ; if ( ( cfun -> machine -> frame . mask | cfun -> machine -> frame . fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 ; step1 = MIN ( size , MIPS_MAX_FIRST_STACK_STEP ) ; RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ) ) = <NUM_LIT> ; size -= step1 ; mips_for_each_saved_reg ( size , mips_save_reg ) ; } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ) = <NUM_LIT> ; else { emit_move_insn ( MIPS_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( size ) ) ; if ( TARGET_MIPS16 ) { gcc_assert ( frame_pointer_needed ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_sub3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; } else emit_insn ( gen_sub3_insn ( stack_pointer_rtx , stack_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - size ) ) ) ; } } if ( frame_pointer_needed ) { if ( TARGET_MIPS16 && cfun -> machine -> frame . args_size != <NUM_LIT> ) { rtx offset = GEN_INT ( cfun -> machine -> frame . args_size ) ; if ( SMALL_OPERAND ( cfun -> machine -> frame . args_size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , offset ) ) ) = <NUM_LIT> ; else { emit_move_insn ( MIPS_PROLOGUE_TEMP ( Pmode ) , offset ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( stack_pointer_rtx , cfun ->


<s> if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI -> getMaxCallFrameSize ( ) ; NumBytes = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; if ( MFI -> getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = RoundUpToAlignment ( NumBytes , MFI -> getMaxAlignment ( ) ) ; } MFI -> setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA ,


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; MinSize = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false


<s> if ( T . isMacOSX ( ) && T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ; UseIntegratedAssembler =


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent ( ) ; return NextI ; } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . add ( StMO ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> hasUnscaledLdStOffset ( * LoadI ) ; assert ( IsUnscaled == TII -> hasUnscaledLdStOffset ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; Register DestReg = IsStoreXReg ? Register ( TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt ,


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { auto * Ld = cast < LoadSDNode > ( In ) ; if ( Ld -> isSimple ( ) ) { MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , VT . getVectorNumElements ( ) ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } } if ( Subtarget . hasAVX ( ) && N


<s> static __inline void si_stqa ( qword a , unsigned


<s> bool isNotSingleFloat ( ) const { return !


<s> switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>DAGToDAGISel :: SelectMVE_WB ( SDNode * N , const uint16_t * Opcodes , bool Predicated ) { SDLoc Loc ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; uint16_t Opcode ; switch ( N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : Opcode = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : Opcode = Opcodes


<s> vec_uchar16 tmp ; tmp = ( vec_uchar16 ) ( a ) ; tmp = vec_or ( tmp , vec_sld ( tmp , tmp , <NUM_LIT> ) ) ; tmp = vec_or ( tmp , vec_sld ( tmp , tmp ,


<s> CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ; OutStreamer -> EmitInstruction ( CallInst ,


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 || MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 && <STR_LIT> ( Imm ) < <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned s = <NUM_LIT> ; s != NumElts * <NUM_LIT> ; s += NumElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( NewImm % NumLaneElts + s + l ) ; NewImm /=


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else llvm_unreachable (


<s> const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> <ISA_LIT>MCAsmInfoGNUCOFF :: <ISA_LIT>MCAsmInfoGNUCOFF ( ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; Data16bitsDirective =


<s> __builtin_ia32_storedquhi128_mask ( ( short * ) __P , ( __v8hi


<s> unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister ( & <STR_LIT>


<s> SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget -> hasXMMInt ( ) , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl ,


<s> return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == <NUM_LIT>

&& ( alignOK || Memory . Alignment == <NUM_LIT> ) ;


<s> if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple .


<s> case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT> ) ; OffsetOpnd . setImm ( OffsetOpnd . getImm ( ) + LocalStackSize / Scale ) ; if ( NeedsWinCFI ) { * HasWinCFI = true ; auto MBBI = std :: next ( MachineBasicBlock :: iterator ( MI


<s> temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [


<s> return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT>


<s> unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( LATOpcode ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent (


<s> Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; Register ResultReg ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) -> getAlignment ( ) ) ) return false ; updateValueMap ( I , ResultReg ) ; return true


<s> PM -> add ( create<ISA_LIT>ISelDag (


<s> return ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return


<s> if ( ! isUInt < N > ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler


<s> Out . EmitBundleLock ( true ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock (


<s> static bool arm_cxx_cdtor_returns_this


<s> } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isGVInGOT ( GV ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else if ( MF . getTarget ( ) . isPositionIndependent ( ) )


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>leTarget ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y


<s> void <ISA_LIT>DAGToDAGISel :: SelectStoreLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT>


<s> arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = force_reg ( Pmode , expand_normal ( arg0 ) ) ; if ( ! target ) target = gen_reg_rtx ( Pmode ) ; else target = force_reg ( Pmode , target ) ; emit_move_insn ( target , op0 ) ; if ( fcode == AARCH64_PAUTH_BUILTIN_XPACLRI ) { rtx lr = gen_rtx_REG ( Pmode , R30_REGNUM ) ; icode = CODE_FOR_xpaclri ; emit_move_insn ( lr , op0 ) ; emit_insn ( GEN_FCN ( icode ) ( ) ) ; emit_move_insn ( target , lr ) ; } else { tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op1 = force_reg ( Pmode , expand_normal ( arg1 ) ) ; icode = ( fcode == AARCH64_PAUTH_BUILTIN_PACIA1716 ? CODE_FOR_paci1716 : CODE_FOR_auti1716 ) ; rtx x16_reg = gen_rtx_REG ( Pmode , R16_REGNUM ) ; rtx x17_reg = gen_rtx_REG ( Pmode


<s> Value * Cursor = II . getOperand ( <NUM_LIT> ) , * EarliestReplacement = nullptr ; const auto * IVTy = cast < VectorType > ( II . getType ( ) ) ; while ( Cursor ) { const auto * CursorVTy = cast < VectorType > ( Cursor -> getType ( ) ) ; if ( CursorVTy -> getElementCount ( ) . getKnownMinValue ( ) < IVTy -> getElementCount ( )


<s> HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b =


<s> case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern ::


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) ==


<s> if ( ! parseFpABIValue ( FpABI , <STR_LIT> ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT>


<s> MVT VecVT = Vec . getSimpleValueType ( ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , Elt ) ; if ( IdxVal ) EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , EltInVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return EltInVec ; return DAG . getNode ( <STR_LIT> , dl , VecVT ,


<s> static __inline qword si_fs ( qword a , qword


<s> case <STR_LIT> : { ConstantSDNode * Constant = dyn_cast < ConstantSDNode > ( Extend . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! Constant ) return <STR_LIT> ; uint32_t Mask = Constant -> getZExtValue ( ) ; if ( Mask == UCHAR_MAX ) return <STR_LIT> ; else if ( Mask == USHRT_MAX ) return <STR_LIT> ; else if ( Mask == UINT_MAX ) return <STR_LIT> ; return <STR_LIT> ; } default : return <STR_LIT> ; } llvm_unreachable (


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( ContextImmediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> ForCodeSize = MF . getFunction ( ) . hasOptSize ( ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> std :: string lowerCase = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex


<s> break ; } MCOperand RegLR = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegS0 = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegS12 = MCOperand :: createReg ( <STR_LIT> ) ; MCSymbol * GetTLSLabel = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; MCOperand cim24 = MCOperand :: createImm ( - <NUM_LIT> ) ; MCOperand loImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO32 , AddrSym , OutContext ) ; emitLEAzii ( * OutStreamer , cim24 , loImm , RegS0 , STI ) ; MCOperand ci32 = MCOperand :: createImm ( <NUM_LIT> ) ; emitANDrm0 ( * OutStreamer , RegS0 , ci32 , RegS0 , STI ) ; emitSIC ( * OutStreamer , RegLR , STI ) ; MCOperand hiImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI32 , AddrSym , OutContext ) ; emitLEASLrri ( * OutStreamer , RegS0 , RegLR , hiImm , RegS0 , STI ) ; MCOperand ci8 = MCOperand :: createImm ( <NUM_LIT> ) ; MCOperand loImm2 = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 , GetTLSLabel , OutContext ) ; emitLEAzii ( * OutStreamer , ci8 , loImm2 , RegS12 , STI ) ; emitANDrm0 ( * OutStreamer , RegS12 , ci32 , RegS12 ,


<s> bool <ISA_LIT>FastISel :: SelectSelect ( const Instruction * I ) { MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned CondReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; int Imm = <NUM_LIT> ; bool UseImm = false ; bool isNegativeImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; Imm = ( int ) ConstInt -> getValue ( ) . getZExtValue ( ) ; if ( Imm < <NUM_LIT> ) { isNegativeImm = true ; Imm = ~ Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm ) { Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; } unsigned CmpOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CondReg = constrainOperandRegClass ( TII . get ( CmpOpc ) , CondReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; if ( ! UseImm ) { Op2Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op2Reg , <NUM_LIT> ) ; Op1Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op1Reg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op2Reg ) . addReg ( Op1Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { Op1Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op1Reg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , ResultReg ) . addReg

( Op1Reg ) . addImm ( Imm ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ <STR_LIT> ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; <ISA_LIT>ELFStreamer & MEF = static_cast < <ISA_LIT>ELFStreamer & > ( Streamer ) ; MEF . Emit<ISA_LIT>OptionRecords ( )


<s> if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; if ( can_issue_more == issue_rate - <NUM_LIT> ) end = false ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } n_nops -- ; } can_issue_more ++ ; * group_end = ( end || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p


<s> return Res ; } if ( Kind == MCExpr :: SymbolRef ) { <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : FixupKind = <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT>


<s> if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> return getSTI ( ) . getFeatureBits (


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL ,


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! EnableBasePointer ) return false ; if ( needsStackRealignment ( MF ) && ( MFI -> hasVarSizedObjects ( ) || !

TFI -> hasReservedCallFrame ( MF ) ) ) return true ;


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( getLdStRegOp ( MI ) . getReg ( ) == BaseReg && getLdStBaseOp ( MI ) . getReg ( ) == BaseReg && getLdStOffsetOp ( MI ) . getImm ( ) <= <NUM_LIT> && getLdStOffsetOp ( MI ) . getImm ( ) >= - <NUM_LIT> ) { if ( ! Offset || Offset == MI -> getOperand ( <NUM_LIT> ) .


<s> if ( Disp . getImm ( ) != <NUM_LIT> ) O << Disp . getImm ( ) ; } if ( Base . getReg ( ) ) O << '[' << getRegisterName ( Base . getReg ( ) )


<s> int NumV2Inputs = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , isV2 ) ; if ( NumV2Inputs == <NUM_LIT> ) return lowerV8I16SingleInputVectorShuffle ( DL , V1 , Mask , Subtarget , DAG ) ; assert ( NumV1Inputs > <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( Subtarget -> hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Rotate ; if ( NumV1Inputs + NumV2Inputs <= <NUM_LIT> ) return lowerV8I16BasicBlendVectorShuffle ( DL , V1 , V2 , Mask , Subtarget , DAG ) ; if ( shouldLowerAsInterleaving ( Mask ) ) { int EMask [ <NUM_LIT> ] , OMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { EMask [ i ] = Mask [ <NUM_LIT> * i ] ; OMask [ i ] = Mask [ <NUM_LIT> * i + <NUM_LIT> ] ; EMask [ i + <NUM_LIT> ] = - <NUM_LIT> ; OMask [ i + <NUM_LIT> ] = - <NUM_LIT> ; } SDValue Evens = DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , EMask ) ; SDValue Odds = DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , OMask ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Evens , Odds ) ; } int LoBlendMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiBlendMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { LoBlendMask [ i ] = Mask [ i ] ; HiBlendMask [ i ] = Mask [


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( MachineRegisterInfo :: reg_iterator ri = MRI . reg_begin ( <STR_LIT> ) , re = MRI . reg_end ( ) ; ri != re ; ++ ri ) if ( ri -> isCopy ( ) ) return true ; return false


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr


<s> if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER )


<s> case FpABIKind :: ANY : return Val_GNU_MIPS_ABI_FP_ANY ; case FpABIKind :: XX : return Val_GNU_MIPS_ABI_FP_XX ; case FpABIKind


<s> if ( C2 > ElemSizeInBits ) return SDValue ( ) ; unsigned ElemMask = ( <NUM_LIT> << ElemSizeInBits ) - <NUM_LIT> ; if ( ( C1 & ElemMask ) != ( ~ C2 & ElemMask ) ) return SDValue ( ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; SDValue Y = Shift . getOperand ( <NUM_LIT> ) ; unsigned Intrin = IsShiftRight ? <STR_LIT> : <STR_LIT> ; SDValue ResultSLI = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Intrin , DL , <STR_LIT> ) , X , Y , Shift . getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> )


<s> else { while ( GET_CODE ( x ) == SUBREG ) { off += subreg_regno_offset ( REGNO ( SUBREG_REG ( x ) ) , GET_MODE ( SUBREG_REG ( x ) ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) ; x = SUBREG_REG ( x ) ; } if ( GET_CODE ( x ) == REG ) regno = REGNO ( x ) + off ; } } else if ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( rclass == HILO_REGS && ! CSKY_GENERAL_REGNO_P ( regno ) ) return GENERAL_REGS ; if ( rclass == V_REGS && ! CSKY_GENERAL_REGNO_P (


<s> bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> case IES_OR : case IES_XOR : case IES_AND : case IES_EQ : case IES_NE : case IES_LT : case IES_LE : case IES_GT : case IES_GE : case IES_LSHIFT : case IES_RSHIFT : case IES_DIVIDE : case IES_MOD : case IES_MULTIPLY : case IES_LPAREN : case IES_INIT : case IES_LBRAC : State = IES_INTEGER ; if ( PrevState == IES_REGISTER


<s> if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; } else { int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) EmitAlignment ( <NUM_LIT> ) ; printInstruction ( MI )


<s> O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << MO2 . getImm ( ) * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup


<s> bool IsKnown ( ) const { return ThisABI !=


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT>


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget ( ) ) , TII ( * TM

. getSubtargetImpl ( ) -> getInstrInfo ( ) ) , TLI ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( ZeroReg ) MIB . addReg ( ZeroReg ) ; if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState


<s> SDLoc DL ( Op ) ; EVT Ty = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue (


<s> return ( vector unsigned char ) __builtin_altivec_vsrab ( ( vector signed char ) a1 ,


<s> if ( ST -> isSwift ( ) && Opcode == Instruction :: InsertElement && ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( )


<s> if ( ! ST -> hasDSP ( ) || ! EnableDSP || ! isSupportedType ( I ) ) return false ; if ( ST -> isThumb ( ) && ! ST -> hasThumb2 ( ) ) return false ; if ( I -> getOpcode ( ) != Instruction :: Add && I -> getOpcode ( ) != Instruction :: Sub ) return false ; for ( auto & Op : I -> operands ( ) ) { if ( isa < Constant > ( Op ) ) { if ( ! EnableDSPWithImms ) return false ; } } return true


<s> SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == Release ) { Domain = <STR_LIT>


<s> case <STR_LIT> : Is64Bit = <NUM_LIT> ; CC = <STR_LIT> ; break ; case <STR_LIT> : Is64Bit = <NUM_LIT> ; CC = <STR_LIT> ; break ; } unsigned SrcReg = Cond [ <NUM_LIT> ] . getReg ( ) ; if ( Is64Bit ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } else { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } break ; } case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = &


<s> case <STR_LIT> : ScaleFactor = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ScaleFactor = <NUM_LIT> ; break ; } bool UseScaled = true ; if ( ( Addr . getOffset ( ) < <NUM_LIT> ) || ( Addr . getOffset ( ) & ( ScaleFactor - <NUM_LIT> ) ) ) { UseScaled = false ; ScaleFactor = <NUM_LIT> ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ]


<s> return MaskBit ? <STR_LIT> ( ITState . Cond


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = MFI . CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_F64 : RTLIB :: SINCOS_F32 ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol (


<s> Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; unsigned char OpFlags = <NUM_LIT> ; if ( Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) OpFlags = <STR_LIT> ; if ( isThumb2 ) AddDefaultPred ( MIB ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress ( GV ,


<s> SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ; SDValue Offset ; switch ( model ) { case TLSModel :: GeneralDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; break ; } case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; break ; } case TLSModel :: LocalExec : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcSV = Op . getOperand ( <NUM_LIT> ) ; assert ( <NUM_LIT> && <STR_LIT> )


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI


<s> Value &= ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Value + Offset ) ) ; return MCDisassembler


<s> else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand


<s> } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data ( ) ) , Opcodes . size ( ) ) ) ; } SwitchSection ( & FnStart -> getSection ( ) ) ; Reset (


<s> f_hi = expand_binop ( SImode , lshr_optab , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; f_lo = expand_binop ( SImode , and_optab , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; chain = force_operand ( chain , NULL ) ; c_hi = expand_binop ( SImode , lshr_optab , chain , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; c_lo = expand_binop ( SImode , and_optab , chain , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , f_hi , gen_int_mode ( movhi_r13 , SImode ) , f_hi , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , c_hi , gen_int_mode ( movhi_r11 , SImode ) , c_hi , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , f_lo , gen_int_mode ( ori_r13_r13 , SImode ) , f_lo , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , c_lo , gen_int_mode ( ori_r11_r11 , SImode ) , c_lo , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = gen_int_mode ( jr_r13 , SImode ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { rtx mem = adjust_address ( m_tramp , SImode , i * <NUM_LIT> ) ; emit_move_insn ( mem , tramp [


<s> NewMBB -> transferSuccessors ( ThisMBB ) ; ThisMBB -> addSuccessor ( NewBRTarget , ProbToNewTarget ) ; ThisMBB -> addSuccessor ( NewMBB , ProbToNewTarget . getCompl ( ) ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( NewBROpcode ) ) . addReg ( BSI . SplitCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewBRTarget ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewMBB ) ; if ( BSI . MIToDelete ) BSI . MIToDelete -> eraseFromParent ( ) ; auto FirstTerminator = NewMBB -> getFirstTerminator ( ) ; if ( BSI . NewCond ) { assert ( FirstTerminator -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; FirstTerminator -> getOperand ( <NUM_LIT> ) . setReg ( BSI . NewCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( BSI . InvertOrigBranch ) FirstTerminator -> setDesc ( TII -> get ( InvertedOpcode ) ) ; for ( auto * Succ : NewMBB -> successors ( ) ) { updatePHIs ( Succ , ThisMBB , NewMBB , MRI ) ; } addIncomingValuesToPHIs ( NewBRTarget , ThisMBB , NewMBB , MRI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ThisMBB -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewMBB -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewBRTarget -> dump ( ) ) ; return


<s> case <STR_LIT> : return LowerCTPOP ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerAtomicArith ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , Subtarget , DAG ) ; case <STR_LIT> : return lowerVectorShuffle ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerExtendedLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op


<s> CodePointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling :: WinEH ; } else { ExceptionsType = ExceptionHandling :: DwarfCFI ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; AllowAtInName = true ; UseIntegratedAssembler = true


<s> emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow )


<s> if ( __builtin_expect ( __builtin_tbegin ( <NUM_LIT> ) ,

<NUM_LIT> ) ) return _HTM_TBEGIN_STARTED ;


<s> else output_asm_insn ( <STR_LIT> , low ) ; return <STR_LIT> ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( low [ <NUM_LIT> ] == const0_rtx ) pattern = <NUM_LIT> , carry = <NUM_LIT> ; else if ( low [ <NUM_LIT> ] == constm1_rtx ) pattern = <STR_LIT> ; else pattern = <STR_LIT> ; } else { if ( low [ <NUM_LIT> ] == constm1_rtx ) pattern = <STR_LIT> ; else if ( low [ <NUM_LIT> ] == const0_rtx ) pattern = get_insn_template ( CODE_FOR_movsi , insn ) , carry = <NUM_LIT> ; else pattern = <STR_LIT> ; } if ( pattern ) output_asm_insn ( pattern , low ) ; if ( carry ) { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; return <STR_LIT> ; } return get_insn_template ( CODE_FOR_subsi3 , insn ) ; } default : gcc_unreachable (


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; high = ( highp ? <NUM_LIT> : nelt / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 ,


<s> if ( ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> ) { if ( A ) { const MCSymbol & Sym = A -> getSymbol ( ) ; if ( Asm . isThumbFunc ( & Sym ) ) Value |= <NUM_LIT> ; } } if ( A && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { const MCSymbol & Sym = A -> getSymbol (


<s> unsigned getFirstDomain ( ) const { return CountTrailingZeros_32 ( AvailableDomains


<s> LLVM_DEBUG ( dumpCurrGroup ( <STR_LIT> ) ) ; LLVM_DEBUG ( CurGroupDbg = <STR_LIT> ; ) ; GrpCount ++ ; CurrGroupSize = <NUM_LIT> ; CurrGroupHas4RegOps = false ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ; if ( CriticalResourceIdx != UINT_MAX && ( ProcResourceCounters [ CriticalResourceIdx ] <= ProcResCostLim ) ) CriticalResourceIdx = UINT_MAX ; LLVM_DEBUG ( dumpState ( )


<s> Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , SP ) ; SDValue Ops [ <NUM_LIT> ] = { SP , Chain } ; return DAG . getMergeValues ( Ops , DL ) ; } SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Chain , Flag ) ; SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { NewSP , Chain


<s> switch ( get_attr_type ( insn ) ) { case TYPE_DIV : case TYPE_SDIV : case TYPE_DDIV : case TYPE_VECDIV : case TYPE_SSQRT : case TYPE_DSQRT : return false ; default : return


<s> bool <ISA_LIT>ElimCompare :: optimizeCompareZero ( MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { if ( ! isCompareZero ( Compare ) ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock & MBB = * Compare . getParent ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = MBB . begin ( ) ; Reference CCRefs ; Reference SrcRefs ; while ( MBBI != MBBE ) { -- MBBI ; MachineInstr & MI = * MBBI ; if ( resultTests ( MI , SrcReg ) ) { if ( ! CCRefs . Use && ! SrcRefs ) { if ( convertToBRCT ( MI , Compare , CCUsers ) ) { BranchOnCounts += <NUM_LIT> ; return true ; } if ( convertToLoadAndTrap ( MI , Compare , CCUsers ) ) { LoadAndTraps += <NUM_LIT> ; return true ; } } if ( ( ! CCRefs && convertToLoadAndTest ( MI , Compare , CCUsers ) ) || ( ! CCRefs . Def && adjustCCMasksForInstr ( MI , Compare , CCUsers ) ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) break ; CCRefs |= getRegReferences ( MI , <STR_LIT> ) ; if ( CCRefs . Use && CCRefs . Def ) break ; } MBBI = Compare , MBBE = MBB . end ( ) ; while ( ++ MBBI != MBBE ) { MachineInstr & MI = * MBBI ; if ( preservesValueOf ( MI , SrcReg ) ) { if ( convertToLoadAndTest ( MI , Compare , CCUsers ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } if ( getRegReferences ( MI , SrcReg ) . Def ) return false ; if ( getRegReferences ( MI , <STR_LIT> )


<s> static bool isLegalMaskCompare ( SDNode * N , const <ISA_LIT>Subtarget * Subtarget ) { unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return


<s> static __inline vec_double2 spu_slqwbyte ( vec_double2 a , unsigned int count


<s> setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setMinFunctionAlignment ( Align ( <NUM_LIT> ) ) ; setMinStackArgumentAlignment ( Align (


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>3 (


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( <STR_LIT> ) : ( <STR_LIT>


<s> vec_mode = mode ; imode = SImode ; break ; case E_V8DImode : case E_V4DImode : case E_V2DImode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : vec_mode = mode ; imode = DImode ; break ; case E_TImode : case E_TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - <NUM_LIT> , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode


<s> static void mips_set_architecture ( const struct mips_cpu_info * info


<s> SmallVector < RegDomain , <NUM_LIT> > getLegalDstDomains ( ) const { return


<s> for ( i = probe_interval ; i < size ; i += probe_interval ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { gcc_assert ( int_registers_saved ) ; HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , probe_interval ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( gen_probe_stack_range ( Pmode , sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx

, sr . reg ) , rounded_size - size ) ) ;


<s> rtx unspec = NULL_RTX ; rtx mem , addr , base , insn ; unsigned int align ; addr = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( mode , addr ) ; align = MIN ( GET_MODE_ALIGNMENT ( mode ) , INCOMING_STACK_BOUNDARY ) ; set_mem_align ( mem , align ) ; if ( mode == V4SFmode && align < <NUM_LIT> ) unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_STOREU ) ; insn = emit_insn ( gen_rtx_SET ( mem , unspec ? unspec : reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } } else if ( base != m -> fs . cfa_reg


<s> bool <ISA_LIT>BlockPlacement :: blockIsBefore ( MachineBasicBlock * BB , MachineBasicBlock * Other ) { return BBUtils -> getOffsetOf ( Other ) > BBUtils -> getOffsetOf ( BB


<s> Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType


<s> if ( ! Check ( S , DestRegDecoder ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DestRegDecoder ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DestRegDecoder ( Inst , Vn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) )


<s> bool FixupLEAPass :: fixupIncDec ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) const { MachineInstr & MI = * I ; int Opcode = MI . getOpcode ( ) ; if ( ! isLEA ( Opcode ) ) return false ; if ( isLEASimpleIncOrDec ( MI ) && TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) { int NewOpcode ; bool isINC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; switch ( Opcode ) { case <STR_LIT> : NewOpcode = isINC ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NewOpcode = isINC ? <STR_LIT>


<s> SelectAndParts32 ( dl , Res , InstCnt ) ; if ( ( ! HasZeros || LateMask ) && ! Res ) { ValueRotInfo & VRI = ValueRotsVec [ <NUM_LIT> ] ; if ( VRI . RLAmt ) { if ( InstCnt ) * InstCnt += <NUM_LIT> ; SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { Res = VRI . V ; } for ( auto I = BitGroups . begin ( ) ; I != BitGroups . end ( ) ; ) { if ( I -> V == VRI . V && I -> RLAmt == VRI . RLAmt ) I = BitGroups . erase ( I ) ; else ++ I ; } } if ( InstCnt ) * InstCnt += BitGroups . size ( ) ; for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { BG . V , getI32Imm ( BG . RLAmt ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , BG . V , getI32Imm ( BG . RLAmt ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } } if ( LateMask ) { unsigned Mask = ( unsigned ) getZerosMask ( ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal


<s> ScaledMask . assign ( static_cast < size_t > ( NumElts * Scale ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { for ( int s = <NUM_LIT> ; s != Scale ; ++ s ) ScaledMask [ ( Scale * i ) + s ] = M ; continue ; } for ( int s = <NUM_LIT> ; s != Scale ; ++ s ) ScaledMask [ ( Scale * i ) +


<s> bool ExpandPseudo :: expandInstr ( MachineBasicBlock & MBB , Iter I ) { switch ( I -> getOpcode ( ) ) { case <STR_LIT> : expandLoadCCond ( MBB , I ) ; break ; case <STR_LIT> : expandStoreCCond ( MBB , I ) ; break ; case <STR_LIT> : case <STR_LIT> : expandLoadACC ( MBB ,


<s> static bool isPrefix ( const MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> const auto & FGR64RegClass = TRI -> getRegClass ( <STR_LIT> ) ; unsigned Fc2 = RegInfo . createVirtualRegister ( FGR64RegClass ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , Fc2 ) . addImm ( <NUM_LIT> ) . addReg ( Fc ) . addImm ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( Fc2


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB


<s> static SDValue performUnpackCombine ( SDNode * N , SelectionDAG & DAG ) { assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return DAG . getUNDEF ( N -> getValueType ( <NUM_LIT> ) ) ; return SDValue (


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return <STR_LIT>


<s> break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering


<s> static rtx ix86_internal_arg_pointer ( void ) { return virtual_incoming_args_rtx


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && ! aarch64_vect_struct_mode_p ( mode ) ) return <NUM_LIT> ; if ( FP_REGNUM_P ( regno ) ) { if ( aarch64_vect_struct_mode_p ( mode ) ) return ( regno + aarch64_hard_regno_nregs ( regno , mode ) - <NUM_LIT> ) <= V31_REGNUM ; else return <NUM_LIT> ; } return <NUM_LIT>


<s> MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( SDValue ( CmpSwap ,


<s> unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val < NumElems ) MaskVec . push_back ( DAG . getConstant ( Val + NumElems , EltVT ) ) ; else MaskVec . push_back ( DAG . getConstant ( Val - NumElems , EltVT ) ) ; } return DAG . getNode ( <STR_LIT> , dl , MaskVT ,


<s> } if ( PInfo . HighLatencyCPSR ) { HighLatencyCPSR = true ; break ; } } bool IsSelfLoop = MBB . isSuccessor ( & MBB ) ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = std :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) ) { BundleMI = MI ; continue ; } if ( MI -> isDebugInstr ( ) ) continue ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; bool NextInSameBundle = NextMII != E && NextMII -> isBundledWithPred ( ) ; if ( ReduceMI ( MBB , MI , LiveCPSR , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = std :: prev ( NextMII ) ; MI = & * I ; if ( NextInSameBundle && ! NextMII -> isBundledWithPred ( ) ) NextMII -> bundleWithPred ( ) ; } if ( BundleMI && ! NextInSameBundle && MI -> isInsideBundle ( ) ) { if ( BundleMI -> killsRegister ( <STR_LIT> ) ) LiveCPSR = false ; MachineOperand * MO = BundleMI -> findRegisterDefOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isDead ( ) ) LiveCPSR = true ; MO = BundleMI -> findRegisterUseOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isKill ( ) ) LiveCPSR = true ; } bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> isCall ( ) ) { CPSRDef = nullptr ; HighLatencyCPSR = false ; IsSelfLoop = false ; } else if ( DefCPSR ) { CPSRDef = MI ; HighLatencyCPSR = isHighLatencyCPSR ( CPSRDef ) ; IsSelfLoop = false ; } } MBBInfo & Info = BlockInfo [ MBB . getNumber ( ) ] ; Info . HighLatencyCPSR = HighLatencyCPSR ; Info . Visited


<s> getSORegRegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Binary = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO .


<s> static rtx rs6000_expand_set_fpscr_drn_builtin ( enum insn_code icode , tree exp ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( TARGET_32BIT ) fatal_error ( input_location , <STR_LIT> <STR_LIT>


<s> static DecodeStatus DecodeLoadI64 ( MCInst & Inst , uint64_t insn

, uint64_t Address , const MCDisassembler * Decoder ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( )


<s> if ( args_so_farp -> regs + <NUM_LIT> < MMIX_MAX_ARGS_IN_REGS ) * pretend_sizep = ( MMIX_MAX_ARGS_IN_REGS - ( args_so_farp -> regs + <NUM_LIT> ) ) * <NUM_LIT> ; if ( ( <NUM_LIT> + ( MMIX_FUNCTION_ARG_SIZE ( mode , vartype ) ) ) / <NUM_LIT> !=


<s> if ( ! isIndirect ) return getSymbol ( GV ) ; MCSymbol * MCSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry


<s> static unsigned <ISA_LIT>ChooseCmpImmediateOpcode ( EVT VT , const ConstantInt * RHSC ) { switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> vqtbx4_p8 ( poly8x8_t r , poly8x16x4_t tab , uint8x8_t idx ) { __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT>


<s> CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; Constant * C0 = ConstantVector :: get ( CV0 ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue XR2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , XR1 , XR2 ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Unpck2 = getUnpackl ( DAG , dl , <STR_LIT> , Unpck1 , CLod0 ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck2 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; int ShufMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; SDValue Shuf = DAG . getVectorShuffle ( <STR_LIT> , dl , Sub , DAG . getUNDEF ( <STR_LIT> ) , ShufMask ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl ,


<s> inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI , int Offset = <NUM_LIT> , bool mem = true ) { if ( mem ) return MIB . addImm ( Offset ) . addFrameIndex ( FI ) ; else return MIB . addFrameIndex ( FI )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; int64_t Shift =


<s> emit_move_insn ( op0 , op1 ) ; for ( insn = get_last_insn ( ) ; insn != first ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) ) PATTERN (

insn ) = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , PATTERN ( insn ) ) ;


<s> rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = const_double_from_real_value ( r_pow , DFmode


<s> SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , <STR_LIT> , dl , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Add ,

DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> return ( ( val & ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << <NUM_LIT> ) ) == val || ( val & ( ( (

HOST_WIDE_INT ) <NUM_LIT> ) << <NUM_LIT> ) ) == val ) ;


<s> fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; ASM_OUTPUT_ALIGN ( asm_out_file , <NUM_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , <STR_LIT> ) ; recurse = <NUM_LIT> ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , <NUM_LIT> ) [ <NUM_LIT> ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , <NUM_LIT> ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , <STR_LIT> , name ) ; return true


<s> MCSymbol * <ISA_LIT>AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ <NUM_LIT> ] ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix

( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;