<s> if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getConstant ( ByteRotation , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ByteVT == <STR_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - ByteRotation ; int HiByteShift = ByteRotation ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( HiByteShift , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoShift , HiShift


<s> const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI -> getMF ( ) -> getSubtarget ( ) ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( )

&& MMO -> getAlign ( ) < MMO -> getSize ( ) ) ) return true ;


<s> unsigned HOST_WIDE_INT offset ; unsigned int extra ; if ( GET_CODE ( x ) != PLUS ) return false ; if ( ! REG_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; if ( ! INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return false ; if ( mode_supports_vsx_dform_quad ( mode ) ) return quad_address_p ( x , mode , strict ) ; if ( ! reg_offset_addressing_ok_p ( mode ) ) return virtual_stack_registers_memory_p ( x ) ; if ( legitimate_constant_pool_address_p ( x , mode , strict || lra_in_progress ) ) return true ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; extra = <NUM_LIT> ; switch ( mode ) { case E_V2SImode : case E_V2SFmode : return false ; case E_DFmode : case E_DDmode : case E_DImode : if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; case E_TFmode : case E_IFmode : case E_KFmode : case E_TDmode : case E_TImode : case E_PTImode : extra = <NUM_LIT> ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; default : break ; } offset += <NUM_LIT> ; return offset < <NUM_LIT> -


<s> const bool IsReduction = RecurrenceDescriptor :: AddReductionVar ( & Phi , RecurrenceDescriptor :: RK_IntegerAdd , TheLoop , HasFnNoNaNAttr , RecDesc ) ; if ( ! IsReduction ) continue ; Instruction * Acc = dyn_cast < Instruction > ( Phi . getIncomingValueForBlock ( Latch ) ) ; if ( ! Acc ) continue ; Reductions . push_back ( Reduction ( & Phi , Acc ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto R : Reductions ) { dbgs ( ) << <STR_LIT> ; R . Phi -> dump ( ) ; dbgs ( ) << <STR_LIT> ; R . AccIntAdd -> dump ( ) ; } ) ; return Reductions


<s> return create<ISA_LIT>MachObjectWriter ( OS , false , MachO :: CPU_TYPE_<ISA_LIT> ,


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O


<s> void <ISA_LIT>TargetELFStreamer :: emitArchDefaultAttributes ( ) { using namespace <ISA_LIT>BuildAttrs ; <ISA_LIT>ELFStreamer & S = getStreamer ( ) ; S . setAttributeItem ( CPU_name , <STR_LIT> ( Arch ) , false ) ; if ( EmittedArch == <STR_LIT> :: INVALID ) S . setAttributeItem ( CPU_arch , <STR_LIT> ( Arch ) , false ) ; else S . setAttributeItem ( CPU_arch , <STR_LIT> ( EmittedArch ) , false ) ; switch ( Arch ) { case <STR_LIT> :: <ISA_LIT>V2 : case <STR_LIT> :: <ISA_LIT>V2A : case <STR_LIT> :: <ISA_LIT>V3 : case <STR_LIT> :: <ISA_LIT>V3M : case <STR_LIT> :: <ISA_LIT>V4 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V4T : case <STR_LIT> :: <ISA_LIT>V5T : case <STR_LIT> :: XSCALE : case <STR_LIT> :: <ISA_LIT>V5TE : case <STR_LIT> :: <ISA_LIT>V6 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6T2 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6K : case <STR_LIT> :: <ISA_LIT>V6KZ : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; S . setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6M : S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7A : S . setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7R : S . setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7EM : case <STR_LIT> :: <ISA_LIT>V7M : S . setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; S . setAttributeItem ( THUMB_ISA_use ,


<s> I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( ! Subtarget . hasFPExtension ( ) ) setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget . hasFPExtension ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> ,


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , (


<s> unsigned int found_flags = initial_state ; while ( ( ntoken = strchr ( specs , separator ) ) ) { size_t token_length = ntoken - specs ; unsigned token_ops = aarch64_parse_one_option_token ( specs , token_length , flags , option_name ) ; if ( ! token_ops )


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue LowV = V1 , HighV = V2 ; int NewMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] } ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( NumV2Elements == <NUM_LIT> ) { int V2Index = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) - Mask . begin ( ) ; int V2AdjIndex = V2Index ^ <NUM_LIT> ; if ( Mask [ V2AdjIndex ] == - <NUM_LIT> ) { if ( V2Index < <NUM_LIT> ) std :: swap ( LowV , HighV ) ; NewMask [ V2Index ] -= <NUM_LIT> ; } else { int V1Index = V2AdjIndex ; int BlendMask [ <NUM_LIT> ] = { Mask [ V2Index ] - <NUM_LIT> , <NUM_LIT> , Mask [ V1Index ] , <NUM_LIT> } ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask


<s> BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveThumb ( SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; return


<s> reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>16 ( ) ; Parser . Lex


<s> psllh_u ( uint16x4_t s , uint8_t amount ) { return __builtin_loongson_psllh_u ( s ,


<s> void emitDefCFAOffsets ( MachineBasicBlock & MBB , const DebugLoc & dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset += Info . SPAdjust ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , std :: next ( Info . I ) , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex

) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> static MCTargetStreamer * createObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { return new <ISA_LIT>TargetELFStreamer ( S


<s> if ( ! MF . hasEHFunclets ( ) ) return ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; if ( MBBI -> isTerminator ( ) ) return ; int UnwindHelpFI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; DebugLoc DL ; RS -> enterBasicBlock ( MBB ) ; unsigned DstReg = RS -> scavengeRegister ( & <STR_LIT> , MBBI , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , DstReg ) .


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , <NUM_LIT> ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO


<s> CpDef = Copy ; if ( ! Copy -> isCopy ( ) ) return Copy ; unsigned CopySrc = Copy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Subreg = Copy -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrc ) ) { const TargetRegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg


<s> if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( ) && ! DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl ,


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ; PassRegistry & PR = * PassRegistry ::


<s> cbranch_trace ( rtx_insn * insn ) : cbranch_insn ( insn ) , condition_rtx_in_insn ( NULL ) , cbranch_type ( unknown_branch_condition ) , setcc ( ) { if ( is_conditional_insn ( cbranch_insn ) ) condition_rtx_in_insn = & XEXP ( XEXP ( PATTERN ( cbranch_insn ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( rtx x = pc_set ( cbranch_insn ) ) condition_rtx_in_insn = & XEXP ( XEXP ( x


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) ,


<s> static bool needsFP ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> gcc_assert ( TARGET_OLDABI ) ; if ( from_fp_p ) s = <STR_LIT> ; else s = <STR_LIT> ; gparg = GP_ARG_FIRST ; fparg = FP_ARG_FIRST ; for ( f = ( unsigned int ) fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) { if ( ( fparg & <NUM_LIT> ) != <NUM_LIT> ) ++ fparg ; fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg ] ) ; } else if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) { if ( TARGET_64BIT ) fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg ] ) ; else { if ( ( fparg & <NUM_LIT> ) != <NUM_LIT> ) ++ fparg ; if ( TARGET_BIG_ENDIAN ) fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg + <NUM_LIT> ] , s , reg_names [ gparg + <NUM_LIT> ] , reg_names [ fparg ] ) ; else fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg ] , s , reg_names [ gparg + <NUM_LIT> ] , reg_names [ fparg + <NUM_LIT> ] ) ; ++


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> void * ptr ; if ( alignment == malloc_align && alignment == vec_align ) return malloc ( size ) ; if ( alignment < vec_align ) alignment = vec_align ; if ( posix_memalign ( & ptr , alignment , size ) == <NUM_LIT> ) return ptr ; else return


<s> } void erase ( const Node & N ) { size_type Idx = G . getNodeIndex ( N ) ; V . reset ( Idx ) ; } bool contains ( const Node & N ) const { size_type Idx = G . getNodeIndex ( N ) ; return V . test


<s> static __inline __m64 _mm_set1_pi8 ( char __b ) { unsigned int __w = ( unsigned char ) __b << <NUM_LIT> | ( unsigned char ) __b ; unsigned int __i = __w << <NUM_LIT> | __w ; return _mm_set1_pi32 ( __i )


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; unsigned NumElems = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; return true


<s> for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : Changed = visitAND < uint32_t > ( <STR_LIT> , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitAND < uint64_t > ( <STR_LIT> , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitORR ( MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSUB < uint32_t > ( <STR_LIT> , <STR_LIT> , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSUB < uint32_t > ( <STR_LIT> , <STR_LIT> , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSUB < uint64_t > ( <STR_LIT> , <STR_LIT> , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSUB < uint64_t > ( <STR_LIT> , <STR_LIT> , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSSUBS < uint32_t > ( { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSSUBS < uint32_t > ( { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSSUBS < uint64_t > ( { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitADDSSUBS < uint64_t > ( { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT>


<s> return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : if ( LT . second != <STR_LIT> ) return ( Cost + <NUM_LIT> ) * LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Cost + <NUM_LIT> ) * LT . first ; case <STR_LIT> : if ( isa < FixedVectorType > ( Ty ) && ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Cost + <NUM_LIT> ) * LT . first ; return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty ,


<s> TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> bool SelectAddrIdx ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Index ) { return <ISA_LIT>Lowering . SelectAddressRegReg ( N , Base , Index , *


<s> case <STR_LIT> : return lowerAnd ( Op , DAG ) ; case <STR_LIT> : return lowerOr ( Op , DAG ) ; case <STR_LIT> : return lowerXor ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case


<s> return getSchedModel ( ) . hasInstrSchedModel (


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv4hi ( ( int16x4_t


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( ! ( Subtarget . hasSSE2 ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) && ! ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . useBWIRegs ( ) && ( VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue SubusLHS , SubusRHS ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SubusRHS = Op1 ; SDValue MaxLHS = Op0 . getOperand ( <NUM_LIT> ) ; SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT TruncVT = Op1 . getOperand ( <NUM_LIT>


<s> static DecodeStatus DecodeVecShiftR8Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm


<s> bool isSub = Opc == sub ; return Imm12 | ( ( int ) isSub << <NUM_LIT> ) |

( SO << <NUM_LIT> ) | ( IdxMode << <NUM_LIT> ) ;


<s> return mode == DFmode ? mips_cost -> fp_mult_df


<s> int local_regparm , globals = <NUM_LIT> , regno ; for ( local_regparm = <NUM_LIT> ; local_regparm < <NUM_LIT> ; local_regparm ++ ) if ( global_regs [ local_regparm ] ) break ; if ( local_regparm == <NUM_LIT> && decl_function_context ( decl ) && ! DECL_NO_STATIC_CHAIN ( decl ) ) local_regparm = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; regno ++ ) if ( global_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : <NUM_LIT> ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm


<s> right -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = right ; else if ( node == node -> par -> left ) node -> par -> left


<s> DestReg1 = TRI . getSubReg ( DestReg , SubIdx1 ) ; SubIdx1 = <NUM_LIT> ; IsUndef = false ; } BuildMI ( MBB , InsertBefore , DebugLoc ( ) , MCID ) . addReg ( DestReg0 , RegState :: Define | getUndefRegState ( IsUndef ) , SubIdx0 ) . addReg ( DestReg1 , RegState ::

Define | getUndefRegState ( IsUndef ) , SubIdx1 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> for ( unsigned i = <NUM_LIT> , e = SrcVT . getVectorNumElements ( ) ; i != e ; ++ i ) { SDValue Op = N0 . getOperand ( i ) ; LowUndef &= Op . isUndef ( ) || ( i >= e / <NUM_LIT> ) ; AllUndefOrZero &= ( Op . isUndef ( ) || isNullConstant ( Op ) ) ; } if ( AllUndefOrZero ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc dl ( N00 ) ; N00 = LowUndef ? DAG . getAnyExtOrTrunc ( N00 , dl , <STR_LIT> ) : DAG . getZExtOrTrunc ( N00 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N00 ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) return createMMXBuildVector ( N0 , DAG , Subtarget ) ; if ( ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) && isNullConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getValueType ( ) . is128BitVector ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N00 ) , VT , DAG . getBitcast ( <STR_LIT> , N00 ) ) ; } if ( SrcVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) { SDLoc DL ( N0 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( <STR_LIT> , Res ) ) ; } } if ( Subtarget . hasAVX512 ( ) && VT . isScalarInteger ( ) && SrcVT . isVector ( ) && SrcVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ( N0 . getNode ( ) ) ) { return combinevXi1ConstantToInteger ( N0 , DAG ) ; } if ( SDValue V = combineCastedMaskArithmetic ( N , DAG , DCI , Subtarget )


<s> unsigned getPreferVectorWidth ( ) const { return


<s> StringRef Name ; const MCExpr * Value ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Dollar ) ) { MCSymbol * Symbol ; SMLoc DollarLoc = getLexer ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( DollarLoc . getPointer ( ) + <NUM_LIT> != getTok ( ) . getLoc ( ) . getPointer (


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return


<s> for ( StringMap < const <ISA_LIT>CallEntry * > :: iterator I = ExternalCallEntries . begin ( ) , E =

ExternalCallEntries . end ( ) ; I != E ;


<s> static MachineBasicBlock :: iterator skipAlignedDPRCS2Spills ( MachineBasicBlock :: iterator MI , unsigned NumAlignedDPRCS2Regs ) { ++ MI ; ++ MI ; ++ MI ; assert ( MI -> mayStore (


<s> unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm ( opc1 ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm (


<s> if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return <NUM_LIT> ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious )


<s> for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( ! MRI . reg_nodbg_empty ( <STR_LIT> + i ) ) { FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; Bundles = & getAnalysis < EdgeBundles > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; df_iterator_default_set < MachineBasicBlock * > Processed ; MachineBasicBlock * Entry = & MF . front ( ) ; LiveBundle & Bundle = LiveBundles [ Bundles -> getBundle ( Entry -> getNumber ( ) , false ) ] ; if ( ( Entry -> getParent ( ) -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_RegCall ) && ( Bundle . Mask && ! Bundle . FixCount ) ) { assert ( ( Bundle . Mask & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Bundle . FixCount = <NUM_LIT> ; Bundle . FixStack [ <NUM_LIT> ] = <NUM_LIT> ; } bool Changed = false


<s> MCContext & Ctx = Asm . getContext ( ) ; MCFixupKind Kind = Fixup . getKind ( ) ; MCFixupKindInfo Info = getFixupKindInfo ( Kind ) ; unsigned Offset = Fixup . getOffset ( ) ; if ( Kind == static_cast < MCFixupKind > ( <STR_LIT> ) || Kind == static_cast < MCFixupKind > ( <STR_LIT> ) ) Data [ Offset ] &= <NUM_LIT> ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; Value <<= Info


<s> return ( int32x4_t ) __builtin_neon_vdup_lanev4si ( __a ,


<s> if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) return Op ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX (


<s> for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back ( NElts


<s> MBB . splice ( std :: next ( Slot ) , & MBB , std :: next ( Filler ) . base ( ) ) ; MIBundleBuilder ( MBB , Slot , std :: next ( Slot , <NUM_LIT> ) ) ; ++ UsefulSlots


<s> bool isSystemPStateFieldWithImm0_1 ( ) const { if ( ! isSysReg ( ) ) return false ; return ( SysReg . PStateField == <STR_LIT> || SysReg . PStateField == <STR_LIT> || SysReg . PStateField

== <STR_LIT> || SysReg . PStateField == <STR_LIT> ) ;


<s> for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global ) ; for ( const auto & Alias : M . aliases ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Alias ) ; OS . flush ( ) ; if ( ! Flags . empty (


<s> unsigned int vectors_per_tuple ( ) const override { return


<s> } out ; union { float f [ <NUM_LIT> ] ; vec_float4 vf ; } in ; in . vf = ( vec_float4 ) ( a ) ; out . d [ <NUM_LIT> ] = ( double ) ( in . f [ <NUM_LIT> ] ) ; out . d [ <NUM_LIT> ] = ( double ) ( in . f [ <NUM_LIT> ] ) ; return ( ( qword ) (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> getInstSizeInBytes ( * MI ) ; MI -> eraseFromParent (


<s> bool supportsScalableVectors ( ) const { return ST -> hasSVE (


<s> rtx x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_reg_br_prob_note ( insn , profile_probability ::


<s> if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> <ISA_LIT>CC = <STR_LIT> ; SDValue CompareFlag ; if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; <ISA_LIT>CC = DAGIntCCTo<ISA_LIT>CC ( CC ) ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ,


<s> else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode ,


<s> case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT : case TYPE_VECFDIV : case


<s> if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , Reg , <STR_LIT> , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRSaveToReg ( MBB , It , Reg ) ; CallPt = MBB . insert ( It , CallMIB ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , <STR_LIT> , Reg , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRRestoreFromReg ( MBB , It ) ; It -- ; return CallPt ; } if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; bool Auth = ! AFI . isLRSpilled ( ) && AFI . shouldSignReturnAddress ( true ) ; saveLROnStack ( MBB , It , ! AFI . isLRSpilled ( ) , Auth ) ; CallPt = MBB . insert ( It , CallMIB ) ; restoreLRFromStack ( MBB , It , ! AFI . isLRSpilled ( ) , Auth ) ; It -- ; return


<s> const uint8_t ABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT . getTriple ( )


<s> case ldexp_optab : case scalb_optab : case round_optab : case lround_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_SSE4_1 && mode1 != HFmode ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( ( ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && TARGET_SSE4_1 ) || mode1 == HFmode ) && ! flag_trapping_math ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab


<s> MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ( Size * <NUM_LIT> ) ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; if ( Size == <NUM_LIT> ) { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor


<s> if ( regno < <NUM_LIT> ) return regno ; if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; else return <NUM_LIT> + ( regno - FIRST_VFP_REGNUM ) / <NUM_LIT> ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) )

return <NUM_LIT> + regno - FIRST_IWMMXT_GR_REGNUM ;


<s> int64_t Val = CE -> getValue ( ) ; return ( Val == INT32_MIN ) || ( Val > - <NUM_LIT>


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth >


<s> bool use64BitRegs ( ) const { return


<s> bool isTargetCOFF ( ) const { return isTargetMingw ( ) || isTargetCygwin ( ) || isTargetWindows (


<s> Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> | <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; CCValid = <STR_LIT> ; return true ; case <STR_LIT> : case


<s> HasAbsolutizedSet = true ; HasScatteredSymbols =


<s> static SDValue PromoteSplat ( ShuffleVectorSDNode * SV , SelectionDAG & DAG ) { EVT PVT = <STR_LIT> ; EVT VT = SV -> getValueType ( <NUM_LIT> ) ; DebugLoc dl = SV -> getDebugLoc ( ) ; SDValue V1 = SV -> getOperand ( <NUM_LIT> ) ; int NumElems = VT . getVectorNumElements ( ) ; int EltNo = SV -> getSplatIndex ( ) ; while ( NumElems > <NUM_LIT> ) { if ( EltNo < NumElems / <NUM_LIT> ) { V1 = getUnpackl ( DAG , dl , VT , V1 , V1 ) ; } else { V1 = getUnpackh ( DAG , dl , VT , V1 , V1 ) ; EltNo -= NumElems / <NUM_LIT> ; } NumElems >>= <NUM_LIT> ; } int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo ,


<s> bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) )


<s> rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; value = XEXP ( value , <NUM_LIT> ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , <NUM_LIT>


<s> if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return <STR_LIT> ; isV_UNDEF = true ; if ( isVTRN_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return <STR_LIT> ; if ( isVUZP_v_undef_Mask ( ShuffleMask , VT ,


<s> OperandMatchResultTy parsePKHASRImm ( SmallVectorImpl < MCParsedAsmOperand * > & O ) { return parsePKHImm ( O , <STR_LIT> , <NUM_LIT> ,


<s> bool <ISA_LIT>InstrInfo :: analyzeSelect ( const MachineInstr & MI , SmallVectorImpl < MachineOperand > & Cond , unsigned & TrueOp , unsigned & FalseOp , bool & Optimizable ) const { return false


<s> case <STR_LIT> : case <STR_LIT> : Suffix = <STR_LIT> ; break ; } if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal


<s> if ( ! DynAllocFI ) DynAllocFI = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; return


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( ) ) . addGlobalAddress (


<s> bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector


<s> for ( i = <NUM_LIT> ; i < subparts / <NUM_LIT> ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / <NUM_LIT> ) ; for ( i = subparts / <NUM_LIT> ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / <NUM_LIT> ) ; return


<s> MOpc = NVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; New = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , NVT , New ) , <NUM_LIT> ) ; if ( NVT == <STR_LIT> ) { New = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , New , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ; } } MachineSDNode * NewNode ; SDValue Input = N0 -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( tryFoldLoad ( Node , Input , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , New , Input . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( NVT , <STR_LIT> ) ; NewNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( N1 . getValue ( <NUM_LIT> ) , SDValue ( NewNode , <NUM_LIT> ) ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( Input ) ; if ( LoadNode ) { MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LoadNode -> getMemOperand ( ) ; NewNode -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; } } else { NewNode = CurDAG -> getMachineNode ( ROpc , dl , NVT , Input , New ) ; } ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( NewNode , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node


<s> Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; setFpFormat ( Format2 ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc ,


, <NUM_LIT> , ( __mmask16 ) - <NUM_LIT> ) ;


<s> virtual const char * getPassName ( )


<s> rtx l1 , labelno , offset_rtx ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , orig , offset_rtx ) ,


<s> return { { MachineOperand :: CreateImm ( static_cast < int64_t > ( Pred ) ) , MachineOperand

:: CreateReg ( PredReg , <NUM_LIT> ) } } ;


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { assert ( Pred1 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Pred2 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1

[ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ;


<s> bool isCK860 ( ) const { return <ISA_LIT>ProcFamily ==


<s> return ( __m128i ) __builtin_ia32_vpcomequq ( ( __v2di )


<s> const MCExpr * Offset ; SMLoc E ; if ( getParser ( ) . parseExpression ( Offset , E ) ) return MatchOperand_ParseFail ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Offset ) ; if ( ! CE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) Val = INT32_MIN ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S , E ) ) ; return MatchOperand_Success ; } bool haveEaten = false ; bool isAdd = true ; if ( Tok . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; haveEaten = true ; } else if ( Tok . is ( AsmToken :: Minus ) ) { Parser . Lex


<s> void setAppendAfterOperand ( ) { AttachToOperandIdx =


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF )


<s> static const uint32_t * getMaskForArgs ( SmallVectorImpl < <ISA_LIT>CallLowering :: ArgInfo > & OutArgs , <ISA_LIT>CallLowering :: CallLoweringInfo & Info , const <ISA_LIT>RegisterInfo & TRI , MachineFunction & MF ) { const uint32_t * Mask ; if ( ! OutArgs . empty ( ) && OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . isReturned ( ) ) { Mask = TRI . getThisReturnPreservedMask ( MF , Info . CallConv ) ; if ( ! Mask ) { OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . setReturned ( false ) ; Mask = TRI . getCallPreservedMask ( MF , Info . CallConv ) ; } }


<s> unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( RegSize / VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; SDValue Root = matchBinOpReduction ( Extract , <STR_LIT> ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Zext0 , Zext1 ; if ( ! detectZextAbsDiff ( Root , Zext0 , Zext1 ) ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue SAD = createPSADBW ( DAG , Zext0 , Zext1 , DL ) ; unsigned Stages = Log2_32 ( VT . getVectorNumElements ( ) ) ; MVT SadVT = SAD


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ) : ( Subtarget . isABI_N64 (


<s> return __builtin_mve_vcmulq_rot180v4sf ( __a ,


<s> CurDAG -> RepositionNode ( N . getNode ( ) -> getIterator ( ) , M . getNode ( ) ) ; CurDAG -> ReplaceAllUsesWith ( N , M


<s> RetType = <STR_LIT> ; break ; case CFRet : RetType = <STR_LIT> ; break ; case CDRet : RetType = <STR_LIT> ; break ; case NoFPRet : RetType = <STR_LIT> ; break ; } const char * Parms ; switch ( Signature -> ParamSig ) { case FSig : Parms = <STR_LIT> ; break ; case FFSig : Parms = <STR_LIT> ; break ; case FDSig : Parms = <STR_LIT> ; break ; case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer -> AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 (


<s> static SDValue combineGatherScatter ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDLoc DL ( N ) ; auto * GorS = cast < MaskedGatherScatterSDNode > ( N ) ; SDValue Index = GorS -> getIndex ( ) ; SDValue Base = GorS -> getBasePtr ( ) ; SDValue Scale = GorS -> getScale ( ) ; if ( DCI . isBeforeLegalize ( ) ) { unsigned IndexWidth = Index . getScalarValueSizeInBits ( ) ; if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Index ) ) { if ( BV -> isConstant ( ) && IndexWidth > <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( ( Index . getOpcode ( ) == <STR_LIT> || Index . getOpcode ( ) == <STR_LIT> ) && IndexWidth > <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) { unsigned IndexWidth = Index . getScalarValueSizeInBits ( ) ; if ( IndexWidth != <NUM_LIT> && IndexWidth != <NUM_LIT> ) { MVT EltVT = IndexWidth > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT IndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , Index . getValueType ( ) . getVectorNumElements ( ) ) ; Index = DAG . getSExtOrTrunc ( Index ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV ,


<s> void Warning ( SMLoc L , const Twine


<s> if ( ! reload_completed || frame_pointer_needed ) return <NUM_LIT> ; if ( crtl -> args . pops_args && crtl -> args . size >= <NUM_LIT> ) return <NUM_LIT> ; ix86_compute_frame_layout ( &


<s> if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } if ( Opc == <STR_LIT> && ! hasV8Ops ( ) ) { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresV8 ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst

. getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return Match_RequiresV8 ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg = <STR_LIT> ; return MFI . getObjectOffset (


<s> return :: getPromotedVTForPredicate (


<s> UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( I ) ; if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; CPUsers . push_back ( CPUser ( I , CPEMI , MaxOffs , NegOk , IsSoImm ) ) ; CPEntry * CPE = findConstPoolEntry ( CPI , CPEMI ) ; assert ( CPE && <STR_LIT> ) ; CPE -> RefCount


<s> static const char * invalid_arg_for_unprototyped_fn ( const_tree typelist , const_tree funcdecl , const_tree val ) { return ( ! rs6000_darwin64_abi && typelist == <NUM_LIT> && TREE_CODE ( TREE_TYPE ( val ) ) == VECTOR_TYPE && ( funcdecl == NULL_TREE || ( TREE_CODE (

funcdecl ) == FUNCTION_DECL && DECL_BUILT_IN_CLASS ( funcdecl ) != BUILT_IN_MD ) ) ) ? N_ ( <STR_LIT> ) : NULL ;


<s> case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && Imm == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Imm == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Shift = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Imm == <NUM_LIT> && Shift == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && Imm == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Imm = MI . getOperand ( <NUM_LIT>


<s> fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( mem ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( scratch ) ; } gcc_assert ( regno >= <NUM_LIT> && regno < FIRST_PSEUDO_REGISTER ) ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; rclass = REGNO_REG_CLASS ( regno ) ; gcc_assert ( rclass == GENERAL_REGS || rclass == BASE_REGS ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PRE_MODIFY ) { gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) == XEXP ( addr , <NUM_LIT> ) ) ; scratch_or_premodify = XEXP ( addr , <NUM_LIT> ) ; if ( ! HARD_REGISTER_P ( scratch_or_premodify ) ) scratch_or_premodify = find_replacement ( & XEXP ( addr , <NUM_LIT> ) ) ; addr = XEXP ( addr , <NUM_LIT> ) ; } gcc_assert ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) ; rs6000_emit_move ( scratch_or_premodify , addr , Pmode ) ; mem = replace_equiv_address_nv ( mem , scratch_or_premodify ) ; if ( store_p ) emit_insn ( gen_rtx_SET ( mem , reg ) ) ; else emit_insn ( gen_rtx_SET ( reg ,


<s> return ( __m256h ) __builtin_ia32_vfnmsubph256_mask ( ( __v16hf ) __A , ( __v16hf )


<s> rtx op1 = XEXP ( addr , <NUM_LIT> ) ; if ( op0 == pic_offset_table_rtx && symbolic_operand ( op1 , VOIDmode


<s> HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasADX = false ; HasSHA = false ; HasPRFCHW =


<s> SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue


<s> default : break ; case <STR_LIT> : if ( Node -> getSimpleValueType ( <NUM_LIT> ) . isVector ( ) && selectVecAddAsVecSubIfProfitable ( Node ) ) return ; break ; case <STR_LIT> : ReplaceNode ( Node , getGlobalBaseReg ( false ) ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( ( Subtarget -> systemSupportsUnalignedAccess ( cast < MemSDNode > ( Node ) -> getAddressSpace ( ) ) || ( cast < MemSDNode > ( Node ) -> getMemoryVT ( ) .

getSizeInBits ( ) / <NUM_LIT> ) <= cast < MemSDNode > ( Node ) -> getAlignment ( ) ) && <STR_LIT> ) ;


<s> const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( )

|| MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ;


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( ) { AssemblerDialect = AsmWriterVariant == Default ? <NUM_LIT> : AsmWriterVariant ; PrivateGlobalPrefix = <STR_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AlignmentIsInBytes =


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAME_TO_ARGS_OFFSET ( SDValue Op , SelectionDAG & DAG ) const { return DAG . getIntPtrConstant ( <NUM_LIT> * TD


<s> unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) UsesHighByteReg = true ; if ( <STR_LIT> ( Reg ) ) REX |= <NUM_LIT> ; } else if ( MO . isExpr ( ) && STI . getTargetTriple ( ) . isX32 ( ) ) { const auto * Ref = dyn_cast < MCSymbolRefExpr > ( MO . getExpr ( ) ) ; if ( Ref && ( Ref -> getKind ( ) == MCSymbolRefExpr :: VK_GOTTPOFF || Ref -> getKind ( ) == MCSymbolRefExpr :: VK_TLSDESC ) ) { REX |= <NUM_LIT> ; } } } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ( LastBr == End ) || ( ! LastBr -> isConditionalBranch ( ) && ! LastBr -> isUnconditionalBranch ( ) ) ) return ; ReverseIter FirstBr = getNonDebugInstr ( std :: next ( LastBr ) , End ) ; if ( ( FirstBr == End ) || ( ! FirstBr -> isConditionalBranch ( ) && ! FirstBr -> isUnconditionalBranch ( ) ) ) return ; assert ( ! FirstBr -> isIndirectBranch ( ) && <STR_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB -> getBasicBlock ( ) ) ; MachineBasicBlock * Tgt = getTargetMBB ( * FirstBr ) ; NewMBB -> transferSuccessors ( MBB ) ; NewMBB -> removeSuccessor ( Tgt , true ) ; MBB -> addSuccessor ( NewMBB ) ; MBB -> addSuccessor ( Tgt ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB )


<s> HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; break ; } } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) ; if ( RequiresBundling ) finalizeBundle ( MBB , LO16 -> getIterator ( ) , MBBI -> getIterator ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 ,


<s> MRI -> setRegClass ( Reg , getDstRC ( MRI -> getRegClass ( Reg ) , Domain ) ) ; for ( auto & MO : MRI -> use_operands ( Reg ) ) { if ( MO . isReg ( ) ) MO . setSubReg ( <NUM_LIT> ) ; } } for ( auto MI : ToErase ) MI


<s> if ( ! restrict_addressing_modes_for_nacl ) { if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if (


<s> if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList


<s> for ( prev = as_a < rtx_insn * > ( vec_lab ) ; ; prev = PREV_INSN ( prev ) ) { if ( ! JUMP_P ( prev ) ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , <NUM_LIT> ) != <NUM_LIT> ) continue ; x = XVECEXP ( prevpat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == LABEL_REF && XEXP ( x , <NUM_LIT> ) == vec_lab ) break ; } if ( ! prev ) continue ; braf_label = XEXP ( XEXP ( SET_SRC ( XVECEXP ( prevpat , <NUM_LIT> , <NUM_LIT> ) ) ,


<s> void printASROperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printShiftOperand ( <STR_LIT> , MI


<s> C . CCValid = <STR_LIT> ; C . Opcode = <STR_LIT> ; adjustForFNeg ( C ) ; } else { C . CCValid = <STR_LIT> ; C . Opcode = <STR_LIT> ; if ( C . CCMask == <STR_LIT> || C . CCMask == <STR_LIT> || ( DAG . SignBitIsZero ( C . Op0 ) && DAG . SignBitIsZero ( C . Op1 ) ) ) C . ICmpType = <STR_LIT> ; else if ( C . CCMask & <STR_LIT> ) C . ICmpType = <STR_LIT> ; else C . ICmpType = <STR_LIT> ; C . CCMask &= ~ <STR_LIT> ; adjustZeroCmp ( DAG , DL , C ) ; adjustSubwordCmp ( DAG , DL , C ) ; adjustForSubtraction ( DAG , DL , C ) ; adjustForLTGFR ( C ) ; adjustICmpTruncate ( DAG , DL , C ) ; } if ( shouldSwapCmpOperands ( C ) ) { std :: swap ( C . Op0 , C


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; MF . getFrameInfo ( ) -> setFrameAddressIsTaken ( true ) ; SDLoc DL ( Op ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT )

, DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) , DL ) ) ;


<s> StringRef getType ( ) { return CurType


<s> if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) return false ; return ( decl && ( * targetm . binds_local_p ) ( decl


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || Subtarget . hasBWI ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; if ( InVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) ExtVT =

<STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ;


<s> inline vector signed char vec_srl ( vector signed char a1 , vector unsigned char


<s> void addStrictlyFGR64AsmRegOperands ( MCInst & Inst ,


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16


<s> Value * Args [ ] = { NewLd0 , NewLd1 , Acc } ; Function * SMLAD = nullptr ; if ( Exchange ) SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; else SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; CallInst * Call = Builder .


<s> unsigned UseOpc = UseMI -> getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : { if ( Commute ) return false ; ImmVal = - ImmVal ; NewUseOpc = <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } case <STR_LIT>


<s> if ( fs . sp_realigned && cfa_offset <= fs . sp_realigned_offset ) { gcc_assert ( cfa_offset <= fs . sp_realigned_fp_last ) ; return false


<s> static unsigned adjustFixupValue ( unsigned


<s> bool IsEffectivelyImm13 = IsImm && ( ( is64Bit ( ) ? <NUM_LIT> : - <NUM_LIT> ) <= ImmValue && ImmValue < <NUM_LIT> ) ; const MCExpr * ValExpr ; if ( IsImm ) ValExpr = MCConstantExpr :: create ( ImmValue , getContext ( ) ) ; else ValExpr = MCValOp . getExpr ( ) ; MCOperand PrevReg = MCOperand :: createReg ( <STR_LIT> ) ; if ( ! IsEffectivelyImm13 ) { MCInst TmpInst ; const MCExpr * Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , ValExpr , getContext ( ) ) ; TmpInst . setLoc ( IDLoc ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCRegOp ) ; TmpInst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; Instructions . push_back ( TmpInst ) ; PrevReg = MCRegOp ; } if ( ! IsImm || IsEffectivelyImm13 || ( ImmValue & <NUM_LIT> ) ) { MCInst TmpInst ; const MCExpr * Expr ; if ( IsEffectivelyImm13 ) Expr = ValExpr ; else Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , ValExpr , getContext ( ) ) ; TmpInst . setLoc ( IDLoc ) ; TmpInst . setOpcode ( <STR_LIT>


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * MBB ) const { llvm_unreachable (


<s> return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerAND ( Op , DAG ) ; case <STR_LIT> : return LowerOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case


<s> EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned AddressSpace = Ld -> getAddressSpace ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Alignment >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment


<s> bool llvm :: convertToNonDenormSingle ( APInt & ArgAPInt ) { double DpValue = ArgAPInt . bitsToDouble ( ) ; APFloat APFloatDp ( DpValue


<s> if ( N -> getMaskElt ( i ) < <NUM_LIT> ) { if ( ! LDBase ) return false ; continue ; } SDValue Elt = DAG . getShuffleScalarElt ( N , i ) ; if ( ! Elt . getNode ( ) || ( Elt . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Elt . getNode ( ) ) ) ) return false ; if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return false ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return false ; LastLoadedElt = i ; } return true


<s> Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result , DAG . getConstant (


<s> Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC /


<s> } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetArchDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Warning ( Tok . getLoc ( ) , <STR_LIT> ) ; getParser ( ) . Lex ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getParser ( ) . Lex ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFpDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetOddSPRegDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoOddSPRegDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPopDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPushDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { if ( has<ISA_LIT>64r6 ( ) ) { Error ( Tok . getLoc ( ) , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>0Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT>


<s> return ( uint64x2_t ) __builtin_neon_vdup_nv2di (


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { ds [ i ] = * d ; ds [ i ] . vmode = V32HImode ; ds [ i ] . nelt = <NUM_LIT> ; ds [ i ] . target = gen_reg_rtx ( V32HImode ) ; ds [ i ] . op0 = gen_lowpart ( V32HImode , d -> op0 ) ; ds [ i ] . op1 = gen_lowpart ( V32HImode , d -> op1 ) ; } for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { ds [ i & <NUM_LIT> ] . perm [ i / <NUM_LIT> ] = d -> perm [ i ] / <NUM_LIT> ; if ( i & <NUM_LIT> ) { rperm [ i ] = constm1_rtx ; rperm [ i + <NUM_LIT> ] = GEN_INT ( ( i & <NUM_LIT> ) + ( d -> perm [ i ] & <NUM_LIT> ) ) ; } else { rperm [ i ] = GEN_INT ( ( i & <NUM_LIT> ) + ( d -> perm [ i ] & <NUM_LIT> ) ) ; rperm [ i + <NUM_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . End -> eraseFromParent ( ) ; LoLoop . Dec -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart


<s> return DAG . getBuildVector ( VT , DL , Ops ) ; } if ( Value . isUndef ( ) ) return DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> inline bool CC_<ISA_LIT>_GHC_Error ( unsigned & , MVT & , MVT & , CCValAssign :: LocInfo & , <STR_LIT> & , CCState & ) { report_fatal_error ( <STR_LIT>


<s> static bool IsSP ( const MachineOperand & MO ) { if ( MO . isReg ( ) && ( ( MO . getReg ( ) == <STR_LIT> ) ) ) return true ; return false


<s> static bool contains_string_p ( const char * * arr , const char * str ) { bool res = false ; if ( arr [ <NUM_LIT> ]


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( poly8x16_t ) __builtin_aarch64_qtbl3v16qi ( __o , ( int8x16_t


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( createTLOF ( ) )

, Subtarget ( TT , CPU , FS , * this ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode3 ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( Op ) ; if ( ! restrict_addressing_modes_for_nacl ) { if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC


<s> MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = FunctionAlignment . getValue ( ) ? std :: log2 ( FunctionAlignment . getValue ( ) ) : <NUM_LIT> ; PrefLoopAlignment = LoopAlignment . getValue ( ) ? std :: log2 ( LoopAlignment . getValue ( ) ) : <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case


<s> void forwardVPTPosition ( ) { if ( ! inVPTBlock ( )


<s> MachineRegisterInfo & RI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned StackAlignment = <ISA_LIT>RI -> getStackAlignment ( ) ; for ( unsigned i = <NUM_LIT> , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RI . getRegClass ( Reg ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setReserveFP ( true ) ; return true ; } } return false


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> ,


<s> else if ( V1 . getValueSizeInBits ( ) < Width ) V1 = insertSubVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , Width ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( BV -> getOperand ( i ) . isUndef ( ) ) DemandedElts . clearBit ( i ) ; unsigned HalfNumElts = NumElts / <NUM_LIT> ; if ( VT . is256BitVector ( ) && DemandedElts . lshr ( HalfNumElts ) == <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( VT . getScalarType ( ) , HalfNumElts ) ; V0 = extractSubVector ( V0 , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; SDValue Half = DAG . getNode ( HOpcode , SDLoc ( BV ) , HalfVT , V0 , V1 ) ; return insertSubVector ( DAG . getUNDEF ( VT ) , Half , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; } return DAG . getNode ( HOpcode , SDLoc (


<s> if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , Address , OS ) ) printInstruction ( MI ,


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getTLSDescCallPreservedMask ( ) const { return


<s> bool isTargetzOS ( ) const { return TargetTriple . isOSzOS (


<s> void \ sbss_section ( ) \ { \ if ( in_section != in_sbss ) \ { \ fprintf ( asm_out_file , <STR_LIT> , SBSS_SECTION_ASM_OP ) ;


<s> for ( i = <NUM_LIT> ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , LHS , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS


<s> if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known = DAG . computeKnownBits ( In ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( SVT == <STR_LIT> && NumSignBits != InSVT . getSizeInBits ( ) ) return SDValue ( ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedSignBits ) ) return truncateVectorWithPACK ( <STR_LIT> ,


<s> case V8SFmode : case V8SImode : case V32QImode : case V16HImode : case V4DFmode : case V4DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case V8QImode : case V4HImode : case V2SImode : case V2SFmode : case V1TImode : case V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> mmx_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> mmx_regno + FIRST_MMX_REG ) ; } break ; } if ( error_p ) { cum -> float_in_sse = <NUM_LIT> ; error ( <STR_LIT> <STR_LIT> , cum -> decl ) ; sorry ( <STR_LIT> <STR_LIT> )


<s> if ( GET_CODE ( op ) != REG ) return <NUM_LIT> ; if ( op == virtual_incoming_args_rtx || op == virtual_stack_vars_rtx || op == virtual_stack_dynamic_rtx || op == virtual_outgoing_args_rtx || op == virtual_cfa_rtx ) return <NUM_LIT> ; if ( ! reload_completed && flag_omit_frame_pointer && ! current_function_calls_alloca && op == frame_pointer_rtx ) return <NUM_LIT> ; return register_operand ( op


<s> } else { OutStreamer -> emitAssemblerFlag ( MCAF_Code32 ) ; } if ( AFI -> isCmseNSEntryFunction ( ) ) { MCSymbol * S = OutContext . getOrCreateSymbol ( <STR_LIT> + CurrentFnSym -> getName ( ) ) ; emitLinkage ( & MF -> getFunction (


<s> case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Swift : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: Intel_OCL_BI : case CallingConv ::


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg )


sparc_leaf_function_p == crtl -> uses_only_leaf_regs ) ;


<s> if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC ,


<s> if ( flag_nop_mcount ) fprintf ( file , <STR_LIT>


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned FrameReg = <STR_LIT> ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue FrameAddr ; if ( depth == <NUM_LIT> ) FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; else { SDValue Chain = getFLUSHW ( Op , DAG ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg


<s> return ( __m256 ) __builtin_ia32_rsqrt14ps256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( ) ,


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_prefetch_i64scatter_pd ( void * addr , __m512i index , int scale , int hint ) { __builtin_ia32_scatterpfqpd ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , ( long long


<s> if ( Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMADD ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask , APInt & UndefElts ) { SmallVector < APInt , <NUM_LIT> > EltBits ; if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits , true , false ) ) return false ; for ( const APInt & Elt : EltBits ) RawMask . push_back ( Elt .


<s> int getVarArgsGPRIndex ( ) const { return VarArgsGPRIndex


<s> static SDValue lowerVectorShuffleAsBitMask ( SDLoc DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG ) { MVT EltVT = VT . getVectorElementType ( ) ; int NumEltBits = EltVT . getSizeInBits ( ) ; MVT IntEltVT = <STR_LIT> ( NumEltBits ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , DL , IntEltVT ) ; if ( EltVT . isFloatingPoint ( ) ) { Zero = DAG . getBitcast ( EltVT , Zero ) ; AllOnes = DAG . getBitcast ( EltVT , AllOnes ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i


<s> MachineInstr * MVETPAndVPTOptimisations :: CheckForLRUseInPredecessors ( MachineBasicBlock * PreHeader , MachineInstr * LoopStart ) { SmallVector < MachineBasicBlock * > Worklist ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited ; Worklist . push_back ( PreHeader ) ; Visited . insert ( LoopStart -> getParent ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; if ( Visited . count ( MBB ) ) continue ; for ( MachineInstr & MI : * MBB ) { if ( ! IsInvalidTPInstruction ( MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB = BuildMI ( * PreHeader , PreHeader -> getFirstTerminator ( ) , LoopStart -> getDebugLoc ( ) , TII


<s> if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <=


<s> MVT EltVT = VT . getVectorElementType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] )


<s> const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT>


<s> if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; Register ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC , true , <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ) ) return false ; updateValueMap ( I , ResultReg ) ; return


<s> if ( X . getValueType ( ) . isScalarInteger ( ) ) return true ; if ( DAG . isSplatValue ( Y , true ) ) return true ; if ( Subtarget . hasAVX2 ( ) )


<s> static SDValue convertToScalableVector ( SelectionDAG & DAG , EVT VT , SDValue V ) { assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; assert ( V . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( V ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , V ,


<s> if ( ( Subtarget -> isTargetWindowsGNU ( ) || Subtarget -> isTargetWindowsCygwin ( ) ) && ( Name [ <NUM_LIT> ] == getDataLayout ( ) . getGlobalPrefix ( ) ) ) Name = Name . drop_front ( ) ; OS << Name ; if ( IsData ) { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; } OS . flush (


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; SDValue Vec ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst ,


<s> bool SVEIntrinsicOpts :: optimizeFunctions ( SmallSetVector < Function * , <NUM_LIT> > & Functions ) { bool Changed = false ; Changed |= optimizePTrueIntrinsicCalls ( Functions ) ; Changed |= optimizeIntrinsicCalls ( Functions ) ; return Changed


<s> MCContext & Ctx = getContext ( ) ; const MCRegisterInfo * RI = Ctx . getRegisterInfo ( ) ; if ( ! RI -> getRegClass ( <STR_LIT> ) . contains ( RegNum ) ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; Parser . Lex ( ) ; if ( ! parseOptionalToken ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , false , S , getLoc (


<s> bool <ISA_LIT>BaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) PM . add ( create<ISA_LIT>GlobalMergePass ( getTargetLowering ( ) ) ) ; return false


<s> } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr =


<s> else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ]