<s> if ( <STR_LIT> ( Reg ) ) REX |= <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : { REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; } case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } if ( ! ( IsZExt && isZExtLoad ( LoadMI ) ) && ! ( ! IsZExt && isSExtLoad ( LoadMI ) ) ) return false ; if ( RetVT != <STR_LIT> || SrcVT > <STR_LIT> ) { updateValueMap ( I , Reg ) ; return true ; } if ( IsZExt ) { Register Reg64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( Reg , getKillRegState ( true ) ) . addImm ( <STR_LIT> ) ; Reg =


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get (

<STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ;


<s> AddDefaultPred ( LDM . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; AddDefaultPred ( STM . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; llvm :: SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; std :: sort ( ScratchRegs . begin ( ) , ScratchRegs . end ( ) , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue ( Reg2 ) ; } ) ; for ( const auto & Reg : ScratchRegs ) { LDM . addReg ( Reg , RegState :: Define ) ; STM . addReg ( Reg , RegState ::


<s> bool IsN32 ( ) const { return ThisABI == ABI ::


<s> CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , false , Op0 , Op1 , DAG ) ; assert ( CondCode != <STR_LIT> &&


<s> return ( __m256i ) __builtin_ia32_packusdw256 ( ( __v8si


<s> return E . value ( ) < <NUM_LIT> || E . value ( ) == ( int ) E . index ( ) + <NUM_LIT> ; } ) ) return <NUM_LIT> ; unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { assert ( M [ i ] < <NUM_LIT> && <STR_LIT> ) ; if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex


const __A , int const __D , int const __N ) {


<s> default : break ; case <STR_LIT> : case <STR_LIT> : EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; int64_t Cnt ; if ( ! isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) break ; unsigned VShiftOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( VShiftOpc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG .


<s> unsigned ResultReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ResultReg && <STR_LIT> ) ; if ( DestVT == <STR_LIT> ) { Register Reg64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( ResultReg ) . addImm ( <STR_LIT> ) ; ResultReg = Reg64 ; } return ResultReg ; } else { if ( DestVT ==


<s> static DecodeStatus DecodeFMOVLaneInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned IsToVec = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( IsToVec ) { DecodeVPR128RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; } else { DecodeGPR64RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeVPR128RegisterClass ( Inst , Rn , Address , Decoder ) ; } Inst . addOperand ( MCOperand ::


<s> MI -> setDesc ( get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) .


<s> vax_add_reg_cfa_offset ( insn , <NUM_LIT> , frame_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , <NUM_LIT> , pc_rtx ) ; offset = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( mask & ( <NUM_LIT> << regno ) ) { vax_add_reg_cfa_offset ( insn , offset , gen_rtx_REG ( SImode , regno ) ) ; offset += <NUM_LIT> ; } add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; size = get_frame_size ( ) ; size -= vax_starting_frame_offset ( ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx ,


<s> void addImmSExt8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateMCValue ( getImm ( )


<s> RegisterTargetMachine < <ISA_LIT>_64TargetMachine > Y ( The<ISA_LIT>_64Target ) ; RegisterAsmInfoFn A ( The<ISA_LIT>_32Target , createMCAsmInfo ) ; RegisterAsmInfoFn B ( The<ISA_LIT>_64Target , createMCAsmInfo ) ; TargetRegistry :: RegisterCodeEmitter ( The<ISA_LIT>_32Target , create<ISA_LIT>_32MCCodeEmitter ) ; TargetRegistry :: RegisterCodeEmitter ( The<ISA_LIT>_64Target , create<ISA_LIT>_64MCCodeEmitter ) ; TargetRegistry :: RegisterAsmBackend (


<s> tmpInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; tmpInst . addOperand ( Imm ) ; tmpInst . setLoc ( IDLoc


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) .


<s> case TargetOpcode :: G_GLOBAL_VALUE : { const GlobalValue & GV = * MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( ) ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : return


<s> ( * lang_hooks . types . register_builtin_type ) ( intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( aarch64_fp16_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( bfloat16_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node


<s> return Kind == k_ShiftedRegister && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegShiftedReg . SrcReg ) && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> __attribute__ ( ( __always_inline__ ) ) _mm_cvtsi64_si64x ( __m64 __i ) { return ( long long ) __i


<s> if ( Op -> getOpcode ( ) == <STR_LIT> ) return true ; if ( isa < ConstantSDNode > ( Op


<s> MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; EnclosedEdges . clear ( ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; unsigned ClosureID = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) ) continue ; Closure C ( ClosureID ++ , { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back ( std :: move ( C ) ) ; } for ( Closure & C : Closures


<s> FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { crtl -> stack_realign_needed = stack_realign ; crtl -> stack_realign_finalized


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetDsp (


<s> machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( VECTOR_MODE_P ( mode2 ) ) op2 = safe_vector_operand ( op2 , mode2 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( builtin_sha1cpm_p ) op3 = GEN_INT ( TARGET_BIG_END ?


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( Count % <NUM_LIT> != <NUM_LIT> )


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << getRegisterName ( MO2 . getReg ( )


<s> SDLoc DL ( Op ) ; EVT Ty = Subtarget -> isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = Subtarget -> isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = Subtarget -> isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( ) ) , Chain


<s> const Function & F = * MF . getFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; unsigned NumArgs = Args . size ( ) ; Function :: const_arg_iterator CurOrigArg = Args . begin ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i , ++ CurOrigArg ) { MVT ValVT = <STR_LIT> ( CurOrigArg -> getType ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , <STR_LIT> ( ) , CCInfo ) ; assert ( ! Res && <STR_LIT>


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else llvm_unreachable (


<s> rtx reg ; slotno = mt_function_arg_slotno ( cum , mode , type , named , incoming_p , & regno ) ; if ( slotno == - <NUM_LIT> ) reg = NULL_RTX ; else reg = gen_rtx_REG ( mode , regno ) ; return


<s> static void pa_elf_file_start ( void ) { pa_file_start_level ( ) ; pa_file_start_mcount ( <STR_LIT> ) ; pa_file_start_file ( <NUM_LIT>


<s> End = <NUM_LIT> - LSB ; return true ; } if ( isStringOfOnes ( Mask ^ allOnes ( BitSize ) , LSB , Length ) ) { assert ( LSB > <NUM_LIT> && <STR_LIT> ) ; assert ( LSB + Length < BitSize && <STR_LIT> ) ; Start = <NUM_LIT> - ( LSB - <NUM_LIT> ) ; End = <NUM_LIT> - ( LSB + Length ) ; return true


<s> for ( auto & LR : interferenceGraph ) { if ( LR -> contains ( MI ) ) { ranges . push_back (


<s> __inline__ static unsigned long long sh_media_MSHFLO_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> virtual void print ( raw_ostream & OS )


<s> Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = FixedVectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else


<s> gcc_assert ( REG_P ( op ) ) ; if ( ! strict || REGNO ( op ) < FIRST_PSEUDO_REGISTER || ! reg_renumber || reg_renumber [ REGNO ( op ) ] < <NUM_LIT> ) return REGNO ( op ) ; return reg_renumber [ REGNO (


<s> * __carry_out = ( __builtin_arm_get_fpscr_nzcvqc ( ) >> <NUM_LIT> ) & <NUM_LIT> ; return __res


<s> return DecodeVecShiftLImm ( Inst , Imm , <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI ) { const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned


<s> return ( uint32x2_t ) __builtin_neon_vcagtv2sf


<s> if ( OptLevel != CodeGenOpt :: None && Subtarget . hasSSE2 ( )


<s> return __arm_vstrhq_p_f16 ( __addr ,


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( IsN64 ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding (


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeRROperand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op


<s> return isMemDisp12 ( BDVMem , GR64Reg


<s> return ( uint16x4_t ) __builtin_neon_vabduv4hi ( ( int16x4_t ) __a , (


<s> bool isArgumentHandler ( ) const override { return


<s> const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= <NUM_LIT> && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsUnalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; return Size >= <NUM_LIT>


<s> gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case QImode : case HImode : emit_insn ( gen_rtx_SET ( VOIDmode , dest , source ) ) ; return true ; case SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & <NUM_LIT> ) ) ) ) ; break ; case DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = ( ( c & <NUM_LIT>


<s> bool MadeChange = false ; for ( Loop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I )

; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> void printf80mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source ,


<s> setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; if ( Ty != <STR_LIT> ) { setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'O' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( auto * CST = dyn_cast < ConstantSDNode


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_i ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_X ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode


<s> mips_sim_reset ( state ) ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { mips_sim_wait_insn ( state , insn ) ; mips_sim_issue_insn ( state ,


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function &


<s> static bool equal_keys ( const char * a , const char * b ) { return strcmp ( a , b


<s> static DecodeStatus DecodeDTripleRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeRegisterClassByID ( Inst , RegNo , <STR_LIT> , Decoder


<s> aarch64_def_or_undef ( TARGET_LSE , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_AES , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_FRINT , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_TME , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_RNG , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_MEMTAG , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( aarch64_bti_enabled ( ) , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; if ( aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE ) { int v = <NUM_LIT> ; if ( aarch64_ra_sign_key == AARCH64_KEY_A ) v |= <NUM_LIT> ; if ( aarch64_ra_sign_key == AARCH64_KEY_B ) v |= <NUM_LIT> ; if ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL ) v |= <NUM_LIT> ; builtin_define_with_int_value ( <STR_LIT> , v ) ; } aarch64_def_or_undef ( TARGET_I8MM , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_BF16_SIMD , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_BF16_FP , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_LS64 , <STR_LIT> , pfile


<s> bool isAIXABI ( ) const { return TargetTriple .


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder


<s> void <ISA_LIT>VolatileTileData :: replacePhiDefWithLoad ( Instruction * PHI ,


<s> case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : if ( ConstantSDNode * Op2 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Value = - Op2 -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || isInt < <NUM_LIT> > ( Value ) ) { SDValue Ops [ ] = { Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( int32_t ( Value ) , VT ) } ; Node = CurDAG -> MorphNodeTo ( Node , <STR_LIT> , Node -> getVTList ( ) , Ops , array_lengthof ( Ops ) ) ; } } break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs (


<s> return new <ISA_LIT>ExpandAtomicPseudo (


<s> LLVMContext * Context = & MF -> getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; unsigned ConstAlign = MF -> getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF -> getConstantPool ( ) -> getConstantPoolIndex ( CPV , ConstAlign ) ; unsigned TempReg = MF -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; Opc = Subtarget -> isThumb ( ) ? <STR_LIT> : UseGOT_PREL ? <STR_LIT> : <STR_LIT> ; DestReg = constrainOperandRegClass ( TII . get ( Opc ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) .

addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ;


<s> case <STR_LIT> : case <STR_LIT> : return getUsefulBitsFromAndWithImmediate ( SDValue ( UserNode , <NUM_LIT> ) , UsefulBits , Depth ) ; case <STR_LIT> : case <STR_LIT> : return getUsefulBitsFromUBFM ( SDValue ( UserNode , <NUM_LIT> ) , UsefulBits , Depth ) ; case <STR_LIT> : case <STR_LIT> : if ( UserNode -> getOperand ( <NUM_LIT> ) != Orig && UserNode -> getOperand ( <NUM_LIT> ) == Orig ) getUsefulBitsFromOrWithShiftedReg ( SDValue ( UserNode , <NUM_LIT> ) , UsefulBits , Depth ) ; return ; case <STR_LIT> : case


<s> return ( __m128 ) __builtin_ia32_rcpps ( ( __v4sf )


<s> bool hasSSEUnalignedMem ( ) const { return HasSSEUnalignedMem


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc =


<s> switch ( ( int ) ARM_FUNC_TYPE ( func_type ) ) { default : case ARM_FT_NORMAL : break ; case ARM_FT_INTERWORKED : asm_fprintf ( f , <STR_LIT> ) ; break ; case ARM_FT_ISR : asm_fprintf ( f , <STR_LIT> ) ; break ; case ARM_FT_FIQ : asm_fprintf ( f , <STR_LIT> ) ; break ; case ARM_FT_EXCEPTION : asm_fprintf ( f , <STR_LIT> ) ; break ; } if ( IS_NAKED ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_VOLATILE ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_NESTED ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_STACKALIGN ( func_type ) ) asm_fprintf


<s> for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI ) ; MRI -> constrainRegClass ( EvenReg , TRC ) ; MRI -> constrainRegClass ( OddReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg , <STR_LIT> , EvenReg ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) { MachineInstr * Op = Ops . back ( ) ; Ops . pop_back ( ) ; MBB -> splice ( InsertPos , MBB , Op ) ; } } NumLdStMoved += NumMove ; RetVal = true ; } } } return RetVal


<s> static MCDisassembler * create<ISA_LIT>LEDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> * second_code = UNKNOWN ; switch ( code ) { case GT : case GE : case ORDERED : case UNORDERED : case UNEQ : case UNLT : case UNLE : case LTGT : break ; case LT : * first_code = UNLT ; * bypass_code = UNORDERED ; break ; case LE : * first_code = UNLE ; * bypass_code = UNORDERED ; break ; case EQ : * first_code


<s> FunctionPass * llvm :: create<ISA_LIT>ProtectSpillSupport ( ) { return new


<s> ParseDirective ( AsmToken DirectiveID ) { return


<s> if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( unsigned JTI = <NUM_LIT> , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; EmitAlignment ( Log2_32 ( Size ) ) ; OutStreamer -> EmitLabel ( GetJTISymbol ( JTI ) ) ; for ( auto * JTBB : JTBBs ) emitJumpTableEntry ( MJTI , JTBB


<s> return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; if ( MOP . isReg ( ) && ! MOP . isImplicit ( ) && ( MOP . getReg ( ) == <STR_LIT> || MOP . getReg ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return outliner :: InstrType :: Legal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return UnknownCallOutlineType ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return UnknownCallOutlineType ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo


<s> assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && <STR_LIT> ) ; assert ( V1 . getValueType ( ) . isSimple ( ) && <STR_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfNumElts = NumElts / <NUM_LIT> ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , HalfNumElts ) ; auto getHalfVector = [ & ] ( int HalfIdx ) { if ( HalfIdx < <NUM_LIT> ) return DAG . getUNDEF ( HalfVT ) ; SDValue V = ( HalfIdx < <NUM_LIT> ? V1 : V2 ) ; HalfIdx = ( HalfIdx % <NUM_LIT> ) * HalfNumElts ; return DAG . getNode ( <STR_LIT> , DL , HalfVT , V , DAG . getIntPtrConstant ( HalfIdx , DL ) ) ; } ; SDValue Half1 = getHalfVector ( HalfIdx1 ) ; SDValue Half2 = getHalfVector ( HalfIdx2 ) ; SDValue V = DAG . getVectorShuffle ( HalfVT , DL , Half1 , Half2 ,


<s> uint32_t IntMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < uint32_t > Mask = makeArrayRef ( IntMask1 , <NUM_LIT> ) ; Value * IntrVec1 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec2 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; uint32_t IntMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask2 , <NUM_LIT> ) ; Value * IntrVec3 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec4 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; uint32_t IntMask3 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask3 , <NUM_LIT> ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1 , IntrVec2 , Mask ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec3


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> )


<s> ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasXMM ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue


<s> Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Value * Next = Builder . CreateLoad ( FSZero ) ; Builder . CreateStore ( Next , Builder . CreateStructGEP ( LinkTy , Link


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>elTarget


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI ->


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; return MCDisassembler ::


<s> WorkList . push_back ( V ) ; Defs . insert ( V ) ; while ( ! WorkList . empty ( ) ) { Value * Curr = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( User * CurrUser = dyn_cast < User > ( Curr ) ) for ( auto & Op : CurrUser -> operands ( ) ) if ( Defs . insert ( Op ) . second


<s> SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( int I : ShuffleMask ) VTBLMask . push_back ( DAG . getConstant ( I , DL , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getBuildVector ( <STR_LIT>


<s> if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( insn ) ) ) return ; use_record = DF_INSN_USES ( use_insn ) ; if ( DF_REF_CHAIN ( use_record ) && DF_REF_CHAIN ( use_record ) -> next ) return ; if ( ! active_insn_p ( use_insn ) ) return ; if ( ! nds32_float_reg_load_store_p ( use_insn ) || find_post_update_rtx ( use_insn ) != - <NUM_LIT> ) return ; } group_id = GEN_INT ( nds32_alloc_relax_group_id (


<s> return createMachObjectWriter ( OS , true , object :: mach ::

CTM_x86_64 , object :: mach :: CS<ISA_LIT>_ALL , true ) ;


<s> else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & <NUM_LIT> ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = frame_insn (


<s> * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; * IsIndirectCall =


<s> SDLoc dl ( Op ) ; assert ( ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) || ( VT == <STR_LIT> && Subtarget -> hasInt256 ( ) ) ) ; const int Mask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Odd0 = DAG . getVectorShuffle ( VT , dl , Op0 , Op0 , Mask ) ; SDValue Odd1 = DAG . getVectorShuffle ( VT , dl , Op1 , Op1 , Mask ) ; MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget -> hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode

( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ;


<s> if ( Subtarget . hasZeroCycleZeroingFP ( ) ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; } if ( Subtarget . hasZeroCycleZeroingGP ( ) ) { if ( Opcode == TargetOpcode :: COPY && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return true ; } if ( Subtarget . hasExynosCheapAsMoveHandling ( ) ) { if ( isExynosResetFast ( MI ) || isExynosShiftLeftFast ( MI ) ) return true ; else return MI . isAsCheapAsAMove ( ) ; } switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress


<s> const MachineFunction & MF = * MBB . getParent ( ) ; for ( const CalleeSavedInfo & CSI : MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ) for ( MCRegister Reg : TRI -> sub_and_superregs_inclusive ( CSI . getReg ( ) ) ) RegsToZero . reset ( Reg ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; for ( MachineBasicBlock :: iterator I = MBBI , E = MBB . end ( ) ; I != E ; ++ I ) for ( const MachineOperand & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; for ( const MCPhysReg & Reg : TRI -> sub_and_superregs_inclusive ( MO . getReg ( ) ) ) RegsToZero . reset ( Reg ) ; } DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( MCRegister Reg : RegsToZero . set_bits ( ) ) { if ( ! <STR_LIT> . contains ( Reg ) ) continue ; unsigned NumFPRegs = ST . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumFPRegs ; ++ i ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumFPRegs ; ++ i ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; break ; } BitVector GPRsToZero ( TRI -> getNumRegs ( ) ) ; for ( MCRegister Reg : RegsToZero . set_bits ( ) ) if ( TRI -> isGeneralPurposeRegister ( MF , Reg ) ) { GPRsToZero . set ( get<ISA_LIT>SubSuperRegisterOrZero ( Reg , <NUM_LIT> ) ) ; RegsToZero . reset ( Reg ) ; } for ( MCRegister Reg : GPRsToZero . set_bits ( ) ) BuildMI ( MBB , MBBI , DL , TII . get (

<STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getAddrModeSBit ( const MachineInstr & MI , const MCInstrDesc & MCID ) const { for ( unsigned i = MI . getNumOperands ( ) , e = MCID

. getNumOperands ( ) ; i >= e ; -- i ) {


<s> case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue SetFFR = DAG . getNode ( <STR_LIT> , dl , NodeTys , N -> getOperand ( <NUM_LIT> ) ) ; SDValue LoadOps [ ] = { SetFFR , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , SDValue ( SetFFR . getNode ( ) , <NUM_LIT> ) } ; SDVTList LoadVTs = DAG . getVTList ( NewVT , <STR_LIT> ) ; SDValue Load = DAG . getNode ( Opc , dl , LoadVTs , LoadOps ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; SDValue PredOps [ ] = { LoadChain , N -> getOperand ( <NUM_LIT> ) } ; SDVTList PredVTs = DAG . getVTList ( PredVT


<s> Inst . addOperand ( MCOperand :: createImm


<s> static MachineBasicBlock * getBBFallenThrough ( MachineBasicBlock * MBB , const TargetInstrInfo * TII ) { MachineFunction :: iterator MBBI ( MBB ) ; if ( MBBI == MBB -> getParent ( ) -> begin ( ) ) return nullptr ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * PrevBB = & * std :: prev ( MBBI ) ; for ( MachineBasicBlock * S : MBB -> predecessors ( ) ) if ( S == PrevBB && ! TII -> AnalyzeBranch ( * PrevBB , TBB , FBB , Cond ) && ! TBB && ! FBB ) return S ; return nullptr


<s> std :: swap ( V1 , V2 ) ; SwappedOps = true ; } if ( V1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Src = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( ! SrcVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return SDValue ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget .


<s> case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg , Mask ) ; unsigned ResultReg = fastEmitInst_rr ( Opc , RC , Op0Reg , Op1Reg ) ; if ( NeedTrunc ) ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ; return ResultReg


<s> if ( V -> getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ) return false ; ConstantSDNode * CN = cast < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ; return CurDAG -> MaskedValueIsZero ( V -> getOperand ( <NUM_LIT> ) , CN ->


<s> int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup


<s> case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : assert ( MI -> getNumOperands ( ) >= <NUM_LIT> ) ; const MachineOperand & Reg = MI -> getOperand ( <NUM_LIT> ) ; assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & RegOrImm = MI -> getOperand ( <NUM_LIT> ) ; if ( RegOrImm . isImm ( ) ) break ; assert ( RegOrImm . isReg ( ) && <STR_LIT> ) ; assert ( RegOrImm . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( RegOrImm


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue Copy = Op0 -> getOperand ( <NUM_LIT> ) ; if ( Copy . getValueType ( ) == <STR_LIT> && Copy -> getOpcode ( ) == <STR_LIT> ) { SDValue Ops [ ] = { Copy -> getOperand ( <NUM_LIT> ) , Copy -> getOperand ( <NUM_LIT> ) } ; SDValue NewCopy = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Ops ) ; return NewCopy ; } } APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Op0 , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue (


<s> if ( modifiesConditionCode ( MI , CmpInstr , CheckOnlyCCWrites , TRI ) ) return false ; unsigned NewOpc = MI -> getOpcode ( ) ; switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } bool IsSafe = false ; for ( MachineBasicBlock :: iterator I = CmpInstr , E = CmpInstr -> getParent ( ) -> end ( ) ; ! IsSafe && ++ I != E ; ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! IsSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { IsSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { IsSafe = true ; break ; } unsigned Opc = Instr . getOpcode ( ) ; <STR_LIT> CC ; switch ( Opc ) { default : return false ; case <STR_LIT> : CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; } switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( Next != StringRef :: npos ) { size_t Dot = Name . find ( '.' , Next + <NUM_LIT> ) ; StringRef Format = Name . slice ( Next , Dot ) ; if ( Dot == StringRef :: npos ) Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; else { if ( Name . startswith ( <STR_LIT> ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , NameLoc ) ) ; int Cc = ConvertCcString ( Format ) ; if ( Cc == - <NUM_LIT> ) { return Error ( NameLoc , <STR_LIT> ) ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( )


<s> B . setInstrAndDebugLoc ( MI ) ; ApplyFn ( B , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent


<s> if ( parseOperand ( Operands , Name ) ) return true ; while ( parseOptionalToken ( AsmToken :: Comma ) ) if ( parseOperand ( Operands , Name ) ) return true ; if ( parseOptionalToken ( AsmToken :: EndOfStatement


<s> case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default :


<s> switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ( ( Subtarget -> hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ) && isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue N000 = N0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue FPConst = DAG . getBitcast ( VT , N0 . getOperand (


<s> void <ISA_LIT>FlagsCopyLoweringPass :: rewriteCMov ( MachineBasicBlock & TestMBB , MachineBasicBlock :: iterator TestPos , const DebugLoc & TestLoc , MachineInstr & CMovI , MachineOperand & FlagUse , CondRegArray & CondRegs ) { <STR_LIT> Cond = <STR_LIT> ( CMovI ) ; unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc ( ) , CondReg ) ; CMovI . getOperand ( CMovI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . setImm (


<s> return ( int32_t ( Value ) & <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , E , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT>


<s> thunk_name = thunk_name_buf ; } else thunk_name = NULL ; if ( sibcall_p ) { if ( thunk_name != NULL ) { if ( need_prefix == indirect_thunk_prefix_bnd ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; } else output_indirect_thunk ( need_prefix , regno ) ; } else { if ( thunk_name != NULL ) { if ( need_prefix == indirect_thunk_prefix_bnd ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; return ; } char indirectlabel1 [ <NUM_LIT> ] ; char indirectlabel2 [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; if ( need_prefix == indirect_thunk_prefix_bnd ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( thunk_name != NULL


<s> break ; case EQ : case NE : if ( op1 != const0_rtx ) return false ; op1 = const1_rtx ; code = ( code == EQ ? LTU : GEU ) ; break ; case GTU : case LEU : if ( CONST_INT_P ( op1 ) ) { op1 = gen_int_mode ( INTVAL ( op1 ) + <NUM_LIT> , GET_MODE ( op0 ) ) ; if ( op1 == const0_rtx || ! x86_64_immediate_operand ( op1 , GET_MODE ( op1 ) ) ) return false ; code = ( code == GTU ? GEU : LTU ) ; } else { std :: swap ( op0 , op1 ) ; code = ( code == GTU ? LTU : GEU ) ; } break ; case LT : case GE : if ( mode == DImode || op1 != const0_rtx ) return false ; op1 = gen_int_mode ( <NUM_LIT> << ( GET_MODE_BITSIZE ( mode ) - <NUM_LIT> ) , mode ) ; code = ( code == LT ? GEU : LTU ) ; break ; case LE : case GT : if ( mode == DImode || op1 != constm1_rtx


<s> if ( ! shouldUseHorizontalOp ( true , DAG , Subtarget ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS != RHS && LHS . getOpcode ( ) == N -> getOpcode ( ) && LHS . getOpcode ( ) == RHS . getOpcode ( ) && LHS . getValueType ( ) == RHS . getValueType ( ) && N -> isOnlyUserOf ( LHS . getNode ( ) ) && N -> isOnlyUserOf ( RHS . getNode ( ) ) ) { SDValue LHS0 = LHS . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = LHS . getOperand ( <NUM_LIT> ) ; SDValue RHS0 = RHS . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = RHS . getOperand ( <NUM_LIT> ) ; if ( ( LHS0 == LHS1 || LHS0 . isUndef ( ) || LHS1 . isUndef ( ) ) && ( RHS0 == RHS1 || RHS0 . isUndef ( ) || RHS1 . isUndef ( ) ) ) { SDLoc DL ( N ) ; SDValue Res = DAG . getNode ( LHS . getOpcode ( ) , DL , LHS . getValueType ( ) , LHS0 . isUndef ( ) ? LHS1 : LHS0 , RHS0 . isUndef ( ) ? RHS1 : RHS0 ) ; MVT ShufVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; Res = DAG . getBitcast ( ShufVT , Res ) ; SDValue NewLHS = DAG . getNode ( <STR_LIT> , DL , ShufVT , Res , getV4<ISA_LIT>ShuffleImm8ForMask ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , DL , DAG ) ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , ShufVT , Res , getV4<ISA_LIT>ShuffleImm8ForMask ( { <NUM_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static MCOperand create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VariantKind Kind , MCSymbol * Sym , MCContext & OutContext ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Sym , OutContext ) ; const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: Create ( Kind , MCSym


<s> assert ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; case <NUM_LIT> : if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits | <NUM_LIT> , <STR_LIT> ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits | <NUM_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : { uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) Val |= BitMask ; else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) return SDValue ( ) ; BitMask <<= <NUM_LIT> ; } return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } default : llvm_unreachable ( <STR_LIT>


<s> if ( TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ( DECL_INITIAL ( decl ) == <NUM_LIT> || DECL_INITIAL ( decl ) == error_mark_node ) ) { if ( TREE_PUBLIC ( decl ) && DECL_NAME ( decl ) ) targetm . asm_out . globalize_label ( stream , name ) ; switch_to_section ( readonly_data_section ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; mips_declare_object ( stream , name , <STR_LIT> , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , size ) ; } else mips_declare_common_object ( stream , name , <STR_LIT> , size


<s> const TargetLowering * TLI = TM . getTargetLowering ( ) ; O << * static_cast < const <ISA_LIT>TargetLowering * > (

TLI ) -> getPICBaseSymbol ( MF , OutContext ) ;


<s> return __builtin_ia32_divph512_mask ( __B , __C , _mm512_setzero_ph ( ) ,


<s> else { HOST_WIDE_INT value = INTVAL ( operands [ <NUM_LIT> ] ) ; HOST_WIDE_INT value_hi_lo [ <NUM_LIT> ] ; gcc_assert ( ! complement_final_p ) ; gcc_assert ( ! complement_op1_p ) ; gcc_assert ( ! complement_op2_p ) ; value_hi_lo [ hi ] = value >> <NUM_LIT> ; value_hi_lo [ lo ] = value & lower_32bits ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { HOST_WIDE_INT sub_value = value_hi_lo [ i ] ; if ( sub_value & sign_bit ) sub_value |= upper_32bits ; op2_hi_lo [ i ] = GEN_INT ( sub_value ) ; if ( code == AND && sub_value != - <NUM_LIT> && sub_value != <NUM_LIT> && ! and_operand ( op2_hi_lo [ i ] , SImode ) ) op2_hi_lo [ i ] = force_reg ( SImode , op2_hi_lo [ i ] ) ; } } } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( ( code == IOR || code == XOR ) && GET_CODE ( op2_hi_lo [ i ] ) == CONST_INT && ! complement_final_p && ! complement_op1_p && ! complement_op2_p && ! logical_const_operand ( op2_hi_lo [ i ] , SImode ) ) { HOST_WIDE_INT value = INTVAL ( op2_hi_lo [ i ] ) ; HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C ( <NUM_LIT> ) ; HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C (


<s> if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( canUseRedZone ( MF ) ) return false ; if ( hasVarSizedRegions ( MF ) ) return false ; return true


<s> case LTGT : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return true ; default : gcc_unreachable ( )


<s> unsigned int elt = <NUM_LIT> - ( sel [ i ] & <NUM_LIT> ) ; perm [ i ] = GEN_INT ( elt ) ; } if ( ! REG_P ( op0 ) ) op0 = force_reg ( V16QImode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( V16QImode , op1 ) ; constv = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( <NUM_LIT> , perm ) ) ; constv = force_reg ( V16QImode , constv ) ; unspec = gen_rtx_UNSPEC ( V16QImode , gen_rtvec ( <NUM_LIT> , op1 , op0 ,


<s> unsigned Reg ; SMLoc DummyLoc ; if ( ParseRegister ( Reg , DummyLoc , DummyLoc ) || parseEOL


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( StringRef TT , StringRef CPU , StringRef FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) , CPUString ( CPU ) { initializeSubtargetFeatures ( CPU ,


<s> rtx addr_new_pattern = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , addr_new_set , addr_use ) ) ; validate_change ( addr_insn , & PATTERN ( addr_insn ) , addr_new_pattern , false ) ; rtvec v_store = gen_rtvec ( <NUM_LIT> , reg , label_num ) ; rtx new_store = gen_rtx_UNSPEC ( mem_mode , v_store , UNSPEC_PCREL_OPT_ST_RELOC ) ; rtx new_store_set = gen_rtx_SET ( mem , new_store ) ; rtx store_clobber = gen_rtx_CLOBBER ( VOIDmode , addr_reg ) ; rtx new_store_pattern = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , new_store_set , store_clobber ) ) ; validate_change ( store_insn , & PATTERN ( store_insn ) , new_store_pattern , false ) ; if ( ! apply_change_group ( ) ) { counters . failed_stores ++ ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( addr_insn ) , INSN_UID ( store_insn ) ) ; return ; } counters . stores


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; return ! Subtarget -> isThumb1Only (


<s> unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = EmitIntExt ( SrcVT . getSimpleVT ( ) , SrcReg , <STR_LIT> , ! Signed ) ; if ( ! SrcReg


<s> const CCState & getCCInfo ( ) const { return CCInfo


<s> unsigned getHiLo16ImmOpValue ( const MachineInstr & MI ,


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT>


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addImm ( CI -> getZExtValue ( ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg ) ; return true ; } case <STR_LIT> : { DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress ( ) && <STR_LIT> ) ; if ( ! <ISA_LIT>SelectAddress ( DI -> getAddress ( ) , AM ) ) return false ; const TargetInstrDesc & II = TII . get ( TargetOpcode :: DBG_VALUE ) ; addFullAddress ( BuildMI ( MBB , DL , II ) , AM ) . addImm ( <NUM_LIT> ) . addMetadata ( DI -> getVariable ( ) ) ; return true ; } case <STR_LIT> : { BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned DestReg1 = UpdateValueMap ( & I , ResultReg ) ; if ( DestReg1 != ResultReg ) ResultReg = DestReg1 + <NUM_LIT> ; else ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; if ( I . getIntrinsicID ( ) == <STR_LIT> )


<s> return ( __m64 ) __builtin_ia32_pfadd ( ( __v2sf ) __A ,


<s> MCStreamer * S = new <ISA_LIT>MCAsmStreamer ( Context , std :: move ( FOut ) , Options . MCOptions . AsmVerbose , InstPrinter , Options . MCOptions . ShowMCInst ) ; return S


<s> if ( CSKY_VREG_P ( dstreg ) ) return <NUM_LIT> ; return <NUM_LIT> ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { split_double ( src , operands + <NUM_LIT> , operands + <NUM_LIT> ) ; if ( CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) && CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) && REGNO ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT> ; } } else if ( GET_CODE ( dst ) == MEM && GET_CODE ( src ) == REG ) { rtx memexp = XEXP ( dst , <NUM_LIT> ) ; int srcreg = REGNO ( src ) ; int offset = - <NUM_LIT> ; if ( CSKY_VREG_P ( srcreg ) ) return <NUM_LIT> ; if ( GET_CODE ( memexp ) == REG ) offset = <NUM_LIT> ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) offset = INTVAL ( XEXP ( memexp , <NUM_LIT> ) ) ; else if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) offset = INTVAL ( XEXP ( memexp , <NUM_LIT> ) ) ; else gcc_unreachable (


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op .


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI .


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , DL ( computeDataLayout ( is64bit ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo (


<s> EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister (


<s> return ( __builtin_sh_media_LDHI_Q ( ( char * ) p + <NUM_LIT> ) | __builtin_sh_media_LDLO_Q ( p ) ) ; return ( __builtin_sh_media_LDLO_Q ( ( char * ) p +

<NUM_LIT> ) | __builtin_sh_media_LDHI_Q ( p ) ) ;


<s> unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool

( ) , false , false , false , <NUM_LIT> ) ;


<s> uint8_t BitA = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitB = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitC = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitD = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitE = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitF = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT> ; EncVal |= BitB ; EncVal <<= <NUM_LIT> ; EncVal |= BitC ; EncVal <<= <NUM_LIT> ; EncVal |= BitD ; EncVal <<= <NUM_LIT> ; EncVal |= BitE ; EncVal <<= <NUM_LIT>


<s> if ( TT . getArch ( ) == Triple :: x86_64 ) return DWARFFlavour :: <ISA_LIT>_64 ; if ( TT . isOSDarwin ( ) ) return isEH ? DWARFFlavour :: <ISA_LIT>_32_DarwinEH : DWARFFlavour :: <ISA_LIT>_32_Generic ; if ( TT . isOSCygMing ( ) ) return DWARFFlavour :: <ISA_LIT>_32_Generic ; return DWARFFlavour ::


<s> rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , tmp , tmp , sel ) , UNSPEC_VPERM ) ; gcc_assert ( REG_P ( op0 ) ) ; emit_insn (


<s> void printS22ImmOperand ( const MachineInstr * MI , unsigned OpNo ) { int val = ( unsigned int ) MI -> getOperand ( OpNo ) . getImm ( ) ; if ( val >= <NUM_LIT> ) val = val -


<s> if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; Register DestReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I ,


<s> Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: aarch64_be ) IsLittleEndian = false ; PointerSize =


<s> MachineInstr * A15SDOptimizer :: elideCopies ( MachineInstr * MI ) { if ( ! MI -> isFullCopy ( ) ) return MI ; if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MachineInstr * Def = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! Def ) return nullptr ; return elideCopies ( Def


<s> void <ISA_LIT>InstPrinter :: printNoHashImmediate ( const MCInst * MI , unsigned OpNum


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i + <NUM_LIT> ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT>


<s> return true ; } while ( processInstruction ( Inst , Operands ) ) ; forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc ,


<s> if ( Op . getValueType ( ) != <STR_LIT> || ( hasHardQuad && TLI . isTypeLegal ( OpVT ) ) ) return SDValue ( ) ; return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: UINTTOFP_I32_F128 :

RTLIB :: UINTTOFP_I64_F128 ) , <NUM_LIT> ) ;


<s> static bool mep_repeat_loop_p ( struct mep_doloop * loop ) { struct mep_doloop_end * end ; rtx fallthrough ; if ( loop -> begin == <NUM_LIT> || loop -> end == <NUM_LIT> || loop -> begin -> next != <NUM_LIT>


<s> return __builtin_loongson_pinsrh_2_s ( s ,


<s> const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; MCOperand MCRegOP = MCOperand :: createReg ( MO . getReg ( ) ) ; if ( ! isPositionIndependent ( ) ) { switch ( TM . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , MCRegOP , OutContext , STI ) ; break ; case CodeModel :: Medium : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand lo = create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , GOTLabel , OutContext ) ; EmitOR ( * OutStreamer , MCRegOP , lo , MCRegOP , STI ) ; break ; } case CodeModel :: Large


<s> * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) < FIRST_PSEUDO_REGISTER && INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && reg_offset_p && ! SPE_VECTOR_MODE ( mode ) && ! ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) && ( quad_offset_p || ! VECTOR_MODE_P ( mode ) || VECTOR_MEM_NONE_P ( mode ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; HOST_WIDE_INT low = ( ( val & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; HOST_WIDE_INT high = ( ( ( val - low ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( high + low != val || ( quad_offset_p && ( low & <NUM_LIT> ) ) ) { * win = <NUM_LIT> ; return x ; } x = gen_rtx_PLUS ( GET_MODE ( x ) , gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high ) ) , GEN_INT ( low ) ) ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( x ) ; } push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == SYMBOL_REF && reg_offset_p && ! quad_offset_p && ( ! VECTOR_MODE_P ( mode ) || VECTOR_MEM_NONE_P ( mode ) ) && ! SPE_VECTOR_MODE ( mode ) && DEFAULT_ABI == ABI_DARWIN && ( flag_pic || MACHO_DYNAMIC_NO_PIC_P ) && machopic_symbol_defined_p ( x ) && DEFAULT_ABI == ABI_V4 && ! flag_pic && ! reg_addr [ mode ] . scalar_in_vmx_p && mode != TFmode && mode != TDmode && mode != IFmode && mode != KFmode && ( mode != TImode || ! TARGET_VSX_TIMODE ) && mode != PTImode && ( mode != DImode || TARGET_POWERPC64 ) && ( ( mode != DFmode && mode != DDmode ) || TARGET_POWERPC64 || ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) ) ) { if ( flag_pic ) { rtx offset = machopic_gen_offset ( x ) ; x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_HIGH ( Pmode , offset ) ) , offset ) ; } else x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT , const MachineFunction & ) const { Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT>

) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> StringRef Name = ELFAttrs :: attrTypeAsString ( Attribute , <STR_LIT> ) ; if ( ! Name . empty ( ) ) OS


<s> if ( TARGET_LONG_DOUBLE_128 ) { if ( ! TARGET_IEEEQUAD ) init_float128_ibm ( TFmode ) ; else init_float128_ieee ( TFmode )


<s> return ( __m64 ) __builtin_arm_wsubw ( ( __v2si ) __m1 , ( __v2si )


<s> SDLoc DL ( Op ) ; unsigned CCValid , CCMask ; SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCValid , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCValid , <STR_LIT> ) ) ; Ops . push_back ( DAG . getConstant ( CCMask ,


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , <NUM_LIT> ) , adj . offset_adjust , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return


<s> const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const unsigned globalRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; globalRegs [ i ] != <NUM_LIT> ; ++ i ) { unsigned reg = globalRegs


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> static unsigned Get<ISA_LIT>RegNum ( const MCOperand & MO


<s> vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , adjust ) ) ; for ( i = <NUM_LIT> ; i < count - <NUM_LIT> ; i ++ ) XVECEXP ( vector , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == <NUM_LIT> ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; XVECEXP ( vector , <NUM_LIT> , count - <NUM_LIT> ) = ret_rtx ; return


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI ) { EmitSled ( MI , SledKind ::


<s> emitInst ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( CLI . Ins , RetCC_<ISA_LIT> , CLI . RetTy , CLI . Symbol ? CLI . Symbol -> getName ( ) . data ( ) : nullptr ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] .


<s> return ( ( qword ) ( vec_sub ( vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT> ) ,


<s> if ( TARGET_MMX ) ix86_init_mmx_sse_builtins (


<s> CalleeFn = dyn_cast < Function > ( G -> getGlobal ( ) ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; const char * CalleeName = E


<s> return AM2Opc & ( ( <NUM_LIT> << <NUM_LIT> )


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new

Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( computeDataLayout ( Subtarget ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm &


<s> OperandMatchResultTy parseBDXAddr64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands


<s> SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , VSrc . getValueType ( ) , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; return ResNode


<s> auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI . memoperands ( ) ) ; SetCCI . eraseFromParent


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , STI , O ) && ! print<ISA_LIT>AliasInstr ( MI , STI , O ) ) printInstruction ( MI


<s> MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; SDValue Src0 = N -> getSrc0 ( ) ; Src0 = ExtendToType ( Src0 , WideDataVT , DAG ) ; MVT MaskEltTy = Mask . getSimpleValueType ( ) . getScalarType ( ) ; assert ( ( MaskEltTy == <STR_LIT> || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( MaskEltTy , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; if ( MaskEltTy != <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) , Mask ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , Src0 , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Exract , NewLoad . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps ,


<s> unsigned ADDIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned LISInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ORIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt


<s> if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath )


<s> case <STR_LIT> : LibCall = is64Bit ? <STR_LIT> : <STR_LIT> ; break ; } SDValue Callee = DAG . getExternalSymbol ( LibCall , getPointerTy ( ) ) ; Type * RetTy = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; ArgListTy Args ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = LowerF128_LibCallArg ( Chain , Args , LHS , DL , DAG ) ; Chain = LowerF128_LibCallArg ( Chain , Args , RHS , DL , DAG ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , RetTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , Callee , Args , DAG , DL ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT>


<s> void addRegShiftedImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg ) ) ; unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ? <NUM_LIT> : RegShiftedImm . ShiftImm ) ; Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> (


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( const auto & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( ! canDefBePartOfLOH ( & MI ) ) continue ; for ( MachineInstr :: const_mop_iterator IO = MI . operands_begin ( ) , IOEnd = MI . operands_end ( ) ; IO != IOEnd ; ++ IO ) { if ( ! IO -> isReg ( ) || ! IO -> isDef ( ) ) continue ; unsigned CurReg = IO -> getReg (


<s> temp = * cum ; if ( iq2000_function_arg ( pack_cumulative_args ( & temp ) , mode , type , named ) != <NUM_LIT> ) return <NUM_LIT> ; } if ( type == NULL_TREE || mode == DImode || mode == DFmode ) return <NUM_LIT> ; size = int_size_in_bytes ( type


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ==


<s> static SDValue PerformMSTORECombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { MaskedStoreSDNode * Mst = cast < MaskedStoreSDNode > ( N ) ; if ( ! Mst -> isTruncatingStore ( ) ) return SDValue ( ) ; EVT VT = Mst -> getValue ( ) . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT

. getScalarType ( ) , NumElems * SizeRatio ) ;


<s> void <ISA_LIT>InstPrinter :: printCImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm


<s> bool Changed = false ; SmallSetVector < Function * , <NUM_LIT> > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case <STR_LIT>


<s> if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return ( STI . useThumbBacktraces ( ) || STI . isThumb ( ) ) ? <STR_LIT> : <STR_LIT> ; else return <STR_LIT>


<s> return __builtin_aarch64_floatsihf (


<s> if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB


<s> canSimplifyCallFramePseudos ( MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter (


<s> return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return false ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond


<s> if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; if ( VT == <STR_LIT> ) Addr . Offset = ( <ISA_LIT>SubTarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI .


<s> return ( TM . getRelocationModel ( ) != Reloc :: Static ? Reloc :: LocalOrGlobal :


<s> return false ; } int Num1s = ( ImmS & ( Width - <NUM_LIT> ) ) + <NUM_LIT> ; if ( Num1s == Width ) return false ; int Rotation = ( ImmR & ( Width - <NUM_LIT> ) ) ; uint64_t Mask = ( <NUM_LIT> << Num1s ) - <NUM_LIT> ; uint64_t WidthMask = Width == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << Width ) - <NUM_LIT> ; Mask = ( Mask >> Rotation ) | ( ( Mask << ( Width - Rotation ) ) & WidthMask ) ; Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < RegWidth / Width ;


<s> virtual const char * getPassName ( )


<s> bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT . getVectorNumElements ( ) ; ++ k ) { ConstantSDNode * CN0 = dyn_cast < ConstantSDNode > ( BVN0 -> getOperand ( k ) ) ; ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( BVN1 -> getOperand ( k ) ) ; if ( ! CN0 || ! CN1 || CN0 -> getZExtValue ( ) != ( BitMask & ~ CN1 -> getZExtValue ( ) ) ) { FoundMatch = false ; break ; } } if ( FoundMatch ) return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( BVN0 , <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> - i ) , N1 -> getOperand ( <NUM_LIT> - j ) ) ; } return SDValue ( )


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo


<s> SDValue AddrOp ; if ( LDN || ( MIN && MIN -> getOpcode ( ) == <STR_LIT> ) ) AddrOp = N -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOpcode

( ) == <STR_LIT> ? AddrOp . getOperand ( <NUM_LIT> ) :


<s> bool loongarch_signed_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = <NUM_LIT> ) { x += <NUM_LIT> << ( bits + shift -


<s> const ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsO32 ( ) )


<s> machine_mode mode = GET_MODE ( x ) ; if ( mode == VOIDmode ) return false ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr <


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > MaxVal ) { TokError ( <STR_LIT> + utostr ( MaxVal ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = LookupByEncoding ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM . getValueOr ( <STR_LIT> ) , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = LookupByName ( Tok . getString ( ) ) ; if ( ! PRFM ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( * PRFM , Tok . getString ( ) , S , getContext ( ) ) ) ; Lex ( ) ; return MatchOperand_Success


<s> MachineBasicBlock * BeforePrev = Before -> getPrevNode ( ) ; assert ( BeforePrev && <STR_LIT> ) ; MachineFunction * F = BB -> getParent ( ) ; BB -> moveBefore ( Before ) ; auto FixFallthrough = [ & ] ( MachineBasicBlock * From , MachineBasicBlock * To ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> ) ; assert ( From -> isSuccessor ( To ) && <STR_LIT> ) ; MachineInstr & Terminator = * ( -- From -> terminators ( ) . end ( ) ) ; if ( ! Terminator . isUnconditionalBranch ( ) ) { MachineInstrBuilder MIB = BuildMI ( From , Terminator . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addMBB ( To ) ; MIB . addImm ( <STR_LIT> :: AL ) ; MIB . addReg ( <STR_LIT>


<s> CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ? <NUM_LIT> :


<s> if ( ! DestSrc ) return None ; Register DestReg = DestSrc -> Destination -> getReg ( ) ; Register SrcReg = DestSrc -> Source -> getReg ( ) ; auto Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , { } ) ; if ( DestReg == DescribedReg ) return ParamLoadedValue ( MachineOperand :: CreateReg


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore

, MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;


<s> SDLoc dl ( N ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> ) { SDValue CondSrc = Cond -> getOperand ( <NUM_LIT> ) ; if ( CondSrc -> getOpcode ( ) == <STR_LIT> ) Cond = CondSrc -> getOperand ( <NUM_LIT> ) ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue


<s> bool <ISA_LIT>BaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( STI .

getFramePointerReg ( ) ) ) return false ;


<s> if ( TripCount == - <NUM_LIT> ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( )


<s> } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { Register TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill = true ; } return fastEmitInst_rii ( Opc , RC , Op0 , Op0IsKill


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , raw_ostream & O ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( O , MAI ) ; if ( SyntaxVariant == <NUM_LIT> ) return

new <ISA_LIT>IntelInstPrinter ( O , MAI ) ;