<s> if ( ! DefMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; const MCInstrDesc & DefMCID = DefMI . getDesc ( ) ; if ( DefMCID . hasOptionalDef ( ) ) { unsigned NumOps = DefMCID . getNumOperands ( ) ; const MachineOperand & MO = DefMI . getOperand ( NumOps - <NUM_LIT> ) ; if ( MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return false ; } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ?


<s> if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < XVECLEN ( out_pat , <NUM_LIT> ) ; i ++ ) { out_exp = XVECEXP ( out_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } else { in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( i = <NUM_LIT> ; i < XVECLEN ( in_pat , <NUM_LIT> ) ; i ++ ) { in_exp = XVECEXP ( in_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET


<s> if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == <NUM_LIT> ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) + <NUM_LIT> ) ; return mep_expand_setcc_1 ( LT , dest , op1 , op2 ) ; case LEU : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == - <NUM_LIT> ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) + <NUM_LIT> , SImode ) ) ; return mep_expand_setcc_1 ( LTU , dest , op1 , op2 ) ; case GE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == trunc_int_for_mode ( <NUM_LIT> , SImode ) ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) -


<s> if ( frame_size > PROBE_INTERVAL && frame_size > STACK_CHECK_PROTECT ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size - STACK_CHECK_PROTECT ) ; } else if ( frame_size > <NUM_LIT> ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size ) ; } if ( offset >= <NUM_LIT> ) { offset = hard_fp_offset ; if ( offset >= <NUM_LIT> ) offset = cfun -> machine -> frame . saved_regs_size ; frame_size -= ( offset + crtl -> outgoing_args_size ) ; fp_offset = <NUM_LIT> ; if ( frame_size >= <NUM_LIT> ) { rtx op0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; emit_move_insn ( op0 , GEN_INT ( - frame_size ) ) ; insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , op0 ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - frame_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( frame_size > <NUM_LIT> ) { int hi_ofs = frame_size & <NUM_LIT> ; int lo_ofs = frame_size & <NUM_LIT> ; if ( hi_ofs ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - hi_ofs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( lo_ofs ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - lo_ofs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } else frame_size = - <NUM_LIT> ; if ( offset > <NUM_LIT> ) { bool skip_wb = false ; if ( frame_pointer_needed ) { skip_wb = true ; if ( fp_offset ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; aarch64_save_callee_saves ( DImode , fp_offset , R29_REGNUM , R30_REGNUM , false ) ; } else aarch64_pushwb_pair_reg ( DImode , R29_REGNUM , R30_REGNUM , offset ) ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_offset


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsSHL ( uint64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { unsigned Shamt = countTrailingZeros ( Imm ) ; GetInstSeqLs ( Imm >> Shamt , RemSize - Shamt , SeqLs


<s> if ( regno == RETURN_ADDR_REGNUM ) return


<s> static Value * CheckAndCreateOffsetAdd ( Value * X , Value * Y , Value * GEP , IRBuilder < > & Builder ) { auto FixSummands = [ & Builder ] ( FixedVectorType * & VT , Value * & NonVectorVal ) { ConstantInt * Const ; if ( ( Const = dyn_cast < ConstantInt > ( NonVectorVal ) ) && VT -> getElementType ( ) != NonVectorVal -> getType ( ) ) { unsigned TargetElemSize = VT -> getElementType ( ) -> getPrimitiveSizeInBits ( ) ; uint64_t N = Const -> getZExtValue ( ) ; if ( N < ( unsigned ) ( <NUM_LIT> << ( TargetElemSize - <NUM_LIT> ) ) ) { NonVectorVal = Builder . CreateVectorSplat ( VT -> getNumElements ( ) , Builder . getIntN ( TargetElemSize , N ) ) ; return ; } } NonVectorVal = Builder . CreateVectorSplat ( VT -> getNumElements ( ) , NonVectorVal ) ; } ; FixedVectorType * XElType = dyn_cast < FixedVectorType > ( X -> getType ( ) ) ; FixedVectorType * YElType = dyn_cast < FixedVectorType > ( Y -> getType ( ) ) ; if ( XElType && ! YElType ) { FixSummands ( XElType , Y ) ; YElType = cast < FixedVectorType > ( Y -> getType ( ) ) ; } else if ( YElType && ! XElType ) { FixSummands ( YElType , X ) ; XElType = cast < FixedVectorType > ( X -> getType ( ) ) ; } if ( XElType != YElType ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( XElType -> getElementType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) { Constant * ConstX = dyn_cast < Constant > ( X ) ; Constant * ConstY = dyn_cast < Constant > ( Y ) ; if ( ! ConstX || ! ConstY ) return nullptr ; unsigned TargetElemSize = <NUM_LIT> / XElType -> getNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i <

XElType -> getNumElements ( ) ; i ++ ) {


<s> if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; else if ( Value > <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ?


<s> void EmitARM64WinCFIEpilogEnd ( ) override { OS <<


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol (

Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ;


<s> SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> const Function & F = MF -> getFunction ( ) ; return isa < ScalableVectorType > ( F . getReturnType ( ) ) || any_of ( F . args ( ) , [ ] ( const Argument & Arg ) { return isa < ScalableVectorType > ( Arg . getType


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : noImmForm = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( ! noImmForm && isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned SReg = MF . getRegInfo ( ) . createVirtualRegister ( is64Bit ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( noImmForm ) OperandBase = <NUM_LIT> ; else if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode ) ) ; OperandBase = <NUM_LIT> ; } else { OperandBase = OffsetOperandNo ; } unsigned StackReg = MI . getOperand ( FIOperandNum ) . getReg ( ) ; MI . getOperand ( OperandBase ) . ChangeToRegister ( StackReg , false ) ; MI . getOperand ( OperandBase + <NUM_LIT> ) . ChangeToRegister ( SReg , false ,


<s> } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSplatShuffle ( II -> getOperand ( <NUM_LIT> ) ) ) Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; if ( isSplatShuffle ( II -> getOperand ( <NUM_LIT> ) ) ) Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; return ! Ops . empty ( ) ; case <STR_LIT> : if ( ! areOperandsOfVmullHighP64 ( II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ) return false ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 -> getOperand ( <NUM_LIT> ) , Ext2 -> getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; ShuffleVectorInst * Shuffle = dyn_cast < ShuffleVectorInst > ( Op ) ; if ( ! Shuffle || ! Shuffle -> isZeroEltSplat ( ) ) continue ; Value * ShuffleOperand = Shuffle -> getOperand ( <NUM_LIT> ) ; InsertElementInst * Insert = dyn_cast < InsertElementInst > ( ShuffleOperand ) ; if ( ! Insert ) continue ; Instruction * OperandInstr = dyn_cast < Instruction > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! OperandInstr ) continue ; ConstantInt * ElementConstant = dyn_cast < ConstantInt > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! ElementConstant || ElementConstant -> getZExtValue ( ) != <NUM_LIT> ) continue ; unsigned Opcode = OperandInstr -> getOpcode ( ) ; if ( Opcode != Instruction :: SExt && Opcode != Instruction :: ZExt ) continue ; Ops . push_back ( & Shuffle -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Op ) ; IsProfitable =


<s> return ( __m256 ) __builtin_ia32_sqrtps256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( )


<s> MI . addOperand ( MCOperand :: createImm ( <ISA_LIT>ValToCondCode ( cf , isIntegerBCKind ( MI ) ) ) ) ; return MCDisassembler


<s> int PossibleAluOpIdx = Offset + <NUM_LIT> ; int PossibleBaseIdx = Offset + <NUM_LIT> ; int PossibleDestIdx = Offset + <NUM_LIT> ; if ( <ISA_LIT>Operand * PossibleAluOp = static_cast < <ISA_LIT>Operand * > ( Operands [ PossibleAluOpIdx ] . get ( ) ) ) if ( PossibleAluOp -> isImm ( ) ) if ( const MCConstantExpr * ConstExpr = dyn_cast

< MCConstantExpr > ( PossibleAluOp -> getImm ( ) ) ) Modifies = LPAC :: modifiesOp ( ConstExpr -> getValue ( ) ) ;


<s> FunctionPass * llvm :: createFalkorMarkStridedAccessesPass (


<s> EVT PtrVT = getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , PtrVT ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return false ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; return true


<s> assert ( MOImm8 . isImm ( ) && <STR_LIT> ) ; uint32_t Imm8 = MOImm8 . getImm ( ) ; uint32_t Fraction = Imm8 & <NUM_LIT> ; uint32_t Exponent = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; uint32_t Negative = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; float Val = <NUM_LIT> + Fraction / <NUM_LIT> ; if ( Exponent & <NUM_LIT> ) { Val /= <NUM_LIT> << ( <NUM_LIT> - Exponent ) ; }


<s> return ( int16x8_t ) __builtin_neon_vqsubsv8hi (


<s> if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) ==


<s> return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; else return CSR_64_AllRegs_RegMask


<s> bool isActive ( ) const { return Active


<s> } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg

) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ;


<s> return m16_check_op ( op , ( - <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> ,


<s> if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT>


<s> else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < <NUM_LIT> ) nops = <NUM_LIT> ; else if ( TUNE_P6600 && TARGET_CB_MAYBE && ! optimize_size && ( ( mips_classify_branch_p6600 ( after ) == UC_BALC && mips_classify_branch_p6600 ( insn ) == UC_OTHER ) || ( mips_classify_branch_p6600 ( insn ) == UC_BALC && mips_classify_branch_p6600 ( after ) == UC_OTHER ) ) ) nops = <NUM_LIT> ; else nops = <NUM_LIT> ; * hilo_delay += nops ; rtx_insn * real_after = after ; if ( real_after && nops && CALL_P ( real_after ) ) while ( real_after && ( NOTE_P ( NEXT_INSN ( real_after ) ) || BARRIER_P ( NEXT_INSN ( real_after ) ) ) ) real_after = NEXT_INSN ( real_after ) ; while ( nops -- > <NUM_LIT> ) emit_insn_after ( gen_hazard_nop ( ) , real_after ) ; * hilo_delay += ninsns ; * delayed_reg = <NUM_LIT> ; * fs_delay = false ; if ( INSN_CODE ( insn ) >= <NUM_LIT> ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : if ( TUNE_P6600 && ! optimize_size && TARGET_CB_MAYBE && mips_classify_branch_p6600 ( insn ) == UC_OTHER ) * fs_delay = true ; break ; case HAZARD_FORBIDDEN_SLOT : if ( TARGET_CB_MAYBE ) * fs_delay = true ; break ; case HAZARD_HILO : * hilo_delay = <NUM_LIT> ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set ) ; * delayed_reg = SET_DEST ( set


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr


<s> if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } MCSubtargetInfo * X =


<s> return ( __m128i ) __builtin_ia32_cvttpd2dq ( ( __v2df )


<s> if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_bdz_si || icode == CODE_FOR_bdz_di || icode == CODE_FOR_bdnz_si || icode == CODE_FOR_bdnz_di || icode == CODE_FOR_bdztf_si || icode == CODE_FOR_bdztf_di || icode == CODE_FOR_bdnztf_si || icode == CODE_FOR_bdnztf_di ) ) return false ; return


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSectionImpl ( const GlobalObject * GO , const TargetMachine & TM ) const { const <ISA_LIT>Subtarget & Subtarget = * static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == <STR_LIT> || Section == <STR_LIT> ) return true ; return false ; } if ( ! LocalSData && GVA -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; if ( EmbeddedData && GVA -> isConstant ( ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized (


<s> return ( mode == HFmode ? true : default_scalar_mode_supported_p ( mode


<s> EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode ( <STR_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> mt_compute_frame_size ( get_frame_size ( ) ) ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return <NUM_LIT> ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return current_frame_info


<s> for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , Offset ) ) return MBBI ; TII -> trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] || UsedRegs [ BaseReg ]


<s> if ( Mask [ i ] < <NUM_LIT> ) continue ; int Val = ( i & <NUM_LIT> ) + NumElts * ( i & <NUM_LIT> ) ; int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i ] > Val + <NUM_LIT> ) ShufpdMask = false ; if ( Mask [ i ] < CommutVal || Mask [ i ] > CommutVal + <NUM_LIT> ) CommutableMask = false ; Immediate |= ( Mask [ i ] % <NUM_LIT>


<s> static int neon_endian_lane_map ( machine_mode mode , int lane ) { if ( BYTES_BIG_ENDIAN ) { int nelems = GET_MODE_NUNITS (


<s> assert ( allowAutoPadding ( ) && <STR_LIT> ) ; if ( OS . getAssembler ( ) . isBundlingEnabled ( ) ) return false ; if ( ! ( STI . hasFeature ( <STR_LIT> ) || STI . hasFeature ( <STR_LIT> ) ) ) return false ; return


<s> static bool mips_keep_interrupts_masked_p (


<s> if ( MatchAddress ( Addr , AM , false ) ) return false ; EVT VT = Addr . getValueType ( ) ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <STR_LIT> ) if ( AM . Base . Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <STR_LIT> ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity += <NUM_LIT> ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Disp && ( AM . Base . Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity += <NUM_LIT> ; if ( Complexity > <NUM_LIT> ) { getAddressOperands ( AM , Base , Disp , Index ) ; return true ; } return false


<s> void FixupLEAPass :: processInstructionForSLM ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr & MI = * I ; const int opcode = MI . getOpcode ( ) ; if ( ! isLEA ( opcode ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) return ; const unsigned DstR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; int addrr_opcode , addri_opcode ; switch ( opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = nullptr ; const MachineOperand & Dst = MI . getOperand


<s> const auto & MFI = MF . getFrameInfo ( ) ; return MFI . getObjectOffset ( FI )


<s> unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm


<s> static unsigned getMinCallArgumentsSize ( bool LP64 , bool isMacho ) { if ( isMacho ) return <NUM_LIT> * ( LP64 ? <NUM_LIT> : <NUM_LIT> ) ; return <NUM_LIT>


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter (

TM , Streamer ) , MCInstLowering ( * this ) {


<s> assert ( SymExpr -> getSymbol ( ) . getName ( ) == <STR_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; } MCFixupKind fixupKind = ( MCFixupKind ) <STR_LIT> ; if ( const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { if ( SExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 ) fixupKind = ( MCFixupKind ) <STR_LIT> ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , fixupKind ) ) ; return


<s> if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT ANDVT = VT . is128BitVector (


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> get ( ADDU ) , RA ) . addReg


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc DL ; const unsigned HipeLeafWords = <NUM_LIT> ; const unsigned CCRegisteredArgs = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; const unsigned Guaranteed = HipeLeafWords * SlotSize ; unsigned CallerStkArity = MF . getFunction ( ) -> arg_size ( ) > CCRegisteredArgs ? MF . getFunction ( ) -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; unsigned MaxStack = MFI -> getStackSize ( ) + CallerStkArity * SlotSize + SlotSize ; assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of (

<STR_LIT> ) == StringRef :: npos ) continue ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( getThe<ISA_LIT>Target ( ) ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target (


<s> bool RequiresBW ; bool HasAVX512Solution = isSupportedOnAVX512 ( VecTy , RequiresBW ) ; if ( ST -> hasAVX512 ( ) && HasAVX512Solution && ( ! RequiresBW || ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy ,


<s> switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget . is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , PtrVT ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , PtrVT ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , PtrVT , Subtarget . is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , PtrVT , model , Subtarget . is64Bit ( ) , PositionIndependent ) ; } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget . isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget . isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = PositionIndependent && ! Subtarget . is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , Chain . getValue ( <NUM_LIT> ) , DL ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; unsigned Reg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget . isTargetKnownWindowsMSVC ( ) || Subtarget . isTargetWindowsItanium ( ) || Subtarget . isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG .


<s> case ONEBYTE : dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP8_MAP : dec = & XOP8_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP9_MAP : dec = & XOP9_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOPA_MAP : dec = & XOPA_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEDNOW_MAP : dec = & THREEDNOW_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec


<s> set_optab_libfunc ( sdiv_optab , TFmode , <STR_LIT> ) ; } else { set_optab_libfunc ( add_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , TFmode , <STR_LIT> ) ; } else { set_optab_libfunc ( add_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , TFmode , <STR_LIT> ) ; if ( TARGET_PPC_GPOPT || TARGET_POWER2 ) set_optab_libfunc ( sqrt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode


<s> assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if (


<s> result = build_variant_type_copy ( result ) ; add_builtin_type ( name , result ) ; return result


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) || ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) ) FrameReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; int64_t Offset ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) || <ISA_LIT>FI -> isGlobalRegFI ( FrameIndex ) ) Offset = spOffset ; else Offset = spOffset + ( int64_t ) stackSize ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ATReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>AnalyzeImmediate :: Inst LastInst ( <NUM_LIT> ,


<s> } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; <STR_LIT> AluOperator = static_cast < <STR_LIT> > ( Addr . getOpcode ( ) ) ; if ( AluOperator == <STR_LIT> ) { AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( ( RiMode && isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) || ( ! RiMode && isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } if ( AluOperator == <STR_LIT> && RiMode && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> Optional < MCFixupKind > <ISA_LIT>MCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_390_NONE ) . Case ( <STR_LIT> , ELF :: R_390_8 ) . Case ( <STR_LIT> , ELF :: R_390_16 ) . Case ( <STR_LIT> , ELF :: R_390_32 ) . Case ( <STR_LIT> , ELF :: R_390_64 )


<s> else if ( aarch64_evpc_zip ( d ) ) return true ; else if ( aarch64_evpc_uzp ( d ) ) return true ; else if ( aarch64_evpc_trn ( d ) ) return true ; else if ( aarch64_evpc_sel ( d ) ) return true ; if ( d -> vec_flags == VEC_SVE_DATA ) return aarch64_evpc_sve_tbl ( d ) ; else if ( d -> vec_flags == VEC_ADVSIMD ) return aarch64_evpc_tbl ( d


<s> assert ( RC && <STR_LIT> ) ; assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; unsigned OpCode = <STR_LIT> . hasSubClassEq ( RC ) ? <STR_LIT> : <STR_LIT> ; unsigned SelectPred = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned SubIdx ; bool SwapOps ; switch ( SelectPred ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; } unsigned FirstReg = SwapOps ? FalseReg : TrueReg , SecondReg = SwapOps ? TrueReg


<s> static const struct mips_cpu_info * mips_cpu_info_from_isa ( int isa ) { unsigned int i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ )

if ( mips_cpu_info_table [ i ] . isa == isa ) return mips_cpu_info_table + i ;


<s> unsigned CPELogAlign = getCPELogAlign ( U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ]


<s> assert ( llvm :: is_sorted ( MemoryFoldTable4 ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable4 ) , std :: end ( MemoryFoldTable4 ) ) == std :: end ( MemoryFoldTable4 ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( BroadcastFoldTable2 ) && std :: adjacent_find ( std :: begin ( BroadcastFoldTable2 ) , std :: end ( BroadcastFoldTable2 ) ) == std :: end ( BroadcastFoldTable2 ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( BroadcastFoldTable3 ) && std :: adjacent_find ( std :: begin ( BroadcastFoldTable3 ) , std :: end ( BroadcastFoldTable3 ) ) == std :: end ( BroadcastFoldTable3 ) && <STR_LIT> ) ; FoldTablesChecked . store ( true , std :: memory_order_relaxed ) ; } const <ISA_LIT>MemoryFoldTableEntry * Data = llvm :: lower_bound ( Table , RegOp ) ; if ( Data != Table . end ( ) && Data -> KeyOp == RegOp && ! ( Data -> Flags & TB_NO_FORWARD ) ) return Data ; return


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned Reg = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( Reg == <NUM_LIT> ) return MatchOperand_NoMatch ; RegNum = Reg ; Parser . Lex ( ) ; return


<s> ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( Is<ISA_LIT>64 ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS


<s> else if ( mode == DImode ) fn = gen_load_locked_di ; emit_insn ( fn ( reg


<s> case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp =


<s> break ; case COMPLEX_TYPE : mode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( mode != DFmode && mode != SFmode && mode != TFmode ) return - <NUM_LIT> ; if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case VECTOR_TYPE : size = int_size_in_bytes ( type ) ; switch ( size ) { case <NUM_LIT> : mode = V2SImode ; break ; case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count = count > sub_count ? count : sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count *


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned


<s> if ( ! getConstantValueForReg ( IdxReg , MRI , LaneIdx ) ) return false ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; MachineIRBuilder MIRBuilder ( I ) ; if ( VecSize < <NUM_LIT> ) { MachineInstr * ScalarToVec = emitScalarToVector ( VecSize , & <STR_LIT> , SrcReg , MIRBuilder ) ; if ( ! ScalarToVec ) return false ; SrcReg = ScalarToVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineInstr * InsMI = emitLaneInsert ( None , SrcReg , EltReg , LaneIdx , EltRB , MIRBuilder ) ; if ( VecSize < <NUM_LIT> ) { unsigned DemoteVec = InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = getMinClassForRegBank ( * RBI . getRegBank ( DemoteVec , MRI , TRI ) , VecSize ) ; if ( RC != & <STR_LIT> && RC != & <STR_LIT> ) { LLVM_DEBUG ( dbgs ( )


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> )


<s> static bool rs6000_lra_p ( void ) { return TARGET_LRA


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT>


<s> case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) ) UseFastISel = false ; return UseFastISel ? <STR_LIT> ( funcInfo , libInfo )


<s> void addImm1_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; unsigned AndOpc ; if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else return false ; unsigned DefReg = SrcReg ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) { DefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , DefReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } MachineInstr & AndInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( AndOpc ) , DstReg ) . addReg ( DefReg ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( AndInst , TII , TRI , RBI


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) CASE_OBF_MASK ( <NUM_LIT> ) case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return


<s> void <ISA_LIT>64LinuxTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM .


<s> MCCodeEmitter * llvm :: create<ISA_LIT>LEMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ,


<s> for ( auto BB = L -> block_begin ( ) , BE = L -> block_end ( ) ; BB != BE ; ++ BB ) if ( ! VisitedBlocks . count ( * BB ) ) Worklist . push_back ( * BB ) ; if ( auto PreHeader = L -> getLoopPreheader ( ) ) if ( ! VisitedBlocks . count ( PreHeader ) ) Worklist . push_back ( PreHeader ) ; while ( ! Worklist . empty ( ) ) { auto BB = Worklist . pop_back_val ( ) ; LoopOptimized |= Optimize_PreWhileConversion ( BB ) ; LoopOptimized |= Optimize_PostWhileConversion ( BB ) ; LoopOptimized |= Transform_StructAddressing ( BB ) ; VisitedBlocks . insert ( BB ) ; } ++ NumVisited


<s> if ( DAG . getSubtarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) return ( <NUM_LIT> / EltSize ) - <NUM_LIT> - ( SVOp -> getMaskElt ( <NUM_LIT> ) / EltSize ) ; else return SVOp -> getMaskElt (


<s> case MEMORY_IMM : OS << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case MEMORY_REG_IMM : OS << <STR_LIT> << getMemBaseReg ( ) << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case MEMORY_REG_REG : assert ( getMemOffset ( ) ==


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo (


<s> Inst . setLoc ( IDLoc ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] )


<s> switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>DarwinTargetAsmInfo ( ) ; default : return new <ISA_LIT>ELFTargetAsmInfo ( )


<s> void ix86_split_copysign_var ( rtx operands [ ] ) { enum machine_mode mode , vmode ; rtx dest , scratch , op0 , op1 , mask , nmask , x ; dest = operands [ <NUM_LIT> ] ; scratch = operands [ <NUM_LIT> ] ; op0 = operands [ <NUM_LIT> ] ; op1 = operands [ <NUM_LIT> ] ; nmask = operands [ <NUM_LIT> ] ; mask = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; if ( rtx_equal_p ( op0 , op1 ) ) { emit_move_insn ( dest , op0 ) ; return ; } if ( REG_P ( mask ) && REGNO ( dest ) == REGNO ( mask ) ) { gcc_assert ( REGNO ( op1 ) == REGNO ( scratch ) ) ; x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; dest = mask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , <NUM_LIT> ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = simplify_gen_subreg ( vmode , op1 , mode , <NUM_LIT> ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = simplify_gen_subreg ( vmode , op0 , mode , <NUM_LIT> ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; } else { gcc_assert ( REGNO ( nmask ) == REGNO ( dest ) ) ; dest = nmask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , <NUM_LIT> ) ; x = gen_rtx_AND ( vmode , dest , op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x


<s> call = get_call_rtx_from ( insn ) ; symbol = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF )


<s> return __builtin_aarch64_lroundv2dfv2di (


<s> return ( __m256i ) __builtin_ia32_paddd256_mask ( ( __v8si ) __A , ( __v8si )


<s> df_analyze ( ) ; shorten_branches ( get_insns ( ) ) ; pru_reorg_loop ( insns ) ; df_finish_pass ( false


<s> TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter )


<s> case Immediate : case ContextImmediate : if ( Signed ) return isInt < Width > ( getImmS16Context ( ) ) && ( getImmS16Context ( ) & ( Multiple - <NUM_LIT> ) )


<s> static void set_pic_reg_ever_live ( ) { if ( reload_in_progress ) df_set_regs_ever_live ( REGNO ( pic_offset_table_rtx


<s> bool hasVirtualTileReg ( ) const { return HasVirtualTileReg


<s> case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx


<s> } if ( TARGET_SSE_MATH ) { tree mxcsr_orig_var = create_tmp_var ( unsigned_type_node ) ; tree mxcsr_mod_var = create_tmp_var ( unsigned_type_node ) ; tree stmxcsr = ix86_builtins [ IX86_BUILTIN_STMXCSR ] ; tree ldmxcsr = ix86_builtins [ IX86_BUILTIN_LDMXCSR ] ; tree stmxcsr_hold_call = build_call_expr ( stmxcsr , <NUM_LIT> ) ; tree hold_assign_orig = build2 ( MODIFY_EXPR , unsigned_type_node , mxcsr_orig_var , stmxcsr_hold_call ) ; tree hold_mod_val = build2 ( BIT_IOR_EXPR , unsigned_type_node , mxcsr_orig_var , build_int_cst ( unsigned_type_node , <NUM_LIT> ) ) ; hold_mod_val = build2 ( BIT_AND_EXPR , unsigned_type_node , hold_mod_val , build_int_cst ( unsigned_type_node , <NUM_LIT> ) ) ; tree hold_assign_mod = build2 ( MODIFY_EXPR , unsigned_type_node , mxcsr_mod_var , hold_mod_val ) ; tree ldmxcsr_hold_call = build_call_expr ( ldmxcsr , <NUM_LIT> , mxcsr_mod_var ) ; tree hold_all = build2 ( COMPOUND_EXPR , unsigned_type_node , hold_assign_orig , hold_assign_mod ) ; hold_all = build2 ( COMPOUND_EXPR , void_type_node , hold_all , ldmxcsr_hold_call ) ; if ( * hold ) * hold = build2 ( COMPOUND_EXPR , void_type_node , * hold , hold_all ) ; else * hold = hold_all ; tree ldmxcsr_clear_call = build_call_expr ( ldmxcsr , <NUM_LIT> , mxcsr_mod_var ) ; if ( * clear ) * clear = build2 ( COMPOUND_EXPR , void_type_node , * clear , ldmxcsr_clear_call ) ; else * clear = ldmxcsr_clear_call ; tree stxmcsr_update_call = build_call_expr ( stmxcsr , <NUM_LIT> ) ; tree exceptions_sse = fold_convert ( integer_type_node , stxmcsr_update_call ) ; if ( * update ) { tree exceptions_mod = build2 ( BIT_IOR_EXPR , integer_type_node , exceptions_var , exceptions_sse ) ; tree exceptions_assign = build2 ( MODIFY_EXPR ,


<s> return ( uint32x2_t ) __builtin_neon_vrshluv2si ( (


<s> return ( Reg == <STR_LIT> || Reg == <STR_LIT> || ( Reg == <STR_LIT> &&


<s> bool isMemVZ64 ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg

( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( Target ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , Target -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( Target , BranchWeight ) ; return true ; } else if ( foldXALUIntrinsic ( CC , I , BI -> getCondition ( ) ) ) { unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( ! CondReg ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TBB , BranchWeight ) ; fastEmitBranch ( FBB , DbgLoc ) ; return true ; } unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondRegIsKill = hasTrivialKill ( BI -> getCondition ( ) ) ; emitICmp_ri ( <STR_LIT> , CondReg , CondRegIsKill , <NUM_LIT> ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CC = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI


<s> __v2du rshift , shmask ; const __v2du shmax = { <NUM_LIT> , <NUM_LIT> } ; __v2du result ; rshift = ( __v2du ) vec_splat ( ( __v2du ) __B , <NUM_LIT> ) ; shmask = rshift < shmax ; result = vec_vsrd ( ( __v2du


<s> static SDValue LowerFNEG ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI , bool is64Bit ) { if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF64Op ( Op , DAG ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , ( ( is64Bit ) ? <STR_LIT> : <STR_LIT> ) , <NUM_LIT> ) ; return


<s> return _mm_set_epi64 ( ( __m64 ) <NUM_LIT> ,


<s> SDValue Inner = N0 . getOperand ( <NUM_LIT> ) ; if ( SraAmt && Inner . hasOneUse ( ) && Inner . getOpcode ( ) == <STR_LIT> ) { if ( auto * ShlAmt = dyn_cast < ConstantSDNode > ( Inner . getOperand ( <NUM_LIT> ) ) ) { unsigned Extra = ( VT . getSizeInBits ( ) - N0 . getValueSizeInBits ( ) ) ; unsigned NewShlAmt = ShlAmt -> getZExtValue ( ) + Extra ; unsigned NewSraAmt = SraAmt -> getZExtValue ( ) + Extra ; EVT ShiftVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , SDLoc ( Inner ) , VT , Inner . getOperand ( <NUM_LIT> ) ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SDLoc ( Inner ) , VT , Ext , DAG . getConstant ( NewShlAmt , SDLoc ( Inner ) , ShiftVT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , VT , Shl

, DAG . getConstant ( NewSraAmt , SDLoc ( N0 ) , ShiftVT ) ) ;


<s> static const int Masks [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } , { <STR_LIT> , <NUM_LIT> , ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) , <STR_LIT> , } , { <STR_LIT> , ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) , <NUM_LIT> , <STR_LIT> , } , { <NUM_LIT> , ( <STR_LIT> | <STR_LIT> ) , ( <STR_LIT> | <STR_LIT> | <STR_LIT> ) , <STR_LIT> , } , { <NUM_LIT> , ( <STR_LIT> | <STR_LIT> | <STR_LIT> ) , ( <STR_LIT> | <STR_LIT> ) , <STR_LIT> , } } ; int Mask = <NUM_LIT> ; if ( Pred & CmpInst :: FCMP_OEQ ) Mask |= Masks [ WhichConst ] [ <NUM_LIT> ] ; if ( Pred & CmpInst :: FCMP_OGT ) Mask |= Masks [ WhichConst ] [ <NUM_LIT> ] ; if ( Pred & CmpInst :: FCMP_OLT ) Mask |= Masks [ WhichConst ] [ <NUM_LIT> ] ; if ( Pred & CmpInst :: FCMP_UNO ) Mask |= Masks [ WhichConst ] [ <NUM_LIT> ] ; bool Worthy = false ; if ( CallInst * CI = dyn_cast < CallInst > ( Op0 ) ) { Function * F = CI -> getCalledFunction ( ) ; if ( F && F -> getIntrinsicID ( ) == <STR_LIT>


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB (


<s> EVT CEltT = ( LHS . getValueType ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT CVT = EVT :: getVectorVT ( * DAG . getContext ( ) , CEltT , EltNum ) ; LHS = SDValue ( DAG . getMachineNode ( TargetOpcode :: SUBREG_TO_REG , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , LHS , DAG . getTargetConstant ( SubConstant , <STR_LIT> ) ) , <NUM_LIT> ) ; RHS = SDValue ( DAG . getMachineNode ( TargetOpcode :: SUBREG_TO_REG , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , RHS , DAG . getTargetConstant ( SubConstant , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue VSetCC = DAG . getSetCC ( dl , CVT , LHS , RHS , CC ) ; SDValue ResCC = LowerVectorSETCC ( VSetCC , DAG ) ; if ( CEltT . getSizeInBits ( ) < IfTrueVT . getSizeInBits ( ) ) { EVT DUPVT = EVT :: getVectorVT ( * DAG . getContext ( ) , CEltT , IfTrueVT . getSizeInBits ( ) / CEltT . getSizeInBits ( ) ) ; ResCC = DAG . getNode ( <STR_LIT> , dl , DUPVT , ResCC , DAG . getConstant ( <NUM_LIT> , <STR_LIT> , false ) ) ; ResCC = DAG . getNode ( <STR_LIT> , dl , CondVT , ResCC ) ; } else { assert ( CEltT . getSizeInBits ( ) == IfTrueVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned ExEltNum = EltNum * IfTrueVT . getSizeInBits ( ) / ResCC . getValueSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , CEltT , ExEltNum ) ; ResCC = DAG . getNode ( <STR_LIT> , dl , ExVT , ResCC , DAG . getConstant ( <NUM_LIT> , <STR_LIT> , false ) ) ; ResCC = DAG . getNode ( <STR_LIT> , dl , CondVT , ResCC ) ; } SDValue VSelect = DAG . getNode ( <STR_LIT> , dl , IfTrue . getValueType ( ) , ResCC , IfTrue , IfFalse ) ; return VSelect ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; EVT SEVT = <STR_LIT> ; if ( IfTrue . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) >


<s> if ( factor > <NUM_LIT> * <NUM_LIT> ) { int extra_shift = exact_log2 ( low_bit ) ; shift += extra_shift ; factor >>= extra_shift ; } val = gen_int_mode ( poly_int64 ( factor * <NUM_LIT> , factor * <NUM_LIT> ) , mode ) ; } else { if ( low_bit <= <NUM_LIT> * <NUM_LIT> ) factor /= low_bit ; else low_bit = <NUM_LIT> ; val = gen_int_mode ( poly_int64 ( low_bit * <NUM_LIT> , low_bit * <NUM_LIT> ) , mode ) ; val = aarch64_force_temporary ( mode , temp1 , val ) ; if ( can_create_pseudo_p ( ) ) { rtx coeff1 = gen_int_mode ( factor , mode ) ; val = expand_mult ( mode , val , coeff1 , NULL_RTX , true , true ) ; } else { if ( code == MINUS && src == const0_rtx ) { factor = - factor ; code = PLUS ; } rtx coeff1 = gen_int_mode ( factor , mode ) ; coeff1 = aarch64_force_temporary ( mode , temp2 , coeff1 ) ; val = gen_rtx_MULT ( mode , val , coeff1 ) ; } } if ( shift > <NUM_LIT> ) { val = aarch64_force_temporary ( mode , temp1 , val ) ; val = gen_rtx_ASHIFT ( mode , val , GEN_INT ( shift ) ) ; } else if ( shift == - <NUM_LIT> ) { val = aarch64_force_temporary ( mode , temp1 , val ) ; val = gen_rtx_ASHIFTRT ( mode , val , const1_rtx ) ; } if ( src != const0_rtx


<s> PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation =


<s> SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs


<s> SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , WideVT ) , BitShift ) ; if ( Opcode != <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( <NUM_LIT> - BitSize , WideVT ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( uint32_t ( - <NUM_LIT> ) >> BitSize , WideVT ) ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , Src2 , BitShift , NegBitShift , DAG . getConstant ( BitSize , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( Opcode , DL , VTList , Ops , array_lengthof ( Ops ) , NarrowVT , MMO ) ; SDValue ResultShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift , DAG . getConstant ( BitSize , WideVT ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , WideVT , AtomicOp , ResultShift ) ; SDValue RetOps [ <NUM_LIT> ] = { Result , AtomicOp . getValue (


<s> if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> || ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } } else if ( ConstantSDNode * ShAmt1C = dyn_cast < ConstantSDNode > ( ShAmt1 ) ) { ConstantSDNode * ShAmt0C = dyn_cast < ConstantSDNode > ( ShAmt0 ) ; if ( ShAmt0C && ( ShAmt0C -> getSExtValue ( ) + ShAmt1C -> getSExtValue ( ) ) == Bits ) return DAG . getNode ( Opc , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } else if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ) { unsigned InnerShift = ( <STR_LIT> == Opc ? <STR_LIT> : <STR_LIT> ) ; SDValue ShAmt1Op0 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op0 . getOpcode ( ) == <STR_LIT> ) ShAmt1Op0 = ShAmt1Op0 . getOperand ( <NUM_LIT> ) ; if ( MaskC -> getSExtValue ( ) == ( Bits - <NUM_LIT> ) && ShAmt1Op0 == ShAmt0 ) { if ( Op1 . getOpcode ( ) == InnerShift && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) { return DAG . getNode ( Opc , DL , VT , Op0 , Op1 . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } if ( InnerShift == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) ==


<s> const FeatureBitset & FeatureBits = Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ! FeatureBits [ <STR_LIT> ] || ! FeatureBits [ <STR_LIT> ] ) return MCDisassembler :: Fail ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT>

, <NUM_LIT> ) != <NUM_LIT> ) S = MCDisassembler :: SoftFail ;


<s> return ( unsigned ) ( Opcode & ~ BR_HINT_MASK


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O <<


<s> if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; bool is31 = ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) ; if ( is<ISA_LIT>64 ) return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , is31 ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) ; else return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl ,


<s> return V -> getType ( ) -> getScalarSizeInBits ( ) <


<s> static MCTargetStreamer * create<ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS

, MCInstPrinter * InstPrint , bool isVerboseAsm ) {


<s> static <STR_LIT> GetCondFromBranchOpc ( unsigned BrOpc ) { switch ( BrOpc ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> <ISA_LIT>AddressingMode AM ( <STR_LIT> , DR ) ; if ( ! selectAddress ( Addr , AM ) ) return false ; getAddressOperands ( AM , Addr . getValueType ( ) , Base , Disp ) ; return true


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI

-> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ;


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == Count - <NUM_LIT> ) LdrOpc = <STR_LIT> ; else LdrOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ i ] . getFrameIdx ( ) << <STR_LIT> << CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ; const int Offset = ( i == Count - <NUM_LIT> ) ? Count : Count - i - <NUM_LIT> ; assert ( ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) MIB . addReg ( <STR_LIT> , RegState :: Define ) ; MIB . addReg ( Reg2 , getDefRegState ( true ) ) . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT>


<s> unsigned CCMIOpc = CCMI -> getOpcode ( ) ; if ( CCMIOpc != TargetOpcode :: G_ICMP && CCMIOpc != TargetOpcode :: G_FCMP ) return false ; MachineIRBuilder MIB ( I ) ; Register LHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( CCMIOpc == TargetOpcode :: G_FCMP ) { emitFPCompare ( LHS , RHS , MIB ) ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CC1 , CC2 ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC1 ) . addMBB ( DestMBB ) ; if ( CC2 != <STR_LIT> ) MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC2 ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return true ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; MachineInstr * LHSMI = getDefIgnoringCopies ( LHS , MRI ) ; if ( VRegAndVal && LHSMI -> getOpcode ( ) != TargetOpcode :: G_AND ) { int64_t C = VRegAndVal -> Value ; if ( C == - <NUM_LIT> && Pred == CmpInst :: ICMP_SGT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , false , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } if ( C == <NUM_LIT> && Pred == CmpInst :: ICMP_SLT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , true , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } } if ( !


<s> RegisterTarget < Triple :: ppc , true > X ( getThe<ISA_LIT>32Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsDarwinABI = Subtarget . isDarwinABI ( ) ; if ( ( is<ISA_LIT>64 && VT != <STR_LIT> && VT != <STR_LIT> ) || ( ! is<ISA_LIT>64 && VT != <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; bool is64Bit = is<ISA_LIT>64 && VT == <STR_LIT> ; Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , is64Bit ? <STR_LIT> : <STR_LIT> ) . Case ( <STR_LIT> , ( IsDarwinABI || is<ISA_LIT>64 ) ? Register ( ) :

<STR_LIT> ) . Case ( <STR_LIT> , ( ! is<ISA_LIT>64 && IsDarwinABI ) ? Register ( ) :


<s> if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { unsigned Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * Paired ) ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; } else { DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent (


<s> const <ISA_LIT>Subtarget & Subtarget = * static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ; if ( ! Subtarget . isCheri (


<s> if ( const auto & Loc = MI . getDebugLoc ( ) ) if ( const auto * Samples = TopSamples -> findFunctionSamples ( Loc ) ) return Samples -> findCallTargetMapAt ( FunctionSamples :: getOffset ( Loc ) , Loc -> getBaseDiscriminator ( ) ) ; return std :: error_code (


<s> bool <ISA_LIT>GNULDBackend :: initTargetStubs ( ) { StubFactory * factory = getStubFactory ( ) ; if ( factory != NULL ) { factory -> addPrototype ( new <ISA_LIT>LongBranchStub ( config ( ) . isCodeIndep ( ) ) ) ; if ( config ( ) . targets


<s> void addAddSubImmNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * MCE = isShiftedImm ( ) ? getShiftedImmVal ( ) : getImm ( ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( MCE ) ; int64_t Val = - CE


<s> void ix86_bd_do_dispatch ( rtx_insn * insn , int mode ) { if ( mode == DISPATCH_INIT ) init_dispatch_sched ( ) ; else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window ( insn


<s> Optional < MCFixupKind > getFixupKind ( StringRef Name ) const override { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>ARC_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>ARC_8 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>ARC_16 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>ARC_32 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>ARC_64 ) . Default ( - <NUM_LIT> ) ; if ( Type == - <NUM_LIT> ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind


<s> CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( * pcum < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode , CSKY_FIRST_PARM_REGNUM + * pcum


<s> if ( Desc . getOpcode ( ) == <STR_LIT> ) Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ; return Size


<s> for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { TruncateToInt32 ( BG . V , dl ) , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , TruncateToInt32 ( BG . V , dl ) , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } } if ( LateMask ) { unsigned Mask = ( unsigned ) getZerosMask ( ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool isPCRel ) const { unsigned NumBytes = <NUM_LIT> ; Value = adjustFixupValue ( Fixup , Value ) ; if ( !


<s> CAOops . clear ( ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; addCastAndOpKind ( <STR_LIT> , <STR_LIT> , <STR_LIT> )


<s> assert ( nOps > <NUM_LIT> && <STR_LIT> ) ; SDValue Operand0 = N -> getOperand ( <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < nOps ; ++ i ) { if ( N -> getOperand ( i )


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo (


<s> if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes ( type


<s> assert ( ! Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , Op , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant (

<NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) , <NUM_LIT> , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , true ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , false ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , true ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , false ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return


<s> unsigned getPCAdjustment ( ) const { return PCAdjust


<s> auto * PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; auto * MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm (


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( UseCmp ) { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT>


<s> void <ISA_LIT>RegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { unsigned FIOperandNum = <NUM_LIT> ; while ( ! MI . getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectIntAddrSImm10Lsl3 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> , <NUM_LIT> ) ) return true ; return selectAddrDefault ( Addr , Base ,


<s> } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; MVT SVT = SrcVT . getSimpleVT ( ) ; MVT DVT = DstVT . getSimpleVT ( ) ; if ( ! SVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SVT . is256BitVector ( ) ) && ! ( Subtarget -> hasAVX512 ( ) && SVT . is512BitVector ( ) && ( Subtarget -> hasBWI ( ) || ( SVT . getScalarSizeInBits ( ) >= <NUM_LIT> && DVT . getScalarSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return


<s> else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( Mnemonic . upper ( ) + std :: string ( PRCTX -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( PRCTX -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } uint16_t PRCTX_Op2 = Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; assert ( PRCTX_Op2 && <STR_LIT> ) ; createSysAlias ( PRCTX -> Encoding << <NUM_LIT> | PRCTX_Op2 , Operands , S ) ; } Parser . Lex ( ) ; bool ExpectRegister = ( Op . lower ( ) . find ( <STR_LIT> ) == StringRef :: npos ) ; bool HasRegister = false ; if ( parseOptionalToken ( AsmToken


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ?


<s> Op -> BTIHint . Val = Val << <NUM_LIT> | <NUM_LIT> ; Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str


<s> df_ref ref = DF_REG_DEF_CHAIN ( REGNO (


<s> static void mips_sim_wait_insn ( struct mips_sim * state


<s> if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI -> hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! HasFP ) return Offset + StackSize ; Offset += SlotSize ; int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> )


<s> void <ISA_LIT>InstPrinter :: printBTIHintOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned btihintop = ( MI -> getOperand ( OpNum ) . getImm ( ) ^ <NUM_LIT> ) >> <NUM_LIT> ; auto BTI = <STR_LIT> ( btihintop ) ; if ( BTI ) O << BTI -> Name ; else O << '#' <<


<s> unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( JumpOffset


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return Opc


<s> unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( Op ) ; updateValueMap ( I , ResultReg ) ; return true


<s> ValueList RHS ; if ( IsNarrowSequence < <NUM_LIT> > ( MulOp0 , LHS ) && IsNarrowSequence


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( unsigned JTI = <NUM_LIT> , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; EmitAlignment ( Align ( Size ) ) ; OutStreamer -> EmitLabel ( GetJTISymbol ( JTI ) ) ; for ( auto * JTBB : JTBBs ) emitJumpTableEntry ( MJTI


<s> void mep_file_cleanups ( void ) { if ( pragma_htab ) pragma_htab -> traverse < void * , note_unused_pragma_disinterrupt