<s> tree function_resolver :: resolve_uniform_opt_n ( unsigned int nops ) { unsigned int i , nargs ; type_suffix_index type ; if ( ! check_gp_argument ( nops , i , nargs ) || ( type = infer_vector_type ( i ) ) ==


<s> Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT> ||


<s> if ( x > <NUM_LIT> ) return __clz_tab [ x >> <NUM_LIT>


<s> if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) && ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; return TargetTransformInfo :: getVectorInstrCost ( Opcode


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseMSA128BRegs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseMSARegs ( Operands , ( int


<s> bool <ISA_LIT>TargetLowering :: needsCmpXchgNb ( Type * MemType ) const { unsigned OpWidth = MemType -> getPrimitiveSizeInBits (


<s> int check_use_sfunc_addr ( rtx insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == JUMP_INSN ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) !=


<s> if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) { CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } if ( ( TheTriple . getArch ( ) == Triple :: mipsel ) || ( TheTriple . getArch ( ) == Triple :: mips ) ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString =


<s> vpmaxq_u16 ( uint16x8_t a , uint16x8_t b ) { return ( uint16x8_t ) __builtin_aarch64_umaxpv8hi ( ( int16x8_t ) a ,


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterAsmParser < <ISA_LIT>_32ATTAsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterAsmParser < <ISA_LIT>_64ATTAsmParser > Y ( The<ISA_LIT>_64Target


<s> void <ISA_LIT>MCAsmStreamer :: EmitWeakReference ( MCSymbol * Alias , const MCSymbol * Symbol ) { llvm_unreachable (


<s> if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! MRI . isPhysRegUsed ( <STR_LIT> + NumSpills ) ) break ; if ( NumSpills < <NUM_LIT> ) return ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ->


<s> Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ; return Binary


<s> switch ( N -> getOpcode ( ) ) { default : assert ( false && <STR_LIT> ) ; return ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; std :: vector < EVT > NodeTys ; SDValue Ops [ <NUM_LIT> ] , Result , MFFSreg , InFlag , FPreg ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; MFFSreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT>


<s> bool isU8ImmX8 ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) && ( getImm ( ) & <NUM_LIT> )


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool isIXAddr = usesIXAddr ( MI ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) .


<s> static HOST_WIDE_INT ix86_static_rtx_alignment ( machine_mode mode ) { if ( mode == DFmode ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( mode ) ) return MAX ( <NUM_LIT> , GET_MODE_ALIGNMENT ( mode ) ) ; return GET_MODE_ALIGNMENT ( mode


<s> * __CF = ( unsigned char ) __builtin_ia32_kortestcqi ( __A , __B ) ; return ( unsigned char ) __builtin_ia32_kortestzqi ( __A ,


<s> return __builtin_mve_vldrhq_z_uv8hi ( ( __builtin_neon_hi * )


<s> PointerSize = <NUM_LIT> ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = true ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler = true


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( Subtarget -> isTargetELF ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTLSModel ( GV , getTargetMachine ( ) . getRelocationModel ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel


<s> } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( uint64_t ) MI . getOperand (


<s> return expandMOV32r1 ( MIB , * this , true ) ; case <STR_LIT> : case <STR_LIT> : return ExpandMOVImmSExti8 ( MIB ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case TargetOpcode :: LOAD_STACK_GUARD : expandLoadStackGuard ( MIB , * this ) ; return


<s> return __builtin_aarch64_floatv2siv2sf ( __a )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> static SDValue Concat256BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned NumElems , SelectionDAG & DAG , SDLoc dl ) { SDValue V = Insert256BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG ,


<s> } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = fastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , false , Addr . Offset , <STR_LIT> ) ; Addr . Offset = <NUM_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; break ; } case <STR_LIT> : emitPseudoInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitDataProcessingInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT>


<s> unsigned Alignment = <NUM_LIT> ; if ( LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( Parent ) ) { unsigned LSNAlign = LSN -> getAlignment ( ) ; unsigned MemSize = LSN -> getMemoryVT ( ) . getSizeInBits (


<s> ArrayRef < MCPhysReg > RegList = CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ; bool Is64bit = static_cast < const <ISA_LIT>Subtarget & > ( State . getMachineFunction ( ) . getSubtarget ( ) ) . is64Bit ( ) ; for ( auto Reg : RegList ) { if ( ! State . isAllocated (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRI12Only ( SDValue Op , SDValue & Addr , SDValue &


<s> MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand (


<s> MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = ABI . GetStackPtr ( ) ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , OffsetBitSize == <NUM_LIT> ? & NewImm : nullptr ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAdduOp ( ) ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; FrameReg = Reg


<s> const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT> ; int32_t tmp = ( int32_t ) MO2 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp


<s> MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) .


<s> mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , <NUM_LIT> , par_index ) = gen_rtx_SET


<s> SplatValueA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValueB ) ; } if ( BigEndian ) std :: swap ( SplatValueA , SplatValueB ) ; SDValue Ops [ <NUM_LIT> ] = { SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , ArrayRef < SDValue > ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ; if ( VecTy != ViaVecTy ) Result = DAG . getNode ( <STR_LIT> ,


<s> return __A ; } if ( __count == <NUM_LIT> ) return __B ; if ( __count >= <NUM_LIT> ) { if ( __count >= <NUM_LIT> ) { const __v16qu zero = { <NUM_LIT> } ; return ( __m128i ) zero ; } else { const __v16qu __shift = vec_splats ( ( unsigned char ) ( ( __count - <NUM_LIT> ) * <NUM_LIT> ) ) ; return ( __m128i ) vec_sro ( ( __v16qu ) __A , __shift ) ; return ( __m128i ) vec_slo ( ( __v16qu ) __A , __shift ) ; } } else { const __v16qu __shiftA = vec_splats ( ( unsigned char ) ( ( <NUM_LIT> - __count ) * <NUM_LIT> ) ) ; const __v16qu __shiftB = vec_splats ( ( unsigned char ) ( __count * <NUM_LIT> ) ) ; __A = ( __m128i ) vec_slo ( (


<s> OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; else OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT>


<s> static MachineInstr * MakeM0Inst ( const TargetInstrInfo & TII , unsigned Opcode , ArrayRef < MachineOperand > MOs , MachineBasicBlock :: iterator InsertPt , MachineInstr * MI ) { MachineInstrBuilder MIB = BuildMI ( * InsertPt -> getParent ( ) , InsertPt , MI -> getDebugLoc ( ) ,


<s> if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> )


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions


<s> if ( InfoAndKind . Is<ISA_LIT> ) { CCVal = DAG . getConstant ( <STR_LIT> ( InfoAndKind . Info . <ISA_LIT> . CC ) , dl , <STR_LIT> ) ; Cmp = * InfoAndKind . Info . <ISA_LIT> . Cmp ; } else Cmp = get<ISA_LIT>Cmp ( * InfoAndKind . Info . Generic . Opnd0 , * InfoAndKind . Info . Generic . Opnd1 , <STR_LIT> ( InfoAndKind . Info . Generic . CC , CmpVT ) , CCVal , DAG , dl ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; LHS = DAG . getNode ( <STR_LIT> , dl , VT , RHS , DAG . getConstant (


<s> break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportLinkage ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue


<s> int nunits = GET_MODE_NUNITS ( mode ) ; int nsets = nunits / <NUM_LIT> ; int set = <NUM_LIT> ; int i , j ; for ( j = <NUM_LIT> ; j < nsets ; j ++ , set = <NUM_LIT> * j ) for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( INTVAL ( XVECEXP ( op , <NUM_LIT> , i ) ) != ( INTVAL ( XVECEXP ( op , <NUM_LIT> , set + i ) ) -

set ) ) || ! IN_RANGE ( INTVAL ( XVECEXP ( op , <NUM_LIT> , set + i ) ) , <NUM_LIT> , set + <NUM_LIT> ) ) return false ;


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) for ( const auto & I : <ISA_LIT>FI -> StubsNeeded ) { const char * Symbol = I . first ; const <STR_LIT> * Signature = I .


<s> case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitCallAsanReport ( Ctx , Out , AccessSize , IsWrite ) ; EmitLabel ( Out , DoneSym ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg


<s> if ( V2 . isUndef ( ) ) { if ( <STR_LIT> ( SVOp , <NUM_LIT> ) || <STR_LIT> ( SVOp , <NUM_LIT> ) || <STR_LIT> ( SVOp , <NUM_LIT> ) || <STR_LIT> ( SVOp , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , DAG ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , <NUM_LIT> , DAG ) || ( Subtarget . hasP8Altivec ( ) && ( <STR_LIT> ( SVOp , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , true , <NUM_LIT> , DAG ) || <STR_LIT> ( SVOp , false , <NUM_LIT> , DAG ) ) ) ) { return Op ; } } unsigned int ShuffleKind = isLittleEndian ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( SVOp , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , ShuffleKind , DAG ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , <NUM_LIT> , ShuffleKind , DAG ) || ( Subtarget . hasP8Altivec ( ) && ( <STR_LIT> ( SVOp , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , true , ShuffleKind , DAG ) || <STR_LIT> ( SVOp , false , ShuffleKind , DAG ) ) ) ) return Op ; ArrayRef < int > PermMask = SVOp -> getMask ( ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle =


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { unsigned char OpFlags = Subtarget . ClassifyBlockAddressReference ( ) ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags


<s> void \ fini_section ( ) \ { \ if ( ( ! TARGET_ELF ) && in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP


<s> bool isMovImm32Shifter ( ) const { if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = getShiftExtendType ( ) ; if ( ST != <STR_LIT> ) return false ; uint64_t Val = getShiftExtendAmount ( ) ; return ( Val == <NUM_LIT> || Val == <NUM_LIT>


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF ,


<s> if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT ==

<STR_LIT> || VT == <STR_LIT> ) ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ;


<s> IncomingArgSize = Size ; HasByvalArg = HasByval


<s> cfun -> machine -> return_used_this_function = <NUM_LIT> ; } else { offsets = arm_get_frame_offsets ( ) ; gcc_assert ( ! use_return_insn ( FALSE , NULL ) || ( cfun -> machine -> return_used_this_function

!= <NUM_LIT> ) || offsets -> saved_regs == offsets -> outgoing_args || frame_pointer_needed ) ;


<s> fprintf ( f , <STR_LIT> ) ; } fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> InstructionCost MinMaxCost = <NUM_LIT> ; if ( LT . first != <NUM_LIT> && MTy . isVector ( ) && MTy . getVectorNumElements ( ) < ValVTy -> getNumElements ( ) ) { Ty = FixedVectorType :: get ( ValVTy -> getElementType ( ) , MTy . getVectorNumElements ( ) ) ; auto * SubCondTy = FixedVectorType :: get ( CondTy -> getElementType ( ) , MTy . getVectorNumElements ( ) ) ; MinMaxCost = getMinMaxCost ( Ty , SubCondTy , IsUnsigned ) ; MinMaxCost *= LT . first - <NUM_LIT> ; NumVecElts = MTy . getVectorNumElements ( ) ; } if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; if ( ST -> hasSSE41 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE41CostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; if ( ST -> hasSSE2 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE2CostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; unsigned ScalarSize = ValTy -> getScalarSizeInBits ( ) ; if ( ! isPowerOf2_32 ( ValVTy -> getNumElements ( ) ) || ScalarSize != MTy . getScalarSizeInBits ( ) ) return BaseT :: getMinMaxReductionCost ( ValTy , CondTy , IsUnsigned , CostKind ) ; while ( NumVecElts > <NUM_LIT> ) { unsigned Size = NumVecElts * ScalarSize ; NumVecElts /= <NUM_LIT> ; if ( Size > <NUM_LIT> ) { auto * SubTy = FixedVectorType :: get ( ValVTy -> getElementType ( ) , NumVecElts ) ; MinMaxCost += getShuffleCost ( TTI :: SK_ExtractSubvector , Ty , None , NumVecElts , SubTy ) ; Ty = SubTy ; } else if ( Size == <NUM_LIT> ) { VectorType * ShufTy ; if ( ValTy -> isFloatingPointTy ( ) ) ShufTy = FixedVectorType :: get ( Type :: getDoubleTy ( ValTy -> getContext ( ) ) , <NUM_LIT> ) ; else ShufTy = FixedVectorType :: get ( Type :: getInt64Ty ( ValTy -> getContext ( ) ) , <NUM_LIT> ) ; MinMaxCost += getShuffleCost ( TTI :: SK_PermuteSingleSrc , ShufTy , None , <NUM_LIT> , nullptr ) ; } else if ( Size == <NUM_LIT> ) { FixedVectorType * ShufTy ; if ( ValTy -> isFloatingPointTy ( ) ) ShufTy = FixedVectorType :: get ( Type :: getFloatTy ( ValTy -> getContext ( ) ) , <NUM_LIT> ) ; else ShufTy = FixedVectorType :: get ( Type :: getInt32Ty ( ValTy -> getContext ( ) ) , <NUM_LIT> ) ; MinMaxCost += getShuffleCost ( TTI :: SK_PermuteSingleSrc ,


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_type_node ) return <STR_LIT> ; if ( TARGET_FLOAT128 ) { if ( type == ieee128_float_type_node ) return <STR_LIT> ; if ( type == ibm128_float_type_node ) return <STR_LIT> ; if ( type == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return ( TARGET_IEEEQUAD ) ? <STR_LIT> : <STR_LIT> ; } if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 &&


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue


<s> SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; <STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ; assert ( Carry . getOpcode ( )


<s> EVT PtrVT = getPointerTy ( ) ; SDLoc DL ( Op ) ; ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , DL , PtrVT ,

DAG . getTargetGlobalAddress ( GV , DL , PtrVT ) ) ;


<s> bool is64BitUnsignedCompare = OpC == <STR_LIT> || OpC == <STR_LIT> ; MachineInstr * MI = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! MI ) return false ; int MIOpC = MI -> getOpcode ( ) ; bool equalityOnly = false ; bool noSub = false ; if ( is<ISA_LIT>64 ) { if ( is32BitSignedCompare ) { if ( MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> ) { noSub = true ; } else return false ; } else if ( is32BitUnsignedCompare ) { if ( MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> || MIOpC == <STR_LIT> ) { noSub = true ; equalityOnly = true ; } else return false ; } else equalityOnly = is64BitUnsignedCompare ; } else equalityOnly = is32BitUnsignedCompare ; if ( equalityOnly ) { for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( CRReg ) , IE = MRI -> use_end ( ) ; I != IE ; ++ I ) { MachineInstr * UseMI = & * I ; if ( UseMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Pred = UseMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) return false ; } else if ( UseMI -> getOpcode ( ) == <STR_LIT> || UseMI -> getOpcode ( ) == <STR_LIT> ) { unsigned SubIdx = UseMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( SubIdx != <STR_LIT> ) return false ; } else return false ; } } MachineBasicBlock :: iterator I = CmpInstr ; for ( MachineBasicBlock :: iterator EL = CmpInstr -> getParent ( ) -> end ( ) ; I != EL ; ++ I ) { bool FoundUse = false ; for ( MachineRegisterInfo :: use_iterator J = MRI -> use_begin ( CRReg ) , JE = MRI -> use_end ( ) ; J != JE ; ++ J ) if ( & * J == & * I ) { FoundUse = true ; break ; } if ( FoundUse ) break ; } MachineInstr * Sub = NULL ; if ( SrcReg2 != <NUM_LIT> ) MI = NULL ; else if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) || Value != <NUM_LIT> ) { return false ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; -- I ; MachineBasicBlock :: iterator E = MI , B = CmpInstr -> getParent ( ) -> begin ( ) ; for ( ; I != E && ! noSub ; -- I ) { const MachineInstr & Instr = *


<s> auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; return


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { MCInst TmpInst = MI ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode =


<s> if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> && F . getFnAttribute ( <STR_LIT> ) . getValueAsString

( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src1 ) && REG_P ( src2 ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si


<s> } if ( isSymbol ) { if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( StartInBrac , ErrMsg ) ; return nullptr ; } return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI ,

SmallVectorImpl < SDValue > & InVals ) const {


<s> if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( MF , PMBBI , NumBytes ) ) emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( MF , MBBI , NumBytes ) ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( ArgRegsSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) )

) . addReg ( <STR_LIT> , RegState :: Define ) ;


<s> if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg )

. addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ;


_mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


) _mm256_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return make_unique < <ISA_LIT>DCFunction > ( DCM


<s> Optional < ParamLoadedValue > <ISA_LIT>InstrInfo :: describeLoadedValue ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; int Immediate = MI . getOperand ( <NUM_LIT>


<s> static unsigned PrepareCall ( SelectionDAG & DAG , SDValue & Callee , SDValue & InFlag , SDValue & Chain , SDLoc dl , int SPDiff , bool isTailCall , SmallVectorImpl < std :: pair < unsigned , SDValue > > & RegsToPass , SmallVectorImpl < SDValue > & Ops , std :: vector < EVT > & NodeTys , const <ISA_LIT>Subtarget & Subtarget ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isSVR4ABI = Subtarget . isSVR4ABI ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; unsigned CallOpc = <STR_LIT> ; bool needIndirectCall = true ; if ( ! isSVR4ABI || ! is<ISA_LIT>64 ) if ( SDNode * Dest = isBLACompatibleAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; needIndirectCall = false ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( ! DAG . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isJITCodeModel ( ) ) { unsigned OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( Subtarget . getTargetTriple ( ) . isMacOSX ( ) && Subtarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) && ( G -> getGlobal ( ) -> isDeclaration ( ) || G -> getGlobal ( ) -> isWeakForLinker ( ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , Callee . getValueType ( ) , <NUM_LIT> , OpFlags ) ; needIndirectCall = false ; } } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( Subtarget . getTargetTriple ( ) . isMacOSX ( ) && Subtarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee ,


<s> OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Weak ) ; OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Hidden ) ; OutStreamer -> EmitLabel ( Sym ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; MCSymbol * HandleMismatchSym = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr

( MCSymbolRefExpr :: create ( HandleMismatchSym , OutContext ) ) , * STI ) ;


<s> static void printExpr ( const MCExpr * Expr , raw_ostream & O ) { const MCSymbolRefExpr * SRE ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; else SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; if ( Kind == MCSymbolRefExpr :: VK_None ) { O << *


<s> out |= ( Value & <NUM_LIT> ) ; uint64_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : { Value = Value - <NUM_LIT> ; Value >>= <NUM_LIT> ; uint64_t out = <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint32_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : { unsigned isNeg = ( int64_t ( Value ) < <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; uint32_t Binary = <NUM_LIT> ; Value = <NUM_LIT> & ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) ; Binary = ( Value & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; Binary |= isNeg << <NUM_LIT> ; return Binary ; } case <STR_LIT> : { unsigned isNeg = ( int64_t ( Value ) < <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; uint32_t Binary = <NUM_LIT> ; Value = <NUM_LIT> & ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) ; Binary = ( Value & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; Binary |= isNeg << <NUM_LIT> ; return Binary ; } case <STR_LIT> : return ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { uint32_t Binary = ( Value - <NUM_LIT> ) >> <NUM_LIT> ; return ( ( Binary & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Binary & <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : return ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: IsTailCallConvention ( CallingConv :: ID CallCC )


<s> if ( ! isa < Instruction > ( V ) ) return false ; unsigned Opc = cast < Instruction > ( V ) -> getOpcode


<s> if ( Subtarget . hasSSE41 ( ) || PackSVT == <STR_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( BitSize * <NUM_LIT> , BitSize ) ; if ( ( N1 . isUndef ( ) || DAG . MaskedValueIsZero ( VV1 , ZeroMask ) ) && ( N2 . isUndef ( ) || DAG . MaskedValueIsZero ( VV2 , ZeroMask ) ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } if ( ( N1 . isUndef ( ) || DAG . ComputeNumSignBits ( VV1 ) > BitSize ) && ( N2 . isUndef ( ) || DAG . ComputeNumSignBits ( VV2 ) > BitSize ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode =


<s> TargetRegistry :: RegisterMCDisassembler (


<s> type_suffix_index function_resolver :: infer_integer_scalar_type ( unsigned int argno ) { tree actual = get_argument_type ( argno ) ; if ( actual == error_mark_node ) return NUM_TYPE_SUFFIXES ; if ( INTEGRAL_TYPE_P ( actual ) ) { bool uns_p = TYPE_UNSIGNED ( actual ) ; if ( TYPE_PRECISION ( actual ) < <NUM_LIT> ) return TYPE_SUFFIX_s32 ; if ( TYPE_PRECISION ( actual ) == <NUM_LIT> ) return


<s> int <ISA_LIT>TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty ) const { if ( isLegalAddressingMode ( AM , Ty ) ) return AM . Scale != <NUM_LIT> && AM . Scale != <NUM_LIT> ; return -


<s> bool is<ISA_LIT>SOImmNeg ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value ) == - <NUM_LIT> && <STR_LIT> ( - Value


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , CmpOp , IfTrue , IfFalse , A64cc ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; SDValue A64SELECT_CC = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , SetCC , IfTrue , IfFalse , A64cc ) ; if ( Alternative != <STR_LIT> ) { A64cc = DAG . getConstant ( Alternative , <STR_LIT> ) ; A64SELECT_CC = DAG . getNode ( <STR_LIT> , dl , Op . getValueType (

) , SetCC , IfTrue , A64SELECT_CC , A64cc ) ;


<s> sh_emit_storesi ( addr , offset , gen_int_mode ( TARGET_LITTLE_ENDIAN ? ( w0 | ( w1 << <NUM_LIT> ) )


<s> bool <ISA_LIT>TargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = reinterpret_cast < const yaml :: <ISA_LIT>FunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < <ISA_LIT>FunctionInfo > ( )

-> initializeBaseYamlFields ( YamlMFI ) ;


<s> static <STR_LIT> isUseDefConvertible ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __bextr_u32 ( unsigned int __X , unsigned int __Y ) { return __builtin_ia32_bextr_u32 ( __X ,


<s> unsigned getFramePtr ( ) const { return


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return split256IntArith ( Op ,


<s> return __builtin_aarch64_fmaxv2df ( __a ,


<s> formatted_raw_ostream & HackStreamer (


<s> StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( STI . isGP32bit ( ) ) OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; } getTargetStreamer ( ) . updateABIInfo ( STI ) ; if ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) getTargetStreamer ( ) . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) getTargetStreamer


<s> } } for ( MachineBasicBlock & MBB : MF ) { for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MBB . isLiveIn ( reg ) ) continue ; MBB . removeLiveIn ( reg ) ; MBB . addLiveIn ( reg - <STR_LIT> + <STR_LIT> ) ; } for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MBB . isLiveIn ( reg ) ) continue ; MBB . removeLiveIn ( reg ) ; MBB . addLiveIn ( reg - <STR_LIT> +


<s> Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; return


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; const IndirectBrInst * IB = cast <


<s> bool <ISA_LIT>AsmParser :: IsSIReg ( unsigned Reg ) { switch ( Reg ) { default : llvm_unreachable ( <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static SDValue combineFaddFsub ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( SDValue HOp = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return HOp ; if ( SDValue COp = combineFaddCFmul ( N , DAG , Subtarget ) ) return COp ; if ( SDValue Sel = combineBinopWithSelect ( N , DAG ,


<s> rtx worker = mova ; rtx lab = gen_label_rtx ( ) ; rtx wpat , wpat0 , wpat1 , wsrc , diff ; do { worker = NEXT_INSN ( worker ) ; gcc_assert ( worker && GET_CODE ( worker ) != CODE_LABEL && GET_CODE ( worker ) != JUMP_INSN ) ; } while ( GET_CODE ( worker ) == NOTE || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , <NUM_LIT> , <NUM_LIT> ) ; wpat1 = XVECEXP ( wpat , <NUM_LIT> , <NUM_LIT> ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , <NUM_LIT> , <NUM_LIT> ) , XEXP ( XVECEXP ( wsrc , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , lab , XEXP ( wpat1 , <NUM_LIT> ) ) ) ; INSN_CODE ( worker ) = - <NUM_LIT> ; diff = gen_rtx_MINUS ( Pmode , XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , <NUM_LIT> , <NUM_LIT> ) , gen_rtx_LABEL_REF ( Pmode ,


<s> return __builtin_loongson_punpcklhw_s ( s ,


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter >


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) == Type :: DoubleTy ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } } } return false


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _mm_monitor ( void const * __P ,


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; if ( Opcode == <STR_LIT> ) return true ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned RegEnum = <NUM_LIT> ; switch ( OpInfo [ <NUM_LIT> ] . RegClass ) { case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , false ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , true ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; } MI . addOperand ( MCOperand :: CreateReg ( RegEnum


<s> return ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( )


<s> ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Tok = Parser . getTok ( ) . getIdentifier ( ) ; if ( Tok [ <NUM_LIT> ] != 'c' && Tok [ <NUM_LIT> ] != 'C' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex


<s> MCAsmParser & getParser ( ) const { return


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned int __Y ) { return ( ~ __X &


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer .


<s> assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmOp64 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ImmOp64 = convertIntToDoubleImm ( ImmOp64 ) ; uint32_t ImmOp32 = covertDoubleImmToSingleImm ( ImmOp64 ) ; unsigned TmpReg = <STR_LIT> ; if ( ImmOp32 != <NUM_LIT> ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; } if ( Lo_32 ( ImmOp64 ) == <NUM_LIT> ) { if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp32 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym

, MCSymbolRefExpr :: VK_None , getContext ( ) ) ;


<s> void <ISA_LIT>FrameLowering :: createTailCallBranchInstr ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( JumpTarget . getImm ( ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand (


<s> static rtx gen_frame_set ( rtx reg , rtx frame_reg , int offset , bool store ) { rtx addr , mem ; addr = gen_rtx_PLUS ( Pmode , frame_reg , GEN_INT ( offset ) ) ; mem = gen_frame_mem ( GET_MODE (


<s> static inline const MachineInstrBuilder & addDirectMem ( const MachineInstrBuilder & MIB , unsigned


<s> Value * <ISA_LIT>IREmitter :: visitVTBL1 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> report_fatal_error ( <STR_LIT> ) ; return ; } if ( Target . getSymB ( ) ) { if ( RelocType == macho :: RIT_<ISA_LIT>_Half || RelocType == macho :: RIT_<ISA_LIT>_HalfDifference ) return Record<ISA_LIT>MovwMovtRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; } MCSymbolData * SD = <NUM_LIT> ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel && RelocType == macho :: RIT_Vanilla ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && SD && ! Writer -> doesSymbolRequireExternRelocation ( SD ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout ,

Writer -> getSectionAddressMap ( ) ) ) {


<s> printThumbAddrModeRI5Operand ( MI , Op ,


<s> void FixupLEAPass :: processInstructionForSLM ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr & MI = * I ; const int Opcode = MI . getOpcode ( ) ; if ( ! isLEA ( Opcode ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) return ; const unsigned DstR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI


<s> return __builtin_mve_vmullbq_int_m_uv16qi ( __arm_vuninitializedq_u16 ( ) , __a


<s> JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( )


<s> void EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Bits = getBinaryCodeForInstr ( MI , Fixups ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { OS << ( char ) ( Bits >> <NUM_LIT> ) ; Bits <<= <NUM_LIT> ; } ++ MCNumEmitted


<s> TRI = TM -> getRegisterInfo ( ) ; Subtarget = & TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; Is64Bit = Subtarget -> is64Bit ( ) ; assert ( Subtarget -> isTargetNaCl ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { Modified |= runOnMachineBasicBlock ( * MFI ) ; } Modified |= AlignJumpTableTargets ( MF ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> static DecodeStatus DecodeDDDDRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr ,


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo (


<s> } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT


<s> static DecodeStatus decodeBDLAddr64Disp12Len4Operand ( MCInst & Inst , uint64_t Field , uint64_t


<s> unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( )

, ACPV -> getLabelId ( ) , OutContext ) ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> CallingConv :: ID CalleeCC = Info . CallConv ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; MachineInstrBuilder CallSeqStart ; if ( ! IsSibCall ) CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , true ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; MIB . addImm ( <NUM_LIT> ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; int FPDiff = <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; if ( ! IsSibCall ) { unsigned NumReusableBytes = FuncInfo -> getBytesInStackArgArea ( ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , F . getContext ( ) ) ; <ISA_LIT>OutgoingValueAssigner CalleeAssigner ( AssignFnFixed , AssignFnVarArg , Subtarget , false ) ; if ( ! determineAssignments ( CalleeAssigner , OutArgs , OutInfo ) ) return false ; NumBytes = alignTo ( OutInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; FPDiff = NumReusableBytes - NumBytes ; if ( FPDiff < <NUM_LIT> && FuncInfo -> getTailCallReservedStack ( ) < ( unsigned ) - FPDiff ) FuncInfo -> setTailCallReservedStack ( - FPDiff ) ; assert ( FPDiff % <NUM_LIT> ==


<s> It . convertToMem ( State . AllocateStack ( Size , std :: max ( ( unsigned ) Align . value ( ) , SlotAlign ) ) ) ; State . addLoc ( It ) ; SlotAlign = <NUM_LIT> ; } PendingMembers . clear ( )


<s> NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Op = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Op ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; SpillsVRS = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> .


<s> } } MachineBasicBlock :: iterator I = CmpInstr , E = MI , B = CmpInstr . getParent ( ) -> begin ( ) ; if ( I == B ) return false ; MachineInstr * SubAdd = nullptr ; if ( SrcReg2 != <NUM_LIT> ) MI = nullptr ; else if ( MI -> getParent ( ) != CmpInstr . getParent ( ) || CmpValue != <NUM_LIT> ) { if ( CmpInstr . getOpcode ( ) == <STR_LIT> || CmpInstr . getOpcode ( ) == <STR_LIT> || CmpInstr . getOpcode ( ) == <STR_LIT> ) MI = nullptr ; else return false ; } bool IsThumb1 = false ; if ( MI && ! isOptimizeCompareCandidate ( MI , IsThumb1 ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MI && IsThumb1 ) { -- I ; if ( I != E && ! MI -> readsRegister ( <STR_LIT> , TRI ) ) { bool CanReorder = true ; for ( ; I != E ; -- I ) { if ( I -> getOpcode ( ) != <STR_LIT> ) { CanReorder = false ; break ; } } if ( CanReorder ) { MI = MI -> removeFromParent ( ) ; E = CmpInstr ; CmpInstr . getParent ( ) -> insert ( E , MI ) ; } } I = CmpInstr ; E = MI ; } bool SubAddIsThumb1 = false ; do { const MachineInstr & Instr = * -- I ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & Instr , SubAddIsThumb1 ) ) { SubAdd = & * I ; break ; } if ( I == E ) break ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( I == B ) { return false ; } } while ( true ) ; if ( ! MI && ! SubAdd ) return false ; if ( SubAdd ) { MI = SubAdd ; IsThumb1 = SubAddIsThumb1 ; } if ( isPredicated ( * MI ) ) return false ; SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++


<s> raw_svector_ostream ( NameSV ) << Context . getAsmInfo ( ) -> getPrivateGlobalPrefix ( ) << Prefix << Context . getUniqueSymbolID ( ) ; return Context . GetOrCreateSymbol ( NameSV


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; std :: pair < SDNode * , SDNode * > LoHi = selectMULT ( Node , MultOpc , DL , NodeTy , true , true ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . first , <NUM_LIT> ) ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . second , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; auto LoHi = selectMULT ( Node , MultOpc , DL , NodeTy , false , true ) ; ReplaceNode ( Node , LoHi . second ) ; return


<s> case <STR_LIT> : case <STR_LIT> : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ST -> hasMVEFloatOps ( ) ) continue ; LLVM_FALLTHROUGH ; default : break ; } if ( IsMasked ( & I ) ) { auto * VecTy = getVectorType ( Int ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; continue ; } for ( const Use & U : Int -> args ( ) ) { if ( isa < VectorType > ( U -> getType ( ) ) ) return false ; } } } if ( ! ActiveLaneMask ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( TargetMachine & TM ) : TargetLowering ( TM , new TargetLoweringObjectFileELF ( ) ) { addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> if ( rx_gp_base_regnum_val == INVALID_REGNUM


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO .

getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> static bool pru_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { if ( to == STACK_POINTER_REGNUM ) return !


<s> Align Alignment = std :: min ( Flags . getNonZeroByValAlign ( ) , Align ( RegSizeInBytes ) ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; unsigned NumRegs = LastReg - FirstReg ; if ( NumRegs ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetByValArgRegs ( ) ; bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT>


<s> const EVT VT = TLI . getMemValueType ( DL , CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; ElementCount EC = VT . getVectorElementCount ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumVecs ; ++ I ) assert ( VT == TLI . getMemValueType ( DL , CI . getArgOperand ( I ) -> getType ( ) ) && <STR_LIT> ) ; Info . memVT = EVT :: getVectorVT ( CI . getType ( ) -> getContext ( ) , VT . getScalarType ( ) , EC * NumVecs ) ; Info . ptrVal = CI . getArgOperand ( CI . getNumArgOperands ( )


<s> if ( INTVAL ( x ) & <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; prefix = <STR_LIT> ; } fprintf ( file , <STR_LIT> , prefix , ( int ) INTVAL ( x ) & <NUM_LIT> ) ; return ; } break ; case 'X' : { unsigned int regno = REGNO ( x ) ; fprintf ( file , <STR_LIT> , reg_names [ regno ] , reg_names [ regno + <NUM_LIT> ] ) ; } return ; case 'r' : if ( GET_CODE ( x ) == REG ) fputs ( reg_names [ REGNO ( x ) ] , file ) ; else if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) fputs ( <STR_LIT> , file ) ; else if ( GET_CODE ( x ) == CONST_INT ) output_addr_const ( file , x ) ; else output_operand_lossage ( <STR_LIT> ) ; return ; case 'v' : gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; x = simplify_subreg ( DImode , x , GET_MODE ( x ) , <NUM_LIT> ) ; break ; case '+' : { const char * which ; x = find_reg_note ( current_output_insn , REG_BR_PROB , <NUM_LIT> ) ; if ( x ) { int pred_val = profile_probability :: from_reg_br_prob_note ( XINT ( x , <NUM_LIT> ) ) . to_reg_br_prob_base ( ) ; if ( pred_val < REG_BR_PROB_BASE / <NUM_LIT> && br_prob_note_reliable_p ( x ) ) which = <STR_LIT> ; else if ( pred_val < REG_BR_PROB_BASE / <NUM_LIT> ) which = <STR_LIT> ; else if ( pred_val < REG_BR_PROB_BASE / <NUM_LIT> * <NUM_LIT> || ! br_prob_note_reliable_p ( x ) ) which = <STR_LIT> ; else which = <STR_LIT> ; } else if ( CALL_P ( current_output_insn ) ) which = <STR_LIT> ; else which = <STR_LIT> ; fputs ( which , file ) ; return ; } case ',' : x = current_insn_predicate ; if ( x ) { unsigned int regno = REGNO ( XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == EQ ) regno += <NUM_LIT> ; fprintf ( file , <STR_LIT> , reg_names [ regno ] ) ; } return ; default : output_operand_lossage ( <STR_LIT> ) ; return ; } switch ( GET_CODE ( x ) ) { case POST_INC : case POST_DEC : case POST_MODIFY : x = XEXP ( x , <NUM_LIT> ) ; case REG : fputs ( reg_names [ REGNO ( x ) ] , file ) ; break ; case MEM


<s> bool IsInt8 = Offset . isImm ( ) && isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ; switch ( LEAOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return IsInt8 ?


<s> for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , <NUM_LIT> ) ) return false ; return true


<s> bool <ISA_LIT>FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize


<s> unsigned Offset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( isThumb && MI -> getOpcode ( ) == <STR_LIT> && Offset % <NUM_LIT> != <NUM_LIT> ) Offset += <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; ; ++ I ) { assert ( I != MBB -> end (


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Src -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { SDValue UnpkOp = Src -> getOperand ( <NUM_LIT> ) ; SDValue Dup = N -> getOperand ( <NUM_LIT> ) ; if ( Dup . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Dup -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t ExtVal = C -> getZExtValue ( ) ; EVT EltTy = UnpkOp -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) .


<s> SDValue <ISA_LIT>TargetLowering :: LowerSINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { bool IsStrict = Op -> isStrictFPOpcode ( ) ; unsigned OpNo = IsStrict ? <NUM_LIT> : <NUM_LIT> ; SDValue Src = Op . getOperand ( OpNo ) ; SDValue Chain = IsStrict ? Op -> getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( Subtarget . isTargetWin64 ( ) && SrcVT == <STR_LIT> ) return LowerWin64_INT128_TO_FP ( Op , DAG ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( SDValue R = lowerFPToIntToFP ( Op , DAG , Subtarget ) ) return R ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) return lowerINT_TO_FP_vXi64 ( Op , DAG , Subtarget ) ; return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; uint32_t Binary = getAddrMode2OffsetOpValue ( MI , OpIdx +


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isImm ( ) ) { Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return ; } Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . OffsetRegNum ) ) ; if ( ! Memory . OffsetRegNum ) { if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; } else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm ) ) ; } else


<s> bool shouldInsertFencesForAtomic ( const Instruction *


<s> return ( __mmask8 ) __builtin_ia32_ptestnmq512 ( ( __v8di ) __A ,


<s> if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NegShift = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue NegShiftLeft = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Opc , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , NegShift ) ; return NegShiftLeft


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT>


<s> SmallVector < SDValue , <NUM_LIT> > Opnds ; DenseMap < SDValue , unsigned > VecInMap ; EVT VT = <STR_LIT> ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVector < SDValue , <NUM_LIT> > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) &&


<s> static inline __ev64_opaque__ __internal_ev_mwhsmfanw ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhsmf ( a


<s> O << <ISA_LIT>RegisterInfo :: stripRegisterPrefix ( RegName ) ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { PrintSymbolOperand ( MO , O ) ; return ; } default : O << <STR_LIT> << ( unsigned ) MO . getType (


<s> while ( ! MI -> getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI -> getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo ) . getImm ( ) ; return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == TargetOpcode :: STACKMAP || MI -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || ( isInt < <NUM_LIT> > (

Offset ) && ( Offset % offsetMinAlign ( * MI ) ) == <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot ,

const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( isFP64bit ( ) && ! has<ISA_LIT>64 ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( inAbs2008Mode ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; assert ( inAbs2008Mode ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2


<s> if ( HasChainIn ) Ops . push_back ( Op -> getOperand ( OpNo ++ ) ) ; assert ( Op -> getOperand ( OpNo ) . getOpcode ( ) == <STR_LIT> ) ; SDValue Opnd = Op -> getOperand ( ++ OpNo ) , In64 ; if ( Opnd . getValueType ( ) == <STR_LIT> ) In64 = initAccumulator ( Opnd , DL , DAG ) ; else Ops . push_back ( Opnd ) ; for ( ++ OpNo ; OpNo < Op -> getNumOperands ( ) ; ++ OpNo ) Ops . push_back ( Op -> getOperand ( OpNo ) ) ; if ( In64 . getNode ( ) ) Ops . push_back ( In64 ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; for ( SDNode :: value_iterator I = Op -> value_begin ( ) , E = Op -> value_end ( ) ; I != E ; ++ I ) ResTys . push_back ( ( * I == <STR_LIT> ) ? <STR_LIT> : * I ) ; SDValue Val = DAG . getNode ( Opc , DL , ResTys ,


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; return


<s> imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeFPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeFPR128RegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned isLS = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool isOnlyStoreBarrier = ( isLL == <NUM_LIT> && isLS == <NUM_LIT> ) ; <STR_LIT> DMBOpt ; if ( isDeviceBarrier ) DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ; else DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant


<s> static SDValue buildScalarToVector ( SelectionDAG & DAG , SDLoc DL , EVT VT , SDValue Value ) { if ( Value . getOpcode ( ) == <STR_LIT> || Value . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Value ) ; return DAG . getBuildVector ( VT


<s> unsigned getReturnRegsCount ( ) const { return ReturnRegsCount


<s> Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelDyn ( ) const { assert ( m_pRelDyn != NULL


<s> if ( attr_length_indirect_call ( insn ) == <NUM_LIT> ) return <STR_LIT> ; xoperands [ <NUM_LIT> ] = NULL_RTX ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_SOM || ! TARGET_GAS ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( xoperands [ <NUM_LIT> ] ) ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands


<s> if ( hasShortDelaySlot ) emitRR ( <STR_LIT> , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; else emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , IDLoc


_mm_setzero_hi ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( int16x4_t ) __builtin_aarch64_shaddv4hi


<s> static __inline__ long long __fctidz ( double a


<s> case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: createSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( OpSym , OutContext ) , DotExpr , OutContext ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( DotExpr ) ) ; return ; } case TargetOpcode :: STATEPOINT : return LowerSTATEPOINT ( * MI , MCInstLowering ) ; case TargetOpcode :: FAULTING_OP : return LowerFAULTING_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: FENTRY_CALL : return LowerFENTRY_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_OP : return LowerPATCHABLE_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : return LowerPATCHABLE_FUNCTION_ENTER ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_RET : return LowerPATCHABLE_RET ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TAIL_CALL : return LowerPATCHABLE_TAIL_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_EVENT_CALL : return LowerPATCHABLE_EVENT_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TYPED_EVENT_CALL : return LowerPATCHABLE_TYPED_EVENT_CALL ( * MI , MCInstLowering ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitSEHInstruction ( MI ) ; return ; case <STR_LIT> : { assert ( MF -> hasWinCFI ( ) && <STR_LIT> ) ; MachineBasicBlock :: const_iterator MBBI ( MI ) ; for ( MBBI = PrevCrossBBInst ( MBBI ) ; MBBI != MachineBasicBlock :: const_iterator ( ) ; MBBI = PrevCrossBBInst ( MBBI ) ) { if ( ! MBBI -> isPseudo ( ) ) { if ( MBBI -> isCall ( ) ) EmitAndCountInstruction


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP_i32 ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , dl , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> rtx gen_compare_reg ( rtx cmp ) { return gen_compare_reg_1 ( GET_CODE ( cmp ) , XEXP ( cmp , <NUM_LIT> ) , XEXP


<s> bool <ISA_LIT>IntelAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; printMemReference ( MI ,


<s> return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: ExtractValue : return <ISA_LIT>SelectExtractValue ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return


<s> unsigned <ISA_LIT>CodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( ( ! Subtarget . hasDQI ( ) && ( VecVT . getVectorNumElements ( ) == <NUM_LIT> ) ) || ( VecVT . getVectorNumElements ( ) < <NUM_LIT> ) ) { VecVT = <STR_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , DAG . getUNDEF ( VecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } unsigned MaxSift = VecVT . getVectorNumElements ( ) - <NUM_LIT> ; if ( MaxSift - IdxVal ) Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG

. getConstant ( MaxSift - IdxVal , dl , <STR_LIT> ) ) ;


<s> union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; vec_uchar16 mask ; count = <NUM_LIT> - count ; x . i [ <NUM_LIT> ] = count << <NUM_LIT> ; mask = ( count & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ; return ( ( qword ) ( vec_and ( vec_sro ( ( vec_uchar16 ) ( a ) , x .


<s> if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( )


<s> static SDValue lowerShuffleAsRotate ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) )


<s> case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : return combineFP_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : return combineBR_CCMASK ( N , DCI ) ; case <STR_LIT> : return combineSELECT_CCMASK ( N , DCI ) ; case <STR_LIT> : return combineGET_CCMASK ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label


<s> bool isStub = ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] == <NUM_LIT> ; RetAddr -- ; RetAddr -= <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << ( void * ) RetAddr << <STR_LIT> << ( void * ) StackPtr << <STR_LIT> << TheVM -> getFunctionReferencedName ( ( void * ) RetAddr ) << <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) { * ( unsigned char * ) ( RetAddr - <NUM_LIT> ) = <NUM_LIT> ; * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = diff & <NUM_LIT> ; } else { * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = NewVal ; ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] = ( <NUM_LIT> | ( <NUM_LIT> <<

<NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return &


<s> if ( LHSDef && RHSDef ) { int64_t RHSC = ( int64_t ) RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { if ( LHSDef -> getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHSDef -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder &


<s> if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2