<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; for ( MCRegAliasIterator AI ( CurReg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) { MapRegToId :: const_iterator ItRegId = RegToId . find ( * AI ) ; if ( ItRegId == RegToId . end ( ) ) continue ; BBKillSet . set ( ItRegId -> second ) ; BBGen [ ItRegId -> second ] = & MI ; } BBGen [ ItCurRegId -> second ] = & MI ; } } if ( ! ADRPMode && DummyOp && ! MBB . succ_empty ( ) ) for ( unsigned CurReg = <NUM_LIT> ; CurReg < NbReg ; ++ CurReg

) if ( BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( DummyOp ) ;


<s> SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForNode ( CallingConv :: ID CC ) const { if ( Subtarget -> is64Bit ( ) ) { if ( CC == CallingConv ::


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_ANY_SVE ) return false ; if ( known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return true ; if ( known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return ( regno & <NUM_LIT>


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2


<s> bool hasFP ( const MachineFunction & ) const override { return true


<s> if ( WriteMaskOp . isReg ( ) ) { CS << <STR_LIT> << GetRegisterName ( WriteMaskOp . getReg ( ) ) << <STR_LIT> ; if ( SrcOp1Idx == <NUM_LIT> ) { CS << <STR_LIT> ; } } } CS << <STR_LIT> ; for ( int i = <NUM_LIT> , e = ShuffleMask . size ( ) ; i != e ; ++ i ) { if ( i != <NUM_LIT> ) CS << <STR_LIT> ; if ( ShuffleMask [ i ] == SM_SentinelZero ) { CS << <STR_LIT> ; continue ; } bool isSrc1 = ShuffleMask [ i ] < ( int ) e ; CS << ( isSrc1 ? Src1Name : Src2Name ) << '[' ; bool IsFirst = true ; while ( i != e && ShuffleMask [ i ] != SM_SentinelZero && ( ShuffleMask [ i ] < ( int ) e ) == isSrc1 ) { if ( ! IsFirst ) CS << ',' ; else IsFirst = false ; if ( ShuffleMask [ i ] == SM_SentinelUndef ) CS << <STR_LIT> ; else CS << ShuffleMask [ i ] % ( int ) e ; ++ i ; } CS <<


<s> output_asm_insn ( s , operands ) ; s = <STR_LIT> ; } return


<s> BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> , RegState :: Undef ) . addUse ( <STR_LIT> ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } else { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) )


<s> return TargetTriple . getOS ( ) == Triple ::


<s> if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; } if ( Subtarget -> hasAVX ( ) ) { if ( ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) || ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) ) { SDValue ZeroVec = getZeroVector ( OpVT , Subtarget , DAG , dl ) ; SDValue OpLo = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; SDValue OpHi = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; EVT HVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT

. getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ;


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; return true ; } const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; ( void ) DstSize ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; ( void ) SrcSize


<s> unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; if ( ! UseImm ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op2Reg ) . addReg ( Op1Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op1Reg ) . addImm ( Imm ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; UpdateValueMap ( I , ResultReg


<s> if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( <STR_LIT> ) ; CSI . back ( ) . setRestored ( false ) ; } const auto & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo >


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForNode ( unsigned CC ) const { if ( Subtarget -> is64Bit ( )


<s> if ( ! UC . hasFnStart ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc


<s> int arm_eliminable_register ( rtx x ) { return REG_P ( x ) && ( REGNO ( x ) == FRAME_POINTER_REGNUM || REGNO ( x ) == ARG_POINTER_REGNUM || ( REGNO (

x ) >= FIRST_VIRTUAL_REGISTER && REGNO ( x ) <= LAST_VIRTUAL_REGISTER ) ) ;


<s> if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } Register FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill


<s> assert ( ! Val == ! VReg && <STR_LIT> ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VReg , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return


<s> } else if ( STI . isTargetDarwin ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; } else if ( STI . isTargetWin32 ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetDragonFly ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetFreeBSD ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; if ( STI . isTargetLinux ( ) || STI . isTargetWin32 ( ) || STI . isTargetWin64 ( ) || STI . isTargetDragonFly ( ) ) { BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ; } else if ( STI . isTargetDarwin ( ) ) { unsigned ScratchReg2 ; bool SaveScratch2 ; if ( CompareStackPointer ) { ScratchReg2 = GetScratchRegister ( Is64Bit , IsLP64 , MF , true ) ; SaveScratch2 = false ; } else { ScratchReg2 = GetScratchRegister ( Is64Bit , IsLP64 , MF , false ) ; SaveScratch2 = MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) ; } assert ( ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) || SaveScratch2 ) && <STR_LIT> ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg2 , RegState :: Kill ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & PrologueMBB ) ; if ( Is64Bit ) { const unsigned RegAX = IsLP64 ? <STR_LIT> :


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) return false ; bool CanChangeType = isLE && ! IsMasked ; ConstantSDNode * RHS = cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; auto IsInRange = [ & ] ( int RHSC , int Limit , int Scale ) { if ( RHSC < <NUM_LIT> && RHSC > - Limit * Scale && RHSC % Scale == <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < Limit * Scale && RHSC % Scale == <NUM_LIT> ) { isInc = Ptr -> getOpcode ( ) ==


<s> if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , NewEFLAGS ) ; } } } if ( CC == <STR_LIT> ) { return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Y . getOperand ( <NUM_LIT> ) ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y -> getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewEFLAGS ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( CouldJump ? <STR_LIT> : <STR_LIT> ) << ( CouldCall ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned HintNum = <NUM_LIT> ; if ( CouldCall ) HintNum |= <NUM_LIT> ; if ( CouldJump ) HintNum |= <NUM_LIT> ; assert ( HintNum != <NUM_LIT> && <STR_LIT> ) ; auto MBBI = MBB . begin ( ) ; for ( ; MBBI != MBB . end ( ) && MBBI -> isMetaInstruction ( )


<s> const char * xasm ; if ( SIBLING_CALL_P ( insn ) ) { if ( direct_p ) xasm = <STR_LIT> ; else if ( TARGET_SEH ) xasm = <STR_LIT> ; else xasm = <STR_LIT> ; output_asm_insn ( xasm , & call_op ) ; return <STR_LIT> ; } if ( TARGET_SEH ) { rtx_insn * i ; for ( i = NEXT_INSN ( insn ) ; i ; i = NEXT_INSN ( i ) ) { if ( INSN_P ( i ) ) break ; if ( NOTE_P ( i ) && NOTE_KIND ( i ) == NOTE_INSN_EPILOGUE_BEG && ! flag_non_call_exceptions && ! can_throw_internal ( insn ) ) { seh_nop_p = true ; break ; } } if ( i == NULL


<s> Op -> Kind = MEMORY_REG_IMM ; Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ; Op -> Mem . OffsetReg = <NUM_LIT> ; Op -> Mem . Offset = Imm ; return


<s> if ( verbose ) fprintf ( stream , <STR_LIT> , more , r ) ; return


<s> } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; O << * DispSpec . getExpr ( ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg .


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFRegPX ( SMLoc L ) { unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveFRegPX (


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; return


<s> if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false


<s> static const char * checkPCRelOffset ( uint64_t Value , int64_t Min , int64_t Max ) { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset < Min || Offset > Max ) return <STR_LIT> ; return nullptr


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef ShiftName = Tok . getString ( ) ; bool isASR ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) isASR = false ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) isASR = true ; else { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( isASR ) { if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( isThumb ( ) && Val == <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Val == <NUM_LIT> ) Val = <NUM_LIT> ; } else { if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } Operands . push_back ( <ISA_LIT>Operand :: CreateShifterImm ( isASR , Val , S , EndLoc ) ) ; return


<s> static inline unsigned getT2SOImmTwoPartSecond ( unsigned Imm ) { Imm ^= getT2SOImmTwoPartFirst ( Imm


<s> for ( unsigned int i = <NUM_LIT> ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( fpubits , all_fpus [ i ] . isa_bits ) ; bitmap_and_compl ( tmpset , isa_all_fpubits_internal , fpubits ) ; bitmap_clear ( isa_all_fpubits_internal ) ; bitmap_copy ( isa_all_fpubits_internal , tmpset ) ; } if ( ! bitmap_empty_p ( isa_all_fpubits_internal ) ) { fprintf ( stderr , <STR_LIT> <STR_LIT> <STR_LIT> ) ; ASSERT_TRUE ( bitmap_empty_p ( isa_all_fpubits_internal


<s> if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue CMovOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue CMovOp1 = N0 . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( CMovOp0 . getNode ( ) ) || ! isa < ConstantSDNode > ( CMovOp1 . getNode ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( IntermediateBitwidthOp ) { unsigned IntermediateOpc = IntermediateBitwidthOp . getOpcode ( ) ; CMovOp0 = DAG . getNode ( IntermediateOpc , DL , DstVT , CMovOp0 ) ; CMovOp1 = DAG . getNode ( IntermediateOpc , DL , DstVT , CMovOp1 ) ; } CMovOp0 = DAG . getNode ( <STR_LIT> , DL , DstVT , CMovOp0 , N1 ) ; CMovOp1 = DAG . getNode ( <STR_LIT> , DL , DstVT , CMovOp1 , N1 ) ; EVT CMovVT = DstVT ; if ( DstVT == <STR_LIT> ) { CMovVT = <STR_LIT> ; CMovOp0 = DAG . getNode ( <STR_LIT> , DL , CMovVT , CMovOp0


<s> const struct machine_frame_state & fs = cfun -> machine -> fs ; if ( fs . sp_realigned && cfa_offset <= fs .


<s> if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ; if ( REGNO ( reg1 ) % <NUM_LIT> != <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_V9 && SPARC_INT_REG_P ( REGNO ( reg1 ) ) )


<s> return parseRegister ( Operands , RegAR , <STR_LIT> ,


<s> const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( Paired ) : getLdStBaseOp ( I ) ; MachineInstr * RtMI , * Rt2MI ; if ( getLdStOffsetOp ( I ) . getImm ( ) == getLdStOffsetOp ( Paired ) . getImm ( ) + OffsetStride ) { RtMI = Paired ; Rt2MI = I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = I ; Rt2MI = Paired ; } int OffsetImm = getLdStOffsetOp ( RtMI ) . getImm ( ) ; if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ) OffsetImm /= OffsetStride ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( )


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned i = <NUM_LIT> ; for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + <NUM_LIT> , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( *


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > (


<s> return ( uint32x2_t ) __builtin_aarch64_sqmovunv2di


<s> static void adjustICmpTruncate ( SelectionDAG & DAG , const SDLoc & DL , Comparison & C ) { if ( C . Op0 . getOpcode ( ) == <STR_LIT> && C . Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { auto * L = cast < LoadSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( L -> getMemoryVT ( ) . getStoreSizeInBits ( ) <= C . Op0 . getValueType ( ) . getSizeInBits ( ) ) { unsigned Type = L ->


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __pause ( void ) { __builtin_ia32_pause ( )


<s> if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset


<s> assert ( ( IsFadd || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , IsFadd ) && shouldCombineToHorizontalOp ( LHS == RHS , DAG , Subtarget ) ) { auto NewOpcode = IsFadd ? <STR_LIT> :


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else


<s> O << MO . getImm ( ) ; return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << <STR_LIT> ; return false ; case MachineOperand :: MO_Register : O << '(' ; printOperand ( * this , MI , OpNo , O ) ; O << ')' ; return false ; } case 'c' : switch ( MO . getType ( ) ) { default : printOperand ( * this , MI , OpNo , O ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; break ; } return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( * this , MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDXAddr20Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ; uint64_t Index = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isInt < <NUM_LIT> > ( Disp )


<s> static SetOfMachineInstr & getSet ( BlockToSetOfInstrsPerColor & sets , const MachineBasicBlock & MBB , unsigned reg , unsigned nbRegs ) { SetOfMachineInstr * result ; BlockToSetOfInstrsPerColor :: iterator it = sets . find ( & MBB ) ; if ( it != sets . end ( ) ) result = it -> second . get ( ) ; else result = ( sets [ & MBB ] = make_unique < SetOfMachineInstr [ ] > ( nbRegs ) )


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : return false


<s> void <ISA_LIT>InstPrinter :: printBranchOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; if ( ! TT . isOSAIX ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; int32_t Imm = SignExtend32 < <NUM_LIT> > ( ( unsigned ) MI -> getOperand ( OpNo ) . getImm ( ) << <NUM_LIT> ) ; if ( Imm >= <NUM_LIT> ) O << <STR_LIT> ; O <<


<s> return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind


<s> bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg ,


<s> if ( SrcRC == & <STR_LIT> ) return & <STR_LIT> ; if ( SrcRC == & <STR_LIT> ) return & <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; return


<s> Op -> Mem . IndexReg = Index ; Op -> Mem . Index = nullptr ; Op -> Mem . Offset = Imm ; return Op


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> return ( __m128d ) __builtin_ia32_cmpneqsd ( ( __v2df )


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT , const MachineFunction & ) const { Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> bool <ISA_LIT>PreAMXConfig :: preTileConfig ( ) { DenseMap < Instruction * , SmallVector < Value * , <NUM_LIT> >> PosAndShapes ; bool NeedCfg = findConfigShapes ( PosAndShapes )


<s> unsigned LATOpcode = TII -> getLoadAndTrap ( MI . getOpcode ( ) ) ; if ( ! LATOpcode ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; while ( Branch -> getNumOperands ( ) ) Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( LATOpcode ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true


) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static __inline void _mm_free ( void * __ptr ) { free ( __ptr


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; Register FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI


<s> return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch


<s> static __inline qword si_fcmeq ( qword a , qword b ) { vec_float4 msb = ( vec_float4 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return ( ( qword ) ( vec_cmpeq ( vec_andc ( ( vec_float4 ) ( a ) , msb ) , vec_andc ( ( vec_float4 ) ( b


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { emit_insn ( gen_aarch64_load_exclusive ( mode , rval ,


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( RA , getRegClassFor ( VT


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_'


<s> return SelectThumbAddrModeRI ( N , Base


<s> unsigned <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm8OpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI .


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return <STR_LIT> ; assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT> ) ; return <STR_LIT>


<s> InvertOrigBranch = true ; TargetIsFallThrough = true ; return ; case <STR_LIT> : InvertNewBranch = UsingDef1 ; InvertOrigBranch = ! UsingDef1 ; TargetIsFallThrough = false ; return ; case <STR_LIT> : InvertNewBranch = ! UsingDef1 ; InvertOrigBranch = ! UsingDef1 ; TargetIsFallThrough = true ; return ; } } else if ( BROp == <STR_LIT> || BROp == <STR_LIT> ) { switch ( CROp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : InvertNewBranch = true ; InvertOrigBranch = false ; TargetIsFallThrough = true ; return ; case <STR_LIT> : InvertNewBranch = false ; InvertOrigBranch = false ; TargetIsFallThrough = false ; return ; case <STR_LIT> : InvertNewBranch = false ; InvertOrigBranch = true ; TargetIsFallThrough = true ; return ; case


<s> if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return Val > - <NUM_LIT> && Val < <NUM_LIT> ; } return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMSA128Reg


<s> bool Lo = Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; MVT ShuffleVT = <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; Op = DAG . getBitcast ( ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( RootVT , Op ) , true ) ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { bool Lo = Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; MVT ShuffleVT = <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; Op = DAG . getBitcast ( ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( RootVT , Op ) , true ) ; return true ; } } if ( ! FloatDomain && VT . is128BitVector ( ) && ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) { bool Lo = Mask [ <NUM_LIT> ] == <NUM_LIT> ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; MVT ShuffleVT ; switch ( Mask . size ( ) ) { case <NUM_LIT> : ShuffleVT =


<s> if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool MIIsUnscaled = isUnscaledLdst ( MI -> getOpcode ( ) ) ; if ( ! inBoundsForPair ( MIIsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; continue ; } if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; continue ; } if ( MayLoad && Reg == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; continue ; } if ( ! ModifiedRegs [ MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ] && ! UsedRegs [ MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ] ) { MergeForward = false ; return MBBI ; } if ( ! ModifiedRegs [ FirstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ] && ! UsedRegs [ FirstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ] ) { MergeForward = true ; return MBBI ; } } } if ( MI -> mayStore ( ) || MI -> isCall ( )


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { return NumCycles ==


<s> SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements (


<s> switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ; Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; if ( Diff != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( Diff , DL , Cond . getValueType ( ) ) ) ; if ( FalseC -> getAPIntValue ( ) != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } } } } if ( ! DCI . isBeforeLegalize ( ) && ! DCI . isBeforeLegalizeOps ( ) ) { ConstantSDNode * CmpAgainst = nullptr ; if ( ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) && ( CmpAgainst = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) && ! isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) { if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( FalseOp ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( TrueOp ) ) { SDValue Ops [ ] = { FalseOp , Cond . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CC , DL , <STR_LIT> ) , Cond } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } } } if ( CC == <STR_LIT> ) { SDValue Flags ; <STR_LIT> CC0 , CC1 ; bool isAndSetCC ; if ( checkBoolTestAndOrSetCCCombine ( Cond , CC0 , CC1 , Flags , isAndSetCC ) ) { if ( isAndSetCC ) { std :: swap ( FalseOp , TrueOp ) ; CC0 = <STR_LIT> ( CC0 ) ; CC1 = <STR_LIT> ( CC1 ) ; } SDValue LOps [ ] = { FalseOp , TrueOp , DAG . getConstant ( CC0 , DL , <STR_LIT> ) , Flags } ; SDValue LCMOV = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , LOps ) ; SDValue Ops [ ] = { LCMOV , TrueOp , DAG . getConstant ( CC1 , DL , <STR_LIT> ) , Flags } ; SDValue CMOV = DAG . getNode ( <STR_LIT> , DL ,


<s> int gpr_reg_base ; rtx retval ; if ( mode == VOIDmode ) return NULL_RTX ; arg_size = FUNCTION_ARG_SIZE ( mode , type ) ; if ( ! TARGET_64BIT ) { if ( cum -> words + arg_size > max_arg_words ) return NULL_RTX ; } else { if ( arg_size > <NUM_LIT> ) alignment = cum -> words & <NUM_LIT> ; if ( cum -> words + alignment >= max_arg_words ) return NULL_RTX ; } if ( TARGET_64BIT ) { gpr_reg_base = <NUM_LIT> - cum -> words ; fpr_reg_base = <NUM_LIT> + cum -> words ; if ( arg_size > <NUM_LIT> || mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> , ub = arg_size ; gpr_reg_base -= alignment ; ub = MIN ( ub , max_arg_words - cum -> words - alignment ) ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , GEN_INT ( offset ) ) ; gpr_reg_base -= <NUM_LIT> ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( ub , loc ) ) ; } } else { if ( arg_size > <NUM_LIT> ) { if ( cum -> words ) { gpr_reg_base = <NUM_LIT> ; fpr_reg_base = <NUM_LIT> ; } else { gpr_reg_base = <NUM_LIT> ; fpr_reg_base = <NUM_LIT> ; } if ( mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } else { gpr_reg_base = <NUM_LIT> -


<s> SMLoc S = getLoc ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) return MatchOperand_NoMatch ; auto Ry = Operands . back ( ) -> getReg ( ) ; Operands . pop_back ( ) ; if ( getLexer ( ) . isNot ( AsmToken


<s> TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI


<s> bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { IsResolved = true ; ( void ) adjustFixupValue ( Fixup , Value , & Asm .


<s> static HOST_WIDE_INT arm_vector_alignment ( const_tree type ) { HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; if ( TARGET_AAPCS_BASED ) align = MIN


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseRegs ( Operands , is<ISA_LIT>64 ( ) ? ( int ) <STR_LIT> : ( int ) <STR_LIT> ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( IdVal == <NUM_LIT> ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; int RegNo = op -> getReg ( ) ; Operands . pop_back (


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return Cost ; } if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> && CondTy ) { static const TypeConversionCostTblEntry NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first ; } int BaseCost =


<s> if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OddReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg


<s> Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; ArgInfos . push_back ( Arg ) ; OrigArgIndices . push_back ( i ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; bool IsCalleeVarArg = false ; if ( Info . Callee . isGlobal ( ) ) { const Function * CF = static_cast < const Function * > ( Info . Callee . getGlobal ( ) ) ; IsCalleeVarArg = CF -> isVarArg ( ) ; } <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , IsCalleeVarArg , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , <NUM_LIT> ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; if ( IsCalleeGlobalPIC ) { MIRBuilder . buildCopy ( Register ( <STR_LIT> ) , MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseRegForGlobalISel ( ) ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( MIB -> getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MIRBuilder . getMF (


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ; return false


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> ||


<s> void <ISA_LIT>TargetStreamer :: emitStoreWithImmOffset ( unsigned Opcode , unsigned SrcReg , unsigned BaseReg , int64_t Offset , std :: function < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { if ( isInt < <NUM_LIT> > ( Offset ) ) { emitRRI ( Opcode , SrcReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned ATReg = GetATReg


<s> <ISA_LIT>O0PreLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) { if ( ! GeneratedRuleCfg . parseCommandLineOption ( ) )


<s> auto CalleeArgIter = CB . arg_begin ( ) ; auto CalleeArgEnd = CB . arg_end ( ) ; Function :: const_arg_iterator CallerArgIter = CallerFn -> arg_begin ( ) ; for ( ; CalleeArgIter != CalleeArgEnd ; ++ CalleeArgIter , ++ CallerArgIter ) { const Value * CalleeArg = * CalleeArgIter ; const Value * CallerArg = & ( * CallerArgIter ) ; if ( CalleeArg == CallerArg


<s> if ( startswith ( format , <STR_LIT> ) ) { format += <NUM_LIT> ; return acle_svprfop ; } gcc_unreachable ( ) ; } if ( ch == 's' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ; } if ( ch == 't' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; vector_type_index vector_type = type_suffixes [ suffix ] . vector_type ; unsigned int num_vectors = instance . vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - <NUM_LIT> ] [ vector_type ] ; } if ( ch == 'v' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return acle_vector_types [ <NUM_LIT> ] [ type_suffixes [ suffix ] . vector_type


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> )


<s> static unsigned getSubRegIndex ( const TargetRegisterClass * RC ) { unsigned SubIdx = <STR_LIT> ; if ( RC == & <STR_LIT> ) { SubIdx = <STR_LIT>


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return RC -> hasSubClassEq ( MRI -> getRegClass ( Reg ) ) ; return RC -> contains (


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeGV ( const GlobalValue * GV , MVT VT ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return <NUM_LIT> ; <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( GV , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == nullptr ) return AM . Base . Reg ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static && TLI . getPointerTy ( ) == <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addGlobalAddress ( GV ) ; } else { unsigned Opc = TLI . getPointerTy ( ) == <STR_LIT> ? ( Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; } return


<s> } } if ( i386_pe_dllexport_p ( decl ) ) i386_pe_mark_dllexport ( decl ) ; else if ( i386_pe_dllimport_p ( decl ) ) i386_pe_mark_dllimport ( decl ) ; else gcc_assert ( ! ( ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CODE ( decl ) == VAR_DECL ) && rtl != NULL_RTX && GET_CODE ( rtl ) == MEM && GET_CODE ( XEXP ( rtl , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XEXP ( rtl , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && i386_pe_dllimport_name_p ( XSTR ( XEXP (

XEXP ( rtl , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ;


<s> case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFP_TO_SINTCombine ( N , DAG ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( find ( WidenedMask , SM_SentinelZero ) != WidenedMask . end ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } if ( canonicalizeShuffleMaskWithCommute ( Mask ) ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( SDValue V = lowerVectorShuffleWithVPMOV ( DL , Mask , VT , V1 , V2 , DAG , Subtarget ) ) return V ; if ( VT . is128BitVector ( ) ) return lower128BitVectorShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ; if ( VT . is256BitVector ( ) ) return lower256BitVectorShuffle ( DL , Mask , VT , V1 , V2 , Zeroable


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream

& O , StringRef Annot , const MCSubtargetInfo & STI ) {


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i


<s> while ( ( Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ) != Exit ) { if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp % <NUM_LIT> ) return ; StackDisp /= <NUM_LIT> ; assert ( ( size_t ) StackDisp < Context . MovVector . size ( ) && <STR_LIT> ) ; if ( Context . MovVector [ StackDisp


<s> Idx [ <NUM_LIT> ] = Builder . getInt32 ( getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ getTranslator ( ) . getRegSetDesc ( ) . RegLargestSupers [ <STR_LIT> ] ] ) ; return Builder . CreateTrunc ( Builder . CreateLoad ( Builder . CreateInBoundsGEP ( RegSet , Idx ) ) , Builder . getInt32Ty


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) isImplicitlyPrivate = true ; getMang ( ) -> getNameWithPrefix ( Name , GV , isImplicitlyPrivate ) ; } else if ( MO . isSymbol ( ) ) { Name += MAI . getGlobalPrefix ( ) ; Name += MO . getSymbolName ( ) ; } else if ( MO . isMBB ( ) ) { Name += MO . getMBB ( ) -> getSymbol ( ) -> getName ( ) ; } switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : { const char * Prefix = <STR_LIT> ; Name . insert ( Name . begin ( ) , Prefix , Prefix + strlen ( Prefix ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; }


<s> static tree ix86_md_asm_clobbers ( tree , tree , tree clobbers ) { clobbers = tree_cons ( NULL_TREE , build_string ( <NUM_LIT> , <STR_LIT> ) ,


<s> bool loongarch_symbol_binds_local_p ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return false ; return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P


<s> switch ( Opc ) { case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; if ( base . getReg ( ) == ( target . getReg ( ) ) ) { instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( atReg ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( atReg ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; instr3 = move ; } else { two_instructions = true ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; } break ; } case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( atReg ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; instr3 . setOpcode ( <STR_LIT> ) ; instr3 . addOperand ( target ) ; instr3 . addOperand ( atReg ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( base . getReg ( ) != target . getReg ( ) ) ; two_instructions = true ; MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; break ; } case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( atReg ) ; instr2 . addOperand (


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property ::


<s> return ( int8x16_t ) __builtin_neon_vqaddsv16qi ( __a ,


<s> EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( SrcRegs [ I ] != DestRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> AddComment (


<s> if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef && any_of ( Mask , [ NumElements ] ( int M ) { return M >= NumElements ; } ) ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , DL , V1 , V2 , NewMask ) ; } int MaskUpperLimit = Mask . size ( ) * ( V2IsUndef ? <NUM_LIT> : <NUM_LIT> ) ; ( void ) MaskUpperLimit ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return - <NUM_LIT> <= M && M < MaskUpperLimit ; } ) && <STR_LIT> ) ; APInt Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; if ( Zeroable . isAllOnesValue ( ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; bool V2IsZero = ! V2IsUndef && <STR_LIT> ( V2 . getNode ( ) ) ; SmallVector < int , <NUM_LIT> > ZeroableMask ( Mask . begin ( ) , Mask . end ( ) ) ; if ( V2IsZero ) { assert ( ! Zeroable . isNullValue ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElements ; ++ i ) if ( Mask [ i ] != SM_SentinelUndef && Zeroable [ i ] ) ZeroableMask [ i ] = SM_SentinelZero ; } SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( ZeroableMask , WidenedMask ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT .


<s> const <ISA_LIT>TargetLowering * getTLI (


<s> static DecodeStatus DecodeGPRRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler ::


<s> Sec -> setAlignment ( <NUM_LIT> ) ; OS . PushSection ( ) ; OS . SwitchSection ( Sec ) ; OS . EmitValueImpl ( ExprRef , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> ,


<s> if ( group == disp_no_group || group == disp_branch ) return true ; if ( window_list_next ) window_list = window_list_next ; if ( window_list -> window_num == <NUM_LIT> ) { sum = window_list -> prev -> window_size + window_list -> window_size ; if ( sum == <NUM_LIT> || ( ix86_min_insn_size ( insn ) + sum ) >= <NUM_LIT> ) return true ; } num_restrict = count_num_restricted ( insn , window_list ) ; if ( num_restrict > num_allowable_groups [ group ] ) return false ; if ( window_list -> window_num


<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) const { unsigned VaListSize = Subtarget -> isTargetDarwin ( ) ? <NUM_LIT> : <NUM_LIT> ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue


<s> switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = <NUM_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( signExtend &&


<s> int Splat = getT2SOImmValSplatVal ( Arg ) ; if ( Splat != - <NUM_LIT> ) return Splat ; int Rot = getT2SOImmValRotateVal


<s> MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( getANDriOpcode ( Uses64BitFramePtr , Val ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Val ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead (


<s> if ( CALL_P ( insn ) ) { if ( cfun -> machine -> func_type == TYPE_NORMAL ) return X86_DIRFLAG_ANY ; else return TARGET_CLD ? X86_DIRFLAG_ANY : X86_DIRFLAG_RESET ; } if ( recog_memoized ( insn ) < <NUM_LIT> ) return X86_DIRFLAG_ANY ; if ( get_attr_type ( insn ) == TYPE_STR ) { if ( cfun -> machine -> func_type == TYPE_NORMAL ) return TARGET_CLD ? X86_DIRFLAG_RESET : X86_DIRFLAG_ANY ; else return


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_NOREORDER ; MCA . setELFHeaderEFlags


<s> unsigned CallOpc = getCallOpcode ( CFlags , DAG . getMachineFunction ( ) . getFunction ( ) , Callee , Subtarget , DAG . getTarget ( ) ) ; if ( ! CFlags . IsIndirect ) Callee = transformCallee ( Callee , DAG , dl , Subtarget ) ; else if ( Subtarget . usesFunctionDescriptors ( ) ) prepareDescriptorIndirectCall ( DAG , Callee , Glue , Chain , CallSeqStart , CB , dl , CFlags . HasNest , Subtarget ) ; else prepareIndirectCall ( DAG , Callee , Glue , Chain , dl ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; buildCallOperands ( Ops , CFlags , dl , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget ) ; if ( CFlags . IsTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) || ( CFlags . IsIndirect && Subtarget . isUsingPCRelativeCalls ( ) ) ) && <STR_LIT> <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { { <STR_LIT> , <STR_LIT> } } ; Chain = DAG . getNode ( CallOpc , dl , ReturnTypes , Ops ) ; DAG . addNoMergeSiteInfo ( Chain . getNode ( ) , CFlags . NoMerge ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; int BytesCalleePops = ( CFlags . CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( BytesCalleePops , dl , true ) , Glue , dl ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , Glue , CFlags . CallConv , CFlags . IsVarArg , Ins


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter


<s> return __builtin_aarch64_reduc_smin_scal_v8qi (


<s> bool SelectAddrImmX16 ( SDValue N , SDValue &


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , DebugLoc dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) ,


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) <<


<s> MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || ! Succ -> begin ( ) -> isPHI ( ) ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( llvm :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E = NewBB -> end ( ) ; I != E ; ++ I ) NewBBSize += TII -> GetInstSizeInBytes ( I ) ; unsigned OrigBBI = OrigBB -> getNumber


<s> switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> getTargetStreamer ( ) . EmitARM64WinCFISetFP ( ) ; return false


<s> raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( I , TmpInst0 ) ; EmitToStreamer ( OutStreamer , TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( )


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , CmpOp , A64cc , DestBB ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; SDValue A64BR_CC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , SetCC , A64cc , DestBB ) ; if ( Alternative != <STR_LIT> ) { A64cc = DAG . getConstant ( Alternative , <STR_LIT> ) ; A64BR_CC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A64BR_CC , SetCC , A64cc , DestBB ) ; } return


<s> bool hasPopulationCount ( ) const { return


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex (

Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc , Len , Size ) ) ; const MCExpr * Imm = MCConstantExpr :: Create ( Size , getContext ( ) ) ; return <STR_LIT> ( Imm , Start


<s> } ; if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment ,


<s> for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset -= Info . SPAdjust ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction

:: createDefCfaOffset ( nullptr , CFAOffset ) ) ;


<s> } } if ( OtherUsers || KillsAddendSrc ) continue ; unsigned KilledProdOp = <NUM_LIT> , OtherProdOp = <NUM_LIT> ; if ( LIS -> getInterval ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . Query ( FMAIdx ) . isKill ( ) ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } else if ( LIS -> getInterval ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . Query ( FMAIdx ) . isKill ( ) ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } if ( ! KilledProdOp ) continue ; if ( TargetRegisterInfo :: isVirtualRegister ( AddendSrcReg ) && ! LIS -> getInterval ( AddendSrcReg ) . liveAt ( FMAIdx ) ) continue ; unsigned KilledProdReg = MI -> getOperand ( KilledProdOp ) . getReg ( ) ; unsigned OtherProdReg = MI -> getOperand ( OtherProdOp ) . getReg ( ) ; unsigned AddSubReg = AddendMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned KilledProdSubReg = MI -> getOperand ( KilledProdOp ) . getSubReg ( ) ; unsigned OtherProdSubReg = MI -> getOperand ( OtherProdOp ) . getSubReg ( ) ; bool AddRegKill = AddendMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool KilledProdRegKill = MI -> getOperand ( KilledProdOp ) . isKill ( ) ; bool OtherProdRegKill = MI -> getOperand ( OtherProdOp ) . isKill ( ) ; bool AddRegUndef = AddendMI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool KilledProdRegUndef = MI -> getOperand ( KilledProdOp ) . isUndef ( ) ; bool OtherProdRegUndef = MI -> getOperand ( OtherProdOp ) . isUndef ( ) ; unsigned OldFMAReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( OldFMAReg == KilledProdReg ) continue ; if ( ! MRI . constrainRegClass ( KilledProdReg , MRI . getRegClass ( OldFMAReg ) ) ) continue ; assert ( OldFMAReg == AddendMI -> getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ; ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( KilledProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( KilledProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( AddendSrcReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( OtherProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( KilledProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( KilledProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( AddSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( OtherProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( KilledProdRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( AddRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( OtherProdRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef (


<s> if ( a >= - ( DFtype ) ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) return ( SItype ) ( a + ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ; return ( SItype


<s> MachineMemOperand * MMO ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; Chain = ST -> getChain ( ) ; Base = ST -> getBasePtr ( ) ; MMO = ST -> getMemOperand ( ) ; SrcOpnd = <NUM_LIT> ; if ( MMO -> getSize ( ) < <NUM_LIT> ) return SDValue ( ) ; break ; } case <STR_LIT> : { MemIntrinsicSDNode * Intrin = cast < MemIntrinsicSDNode > ( N ) ; Chain = Intrin -> getChain ( ) ; Base = Intrin -> getOperand ( <NUM_LIT> ) ; MMO = Intrin -> getMemOperand ( ) ; SrcOpnd = <NUM_LIT> ; break ; } } SDValue Src = N ->


<s> unsigned NewOpc = sForm ( * MI ) ; if ( NewOpc == <STR_LIT> ) return false ; if ( ! canInstrSubstituteCmpInstr ( MI , CmpInstr , TRI ) ) return false ; MI -> setDesc ( get ( NewOpc ) ) ; CmpInstr -> eraseFromParent ( ) ; bool succeeded = UpdateOperandRegClass ( MI ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; MI -> addRegisterDefined ( <STR_LIT> , TRI ) ; return


<s> Stub * <ISA_LIT>ToTHMStub :: doClone ( ) { return new <ISA_LIT>ToTHMStub ( m_pData , m_Size , fixup_begin ( ) ,


<s> if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { E = MI . getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( MI . getOperand ( I ) . isReg ( ) ) { unsigned SrcReg = MI . getOperand ( I ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI == NULL || ! isSignOrZeroExtended ( * SrcMI , SignExt , Depth + <NUM_LIT> ) ) return false ; } else return false ; } return true ; } case <STR_LIT> : case <STR_LIT>


<s> if ( Subtarget . hasInt256 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; return true


<s> if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType ( ) . getSimpleVT ( ) != <STR_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction


<s> } if ( ! Shift ) return Result ; if ( ( unsigned ) ( Imm & <NUM_LIT> ) == Remainder ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( Imm ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> - Shift ) ) ; } if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm


<s> void <ISA_LIT>TargetELFStreamer :: emitObjectArch ( <STR_LIT> Value ) { EmittedArch =


<s> MCAsmParser & Parser = getParser ( ) ; auto Token = Parser . getLexer ( ) . peekTok ( false ) ; if ( Token . is ( AsmToken :: Identifier ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; StringRef Identifier = Token . getIdentifier ( ) ; OperandMatchResultTy ResTy = matchAnyRegisterNameWithoutDollar ( Operands , Identifier , S ) ; return ResTy


<s> if ( CModel == CodeModel :: Large || ! GVar || ! GVar -> hasInitializer ( ) || GVar -> hasCommonLinkage ( ) || GVar -> hasAvailableExternallyLinkage ( ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; } return DestReg


<s> bool UseFastISel = TM . Options . EnableFastISel && Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . in<ISA_LIT>16Mode ( ) && ! Subtarget . inMicro<ISA_LIT>Mode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) || Subtarget . useXGOT ( ) ) UseFastISel = false ; return UseFastISel ? <STR_LIT> ( funcInfo ,


<s> const int CC = static_cast < const int > ( MI


<s> __ev64_opaque__ v ; int16_t i [ <NUM_LIT> ] ; } u ; u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT> ]


<s> static DecodeStatus DecodeBranchImmInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> )


<s> if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ; return false


<s> static unsigned int aarch64_sve_adjust_stmt_cost ( class vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( kind == vector_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) stmt_cost = <NUM_LIT> ; if ( kind == vector_stmt && aarch64_integer_truncation_p ( stmt_info ) ) stmt_cost = <NUM_LIT> ; if ( STMT_VINFO_GROUPED_ACCESS ( stmt_info ) ) { stmt_vec_info first = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; unsigned int count = DR_GROUP_SIZE ( first ) - DR_GROUP_GAP ( first ) ; unsigned int elt_bits = GET_MODE_UNIT_BITSIZE ( TYPE_MODE ( vectype ) ) ; if ( multiple_p ( count * elt_bits , <NUM_LIT> ) && aarch64_advsimd_ldp_stp_p ( kind , stmt_info ) ) stmt_cost *= <NUM_LIT> ; } return stmt_cost


<s> unsigned RegOp0 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegOp1 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg0 = Ctx . getRegisterInfo ( ) -> getEncodingValue ( RegOp0 ) ; unsigned Reg1 = Ctx . getRegisterInfo ( ) -> getEncodingValue ( RegOp1 ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { assert ( Reg0 != Reg1 && <STR_LIT> ) ; if ( Reg0 < Reg1 ) return ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Reg0 >= Reg1 ) return ; } else llvm_unreachable ( <STR_LIT> ) ; Inst . getOperand ( <NUM_LIT> ) . setReg ( RegOp1 ) ; Inst . getOperand ( <NUM_LIT> ) . setReg (


<s> bool canExtendTo512BW ( ) const { return hasBWI ( )


<s> unsigned Idx = Lane >= ( int ) VT . getVectorNumElements ( ) / <NUM_LIT> ; Lane -= Idx * VT . getVectorNumElements ( ) / <NUM_LIT> ; V1 = WidenVector ( V1 . getOperand ( Idx ) , DAG ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V1 = WidenVector ( V1 , DAG ) ; return DAG . getNode ( Opcode , dl , VT , V1 , DAG . getConstant ( Lane , dl , <STR_LIT> ) ) ; } if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; bool ReverseEXT = false ; unsigned Imm ; if ( isEXTMask ( ShuffleMask , VT , ReverseEXT , Imm ) ) { if ( ReverseEXT ) std :: swap ( V1 , V2 ) ; Imm *= getExtFactor ( V1 ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } else if ( V2 -> getOpcode ( ) == <STR_LIT> && isSingletonEXTMask ( ShuffleMask , VT , Imm ) ) { Imm *= getExtFactor ( V1 ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V1 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } unsigned WhichResult ; if ( isZIPMask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( ) , V1 , V2 ) ; } if ( isUZPMask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( ) , V1 , V2 ) ; } if ( isTRNMask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( )


<s> MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; int Offset = getBackchainOffset ( MF ) - <STR_LIT> ; FI = MFFrame . CreateFixedObject ( <NUM_LIT> , Offset , false ) ; ZFI -> setFramePointerSaveIndex


<s> MachineInstr * NewInst = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opc ) ) . addDef ( Dest ) . add ( BaseAddr ) . addImm ( Offset ) . addUse ( TiedDest ) . addMemOperand ( * I . memoperands_begin ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * NewInst , TII


<s> return & InstrInfo . getRegisterInfo (


<s> bool hasV8MMainlineOps ( ) const { return HasV8MMainlineOps


<s> void addInst ( MachineInstr * MI , SetVector < MachineInstr * > & Preds ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( ! Divergent && ! set_difference ( Preds , PredicateThen -> Predicates ) . empty ( ) ) { Divergent = & Insts . back ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Divergent -> MI ) ; } Insts . emplace_back ( MI , Preds )


<s> auto ceil = [ ] ( unsigned A , unsigned B ) { return ( A + B - <NUM_LIT> ) / B ; } ; unsigned NumElts = cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) ; assert ( Factor > <NUM_LIT> && NumElts % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned VF = NumElts / Factor ; unsigned NumEltsPerVecReg = ( <NUM_LIT> / getScalarSizeInBits ( VecTy ) ) ; unsigned NumVectorMemOps = getNumVectorRegs ( VecTy ) ; unsigned NumPermutes = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) { BitVector UsedInsts ( NumVectorMemOps , false ) ; std :: vector < BitVector > ValueVecs ( Factor , BitVector ( NumVectorMemOps , false ) ) ; for ( unsigned Index : Indices ) for ( unsigned Elt = <NUM_LIT> ; Elt < VF ; ++ Elt ) { unsigned Vec = ( Index + Elt * Factor ) / NumEltsPerVecReg ; UsedInsts . set ( Vec ) ; ValueVecs [ Index ] . set ( Vec ) ; } NumVectorMemOps = UsedInsts . count ( ) ; for ( unsigned Index : Indices ) { unsigned NumSrcVecs = ValueVecs [ Index ] . count ( ) ; unsigned NumDstVecs = ceil ( VF * getScalarSizeInBits ( VecTy )


<s> const TargetRegisterClass * RC = TRI . isPhysicalRegister ( Reg ) ? TRI . getMinimalPhysRegClass ( Reg ) : MRI . getRegClass ( Reg ) ; unsigned OpcCmp = ~ <NUM_LIT> ; if ( RC -> hasSuperClassEq ( & <STR_LIT>


__index , int const * __addr , int __scale ) {


<s> assert ( AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> ) ; if ( AM . BaseType == <STR_LIT> ) MIB . addReg ( AM . Base . Reg ) ; else if ( AM . BaseType == <STR_LIT> ) MIB . addFrameIndex ( AM . Base . FrameIndex ) ; else assert ( <NUM_LIT> ) ; MIB . addImm ( AM . Scale ) .


<s> bool isImmSExti16i8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return true ; return isImmSExti16i8Value ( CE -> getValue (


<s> EVT VT = V2 . getValueType ( ) ; SDValue V1 = IsZero ? getZeroVector ( VT , Subtarget , DAG , SDLoc ( V2 ) ) : DAG . getUNDEF ( VT ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec . push_back ( i == Idx ? NumElems : i ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V2 ) ,


<s> } unsigned DelayLimit = SchedModel . MispredictPenalty * <NUM_LIT> / <NUM_LIT> ; unsigned HeadDepth = Trace . getInstrCycles ( * CmpConv . Head -> getFirstTerminator ( ) ) . Depth ; unsigned CmpBBDepth = Trace . getInstrCycles ( * CmpConv . CmpBB -> getFirstTerminator ( ) ) . Depth ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadDepth << <STR_LIT> << CmpBBDepth << '\n' ) ; if ( CmpBBDepth > HeadDepth + DelayLimit ) { DEBUG ( dbgs ( ) << <STR_LIT>


<s> assert ( ( RegClass == <STR_LIT> || RegClass == <STR_LIT> ) && <STR_LIT> ) ; bool isSP = ( RegClass == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRd ( insn , isSP ) ) ) ) ; ++ OpIdx ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRn ( insn , isSP ) ) ) ) ; ++


<s> assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; MVT ExtEltVT = ( NumElts <= <NUM_LIT> ) ? <STR_LIT> ( <NUM_LIT> / NumElts ) : <STR_LIT> ; MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } if ( EltVT != <STR_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Idx ) ; return DAG . getAnyExtOrTrunc ( Extract , dl , EltVT ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue (


<s> unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = <STR_LIT> ; else if ( OpTy -> isDoubleTy (


<s> if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = IsLittleEndian ? i


<s> FunctionPass * create<ISA_LIT>PostLegalizerLowering ( ) { return new <ISA_LIT>PostLegalizerLowering ( )


<s> addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . useConstIslands ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( create<ISA_LIT>NaClRewritePass (


<s> case E_QImode : return QUAL_TYPE ( QI ) ; case E_HImode : return QUAL_TYPE ( HI ) ; case E_SImode : return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ; case E_TImode : return QUAL_TYPE ( TI


<s> StringRef getPassName ( ) const override


<s> Zero = TBB ; break ; case <STR_LIT> : Nonzero = TBB ; Zero = FBB ; break ; default : return Optional < BlockBRNZ > ( ) ; } MachineBasicBlock :: const_reverse_instr_iterator MI = MBB . instr_rbegin ( ) ; while ( MI != MBB . instr_rend ( ) && MI -> isUnconditionalBranch ( ) ) ++ MI ; if ( MI == MBB . instr_rend ( ) || ! MI -> isConditionalBranch ( ) ) return Optional < BlockBRNZ > ( ) ; BlockBRNZ Desc ; Desc . Zero = Zero ; Desc . Nonzero = Nonzero ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & op = MI -> getOperand ( <NUM_LIT> ) ; if ( op . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return Optional < BlockBRNZ > ( ) ; Desc . IsKill = op . isKill ( ) ; Desc . Regs . push_back ( op . getReg ( ) ) ; break ; } if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return Optional < BlockBRNZ > ( ) ; } if ( Desc . Regs . size ( ) != <NUM_LIT> ) { return Optional < BlockBRNZ > ( ) ; } const Register & Reg0 = Desc . Regs [ <NUM_LIT> ] ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> isPHI ( ) ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg0 ) { unsigned NumOperands = MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOperands ; I += <NUM_LIT> ) { Desc . Regs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; } } return Desc ; } if ( MI -> modifiesRegister ( Reg0 , TRI ) ) return Optional < BlockBRNZ > ( ) ; if ( MI -> readsRegister ( Reg0 , TRI ) ) Desc . IsKill = false ; } return


<s> int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_pcmpgtw128 ( ( __v8hi


<s> SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) , DL ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , Offset , Op . getOperand ( <NUM_LIT> )


<s> if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned reglist = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( ! Check ( S , DecodeDPRRegListOperand ( Inst , reglist , Address , Decoder ) ) ) { return MCDisassembler


<s> if ( ListContainsSP && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; return