<s> if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; getTargetStreamer ( ) . emitPad ( CE -> getValue ( ) ) ; return false


<s> bool EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ,

const MCFixup * Fixup ) const override {


<s> switch ( get_attr_type ( insn ) ) { case TYPE_MAC : if ( REG_P ( XEXP ( exp , <NUM_LIT> ) ) ) return XEXP ( exp , <NUM_LIT> ) ; else return XEXP ( exp , <NUM_LIT> ) ; default : gcc_unreachable ( )


<s> addPass ( create<ISA_LIT>SEISelDAG ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> return NULL_TREE ; } if ( ! VECTOR_TYPE_P ( type ) ) { error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } if ( ! sizeless_type_p ( type ) ) { error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } tree new_sve_type_args = copy_list ( TREE_VALUE ( attr ) ) ; tree mangled_name_node = chain_index ( <NUM_LIT> , new_sve_type_args ) ; const char * old_mangled_name = IDENTIFIER_POINTER ( TREE_VALUE ( mangled_name_node ) ) ; char * new_mangled_name = xasprintf ( <STR_LIT> , old_mangled_name , ( int ) value ) ; TREE_VALUE ( mangled_name_node ) = get_identifier ( new_mangled_name ) ; free ( new_mangled_name


<s> if ( * CM == CodeModel :: Tiny ) report_fatal_error ( <STR_LIT> ) ; if ( * CM == CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> ) ; return * CM ; } if ( Is64Bit )


<s> if ( fpB != llvm :: <STR_LIT> ) return false ; return fpA == llvm :: <STR_LIT> || fpA == llvm :: <STR_LIT> || fpA


<s> static DecodeStatus DecodeBranchTarget10MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset )


<s> set_optab_libfunc ( ne_optab , mode , NULL ) ; set_optab_libfunc ( lt_optab , mode , NULL ) ; set_optab_libfunc ( le_optab , mode , NULL ) ; set_optab_libfunc ( ge_optab , mode , NULL


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetOps


<s> bool <ISA_LIT>AsmParser :: parseMemRegOffsetShift ( <STR_LIT> & St , unsigned & Amount ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else return Error ( Loc , <STR_LIT> ) ; Parser . Lex ( ) ; Amount = <NUM_LIT> ; if ( St != <STR_LIT> ) { Loc = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & HashTok = Parser . getTok


<s> MIB = BuildMI ( MBB , std :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( IsMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) .


<s> void addMem32Operands ( MCInst & Inst , unsigned N ) const { addMemOperands ( Inst ,


<s> if ( ( isa < CallInst > ( I ) && ! isa < IntrinsicInst > ( I ) ) || I ->


<s> Value * <ISA_LIT>IREmitter :: visitVMOVRRD ( const SDNode *


<s> bool enableIndirectBrExpand ( ) const override


<s> HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple


<s> for ( unsigned virtReg : virtRegs ) { for ( auto & useDef : regInfo . reg_operands ( virtReg ) ) { ( void ) useDef ; ++ useDefCount ; } } return ( useDefCount / degree


<s> static __inline __m64 _mm_absdiff_pu32 ( __m64 a , __m64 b ) { return ( __m64 ) __builtin_arm_wabsdiffw ( ( __v2si ) a ,


<s> if ( InterlEarlyExit . find ( Subtarget ) != InterlEarlyExit . end ( ) ) return InterlEarlyExit [ Subtarget ] ; for ( auto & I : IRT ) { OriginalMCID = & TII -> get ( I . OrigOpc ) ; for ( auto & Repl : I . ReplOpc ) ReplInstrMCID . push_back ( & TII -> get ( Repl ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) { InterlEarlyExit [ Subtarget ] = false ; return false ; } ReplInstrMCID . clear ( ) ; } InterlEarlyExit [ Subtarget ] = true ; break ; } return


<s> Value * <ISA_LIT>IREmitter :: visitCALL_NOLINK ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned FixedObject = IsWin64 ? alignTo ( AFI -> getVarArgsGPRSize ( ) , <NUM_LIT> ) : <NUM_LIT> ; unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize ( MF . getFrameInfo (


<s> const int64_t Offset = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; MI . setDesc ( get ( Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( <STR_LIT> ) . addImm ( Offset ) ; return true ; } } return false


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT , CPU ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS


<s> if ( ! Reg . isVirtual ( ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr & DefMI = * MRI -> getVRegDef ( Reg ) ; if ( ( DefMI . getOpcode ( ) != <STR_LIT> && DefMI . getOpcode ( ) != <STR_LIT> ) || DefMI . getParent (

) != FrameSetup -> getParent ( ) ) return nullptr ;


<s> if ( ThreeOp ) return MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) ; return MIB . addFrameIndex ( FI ) .


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> unsigned int save_reg_mask = <NUM_LIT> ; unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return <NUM_LIT> ; if ( frame_pointer_needed ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( )


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; if ( TARGET_HAVE_MVE && ( VALID_MVE_SI_MODE ( mode ) || VALID_MVE_PRED_MODE ( mode ) ) )


<s> __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT>


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return


<s> assert ( MI -> getOpcode ( ) == TargetOpcode :: COPY && <STR_LIT> ) ; for ( const auto & MO : MI -> operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI . memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI . memoperands_end ( ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * checkSspMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * fallMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * fixShadowMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * fixShadowLoopPrepareMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * fixShadowLoopMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , checkSspMBB ) ; MF -> insert ( I , fallMBB ) ; MF -> insert ( I , fixShadowMBB ) ; MF -> insert ( I , fixShadowLoopPrepareMBB ) ; MF -> insert ( I , fixShadowLoopMBB ) ; MF -> insert ( I , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , MachineBasicBlock :: iterator ( MI ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( checkSspMBB ) ; unsigned ZReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned XorRROpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( checkSspMBB , DL , TII -> get ( XorRROpc ) ) . addDef ( ZReg ) . addReg ( ZReg , RegState :: Undef ) . addReg ( ZReg , RegState :: Undef ) ; unsigned SSPCopyReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned RdsspOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( checkSspMBB , DL , TII -> get ( RdsspOpc ) , SSPCopyReg ) . addReg ( ZReg ) ; unsigned TestRROpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( checkSspMBB , DL , TII -> get ( TestRROpc ) ) . addReg ( SSPCopyReg ) . addReg ( SSPCopyReg ) ; BuildMI ( checkSspMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; checkSspMBB -> addSuccessor ( sinkMBB


<s> bool <ISA_LIT>TargetLowering :: isEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , SelectionDAG & DAG ) const { if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; for ( Function :: const_arg_iterator i = CallerF -> arg_begin ( ) , e = CallerF -> arg_end ( ) ; i != e ; ++ i ) if ( i -> hasByValAttr ( ) ) return false ; if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return canGuaranteeTCO ( CalleeCC ) && CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) return false ; const MachineRegisterInfo & MRI = MF . getRegInfo


V1 , V2 , Zeroable , Subtarget , DAG ) ) return PSHUFB ;


<s> assert ( VecWidth == <NUM_LIT> && <STR_LIT> ) ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; uint64_t InsertIdx = ( Index * VecVT . getScalarSizeInBits ( ) ) / VecWidth ; assert ( ( InsertIdx == <NUM_LIT> || InsertIdx == <NUM_LIT> ) && <STR_LIT> ) ; return getI8Imm ( InsertIdx ? <NUM_LIT> : <NUM_LIT>


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator I = F . begin ( ) ; I != F .

end ( ) ; ++ I ) Changed |= runOnMachineBasicBlock ( * I ) ;


<s> ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ) ; return true ; } } } else if ( isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) ) { if ( isMask_64 ( Imm64 ) ) { MB = <NUM_LIT> - countTrailingOnes ( Imm64 ) ; SH = <NUM_LIT> ; if ( Val . getOpcode ( ) == <STR_LIT> ) { auto Op0 = Val . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Op0 . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm <= MB ) { auto ResultType = Val . getNode ( ) -> getValueType ( <NUM_LIT> ) ; auto ImDef = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResultType ) ; SDValue IDVal ( ImDef , <NUM_LIT> ) ; Val = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , ResultType , IDVal , Op0 . getOperand ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SH = <NUM_LIT> - Imm ; } } if ( Val . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Val . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm <= MB ) { assert ( Imm < <NUM_LIT> && <STR_LIT> ) ; Val = Val . getOperand ( <NUM_LIT> ) ; SH = <NUM_LIT> - Imm ; } SDValue Ops [ ] = { Val , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } else if ( isMask_64 ( ~ Imm64 )


<s> else if ( STI . hasFeature ( <STR_LIT> ) ) { if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; else if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; else if ( STI . hasFeature ( <STR_LIT> ) ) { if ( STI . hasFeature ( <STR_LIT> ) && STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; else if ( STI . hasFeature ( <STR_LIT>


<s> return ( ( split_type != SPLIT_FOR_SPEED || mips_tuning_info . fast_mult_zero_zero_p ) && src == const0_rtx && REG_P ( dest ) && GET_MODE_SIZE ( GET_MODE ( dest ) ) == <NUM_LIT> * UNITS_PER_WORD && ( ISA_HAS_DSP_MULT ? ACC_REG_P ( REGNO

( dest ) ) : MD_REG_P ( REGNO ( dest ) ) ) ) ;


<s> SDValue ExtsSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( ExtsSrc . getOpcode ( ) == <STR_LIT> && ExtsSrc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N0 ) ; SDValue ShiftBy = SDValue ( CN1 , <NUM_LIT> ) ; if ( ShiftBy . getValueType ( ) == <STR_LIT> ) ShiftBy = DCI . DAG . getConstant ( CN1 -> getZExtValue (


<s> unsigned getOffsetReg ( ) const { assert ( isRegBase ( ) &&


<s> return Kind == k_Register && Reg . Kind == RegKind :: SVEPredicate

&& <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> static bool isCSRestore ( MachineInstr * MI , const <ISA_LIT>BaseInstrInfo & TII , const unsigned * CSRegs ) { return ( ( MI -> getOpcode ( ) == ( int ) <STR_LIT> || MI -> getOpcode ( ) == ( int ) <STR_LIT> || MI -> getOpcode ( ) == ( int ) <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI ->

getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) ;


<s> if ( Offset ) Ptr = IRB . CreateConstGEP1_32 ( IRB . getInt8Ty ( ) , Ptr , Offset ) ; IRB . CreateCall ( SetTagFn , { Ptr , ConstantInt :: get ( IRB


<s> int _U_Qfle ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_EQ


<s> unsigned <ISA_LIT>FastISel :: MaterializeInt ( const Constant * C , MVT VT ) { if ( VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; const ConstantInt * CI = cast <


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > (


<s> if ( flag_pic ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , reg_names [ PIC_OFFSET_TABLE_REGNUM ] ) ; fprintf ( file , <STR_LIT> , reg_names [ PIC_OFFSET_TABLE_REGNUM ] , reg_names [ PIC_OFFSET_TABLE_REGNUM ] ) ; if ( TARGET_ISA_V3 ) fprintf ( file , <STR_LIT> ) ; else { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , reg_names [ PIC_OFFSET_TABLE_REGNUM ] , reg_names [ PIC_OFFSET_TABLE_REGNUM ] ) ; } } if ( delta != <NUM_LIT> ) { if ( satisfies_constraint_Is15 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , this_regno , this_regno , delta ) ; } else if ( satisfies_constraint_Is20 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } else { fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } } if ( flag_pic ) { fprintf ( file , <STR_LIT> ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , reg_names [ PIC_OFFSET_TABLE_REGNUM ] , reg_names [ STACK_POINTER_REGNUM ] ) ; fprintf ( file , <STR_LIT> ) ; } else { fprintf ( file


<s> case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; return false ; } if ( RegNo == <NUM_LIT> && Tok . getString ( ) . size ( ) == <NUM_LIT> && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; case '6' : RegNo = <STR_LIT>


<s> BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TrapBB ) ; MI -> eraseFromParent ( ) ; return ContBB


<s> if ( is_microcoded_insn ( insn ) ) return true ; if ( ! rs6000_sched_groups ) return false ; type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_DELAYED_CR : case TYPE_CR_LOGICAL : case TYPE_MTJMPR : case TYPE_MFJMPR : case TYPE_DIV : case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_ISYNC : case TYPE_SYNC : return true ; default : break ; } break ; case PROCESSOR_POWER6 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_EXTS : case TYPE_CNTLZ : case TYPE_TRAP : case TYPE_MUL : case TYPE_INSERT : case TYPE_FPCOMPARE : case TYPE_MFCR : case TYPE_MTCR : case TYPE_MFJMPR : case TYPE_MTJMPR : case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return true ; case TYPE_SHIFT : if ( get_attr_dot ( insn ) == DOT_NO || get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) return true ; else break ; case TYPE_DIV : if ( get_attr_size ( insn ) == SIZE_32 ) return true ; else break ; case TYPE_LOAD : case TYPE_STORE : case TYPE_FPLOAD : case TYPE_FPSTORE : if ( get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER7 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_CR_LOGICAL : case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_DIV : case TYPE_ISYNC : case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_MFJMPR : case TYPE_MTJMPR : return true ; case TYPE_MUL : case TYPE_SHIFT : case TYPE_EXTS : if ( get_attr_dot ( insn ) == DOT_YES ) return true ; else break ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES || get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : case TYPE_FPLOAD : case TYPE_FPSTORE : if ( get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_CR_LOGICAL : case TYPE_DELAYED_CR : case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_SYNC : case TYPE_ISYNC : case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_VECSTORE


<s> const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame -> getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { int64_t Delta = - int64_t ( StackSize )


<s> } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; if ( BaseReg == <STR_LIT> || ( Is64BitMode && DispForReloc ) ) { assert ( IndexReg . getReg ( ) == <NUM_LIT> && Is64BitMode && <STR_LIT> ) ; MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; return ; } bool IsPCRel = MCE . earlyResolveAddresses ( ) ? true : false ; unsigned BaseRegNo = - <NUM_LIT> ; if ( BaseReg != <NUM_LIT> && BaseReg != <STR_LIT> ) BaseRegNo = <ISA_LIT>_MC :: get<ISA_LIT>RegNum ( BaseReg ) ; if ( IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! Is64BitMode || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; return ; } if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; return ; } if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; return ; } MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , IsPCRel ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispForReloc ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } else if ( isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT>


<s> UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setShiftAmountType ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineSelectAndUseCommutative ( N , DCI , false ) ; case <STR_LIT> : return combineSelectAndUseCommutative ( N , DCI , true ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; } return SDValue


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; return


<s> if ( ! isa < ScalableVectorType > ( Src ) ) return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , Src


<s> static SDValue LowerF128_FPROUND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return Op ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F64 ) , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F32 ) , <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> unsigned Register = CLRMGPRDecoderTable [ RegNo ] ; if ( Register == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> bool isVSFRCRegClass ( const TargetRegisterClass * RC ) const { return RC -> getID (


<s> return ( __m128i ) __builtin_ia32_pmovqb512_mask ( ( __v8di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , (


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand (

MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>BranchTargets :: getAnalysisUsage ( AnalysisUsage & AU )


<s> static int vax_return_pops_args ( tree fundecl ATTRIBUTE_UNUSED , tree funtype ATTRIBUTE_UNUSED ,


<s> MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : { unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShiftReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ShiftTy = MRI . getType ( ShiftReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy . isVector ( ) ) return ; assert ( ! ShiftTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) != <NUM_LIT> || ShiftTy . getSizeInBits ( ) != <NUM_LIT> ) return ; auto * AmtMI = MRI . getVRegDef ( ShiftReg ) ; assert ( AmtMI && <STR_LIT> ) ; if ( AmtMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { MachineIRBuilder MIB ( I ) ; auto Trunc = MIB . buildInstr ( TargetOpcode :: COPY , { SrcTy } , { } ) . addReg


<s> if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; struct CleanupObject { SmallVector < MCParsedAsmOperand * , <NUM_LIT> > Operands ; ~ CleanupObject ( ) { for ( unsigned I = <NUM_LIT> , E = Operands . size ( ) ; I != E ; ++ I )


<s> HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasQuadwordAtomics = false ; HasDirectMove = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasStoreFusion = false ; HasAddiLoadFusion = false ; HasAddisLoadFusion = false ; IsISA2_07 = false ; IsISA3_0 = false ; IsISA3_1 = false ; UseLongCalls = false ; SecurePlt = false ; VectorsUseTwoUnits = false ; Use<ISA_LIT>PreRASchedStrategy = false ; Use<ISA_LIT>PostRASchedStrategy = false ; PairedVectorMemops = false ; PredictableSelectIsExpensive = false ; HasModernAIXAs = false ; IsAIX = false ; HasPOPCNTD = POPCNTD_Unavailable


<s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , AtomicOrdering

Ord , bool IsStore , bool IsLoad ) const {


<s> case CallingConv :: <ISA_LIT>_64_SysV : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: <ISA_LIT>_FastCall : return true ; default : return canGuaranteeTCO ( CC


<s> if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( ) .


<s> DT = & getAnalysis < MachineDominatorTree > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; isThumb1 = AFI -> isThumb1OnlyFunction ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; HasFarJump = false ; bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [


<s> int sh_attr_renesas_p ( tree td ) { if ( TARGET_HITACHI ) return <NUM_LIT> ; if ( td == <NUM_LIT> ) return <NUM_LIT> ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node


<s> const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT> ) { Amount = alignTo ( Amount , getStackAlignment ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , -


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RRegs [ getReg ( ) ]


<s> type = TREE_TYPE ( type ) ; decl_or_type = type ; } a = ix86_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (


<s> } else if ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; Immed = Immed >> <NUM_LIT> ; } else return None ; unsigned ShVal = <STR_LIT> ( <STR_LIT> , ShiftAmt ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Immed ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; Value = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Mask = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT>


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB ; if ( Subtarget . hasV5TEOps ( ) ) { MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; } else { MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; } if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT>


<s> UndefElts = APInt ( NumMaskElts , <NUM_LIT> ) ; RawMask . resize ( NumMaskElts , <NUM_LIT> ) ; if ( MaskEltSizeInBits == CstEltSizeInBits ) { assert ( NumCstElts == NumMaskElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; if ( isa < UndefValue > ( COp ) ) { UndefElts . setBit ( i ) ; RawMask [ i ] = <NUM_LIT> ; continue ; } auto * Elt = cast < ConstantInt > ( COp ) ; RawMask [ i ] = Elt -> getValue ( ) . getZExtValue ( ) ; } return true ; } APInt UndefBits ( CstSizeInBits , <NUM_LIT> ) ; APInt MaskBits ( CstSizeInBits , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumCstElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; unsigned BitOffset = i * CstEltSizeInBits ; if ( isa < UndefValue > ( COp ) ) { UndefBits . setBits ( BitOffset , BitOffset + CstEltSizeInBits ) ; continue ; } MaskBits . insertBits ( cast < ConstantInt > ( COp ) -> getValue ( ) , BitOffset ) ; } for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { unsigned BitOffset = i * MaskEltSizeInBits ; APInt EltUndef = UndefBits . extractBits ( MaskEltSizeInBits , BitOffset ) ; if ( EltUndef . isAllOnesValue ( ) ) { UndefElts . setBit ( i ) ; RawMask [ i ] = <NUM_LIT> ; continue ; } APInt EltBits = MaskBits . extractBits


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == <NUM_LIT> ? AtomicExpansionKind ::


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; if ( ! usesRegClass ( MO , & <STR_LIT> ) && ! usesRegClass ( MO , & <STR_LIT> ) && ! usesRegClass ( MO , & <STR_LIT> ) ) continue ; Defs . push_back ( MO . getReg ( ) ) ; } return Defs


<s> int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC

, <STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC , <STR_LIT> ) ;


<s> bool hasMacroFusion ( ) const { return


<s> static MachineInstr * canFoldIntoMOVCC ( unsigned Reg , const MachineRegisterInfo & MRI , const TargetInstrInfo * TII ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return <NUM_LIT> ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return <NUM_LIT> ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return <NUM_LIT> ; if ( ! MI -> isPredicable ( ) ) return <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return <NUM_LIT> ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) return <NUM_LIT> ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return <NUM_LIT> ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( TII , <NUM_LIT> , DontMoveAcrossStores ) ) return <NUM_LIT> ; return


<s> auto * DesiredClass = TRI -> getRegClass ( RegClassIDs [ NumRegs - <NUM_LIT> ] ) ; auto RegSequence = MIB . buildInstr ( TargetOpcode :: REG_SEQUENCE , { DesiredClass } , { } ) ; for ( unsigned I = <NUM_LIT> , E = Regs . size ( ) ; I < E ; ++ I ) { RegSequence . addUse ( Regs [ I


<s> return __builtin_ia32_vcvtqq2ph256_mask ( ( __v4di ) __A , _mm_setzero_ph ( ) , (


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , bool * Fast ) const { if ( Fast )


<s> } else { NewOpcode = <STR_LIT> ; Start &= <NUM_LIT> ; End &= <NUM_LIT> ; } MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpcode ) ) . add ( Dest ) . addReg ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand


<s> bool <ISA_LIT>AsmParser :: parseDirectiveLtorg ( SMLoc L ) { getTargetStreamer ( ) . emitCurrentConstantPool ( ) ; return false


<s> bool VisitNode ( MachineDomTreeNode * Node , unsigned TLSBaseAddrReg ) { MachineBasicBlock * BB = Node -> getBlock ( ) ; bool Changed = false ; for ( MachineBasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { switch ( I -> getOpcode ( ) ) { case


<s> return performFpToIntCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : { SDValue RV = performSelectCombine ( N , DCI ) ; if ( ! RV . getNode ( ) ) RV = performAcrossLaneMinMaxReductionCombine ( N , DAG , Subtarget ) ; return RV ; } case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr (


<s> strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop1MBB ) ; BB -> addSuccessor (


<s> bool selectBDAddr12Pair ( SDValue Addr , SDValue & Base , SDValue & Disp ) const { return selectBDAddr ( <STR_LIT> , Addr , Base ,


<s> bool <ISA_LIT>LongBranch :: mustRelaxABranch ( ) { for ( auto & Terminator : Terminators ) if ( mustRelaxBranch ( Terminator , Terminator . Address ) ) return true ; return false


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return DW_EH_PE_pcrel | ( Model == CodeModel :: Small || Model == CodeModel :: Medium ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8 ) ; if ( Model == CodeModel :: Small || Model == CodeModel :: Medium ) return


<s> if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return


<s> if ( ! LaneC || LaneC -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; } LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( )


<s> if ( IsRIPRel ) { SDValue Val = N . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) IsRIPRelTLS = true ; } CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) && ( ( M == CodeModel :: Large && ! IsRIPRelTLS ) || ( M == CodeModel :: Medium && ! IsRIPRel ) ) ) return true ; if ( IsRIPRel && AM . hasBaseOrIndexReg ( ) ) return true ; <ISA_LIT>ISelAddressMode Backup = AM ; int64_t Offset = <NUM_LIT> ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; Offset = G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Alignment = CP -> getAlign ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast <


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>32 ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasSwap ( false ) , HasBitCount ( false ) , HasFPIdx ( false ) , In<ISA_LIT>16Mode ( false ) , In<ISA_LIT>16HardFloat ( <ISA_LIT>16HardFloat ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , RM ( _RM ) , OverrideMode ( NoOverride ) , TM ( _TM ) { std :: string CPUName


<s> Op -> PSBHint . Data = Str . data ( ) ; Op -> PSBHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> static void darwin_rs6000_extra_signals ( void ) { struct sigaction sact ; stack_t sigstk ; sigstk . ss_sp = ( char * ) xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; sigemptyset ( & sact


<s> unsigned <ISA_LIT>AsmBackend :: getFixupKindContainereSizeInBytes ( unsigned Kind ) const { if ( Endian == <STR_LIT> ) return <NUM_LIT> ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case FK_Data_8 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) { if ( Cond [ i ] . isReg ( ) ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; else if ( Cond [ i ] . isImm ( ) ) MIB . addImm ( Cond [ i ] . getImm ( ) ) ; else assert ( true && <STR_LIT>


<s> const EDInstInfo * <ISA_LIT>DisassemblerBase :: getEDInfo ( ) const { return


<s> bool <ISA_LIT>MCCodeEmitter :: emitOpcodePrefix ( int MemOperand , const MCInst & MI , const MCSubtargetInfo & STI , raw_ostream & OS ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) emitByte ( <NUM_LIT> , OS ) ; if ( TSFlags & <STR_LIT> || MI . getFlags ( ) & <STR_LIT> ) emitByte ( <NUM_LIT> , OS ) ; if ( TSFlags & <STR_LIT> || MI . getFlags ( ) & <STR_LIT> ) emitByte ( <NUM_LIT> , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; } assert ( ( STI . hasFeature ( <STR_LIT> ) || ! ( TSFlags & <STR_LIT> ) ) && <STR_LIT> ) ; bool HasREX = STI . hasFeature ( <STR_LIT> ) ? emitREXPrefix ( MemOperand , MI , STI , OS ) : false ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; } switch ( TSFlags & <STR_LIT> ) { case


<s> assert ( Offset . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; SDValue Shift = DAG . getConstant ( Log2_32 ( BitWidth / <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue SplatShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ,


<s> if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer ,


<s> if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( ( * p ) -> mode ) ) first_of_size_p = false ; } if ( pool -> first == <NUM_LIT> ) pool -> highest_address = pool -> insn_address - ( UNITS_PER_WORD - <NUM_LIT> ) + <NUM_LIT> ; pool -> highest_address -= GET_MODE_SIZE ( mode ) ; if ( first_of_size_p ) pool -> highest_address -= GET_MODE_SIZE ( mode ) - <NUM_LIT> ; c = XNEW (


<s> void <ISA_LIT>TargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { getStreamer ( ) . setAttributeItems ( Attribute , IntValue ,


<s> const ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsS32 ( ) ) return


<s> if ( TM . getSubtargetImpl ( ) -> in<ISA_LIT>16Mode ( ) ) return llvm :: create<ISA_LIT>16ISelDag (


<s> return isImmediate < <NUM_LIT> , <NUM_LIT>


<s> void EmitInstruction ( uint64_t Val , unsigned Size


<s> return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_3DNOW ) { if ( readModRM ( insn ) ) return - <NUM_LIT> ; insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) )


<s> static __inline qword si_clgth ( qword a , qword b ) { return ( ( qword ) ( vec_cmpgt ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b


<s> case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; } return SDValue


<s> bool isImm1_16 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm


<s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res .


<s> return UNSPEC_COND_NE ; case EQ : return UNSPEC_COND_EQ ; case LT : return UNSPEC_COND_LT ; case GT : return UNSPEC_COND_GT ; case LE


<s> VT = <STR_LIT> ; } } else { if ( Len >= <NUM_LIT> && Alignment == <NUM_LIT> ) VT = <STR_LIT> ; else { VT = <STR_LIT> ; } } bool RV ; Register ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ; assert ( RV &&


<s> Op -> RegShiftedReg . SrcReg = SrcReg ; Op -> RegShiftedReg . ShiftReg = ShiftReg ; Op -> RegShiftedReg . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc


<s> assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr


<s> for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF


<s> arm_init_simd_builtin_scalar_types ( ) ; tree lane_check_fpr = build_function_type_list ( void_type_node , intSI_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_NEON_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , ARM_BUILTIN_NEON_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( neon_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & neon_builtin_data [ i ] ; arm_init_builtin ( fcode , d , <STR_LIT>


<s> XFormOpcode = RI . getMappedIdxOpcForImmOpc ( Opc ) ; if ( XFormOpcode == <STR_LIT> ) return false ; if ( ! instrHasImmForm ( XFormOpcode , isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , III , true ) ) return false ; if ( ! III . IsSummingOperands ) return false ; MachineOperand ImmOperand = MI . getOperand ( III . ImmOpNo ) ; MachineOperand RegOperand = MI . getOperand ( III . OpNoForForwarding ) ; if ( ! ImmOperand . isImm ( ) ) return false ; assert ( RegOperand . isReg ( ) && <STR_LIT> ) ; if ( ! RegOperand . isKill ( ) ) return


<s> inline vector float vec_sub ( vector float a1 , vector


<s> if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rm , Address , Decoder )


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getT2Imm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { int32_t Imm8 = MI . getOperand ( OpIdx ) . getImm ( ) ; bool isAdd = Imm8 >= <NUM_LIT> ; if ( Imm8 < <NUM_LIT> ) Imm8 = - Imm8 ; Imm8 /= <NUM_LIT> ; uint32_t Binary = Imm8 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; return


<s> return ( vector float ) __builtin_altivec_vrsqrtefp ( ( vector


<s> printThumbAddrModeImm5SOperand ( MI , Op , STI


<s> bool <ISA_LIT>TargetLowering :: needsFixedCatchObjects (


<s> bool setsStatusFlags = false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) { if ( MI . getOperand ( i ) . isReg ( ) && TRI -> getName ( MI . getOperand ( i ) . getReg ( ) ) ==


<s> bool IsFMA3Encoding = ( ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( TSFlags & <STR_LIT> ) == <STR_LIT> ) || ( ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( ( TSFlags & <STR_LIT> ) == <STR_LIT> || ( TSFlags & <STR_LIT> ) == <STR_LIT> ) ) ; bool IsFMA3Prefix = ( TSFlags & <STR_LIT> ) == <STR_LIT> ; if ( ! IsFMA3Opcode || ! IsFMA3Encoding || ! IsFMA3Prefix ) return nullptr ; verifyTables ( ) ; ArrayRef < <ISA_LIT>InstrFMA3Group > Table ; if ( TSFlags & <STR_LIT> ) Table = makeArrayRef ( RoundGroups ) ; else if ( TSFlags & <STR_LIT> ) Table = makeArrayRef ( BroadcastGroups ) ; else Table = makeArrayRef


<s> static SDValue PerformLOADCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned AddressSpace = Ld -> getAddressSpace ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment , & Fast ) && ! Fast ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT>


<s> SmallVectorImpl < MachineInstr * > & getUseDefs (


<s> unsigned NextConversion = N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( NextConversion != FirstConversion ) return SDValue ( ) ; if ( N -> getOperand ( i ) != FirstInput ) IsSplat = false ; } if ( IsSplat ) return SDValue ( ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue In = N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( Is32Bit ) { if ( In . isUndef ( ) ) Ops . push_back ( DAG . getUNDEF ( SrcVT ) ) ; else { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , In . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Ops . push_back ( Trunc ) ; } } else Ops . push_back ( In . isUndef ( ) ? DAG . getUNDEF ( SrcVT ) : In . getOperand ( <NUM_LIT> ) ) ; } unsigned Opcode ; if ( FirstConversion == <STR_LIT> || FirstConversion == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; EVT NewVT = TargetVT == <STR_LIT>


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty


<s> EVT IntEltVT = SplatVT . getVectorElementType ( ) ; EVT BoolVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; EVT PredVT = SplatVT . changeVectorElementType ( BoolVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , SplatVT , DAG . getNode ( <STR_LIT> , DL , IntEltVT , InElem ) ) ; SDValue SplatIdx = DAG . getNode ( <STR_LIT> , DL , SplatVT , DAG . getZExtOrTrunc ( InIdx , DL , IntEltVT ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue Seq = DAG . getNode ( <STR_LIT> , DL , SplatVT , Zero , One ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , PredVT , SplatIdx ,

Seq , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> bool has<ISA_LIT>1 ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> FOREACH_FUNCTION_ARGS ( m_fntype , type , iter ) { if ( type == void_type_node || i >= m_nargs ) break ; if ( i >= m_base_arg && TREE_CODE ( type ) == ENUMERAL_TYPE && ! require_immediate_enum ( i - m_base_arg , type ) ) return false ; i +=


<s> int in_toc_section ( ) \ { \ return in_section == in_toc


<s> unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C -> getAPIntValue ( ) ; Ops . push_back ( DAG . getConstant ( CInt . trunc ( EltSize ) , TruncVT ) ) ; } return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , <STR_LIT> ( TruncVT , NumElts ) , Ops . data (


<s> case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) { AsmPieces . clear ( ) ; StringRef ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { InlineAsm :: ConstraintInfoVector Constraints = IA -> ParseConstraints ( ) ; if ( Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { if ( matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) return IntrinsicLowering


<s> static rtx aapcs_libcall_value ( machine_mode mode ) { if ( BYTES_BIG_ENDIAN && ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) mode = SImode ; return aapcs_allocate_return_reg ( mode , NULL_TREE , NULL_TREE


<s> } return SDValue ( ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( VecVT . is256BitVector ( ) || VecVT . is512BitVector ( ) ) { Vec = extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG .


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCOPY_FW ( MachineInstr * MI ,


<s> if ( ! NumVGScaledBytes ) return MCCFIInstruction :: createOffset ( nullptr , DwarfReg , NumBytes ) ; std :: string CommentBuffer ; llvm :: raw_string_ostream Comment ( CommentBuffer ) ; Comment << printReg ( Reg , & TRI ) << <STR_LIT> ; SmallString < <NUM_LIT> > OffsetExpr ; appendVGScaledOffsetExpr ( OffsetExpr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true ) , Comment ) ; SmallString < <NUM_LIT> > CfaExpr ; CfaExpr . push_back ( dwarf :: DW_CFA_expression ) ; uint8_t buffer [


<s> Front . pop_back ( ) ; for ( MachineOperand & MO : MI -> operands ( ) ) { if ( ( ! MO . isReg ( ) ) || ( ! MO . isUse ( ) ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( Reg ) ) continue ; MachineOperand * Op = MI -> findRegisterDefOperand ( Reg ) ; if ( ! Op ) continue ; MachineInstr * Def = Op -> getParent ( ) ; if ( DeadInstr . find ( Def ) != DeadInstr . end ( ) ) continue ; bool IsDead = true ; for ( MachineOperand & MODef : Def -> operands ( ) ) { if ( ( ! MODef . isReg ( ) ) || ( ! MODef . isDef ( ) ) ) continue ; unsigned DefReg = MODef . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( DefReg ) ) { IsDead = false ; break ; } for ( MachineInstr & Use : MRI -> use_instructions ( Reg ) ) { if ( & Use == Def ) continue ; if ( DeadInstr . find ( & Use ) == DeadInstr . end (


<s> IntrinsicInst * IntrI = dyn_cast < IntrinsicInst > ( I ) ; if ( ! IntrI ) return false ; switch ( IntrI -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : return optimizeVectorMul ( IntrI )


<s> assert ( ( TagStores . empty ( ) || TagStores . back ( ) . Offset + TagStores . back

( ) . Size == I . Offset ) && <STR_LIT> ) ;


<s> assert ( Flags . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; for ( SDNode :: use_iterator UI = Flags -> use_begin ( ) , UE = Flags -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User


<s> Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results ,


<s> bool isRegIdx ( ) const { return Kind ==


<s> assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned Lo = RegInfo . getSubReg ( Src , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg (


<s> Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) { GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> return ( __m256 ) __builtin_ia32_sqrtps256_mask ( ( __v8sf ) __A ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> )


<s> rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( d -> vec_flags == VEC_SVE_DATA && elt >= <NUM_LIT> *

GET_MODE_UNIT_SIZE ( vmode ) ) return false ;


<s> if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass


, __artificial__ ) ) _mm256_setzero_ps ( void ) {


<s> bool explicit_type_suffix_p ( unsigned int i )


<s> int Value = Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( Update -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Update -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; Update -> eraseFromParent ( )


<s> if ( TARGET_ELF && tls_referenced_p ( x ) ) return false ; if ( CONST_DOUBLE_P ( x ) ) return easy_fp_constant ( x , mode ) ; if ( GET_CODE ( x ) == CONST_VECTOR ) return easy_vector_constant ( x ,


<s> BasicBlock * CurBB = IPI -> first -> getParent ( ) ; if ( NewBB == CurBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; appendAndTransferDominatedUses ( NewPt , User , OpNo , IPI , InsertPts ) ; return true ; } BasicBlock * CommonDominator = DT . findNearestCommonDominator ( NewBB , CurBB ) ; if ( ! CommonDominator ) continue ; if ( CommonDominator != NewBB ) { assert ( CommonDominator != CurBB && <STR_LIT> ) ; NewPt = CommonDominator -> getTerminator ( ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << '\n' ) ; LLVM_DEBUG ( NewPt -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( )


<s> bool legitimate_indexed_address_p ( rtx x , int strict ) { rtx op0 , op1 ; if ( GET_CODE ( x ) != PLUS ) return false ; op0 = XEXP ( x ,


<s> return ( uint16x8_t ) __builtin_neon_vaddluv8qi ( ( int8x8_t ) __a , (


<s> void addGPRMM16AsmRegMovePOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getGPRMM16Reg


<s> if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; for ( i = ( b & <NUM_LIT> ) ; i > <NUM_LIT> ; -- i ) a >>= <NUM_LIT> ; return


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> static void ix86_dwarf_handle_frame_unspec ( const char * label , rtx pattern , int index ) { rtx unspec = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; switch ( index ) { case UNSPEC_REG_SAVE : dwarf2out_reg_save_reg ( label , XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) , SET_DEST ( pattern ) ) ; break ; case UNSPEC_DEF_CFA : dwarf2out_def_cfa ( label , REGNO ( SET_DEST ( pattern ) ) , INTVAL ( XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; default : gcc_unreachable (


<s> const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; return StackSizeInBytes >= StackProbeSize


<s> } if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) return GOT_None ; const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const MCSymbol & S = Ref -> getSymbol ( ) ; if ( S . getName ( ) != <STR_LIT> ) return GOT_None ; if ( RHS && RHS -> getKind ( ) == MCExpr :: SymbolRef ) return GOT_SymDiff ; return


<s> return new <ISA_LIT>ELFObjectWriter ( true , OSType , ELF :: EM_<ISA_LIT>_64 ,


<s> unsigned PO = Offset + Size ; unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ; if ( ! LA ) return


<s> static int sh_mode_after ( int entity ATTRIBUTE_UNUSED , int mode , rtx_insn * insn ) { if ( TARGET_HITACHI && recog_memoized ( insn ) >= <NUM_LIT> && get_attr_fp_set ( insn ) != FP_SET_NONE ) return ( int ) get_attr_fp_set ( insn ) ; else return mode


<s> } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic !=


<s> SDValue AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V )


<s> unsigned RegPair = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeMovePRegPair ( Inst , RegPair , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; unsigned RegRs ; if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> has<ISA_LIT>32r6 ( ) ) RegRs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; else RegRs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeGPRMM16MovePRegisterClass ( Inst , RegRs , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; unsigned RegRt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeGPRMM16MovePRegisterClass ( Inst , RegRt , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler


<s> return MemOpKey ( PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) ,

PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) ) ;


<s> if ( RemainingSize != <NUM_LIT> ) Changed |= padInstructionViaRelaxation ( RF , Emitter , RemainingSize ) ; if ( RemainingSize != <NUM_LIT> ) Changed |=

padInstructionViaPrefix ( RF , Emitter , RemainingSize ) ;


<s> Cher128FailHardPass ( <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID


<s> for ( SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) , TE = Terminators . end ( ) ; TI != TE ; ++ TI ) if ( mustRelaxBranch ( * TI


<s> return create<ISA_LIT>WinCOFFObjectWriter ( false


<s> tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( TARGET_SILVERMONT || TARGET_INTEL ) if ( stmt_info && stmt_info ->


<s> return ( __m256i ) __builtin_ia32_gather3siv4di ( ( __v4di ) __v1_old , __addr , (


<s> if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) return


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { if ( IsPICCall || ! GlobalOrExternal ) { unsigned T9Reg = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; } else Ops . push_back ( Callee ) ; <ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee


<s> assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! IdxC ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; MVT ExtEltVT = ( NumElts <= <NUM_LIT> ) ? <STR_LIT> ( <NUM_LIT> / NumElts ) : <STR_LIT> ; MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = IdxC -> getZExtValue ( ) ; if ( IdxVal == <NUM_LIT> )


<s> return <NUM_LIT> ; return gen_rtx_REG ( Pmode ,


<s> if ( insn . mode == MODE_64BIT ) baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; else if ( insn . mode == MODE_32BIT ) baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; else { assert ( insn . mode == MODE_16BIT ) ; baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; } MCOperand baseReg = MCOperand :: CreateReg ( baseRegNo ) ; mcInst . addOperand ( baseReg ) ; MCOperand


<s> if ( ! N -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) != <STR_LIT> ) return


<s> return __builtin_mve_vrndpq_m_fv8hf ( __arm_vuninitializedq_f16 ( )


<s> if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = dyn_cast_or_null < const MCSectionELF > ( Sec ) ; if ( SecELF && SecELF -> getSectionName ( ) == <STR_LIT> ) Value = ByteSwap_32 ( unsigned


<s> assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Mld -> getSrc0 ( ) ) ; if ( Mld -> getSrc0 ( ) . getOpcode ( ) != <STR_LIT> ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } SDValue WideLd = DAG . getMaskedLoad ( WideVecVT , dl , Mld -> getChain ( ) , Mld -> getBasePtr ( ) , NewMask , WideSrc0 , Mld -> getMemoryVT ( ) , Mld -> getMemOperand ( ) , <STR_LIT> ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl ,


<s> int <ISA_LIT>FrameLowering :: resolveFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg , bool PreferFP , bool ForSimm ) const { const auto & MFI = MF . getFrameInfo ( ) ; int ObjectOffset = MFI . getObjectOffset ( FI ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed , FrameReg , PreferFP ,


<s> return ( uint16x4_t ) __builtin_neon_vdup_lanev4hi ( ( int16x4_t


<s> return DAG . getTargetJumpTable ( N -> getIndex ( ) ,


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <=


<s> SmallVector < int , <NUM_LIT> > VPShuf ; SmallVector < int , <NUM_LIT> > VPAlign [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > VPAlign2 ; SmallVector < int , <NUM_LIT> > VPAlign3 ; SmallVector < int , <NUM_LIT> > GroupSize ; Value * Vec [ <NUM_LIT> ] , * TempVector [ <NUM_LIT> ] ; MVT VT = <STR_LIT> ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; createShuffleStride ( VT , <NUM_LIT> , VPShuf ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> - i ] , VPAlign [ i ] , false ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2 , true , true ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ; concatSubVector ( Vec , InVec , VecElems , Builder ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , VPShuf ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) TempVector [ i ] = Builder . CreateShuffleVector ( Vec [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , Vec [ i ] , VPAlign [ <NUM_LIT> ] ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( TempVector [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , TempVector [ i ] , VPAlign [ <NUM_LIT> ] ) ; Value * TempVec = Builder . CreateShuffleVector ( Vec [ <NUM_LIT> ] , VPAlign3


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return combineAddOrSubToADCOrSBB ( N


<s> return ( unsigned char ) __builtin_ia32_ktestchi ( __A


<s> auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) || ! Subtarget -> hasVFP2 ( ) ) return false ; auto & Args = F . getArgumentList ( ) ; for ( auto & Arg : Args ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos


<s> if ( ! Subtarget -> hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDVTList VTs = DAG . getVTList ( N -> getMask ( ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ; SDValue NewScatter = DAG . getMaskedScatter ( VTs , VT , dl ,


<s> return <STR_LIT> ( Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( <ISA_LIT>Operand * Err = ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return Err ; return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier


<s> if ( REG_P ( SET_SRC ( set ) ) && ! HARD_REGISTER_P ( SET_SRC ( set ) ) && push_operand ( SET_DEST ( set ) , mode ) ) return set ; df_ref ref ; FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return NULL ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return NULL ; return set


<s> ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t )


<s> static bool mips_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) == <NUM_LIT> && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to )


<s> OperandMatchResultTy parseBDLAddr64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseAddress ( Operands , <STR_LIT> , ADDR64Reg ,


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ( Subtarget . isABI_FPXX ( ) && ! Subtarget . hasMTHC1 ( ) ) || ( FP64 && ! Subtarget . useOddSPReg ( ) ) ) { const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & TRI = * static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = FP64 ? & <STR_LIT> : & <STR_LIT> ; const TargetRegisterClass * RC2 = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC ) ; TII . storeRegToStack ( MBB , I , SrcReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & TRI , N * <NUM_LIT> ) ; return true ; } return


<s> bool hasCRC ( ) const { return HasCRC


<s> RegTOpIdx = <NUM_LIT> ; RegNOpIdx = <NUM_LIT> ; LnOpIdx = <NUM_LIT> ; } Binary |= ( IsThumb ? <STR_LIT> : II -> getPredicate ( & MI ) ) << <STR_LIT> ; unsigned RegT = MI . getOperand ( RegTOpIdx ) . getReg ( ) ; RegT = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , RegNOpIdx ) ; unsigned LaneShift ; if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else LaneShift = <NUM_LIT> ; unsigned Lane = MI . getOperand ( LnOpIdx ) . getImm ( ) << LaneShift ; unsigned Opc1 = Lane >> <NUM_LIT> ; unsigned Opc2 = Lane & <NUM_LIT> ; assert ( ( Opc1 & <NUM_LIT> ) == <NUM_LIT>


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : case TargetOpcode :: G_MUL : return getSameOperandsMapping ( MI , false ) ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumOperands = MI . getNumOperands ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , false ) , <NUM_LIT> ) ; return getInstructionMapping ( DefaultMappingID , <NUM_LIT> , Mapping , NumOperands ) ; } default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_FPTOSI : { auto & Op0 = MI . getOperand ( <NUM_LIT> ) ; auto & Op1 = MI . getOperand ( <NUM_LIT> ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool FirstArgIsFP = Opc == TargetOpcode ::


<s> unsigned GPReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; EVT Ty = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . DAG . getMachineFunction ( ) , CLI . CallConv ) ; assert ( Mask && <STR_LIT>


<s> for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i ) if ( <NUM_LIT> <= Mask [ i ] ) return false ; return true


<s> return ( ( struct machine_function * ) ggc_alloc_cleared

( sizeof ( struct machine_function ) ) ) ;