<s> bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; if ( ( Count % MinNopLen ) != <NUM_LIT> ) return false ; uint64_t Nop32Count =


<s> const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB ( ) ) return true ; unsigned OldCond = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldCond == ThisCond [ <NUM_LIT> ] . getImm ( ) ) continue ; } return false


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set (


<s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - <NUM_LIT> ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) +


<s> static bool riscv_memmodel_needs_release_fence ( enum memmodel model ) { switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : return true ; case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : case MEMMODEL_RELAXED


<s> MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes (


<s> SDValue <ISA_LIT>TargetLowering :: lowerFPVECREDUCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT VecEltVT = Op . getSimpleValueType ( ) ; unsigned RVVOpcode ; SDValue VectorVal , ScalarVal ; std :: tie ( RVVOpcode , VectorVal , ScalarVal ) = getRVVFPReductionOpAndOperands ( Op , DAG , VecEltVT ) ; MVT VecVT = VectorVal . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ScalarSplat = lowerScalarSplat ( ScalarVal , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , DAG

. getUNDEF ( M1VT ) , VectorVal , ScalarSplat , Mask , VL ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; } return false


<s> setAttributeItems ( Attribute , IntValue , StringValue , true


<s> int getVLIndex ( ) const { return static_cast < int8_t > ( VLIndex )


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true


<s> unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg

( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ;


<s> riscv_set_frame_expr ( riscv_frame_set ( mem , reg


<s> StringRef <ISA_LIT>MCExpr :: getVariantKindName ( VariantKind Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI


<s> void setFormalArgInfo ( unsigned Size , bool HasByval ) { IncomingArgSize = Size


<s> SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) ,

static_cast < unsigned > ( IndexLMUL ) ) ;


<s> if ( ! getContext ( ) . getAsmInfo ( ) -> isCheriPurecapABI


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; } else if ( isInt < <NUM_LIT> > ( Val ) ) { unsigned Opc = <STR_LIT> ; bool isSub = Val < <NUM_LIT> ; if ( isSub ) { Val = - Val


<s> if ( lower<ISA_LIT>VMachineInstrToMCInst ( MI , OutMI ) ) return false ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; } switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ; AP . emitNops (


<s> Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ; if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasSameVTYPE ( Require ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ; if ( ! DefMI || ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) ; MBBI -> eraseFromParent


<s> <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask ,


<s> const <STR_LIT> * II = <STR_LIT> ( IntNo ) ; if ( ! II ) return SDValue ( ) ; return Op . getOperand ( II -> VLOperand +


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc


<s> } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT>


<s> MCSymbol * TmpLabel = Ctx . createNamedTempSymbol ( <STR_LIT> ) ; Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel ,

Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget (


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * CI ) const { unsigned Size = CI -> getCompareOperand ( ) -> getType ( )


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > array_lengthof ( FPR64DecoderTable )


<s> void <ISA_LIT>InstPrinter :: printS20ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O <<


<s> case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( )


<s> SDLoc DL ( Op ) ; MVT VecVT = Op . getSimpleValueType ( ) ; assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Res = splatPartsI64WithVL ( DL , ContainerVT , Lo , Hi


<s> const <ISA_LIT>TargetMachine & RTM = static_cast <

const <ISA_LIT>TargetMachine & > ( TM ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { Parser . addAliasForDirective ( <STR_LIT>


<s> const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ; MCA . setELFHeaderEFlags


<s> static void riscv_set_handled_components ( sbitmap components ) { for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( bitmap_bit_p ( components , regno ) ) cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( bitmap_bit_p ( components , regno ) ) cfun -> machine -> reg_is_wrapped_separately


<s> { HandleSDNode Handle ( Upper ) ; SelectCode ( Upper . getNode ( ) ) ; Upper = Handle . getValue ( ) ; } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ; ReplaceUses ( Node , Or . getNode ( ) ) ; CurDAG -> RemoveDeadNode ( Node ) ; SelectCode ( Or . getNode ( )


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > (


<s> memset ( & args , <NUM_LIT> , sizeof args ) ; function_arg_info arg ( const_cast < tree > ( type ) , true ) ; return riscv_pass_by_reference ( cum , arg


<s> unsigned Imm = MI . getOperand ( OpIdx ) . getImm ( ) ; <ISA_LIT>VType :: printVType ( Imm , OS ) ; } else if ( <STR_LIT> ( TSFlags ) ) { unsigned NumOperands = MI . getNumExplicitOperands ( ) ; bool HasPolicy = <STR_LIT> ( TSFlags ) ; if ( OpIdx != NumOperands - HasPolicy - <NUM_LIT> ) return std :: string ( ) ; unsigned Log2SEW = MI . getOperand ( OpIdx ) . getImm ( ) ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW :


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E , bool IsRV64 ) { auto Op = make_unique < <ISA_LIT>Operand > ( Immediate


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>64Target


<s> unsigned XLen = IsRV64 ? <NUM_LIT> : <NUM_LIT> ; std :: vector < std :: string > FeatureVector ; for ( auto Feature : <ISA_LIT>FeatureKV ) { if ( FeatureBits [ Feature . Value ] && llvm :: <STR_LIT> ( Feature . Key ) ) FeatureVector . push_back ( std :: string ( <STR_LIT> ) + Feature . Key ) ; } return llvm :: <STR_LIT> (


<s> void setVTYPE ( <STR_LIT> L , unsigned S , bool TA , bool MA ) { assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ; VLMul = L


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) preAssignMask ( Outs , FirstMaskArgument , CCInfo ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [


<s> SDValue callFunction ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , const char * fnName , SDValue Dst , SDValue Src , SDValue Size ) { auto & Ctx = * DAG . getContext ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; TargetLowering :: ArgListTy Args ; auto pushArg = [ & ] ( SDValue & Op ) { TargetLowering :: ArgListEntry Entry ; Entry . Node = Op ; Entry . Ty = Op . getValueType ( ) . getTypeForEVT ( Ctx ) ; Args . push_back ( Entry


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc StartLoc ,


<s> addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( )


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( )


<s> unsigned Lmul = Imm & <NUM_LIT> ; Sew = <NUM_LIT> << ( Sew + <NUM_LIT> ) ; Lmul = <NUM_LIT> << Lmul ; Ediv = <NUM_LIT> << Ediv ; O << <STR_LIT>


<s> getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( LoadOpcode


<s> return new <ISA_LIT>CleanupVSETVLI (


<s> if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++


<s> void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: Text ; Item -> StringValue = std :: string ( Value ) ; return ; } Contents . push_back ( { AttributeType :: Text , Attribute , <NUM_LIT> , std ::


<s> if ( ! set -> insn ( ) -> is_phi ( ) ) return nullptr ; hash_set < set_info * > sets = get_all_sets ( set , true , false , true ) ; insn_info * first_insn = ( * sets . begin ( ) ) -> insn ( ) ; if ( first_insn -> is_artificial ( ) ) return


<s> for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { vector_block_infos [ bb -> index ( ) ] . local_dem = vector_insn_info ( ) ; vector_block_infos [ bb -> index ( ) ] . reaching_out = vector_insn_info ( ) ; for ( insn_info * insn : bb -> real_insns ( ) ) vector_insn_infos [ insn -> uid ( ) ] . parse_insn ( insn ) ; vector_block_infos [ bb -> index ( ) ] . probability


<s> std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS

, Options . MCOptions . getABIName ( ) , * this ) ;


<s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset (


<s> bool <ISA_LIT>ExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT>


<s> if ( inner_mode == E_BImode ) mclass = MODE_VECTOR_BOOL ; else if ( FLOAT_MODE_P ( inner_mode ) ) mclass = MODE_VECTOR_FLOAT ; else mclass = MODE_VECTOR_INT ; machine_mode mode ; FOR_EACH_MODE_IN_CLASS ( mode , mclass ) if ( inner_mode == GET_MODE_INNER ( mode ) && known_eq ( nunits , GET_MODE_NUNITS ( mode ) ) && riscv_v_ext_vector_mode_p ( mode ) ) return mode ; return opt_machine_mode (


<s> <ISA_LIT>RI5CYIR ( ) : FunctionPass ( ID


<s> EVT getSetCCResultType ( const DataLayout & , LLVMContext & , EVT


<s> cost = <NUM_LIT> + riscv_build_integer ( codes , loval , VOIDmode ) ; if ( loval != hival ) cost += riscv_build_integer ( codes , hival , VOIDmode ) ; return cost


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F )


<s> MachineFunction * MF = MBB . getParent ( ) ; unsigned SecondOpcode ; unsigned FlagsHi ; if ( MF -> getTarget ( ) . isPositionIndependent ( ) ) { const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; FlagsHi = <STR_LIT> ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op


<s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ; SDValue Shl = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { uint64_t VC1 = N -> getConstantOperandVal ( <NUM_LIT>


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionRVC


<s> static bool isVariableSDivUDivURem ( SDValue Val ) { switch ( Val . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT>


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO : case VK_<ISA_LIT>_PCREL_HI


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) )


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! ( hasFP ( MF ) && hasRVVFrameObject (


<s> X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue NegX = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero , X


<s> rtx i32vl = NULL_RTX ; if ( CONST_INT_P ( avl ) ) { unsigned elt_size = GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; unsigned min_size = get_unknown_min_value ( mode ) ; unsigned vlen_max = RVV_65536 ; unsigned vlmax_max = compute_vlmax ( vlen_max , elt_size , min_size ) ; unsigned vlen_min = TARGET_MIN_VLEN ; unsigned vlmax_min = compute_vlmax ( vlen_min , elt_size , min_size ) ; unsigned HOST_WIDE_INT avl_int = INTVAL ( avl ) ; if ( avl_int <= vlmax_min ) i32vl = gen_int_mode ( <NUM_LIT> * avl_int , Pmode ) ; else if ( avl_int >= <NUM_LIT> * vlmax_max ) { i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( demote_mode , i32vl , RVV_VLMAX ) ) ; } else { } } if ( ! i32vl ) { rtx i64vl = gen_reg_rtx


<s> static SDValue getAllOnesMask ( MVT VecVT , SDValue VL ,


<s> case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case


<s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false


<s> Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement (


<s> case TargetTransformInfo :: RGK_Scalar : return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST ->

getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ;


<s> bool demand_p ( enum demand_type type ) const { return m_demands [ type


<s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL ) type = TREE_TYPE ( TYPE_NAME ( type ) ) ; if ( tree attr = lookup_vector_type_attribute ( type ) ) if ( tree id = TREE_VALUE ( chain_index ( <NUM_LIT> , TREE_VALUE ( attr ) ) ) ) return IDENTIFIER_POINTER ( id ) ; return NULL


<s> void add_avl_type_operand ( avl_type type ) { add_input_operand ( gen_int_mode ( type , Pmode )


<s> MVT XLenVT = Subtarget . getXLenVT ( ) ; SDVTList ResultVTs = DAG . getVTList ( XLenVT , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , ResultVTs ,


<s> MCTargetStreamer & TS = * getParser ( ) . getStreamer (


<s> SO = <NUM_LIT> << <NUM_LIT> ; SR = <NUM_LIT> << <NUM_LIT> ; SW = <NUM_LIT> << <NUM_LIT> ; } unsigned pred = PI | PO | PR | PW ; unsigned succ = SI | SO | SR | SW ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( pred , DL , Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) , DAG . getConstant ( succ , DL , Subtarget .

isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> MAB . setForceRelocs ( ) ; } } Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , NameLoc , isRV64 ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands , Name ) ) return true ; unsigned OperandIdx = <NUM_LIT> ; while ( getLexer ( ) . is ( AsmToken


<s> return pred == PRED_TYPE_m || pred == PRED_TYPE_tum || pred ==

PRED_TYPE_tumu || pred == PRED_TYPE_mu ;


<s> int arg_offset = <NUM_LIT> ; add_mem_operand ( mode , use_real_mask_p ( pred ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( use_real_mask_p ( pred ) ) add_input_operand


<s> riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ; return arg . stack_p ? arg


<s> static bool riscv_interrupt_type_p ( tree type ) { return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES (


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC ,

const TargetRegisterInfo * TRI ) const {


<s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; unsigned Reg = Op . getReg ( ) ; bool IsRegFPR32 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR32C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR32 && Kind == MCK_FPR64 ) || ( IsRegFPR32C && Kind == MCK_FPR64C ) ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; return Match_Success ; } return Match_InvalidOperand


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit


<s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) ,


<s> const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ; llvm_unreachable ( <STR_LIT>


<s> assert ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT>


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI , OpNum ,


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode


<s> inline void function_expander :: add_input_operand ( machine_mode mode , rtx op ) { create_input_operand ( & m_ops [ opno ++ ]


<s> bool <ISA_LIT>TargetLowering :: isSExtCheaperThanZExt ( EVT SrcVT , EVT DstVT ) const { return Subtarget . is64Bit ( ) && SrcVT ==


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; auto * Load = cast < LoadSDNode > ( Op ) ; assert ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Load -> getMemoryVT ( ) , * Load -> getMemOperand ( ) ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Load -> getChain ( ) }


<s> Type * ScalarType = DataType -> getScalarType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( ScalarType ) ) return false ; MaybeAlign MA = cast < ConstantInt > ( AlignOp


<s> return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent : return PtrIsCap ? <STR_LIT>


<s> SDValue StepVec = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; uint64_t StepValImm = Op . getConstantOperandVal ( <NUM_LIT> ) ; if ( StepValImm != <NUM_LIT> ) { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == XLenVT && <STR_LIT> ) ; if ( isPowerOf2_64 ( StepValImm ) ) { SDValue StepVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Log2_64 ( StepValImm ) , DL , XLenVT ) ) ; StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ; } else


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return <STR_LIT> ; return getRegClassIDForLMUL ( getLMUL (


<s> if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; return getAddr ( N ,


<s> assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI , OpNum ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SpecialCapReg


<s> case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( Result ) { default : break ; case Match_InvalidImmXLenLI : if ( isRV64 ( ) ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } return generateImmOutOfRangeError ( Operands , ErrorInfo , std :: numeric_limits < int32_t > :: min ( ) , std :: numeric_limits < uint32_t > :: max ( ) ) ; case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImmLog2XLenNonZero : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm6NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , (


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( ) ; Register SPReg = getSPReg ( ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount )


<s> if ( reg_class_subset_p ( GR_REGS , rclass ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST


<s> if ( code >= vec_safe_length ( registered_functions ) )


<s> Target & llvm :: getThe<ISA_LIT>32Target ( ) { static Target The<ISA_LIT>32Target ; return The<ISA_LIT>32Target


<s> else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT

( ArgVT ) . getEVTString ( ) << '\n' ) ;


<s> if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ; return decodeSImmOperand < N > ( Inst , Imm , Address


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok (


<s> fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_mcsr_check ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_emit_attribute_p ) riscv_emit_attribute ( )


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub


<s> if ( NoAliases || ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot


== MODE_FLOAT && GET_MODE_CLASS ( mode2 ) == MODE_FLOAT ) ) ;


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const


<s> <STR_LIT> getExtendForAtomicOps ( ) const override { return


<s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) ,


<s> static bool riscv_slow_unaligned_access ( machine_mode , unsigned int ) { return


<s> addPass ( new IRTranslator ( getOptLevel ( )


<s> void <ISA_LIT>InstPrinter :: printUimm32contig1endOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O <<


<s> unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI )


<s> IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { MGN -> getChain ( ) , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( MGN -> getBasePtr ( ) ) ; Ops . push_back ( Index ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , MGN -> getMemoryVT ( )


<s> static void doMaskedAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - <NUM_LIT> ) ; break ; } insertMaskedMerge ( TII , DL , LoopMBB , ScratchReg , DestReg , ScratchReg , MaskReg , ScratchReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> . contains ( SrcReg ) ) ) { Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else llvm_unreachable ( <STR_LIT>


<s> if ( instance . any_type_float_p ( ) ) return flags | CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS ; return flags


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL


<s> MCRegister SP = MRI . getDwarfRegNum ( SPReg , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; addImplySP ( Inst , Address , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N >


<s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) &&

DefInfo . hasSameVTYPE ( CurInfo ) ) return false ;


<s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode )


<s> rtx expand_builtin ( unsigned int code , tree exp , rtx target ) { registered_function & rfn = * ( *


<s> return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm21Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidFRMArg


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream &


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( )


<s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) ; } else


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return


<s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo = MatchRegisterName


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses


<s> return g_switch_value && IN_RANGE ( size ,


<s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind -


<s> low = riscv_const_insns ( riscv_subword ( x , false ) ) ; high = riscv_const_insns ( riscv_subword ( x , true ) ) ; gcc_assert ( low > <NUM_LIT> && high > <NUM_LIT> ) ; return low + high


<s> SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; ReplaceNode ( Node , Store


<s> EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return


<s> emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand


<s> static bool riscv_legitimate_constant_p ( enum machine_mode


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT ,


<s> unsigned Tmp2 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; return std :: min ( Tmp , Tmp2 ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; } break ; } case <STR_LIT> : if ( Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return <NUM_LIT> ; return Subtarget . getXLen ( ) - Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) + <NUM_LIT> ; } return <NUM_LIT>


<s> DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , A , static_cast < MCFixupKind > ( Add ) , Loc ) ) ; DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , B , static_cast < MCFixupKind > ( Sub ) , Loc ) ) ; DF -> getContents ( ) . resize ( DF -> getContents


<s> return false ; case <STR_LIT> : emitLoadTLSIEAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadTLSGDAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc


<s> InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store )


<s> auto CannotInsertCall = [ ] ( outliner :: Candidate & C ) { const TargetRegisterInfo * TRI = C . getMF ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; C . initLRU ( * TRI ) ; LiveRegUnits LRU = C . LRU ; return ! LRU . available ( <STR_LIT> ) ; } ; llvm :: erase_if ( RepeatedSequenceLocs , CannotInsertCall ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction


<s> return parseRegister ( Operands , 'p' , PCReg ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > createVType ( APInt Sew , APInt Lmul , bool Fractional , bool TailAgnostic , bool MaskedoffAgnostic , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VType ) ; Sew . ashrInPlace ( <NUM_LIT> ) ; unsigned SewLog2 = Sew . logBase2 ( ) ; unsigned LmulLog2 = Lmul . logBase2 ( ) ; Op -> VType . Sew = static_cast < VSEW > ( SewLog2 ) ; if ( Fractional ) { unsigned Flmul = <NUM_LIT> - LmulLog2 ; Op -> VType . Lmul = static_cast < VLMUL > ( Flmul ) ; Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | Flmul ; } else { Op -> VType . Lmul = static_cast < VLMUL > ( LmulLog2 ) ; Op -> VType . Encoding = ( SewLog2


<s> if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( *


<s> Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF (


<s> if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind ::


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; } TargetABI = <STR_LIT> ( TT ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore |


<s> RegNo = MatchRegisterName ( Name ) ; assert ( ! ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) ; assert ( ! ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) ; static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <STR_LIT> ; return RegNo ==


<s> TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( *


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> bool isImmXLen ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT>


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtP ( ) && Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Subtarget . is64Bit ( ) ? Legal : Custom ) ; if ( Subtarget . hasStdExtA ( ) ) { setMaxAtomicSizeInBitsSupported ( Subtarget . getXLen ( ) ) ; setMinCmpXchgSizeInBits ( <NUM_LIT> ) ; } else { setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; unsigned FunctionAlignment = Subtarget . hasStdExtC ( ) ? <NUM_LIT> : <NUM_LIT> ; setMinFunctionAlignment (


<s> if ( <ISA_LIT>VType :: getVLMUL ( Imm ) == <STR_LIT> :: LMUL_RESERVED || <ISA_LIT>VType :: getSEW ( Imm ) > <NUM_LIT> || ( Imm


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Op . getSimpleValueType ( ) == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL ,


<s> static const char * const CondNames [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; uint64_t Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Imm > <NUM_LIT> && Imm < <NUM_LIT> && <STR_LIT> ) ; O << CondNames [ Imm -


<s> if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : return true ; default : return false


<s> } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( *


<s> else ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_FLOAT ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; REAL_VALUE_TYPE f = REAL_VALUE_ATOF ( <STR_LIT> , inner_mode ) ; rtx ele = const_double_from_real_value ( f , inner_mode ) ; start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; rtx dup = gen_const_vec_duplicate ( mode , ele ) ; emit_move_insn ( dest , dup ) ; rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_BOOL ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; emit_move_insn ( dest , CONSTM1_RTX


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( *


<s> return ( reload_completed && cfun -> machine -> frame . total_size == <NUM_LIT> && ! cfun -> machine ->


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> return new <ISA_LIT>ConstantPoolValue (


<s> case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; }


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( )


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RealStackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = getStackSizeWithRVVPadding ( MF ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , getStackSizeWithRVVPadding ( MF ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize , MachineInstr :: FrameSetup ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxAlignment = MFI . getMaxAlign ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment . value ( ) ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment . value ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { unsigned ShiftAmount = Log2 ( MaxAlignment


<s> rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , CONSTM1_RTX ( mode ) ) ) ; end_sequence ( )


<s> bool has_non_zero_avl ( ) const { return m_avl


<s> if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N ,

<NUM_LIT> ) , DAG , Subtarget ) ) return GORC ;


<s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize , MachineInstr :: FrameSetup ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxAlignment = MFI . getMaxAlign ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment . value ( ) ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment . value ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { unsigned ShiftAmount = Log2 ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( hasBP (


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) )


<s> bool isUImm8Lsb00 ( ) const { if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr


<s> bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst *


<s> unsigned getRealMaxVLen ( ) const { unsigned VLen = getMaxRVVVectorSizeInBits ( ) ; return VLen == <NUM_LIT> ? getMaxVLen


<s> if ( info . valid_p ( ) && ! need_vsetvl ( require , info ) ) return ; info =


<s> assert ( Kind == KindTy :: Register && <STR_LIT> ) ; return Reg . RegNum .


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill =


<s> const GlobalValue * GV = N -> getGlobal ( ) ; SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Load ; Entry . Ty = CallTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F64Val -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; } } CurDAG -> RemoveDeadNodes (


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char *

Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const {


<s> Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Parts [ <NUM_LIT> ] = Val ; return true ; } if ( ValueVT . isScalableVector ( ) && PartVT . isScalableVector ( ) ) { LLVMContext & Context = * DAG . getContext ( ) ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ; if ( PartVTBitSize % ValueVTBitSize == <NUM_LIT> ) { if ( ValueEltVT != PartEltVT ) { unsigned Count = ValueVTBitSize / PartEltVT . getSizeInBits ( ) ; assert ( Count != <NUM_LIT> && <STR_LIT> ) ; EVT SameEltTypeVT = EVT :: getVectorVT ( Context , PartEltVT , Count ,


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc = S ; Op -> IsRV64 = IsRV64 ; return


<s> } insn_change_watermark watermark ; validate_change ( rinsn , & PATTERN ( rinsn ) , new_pat , true ) ; if ( ! recog ( attempt , change ) || ! change_is_worthwhile ( change , false ) ) return false ; remove_reg_equal_equiv_notes ( rinsn ) ; confirm_change_group ( ) ; ssa -> change_insn (


<s> static bool classof ( const <ISA_LIT>MCExpr *


<s> Value * <ISA_LIT>TargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { Value * Ordering = Builder . getInt32 ( static_cast < uint32_t > ( Ord ) ) ; Type * Tys [ ] = { AlignedAddr ->


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; else IsValid = isShiftedInt < N - <NUM_LIT> , <NUM_LIT> > (


<s> } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget


<s> return recog_data . operand [ get_attr_vl_op_idx ( rinsn ) ] ; } return SET_DEST ( XVECEXP ( PATTERN ( rinsn


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg (


<s> static unsigned getSPReg ( const <ISA_LIT>Subtarget &


<s> Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | Flmul ; } else { Op -> VType . Lmul = static_cast < VLMUL > ( LmulLog2 ) ; Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | LmulLog2 ; } if ( TailAgnostic ) { Op -> VType . Encoding |= <NUM_LIT> ; } if ( MaskedoffAgnostic ) { Op -> VType .


<s> if ( RegNo >= <NUM_LIT> || ( IsRV32E && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT ,


<s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) || evaluateConstantImm ( Imm


<s> case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) <<


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const


<s> if ( parseOperand ( Operands , ForceImmediate ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , false ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc


<s> return isCheriPureCapABI ( TargetABI ) ?


<s> if ( Size == <NUM_LIT> ) Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; else Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Target = Addr + Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } if ( Inst . getOpcode (


<s> <STR_LIT> Seq ; <STR_LIT> ( Value , isRV64 ( ) , Seq ) ; Register SrcReg = <STR_LIT> ; for ( <STR_LIT> & Inst : Seq ) { if ( Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ; } SrcReg =


<s> char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev ) return false ; Prev =


<s> if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; return getAddr ( N ,


<s> case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; } if ( ! Ok ) { ErrInfo = <STR_LIT> ; return false


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI ->


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn


<s> return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . removeOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset


<s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr


<s> Align StackAlign = std :: max ( Align ( XLenInBytes ) , ArgFlags1 . getNonZeroOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , StackAlign ) , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , Align ( XLenInBytes ) ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else


<s> if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) -


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand ::


<s> break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> | <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ Count


<s> const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI , <STR_LIT>


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , Ctx ) ; if ( Offset )


<s> SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , true , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; if ( IndexLog2EEW == <NUM_LIT> && ! Subtarget -> is64Bit ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL ,


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) +

GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ;


<s> if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc (


<s> } memset ( & args , <NUM_LIT> , sizeof args ) ; return riscv_get_arg_info ( & info , & args , mode


<s> break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case


<s> if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , BBInfo . Change ) && needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { BBInfo . Change = <STR_LIT> (


<s> if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd


<s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero , VL ) ; SplatTrueVal = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT


<s> bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT>


<s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ; assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax


<s> bool isV0Reg ( ) const { return Kind == KindTy :: Register && Reg .


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( ! llvm :: <STR_LIT> ( Imm ) ) return MCDisassembler