<s> MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; I . eraseFromParent


<s> LoadCmpBB -> addLiveIn ( DesiredLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredHi . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addOperand ( DesiredLo ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addOperand ( DesiredHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( StatusReg , RegState :: Kill ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , RegState :: Kill ) . addMBB ( DoneBB ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( NewLo . getReg ( ) ) ; StoreBB -> addLiveIn ( NewHi . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addOperand ( NewLo ) . addOperand ( NewHi ) . addOperand ( Addr ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , RegState :: Kill ) . addMBB ( LoadCmpBB ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs


<s> static int get_num_immediates ( rtx insn , int * imm , int * imm32 , int * imm64 ) { imm_info imm_values = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; find_constant ( insn , & imm_values ) ; * imm = imm_values . imm ; * imm32 = imm_values . imm32 ; * imm64 = imm_values . imm64 ; return imm_values . imm32 * <NUM_LIT> +


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( SDValue V = combineSextInRegCmov ( N , DAG ) ) return V ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> (

N00 . getNode ( ) ) ) return SDValue ( ) ;


<s> large = operands [ <NUM_LIT> ] ; zero_or_two31 = operands [ <NUM_LIT> ] ; input = operands [ <NUM_LIT> ] ; two31 = operands [ <NUM_LIT> ] ; vecmode = GET_MODE ( large ) ; value = gen_rtx_REG ( vecmode , REGNO ( operands [ <NUM_LIT> ] ) ) ; if ( MEM_P ( input ) ) { if ( vecmode == V4SFmode ) emit_insn ( gen_vec_setv4sf_0 ( value , CONST0_RTX ( V4SFmode ) , input ) ) ; else emit_insn ( gen_sse2_loadlpd ( value , CONST0_RTX ( V2DFmode ) , input ) ) ; } else { input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = IntRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; switch ( TYPE_MODE ( type ) ) { case TFmode : return <STR_LIT> ; case XFmode


<s> MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand ::


<s> if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) ) return ; if ( const MachineJumpTableInfo * JTI = MF -> getJumpTableInfo ( ) ) for ( const MachineJumpTableEntry & JTE : JTI -> getJumpTables ( ) ) for ( const MachineBasicBlock * MBB : JTE . MBBs ) { if ( isAlwaysIndirectTarget ( * MBB ) ) BlockJumpTableRefCount [ MBB ] = std :: numeric_limits < int > :: max ( ) ; else ++ BlockJumpTableRefCount [


<s> rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> ; int ub = valsize <= UNITS_PER_WORD ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> + i ) , GEN_INT ( offset ) ) ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( valsize > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( TYPE_MODE ( valtype ) ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE


<s> return ( rs6000_builtin_info [ ( int ) fncode ] . attr

& RS6000_BTC_OVERLOADED ) != <NUM_LIT> ;


<s> static SmallPtrSet < Value * , <NUM_LIT> > findAllDefs ( Value * V ) { SmallPtrSet < Value * , <NUM_LIT> > Defs ; SmallVector < Value * , <NUM_LIT> > WorkList ; WorkList . push_back ( V ) ; Defs . insert ( V ) ; while ( ! WorkList . empty ( ) ) { Value * Curr = WorkList .


<s> BUILTIN_VDQF ( UNOP , abs , <NUM_LIT> ) return fold_build1 ( ABS_EXPR , type , args [ <NUM_LIT> ] ) ; VAR1 ( UNOP , floatv2si , <NUM_LIT> , v2sf ) VAR1 ( UNOP , floatv4si , <NUM_LIT> , v4sf ) VAR1 ( UNOP , floatv2di , <NUM_LIT> , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ <NUM_LIT> ] ) ; default : break ; } return NULL_TREE


<s> MovtBit = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : ThumbBit = <NUM_LIT> ; break ; } if ( Type == MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ) { uint32_t OtherHalf = MovtBit ? ( FixedValue & <NUM_LIT> ) : ( ( FixedValue & <NUM_LIT> ) >> <NUM_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( OtherHalf << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( nullptr , Fragment -> getParent (


<s> if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return false ; if ( IsReassociableFMA ( Root , AddOpIdx , MulOpIdx , true ) ) { assert ( ( MulOpIdx >= <NUM_LIT> ) && <STR_LIT> ) ; Register MULRegL = TRI -> lookThruSingleUseCopyChain ( Root . getOperand ( MulOpIdx ) . getReg ( ) , MRI ) ; Register MULRegR = TRI -> lookThruSingleUseCopyChain ( Root . getOperand ( MulOpIdx + <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! MULRegL && ! MULRegR ) return false ; if ( MULRegL && ! MULRegR ) { MULRegR = TRI -> lookThruCopyLike ( Root . getOperand ( MulOpIdx + <NUM_LIT> ) . getReg ( ) , MRI ) ; IsUsedOnceL = true ; } else if ( ! MULRegL && MULRegR ) { MULRegL = TRI -> lookThruCopyLike ( Root . getOperand ( MulOpIdx ) . getReg ( ) , MRI ) ; IsUsedOnceR = true ; } else { IsUsedOnceL = true ; IsUsedOnceR = true ; } if ( ! Register :: isVirtualRegister ( MULRegL ) || ! Register :: isVirtualRegister ( MULRegR ) ) return false ; MULInstrL = MRI -> getVRegDef ( MULRegL ) ; MULInstrR = MRI -> getVRegDef ( MULRegR ) ; return true ; } return false ; } ; if ( DoRegPressureReduce && IsRPReductionCandidate ( ) ) { assert ( ( MULInstrL && MULInstrR ) && <STR_LIT> ) ; if ( isLoadFromConstantPool ( MULInstrL ) && IsUsedOnceR && IsReassociableAddOrSub ( * MULInstrR , InfoArrayIdxFSubInst ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Patterns . push_back ( MachineCombinerPattern :: REASSOC_XY_BCA ) ; return true ; } if ( ( isLoadFromConstantPool ( MULInstrR ) && IsUsedOnceL && IsReassociableAddOrSub ( * MULInstrL , InfoArrayIdxFSubInst ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Patterns . push_back ( MachineCombinerPattern :: REASSOC_XY_BAC ) ; return true ; } } AddOpIdx = - <NUM_LIT> ; if ( ! IsReassociableFMA ( Root , AddOpIdx , MulOpIdx , false ) ) return false ; assert ( ( AddOpIdx >= <NUM_LIT> ) && <STR_LIT> ) ; Register RegB = Root . getOperand ( AddOpIdx ) . getReg ( ) ; MachineInstr * Prev = MRI -> getUniqueVRegDef


<s> case <STR_LIT> : if ( ST -> hasMVEFloatOps ( ) ) continue ; break ; default : break ; } if ( IsMasked ( & I ) ) { auto * VecTy = getVectorType ( Int ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; continue ; } for ( const Use & U : Int -> args ( ) ) { if ( isa < VectorType > ( U -> getType ( ) ) ) return false ; } } } if ( ! ActiveLaneMask ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return ! MaskedInsts .


<s> static rtx mips_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { return mips_function_value_1 ( valtype ,


<s> void llvm :: emit<ISA_LIT>RegPlusImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , Register DestReg , Register BaseReg , int NumBytes , <STR_LIT> Pred , Register PredReg , const <ISA_LIT>BaseInstrInfo & TII , unsigned MIFlags ) { if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; return ; } bool isSub =


<s> bool allowsUnalignedFPAccess ( ) const { return AllowsUnalignedFPAccess


<s> getSORegImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT>


<s> return build_string_literal ( strlen ( objfmt ) + <NUM_LIT> ,


<s> const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <NUM_LIT> , false , false , MachinePointerInfo

( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> unsigned Rm = decodeRm ( insn ) ; unsigned Rd = decodeNEONRd ( insn ) ; bool WB = Rm != <NUM_LIT> ; unsigned RmEnum = <NUM_LIT> ; if ( WB && Rm != <NUM_LIT> ) RmEnum = getRegisterEnum ( B , <STR_LIT> , Rm ) ; if ( Store ) { assert ( OpIdx < NumOps && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; ++ OpIdx ; } assert ( ( OpIdx + <NUM_LIT> ) < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx += <NUM_LIT> ; if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( RmEnum ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> || OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; RegClass = OpInfo [ OpIdx ] . RegClass ; while ( OpIdx < NumOps && ( unsigned ) OpInfo [ OpIdx ] . RegClass == RegClass ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , Rd , DRegPair ) ) ) ; Rd += Inc ; ++ OpIdx ; } if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeLaneIndex ( insn ) ) ) ; ++ OpIdx ; } } else { RegClass = OpInfo [ <NUM_LIT> ] . RegClass ; while ( OpIdx < NumOps && ( unsigned ) OpInfo [ OpIdx ] . RegClass == RegClass ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , Rd , DRegPair ) ) ) ; Rd += Inc ; ++ OpIdx ; } if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; ++ OpIdx ; } assert ( ( OpIdx + <NUM_LIT> ) < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx +=


<s> static unsigned getFramePointerReg ( const


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr =


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCSetForICMP ( unsigned DefReg , unsigned Pred , MachineIRBuilder & MIRBuilder ) const { const <STR_LIT> InvCC = changeICMPPredTo<ISA_LIT>CC ( CmpInst :: getInversePredicate (


<s> if ( Cost != - <NUM_LIT> ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ICA ,


<s> static unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs


<s> assert ( NarrowTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & DstRB = * RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; for ( unsigned OpIdx = <NUM_LIT> ;


<s> bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize +=


<s> unsigned OrigBROpcode = BSI . OrigBranch -> getOpcode ( ) ; unsigned InvertedOpcode = OrigBROpcode == <STR_LIT> ? <STR_LIT> : OrigBROpcode == <STR_LIT> ? <STR_LIT> : OrigBROpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned NewBROpcode = BSI . InvertNewBranch ? InvertedOpcode : OrigBROpcode ; MachineBasicBlock * OrigTarget = BSI . OrigBranch -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * OrigFallThrough = OrigTarget == * ThisMBB -> succ_begin ( ) ? * ThisMBB -> succ_rbegin ( ) : * ThisMBB -> succ_begin ( ) ; MachineBasicBlock * NewBRTarget = BSI . BranchToFallThrough ? OrigFallThrough : OrigTarget ; BranchProbability ProbToNewTarget = ! BSI . MBPI ? BranchProbability :: getUnknown ( ) : BSI . MBPI -> getEdgeProbability ( ThisMBB , NewBRTarget ) ; MachineBasicBlock :: iterator InsertPoint = BSI . SplitBefore ; const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ThisMBB -> getIterator ( ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( ++ It , NewMBB ) ; NewMBB -> splice ( NewMBB -> end ( ) , ThisMBB , InsertPoint , ThisMBB -> end ( ) ) ; NewMBB -> transferSuccessors ( ThisMBB ) ; ThisMBB -> addSuccessor ( NewBRTarget , ProbToNewTarget ) ; ThisMBB -> addSuccessor ( NewMBB , ProbToNewTarget . getCompl ( ) ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( NewBROpcode ) ) . addReg ( BSI . SplitCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewBRTarget ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc (

) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewMBB ) ;


<s> bool MayNeedRelaxation ( const MCInst


<s> else if ( ( C = dyn_cast < ConstantSDNode > ( Op2 ) ) ) SetCC = Op1 ; else return SDValue ( ) ; if ( C -> getZExtValue ( ) == <NUM_LIT> ) { needOppositeCond = ! needOppositeCond ; checkAgainstTrue = true ; } else if ( C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; bool truncatedToBoolWithAnd = false ; while ( SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> ) { if ( SetCC . getOpcode ( ) == <STR_LIT> ) { int OpIdx = - <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( OpIdx == - <NUM_LIT> ) break ; SetCC = SetCC . getOperand ( OpIdx ) ; truncatedToBoolWithAnd = true ; } else SetCC = SetCC . getOperand ( <NUM_LIT> ) ; } switch ( SetCC . getOpcode ( ) ) { case <STR_LIT> : if ( checkAgainstTrue && ! truncatedToBoolWithAnd ) break ; assert ( <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) ; if ( needOppositeCond ) CC = <STR_LIT> ( CC ) ; return SetCC . getOperand ( <NUM_LIT> ) ; case <STR_LIT> : { ConstantSDNode * FVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * TVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; if ( ! TVal ) return SDValue ( ) ; if ( ! FVal ) { SDValue Op = SetCC . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || Op . getResNo ( ) != <NUM_LIT> ) return SDValue ( ) ; } bool FValIsFalse = true ; if ( FVal && FVal -> getZExtValue ( ) != <NUM_LIT> ) { if ( FVal -> getZExtValue ( ) != <NUM_LIT> ) return


<s> if ( Triple ( TT ) . isOSNaCl ( ) ) return new NaCl<ISA_LIT>AsmBackend ( T , true ) ; return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , true ,


<s> for ( unsigned PseudoReg : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) Mask [ PseudoReg / <NUM_LIT> ] &= ~ (

<NUM_LIT> << ( PseudoReg % <NUM_LIT> ) ) ;


<s> return ( int ) __builtin_ia32_vcvttsd2si32 ( ( __v2df ) __A ,


<s> StringRef getPassName ( ) const override { return


<s> case <STR_LIT> : case <STR_LIT> : isZExt = false ; case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> ) return false ; break ; } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , isZExt , false ) ) return false ; MI -> eraseFromParent ( ) ; return true


<s> return ( uint16x8_t ) __builtin_neon_vreinterpretv8hiv2di ( ( int64x2_t


<s> static <ISA_LIT>ABIInfo Unknown ( ) { return <ISA_LIT>ABIInfo ( <STR_LIT>


<s> void <ISA_LIT>AsmParser :: cvtStWriteBackRegAddrModeImm12 ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm12OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst


<s> return __builtin_mve_vcmphiq_m_uv8hi ( __a ,


<s> unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize (


<s> <ISA_LIT>LoopPreIncPrep ( <ISA_LIT>TargetMachine & TM ) : FunctionPass ( ID ) , TM ( & TM ) { initialize<ISA_LIT>LoopPreIncPrepPass ( * PassRegistry :: getPassRegistry


<s> static bool isPairedLdSt ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static inline void aarch64_add_sp ( rtx temp1 , rtx temp2 , poly_int64


<s> previnsn = result . insn , result . insn = stepfunc ( result . insn ) ) { if ( BARRIER_P ( result . insn ) ) break ; if ( ! NONJUMP_INSN_P ( result . insn ) ) continue ; if ( reg_set_p ( reg , result . insn ) ) { result . set_rtx = set_of ( reg , result . insn ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , <NUM_LIT> ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P (


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm (


<s> bool loongarch_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = <NUM_LIT> ) { return ( x & ( ( <NUM_LIT> << shift ) - <NUM_LIT> ) ) == <NUM_LIT> && x < ( ( unsigned ) <NUM_LIT>


<s> if ( ST -> hasAVX ( ) ) return <NUM_LIT> ; if ( ST -> hasSSE1 ( ) ) return <NUM_LIT> ; return


<s> FeatureBitset FB = ComputeAvailableFeatures ( STI . ToggleFeature ( OldMode . flip ( mode ) ) ) ; setAvailableFeatures ( FB ) ; assert ( FeatureBitset ( { mode } ) == (

STI . getFeatureBits ( ) & AllModes ) ) ;


<s> MCSymbolRefExpr :: VariantKind <ISA_LIT>AsmParser :: getVariantKind ( StringRef Symbol ) { MCSymbolRefExpr :: VariantKind VK = StringSwitch < MCSymbolRefExpr :: VariantKind > ( Symbol ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) . Default ( MCSymbolRefExpr :: VK_None ) ; return


<s> MachineInstr & LoadMI = * I ; Register BaseReg = getLdStBaseOp ( LoadMI ) . getReg ( ) ; if ( MBBI == B ) return false ; ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { MBBI = prev_nodbg ( MBBI , B ) ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && getLdStOffsetOp ( MI ) . isImm ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) ) return false ; if ( MI . mayStore ( ) && LoadMI . mayAlias ( AA , MI , false ) ) return false ; } while ( MBBI != B && Count < Limit ) ; return


<s> return ( uint16x8_t ) __builtin_aarch64_uaddlv8qi ( ( int8x8_t ) __a ,


<s> if ( Offset ) Ptr = IRB . CreateConstGEP1_32 ( Ptr , Offset ) ; IRB . CreateCall ( StgpFn , { Ptr , A , B }


<s> int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth


<s> aarch64_layout_arg ( pcum_v , mode , type , named ) ; gcc_assert ( ( pcum -> aapcs_reg != NULL_RTX ) != ( pcum -> aapcs_stack_words != <NUM_LIT> ) ) ; pcum -> aapcs_arg_processed = false ; pcum -> aapcs_ncrn = pcum -> aapcs_nextncrn ; pcum -> aapcs_nvrn = pcum -> aapcs_nextnvrn ; pcum -> aapcs_stack_size += pcum -> aapcs_stack_words ; pcum -> aapcs_stack_words = <NUM_LIT> ; pcum -> aapcs_reg


<s> inline vector signed int vec_vmaxsw ( vector signed int a1 , vector signed


<s> unsigned <ISA_LIT>TTIImpl :: getRegisterBitWidth ( bool Vector ) { if ( Vector ) { if ( ST -> hasAVX512 ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( ) ) return <NUM_LIT> ; if ( ST -> hasSSE1 (


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI


<s> SDValue <ISA_LIT>TargetLowering :: LowerAsSplatVectorLoad ( SDValue SrcOp , EVT VT , DebugLoc dl , SelectionDAG & DAG ) const { if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( SrcOp ) ) { SDValue Ptr = LD -> getBasePtr ( ) ; if ( ! <STR_LIT> ( LD ) || LD -> isVolatile ( ) ) return SDValue ( ) ; EVT PVT = LD -> getValueType ( <NUM_LIT> ) ; if ( PVT != <STR_LIT> && PVT != <STR_LIT> ) return SDValue ( ) ; int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( Ptr . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < <NUM_LIT> ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , <NUM_LIT> ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % <NUM_LIT> ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ <NUM_LIT> ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int Mask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; EVT VT = ( PVT == <STR_LIT> ) ? <STR_LIT> :


<s> if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_XOR ( mode , op1 , op2 )


<s> if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return


<s> if ( ( FirstMI == nullptr || FirstMI -> getOpcode ( ) == <STR_LIT> ) && SecondMI . getOpcode ( )


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'f' : case 'r' : break ; } } printOperand ( MI ,


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; } else { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT>


<s> return std :: string ( <STR_LIT> ) + ( IsWrite ? <STR_LIT> : <STR_LIT> ) + (


<s> SDNode * N1 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; unsigned NewOpc = <NUM_LIT> ; if ( isSignExtended ( N0 , DAG ) && isSignExtended ( N1 , DAG ) ) NewOpc = <STR_LIT> ; else if ( isZeroExtended ( N0 , DAG ) && isZeroExtended ( N1 , DAG ) ) NewOpc = <STR_LIT> ; else if ( VT == <STR_LIT> ) return SDValue ( ) ; else return Op ; DebugLoc DL = Op .


<s> bool MLxExpansion :: hasRAWHazard ( unsigned Reg , MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Domain = TID . TSFlags & <STR_LIT> ; if ( TID . mayStore ( ) ) return false ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return


<s> assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) ) ; MVT SVT = VT . getVectorElementType ( ) ; MVT InSVT = InVT . getVectorElementType ( ) ; assert ( SVT . getSizeInBits ( ) > InSVT . getSizeInBits ( ) ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( ! ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) && ! ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) && ! ( VT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int InSize = InSVT . getSizeInBits ( ) * VT . getVectorNumElements ( ) ; In = extractSubVector ( In , <NUM_LIT> , DAG , dl , std :: max ( InSize , <NUM_LIT> ) ) ; } assert ( ( Op . getOpcode ( ) != <STR_LIT> || InVT == <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget . hasInt256 ( ) ) { assert ( VT . getSizeInBits ( ) > <NUM_LIT> && <STR_LIT> ) ; unsigned ExtOpc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ExtOpc , dl , VT , In ) ; } assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Curr = In ; MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getVectorElementType ( ) !=


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , STI , O ) ; O << SignExtend32 < <NUM_LIT> > ( ( unsigned ) MI -> getOperand ( OpNo ) .


<s> static MCStreamer * createMCStreamer ( const Triple & TT , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter )


<s> machine_mode elt_mode ; int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ( TARGET_HARD_FLOAT && ! is_complex_IBM_long_double ( mode ) && FLOAT128_2REG_P ( mode ) ) ) ) return <NUM_LIT> ; else if ( FLOAT128_VECTOR_P ( mode ) ) return <NUM_LIT> ; else if ( PAIRED_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> &&

int_size_in_bytes ( type ) < <NUM_LIT> ) ) return <NUM_LIT> ;


<s> static SDValue combineAndnp ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; if ( ! IsPositionIndependent ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ; LHS2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS2 ,


<s> return ( int16x8_t ) __builtin_neon_vpadalsv16qi ( __a ,


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel , bool verbose ) { return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo


<s> return isSImmScaled < Width , <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDAG ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level


<s> switch ( code ) { case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && REG_P ( XEXP ( x , <NUM_LIT> ) ) && speed ) { rtx mul_op0 = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; rtx mul_op1 = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( REG_P ( mul_op0 ) && REG_P ( mul_op1 ) ) { * total = COSTS_N_INSNS


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpc ) , ResultReg ) ; if ( Subtarget -> hasAVX ( ) ) MIB . addReg ( OpReg ) ; MIB . addReg (


<s> return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndex1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEVectorIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEVectorIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEVectorIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEVectorIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc , <STR_LIT> ) ; case Match_MRS


<s> static bool f64AssignAAPCS ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , CCState & State , bool CanFail ) { static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , ShadowRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i


<s> auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } CallSeqStart . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; return


<s> v |= v << <NUM_LIT> ; if ( mode == DImode ) v |= ( v << <NUM_LIT> ) << <NUM_LIT> ; return copy_to_mode_reg ( mode , gen_int_mode ( v , mode ) ) ; } if ( valmode == VOIDmode ) valmode = QImode ; if ( valmode != QImode ) val = gen_lowpart ( QImode , val ) ; if ( mode == QImode ) return val ; if ( ! TARGET_PARTIAL_REG_STALL ) nops -- ; if ( ix86_cost -> mult_init [ mode == DImode ? <NUM_LIT> : <NUM_LIT> ] + ix86_cost -> mult_bit * ( mode == DImode ? <NUM_LIT> : <NUM_LIT> ) <= ( ix86_cost -> shift_const + ix86_cost -> add ) * nops + ( COSTS_N_INSNS ( TARGET_PARTIAL_REG_STALL == <NUM_LIT> ) ) ) { rtx reg = convert_modes ( mode , QImode , val , true ) ; tmp = promote_duplicated_reg ( mode , const1_rtx ) ; return expand_simple_binop ( mode , MULT , reg , tmp , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; } else { rtx reg = convert_modes ( mode , QImode , val , true ) ; if ( ! TARGET_PARTIAL_REG_STALL ) if ( mode == SImode ) emit_insn ( gen_movsi_insv_1 ( reg , reg ) ) ; else emit_insn ( gen_movdi_insv_1 ( reg , reg ) ) ; else { tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( <NUM_LIT> ) , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , <NUM_LIT> , OPTAB_DIRECT ) ; } tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( <NUM_LIT> ) , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , <NUM_LIT> , OPTAB_DIRECT ) ; if ( mode == SImode ) return reg ; tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( <NUM_LIT> ) , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , <NUM_LIT> , OPTAB_DIRECT ) ; return reg


<s> unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> )


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI


<s> assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr ) ; SrcReg = DestReg ; } if ( NumPredicateVectors ) { assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumPredicateVectors , <STR_LIT> ,


<s> return ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno


<s> O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << -


<s> MCTargetStreamer * llvm :: create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrinter , bool IsVerboseAsm ) { return new <ISA_LIT>WinCOFFAsmTargetStreamer ( S , OS , *


<s> assert ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: Selected ) && <STR_LIT> ) ; bool Changed = false ; for ( auto & BB : MF ) Changed |= optimizeNZCVDefs ( BB ) ; return


<s> BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( <NUM_LIT> ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return


<s> unsigned getMatrixReg ( ) const { assert ( Kind == k_MatrixRegister && <STR_LIT> ) ; return MatrixReg .


<s> Inst . addOperand ( MCOperand :: CreateReg ( getGPR32Reg


<s> case V4HImode : pattern = <STR_LIT> ; break ; case V8QImode : pattern = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , <STR_LIT> ) ; for ( i = CONST_VECTOR_NUNITS ( x ) ; i -- ; ) { rtx element ; element = CONST_VECTOR_ELT ( x ,


<s> void setFeatures ( const FeatureBitset &


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None

&& EnableDeadRegisterElimination ) addPass ( create<ISA_LIT>DeadRegisterDefinitions ( ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> OS . emitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . emitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . emitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet = false ; OS . PopSection ( ) ; MCSymbol * CurPCSym = Context . createTempSymbol ( ) ; OS . emitLabel ( CurPCSym ) ; const MCExpr * Size = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( CurPCSym , MCSymbolRefExpr ::

VK_None , Context ) , ExprRef , Context ) ;


<s> return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> case R8 : case D8 : case Q8 : return <NUM_LIT> ; case R9 : case D9 : case Q9 : return <NUM_LIT> ; case R10 : case D10 : case Q10 : return <NUM_LIT> ; case R11 : case D11 : case Q11 : return <NUM_LIT> ; case R12 : case D12 : case Q12 : return <NUM_LIT> ; case SP : case D13 : case Q13 : return <NUM_LIT> ; case LR : case D14 : case Q14 : return <NUM_LIT> ; case PC : case D15 : case Q15 : return <NUM_LIT> ; case D16 : return <NUM_LIT> ; case D17 : return <NUM_LIT> ; case D18 : return <NUM_LIT> ; case D19 : return <NUM_LIT> ; case D20 : return <NUM_LIT> ; case D21 : return <NUM_LIT> ; case D22 : return <NUM_LIT> ; case D23 : return <NUM_LIT> ; case D24 : return <NUM_LIT> ; case D25 : return <NUM_LIT> ; case D26 : return <NUM_LIT> ; case D27 : return <NUM_LIT> ; case D28 : return <NUM_LIT> ; case D29 : return <NUM_LIT> ; case D30 : return <NUM_LIT> ; case D31 : return <NUM_LIT> ; case S0 : case S1 : case S2 : case S3 : case S4 : case S5 : case S6 : case S7 : case S8 : case S9 : case S10 : case S11 : case S12 : case S13 : case S14 : case S15 : case S16 : case S17 : case S18 : case S19 : case S20 : case S21 : case S22 : case S23 : case S24 : case S25 : case S26 : case S27 : case S28 : case S29 : case S30 : case S31 : { if ( isSPVFP ) * isSPVFP = true ; switch ( RegEnum ) { default : return <NUM_LIT> ; case S0 : return


<s> if ( N -> isMachineOpcode ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand (

MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> return parseRegister ( Operands , RegGR ,


<s> return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Immediate ; case 'z' : case 'S' : return C_Other ; } } else if ( parsePredicateConstraint ( Constraint ) != PredicateConstraint :: Invalid ) return C_RegisterClass ; return TargetLowering :: getConstraintType (


<s> { MO_GOT_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PIC_BASE_OFFSET , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_TLSGD , <STR_LIT> } , { MO_TLSLD , <STR_LIT> } , { MO_TLSLDM , <STR_LIT> } , { MO_GOTTPOFF , <STR_LIT> } , { MO_INDNTPOFF , <STR_LIT> } , { MO_TPOFF , <STR_LIT> } , { MO_DTPOFF , <STR_LIT> } , {

MO_NTPOFF , <STR_LIT> } , { MO_GOTNTPOFF , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_DARWIN_NONLAZY , <STR_LIT> } , { MO_DARWIN_NONLAZY_PIC_BASE , <STR_LIT> } , { MO_TLVP , <STR_LIT> } , { MO_TLVP_PIC_BASE , <STR_LIT> } , { MO_SECREL , <STR_LIT> } } ;


<s> MachineBasicBlock * NextBB = next ( MachineFunction :: iterator ( MBB ) ) ; DOUT << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBSizes [ MI -> getParent ( ) -> getNumber ( ) ] -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; AdjustBBOffsetsAfter ( MBB , delta ) ; return true


<s> return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseArithmeticLogic ( ) || hasFuseCCSelect ( ) || hasFuseAdrpAdd (


<s> } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( ( int ) SImm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt16 ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt16 ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt32 ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; } } Opc =


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target ,


<s> return ( uint16x8_t ) __builtin_neon_vceqv8hf (


<s> if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , <NUM_LIT> ) ; } } unsigned const Max = ( NumStores ? ( <NUM_LIT> / NumStores ) : UINT_MAX ) ; if (


<s> if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> ) { return Extract128BitVector ( Vec , Idx , DAG ,


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar


<s> static inline _Unwind_Word _Unwind_GetGR ( _Unwind_Context * context , int regno ) { _uw


<s> if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . add ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr (


<s> addr = gen_rtx_PLUS ( Pmode , frame_reg , GEN_INT ( offset ) ) ; mem = gen_frame_mem ( GET_MODE ( reg ) ,


<s> return ( __m128i ) __builtin_ia32_vpcomleub ( ( __v16qi ) __A ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isLittle = false ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Default ) { if ( Subtarget . isABI_O32 ( ) ) setRelocationModel (


<s> int HomeOffset = FrameLowering . getOffsetOfLocalArea ( ) + <NUM_LIT> ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , NumIntRegs * <NUM_LIT> + HomeOffset , false ) ) ; if ( NumIntRegs < <NUM_LIT> ) FuncInfo -> setVarArgsFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) ) ; } else { FuncInfo -> setVarArgsGPOffset ( NumIntRegs * <NUM_LIT> ) ; FuncInfo -> setVarArgsFPOffset ( ArgGPRs . size ( ) * <NUM_LIT> + NumXMMRegs * <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateStackObject ( ArgGPRs . size ( ) * <NUM_LIT> + ArgXMMs . size ( ) * <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { Register XMMReg = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveXMMRegs . push_back ( DAG . getCopyFromReg ( Chain , DL , XMMReg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps


<s> unsigned Reg = Op . getReg ( ) ; if ( ! ShowVSRNumsAsVR ) Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MII . get ( MI -> getOpcode ( ) ) , Reg , OpNo ) ; const char * RegName ; RegName = getVerboseConditionRegName ( Reg , MRI . getEncodingValue ( Reg ) ) ; if ( RegName == nullptr ) RegName = getRegisterName ( Reg ) ; if ( showRegistersWithPercentPrefix ( RegName ) ) O <<


<s> static SDValue combineSBB ( SDNode * N , SelectionDAG & DAG ) { if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; } SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op1 ) && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getVTList ( ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getRARegister ( ) const { return


<s> const <ISA_LIT>Subtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL ,


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false


<s> MachineInstr :: mmo_iterator MMOEnd = MI . memoperands_end ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) { setUsesTOCBasePtr ( * MBB -> getParent ( ) ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } unsigned BaseReg ; if ( MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; else BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( BaseReg ) . addImm ( BPOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; MIB . addRegMask ( TRI -> getNoPreservedMask (


<s> return __builtin_mve_vrndmq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a


<s> SDValue Hi = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , In ) ; SDValue Lo = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , In ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo


<s> unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; assert ( Offset1 <= Offset2


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; return


<s> return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT>


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getTLSCallPreservedMask ( const MachineFunction & MF ) const { assert ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) && <STR_LIT> ) ; return


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo


<s> void <ISA_LIT>TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ; if ( Constraint . length ( ) > <NUM_LIT> ) return ; char ConstraintLetter = Constraint [ <NUM_LIT> ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) { Result = DAG . getTargetConstant ( Val , Type ) ; break ; } } return ; case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getZExtValue ( ) ; if ( Val == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , Type ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; uint64_t Val = ( uint64_t ) C -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( Val ) ) { Result = DAG . getTargetConstant ( Val , Type ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT>


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment )


<s> for ( int I = MFI . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( *


<s> TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const MCExpr * OffsetExpr ; int64_t OffsetVal ; SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) || ! OffsetExpr -> evaluateAsAbsolute ( OffsetVal ) ) { reportParseError ( ExprLoc , <STR_LIT> ) ; return false ; } Save = OffsetVal ; SaveIsReg = false ; } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } Save = SaveOpnd .


<s> rtx reg ; if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , <NUM_LIT> ) ; if ( mode == BLKmode ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG +


<s> std :: string FS ; if ( TheTriple . getArch ( ) == Triple ::


<s> rtx store = gen_rtx_SET ( VOIDmode , op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( par


<s> if ( ( GET_CODE ( x ) == CONST_VECTOR && aarch64_simd_valid_immediate ( x , mode , false , NULL ) ) ||

CONST_INT_P ( x ) || aarch64_valid_floating_const ( mode , x ) ) return ! targetm . cannot_force_const_mem ( mode , x ) ;


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) { if ( TargetTriple . getArch ( ) == Triple :: ppc64le ) CPUName = <STR_LIT> ; else CPUName = <STR_LIT> ; } ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = <NUM_LIT> ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple :: ppc64le ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { if ( ! isDarwin ( ) && Is<ISA_LIT>64 ) { if ( IsLittleEndian ) TargetABI = <ISA_LIT>_ABI_ELFv2 ; else TargetABI


<s> case LR : case SP : case PC : return true ; case R8 : case R9 : case R10 : case R11 : case R12 : return ! isIOS ; default : return false


<s> rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm


<s> unsigned SrcBitWidth = Op . getOperand ( OpNo ) . getScalarValueSizeInBits ( ) ; EVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getScalarSizeInBits ( ) ; if ( SrcBitWidth > VTBits ) { unsigned SrcExtraBits = SrcBitWidth - VTBits ; if ( Common > SrcExtraBits ) return ( Common - SrcExtraBits ) ; return <NUM_LIT> ; } assert ( SrcBitWidth == VTBits && <STR_LIT> ) ; return Common


<s> bool Changed = false ; const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineFunction :: iterator MBBI = MF . begin ( ) ; MachineFunction :: iterator EndMBB = MF . end ( ) ; for ( ; MBBI != EndMBB ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>MFI ->


<s> static bool checkPartMapping ( const RegisterBankInfo :: PartialMapping & PM , unsigned Start

, unsigned Length , unsigned RegBankID ) {


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result


<s> bool IsLoadInst = ( Inst . getOpcode ( ) == <STR_LIT> ) ; bool DoMove = IsLoadInst && ( SrcReg == DstReg ) && ! IsLargeOffset ; unsigned TmpReg = SrcReg ; if ( IsLargeOffset || DoMove ) { warnIfNoMacro ( IDLoc ) ; TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; } if ( IsLargeOffset ) { if ( loadImmediate ( OffsetValue , TmpReg , SrcReg , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Out , STI ) ) return true ; } if ( DoMove ) std :: swap ( DstReg , TmpReg ) ; unsigned XWL = IsLoadInst ? <STR_LIT> : <STR_LIT> ; unsigned XWR = IsLoadInst ? <STR_LIT> : <STR_LIT> ; TOut . emitRRI ( XWL , DstReg , TmpReg , LxlOffset , IDLoc , STI ) ; TOut . emitRRI ( XWR , DstReg , TmpReg , LxrOffset , IDLoc , STI ) ; if ( DoMove ) TOut . emitRRR ( <STR_LIT> , TmpReg , DstReg ,


<s> SDValue NandABNandA = DAG . getNode ( <STR_LIT> , DL , VT , NandAB , LHS ) ; SDValue NandABNandB = DAG . getNode ( <STR_LIT> , DL , VT , NandAB , RHS ) ; SDValue Xor = DAG . getNode ( <STR_LIT> , DL , VT , NandABNandA , NandABNandB ) ; return


<s> void emitHandlerDataLocNotes ( ) const { for ( const SMLoc & Loc : HandlerDataLocs ) Parser . Note (


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand


<s> DebugLoc DL = MIB -> getDebugLoc ( ) ; Register Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg

( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( -


<s> for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addOperand ( Base ) .

addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> else cr = gen_reg_rtx ( cmpmode ) ; rtx label_ref = gen_rtx_LABEL_REF ( VOIDmode , true_label ) ; if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref ,


<s> for ( unsigned i = CSI . size ( ) , Size = <NUM_LIT> ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) continue ; if ( Size == <NUM_LIT> ) { unsigned Align = TRI -> getSpillAlignment ( <STR_LIT> ) ; int Remainder = SpillSlotOffset % Align ; if ( Remainder < <NUM_LIT> ) SpillSlotOffset -= Align + Remainder ; else SpillSlotOffset -= Remainder ; MFI . ensureMaxAlignment ( Align ) ; Size = TRI -> getSpillSize ( <STR_LIT> ) ; } SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; if ( CalleeSavedXMMFrameSize == <NUM_LIT> ) { CalleeSavedXMMSlotOrigin = SlotIndex ; } CalleeSavedXMMFrameSize += Size ; } <ISA_LIT>FI -> setCalleeSavedXMMFrameInfo ( CalleeSavedXMMFrameSize , CalleeSavedXMMSlotOrigin ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; int Remainder = SpillSlotOffset % Align ; if ( Remainder < <NUM_LIT> ) SpillSlotOffset -= Align + Remainder ; else SpillSlotOffset -= Remainder ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align )


<s> for ( ; len -- ; ) { tree member = VEC_index ( tree , method_vec , len ) ; if ( ! member ) continue ; for ( member = OVL_CURRENT ( member ) ; member ; member = OVL_NEXT ( member ) ) { if ( TREE_CODE ( member ) !=


<s> case <STR_LIT> : case <STR_LIT> : return SetBlendDomain ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return SetBlendDomain ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Subtarget . hasDQI ( ) ) return false ; const uint16_t * table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableCustomAVX512LogicInstrs ) ; assert ( table && <STR_LIT> ) ; if ( Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; MI . setDesc ( get ( table [ Domain - <NUM_LIT> ] ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : if ( Domain != dom && Domain != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( )

== <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) {


<s> if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode ::


<s> assert ( Val . getSimpleValueType ( ) == <STR_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue Result = Op ; if ( false ) { } else { SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue PackedElt = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { Vec , HalfIdx } ) , <NUM_LIT> ) ; SDValue AndIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { AndIdx , Const1 } ) ; SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Mask , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; Val = DAG . getNode ( <STR_LIT> , DL


<s> static bool matches_type_p ( const_tree model_type , const_tree candidate ) { if ( VECTOR_TYPE_P ( model_type ) ) { if ( ! VECTOR_TYPE_P ( candidate ) || maybe_ne ( TYPE_VECTOR_SUBPARTS ( model_type ) , TYPE_VECTOR_SUBPARTS ( candidate ) ) || TYPE_MODE ( model_type ) != TYPE_MODE ( candidate ) ) return false ; model_type = TREE_TYPE ( model_type ) ; candidate = TREE_TYPE ( candidate ) ; } return ( candidate != error_mark_node && TYPE_MAIN_VARIANT ( model_type ) == TYPE_MAIN_VARIANT ( candidate


<s> } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill && ! SrcIsUndef ) MIB -> addRegisterKilled ( SrcReg , TRI , true ) ; else if ( ! SrcIsUndef ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; TransferImpOps ( MI , MIB , MIB ) ; MIB . cloneMemRefs


<s> case TLSModel :: InitialExec : Modifier = <STR_LIT> ; break ; case TLSModel :: LocalExec : Modifier = <STR_LIT> ; break ; } } else if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { Modifier = <STR_LIT> ; } } break ; case MachineOperand :: MO_BlockAddress : Name = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Name = MO . getSymbolName ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Name = GetCPISymbol ( MO . getIndex ( ) ) -> getName ( ) ; break ; } if ( PrintImmediatePrefix ) O


<s> int i ; if ( ! TARGET_V9 ) return <NUM_LIT> ; for ( i = XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { rtx expr = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( expr ) != SET ) return <NUM_LIT> ; if ( GET_CODE ( SET_DEST ( expr ) ) != REG ) return <NUM_LIT> ; regno = REGNO ( SET_DEST ( expr ) ) ; if ( regno >= <NUM_LIT> && regno < <NUM_LIT> ) return <NUM_LIT> ; } return ! epilogue_renumber ( & pat , <NUM_LIT> ) ; } if ( GET_CODE ( pat ) != SET ) return <NUM_LIT> ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG ) return <NUM_LIT> ; regno = REGNO ( SET_DEST ( pat ) ) ; if ( regno >= <NUM_LIT> && regno < <NUM_LIT> ) return <NUM_LIT> ; if ( ! SPARC_INT_REG_P ( regno ) ) return TARGET_V9 && ! epilogue_renumber ( & pat , <NUM_LIT> ) ; return eligible_for_restore_insn ( trial


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE &&


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android )

&& ! isTargetDarwin ( ) && ! isTargetWindows ( ) && ! isTargetNaCl ( ) && ! Enable<ISA_LIT>DwarfEH ;


<s> create_fixed_operand ( & m_ops . last (


<s> bool isLegalMaskedScatter ( Type * Ty , MaybeAlign Alignment ) { return


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , Flags ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { const Constant * C = CP -> getConstVal ( ) ; ImmOpnd = CurDAG -> getTargetConstantPool ( C , <STR_LIT> , CP -> getAlignment ( ) , <NUM_LIT> , Flags ) ; } } if ( FirstOp == <NUM_LIT> ) ( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , ImmOpnd , Base . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; else ( void ) CurDAG -> UpdateNodeOperands ( N , ImmOpnd , Base . getOperand ( <NUM_LIT> ) , N -> getOperand (


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR128DecoderTable [


<s> const IntrinsicData * Data = std :: lower_bound ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) , IntrinsicToFind ) ; if ( Data != std :: end ( IntrinsicsWithoutChain ) && * Data ==


<s> auto * CompareVal = dyn_cast < ConstantSDNode > ( ICmp -> getOperand ( <NUM_LIT> ) ) ; if ( ! CompareVal ) return false ; auto * TrueVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal ) return false ; auto * FalseVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! FalseVal ) return false ; if ( CompareVal -> getZExtValue ( ) == FalseVal -> getZExtValue ( ) ) Invert = ! Invert ; else if ( CompareVal -> getZExtValue ( ) != TrueVal -> getZExtValue ( ) ) return false ; auto * NewCCValid = dyn_cast < ConstantSDNode > (


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue &


<s> } XVECEXP ( pattern , <NUM_LIT> , j ) = set ; } if ( umips_swm_encoding [ i ] >> <NUM_LIT> ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; * mask &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( VOIDmode , reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , <NUM_LIT> , j ) = set ; } pattern = emit_insn ( pattern ) ; if ( fn == mips_save_reg ) RTX_FRAME_RELATED_P ( pattern ) = <NUM_LIT> ; * offset -= UNITS_PER_WORD * nregs


<s> int FI = MFI . CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset , DL , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , DL , DAG . getRegister ( VReg , RegTy ) , StorePtr , MachinePointerInfo ( FuncArg , Offset ) ) ; OutChains . push_back


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; tree arg1 , arg0 ; enum rs6000_builtins fcode = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; enum insn_code icode ; machine_mode tmode , mode0 ; rtx pat , op0 ; const struct builtin_description * d ; size_t i ; * expandedp = true ; switch ( fcode ) { case SPE_BUILTIN_EVSTDD : case SPE_BUILTIN_EVSTDH : case SPE_BUILTIN_EVSTDW : case SPE_BUILTIN_EVSTWHE : case SPE_BUILTIN_EVSTWHO : case SPE_BUILTIN_EVSTWWE : case SPE_BUILTIN_EVSTWWO : arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } break ; default : break ; } switch ( fcode ) { case SPE_BUILTIN_EVSPLATFI : return rs6000_expand_unop_builtin ( CODE_FOR_spe_evsplatfi , exp , target ) ; case SPE_BUILTIN_EVSPLATI : return rs6000_expand_unop_builtin ( CODE_FOR_spe_evsplati , exp , target ) ; default : break ; } d = bdesc_2arg_spe ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_2arg_spe ) ; ++ i , ++ d ) if ( d -> code == fcode ) return rs6000_expand_binop_builtin ( d -> icode , exp , target ) ; d = bdesc_spe_predicates ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_predicates ) ; ++ i , ++ d ) if ( d -> code == fcode ) return spe_expand_predicate_builtin ( d -> icode , exp , target ) ; d = bdesc_spe_evsel ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_evsel ) ; ++ i , ++ d ) if ( d -> code == fcode ) return spe_expand_evsel_builtin ( d -> icode , exp , target ) ; switch ( fcode ) { case SPE_BUILTIN_EVSTDDX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstddx , exp ) ; case SPE_BUILTIN_EVSTDHX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdhx , exp ) ; case SPE_BUILTIN_EVSTDWX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdwx , exp ) ; case SPE_BUILTIN_EVSTWHEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhex , exp ) ; case SPE_BUILTIN_EVSTWHOX


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Value = CE ->


<s> return __builtin_ia32_maxph512_mask_round ( __A , __B , _mm512_setzero_ph ( ) , (


<s> <STR_LIT> Flags = Outs [ i ] . Flags ; EVT ArgVT = Arg . getValueType ( ) ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { if ( ! isVarArg && ! is<ISA_LIT>64 ) { nAltivecParamsAtEnd ++ ; continue ; } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast


<s> credit -= get_attr_length ( prev ) ; } if ( prev && jump_to_label_p ( prev ) ) { rtx_insn * x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; } } } return


<s> MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; if ( isFPCmp ) { BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; } else { BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; } BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand (

<NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> static unsigned getLoadRegOpcode ( unsigned DestReg , const TargetRegisterClass * RC , bool isStackAligned , const TargetMachine & TM ) { unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( isHReg ( DestReg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc =


<s> static bool isV8M ( const <ISA_LIT>Subtarget * Subtarget


<s> void <ISA_LIT>TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = IsN64 ? <STR_LIT> : <STR_LIT> ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [

i ] . first , RegsToPass [ i ] . second , InFlag ) ;


<s> case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createUpper16 ( Expr , OutContext ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_PLT , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr ::

create ( MO . getOffset ( ) , OutContext ) , OutContext ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> bool has<ISA_LIT>32r5 ( ) const { return ( <ISA_LIT>ArchVersion >= <ISA_LIT>32r5 && <ISA_LIT>ArchVersion < <ISA_LIT>32Max )


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , uint32_t CPUType


<s> x = vec_splat ( ( vec_uchar16 ) ( si_from_uint (


<s> StringRef Name ; if ( isMachO ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; Name = Tok . getString ( ) ; Parser . Lex ( ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex (


<s> DebugLoc DL ( Loc ) ; MI -> setDebugLoc


<s> bool <ISA_LIT>TargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = static_cast < const yaml :: <ISA_LIT>FunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < <ISA_LIT>FunctionInfo > (

) -> initializeBaseYamlFields ( YamlMFI ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( GV -> isDeclaration ( ) ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> if ( <STR_LIT> . contains ( DestReg ) ) { assert ( Subtarget . hasBWI ( ) ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) return Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { assert ( Subtarget . hasBWI ( ) ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( SrcReg ) ) return Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg )


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 ; machine_mode tmode = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op0 = safe_vector_operand ( op0 , mode0 ) ; op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = GEN_INT ( d


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , StringRef TT ) { return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) .


<s> return ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>