<s> if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address )


<s> static __inline qword si_xor ( qword a , qword b ) { return ( ( qword ) ( vec_xor ( ( vec_uchar16 ) (


<s> static bool MayFoldIntoZeroExtend ( SDValue Op ) { if ( Op . hasOneUse ( ) ) { unsigned Opcode = Op . getNode ( ) -> use_begin ( ) -> getOpcode ( ) ; return ( <STR_LIT> == Opcode ) ; } return false


<s> bool isImm0_7 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool MVEVPTOptimisations :: runOnMachineFunction ( MachineFunction & Fn ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) || ! STI


<s> bool Aligned = S -> getAlignment ( ) == <NUM_LIT> || S -> getAlignment ( ) >= SABIAlignment ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) )


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT>

<< NextBB -> getNumber ( ) << <STR_LIT> ) ;


<s> __vis_alignaddrl ( void * __A , long __B ) { return __builtin_vis_alignaddrl ( __A ,


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) { if ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) { if ( ! TT . isOSBinFormatMachO ( ) && ! TT . isMacOSX ( ) ) return Reloc :: PIC_ ; } if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; return Reloc ::


<s> if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc


<s> if ( DCI . isBeforeLegalizeOps ( ) && Value . getOpcode ( ) == <STR_LIT> && Value . getNode ( ) -> hasOneUse ( ) && ST -> isUnindexed ( ) && Subtarget -> useSVEForFixedLengthVectors ( ) && Value . getValueType ( ) . isFixedLengthVector ( ) && Value . getValueType ( ) . getFixedSizeInBits ( ) >= Subtarget -> getMinSVEVectorSizeInBits ( ) ) return DAG . getTruncStore ( Chain , SDLoc ( N ) , Value . getOperand ( <NUM_LIT> ) , Ptr , ST -> getMemoryVT ( ) , ST -> getMemOperand ( ) ) ; if ( SDValue Split = splitStores ( N , DCI , DAG , Subtarget ) ) return Split ; if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue


<s> MachineOperand Src ( AccMO ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( Opcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . add ( Src ) . add


<s> unsigned SrcReg = Src . getReg ( ) ; if ( Opc != <STR_LIT> ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI -> getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR


<s> bool Modified = false ; ( void ) std :: initializer_list < int > { Modified |= std :: get < ThunkInserterT > ( ThunkInserters ) . run ( MMI , MF ) ... } ; return Modified


<s> void discardImplicitITBlock ( ) { assert ( inImplicitITBlock (


<s> <ISA_LIT>GenericDisassembler :: <ISA_LIT>GenericDisassembler ( DisassemblerMode mode )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return MachineLocation ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI

-> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> static __inline void * si_to_ptr ( qword q ) { union { qword q ; void * p


<s> static DecodeStatus DecodeGRH32BitRegisterClass ( MCInst & Inst , uint64_t RegNo

, uint64_t Address , const MCDisassembler * Decoder ) {


<s> if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ <STR_LIT> ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; <ISA_LIT>ELFStreamer & MEF = static_cast < <ISA_LIT>ELFStreamer & > ( Streamer ) ; MEF . Emit<ISA_LIT>OptionRecords (


<s> void DecodeBLENDMask ( MVT VT , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { int NumElements = VT .


<s> int pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ! SMALL_INT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; return


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> const uint8_t * THMTo<ISA_LIT>Stub :: getContent ( ) const { return reinterpret_cast < const uint8_t * > (


<s> processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + <STR_LIT> ) ; int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset


<s> avoid_collisions ( tag_map ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> num ) ; tag_map . traverse < void * , dump_insn_list > ( NULL ) ; } tag_map . traverse < void * , free_insn_info


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getFGR32Reg ( ) ) ) ; if ( ! AsmParser . useOddSPReg ( ) && RegIdx . Index &

<NUM_LIT> ) AsmParser . Error ( StartLoc , <STR_LIT> <STR_LIT> ) ;


<s> APInt NUsefulBits ; getUsefulBits ( SDValue ( N , <NUM_LIT> ) , NUsefulBits ) ; if ( ! NUsefulBits ) { CurDAG -> SelectNodeTo ( N , TargetOpcode :: IMPLICIT_DEF , N -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( tryBitfieldInsertOpFromOr ( N , NUsefulBits , CurDAG ) ) return true ; return tryBitfieldInsertOpFromOrAndImm ( N , CurDAG


<s> } if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , <STR_LIT> ) == <NUM_LIT> ) return true ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; ret = rs6000_inner_target_options ( args , true ) ; if ( ret ) { ret = rs6000_option_override_internal ( false ) ; new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( ! new_target ) ret = false ; else if ( fndecl ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl


<s> bool hardenSlsBlr ( ) const { return


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> if ( mips_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , <STR_LIT>


<s> void addVectorIndexSOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> SrcReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; SrcReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg =


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && Predicate . isPredicate ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = * MIRBuilder . getMRI ( ) ; MachineInstr * LHSDef = getDefIgnoringCopies ( LHS . getReg ( ) , MRI ) ; MachineInstr * RHSDef = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; auto P = static_cast < CmpInst :: Predicate > ( Predicate . getPredicate ( ) ) ; if ( isCMN ( LHSDef , P , MRI ) ) return emitCMN ( LHSDef -> getOperand ( <NUM_LIT> ) , RHS , MIRBuilder ) ; if ( isCMN ( RHSDef , P , MRI ) ) return emitCMN ( LHS , RHSDef -> getOperand ( <NUM_LIT> ) , MIRBuilder ) ; if ( ! CmpInst :: isUnsigned ( P ) && LHSDef && LHSDef -> getOpcode ( ) == TargetOpcode :: G_AND ) { auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI


<s> void printf80mem ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT>

) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> static struct machine_function * ia64_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( )


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; assert ( DefMI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; RegMO = & DefMI . getOperand ( <NUM_LIT> ) ; ImmMO = & DefMI .


<s> const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang , MMI


<s> static void encode_pattern ( rtx x ) { patternp = pattern ; encode_pattern_1 ( x ) ; * patternp


<s> unsigned SubIdx = ( IsI64 ? <STR_LIT> : <STR_LIT> ) ; bool DstIsLarger , SrcIsLarger ; tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg


<s> if ( c == PLUS ) { if ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( ARITHMETIC_P ( XEXP ( x , <NUM_LIT> ) ) || ARITHMETIC_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; return <NUM_LIT> ; } return <NUM_LIT>


<s> if ( ( DataWidth < <NUM_LIT> ) || ( Consecutive == <NUM_LIT> ) ) return false ; if ( ST -> hasAVX512 ( ) || ST


<s> if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return ( cfun -> machine -> frame . total_size == <NUM_LIT> &&

! cfun -> machine -> use_frame_header_for_callee_saved_regs ) ;


<s> size_t <ISA_LIT>To<ISA_LIT>Stub :: alignment ( ) const { return


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo (


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS


<s> GetInstSeqLs ( Imm >> Shamt , RemSize - Shamt , SeqLs ) ; AddInstr ( SeqLs , Inst ( SLL , Shamt )


<s> if ( size % UNITS_PER_WORD != <NUM_LIT> ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , <NUM_LIT> ) ; } } if ( mips_abi != ABI_EABI && ! FLOAT_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , GP_RETURN ) ; } if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) return gen_rtx_REG ( mode , FP_RETURN ) ; if ( mode == TFmode ) return mips_return_fpr_pair ( mode , DImode , <NUM_LIT> , DImode , GET_MODE_SIZE ( mode ) / <NUM_LIT> ) ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * <NUM_LIT> ) return mips_return_fpr_pair ( mode , GET_MODE_INNER ( mode ) , <NUM_LIT> , GET_MODE_INNER ( mode ) , GET_MODE_SIZE ( mode ) / <NUM_LIT> ) ; return gen_rtx_REG ( mode


<s> unsigned GetFrameReg ( const MCContext & Ctx , MCStreamer & Out ) { unsigned FrameReg = GetFrameRegGeneric ( Ctx , Out ) ; if ( FrameReg ==


<s> return findNonImmUse ( Root , Def , ImmedUse , Root


<s> void Emitter < CodeEmitter > :: emitMachineBasicBlock ( MachineBasicBlock * BB , unsigned Reloc


<s> ( void ) TII -> getGlobalBaseReg ( & DAG . getMachineFunction ( ) ) ; } return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op . getOperand

( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> int NumEltsInLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned LaneStart = ( i / NumEltsInLane ) * NumEltsInLane ; int Pos = ( i % NumEltsInLane ) / <NUM_LIT> + LaneStart ; Pos += ( Unary ? <NUM_LIT> : NumElts * ( i %


<s> case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : prefix = one_only ? <STR_LIT> : <STR_LIT> ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? <STR_LIT> : <STR_LIT> ; string = ACONCAT ( ( linkonce , prefix , <STR_LIT> , name , NULL ) ) ; set_decl_section_name ( decl , string ) ; return ; } } default_unique_section ( decl , reloc


<s> auto & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } MachineInstrBuilder MIB { MF , I } ; using namespace TargetOpcode ; switch ( I . getOpcode ( ) ) { case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB . addImm ( <NUM_LIT> ) ) ) ; break ; case G_LOAD : I . setDesc ( TII . get (


<s> gcc_assert ( is_valid != <NUM_LIT> ) ; if ( quad ) sprintf ( templ , <STR_LIT> , mnem , width ) ; else sprintf ( templ , <STR_LIT> , mnem , width


<s> unsigned getMinVectorRegisterBitWidth ( )


<s> Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result , DAG . getConstant ( Offset , getPointerTy ( ) ) ) ; return


<s> static bool getSubRegForClass ( const TargetRegisterClass * RC , const TargetRegisterInfo & TRI , unsigned & SubReg ) { switch ( TRI . getRegSizeInBits ( * RC ) ) { case <NUM_LIT> : SubReg = <STR_LIT> ; break ; case <NUM_LIT> : SubReg = <STR_LIT> ; break ; case <NUM_LIT>


<s> for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned tt = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( invSrc ) { MIB = BuildMI ( newMBB , dl , TII -> get ( notOpc ) , tt ) . addReg ( t1 ) ; } else tt = t1 ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( regOpc ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( immOpc ) , t2 ) ; MIB . addReg ( tt ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( copyOpc ) , EAXreg ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( CXchgOpc ) ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MIB . addReg ( t2 ) ; assert ( bInstr -> hasOneMemOperand ( ) && <STR_LIT> ) ; ( * MIB ) . setMemRefs ( bInstr -> memoperands_begin ( ) , bInstr -> memoperands_end ( ) ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( copyOpc ) , destOper . getReg ( ) ) ; MIB . addReg ( EAXreg ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> )


<s> if ( Use -> isMachineOpcode ( ) ) { const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode ==


<s> rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ; return true


<s> if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef ( ) ) if ( SDValue Rotate = lowerShuffleAsBitRotate ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue PSHUFB = lowerShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable ,


<s> std :: string word ; while ( ( cur = val . find_first_of ( <STR_LIT> , prev ) ) != std :: string :: npos ) { word = val . substr ( prev , cur - prev ) ; if ( ! word . empty ( ) ) result . insert (


<s> bool isMemWithUimmWordAlignedOffsetSP ( ) const { return isMem ( ) && isConstantMemOff ( ) && isUInt < Bits > ( getConstantMemOff ( ) ) && ( getConstantMemOff ( ) % <NUM_LIT> ==

<NUM_LIT> ) && getMemBase ( ) -> isRegIdx ( ) && ( getMemBase ( ) -> getGPR32Reg ( ) == <STR_LIT> ) ;


<s> if ( ListFrom == ListTo && ListFrom == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) ; else if ( ListFrom == ListTo && ListFrom == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) ; else if ( ListFrom == <STR_LIT> ) return ListTo - ListFrom + <NUM_LIT> ; else if ( ListFrom == <STR_LIT> ) return ( ( ListTo - ListFrom


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm (

Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> __vector unsigned short __c ; if ( __count <= <NUM_LIT> ) { __r = ( __vector signed short ) vec_splats ( __m ) ; __c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; __r = vec_sl ( __r , ( __vector unsigned short ) __c ) ; return ( __m64 ) ( ( __vector long long ) __r ) [ <NUM_LIT> ] ; } else return (


<s> computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setBooleanContents ( UndefinedBooleanContent ) ; setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> )


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand


<s> NewMI -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; Modified = true ; break ; } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } AddDefaultPred ( LO16 ) ; AddDefaultPred ( HI16 ) ; } MI . eraseFromParent ( ) ; Modified = true ; } } MBBI = NMBBI ; } return Modified


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( getTheThumbLETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( getTheThumbBETarget (


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! IgnoreSPUpdates && ! TFI -> hasReservedCallFrame ( MF ) ) return getFrameIndexReference ( MF , FI


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_subs (


<s> MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( scratch ) . addReg ( ptr ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( stxr_status ) . addMBB ( loopMBB ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = exitMBB ; MI -> eraseFromParent ( )


<s> if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && Operands . size ( ) == <NUM_LIT> && ( Name ==


<s> case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) , false , false , VerboseAsm ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; std :: string Name = Mang -> getMangledName ( GV ) ; O << Name ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && ! GV -> hasHiddenVisibility ( ) && ! GV -> hasProtectedVisibility (

) && ! GV -> hasLocalLinkage ( ) ) O << <STR_LIT> ;


<s> return MaskBit ? <STR_LIT> ( ITState . Cond


<s> return isMem128 ( ) && isMemIndexReg ( <STR_LIT>


<s> MachineFunction & MF = * MBB . getParent ( ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! Src1Ty . isVector ( ) || ! Src2Ty . isVector ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned BytesPerElt = DstTy . getElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < Constant * , <NUM_LIT> > CstIdxs ; for ( int Val : Mask ) { Val = Val < <NUM_LIT> ? <NUM_LIT> : Val ; for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } MachineIRBuilder MIRBuilder ( I ) ; Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIRBuilder ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ; auto TBL2 = MIRBuilder . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) } , { RegSeq , IndexLoad -> getOperand ( <NUM_LIT> ) } ) ; constrainSelectedInstRegOperands ( * RegSeq , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( * TBL2 , TII , TRI ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> TII . loadRegFromStack ( MBB , I , VR , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , Dst ) . addReg (


<s> std :: unique_ptr < MCObjectTargetWriter > llvm ::

create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) {


<s> } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) )


<s> tree ftype , decl ; ix86_init_builtin_types ( ) ; ix86_init_platform_type_builtins ( ) ; def_builtin_const ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , FLOAT128_FTYPE_VOID , IX86_BUILTIN_INFQ ) ; def_builtin_const ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , FLOAT128_FTYPE_VOID , IX86_BUILTIN_HUGE_VALQ ) ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_CONST_STRING ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_FABSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_FABSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_COPYSIGNQ , BUILT_IN_MD ,


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget


<s> } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( ( RHSC & <NUM_LIT> ) == <NUM_LIT> ) && ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( - RHSC , <STR_LIT> ) ; return true ; } } } return


<s> ComplexRendererFns selectAddrModeUnscaled64 ( MachineOperand & Root


<s> if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt ( <NUM_LIT> , <NUM_LIT> ) , LastElt ( <NUM_LIT> , <NUM_LIT> ) ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt =


<s> if ( ! Cand . BranchTargetBlock || FalseMBB || ! Cand . BranchBlock -> isSuccessor ( Cand . BranchTargetBlock ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Cand . BranchBlock -> succ_size ( ) != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } assert ( Cand . BranchBlock -> canFallThrough ( ) && <STR_LIT> ) ; MachineBasicBlock * Succ = ( * Cand . BranchBlock -> succ_begin ( ) == Cand . BranchTargetBlock ) ? * Cand . BranchBlock -> succ_rbegin ( ) : * Cand . BranchBlock -> succ_begin ( ) ; assert ( Succ &&


<s> case ALL_REGS : case FP_REGS : case FP_LO_REGS : return aarch64_vector_mode_p ( mode ) ? ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> : ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; case STACK_REG : return <NUM_LIT> ; case NO_REGS : return <NUM_LIT>


<s> bool sh_cfun_resbank_handler_p ( void ) { return ( ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) && ( lookup_attribute

( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) && TARGET_SH2A ) ;


<s> default_file_start ( ) ; emit_safe_across_calls (


<s> case TargetOpcode :: G_FPTOUI : case TargetOpcode :: G_FCMP : return true ; default : break ; } return hasFPConstraints ( MI , MRI


<s> switch ( RelTy ) { case ELF :: R_<ISA_LIT>_64_PC32 : return true ; case ELF :: R_<ISA_LIT>_64_32 : case ELF :: R_<ISA_LIT>_64_32S : case ELF :: R_<ISA_LIT>_64_64 : return false ; default : llvm_unreachable ( <STR_LIT> )


<s> if ( pType == llvm :: ELF :: R_MIPS_TLS_LDM ) return m_GotTLSLdmEntry ; if ( pType == llvm :: ELF :: R_MIPS_TLS_GD ) { GotEntryKey key ; key . m_GOTPage = m_CurrentGOTPart ; key . m_pInfo = pInfo ; key . m_Addend = <NUM_LIT> ; GotEntryMapType :: iterator it = m_GotTLSGdEntriesMap .


<s> MachineBasicBlock * BrBB = FuncInfo . MBB ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( isValueAvailable ( CI ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt


<s> MVT VecVT = <STR_LIT> ; if ( Subtarget . useAVX512Regs ( ) && ( is64Bit ( ) || ( CallConv == CallingConv :: <ISA_LIT>_VectorCall || CallConv == CallingConv :: Intel_OCL_BI ) ) ) VecVT = <STR_LIT> ; else if ( Subtarget . hasAVX ( ) ) VecVT = <STR_LIT> ; else if ( Subtarget . hasSSE2 ( ) ) VecVT = <STR_LIT> ; SmallVector < MVT , <NUM_LIT> > RegParmTypes ; MVT IntVT = is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; RegParmTypes . push_back ( IntVT ) ; if ( VecVT != <STR_LIT> ) RegParmTypes . push_back ( VecVT ) ; SmallVectorImpl < ForwardedRegister > & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; CCInfo . analyzeMustTailForwardedRegisters ( Forwards , RegParmTypes , CC_<ISA_LIT> ) ; if ( is64Bit ( ) && ! isWin64 ( ) && ! CCInfo . isAllocated


<s> unsigned RegNum ; StringRef Kind ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEDataVector ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ParseSuffix && Kind . empty ( ) ) return MatchOperand_NoMatch ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEDataVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , S , getContext ( ) ) ) ; return MatchOperand_Success


<s> if ( auto MemN = dyn_cast < MemSDNode > ( Op ) ) return MemN -> getMemoryVT ( ) ; switch ( OC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Op -> getValueType ( <NUM_LIT> ) ; } unsigned OriginalOC = OC ; if ( auto VVPOpc = getVVPOpcode ( OC ) ) OC = * VVPOpc ; if ( isVVPReductionOp ( OC ) ) return Op -> getOperand ( hasReductionStartParam ( OriginalOC ) ? <NUM_LIT> : <NUM_LIT> ) . getValueType ( ) ; switch ( OC ) { default : case <STR_LIT> : return Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; case <STR_LIT> : return Op -> getValueType ( <NUM_LIT> ) ; case <STR_LIT> : return Op -> getValueType ( <NUM_LIT> ) ; case <STR_LIT> : return Op -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT>


<s> SDValue NewSub = DAG . getNode ( <STR_LIT> , EFLAGS . getDebugLoc ( ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL


<s> if ( flag_omit_frame_pointer ) flag_omit_leaf_frame_pointer = false ; else if ( flag_omit_leaf_frame_pointer )


<s> PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; GU = T1 . getNode ( ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 ,


<s> if ( Level == BeforeLegalizeTypes ) return true ; if ( N -> getOpcode ( ) != <STR_LIT> ) return true ; if ( Subtarget -> isThumb1Only ( ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return true ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 -> getOpcode ( ) != <STR_LIT> && N1 -> getOpcode ( ) != <STR_LIT> && N1 -> getOpcode ( ) != <STR_LIT> && N1 -> getOpcode ( ) != <STR_LIT> ) return true ; if ( auto * Const = dyn_cast < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ) { if ( Const -> getAPIntValue ( ) . ult ( <NUM_LIT> ) ) return false ; if ( N1 -> getOpcode ( ) == <STR_LIT> && Const -> getAPIntValue ( ) . slt ( <NUM_LIT> ) && Const -> getAPIntValue ( ) . sgt ( -


<s> if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode

( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ;


<s> bool <ISA_LIT>XPLINKFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false


<s> switch ( mode ) { case QImode : fn = gen_store_conditionalqi ; break ; case HImode : fn = gen_store_conditionalhi ; break ; case SImode : fn = gen_store_conditionalsi ; break ; case DImode


<s> for ( unsigned c = <NUM_LIT> ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO


<s> SDValue <ISA_LIT>TargetLowering :: LowerFLT_ROUNDS_ ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const TargetFrameLowering & TFI = * TM . getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; EVT VT = Op . getValueType ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD ,

DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MRI = & F . getRegInfo ( ) ; TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; RCI . runOnMachineFunction ( F ) ; for ( auto & MBB


<s> unsigned Extra = ( VT . getSizeInBits ( ) - N0 . getValueType ( ) . getSizeInBits ( ) ) ; unsigned NewShlAmt = ShlAmt -> getZExtValue ( ) + Extra ; unsigned NewSraAmt = SraAmt -> getZExtValue ( ) + Extra ; EVT ShiftVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , SDLoc ( Inner ) , VT , Inner . getOperand ( <NUM_LIT> ) ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SDLoc ( Inner ) , VT , Ext , DAG . getConstant ( NewShlAmt , ShiftVT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , VT , Shl , DAG . getConstant


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode (

) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { if ( IsAliasOfSX ( SrcReg ) && IsAliasOfSX ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; } else { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; dbgs ( ) << <STR_LIT> << printReg ( SrcReg , TRI ) <<

<STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> ;


<s> rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx res = gen_reg_rtx ( XFmode ) ; rtx cst , cstln2 , cst1 ; rtx_insn * insn ; do_pending_stack_adjust ( ) ; cst = const_double_from_real_value ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ; cstln2 = force_reg ( XFmode , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; cst = force_reg ( XFmode ,


<s> PersonalityLocs = Locs ( ) ; HandlerDataLocs = Locs ( ) ; PersonalityIndexLocs = Locs


<s> static void sandboxBaseDisp ( const MCInst & Inst , const MCInstrInfo & II , unsigned BaseReg , MCStreamer & Out , const MCSubtargetInfo & STI ) { switch ( BaseReg ) { case


<s> if ( Predicate_i16immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { if ( isCN ) { if ( Predicate_i32immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } else { if ( isCN ) { if ( Predicate_i32immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { Opc = <STR_LIT> ; if ( isCN ) { if ( Predicate_i64immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( Predicate_i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } else { Opc = <STR_LIT> ; if ( isCN ) { if ( Predicate_i64immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( Predicate_i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } break ; } DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue Undef = SDValue ( CurDAG -> getTargetNode ( TargetInstrInfo :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; SDValue MemOp = CurDAG -> getMemOperand ( cast < MemSDNode


<s> if ( ( TheTriple . getArch ( ) == Triple :: armeb ) || ( TheTriple . getArch ( ) == Triple :: thumbeb ) ) IsLittleEndian = false ; Data64bitsDirective = nullptr


<s> PredicationCode = CC ; } } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } if ( Mnemonic . startswith ( <STR_LIT>


<s> static SDValue performXorCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; return performIntegerAbsCombine ( N ,


<s> void <ISA_LIT>SEInstrInfo :: expandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , bool isMicro<ISA_LIT> , bool FP64 ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg (


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ; return


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model


<s> assert ( TBB != nullptr ) ; if ( FBB == nullptr ) FBB = MBB . getFallThrough ( ) ; if ( TBB == FBB ) return false ; assert ( MBB . succ_size ( ) == <NUM_LIT> ) ; assert ( analyzeBranchCondCode . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CondCode = <STR_LIT> ( analyzeBranchCondCode [ <NUM_LIT> ] . getImm ( ) ) ; return true


<s> struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && MIPS_9BIT_OFFSET_P (


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16RegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16ZeroRegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; } if ( DecodeGPRMM16RegisterClass ( Inst , Base , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : if ( Offset == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( - <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case


<s> static MCStreamer * create<ISA_LIT>ELFStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr <

MCCodeEmitter > && Emitter , bool RelaxAll ) {


<s> gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode


<s> case TargetOpcode :: G_LSHR : { unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShiftReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ShiftTy = MRI . getType ( ShiftReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy . isVector ( ) ) return ; assert ( ! ShiftTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) != <NUM_LIT> || ShiftTy . getSizeInBits ( ) != <NUM_LIT> ) return ; auto * AmtMI = MRI . getVRegDef ( ShiftReg


<s> bool hasDSPR3 ( ) const { return HasDSPR3


<s> return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_sub ( vec_splat_u8 (

<NUM_LIT> ) , vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ) ) ) ) ;


<s> unsigned int val32 = val64 & <NUM_LIT> ; if ( val32 == ( val64 >> <NUM_LIT> ) ) { mode = SImode ; unsigned int val16 = val32 & <NUM_LIT> ; if ( val16 == ( val32 >> <NUM_LIT> ) ) { mode = HImode ; unsigned int val8 = val16 & <NUM_LIT> ; if ( val8 == ( val16 >> <NUM_LIT> ) ) mode = QImode ; } } HOST_WIDE_INT val = trunc_int_for_mode ( val64 , mode ) ; if ( IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } if ( ( val & <NUM_LIT> ) == <NUM_LIT> && IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } if ( aarch64_bitmask_imm ( val64 , mode )


<s> case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG


<s> case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , ReturnRegsCount ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSAlignGapSize ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) ,

NumAlignedDPRCS2Regs ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , IsSplitCSR ( false ) {


<s> bool hasResetReferenceBitsMultiple (


<s> if ( TM . getSubtargetImpl ( ) -> isDarwin ( ) ) return new TargetLoweringObjectFileMachO ( ) ; if ( TM . getSubtargetImpl ( ) -> isSVR4ABI ( ) ) return new <ISA_LIT>64LinuxTargetObjectFile


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target


<s> ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) ,


<s> paddb_s ( int8x8_t s , int8x8_t t ) { return __builtin_loongson_paddb_s ( s


<s> bool <STR_LIT> ( CallingConv :: ID CallingConv , bool is64Bit , bool IsVarArg , bool TailCallOpt ) { if ( IsVarArg ) return false ; switch ( CallingConv ) { default : return false


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; bool IsZeroV1 = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsZeroV2 = <STR_LIT> ( V2 . getNode ( ) ) ; if ( IsZeroV1 && IsZeroV2 ) return getZeroVector ( ResVT , Subtarget , DAG , dl ) ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG .


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Opc = Old -> getOpcode ( ) ; <STR_LIT> Pred = ( <STR_LIT> ) Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , Pred , PredReg ) ; } else { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressDarwin ( SDValue Op , SelectionDAG & DAG ) const { assert ( ! Subtarget -> isROPI ( ) && ! Subtarget -> isRWPI ( ) && <STR_LIT> ) ; assert ( ! Subtarget -> isPIP ( ) && <STR_LIT> ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) ++ NumMovwMovt ; unsigned Wrapper = isPositionIndependent ( ) ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result


<s> StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( DotStr , DotLoc , is<ISA_LIT>64


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( )


<s> SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal .


<s> Target & llvm :: getThe<ISA_LIT>32Target


<s> virtual const MandarinFrameLowering * getFrameLowering ( ) const { return &


<s> return MFIa -> shouldSignReturnAddress ( false ) == MFIb -> shouldSignReturnAddress ( false ) && MFIa -> shouldSignReturnAddress ( true ) == MFIb ->


<s> return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; unsigned NumDefs = MCID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( MCID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI .


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) { unsigned idx = Count - i - <NUM_LIT> ; unsigned Reg1 = CSI [ idx ] . getReg ( ) ; unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc


<s> Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred


<s> tree perm_type = build_vector_type ( ssizetype , nelts ) ; return gimple_build_assign ( f . lhs , VEC_PERM_EXPR , gimple_call_arg ( f . call , <NUM_LIT> ) , gimple_call_arg ( f . call , nargs - <NUM_LIT> ) , vec_perm_indices_to_tree ( perm_type ,


<s> unsigned getATRegNum ( ) const { return ATReg


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry ( )


<s> void <ISA_LIT>DynAllocaExpander :: computeLowerings ( MachineFunction & MF , LoweringMap & Lowerings ) { DenseMap < MachineBasicBlock * , int64_t > OutOffset ; for ( MachineBasicBlock & MBB : MF ) OutOffset [ & MBB ] = INT32_MAX ; ReversePostOrderTraversal < MachineFunction * > RPO ( & MF ) ; for ( MachineBasicBlock * MBB : RPO ) { int64_t Offset = - <NUM_LIT> ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) Offset = std :: max ( Offset , OutOffset [ Pred ] ) ; if ( Offset == - <NUM_LIT> ) Offset = INT32_MAX ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { int64_t Amount = getDynAllocaAmount ( & MI , MRI ) ; Lowering L = getLowering ( Offset , Amount ) ; Lowerings [ & MI ] = L ; switch ( L ) { case Sub : Offset += Amount ; break ; case


<s> if ( MO . isDef ( ) ) RegDefs . insert ( Reg ) ; if ( MO . isUse ( ) ) { if ( MO . isImplicit ( ) && MI -> getOpcode ( ) == <STR_LIT> ) continue ; RegUses . insert ( Reg )


<s> if ( TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM ) return SYMBOL_PC_RELATIVE ; if ( mips_rtx_constant_in_small_data_p ( get_pool_mode ( x ) ) ) return SYMBOL_GP_RELATIVE ; } if ( TARGET_GPOPT && SYMBOL_REF_SMALL_P ( x ) && ! SYMBOL_REF_WEAK ( x ) ) return SYMBOL_GP_RELATIVE ; if ( TARGET_ABICALLS_PIC2 && ! ( TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p ( x ) ) ) { if ( mips_global_symbol_p ( x ) ) return SYMBOL_GOT_DISP ; return SYMBOL_GOT_PAGE_OFST ; } return SYMBOL_ABSOLUTE


<s> for ( MachineBasicBlock :: iterator MI = MFI -> begin ( ) , ME = MFI -> end ( ) ; MI != ME ; ) { Modified |= runOnInstruction ( MI ++ ) ; } } for ( std :: set < MachineInstr * > :: iterator I = DeadInstr . begin ( ) , E = DeadInstr . end ( ) ; I != E ; ++ I ) { ( * I ) -> eraseFromParent ( ) ; } return Modified


<s> static bool is_cracked_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || type == TYPE_DELAYED_CR || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT &&

get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ;


<s> BOOL DllMain ( HINSTANCE libraryId __attribute__ ( ( __unused__ ) ) , DWORD reason , void * hModule ) { switch ( reason ) { case DLL_NLM_STARTUP : allocRTag = AllocateResourceTag ( hModule , <STR_LIT> , AllocSignature ) ; return allocRTag != NULL ; case DLL_NLM_SHUTDOWN : break ; } return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( *


<s> mips_get_arg_info ( & info , get_cumulative_args ( cum ) , arg . mode , arg . type ,


<s> unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister


<s> bool isMemPCRelImm12 ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . BaseRegNum != <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & , const MCTargetOptions & Options ) { IsLittleEndian = false ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI


<s> return ( isTargetELF ( ) && ! isTargetNaCl ( ) ) || TM . getRelocationModel ( )


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI


<s> if ( ( i & ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) return TRUE ; lowbit = ( ffs ( ( int ) i ) - <NUM_LIT> ) & ~ <NUM_LIT> ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) << lowbit ) ) == <NUM_LIT> ) return TRUE ; else if ( lowbit <= <NUM_LIT> && ( ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> ) ) return TRUE ; return FALSE


<s> static SDValue LowerInterruptReturn ( SmallVectorImpl < SDValue > & RetOps , SDLoc DL , SelectionDAG & DAG ) { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; StringRef IntKind = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; int64_t LROffset ; if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT> <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_EXIT ( const MachineInstr & MI ) { EmitSled ( MI , SledKind


<s> static inline unsigned getAM2IdxMode (


<s> Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if (


<s> auto * And1C = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! And1C ) return false ; APInt MaskVal = And1C -> getAPIntValue ( ) ; unsigned MaskLZ = MaskVal . countLeadingZeros ( ) ; if ( ! MaskLZ || ( VT == <STR_LIT> && MaskLZ == <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> && MaskLZ >= <NUM_LIT> ) { MaskLZ -= <NUM_LIT> ; MaskVal = MaskVal . trunc ( <NUM_LIT> ) ; } SDValue And0 = And -> getOperand ( <NUM_LIT> ) ; APInt HighZeros = APInt :: getHighBitsSet ( MaskVal . getBitWidth ( ) , MaskLZ ) ; APInt NegMaskVal = MaskVal | HighZeros ; unsigned MinWidth = NegMaskVal


<s> unsigned Scale = <NUM_LIT> ; bool HasImmOffset = false ; bool HasShift = false ; bool HasOffReg = true ; bool isLdStMul = false ; unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Entry . WideOpc != <STR_LIT> ) return false ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul =


<s> int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = RoundUpToAlignment ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset +=


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> else return create<ISA_LIT>MachObjectWriter ( MachO :: CPU_TYPE_ARM64

, MachO :: CPU_SUBTYPE_ARM64_ALL , false ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( getTheARM64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; TargetRegistry :: RegisterTarget ( getTheARM64_32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; RegisterTarget < Triple :: aarch64 , true > Z ( getThe<ISA_LIT>leTarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: aarch64_be , true > W ( getThe<ISA_LIT>beTarget ( ) , <STR_LIT>


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MF . getFrameInfo ( ) . setFrameAddressIsTaken ( true ) ; SDLoc DL ( Op ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) , DL ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) { offset_rtx = gen_rtx_REG ( Pmode , FIXED_SCRATCH ) ; emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx =


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering (


<s> if ( BitSize == <NUM_LIT> ) return TTI :: TCC_Free ; if ( BitSize > <NUM_LIT> ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : case <STR_LIT>


<s> if ( Subtarget . hasVPOPCNTDQ ( ) ) { if ( VT == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL ,


<s> std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Tile } ; Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; if ( Bitcast -> hasOneUse ( ) ) return ; Value * Vec = Builder . CreateLoad ( Bitcast -> getType ( ) , ST ->


<s> if ( State . isVarArg ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; <STR_LIT> ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , <NUM_LIT> , <NUM_LIT> , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <=


<s> static HOST_WIDE_INT ix86_GOT_alias_set ( void ) { static HOST_WIDE_INT set = - <NUM_LIT> ; if ( set == - <NUM_LIT> ) set =


<s> case <STR_LIT> : case <STR_LIT> : { if ( BC0 . getOperand ( <NUM_LIT> ) != BC1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue BitOp = DAG . getNode ( Opc , DL , BCVT , BC0 . getOperand ( <NUM_LIT> ) , BC1 . getOperand ( <NUM_LIT> ) ) ; SDValue Shift = DAG . getNode ( BCOpc , DL , BCVT , BitOp , BC0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( VT , Shift ) ; } } return SDValue


<s> if ( canDefBePartOfLOH ( MI ) ) { const MachineOperand & Def = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Def . isReg ( ) && Def . isDef ( ) && <STR_LIT> ) ; assert ( Op . isReg ( ) && Op . isUse ( ) && <STR_LIT> ) ; int DefIdx = mapRegToGPRIndex ( Def . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( Op . getReg ( ) ) ; if ( DefIdx >= <NUM_LIT> && OpIdx >= <NUM_LIT> && handleMiddleInst ( MI , LOHInfos [ DefIdx ] , LOHInfos [ OpIdx ] ) ) continue ; } break ; case <STR_LIT>


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseCCSelect (


<s> case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ; if ( Rs ) { assert ( <STR_LIT> ( MO2 . getImm (


<s> unsigned getMaxNumElements ( ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return VF . getFixedValue (


<s> StackOffset <ISA_LIT>FrameLowering :: resolveFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg , bool PreferFP , bool ForSimm ) const { const auto & MFI = MF . getFrameInfo ( ) ; int64_t ObjectOffset = MFI . getObjectOffset ( FI ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool isSVE = MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ; return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed , isSVE , FrameReg


<s> bool <ISA_LIT>_64GNULDBackend :: initRelocator ( ) { if ( m_pRelocator == NULL ) { m_pRelocator = new <ISA_LIT>_64Relocator ( * this , config ( ) ) ; } return true


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue CMovOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue CMovOp1 = N0 . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( CMovOp0 . getNode ( ) ) || ! isa < ConstantSDNode > ( CMovOp1 . getNode ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( N0 . getValueType ( ) != VT ) { CMovOp0 = DAG . getNode ( <STR_LIT> , DL , VT , CMovOp0 ) ; CMovOp1 = DAG . getNode ( <STR_LIT> , DL , VT , CMovOp1 ) ; } CMovOp0 = DAG . getNode ( <STR_LIT> , DL , VT


<s> MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , Alignment ) ; else OS . emitValueToAlignment ( Alignment , <NUM_LIT> , <NUM_LIT> , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF


<s> return __builtin_loongson_pcmpgtw_u ( s


<s> for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << Extract -> getConstantOperandVal ( <NUM_LIT> ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( SrcVT ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl

, InputVector , StackPtr , MachinePointerInfo ( ) ) ;


<s> if ( TARGET_64BIT && mode == SImode && mode_rep == DImode ) return SIGN_EXTEND ; return


<s> void setSExtIdx ( int V ) { SExtIdx =


<s> targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; targetm . resolve_overloaded_builtin = aarch64_resolve_overloaded_builtin ; targetm . check_builtin_call


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV

-> hasExternalWeakLinkage ( ) ) return <STR_LIT> ;


<s> bool useReciprocalEst ( ) const { return UseReciprocalEst


<s> if ( IsPredicateRegion ) return <STR_LIT> . hasSubClassEq ( c ) ; else return <STR_LIT> . hasSubClassEq ( c ) || <STR_LIT> . hasSubClassEq ( c ) || <STR_LIT>

. hasSubClassEq ( c ) || <STR_LIT> . hasSubClassEq ( c ) ;


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; break ; case


<s> if ( Op . isReg ( ) ) OS << <STR_LIT> << getRegisterName ( Op . getReg ( ) ) ; else if ( Op . isImm ( ) ) OS << formatHex ( Op .


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( UndefLower && isSequentialOrUndefInRange ( Mask , HalfNumElts , HalfNumElts , <NUM_LIT> ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; } int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( HalfNumElts ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) ) return SDValue ( ) ; assert ( HalfMask . size ( ) == HalfNumElts && <STR_LIT> ) ; unsigned NumLowerHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; unsigned NumUpperHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; assert ( NumLowerHalves + NumUpperHalves <= <NUM_LIT> && <STR_LIT> ) ; unsigned EltWidth = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! UndefLower ) { if ( NumUpperHalves == <NUM_LIT> ) return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) ) { if ( EltWidth == <NUM_LIT> && NumLowerHalves && HalfVT . is128BitVector ( ) && ! is128BitUnpackShuffleMask ( HalfMask ) && ( ! isSingleSHUFPSMask ( HalfMask ) || Subtarget . hasFastVariableShuffle ( ) ) ) return SDValue ( ) ; if ( EltWidth == <NUM_LIT> && V2 . isUndef ( ) ) return SDValue ( ) ; } if ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) return SDValue ( ) ; return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; } assert ( NumUpperHalves == <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) && EltWidth == <NUM_LIT> )


<s> bool <ISA_LIT>BaseRegisterInfo :: cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> __arm_srshrl ( int64_t value , const


<s> static inline unsigned int rx_round_up ( unsigned int value , unsigned int alignment ) { alignment -=


<s> SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue Mtvsrz = DAG . getNode ( <STR_LIT> , dl , VT , V2 ) ; unsigned BytesInEachElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned InsertAtElement = C -> getZExtValue (


<s> Value * <ISA_LIT>IREmitter :: visitVMINNM ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicRMWInIR ( AI


<s> RS . forward ( MachineBasicBlock :: iterator ( G -> getStart ( ) ) ) ; unsigned RegClassID = G -> getStart ( ) -> getDesc ( ) . OpInfo [ <NUM_LIT> ] . RegClass ; BitVector AvailableRegs = RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( MachineBasicBlock :: iterator I = G -> getStart ( ) , E = G -> getEnd ( ) ; I != E ; ++ I ) { RS . forward ( I ) ; AvailableRegs &= RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto J : I -> operands ( ) ) { if ( J . isRegMask ( ) ) AvailableRegs . clearBitsNotInMask ( J . getRegMask ( ) ) ; if ( J . isReg ( ) && J . isDef ( ) && AvailableRegs [ J


<s> else if ( ptr_mode == DImode ) return <NUM_LIT> * <NUM_LIT> ; else if ( ISA_HAS_LOAD_DELAY ) return <NUM_LIT> * <NUM_LIT> ; else return <NUM_LIT> * <NUM_LIT>