<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) i ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( N


<s> if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { Info = <STR_LIT> <STR_LIT> ; return true ; } return false


<s> } std :: vector < MachineInstr * > NewMIs ; if ( isPre ) { if ( isLoad ) MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; NewMIs . push_back ( MemMI ) ; NewMIs . push_back ( UpdateMI ) ; } else { if ( isLoad ) MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; if ( WB . isDead ( ) ) UpdateMI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; NewMIs . push_back ( UpdateMI ) ; NewMIs . push_back ( MemMI ) ; } if ( LV ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { unsigned Reg = MO . getReg ( ) ; LiveVariables :: VarInfo & VI = LV -> getVarInfo ( Reg ) ; if ( MO . isDef ( )


<s> processFunctionBeforeFrameFinalized ( MachineFunction &


<s> static __inline qword si_shli ( qword a , unsigned int b ) { vec_uint4 bv ; vec_uint4 mask ; bv = vec_splat ( ( vec_uint4 ) ( si_from_uint ( b


<s> return __builtin_mve_vhsubq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __b ,


<s> return ( __mmask8 ) __builtin_ia32_ucmpw128_mask ( ( __v8hi ) __X , (


<s> int Offset = MFI -> getObjectOffset ( FI ) - TFI . getOffsetOfLocalArea ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { Offset += SlotSize ; } else { unsigned Align = MFI -> getObjectAlignment (


<s> if ( ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) ) return false ; if ( LocVT == <STR_LIT> && ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) ) return false ; return true


<s> b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int ) vec_cmpgt ( b , float_exp_mask ) ; return ( ( __m128 ) vec_or ( c ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameInfo (

TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) {


<s> static bool aarch64_hard_regno_call_part_clobbered ( unsigned int regno ,


<s> unsigned convertBit = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Zeroable . size ( ) ; i < e

; i ++ ) convertBit |= ! ( Zeroable [ i ] ) << i ;


<s> bool isMemRegReg ( ) const { return Kind ==


<s> SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = get<ISA_LIT>SubSuperRegister ( RegNo , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> static MCDisassembler * create<ISA_LIT>64elDisassembler ( const Target & T


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>SEInstrInfo


<s> <ISA_LIT>MCInstLower Lower ( Mang , MF -> getContext ( ) ,


<s> } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = <NUM_LIT> - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = <NUM_LIT> - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return


<s> return StringRef ( PSBHint . Data , PSBHint . Length


<s> RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . DAG . getMachineFunction ( ) , CLI . CallConv ) ; assert ( Mask &&


<s> Value * <ISA_LIT>IREmitter :: visitPINSRW ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> insn_length = get_attr_length ( insn ) ; long_jump_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; r5_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code ) { case EQ


<s> moxie_compute_frame ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> size_for_adjusting_sp ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( cfun -> machine -> size_for_adjusting_sp > <NUM_LIT> ) { int i = cfun -> machine -> size_for_adjusting_sp ; while ( ( i >= <NUM_LIT> ) && ( i <= <NUM_LIT> ) ) { insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; i -= <NUM_LIT> ; } if ( i <= <NUM_LIT> ) { insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( i ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { rtx reg = gen_rtx_REG ( SImode , MOXIE_R12 ) ; insn = emit_move_insn ( reg , GEN_INT ( i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx ,


<s> const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; auto ShlMemOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Basereg , <NUM_LIT> , <NUM_LIT> , SMLoc { } , SMLoc { } , <NUM_LIT> ) ; ShlInst . setOpcode ( <STR_LIT> ) ; ShlMemOp -> addMemOperands ( ShlInst , <NUM_LIT> ) ; ShlInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; FenceInst . setOpcode ( <STR_LIT> ) ; Out . emitInstruction ( ShlInst , getSTI ( ) ) ; Out . emitInstruction ( FenceInst , getSTI ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool isTargetELF ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: ELF || TargetTriple .


<s> default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back (


<s> maskcmp = true ; cmp_mode = nbits > <NUM_LIT> ? int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest ; } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode ) { x = force_reg ( cmp_ops_mode


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> const DataLayout & DL = MF . getDataLayout ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const Function * F = MF . getFunction ( ) ; SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { auto Flags = OrigArg . Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( OrigArg . Ty ) ; Flags . setOrigAlign ( OriginalAlignment ) ; SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs .


<s> return SelectAddrModeIndexed ( N , <NUM_LIT>


<s> assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> ) { SDValue Extend = DAG . getNode ( <STR_LIT> , DL , VT , In ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Extend , DAG . getConstant ( VT . getScalarSizeInBits ( ) - <NUM_LIT> , DL , VT ) ) ; } MVT ExtVT = VT ; if ( ! Subtarget . hasBWI ( ) ) { if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) return SplitAndExtendv16i1 ( <STR_LIT> , VT , In , DL , DAG ) ; ExtVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; } MVT WideVT = ExtVT ; if ( ! ExtVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { NumElts *= <NUM_LIT> / ExtVT . getSizeInBits ( ) ; InVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , InVT , DAG . getUNDEF ( InVT ) , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; WideVT = <STR_LIT> ( ExtVT . getVectorElementType ( ) , NumElts ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , WideVT ) ; SDValue Zero = getZeroVector ( WideVT , Subtarget , DAG , DL ) ; SDValue SelectedVal = DAG . getSelect ( DL , WideVT , In , One , Zero ) ; if ( VT != ExtVT ) { WideVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SelectedVal = DAG . getNode ( <STR_LIT> , DL , WideVT , SelectedVal ) ; } if ( WideVT != VT ) SelectedVal = DAG . getNode ( <STR_LIT> , DL , VT , SelectedVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return SelectedVal


<s> for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { char V = isNegatibleForFree ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; if ( V == <NUM_LIT> ) NewOps [ i ] = getNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; } bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op


<s> void addCOP2AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getCOP2Reg


<s> if ( TheTriple . isOSBinFormatMachO ( ) && TheTriple . getArch ( ) == Triple :: x86_64 ) return create<ISA_LIT>_64MachORelocationInfo ( Ctx ) ; else if ( TheTriple . isOSBinFormatELF ( ) ) return create<ISA_LIT>_64ELFRelocationInfo (


<s> switch ( getKind ( ) ) { case MEK_None : case MEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case MEK_CALL_HI16 : case MEK_CALL_LO16 : case MEK_DTPREL_HI : case MEK_DTPREL_LO : case MEK_GOT : case MEK_GOT_CALL : case MEK_GOT_DISP : case MEK_GOT_HI16 : case MEK_GOT_LO16 : case MEK_GOT_OFST : case MEK_GOT_PAGE : case MEK_GPREL : case MEK_HI : case MEK_HIGHER : case MEK_HIGHEST : case MEK_LO : case MEK_NEG : case MEK_PCREL_HI16 : case MEK_PCREL_LO16 : case MEK_TLSLDM : if ( const <ISA_LIT>MCExpr * E = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) E -> fixELFSymbolsInTLSFixups ( Asm ) ; break ; case MEK_GOTTPREL : case MEK_TLSGD : case MEK_TPREL_HI : case MEK_TPREL_LO


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm16 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; assert ( FIST . getNode ( ) && <STR_LIT> ) ; return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false


<s> bool isToken ( ) const { return Kind ==


<s> return new <ISA_LIT>RedundantCopyElimination (


<s> int _U_Qfle ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_EQ | QCMP_LT


<s> EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData =


<s> vtrnq_u16 ( uint16x8_t a , uint16x8_t b ) { return ( uint16x8x2_t ) { vtrn1q_u16 ( a , b ) , vtrn2q_u16 ( a


<s> void <ISA_LIT>16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const char * <ISA_LIT>16HelperFunction = <NUM_LIT> ; bool Need<ISA_LIT>16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { S -> getSymbol ( ) , <STR_LIT> } ; if ( std :: binary_search ( <ISA_LIT>16IntrinsicHelper , array_endof ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ) { const <ISA_LIT>16IntrinsicHelperType * h = ( std :: find ( <ISA_LIT>16IntrinsicHelper , array_endof ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ) ; <ISA_LIT>16HelperFunction = h -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI


<s> if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo


<s> static void init_idents ( void ) { if ( small_ident1 == <NUM_LIT> ) { small_ident1 = get_identifier (


<s> return m16_check_op ( op , <NUM_LIT> ,


<s> NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; } MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . add ( Reg0Op ) . add ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm (


<s> else if ( idx < ( int ) NumElems ) Mask [ i ] = idx + NumElems ; else Mask [ i ] = idx


<s> return ( __m128 ) __builtin_ia32_cmpltps ( ( __v4sf ) __A ,


<s> MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || Subtarget . hasBWI ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; if ( InVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ; SDValue One = DAG . getConstant ( APInt ( ExtVT . getScalarSizeInBits ( ) , <NUM_LIT> ) , DL , ExtVT ) ; SDValue Zero = DAG . getConstant ( APInt :: getNullValue ( ExtVT . getScalarSizeInBits ( ) ) , DL , ExtVT ) ; SDValue SelectedVal = DAG . getSelect ( DL , ExtVT , In , One , Zero ) ; if ( VT == ExtVT )


<s> const ConstantSDNode * RotConstant = dyn_cast < ConstantSDNode > ( V ) ; assert ( RotConstant && <STR_LIT>


<s> static void rbt_right_rotate ( struct rbt_strings * t , struct rbt_string_node * node ) { struct rbt_string_node * left = node -> left ; assert ( left ) ; node -> left = left -> right ; if ( left -> right != t -> rbt_nil ) left -> right -> par = node ; left -> par = node -> par ; if ( node -> par == t ->


<s> const MachineOperand & DstMO = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; unsigned DstReg = DstMO . getReg ( ) ; unsigned SrcReg = SrcMO . getReg ( ) ; auto getRegClass = [ & ] ( unsigned Reg ) { return TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : TRI . getMinimalPhysRegClass ( Reg ) ; } ; if ( DstMO . getSubReg ( ) == <NUM_LIT> && SrcMO . getSubReg ( ) == <NUM_LIT> ) { assert ( TRI . getRegSizeInBits ( * getRegClass ( DstReg ) ) == TRI . getRegSizeInBits ( * getRegClass ( SrcReg ) ) && <STR_LIT> ) ; if ( IsSpill ) storeRegToStackSlot ( MBB , InsertPt , SrcReg , SrcMO . isKill ( ) , FrameIndex , getRegClass ( SrcReg ) , & TRI ) ; else loadRegFromStackSlot ( MBB , InsertPt , DstReg , FrameIndex , getRegClass ( DstReg ) , & TRI ) ; return & * -- InsertPt ; } if ( IsSpill && DstMO . isUndef ( ) && TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { assert ( SrcMO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * SpillRC ; unsigned SpillSubreg ; switch ( DstMO . getSubReg ( ) ) { default : SpillRC = nullptr ; break ; case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> . contains ( SrcReg ) ) { SpillRC = & <STR_LIT> ; SpillSubreg = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { SpillRC = & <STR_LIT> ; SpillSubreg = <STR_LIT> ; } else SpillRC = nullptr ; break ; case <STR_LIT> : if ( <STR_LIT> . contains ( SrcReg ) ) { SpillRC = & <STR_LIT> ; SpillSubreg = <STR_LIT> ; } else SpillRC = nullptr ; break ; } if ( SpillRC ) if ( unsigned WidenedSrcReg = TRI . getMatchingSuperReg ( SrcReg , SpillSubreg , SpillRC ) ) { storeRegToStackSlot ( MBB , InsertPt , WidenedSrcReg , SrcMO . isKill ( ) , FrameIndex , SpillRC , & TRI ) ; return & * -- InsertPt ; } } if ( IsFill && SrcMO . getSubReg ( ) == <NUM_LIT> && DstMO . isUndef ( ) ) { const TargetRegisterClass * FillRC ; switch ( DstMO . getSubReg ( ) ) { default : FillRC = nullptr ; break ; case <STR_LIT> : FillRC = & <STR_LIT> ; break ; case <STR_LIT> : FillRC = & <STR_LIT> ; break ; case <STR_LIT> : FillRC = & <STR_LIT> ; break ; } if ( FillRC


<s> bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , DestAM ) ; assert ( RV && <STR_LIT> ) ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; DestAM . Disp += Size ; SrcAM . Disp += Size ; } return


<s> DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; const uint64_t MaxSubImm = <NUM_LIT> ; if ( Offset <= MaxSubImm ) { return <NUM_LIT> ; } else { unsigned OffsetReg = <STR_LIT> ; unsigned OffsetQ1 = ( unsigned ) ( Offset & <NUM_LIT> ) ; unsigned OffsetQ2 = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ; unsigned OffsetQ3 = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ; unsigned OffsetQ4 = ( unsigned ) ( ( Offset &


<s> virtual const <ISA_LIT>FrameLowering * getFrameLowering ( ) const { return &


<s> MVT SVT = Vec . getSimpleValueType ( ) . getScalarType ( ) ; MVT VT = <STR_LIT> ( SVT , WideNumElts ) ; return widenSubVector ( VT , Vec , ZeroNewElements , Subtarget , DAG


<s> MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == <NUM_LIT> ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == <NUM_LIT> || SlotSize == <NUM_LIT> ) ; unsigned RegA = ( SlotSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; case Sub : assert ( Amount > <NUM_LIT> ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } break ; } unsigned AmountReg = MI -> getOperand ( <NUM_LIT>


<s> bool isShifterImm ( ) const { return Kind == k_ShifterImmediate


<s> EVT MemVT = StoreNode -> getMemoryVT ( ) ; if ( VT . isVector ( ) ) { if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerFixedLengthVectorStoreToSVE ( Op , DAG ) ; unsigned AS = StoreNode -> getAddressSpace ( ) ; Align Alignment = StoreNode -> getAlign ( ) ; if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment . value ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo


<s> unsigned Opc = LoadMI . getOpcode ( ) ; unsigned UserOpc = UserMI . getOpcode ( ) ; unsigned RegSize = MF . getRegInfo ( ) . getRegClass ( LoadMI . getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && RegSize > <NUM_LIT> ) { switch ( UserOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return


<s> if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && XEXP ( x , <NUM_LIT> ) != frame_pointer_rtx && XEXP ( x , <NUM_LIT> ) != frame_pointer_rtx && thumb1_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && ( thumb1_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) || ( ! strict_p && will_be_in_index_register ( XEXP ( x , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( ( thumb1_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && thumb_legitimate_offset_p ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) == STACK_POINTER_REGNUM && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) + GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == FRAME_POINTER_REGNUM || REGNO ( XEXP ( x , <NUM_LIT> ) ) == ARG_POINTER_REGNUM || ( REGNO ( XEXP ( x , <NUM_LIT> ) ) >= FIRST_VIRTUAL_REGISTER && REGNO ( XEXP ( x , <NUM_LIT> ) ) <= LAST_VIRTUAL_POINTER_REGISTER ) ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_SIZE ( mode ) == <NUM_LIT> && GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> return dyn_cast_or_null < GlobalValue > (


<s> BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addMBB ( MF . getExitBlock ( ) ) ; MF . getExitBlock ( ) -> addPredecessor ( & MBB ) ; unsigned StackIncrement = SlotSize ; unsigned RetOpc = MI -> getOpcode ( ) ; if ( RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; StackIncrement += MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } unsigned AddOpc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * mi = BuildMI ( MBB , MI , DL , TII . get ( AddOpc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackIncrement ) ; mi -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; unsigned JmpOpc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , DL , TII


<s> MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ; verify ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BlockInfo . clear


<s> static AsmPrinter * create<ISA_LIT>AsmPrinterPass ( formatted_raw_ostream & o , TargetMachine & tm , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * tai ) { const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget


<s> rtx labelno = GEN_INT ( pic_labelno ++ ) ; rtx label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; rtx sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_DESCSEQ ) , gen_rtx_CONST ( VOIDmode , label ) , GEN_INT ( ! TARGET_ARM ) ) , UNSPEC_TLS ) ; rtx reg0 = load_tls_operand ( sum , gen_rtx_REG ( SImode , R0_REGNUM ) ) ; emit_insn ( gen_tlscall ( x , labelno ) ) ; if ( ! reg ) reg = gen_reg_rtx ( SImode ) ; else gcc_assert ( REGNO ( reg ) != R0_REGNUM ) ; emit_move_insn ( reg ,


<s> bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . add ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState


<s> static bool sh_ms_bitfield_layout_p ( tree record_type


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction


<s> bool isMovKSymbolG0 ( ) const { return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G0_NC , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC , <ISA_LIT>MCExpr ::


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { OutStreamer . EmitLabel (


<s> OperandMatchResultTy parseGR32 ( SmallVectorImpl < MCParsedAsmOperand * >


<s> cvtStExtTWriteBackReg ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands


<s> } else if ( TREE_CODE ( TREE_VALUE ( args ) ) != INTEGER_CST ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs =


<s> static unsigned getLoadRegOpcode ( Register DestReg , const TargetRegisterClass * RC , bool IsStackAligned , const <ISA_LIT>Subtarget & STI ) { return getLoadStoreRegOpcode ( DestReg , RC , IsStackAligned , STI , true


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( VT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , VT . getVectorNumElements ( ) ) ) ; if ( InVec . getOpcode ( ) == <STR_LIT> && InVec . hasOneUse ( ) && InVec . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; if ( IdxVal == <NUM_LIT> && InVec . hasOneUse ( ) ) { unsigned InOpcode = InVec . getOpcode ( ) ; if ( VT == <STR_LIT> && InVec . getValueType ( ) == <STR_LIT> ) { if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } } if ( ( InOpcode == <STR_LIT> || InOpcode == <STR_LIT> || InOpcode == <STR_LIT> ) && VT . is128BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . is128BitVector ( ) ) { unsigned ExtOp = InOpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ExtOp , SDLoc ( N ) , VT , InVec . getOperand (


<s> LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) . getReg ( <NUM_LIT> ) ; Register OffsetReg = MRI .


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ; return


<s> case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , true ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , false ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , true ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , false ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG


<s> EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( LD -> getAlignment ( ) >= MemVT . getSizeInBits ( ) / <NUM_LIT> ) || ( ( MemVT != <STR_LIT> ) && ( MemVT != <STR_LIT> ) ) ) return SDValue ( ) ; bool IsLittle = Subtarget -> isLittle ( ) ; EVT VT = Op . getValueType ( ) ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; SDValue Chain = LD -> getChain ( ) , Undef = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) ; if ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) { SDValue LDL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return createLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = createLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT> ) || ( ExtType == <STR_LIT> ) ) return LWR ; assert ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) ; SDLoc DL ( LD ) ; SDValue Const32 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue SLL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LWR , Const32 ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SLL , Const32 ) ; SDValue Ops [ ] = { SRL , LWR . getValue ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand (


<s> MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( )


<s> if ( IsTailCall ) ++ NumTailCalls ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ; SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ; if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal , DL ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , DL , Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ; std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue Arg = OutVals [ i ] ; CCValAssign & VA = ArgLocs [ i ] ; MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; assert ( ! IsTailCall && <STR_LIT> ) ; passByValArg ( Chain , DL , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , <ISA_LIT>CCInfo , * ByValArg , Flags , Subtarget . isLittle ( ) ) ; ++ ByValArg ; continue ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . isRegLoc ( ) ) { if ( ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) ) Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; else if ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; unsigned LocRegLo = VA . getLocReg ( ) ; unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; continue ; } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || isTargetAndroid ( ) ) &&

! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> break ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( CSStackSizeInc % <NUM_LIT> == <NUM_LIT> ) ; int64_t CSStackSizeIncImm = CSStackSizeInc ; if ( ! NewIsUnscaled ) CSStackSizeIncImm /= <NUM_LIT> ; MIB . addImm ( CSStackSizeIncImm ) ; MIB . setMIFlags ( MBBI -> getFlags ( ) ) ; MIB . setMemRefs ( MBBI -> memoperands


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case E_DImode : return gen_load_pairdi ( reg1 , mem1 , reg2 , mem2 ) ; case E_DFmode : return gen_load_pairdf ( reg1 , mem1 , reg2


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( )


<s> if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT> , Flag ) ; if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment


<s> } } else if ( AreSequentialLoads ( Ld1 , Ld0 , PMul0 -> VecLd ) && AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; R . AddMulPair ( PMul1 , PMul0 , true ) ; return true ; } return false ; } ; MulCandList & Muls = R . getMuls ( ) ; const unsigned Elems = Muls . size ( ) ; for ( unsigned i = <NUM_LIT> ; i < Elems ; ++ i ) { MulCandidate * PMul0 = static_cast < MulCandidate * > ( Muls [ i ] . get ( ) ) ; if ( PMul0 -> Paired ) continue ; for ( unsigned j = <NUM_LIT> ; j < Elems ; ++ j ) { if ( i == j ) continue ; MulCandidate * PMul1 = static_cast < MulCandidate * > ( Muls [ j ] . get ( ) ) ; if ( PMul1 -> Paired ) continue ; const Instruction * Mul0 = PMul0 -> Root ; const Instruction * Mul1 = PMul1 -> Root ; if ( Mul0 == Mul1


<s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress


<s> if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr ,


<s> SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( NumArgs ) ; ArgRegs . reserve ( NumArgs ) ; ArgVTs . reserve ( NumArgs ) ; ArgFlags . reserve ( NumArgs ) ; for ( unsigned i = <NUM_LIT> , ie = NumArgs ; i != ie ; ++ i ) { <STR_LIT> Flags = CLI . OutFlags [ i ] ; if ( Flags . isInReg ( ) || Flags . isSRet ( ) || Flags . isNest ( ) || Flags . isByVal ( ) ) return false ; Value * ArgValue = CLI . OutVals [ i ] ; Type * ArgTy = ArgValue -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) ) return false ; unsigned Arg = getRegForValue ( ArgValue ) ; if ( Arg == <NUM_LIT> ) return false ; Args . push_back ( ArgValue ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT>


<s> poly8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr :: VK_ABS_G1_NC , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC } ; return isMovWSymbol (


<s> if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE ) return Error ( Loc , <STR_LIT> ) ; int64_t Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( St == <STR_LIT> || St == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( St == <STR_LIT> || St == <STR_LIT> ) && Imm > <NUM_LIT> ) ) return Error ( Loc , <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) St = <STR_LIT> ; if ( Imm == <NUM_LIT> ) Imm = <NUM_LIT> ; Amount =


<s> static SDValue get1bitLaneShuffleImm8ForMask ( ArrayRef < int > Mask , SDLoc DL , SelectionDAG & DAG ) { assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; unsigned Imm =


hasFnAttribute ( <STR_LIT> ) ) return false ;


<s> MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; if ( I . shouldUpdateCallSiteInfo ( ) ) I . getMF ( ) -> eraseCallSiteInfo ( & I ) ; I . eraseFromParent ( ) ; return Copy


<s> if ( Val >= <NUM_LIT> ) break ; } if ( Val >= ( int ) NumElts ) Val -= NumElts - NumLaneElts ; assert ( Val - i > <NUM_LIT> && <STR_LIT> ) ; return ( Val - i ) *


<s> assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ; } } ; if ( BBPrevious -> isSuccessor ( BB ) ) FixFallthrough ( BBPrevious , BB ) ; if ( AfterNext && After -> isSuccessor ( AfterNext ) ) FixFallthrough ( After , AfterNext ) ; if ( BBNext && BB -> isSuccessor ( BBNext ) ) FixFallthrough ( BB , BBNext ) ; BBUtils -> adjustBBOffsetsAfter ( After


<s> Triple T ( STI . getTargetTriple ( ) ) ; Pic = ( MCA . getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) ? true : false ; uint64_t Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_3 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32R6 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_2 ; else EFlags |= ELF :: EF_MIPS_ARCH_1 ; if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_NAN2008 ; EFlags |= ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) ) ; while ( ++ Start != std :: next ( I ) ) { } } dumpStack ( ) ; ) ; ( void ) PrevMI ; Changed = true ; } finishBlockStack ( ) ; return


<s> SDValue SD_ImmQ2 = CurDAG -> getTargetConstant ( ImmQ2 , N , <STR_LIT> ) ; Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , SD_ImmQ2 , CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) , SDValue ( Move , <NUM_LIT> ) ) ; } if ( ImmQ3 ) { SDValue SD_ImmQ3 = CurDAG -> getTargetConstant ( ImmQ3 , N , <STR_LIT> ) ; Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , SD_ImmQ3 , CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) , SDValue ( Move , <NUM_LIT> ) ) ; } if ( ImmQ4 )


<s> mp -> refcount = <NUM_LIT> ; mp -> min_address = - <NUM_LIT> ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp =


<s> SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , FalseVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_I : return translateFPRegister ( mcInst , insn . opcodeModifier ) ; case ENCODING_Rv : translateRegister ( mcInst , insn . opcodeRegister ) ; return false


<s> ( void ) adjustFixupValue ( Fixup , Value ,


_mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; return St


<s> SmallVectorImpl < SDep > & AnchorDeps = Preds ? AnchorSU . Preds : AnchorSU . Succs ; const MachineInstr * FirstMI = Preds ? nullptr : AnchorMI ; const MachineInstr * SecondMI = Preds ? AnchorMI : nullptr ; if ( ! shouldScheduleAdjacent ( * DAG -> TII , DAG -> MF . getSubtarget ( ) , FirstMI , SecondMI ) ) return false ; for ( SDep & Dep : AnchorDeps ) { if ( Dep . isWeak ( ) ) continue ; SUnit & DepSU = * Dep . getSUnit ( ) ; if ( ! Preds && & DepSU == & DAG -> ExitSU ) continue ; const MachineInstr * DepMI = DepSU . getInstr ( ) ; if ( ! DepMI || DepMI -> isPseudo ( ) || DepMI -> isTransient ( ) ) continue ; FirstMI = Preds ? DepMI : AnchorMI ; SecondMI = Preds ? AnchorMI : DepMI ; if ( ! shouldScheduleAdjacent ( * DAG -> TII , DAG -> MF . getSubtarget ( ) , FirstMI , SecondMI ) ) continue ; SUnit & FirstSU = Preds ? DepSU : AnchorSU ; SUnit & SecondSU = Preds ? AnchorSU : DepSU ; DAG -> addEdge ( & SecondSU , SDep ( & FirstSU , SDep :: Cluster ) ) ; for ( SDep & IDep : AnchorDeps ) if ( IDep . getSUnit ( ) == & DepSU ) IDep . setLatency ( <NUM_LIT> ) ; for ( SDep & IDep : Preds ? DepSU . Succs : DepSU . Preds ) if ( IDep . getSUnit ( ) == & AnchorSU ) IDep . setLatency ( <NUM_LIT> ) ; DEBUG ( dbgs ( ) << DAG -> MF . getName ( ) << <STR_LIT> ; FirstSU . print ( dbgs ( ) , DAG ) ; dbgs ( ) << <STR_LIT> ; SecondSU . print ( dbgs ( ) , DAG ) ; dbgs ( ) << <STR_LIT> ; dbgs ( ) << DAG -> TII -> getName ( FirstMI -> getOpcode ( ) ) << <STR_LIT> << DAG -> TII -> getName ( SecondMI -> getOpcode ( ) ) << '\n' ; ) ; ++ NumFused


<s> return isDomainMVE ( & MI ) || isVectorPredicate ( &


<s> case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand ::


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u64 ( unsigned long long __X ) { return __builtin_ia32_tzcnt_u64 ( __X


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( MF . getFunction ( ) . hasOptSize ( ) ) return false ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> || windowsRequiresStackProbe ( MF , StackBumpBytes ) ) return false ; if ( MFI . hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc


<s> Inst . addOperand ( MCOperand :: createImm (


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> bool is32 = <STR_LIT> . contains ( Reg ) ; bool is64 = <STR_LIT> . contains ( Reg ) ; int Mov = is64 ? <STR_LIT> : <STR_LIT> ; int Push = is64 ? <STR_LIT> : <STR_LIT> ; int Pop = is64 ? <STR_LIT> : <STR_LIT> ; int AX = is64 ? <STR_LIT> : <STR_LIT> ; if ( ( FromEFLAGS || ToEFLAGS ) && ( is32 || is64 ) && Subtarget . isTargetNaCl ( ) ) { BuildMI ( MBB , MI , DL , get ( Push ) ) . addReg ( AX ) ; if ( FromEFLAGS ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( Mov ) , Reg ) . addReg ( AX ) ; } if ( ToEFLAGS ) { BuildMI ( MBB , MI , DL , get ( Mov ) , AX ) . addReg ( Reg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; } BuildMI ( MBB , MI , DL , get ( Pop ) , AX ) ; return ; } if ( SrcReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } } if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc


<s> case NSHST : return <STR_LIT> ; case NSHLD : return HasV8 ? <STR_LIT> : <STR_LIT> ; case RESERVED_4 : return <STR_LIT> ; case OSH : return <STR_LIT> ; case OSHST : return <STR_LIT> ; case OSHLD : return HasV8


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegSet ( )


<s> AFI -> setArgRegsSaveSize ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; std :: advance ( CurOrigArg , Ins [ VA . getValNo ( ) ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ VA . getValNo ( ) ] . OrigArgIndex ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> LLVMContext & Ctx = Builder . getContext ( ) ; Type * Ty = LD -> getType ( ) ; EVT VT = EVT :: getEVT ( Ty ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( Ctx ) ; Type * HalfTy = HalfVT . getTypeForEVT ( Ctx ) ; Value * Ptr = LD -> getPointerOperand ( ) ; PointerType * HalfPtrTy = HalfTy -> getPointerTo ( LD -> getPointerAddressSpace ( ) ) ; Value * HalfPtr = Builder . CreateBitCast ( Ptr ,


<s> unsigned <ISA_LIT>FastISel :: emitSubs_rs ( MVT RetVT , unsigned LHSReg , unsigned RHSReg , <STR_LIT> ShiftType , uint64_t ShiftImm , bool WantResult ) { return emitAddSub_rs ( false , RetVT , LHSReg , RHSReg , ShiftType , ShiftImm


<s> return <ISA_LIT>ProcFamily == IntelSLM


<s> EVT IdxVT = EVT :: getEVT ( Idx -> getType ( ) , false ) ; if ( IdxVT . bitsLT ( PtrVT ) ) { IdxN = emitIntExt ( IdxVT . getSimpleVT ( ) , IdxN , PtrVT , false ) ; } else if ( IdxVT . bitsGT ( PtrVT )


<s> static bool isScratchReg ( unsigned RegNo ) { return RegNo > <NUM_LIT> &&


<s> bool <ISA_LIT>SETargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool * Fast ) const { <STR_LIT> SVT = VT . getSimpleVT ( ) . SimpleTy ; switch ( SVT ) { case <STR_LIT>


<s> if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return 't' ; if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return 'n' ; if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return 'f' ; if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) { if ( TREE_VALUE ( list ) && TREE_VALUE ( TREE_VALUE ( list ) ) && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( list ) ) ) == INTEGER_CST ) { int location = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( list ) ) ) ; if ( location >= <NUM_LIT> && location <= <NUM_LIT> ) return 'i' ; } return


<s> static DecodeStatus DecodeGRH32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t

Address , const MCDisassembler * Decoder ) {


<s> inline vector unsigned char vec_splat_u8 ( const char


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( FramePtr == Reg && hasFP ( MF ) ) return true ; break ; case <STR_LIT> : return STI . isR9Reserved ( ) ; } return false


<s> static bool insn_can_be_in_speculative_p ( rtx insn


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill

) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [


<s> SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( ! Subtarget -> useSoftFloat ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return SDValue ( ) ; if ( ! Ld -> isVolatile ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget -> is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget -> getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT


<s> DebugLoc dl = Op . getDebugLoc ( ) ; int CompareOpc ; bool isDot ; if ( ! getAltivecCompareInfo ( Op , CompareOpc , isDot ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) } ; std :: vector < MVT > VTs ; VTs . push_back ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; VTs . push_back ( <STR_LIT> ) ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister

( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ;


<s> if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler :: Success


<s> emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_add ( tmp , tmp , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_sub ( tmp , GEN_INT ( <NUM_LIT> - width ) , tmp ) ) ; rtx mask = gen_reg_rtx ( V16QImode ) ; rtx mask_v2di = gen_reg_rtx ( V2DImode ) ; rtvec v = rtvec_alloc ( <NUM_LIT> ) ; if ( ! BYTES_BIG_ENDIAN ) { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; } else { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; } emit_insn ( gen_vec_initv2didi ( mask_v2di , gen_rtx_PARALLEL ( V2DImode , v ) ) ) ; rtx sub_mask = simplify_gen_subreg ( V16QImode , mask_v2di , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( mask , sub_mask ) ) ; rtx tmp_val = gen_reg_rtx ( SImode ) ; if ( inner_mode == E_SFmode ) if ( TARGET_DIRECT_MOVE_64BIT ) emit_insn ( gen_movsi_from_sf ( tmp_val , val ) ) ; else { rtx stack = rs6000_allocate_stack_temp ( SFmode , false , true ) ; emit_insn ( gen_movsf_hardfloat ( stack , val ) ) ; rtx stack2 = copy_rtx ( stack ) ; PUT_MODE ( stack2 , SImode ) ; emit_move_insn ( tmp_val , stack2 ) ; } else tmp_val = force_reg ( SImode , val ) ; rtx val_v16qi = gen_reg_rtx ( V16QImode ) ; rtx val_v2di = gen_reg_rtx ( V2DImode ) ; rtvec vec_val = rtvec_alloc ( <NUM_LIT> ) ; if ( ! BYTES_BIG_ENDIAN ) { RTVEC_ELT ( vec_val , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; RTVEC_ELT ( vec_val , <NUM_LIT> ) = tmp_val ; } else { RTVEC_ELT ( vec_val , <NUM_LIT> ) = tmp_val ; RTVEC_ELT ( vec_val , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; } emit_insn ( gen_vec_initv2didi ( val_v2di , gen_rtx_PARALLEL ( V2DImode , vec_val ) ) ) ; rtx sub_val = simplify_gen_subreg ( V16QImode , val_v2di , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( val_v16qi , sub_val ) ) ; rtx pcv = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_lvsl ( pcv , tmp ) ) ; rtx val_perm = gen_reg_rtx ( V16QImode ) ; rtx mask_perm = gen_reg_rtx ( V16QImode


<s> MachineBasicBlock * BBPrevious = BB -> getPrevNode ( ) ; assert ( BBPrevious && <STR_LIT> ) ; MachineBasicBlock * AfterNext = After -> getNextNode ( ) ; MachineBasicBlock * BBNext = BB -> getNextNode ( ) ; BB -> moveAfter ( After ) ; auto FixFallthrough = [ & ] ( MachineBasicBlock * From , MachineBasicBlock * To ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> ) ; assert ( From -> isSuccessor ( To ) && <STR_LIT> ) ; MachineInstr & Terminator = * ( -- From -> terminators ( ) . end ( ) ) ; if ( ! Terminator . isUnconditionalBranch ( ) ) { MachineInstrBuilder MIB = BuildMI ( From , Terminator . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addMBB ( To ) ; MIB . addImm ( <STR_LIT> :: AL ) ; MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ; } } ; if ( BBPrevious -> isSuccessor ( BB ) ) FixFallthrough ( BBPrevious , BB ) ; if ( AfterNext && After -> isSuccessor ( AfterNext ) ) FixFallthrough ( After ,


<s> uint32_t <ISA_LIT>MCCodeEmitter :: get<ISA_LIT>BLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand


<s> unsigned <ISA_LIT>ABIInfo :: GetEhDataReg ( unsigned I ) const { static const unsigned EhDataReg [ ] = { <STR_LIT> , <STR_LIT> } ; return EhDataReg [


<s> return true ; } case <STR_LIT> : { unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; if ( maskMatters ( RxSBG , allOnes ( RxSBG . BitSize ) - allOnes ( InnerBitSize ) ) ) return false ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : { auto * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> ) { if ( maskMatters ( RxSBG , allOnes ( Count ) ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) << Count ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate + Count ) & <NUM_LIT> ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( maskMatters ( RxSBG , allOnes ( Count ) << ( BitSize - Count ) ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate - Count ) & <NUM_LIT> ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true


<s> const char * name , * prefix ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = <STR_LIT> ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = <STR_LIT> ; else prefix = <STR_LIT> ; len = strlen ( name ) +


<s> break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_26_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC7_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC16_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_CALL16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_DISP ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC19_S2 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC18_S3 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC21_S2 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC26_S2 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PCHI16 ; break ; case <STR_LIT>


<s> checkNeonReplicateArgs ( FromW , ToW ) ; if ( ToW == <NUM_LIT> && isNEONi64splat ( ) )


<s> rtx cond = XEXP ( XEXP ( pc_set_rtx , <NUM_LIT> ) , <NUM_LIT> ) ; bool branch_if ; if ( GET_CODE ( cond ) == NE && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) branch_if = true ; else if ( GET_CODE ( cond ) == EQ && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) branch_if = false ; else gcc_unreachable ( ) ; if ( branch_target_bb == BRANCH_EDGE ( cbranch_insn_bb ) -> dest ) return branch_if ; else if ( branch_target_bb == FALLTHRU_EDGE ( cbranch_insn_bb ) -> dest ) return ! branch_if ; else gcc_unreachable (


<s> EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT


<s> void setOffset ( int64_t O ) { Offset =


<s> V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , BlendVT , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } case <STR_LIT> : { int Scale = <NUM_LIT> / VT . getVectorNumElements ( ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= Size ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) BlendMask |= <NUM_LIT> << ( i * Scale + j ) ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } case <STR_LIT> : { assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask


<s> OperandMatchResultTy parseBDVAddr64 ( OperandVector & Operands )


<s> static DecodeStatus DecodeMatrixTileListRegisterClass ( MCInst & Inst , unsigned RegMask , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegMask > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( RegMask


<s> assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ,


<s> assert ( FnStart == nullptr ) ; FnStart = getContext ( ) . createTempSymbol ( ) ; emitLabel ( FnStart


<s> LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF ::

SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ;


<s> SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } Ops . append ( OrigChain -> op_begin ( ) + <NUM_LIT> , OrigChain -> op_end ( ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , Ops ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load .

getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> static bool isEqual ( const SlotWithTag & A , const SlotWithTag & B ) { return A ==


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; return S


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForCallingConv ( Context


) _mm512_setzero_si512 ( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( MFI -> isPredecessor ( & * MFI ) ) { I = -- MFI -> end ( ) ; return true ; } else return false


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatMaskL ( SDValue N , SDValue & Imm ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> return <NUM_LIT> - countTrailingZeros < uint64_t >


<s> return MEM_P ( op ) && ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == POST_INC

|| REG_P ( XEXP ( op , <NUM_LIT> ) ) ) ;


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) ) return LowerFCOPYSIGN64 (

Op , DAG , Subtarget -> has<ISA_LIT>32r2 ( ) ) ;


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue (


<s> static MCInst getConditionalBranch ( unsigned Reg , const MCInst & Inst , const MCInstrInfo & II ) { unsigned PredReg ; <STR_LIT> Pred = getPredicate ( Inst , II , PredReg ) ; MCInst


<s> bool supportsEfficientVectorElementLoadStore ( ) { return ST -> getProcFamily (

) == <ISA_LIT>Subtarget :: ThunderX2T99 ;


<s> bool isTargetDarwin ( ) const { return TargetTriple . isOSDarwin


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return <NUM_LIT> ; int Addr = C -> getZExtValue ( ) ; if ( ( Addr & <NUM_LIT> ) != <NUM_LIT> || SignExtend32 < <NUM_LIT> > ( Addr ) != Addr ) return <NUM_LIT> ; return DAG . getConstant ( ( int ) C -> getZExtValue ( ) >> <NUM_LIT> , DAG . getTargetLoweringInfo (


<s> return DAG . getNode ( <STR_LIT> , DL , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , I ) ; } SDValue SllX = DAG . getNode ( <STR_LIT> , DL , TyX , X , Const1 ) ; SDValue SrlX = DAG . getNode ( <STR_LIT> , DL , TyX , SllX , Const1 ) ; SDValue SrlY = DAG . getNode ( <STR_LIT> , DL , TyY , Y , DAG . getConstant ( WidthY - <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( WidthX > WidthY ) SrlY = DAG . getNode ( <STR_LIT> , DL , TyX , SrlY ) ; else if ( WidthY > WidthX ) SrlY = DAG . getNode ( <STR_LIT> , DL , TyX , SrlY ) ; SDValue SllY = DAG . getNode ( <STR_LIT> , DL , TyX , SrlY , DAG . getConstant ( WidthX - <NUM_LIT>


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForCall ( )


<s> static bool isMaskRegClass ( const TargetRegisterClass * RC


<s> switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = ( ArgVT . getSizeInBits ( ) +


<s> else if ( GET_CODE ( x ) == POST_MODIFY && ia64_legitimate_address_reg ( XEXP ( x , <NUM_LIT> ) , strict ) && XEXP ( x , <NUM_LIT> ) != arg_pointer_rtx && ia64_legitimate_address_disp ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else return false


<s> CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , <NUM_LIT> ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine ->


<s> std :: reverse ( RVLocs . begin ( ) , RVLocs .


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU )


<s> void <ISA_LIT>TargetStreamer :: emitRRI ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , int16_t Imm , SMLoc IDLoc


<s> int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister (


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg )


<s> unsigned RegNum = State . getFirstUnallocated ( ArgRegs , NumArgRegs ) ; if ( RegNum != NumArgRegs && RegNum % <NUM_LIT> == <NUM_LIT> ) { State . AllocateReg ( ArgRegs [ RegNum ] ) ; } return false


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , <NUM_LIT> ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case SFmode : case DFmode


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Node ) ; SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT


<s> gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , <NUM_LIT> ) ) ; if ( ptr_mode != Pmode ) base = convert_memory_address ( Pmode , base ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( int_mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( int_mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( const_offset != <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( int_mode , dest , base ) ; aarch64_add_offset ( int_mode , dest , base , const_offset , NULL_RTX , NULL_RTX , false ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { if ( imm == CONSTM1_RTX ( mode ) ) imm = CONSTM1_RTX ( VNx16BImode ) ; rtx_vector_builder builder ; if ( aarch64_get_sve_pred_bits ( builder , imm ) ) { rtx res = aarch64_expand_sve_const_pred ( dest , builder


<s> case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case


<s> static const <ISA_LIT>MCExpr * CreateABS_G2_NC ( const MCExpr *


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op ,


<s> const unsigned SrcSz = SrcVT . getSizeInBits ( ) ; ( void ) DstSz ; assert ( DstSz < SrcSz && SrcSz <= <NUM_LIT> && DstSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) && <STR_LIT> ) ; SDLoc Loc ( Op ) ; if ( SrcSz == <NUM_LIT> && Subtarget -> hasFP16 ( ) ) return Op ; RTLIB :: Libcall LC = RTLIB :: getFPROUND ( SrcVT , DstVT ) ; assert ( LC != RTLIB ::


<s> return __aarch64_vset_lane_any ( * __src


<s> } unsigned StackOffset = <NUM_LIT> ; unsigned RegSize = Subtarget . isGP32bit ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( LastOffsetFI >= <NUM_LIT> ) StackOffset = MFI -> getObjectOffset ( LastOffsetFI ) + MFI -> getObjectSize ( LastOffsetFI ) ; StackOffset = ( ( StackOffset + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { if ( CSI [ i ] . getRegClass ( ) != <STR_LIT> ) break ; MFI -> setObjectOffset ( CSI [ i ] . getFrameIdx ( ) , StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += MFI -> getObjectAlignment ( CSI [ i ] . getFrameIdx ( ) ) ; } if ( hasFP ( MF ) ) { MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize ) , StackOffset ) ; <ISA_LIT>FI -> setFPStackOffset ( StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += RegSize ; } if ( MFI -> hasCalls ( ) ) { MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize ) , StackOffset ) ; <ISA_LIT>FI -> setRAStackOffset ( StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += RegSize ; } StackOffset = ( ( StackOffset + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { if ( CSI [ i ] . getRegClass


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( )


<s> i = strlen ( const_str ) ; str = ( char * ) alloca ( i + <NUM_LIT> ) ; memcpy ( str , const_str , i + <NUM_LIT> ) ; while ( <NUM_LIT> ) { dash = strchr ( str , '-' ) ; if ( ! dash ) { warning ( <NUM_LIT> , <STR_LIT> ) ; return ; } * dash = '\0' ; comma = strchr ( dash + <NUM_LIT> , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , str ) ; return ; } last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash =


<s> } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } } ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE (


<s> bool isCortexA53 ( ) const { return CPUString == <STR_LIT>


<s> if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( )


<s> return new <ISA_LIT>ConstantIslands ( tm


<s> PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; return


<s> const TargetRegisterClass * RC ; if ( SetFlags ) RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; else RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( LHSReg , getKillRegState ( LHSIsKill

) ) . addImm ( Imm ) . addImm ( getShifterImm ( <STR_LIT> , ShiftImm ) ) ;


<s> return ELF :: R_MIPS_64 ; case FK_DTPRel_4 : return ELF :: R_MIPS_TLS_DTPREL32 ; case FK_DTPRel_8 : return ELF :: R_MIPS_TLS_DTPREL64 ; case FK_TPRel_4 : return ELF :: R_MIPS_TLS_TPREL32 ; case FK_TPRel_8 : return ELF :: R_MIPS_TLS_TPREL64 ; case FK_GPRel_4 : return setRTypes ( ELF :: R_MIPS_GPREL32 , is64Bit ( ) ? ELF :: R_MIPS_64 : ELF :: R_MIPS_NONE , ELF :: R_MIPS_NONE ) ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : return setRTypes ( ELF :: R_MIPS_GPREL16 , ELF :: R_MIPS_SUB , ELF :: R_MIPS_HI16 ) ; case <STR_LIT> : return setRTypes ( ELF :: R_MICROMIPS_GPREL16 , ELF :: R_MICROMIPS_SUB , ELF :: R_MICROMIPS_HI16 ) ; case <STR_LIT> : return setRTypes ( ELF :: R_MIPS_GPREL16 , ELF :: R_MIPS_SUB , ELF :: R_MIPS_LO16 ) ; case <STR_LIT> : return setRTypes ( ELF :: R_MICROMIPS_GPREL16 , ELF

:: R_MICROMIPS_SUB , ELF :: R_MICROMIPS_LO16 ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10Lsl1 ( SDValue Addr , SDValue


<s> void <ISA_LIT>A57FPLoadBalancing :: scanInstruction ( MachineInstr * MI , unsigned Idx , std :: map < unsigned , Chain * > & ActiveChains , std :: vector < std :: unique_ptr < Chain >> & AllChains ) { if ( isMul ( MI ) ) { for ( auto & I : MI -> uses ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; for ( auto & I : MI -> defs ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( DestReg ) << <STR_LIT> << * MI ) ; auto G = llvm :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else if ( isMla ( MI ) ) { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AccumReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( DestReg != AccumReg ) maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( ActiveChains . find ( AccumReg ) != ActiveChains . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( AccumReg ) << <STR_LIT> << * MI ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; ActiveChains [ AccumReg ] -> add ( MI , Idx , getColor ( DestReg ) ) ; if ( DestReg != AccumReg ) { ActiveChains [ DestReg ] = ActiveChains [ AccumReg ] ; ActiveChains . erase ( AccumReg ) ; } return ; } DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( DestReg ) << <STR_LIT> ) ; auto G = llvm :: make_unique < Chain > ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G . get ( ) ; AllChains . push_back ( std :: move ( G ) ) ; } else { for ( auto & I : MI -> uses ( ) ) maybeKillChain ( I , Idx , ActiveChains ) ; for ( auto & I : MI -> defs ( ) ) maybeKillChain