<s> bool <ISA_LIT>AsmParser :: parseDirectiveThumbFunc ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; const auto Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; if ( IsMachO ) { if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) || Parser . getTok ( ) . is ( AsmToken :: String ) ) { MCSymbol * Func = getParser ( ) . getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; return false ; } } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) || check ( ! hasThumb ( ) , L , <STR_LIT> ) ) return true ; if ( ! isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag (


<s> static SDValue combineSub ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) +


<s> bool <ISA_LIT>InstrInfo :: isWhileOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags &


<s> return ( ( RegNo > <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo > <STR_LIT> && RegNo <= <STR_LIT> ) || (

RegNo > <STR_LIT> && RegNo <= <STR_LIT> ) ) ;


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT ,


<s> int PIdx = Old -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( PIdx ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , Pred , PredReg ) ; } else { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl ,


<s> string MO_name = TRI -> getName ( MO . getReg ( ) ) ; SExpr * SP_times_8 = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , <STR_LIT> ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * addrInSP = ctx -> load ( <NUM_LIT> , ctx -> address ( <STR_LIT> , SP_times_8 ) ) ; SExpr * ldr = ctx -> store ( ctx -> address ( MO_name ) , addrInSP ) ; alfbb . addStatement ( label + <STR_LIT> + MO_name , string ( <STR_LIT> ) + MO_name + <STR_LIT> , ldr ) ; SExpr * SP_incr = ctx -> add ( <NUM_LIT> , ctx -> load ( <NUM_LIT> , <STR_LIT> ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * incr = ctx -> store ( ctx -> address ( <STR_LIT> ) , SP_incr ) ; alfbb . addStatement ( label + <STR_LIT> +

MO_name + <STR_LIT> , <STR_LIT> , incr ) ;


<s> if ( DEFAULT_ABI != ABI_V4 ) return <NUM_LIT> ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( mode ) || FLOAT_MODE_P ( mode ) ) ) return <NUM_LIT> ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; else { rtx sum = XEXP ( op , <NUM_LIT> ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , <NUM_LIT> ) ) ; if ( summand < <NUM_LIT> || summand > g_switch_value ) return <NUM_LIT> ; sym_ref = XEXP ( sum , <NUM_LIT> ) ; } return SYMBOL_REF_SMALL_P (


<s> static DecodeStatus DecodeAFGR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> || RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo / <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> const MCExpr * LaneIndex ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( LaneIndex ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LaneIndex ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; int64_t Val = CE -> getValue ( ) ; if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> static bool rs6000_use_blocks_for_constant_p ( machine_mode


<s> EVT CondVT = Cond . getValueType ( ) ; SDLoc DL ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( CondVT . isVector ( ) && <STR_LIT> ) ; bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros && ! FValIsAllZeros && Subtarget . hasAVX512 ( ) && Cond . hasOneUse ( ) && CondVT . getVectorElementType ( ) == <STR_LIT> ) { SDValue CondNew = DAG . getNOT ( DL , Cond , CondVT ) ; return DAG . getSelect ( DL , VT , CondNew , RHS , LHS ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( DAG . ComputeNumSignBits ( Cond ) != CondVT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT , Cond ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( CondVT ) ) return SDValue ( ) ; if ( TValIsAllOnes ) { SDValue CastRHS = DAG . getBitcast ( CondVT , RHS ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastRHS ) ; return DAG . getBitcast ( VT , Or ) ; } if ( FValIsAllZeros ) { SDValue CastLHS = DAG . getBitcast ( CondVT , LHS ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastLHS ) ; return DAG . getBitcast ( VT ,


<s> static const <ISA_LIT>MCExpr * createLo ( const MCExpr * Expr , bool isDarwin , MCContext & Ctx ) { return create ( VK_<ISA_LIT>_LO , Expr ,


<s> void mmix_asm_output_skip ( FILE * stream , int nbytes


<s> return new <ISA_LIT>MCInstrAnalysis ( Info )


<s> if ( size == <NUM_LIT> ) { if ( mode == VOIDmode ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr == LAST_ARG_REGNUM ) { asm_fprintf ( f , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; reg_containing_return_addr = LR_REGNUM ; } else if ( size > <NUM_LIT> ) { restore_a4 = TRUE ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } if ( reg_containing_return_addr != LAST_ARG_REGNUM ) { regs_available_for_popping |= <NUM_LIT> << LAST_ARG_REGNUM ; -- pops_needed ; } } thumb_pop ( f , regs_available_for_popping ) ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop &= ~ ( <NUM_LIT> << LR_REGNUM ) ; reg_containing_return_addr = number_of_first_bit_set ( regs_available_for_popping ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << reg_containing_return_addr ) ; } if ( regs_available_for_popping ) { int frame_pointer ; frame_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , frame_pointer ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << frame_pointer ) ; regs_to_pop &= ~ ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) ; if ( regs_available_for_popping ) { int stack_pointer


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: parseImmediate ( ) { SMLoc Start = Parser . getTok ( ) . getLoc ( ) ; SMLoc End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * ExprVal ; switch ( Lexer . getKind ( ) ) { case AsmToken ::


<s> bool hasExtDiv ( ) const { return HasExtDiv


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! ST -> hasV6T2Ops ( ) ) return SDValue ( ) ; SDValue rbit = DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> bool mayNeedRelaxation ( const MCInst & Inst ,

const MCSubtargetInfo & STI ) const override {


<s> static SDValue replaceSplatVectorStore ( SelectionDAG & DAG , StoreSDNode * St ) { SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) return SDValue ( ) ; if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumVecElts = VT . getVectorNumElements ( ) ; if ( NumVecElts != <NUM_LIT> && NumVecElts != <NUM_LIT> ) return SDValue ( ) ; SDValue SplatVal = StVal . getOperand ( <NUM_LIT> ) ; unsigned RemainInsertElts = NumVecElts - <NUM_LIT> ; while ( -- RemainInsertElts ) { SDValue NextInsertElt = StVal . getOperand ( <NUM_LIT> ) ; if ( NextInsertElt . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( NextInsertElt . getOperand ( <NUM_LIT> ) != SplatVal ) return SDValue ( ) ; StVal = NextInsertElt ; } unsigned OrigAlignment = St -> getAlignment ( ) ; unsigned EltOffset = NumVecElts == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Alignment = std :: min ( OrigAlignment , EltOffset ) ; SDLoc DL (


<s> static int iq2000_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - <NUM_LIT> ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> ,


<s> SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; } } return SDValue (


<s> BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget -> isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ; return DAG . getNode ( Opc , SDLoc ( N ) , Ty , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( SplatValue .


<s> if ( ITBlockSize ) { -- ITBlockSize ; } else if ( Opcode == <STR_LIT> ) { unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ; } while ( I -> isDebugValue (


<s> bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MI , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; } return


<s> bool isVPTPredicableCDEInstr ( StringRef Mnemonic ) { if ( ! Mnemonic . startswith ( <STR_LIT> ) )


<s> * _TEXASR_PTR ( TM_buff ) = __builtin_get_texasr ( ) ; * _TEXASRU_PTR ( TM_buff ) = __builtin_get_texasru ( ) ; * _TEXASRL_PTR ( TM_buff ) =


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> if ( nonvoid ) return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_POWERPC64 ) ?


<s> halfmode = V32QImode ; extract = high_p ? gen_vec_extract_hi_v64qi : gen_vec_extract_lo_v64qi ; break ; case E_V32QImode : if ( unsigned_p ) unpack = gen_avx2_zero_extendv16qiv16hi2 ; else unpack = gen_avx2_sign_extendv16qiv16hi2 ; halfmode = V16QImode ; extract = high_p ? gen_vec_extract_hi_v32qi : gen_vec_extract_lo_v32qi ; break ; case E_V32HImode : if ( unsigned_p ) unpack = gen_avx512f_zero_extendv16hiv16si2 ; else unpack = gen_avx512f_sign_extendv16hiv16si2 ; halfmode = V16HImode ; extract = high_p ? gen_vec_extract_hi_v32hi : gen_vec_extract_lo_v32hi ; break ; case E_V16HImode : if ( unsigned_p ) unpack = gen_avx2_zero_extendv8hiv8si2 ; else unpack = gen_avx2_sign_extendv8hiv8si2 ; halfmode = V8HImode ; extract = high_p ? gen_vec_extract_hi_v16hi : gen_vec_extract_lo_v16hi ; break ; case E_V16SImode : if ( unsigned_p ) unpack = gen_avx512f_zero_extendv8siv8di2 ; else unpack = gen_avx512f_sign_extendv8siv8di2 ; halfmode = V8SImode ; extract = high_p ? gen_vec_extract_hi_v16si : gen_vec_extract_lo_v16si ; break ; case E_V8SImode : if ( unsigned_p ) unpack = gen_avx2_zero_extendv4siv4di2 ; else unpack = gen_avx2_sign_extendv4siv4di2 ; halfmode = V4SImode ; extract = high_p ? gen_vec_extract_hi_v8si : gen_vec_extract_lo_v8si ; break ; case E_V16QImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv8qiv8hi2 ; else unpack = gen_sse4_1_sign_extendv8qiv8hi2 ; break ; case E_V8HImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv4hiv4si2 ; else unpack = gen_sse4_1_sign_extendv4hiv4si2 ; break ; case E_V4SImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv2siv2di2 ; else unpack = gen_sse4_1_sign_extendv2siv2di2 ; break ; case E_V8QImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv4qiv4hi2 ; else unpack = gen_sse4_1_sign_extendv4qiv4hi2 ; break ; case E_V4HImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv2hiv2si2 ; else unpack = gen_sse4_1_sign_extendv2hiv2si2 ; break ; case E_V4QImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv2qiv2hi2 ; else unpack = gen_sse4_1_sign_extendv2qiv2hi2 ; break ; default : gcc_unreachable ( ) ; } if ( GET_MODE_SIZE ( imode ) >= <NUM_LIT> ) { tmp = gen_reg_rtx ( halfmode ) ; emit_insn ( extract ( tmp , src ) ) ; } else if ( high_p ) { switch ( GET_MODE_SIZE ( imode ) ) { case <NUM_LIT> : tmp = gen_reg_rtx ( V1TImode ) ; emit_insn ( gen_sse2_lshrv1ti3 ( tmp , gen_lowpart ( V1TImode , src ) , GEN_INT ( <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : tmp = gen_reg_rtx ( V1DImode ) ; emit_insn ( gen_mmx_lshrv1di3 ( tmp , gen_lowpart ( V1DImode , src ) , GEN_INT ( <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : tmp = gen_reg_rtx ( V1SImode ) ; emit_insn ( gen_mmx_lshrv1si3 ( tmp , gen_lowpart ( V1SImode , src ) , GEN_INT ( <NUM_LIT> ) ) ) ; break ; default : gcc_unreachable ( ) ; } tmp = gen_lowpart ( imode , tmp ) ; } else tmp = src ; emit_insn ( unpack ( dest , tmp ) ) ; } else { rtx ( * unpack ) ( rtx , rtx , rtx ) ; switch ( imode ) { case E_V16QImode : if ( high_p ) unpack = gen_vec_interleave_highv16qi ; else unpack = gen_vec_interleave_lowv16qi ; break ; case E_V8HImode : if ( high_p ) unpack = gen_vec_interleave_highv8hi ; else unpack = gen_vec_interleave_lowv8hi ; break ; case


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( ! MO . isExpr ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) ) & <NUM_LIT> ) | RegBits ; const MCExpr * Expr = MO . getExpr ( ) ; switch ( Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( Expr ) ; ( void ) SRE ; assert ( ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ) && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) ) ) ; return <NUM_LIT> ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; assert ( BE -> getOpcode ( ) == MCBinaryExpr :: Add && <STR_LIT> ) ; const MCExpr * LHS = BE -> getLHS ( ) ; const MCExpr * RHS = BE -> getRHS ( ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef ) std :: swap ( LHS , RHS ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef || RHS -> getKind ( ) != MCExpr :: Constant ) llvm_unreachable ( <STR_LIT> ) ; const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( LHS ) ; ( void ) SRE ; const MCConstantExpr * CE = cast


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI .


<s> if ( ! Subtarget -> hasV5TOps ( ) ) return false ; if ( Enable<ISA_LIT>LongCalls ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( CS . arg_size ( ) ) ; ArgRegs . reserve ( CS . arg_size ( ) ) ; ArgVTs . reserve ( CS . arg_size ( ) ) ; ArgFlags . reserve ( CS . arg_size ( ) ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; const Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back


<s> unsigned Type = <NUM_LIT> ; if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_REL32 ; break ; case MCSymbolRefExpr :: VK_TLSGD : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_GOTPCREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_<ISA_LIT>_PLT32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF ::


__imm , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetMsa ( ) ; return


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { bool SCS = MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ; if ( CC == CallingConv :: GHC ) return SCS ? CSR_<ISA_LIT>_NoRegs_SCS_RegMask : CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return SCS ? CSR_<ISA_LIT>_AllRegs_SCS_RegMask : CSR_<ISA_LIT>_AllRegs_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { if ( SCS ) report_fatal_error ( <STR_LIT> ) ; return getDarwinCallPreservedMask ( MF ,


<s> if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else { AM . GVOpFlags = Subtarget -> classifyLocalReference ( nullptr ) ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base .


<s> if ( TARGET_CMODEL != CMODEL_SMALL ) ret = ( ( addr_mask & RELOAD_REG_OFFSET ) == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( TARGET_MINIMAL_TOC ) ? <NUM_LIT> : <NUM_LIT> ; return


<s> Name += <STR_LIT> ; const char * PGP = AP . MAI -> getPrivateGlobalPrefix ( ) ; const char * Prefix = <STR_LIT> ; if ( ! Name . startswith ( PGP ) ) { Prefix = PGP ; } MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + Twine ( Name ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { Name . erase ( Name . end ( ) - <NUM_LIT> , Name . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( Name . str ( ) ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { Name += <STR_LIT>


<s> if ( ST . in<ISA_LIT>16Mode ( ) ) RC = ( const TargetRegisterClass * ) & <STR_LIT> ; else RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * )


<s> return isMem ( MemKind ) && Mem . RegKind ==


<s> assert ( K != TargetTransformInfo :: RGK_Scalar ) ; return K == TargetTransformInfo :: RGK_FixedWidthVector


<s> unsigned BestGrowth = ~ <NUM_LIT> ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> ) return


<s> for ( int i = <NUM_LIT> ; i < NUMBIFSTANZAS ; i ++ ) if ( ! strcmp ( stanza_name , stanza_map

[ i ] . stanza_name ) ) return stanza_map [ i ] . stanza ;


<s> <ISA_LIT>CallFrameOptimization ( ) :


<s> inline vector signed short vec_splat_s16 ( const char a1 ) { return ( vector signed short


<s> const char * getPassName ( ) const override { return


<s> unsigned NextBlockOffset ; Align NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = ++ Water -> getIterator ( ) ; if ( NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = Align ( <NUM_LIT> ) ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockAlignment = NextBlock -> getAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT>


<s> else if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isExpr ( ) ) MO . getExpr ( ) -> print ( O , MAI ) ; else llvm_unreachable (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! BRChange ) break ; MadeChange = true ; } verify (


<s> MVT VT = Op . getSimpleValueType ( ) ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : return SDValue


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_SETJMP (


<s> bool <ISA_LIT>FrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF


<s> aligned_p = <NUM_LIT> ; break ; } fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'B' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case <NUM_LIT> : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = <NUM_LIT> ; break ; } fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'W' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case


<s> Inst . addOperand ( MCOperand :: createReg ( FCCRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmplt ( a , b


<s> ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call


<s> unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; const DebugLoc & dl = MI . getDebugLoc ( ) ; unsigned TOS = getStackEntry ( <NUM_LIT> ) ; if ( Op0 != TOS && Op1 != TOS ) { if ( KillsOp0 ) { moveToTop ( Op0 , I ) ; TOS = Op0 ; } else if ( KillsOp1 ) { moveToTop ( Op1 , I ) ; TOS = Op1 ; } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward )


<s> void Emitter < CodeEmitter > :: emitMulFrmInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; unsigned OpIdx = <NUM_LIT> ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> )


<s> extract_insn_cached ( insn ) ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( GENERAL_REG_P ( recog_data . operand [

i ] ) && ! QI_REGNO_P ( REGNO ( recog_data . operand [ i ] ) ) ) return true ;


<s> SDValue CC = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( ( SetCCOpcode == <STR_LIT> || SetCCOpcode == <STR_LIT> ) && <STR_LIT> ( Op0 . getNode ( ) ) ) std :: swap ( Op0 , Op1 ) ; if ( SetCCOpcode == <STR_LIT> ) { SetCCOpcode = <STR_LIT> ( SetCCOpcode ) ; std :: swap ( Op0 , Op1


<s> static inline __ev64_opaque__ __ev_create_ufix32_fs ( float a , float b ) { __ev64_opaque__ ev ; ev = ( __ev64_opaque__ ) __ev_create_fs ( a , b ) ; return ( __ev64_opaque__ ) __builtin_spe_evfsctuf (


<s> std :: stable_sort ( Globals . begin ( ) , Globals . end ( ) , GlobalCmp ( TD ) ) ; const Type * Int32Ty = Type :: getInt32Ty ( M . getContext ( ) ) ; for ( size_t i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ) { size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < const Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; MergedSize < MaxOffset && j != e ; ++ j ) { const Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { SmallVector < Constant * , <NUM_LIT> > Idx ; Idx . push_back ( ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; Idx . push_back ( ConstantInt :: get ( Int32Ty , k - i ) ) ; Constant * GEP = ConstantExpr :: getInBoundsGetElementPtr ( MergedGV , & Idx [ <NUM_LIT> ] , Idx . size ( ) ) ; Globals [ k ] -> replaceAllUsesWith ( GEP ) ; Globals [ k ] -> eraseFromParent ( ) ; } i = j ; } return true


<s> for ( int Src = <NUM_LIT> ; Src != NumSrcs ; ++ Src ) { int Lo = Src * NumElts ; APInt SrcElts = APInt :: getNullValue ( NumElts ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( DemandedElts [ i ] ) { int M = OpMask [ i ] - Lo ; if ( <NUM_LIT> <= M && M < NumElts ) SrcElts . setBit ( M ) ; } APInt SrcUndef , SrcZero ; if ( SimplifyDemandedVectorElts ( OpInputs [ Src ] , SrcElts , SrcUndef , SrcZero , TLO , Depth + <NUM_LIT> ) ) return true ; } for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! DemandedElts [ i ] ) OpMask [ i ] = SM_SentinelUndef ; if ( isUndefInRange ( OpMask , <NUM_LIT> , NumElts ) ) { KnownUndef . setAllBits ( ) ; return TLO . CombineTo ( Op , TLO . DAG . getUNDEF ( VT ) ) ; } if ( isUndefOrZeroInRange ( OpMask , <NUM_LIT> , NumElts ) ) { KnownZero . setAllBits ( ) ; return TLO . CombineTo ( Op , getZeroVector ( VT . getSimpleVT ( ) , Subtarget , TLO . DAG , SDLoc (


<s> else if ( COP0RegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ; else if ( FGR32RegClass -> contains ( SubReg ) || FGR64RegClass -> contains ( SubReg ) || AFGR64RegClass -> contains ( SubReg ) || MSA128BRegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ; else if ( COP2RegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ; else if ( COP3RegClass -> contains ( SubReg ) ) ri_cprmask


<s> bool hasDSPE60 ( ) const { return HasDSPE60


<s> SDLoc DL ( N ) ; if ( SDValue SSatVal = detectSSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , SSatVal ) ; if ( SDValue USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnes ( VT . getScalarSizeInBits ( )


<s> return ( vector signed int ) __builtin_altivec_vcmpeqfp ( ( vector float


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedScatterBaseWB ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32


<s> <ISA_LIT>MCAsmInfoMicrosoft :: <ISA_LIT>MCAsmInfoMicrosoft ( const Triple & Triple ) { if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling :: WinEH ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue =


<s> static bool areCFlagsAliveInSuccessors ( MachineBasicBlock * MBB ) { for ( auto * BB : MBB -> successors ( ) ) if ( BB

-> isLiveIn ( <STR_LIT> ) ) return true ;


<s> if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstr ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( { NewTy } ,


<s> bool singleword = ( type ? ( integer_zerop ( TYPE_SIZE ( type ) ) || ! TREE_CONSTANT ( TYPE_SIZE ( type ) ) ||

int_size_in_bytes ( type ) <= UNITS_PER_WORD ) : GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) ;


<s> void <ISA_LIT>CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , unsigned OriginalIndex , SmallVectorImpl < ArgInfo > & SplitArgs , SmallVectorImpl < unsigned > & SplitArgsOrigIndices ) const { SplitArgs . push_back ( OrigArg ) ; SplitArgsOrigIndices . push_back


<s> if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftSelf ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftError ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; MVT VT = ArgVT . getSimpleVT ( ) . SimpleTy ; if ( VT . isFloatingPoint ( ) && ! Subtarget -> hasFPARMv8 ( ) ) return false ; if ( VT . isVector ( ) && ( ! Subtarget -> hasNEON ( ) || ! Subtarget -> isLittleEndian ( ) ) ) return false ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) ++ GPRCnt ; else if ( ( VT >= <STR_LIT> && VT <= <STR_LIT> ) || VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ++ FPRCnt ; else return false ; if ( GPRCnt > <NUM_LIT> || FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg Registers [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; VT =


<s> void addNEONi32vmovNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = ~ CE -> getValue ( ) ; if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) |

( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> } unsigned ZeroReg = IsAddress ? ABI . GetNullPtr ( ) : ABI . GetZeroReg ( ) ; unsigned AdduOp = ! Is32BitImm ? <STR_LIT> : <STR_LIT> ; bool UseSrcReg = false ; if ( SrcReg != <STR_LIT> ) UseSrcReg = true ; unsigned TmpReg = DstReg ; if ( UseSrcReg && getContext ( ) . getRegisterInfo ( ) -> isSuperOrSubRegisterEq ( DstReg , SrcReg ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } if ( isInt < <NUM_LIT> > ( ImmValue ) ) { if ( ! UseSrcReg ) SrcReg = ZeroReg ; if ( IsAddress && ! Is32BitImm ) { emitRRI ( <STR_LIT> , DstReg , SrcReg , ImmValue , IDLoc , Instructions ) ; return false ; } emitRRI ( <STR_LIT> , DstReg , SrcReg , ImmValue , IDLoc , Instructions ) ; return false ; } if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { unsigned TmpReg = DstReg ; if ( SrcReg == DstReg ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; } emitRRI ( <STR_LIT> , TmpReg , ZeroReg , ImmValue , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( ABI . GetPtrAdduOp ( ) , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } if ( isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ) { warnIfNoMacro ( IDLoc ) ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits15To0 = ImmValue & <NUM_LIT> ; if ( ! Is32BitImm && ! isInt < <NUM_LIT> > ( ImmValue ) ) { if ( ImmValue == <NUM_LIT> ) { emitRI ( <STR_LIT> , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } emitRRI ( <STR_LIT> , TmpReg , ZeroReg , Bits31To16 , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; if ( Bits15To0 ) emitRRI ( <STR_LIT> , TmpReg , TmpReg , Bits15To0 , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } emitRI ( <STR_LIT> , TmpReg , Bits31To16 , IDLoc , Instructions ) ; if ( Bits15To0 ) emitRRI ( <STR_LIT> , TmpReg , TmpReg , Bits15To0 , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } if ( isShiftedUIntAtAnyPosition < <NUM_LIT> > ( ImmValue ) ) { if ( Is32BitImm


<s> if ( ! optimize_size ) { memcpy ( reg_alloc_order , nds32_reg_alloc_order_for_speed , sizeof


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false


<s> break ; case <STR_LIT> : if ( SelectMoveImmediate ( N ) ) return ; break ; case <STR_LIT> : if ( SelectConditionalBranch ( N ) ) return ; break ; } SelectCode ( N )


<s> SMShadowTracker . reset ( <NUM_LIT> ) ; SM . reset (


<s> DEBUG ( { for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) <<

format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> const IntrinsicData * Data = std :: lower_bound ( std :: begin ( IntrinsicsWithChain ) , std :: end ( IntrinsicsWithChain ) , IntNo ) ; if ( Data != std :: end ( IntrinsicsWithChain ) && Data -> Id ==


<s> if ( FirstOperandOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( FirstOperand . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask_64 ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; if ( SMPos != <NUM_LIT> || SMSize > <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; NewOperand = FirstOperand . getOperand ( <NUM_LIT> ) ; SMSize -- ; return DAG . getNode ( <STR_LIT> , DL , ValTy , NewOperand , DAG . getConstant ( Pos ,

DL , <STR_LIT> ) , DAG . getConstant ( SMSize , DL , <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = - VT . getStoreSize ( ) + <NUM_LIT> ; Info . size = <NUM_LIT> * VT . getStoreSize ( ) - <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case


<s> return ( uint64x1_t ) __builtin_neon_vrshludi ( ( int64x1_t )


<s> if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack , bool IsThumb ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ; new <ISA_LIT>TargetELFStreamer ( * S ) ; S -> getAssembler ( ) .

setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;


<s> assert ( isMyDuty ( pSrcFragRef ) ) ; std :: string sym_name ( <STR_LIT> ) ; sym_name . append ( name ( ) ) . append ( llvm :: utohexstr ( pIsland . numOfStubs ( ) ) ) . append ( <STR_LIT> ) . append ( pIsland . name ( ) ) ; LDSymbol * stub_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( sym_name , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Local , size ( ) , initSymValue ( ) , FragmentRef :: Create ( * this , initSymValue ( ) ) , ResolveInfo :: Default ) ; setSymInfo ( stub_sym -> resolveInfo ( ) ) ; FragmentRef * target = FragmentRef :: Create ( * pSrcFragRef . frag ( ) , pSrcFragRef . offset ( ) + getErratumInsnOffset ( ) + <ISA_LIT>InsnHelpers :: InsnSize ) ; ResolveInfo * target_info = pBuilder . CreateLocalSymbol ( * target ) ; fixup_iterator it = fixup_begin ( ) ; Relocation * reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; std :: unique_ptr < unsigned [ ] > code ( new unsigned [ getErratumSequenceSize ( ) / <NUM_LIT> ] ) ; pSrcFragRef . memcpy ( code . get ( ) , getErratumSequenceSize ( ) , <NUM_LIT> ) ; reloc -> target ( ) = code [ getErratumInsnOffset ( ) / <ISA_LIT>InsnHelpers :: InsnSize ] ; pIsland . addRelocation ( * reloc ) ; ++ it ; reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; reloc -> target ( ) = <ISA_LIT>InsnHelpers :: buildBranchInsn ( ) ; pIsland . addRelocation ( *


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB


<s> MachineBasicBlock & UnsplitSucc = * PrevI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; bool IsEdgeSplit = std :: any_of ( SplitI . getIterator ( ) , MBB . instr_end ( ) , [ & ] ( MachineInstr & MI ) { assert ( MI . isTerminator ( ) && <STR_LIT> ) ; return llvm :: any_of ( MI . operands ( ) , [ & ] ( MachineOperand & MOp ) { return MOp . isMBB ( ) && MOp . getMBB ( ) == & UnsplitSucc ; } ) ; } ) || MBB . getFallThrough ( ) == & UnsplitSucc ; MachineBasicBlock & NewMBB = * MF . CreateMachineBasicBlock ( ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( & MBB ) ) , & NewMBB ) ; NewMBB . splice ( NewMBB . end ( ) , & MBB , SplitI . getIterator ( ) , MBB . end ( ) ) ; for ( auto SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( IsEdgeSplit || * SI != & UnsplitSucc ) NewMBB . copySuccessor ( & MBB , SI ) ; if ( ! IsEdgeSplit ) NewMBB . normalizeSuccProbs ( ) ; for ( MachineBasicBlock * Succ : NewMBB . successors ( ) ) if ( Succ != & UnsplitSucc ) MBB . replaceSuccessor ( Succ , & NewMBB ) ; assert ( MBB . isSuccessor ( & NewMBB ) && <STR_LIT>


<s> switch ( insn . eaBase ) { case EA_BASE_NONE : llvm_unreachable ( <STR_LIT> ) ; break ; ALL_EA_BASES llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case EA_REG_ ## x : \ mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; ALL_REGS default


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / <NUM_LIT> - <NUM_LIT> ; insn = emit_jump_insn (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTarget7OpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm


<s> if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( TARGET_ABICALLS_PIC0 ) return false ; if ( TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p ( x ) && ! SYMBOL_REF_EXTERNAL_P ( x ) )


<s> switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) { assert ( ( Cond [ i ] . isImm ( ) || Cond [ i ] . isReg ( ) ) && <STR_LIT> ) ; MIB . add ( Cond [ i ]


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRRI12 ( SDValue Op , SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { <ISA_LIT>RRIAddressMode AM20 , AM12 ; bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM12 . dump ( ) ) ; EVT VT = Addr . getValueType (


<s> void addRegGxRCNoR0Operands ( MCInst & Inst , unsigned N ) const { if ( is<ISA_LIT>64 ( ) ) addRegG8RCNoX0Operands ( Inst , N ) ; else addRegGPRCNoR0Operands ( Inst , N )


<s> static bool CC_<ISA_LIT>_SVR4_Custom_AlignFPArgRegs ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs ,


<s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode (


<s> bool addAllocPriorityToGlobalRanges ( ) const override { return


<s> SM . serializeToStackMapSection ( ) ; OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { if ( ! Alias . hasDLLExportStorageClass ( ) ) continue ; if ( Alias . getType ( ) -> getElementType ( ) -> isFunctionTy ( ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals ) GenerateExportDirective ( Symbol , true ) ; for ( auto & Symbol : DLLExportedFns ) GenerateExportDirective ( Symbol , false ) ; } } if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>EarlyReturnPass ( ) , false ) ; addPass ( create<ISA_LIT>BranchSelectionPass ( )


<s> rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int len = shift_insns [ INTVAL ( XEXP ( set_src , <NUM_LIT> ) ) ] ; rtx op = XEXP ( set_src ,


<s> return ( uint32x2_t ) ( vabs_f32 ( __a ) >= vabs_f32 ( __b ) ) ; return ( uint32x2_t ) __builtin_neon_vcagev2sf (


<s> void addVectorIndexDOperands ( MCInst & Inst , unsigned N


<s> SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant


<s> unsigned Opcode = <STR_LIT> ; if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( imm


, ( __v16si ) __index , mask , __scale ) ;


<s> bool isSPVFP = <STR_LIT> . contains ( RegM ) ; RegM = II -> getRegisterInfo ( ) . getEncodingValue ( RegM ) ; if ( ! isSPVFP ) { Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) ; Binary |= ( RegM & <NUM_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS4 ( SDValue Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base , OffImm ,


<s> machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; rtx perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm [ i ] = GEN_INT ( i * <NUM_LIT> ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , nelt


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; return


<s> insertDAGNode ( * CurDAG , OrigShiftAmt , X ) ; } else return false ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , DL , SubVT ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Zero , X ) ; NewShiftAmt = Neg ; insertDAGNode ( * CurDAG , OrigShiftAmt , Zero ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , Neg ) ; } else return false ; } else return false ; if ( NewShiftAmt . getValueType ( ) != <STR_LIT> ) { NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; } NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt , CurDAG -> getConstant ( Size - <NUM_LIT> , DL , <STR_LIT> ) ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; SDNode * UpdatedNode = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewShiftAmt ) ; if ( UpdatedNode != N ) { ReplaceNode ( N , UpdatedNode ) ; return true ; } if ( OrigShiftAmt . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( OrigShiftAmt . getNode ( ) ) ; SelectCode ( N ) ; return


<s> if ( ! TARGET_64BIT || cum -> call_abi == MS_ABI ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; save_area = frame_pointer_rtx ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ; bnd_reg = cum -> bnd_regno + cum -> force_bnd_pass ; if ( chkp_function_instrumented_p ( current_function_decl ) ) for ( i = cum -> regno ; i < max ; i ++ ) { rtx addr = plus_constant ( Pmode , save_area , i * UNITS_PER_WORD ) ; rtx reg = gen_rtx_REG ( DImode , x86_64_int_parameter_registers [ i ] ) ; rtx ptr = reg ; rtx bounds ; if ( bnd_reg <= LAST_BND_REG ) bounds = gen_rtx_REG ( BNDmode , bnd_reg ) ; else { rtx ldx_addr = plus_constant ( Pmode , arg_pointer_rtx , ( LAST_BND_REG - bnd_reg ) * GET_MODE_SIZE ( Pmode ) ) ; bounds = gen_reg_rtx ( BNDmode ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_ldx ( bounds , ldx_addr , ptr ) : gen_bnd32_ldx ( bounds , ldx_addr , ptr ) ) ; } emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr , bounds ) ) ; bnd_reg ++


<s> if ( arm_describe_resolver ( fndecl ) == arm_cde_resolver ) return arm_resolve_cde_builtin ( loc , fndecl , arglist ) ; return NULL_TREE


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( isKill ) ) . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned int __Y ) { return ( ~ __X & __Y )


<s> for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + WhichResult ) ) return false ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ; return


<s> unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> setDesc ( TII . get (


<s> return ( __m512d ) __builtin_ia32_sqrtpd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_undefined_pd ( ) , (


<s> emit_insn ( gen_rtx_SET ( gen_rtx_REG ( BImode , SR_F_REGNUM ) , gen_rtx_fmt_ee ( code , BImode ,


<s> static bool isBroadcastShuffleMask ( ArrayRef


<s> if ( CROSSING_JUMP_P ( followee ) && !

CROSSING_JUMP_P ( follower ) ) return false ;


<s> if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return BB


<s> bool i386_pe_type_dllimport_p ( tree decl ) { gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE


<s> LDTLSCleanup ( ) : MachineFunctionPass (


<s> bool fp = false ; if ( vectype != NULL ) fp = FLOAT_TYPE_P ( vectype ) ; switch ( type_of_cost ) { case scalar_stmt : return fp ? costs -> scalar_fp_stmt_cost : costs -> scalar_int_stmt_cost ; case scalar_load : return costs -> scalar_load_cost ; case scalar_store : return costs -> scalar_store_cost ; case vector_stmt : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vector_load : return costs -> vec_align_load_cost ; case vector_store : return costs -> vec_store_cost ; case vec_to_scalar : return costs -> vec_to_scalar_cost ; case scalar_to_vec : return costs -> scalar_to_vec_cost ; case unaligned_load : return costs -> vec_unalign_load_cost ; case unaligned_store : return costs ->


<s> if ( Subtarget . hasDirectMove ( ) && Subtarget . is<ISA_LIT>64 ( ) ) return LowerFP_TO_INTDirectMove ( Op , DAG , dl ) ; ReuseLoadInfo RLI ; LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI

, RLI . Alignment , RLI . MMOFlags ( ) , RLI . AAInfo , RLI . Ranges ) ;


<s> if ( ( Subtarget . hasFastVectorShiftMasks ( ) && VT . isVector ( ) ) || ( Subtarget . hasFastScalarShiftMasks ( ) && ! VT . isVector ( ) ) ) { return N -> getOperand ( <NUM_LIT> ) == N ->

getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;


<s> static bool callsShareTOCBase ( const Function * Caller , SDValue Callee , const TargetMachine & TM ) { const <ISA_LIT>Subtarget * STICaller = & TM . getSubtarget < <ISA_LIT>Subtarget > ( * Caller ) ; assert ( ! STICaller -> isUsingPCRelativeCalls ( ) && <STR_LIT> ) ; GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; if ( ! G ) return false ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , GV ) ) return false ; const Function * F = dyn_cast < Function > ( GV ) ; const GlobalAlias * Alias = dyn_cast < GlobalAlias > ( GV ) ; if ( Alias ) { const GlobalObject * GlobalObj = Alias -> getBaseObject ( ) ; F = dyn_cast < Function > ( GlobalObj ) ; } if ( ! F ) return false ; const <ISA_LIT>Subtarget * STICallee = & TM . getSubtarget < <ISA_LIT>Subtarget > ( * F ) ; if ( STICallee -> isUsingPCRelativeCalls ( ) ) return false ; if ( CodeModel :: Medium == TM . getCodeModel ( ) || CodeModel :: Large == TM . getCodeModel ( ) ) return true ; if ( ! GV -> isStrongDefinitionForLinker ( ) ) return false ; if ( TM . getFunctionSections ( ) || GV -> hasComdat ( ) || Caller -> hasComdat ( ) || GV -> getSection ( ) != Caller -> getSection ( ) ) return false ; if ( const auto * F = dyn_cast <


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand

( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ;


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; return vectorCostAdjustment ( LT . first , Instruction :: ShuffleVector


<s> addPass ( createInterleavedAccessPass ( ) ) ; addPass ( create<ISA_LIT>PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else


<s> void addVectorIndexBOperands ( MCInst & Inst , unsigned


<s> if ( ! ( Ty -> getNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , {

Ptr , Builder . getInt32 ( Increment ) , Input , Mask } ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVZIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned CountD = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned CountS = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned InVal = <NUM_LIT> + CountS ; ShuffleMask [ CountD ] = InVal ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask


<s> unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent (


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic )

|| ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ;


<s> if ( ! FPIsUsed ) return false ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > I = df_ext_begin ( Entry , Processed ) , E = df_ext_end ( Entry , Processed ) ; I != E ; ++ I ) Changed |= processBasicBlock ( MF , * * I ) ; return Changed


<s> if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump


<s> static bool DisassembleThumbFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO Builder ) { uint16_t HalfWord = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( HalfWord == <NUM_LIT> ) { uint16_t op = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; return DisassembleThumb1 ( op , MI , Opcode ,

insn , NumOps , NumOpsAdded , Builder ) ;


<s> __builtin_mve_vst1q_uv4si ( ( __builtin_neon_si * )


<s> if ( llvm :: isNullConstant ( Idx ) && ! <STR_LIT> ( Op ) && ! <STR_LIT> ( Op ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Extract ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || isNullConstant ( Idx ) ) && ( User -> getOpcode ( ) !=

<STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr ,


<s> return ( __m256i ) __builtin_ia32_movdqa64load256_mask ( ( __v4di * ) __P , ( __v4di ) _mm256_setzero_si256 ( ) , (


<s> Value * VecZero = Constant :: getNullValue ( V256I32Ty ) ; for ( auto UI = TileZero -> use_begin ( ) , UE = TileZero -> use_end ( ) ; UI != UE ; ) { Instruction * I = cast < Instruction > ( ( UI ++ ) -> getUser ( ) ) ; Value * Vec ; if ( match ( I , m_BitCast ( m_Value ( Vec ) ) ) ) { I -> replaceAllUsesWith ( VecZero ) ; I -> eraseFromParent ( ) ; } } TileZero -> eraseFromParent ( ) ; return true


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler ::


<s> int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) { offset_rtx = gen_rtx_REG ( Pmode , FIXED_SCRATCH ) ; emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx =


<s> if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , KnownRHS ) ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode


<s> bool in<ISA_LIT>16Mode ( ) const { return STI . getFeatureBits ( )


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) ; if ( RegCtx . AddressReg != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . addressReg ( <STR_LIT> ) ) ) ; } const std :: string & Fn = FuncName ( AccessSize , IsWrite ) ; MCSymbol * FnSym = Ctx . GetOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: Create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) .


<s> last_scheduled_insn = sc -> last_scheduled_insn ; memcpy ( rws_sum , sc -> rws_sum , sizeof ( rws_sum ) ) ; memcpy ( rws_insn , sc -> rws_insn , sizeof ( rws_insn


<s> if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeVCVTImmOperand ( Inst , imm6 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize - AlignOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; NumFrameExtraProbe ++ ; CurrentOffset = StackProbeSize - AlignOffset ; } while ( CurrentOffset + StackProbeSize < Offset ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; NumFrameExtraProbe


<s> for ( unsigned MaybeReg : AvailableRegs ) { if ( MaybeReg ) { AvailableReg = MaybeReg ; break ; } } if ( ! AvailableReg ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const char * Symbol = getIndirectThunkSymbol ( Subtarget , AvailableReg ) ; BuildMI ( * BB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , AvailableReg ) . addReg ( CalleeVReg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToES ( Symbol ) ; MI . setDesc ( TII -> get ( Opc ) ) ; MachineInstrBuilder ( * BB -> getParent ( ) , & MI ) . addReg ( AvailableReg , RegState :: Implicit | RegState :: Kill ) ; return BB


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( CurrentFnSym


<s> Value * <ISA_LIT>IREmitter :: visitVSRI ( const SDNode *


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; return *


<s> LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false


<s> case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) ) ; Type * IdxTy = * GTI ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) ) - <NUM_LIT> ; if ( ShiftAmt == <NUM_LIT> || ShiftAmt > <NUM_LIT> ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( <NUM_LIT> ) -> getType ( ) ) continue ; default : return


<s> if ( SymLoc == <ISA_LIT>MCExpr :: VK_ABS && IsNC ) return ELF :: R_AARCH64_LDST64_ABS_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_GOT && IsNC ) return ELF :: R_AARCH64_LD64_GOT_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_DTPREL && ! IsNC ) return ELF :: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_DTPREL && IsNC ) return ELF :: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_TPREL && ! IsNC ) return ELF :: R_AARCH64_TLSLE_LDST64_TPREL_LO12 ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_TPREL && IsNC ) return ELF :: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_GOTTPREL && IsNC ) return ELF :: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_TLSDESC && IsNC ) return ELF :: R_AARCH64_TLSDESC_LD64_LO12_NC ; report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT> : if ( SymLoc == <ISA_LIT>MCExpr :: VK_ABS && IsNC ) return ELF :: R_AARCH64_LDST128_ABS_LO12_NC ; report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT> : if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G3 ) return ELF :: R_AARCH64_MOVW_UABS_G3 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G2 ) return ELF :: R_AARCH64_MOVW_UABS_G2 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G2_S ) return ELF :: R_AARCH64_MOVW_SABS_G2 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) return ELF :: R_AARCH64_MOVW_UABS_G2_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G1 ) return ELF :: R_AARCH64_MOVW_UABS_G1 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G1_S ) return ELF :: R_AARCH64_MOVW_SABS_G1 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) return ELF :: R_AARCH64_MOVW_UABS_G1_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G0 ) return ELF :: R_AARCH64_MOVW_UABS_G0 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G0_S ) return ELF :: R_AARCH64_MOVW_SABS_G0 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) return ELF :: R_AARCH64_MOVW_UABS_G0_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) return ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G2 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) return ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G1 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) return ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) return ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G0 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) return ELF :: R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_G2 ) return ELF :: R_AARCH64_TLSLE_MOVW_TPREL_G2 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_G1 ) return ELF :: R_AARCH64_TLSLE_MOVW_TPREL_G1 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) return ELF :: R_AARCH64_TLSLE_MOVW_TPREL_G1_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_G0 ) return ELF :: R_AARCH64_TLSLE_MOVW_TPREL_G0 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) return ELF ::


<s> bool mayNeedRelaxation ( const MCInst & Inst ,

const MCSubtargetInfo & STI ) const override {


<s> static bool runTIs ( MachineModuleInfo & MMI , MachineFunction & MF , std :: tuple < ThunkInserterT ... > & ThunkInserters ) { bool Modified = false ; ( void ) std :: initializer_list


<s> MachineInstr * MI = MRI -> getVRegDef ( SReg ) ; if ( ! MI ) return <STR_LIT> ; MachineOperand * MO = MI -> findRegisterDefOperand ( SReg ) ; if ( ! MO ) return <STR_LIT> ; assert ( MO -> isReg ( ) && <STR_LIT> ) ; if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , &


<s> vmlsl_u16 ( uint32x4_t a , uint16x4_t b , uint16x4_t c ) { uint32x4_t result


<s> ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : Res = LowerSADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT>


<s> LDSection * getTextSection ( ) const


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base ,


<s> } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , Ops ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; unsigned NumOps = Call . getNode ( ) -> getNumOperands ( ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode


<s> i = <NUM_LIT> ; if ( mode == V16QImode ) { mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; i += nelt_mode ; if ( i + nelt_v8 < length && i + nelt_v16 > length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - nelt_mode ) ) ) ; offset += length - nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ; else if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ; else set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; return true ; } mode = V8QImode ; nelt_mode = GET_MODE_NUNITS ( mode ) ; reg = gen_lowpart ( V8QImode , reg ) ; } for ( ; ( i + nelt_mode <= length ) ; i += nelt_mode ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , mode , addr , offset + i ) ; if ( MEM_ALIGN ( mem ) >= <NUM_LIT> * BITS_PER_WORD ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storev8qi ( mem , reg ) ) ; } if ( i + UNITS_PER_WORD == length ) { addr = plus_constant ( Pmode , dst , i - UNITS_PER_WORD ) ; offset += i - UNITS_PER_WORD ; mem = adjust_automodify_address ( dstbase , mode , addr , offset ) ; if ( align > UNITS_PER_WORD ) set_mem_align ( mem , BITS_PER_UNIT * UNITS_PER_WORD ) ; emit_insn ( gen_unaligned_storev8qi ( mem , reg ) ) ; } else if ( i < length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - nelt_mode ) ) ) ; offset += length - nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align


<s> unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; <STR_LIT> ShOp = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case


<s> SDValue <ISA_LIT>TargetLowering :: FinishCall ( CallingConv :: ID CallConv , const SDLoc & dl , bool isTailCall , bool isVarArg , bool isPatchPoint , bool hasNest , SelectionDAG & DAG , SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > & RegsToPass , SDValue InFlag , SDValue Chain , SDValue CallSeqStart , SDValue & Callee , int SPDiff , unsigned NumBytes , const SmallVectorImpl < <STR_LIT> > & Ins , SmallVectorImpl < SDValue > & InVals , ImmutableCallSite * CS ) const { std :: vector < EVT > NodeTys ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned CallOpc = PrepareCall ( DAG , Callee , InFlag , Chain , CallSeqStart , dl , SPDiff , isTailCall , isPatchPoint , hasNest , RegsToPass , Ops , NodeTys , CS , Subtarget ) ; if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! isPatchPoint ) { if ( CallOpc == <STR_LIT>


<s> else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Z ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Zy ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode


<s> rettype = unsigned_type_node ; argtype = gpr_type_node ; } else { rettype = unsigned_type_node ; argtype = unsigned_type_node ; } if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ; } if ( d -> name == <NUM_LIT> ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , ( long unsigned ) i ) ; continue ; } op [ nopnds ++ ] = ( void_func ) ? void_type_node : rettype ; if ( attr_args == RS6000_BTC_UNARY ) op [ nopnds ++ ] = argtype ; else if ( attr_args == RS6000_BTC_BINARY ) { op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; } else if ( attr_args == RS6000_BTC_TERNARY ) { op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; } switch ( nopnds


<s> void <ISA_LIT>InstPrinter :: printUnsignedImm ( const MCInst * MI , int OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) O << ( unsigned short int ) MO . getImm ( ) ; else printOperand ( MI , OpNum


<s> static int get_element_number ( tree vec_type , tree arg ) { unsigned HOST_WIDE_INT elt , max = TYPE_VECTOR_SUBPARTS ( vec_type ) - <NUM_LIT> ; if ( ! tree_fits_uhwi_p ( arg ) || ( elt = tree_to_uhwi ( arg ) , elt > max ) ) { error ( <STR_LIT> , max ) ; return <NUM_LIT>


<s> case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op0Reg = emitAnd_ri ( <STR_LIT> , Op0Reg , Op0IsKill , Mask ) ; Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg , Op1IsKill , Mask ) ; Op0IsKill = Op1IsKill = true ; } unsigned ResultReg = fastEmitInst_rr ( Opc , RC , Op0Reg , Op0IsKill


<s> if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ; MI . getOperand ( OpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op


<s> static unsigned offsetMinAlign ( const MachineInstr & MI ) { unsigned OpC = MI . getOpcode


<s> vst3_p16 ( poly16_t * __a , poly16x4x3_t val ) { __builtin_aarch64_simd_ci __o ; poly16x8x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [


<s> if ( Kind == TTI :: SK_Transpose || Kind == TTI :: SK_Select || Kind == TTI :: SK_PermuteSingleSrc ) { static const CostTblEntry ShuffleTbl [ ] = { { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL ,


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: SwiftTail ) return CSR_<ISA_LIT>_AAPCS_SwiftTail_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv

:: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ;


<s> return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> break ; } } SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; if ( VT . isSimple ( ) && VT . isVector ( ) && resolveTargetShuffleInputs ( Op , ShuffleOps , ShuffleMask , DAG , Depth ) ) { int NumOps = ShuffleOps . size ( ) ; if ( ShuffleMask . size ( ) == ( unsigned ) NumElts && llvm :: all_of ( ShuffleOps , [ VT ] ( SDValue V ) { return VT . getSizeInBits ( ) == V . getValueSizeInBits ( ) ; } ) ) { APInt IdentityOp = APInt :: getAllOnesValue ( NumOps ) ; bool AllUndef = true ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = ShuffleMask [ i ] ; if ( SM_SentinelUndef == M || ! DemandedElts [ i ] ) continue ; AllUndef = false ; int Op = M / NumElts ; int Index = M


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT>


<s> return isSimpleMove ( MI , FrameIndex , <STR_LIT>


<s> void <ISA_LIT>TargetAsmStreamer :: emitObjectArch ( unsigned Arch ) { OS << <STR_LIT> << GetArchName (


<s> bool <ISA_LIT>TargetLowering :: areJTsAllowed ( const Function * Fn


<s> case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return <NUM_LIT> ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return <NUM_LIT> ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return <NUM_LIT> ; case PROCESSOR_POWER8


<s> break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> transferSuccessors ( BB ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned scratch = RegInfo . createVirtualRegister ( <STR_LIT> ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB )


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return


<s> return SelectAddrRI12 ( Op , Addr , Base , Disp , true


<s> return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo -> getSlotSize


<s> t = __ev_mwhsmi ( a , b ) ; return __ev_addssiaaw (


<s> return ( __m256i ) __builtin_ia32_loaddquqi256_mask ( ( const char * ) __P , ( __v32qi ) __W ,