<s> if ( ! isGPRMem ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . ShiftType != <STR_LIT> || Memory . ShiftImm != <NUM_LIT>

|| Memory . Alignment != <NUM_LIT> ) return false ;


<s> return ( __m512i ) __builtin_ia32_cvtps2udq512_mask ( ( __v16sf ) __A , ( __v16si )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned B = Value & <NUM_LIT> ; B |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( B


, ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> MachineInstr * MI = & * MBIter ; unsigned PredReg = <NUM_LIT> ; DebugLoc dl = MI -> getDebugLoc ( ) ; <STR_LIT> Pred = getVPTInstrPredicate ( * MI , PredReg ) ; assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } MachineInstrBuilder MIBuilder = BuildMI ( Block , MBIter , dl , TII -> get ( <STR_LIT>


<s> if ( count_op != count_ideal ) return false ; for ( i = <NUM_LIT> ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , <NUM_LIT> , i ) ; rtx elt_ideal = XVECEXP ( ideal , <NUM_LIT> , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return


<s> static unsigned int rest_of_handle_insert_vzeroupper ( void ) { for ( int i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ; g -> get_passes ( ) -> execute_pass_mode_switching ( ) ; df_analyze ( ) ; return <NUM_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM ,

CM , OL ) , InstrInfo ( Subtarget ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) :


<s> static const char * csky_mangle_type ( const_tree type ) { if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> && TYPE_MAIN_VARIANT ( type ) != float16_type_node ) return <STR_LIT> ; return NULL


<s> if ( ! rs6000_tls_symbol ) rs6000_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; return


<s> rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; scratch1 = gen_reg_rtx ( mode0 ) ; scratch2 = gen_reg_rtx ( mode0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , scratch1 , scratch2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF . RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF . CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; MF . RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor ( BB ) ; JTBB -> addSuccessor ( NewBB )


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> )


<s> return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> ,


<s> if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr

( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ;


<s> VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; } if ( VRegAndVal ) C = VRegAndVal -> Value . getSExtValue ( ) ; break ; } case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_SHL : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( VRegAndVal ) C = VRegAndVal -> Value . getSExtValue ( ) ; break ; } } if ( ! C || ! TestReg . isValid ( ) ) break ; Register NextReg ; unsigned TestRegSize = MRI . getType ( TestReg ) . getSizeInBits ( ) ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : if ( ( * C >> Bit ) & <NUM_LIT> ) NextReg = TestReg ; break ; case TargetOpcode :: G_SHL : if ( * C <= Bit && ( Bit - * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit - * C ; } break ; case TargetOpcode :: G_ASHR : NextReg = TestReg ; Bit = Bit + * C ; if ( Bit >= TestRegSize ) Bit = TestRegSize - <NUM_LIT> ; break ; case TargetOpcode :: G_LSHR : if ( ( Bit + * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit


<s> if ( NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes & ( (


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI


<s> union { qword q ; signed char c [ <NUM_LIT> ] ; }


<s> switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default : return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( )


<s> if ( Flags . getNode ( ) ) { SDValue Cond = DAG . getConstant ( CC , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Chain , Dest , Cond ,


<s> bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; return true


<s> default : return true ; case FusionFeature :: FK_AddiLoad : { const MachineOperand & RA = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! RA . isReg ( ) ) return true ; return Register :: isVirtualRegister ( RA . getReg ( ) ) || ( RA . getReg ( ) != <STR_LIT> && RA . getReg ( ) != <STR_LIT> ) ; } case FusionFeature :: FK_AddisLoad : { const MachineOperand & RT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! RT . isReg ( ) ) return true ; if ( ! Register :: isVirtualRegister ( RT . getReg ( ) ) ) if ( ! matchingRegOps ( SecondMI , <NUM_LIT> , SecondMI , <NUM_LIT> ) || ( RT . getReg ( ) == <STR_LIT> || RT . getReg ( ) == <STR_LIT> ) ) return false ; const MachineOperand & SI = FirstMI . getOperand ( <NUM_LIT> ) ; if ( ! SI . isImm ( ) ) return true ; int64_t Imm = SI . getImm ( ) ; if ( ( ( Imm & <NUM_LIT> ) != <NUM_LIT> ) && ( ( Imm & <NUM_LIT> ) != <NUM_LIT> ) )


<s> MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> addRegisterKilled ( <STR_LIT> , & TII -> getRegisterInfo ( ) ) ; MI -> eraseFromParent (


<s> if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC

== CallingConv :: HiPE ) return CSR_NoRegs_RegMask ;


<s> pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , <NUM_LIT> ) ) == SImode


<s> if ( ST -> hasMVEIntegerOps ( ) && ValTy -> isVectorTy ( ) && ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) && cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) > <NUM_LIT> ) { FixedVectorType * VecValTy = cast < FixedVectorType > ( ValTy ) ; FixedVectorType * VecCondTy = dyn_cast_or_null < FixedVectorType > ( CondTy ) ; if ( ! VecCondTy ) VecCondTy = cast < FixedVectorType > ( CmpInst :: makeCmpResultType ( VecValTy ) ) ; if ( Opcode == Instruction :: FCmp && ! ST -> hasMVEFloatOps ( ) ) { return BaseT :: getScalarizationOverhead ( VecValTy , false , true ) + BaseT :: getScalarizationOverhead ( VecCondTy , true , false ) + VecValTy -> getNumElements ( ) * getCmpSelInstrCost ( Opcode , ValTy -> getScalarType ( ) , VecCondTy -> getScalarType ( ) , VecPred , CostKind , I ) ; } std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; int BaseCost = ST -> getMVEVectorCostFactor ( CostKind ) ; if ( LT . second . getVectorNumElements ( ) > <NUM_LIT> ) { if ( LT . first > <NUM_LIT> ) return LT . first * BaseCost + BaseT :: getScalarizationOverhead ( VecCondTy , true , false ) ; return BaseCost ; } } int BaseCost = <NUM_LIT> ; if ( ST -> hasMVEIntegerOps ( ) && ValTy -> isVectorTy ( ) ) BaseCost =


<s> if ( VT . isScalableVector ( ) && ! isTypeLegal ( VT ) && isTypeLegal ( SrcVT ) ) { assert ( ! VT . isFloatingPoint ( ) && SrcVT . isFloatingPoint ( ) && <STR_LIT> ) ; SDValue CastResult = getSVESafeBitCast ( getSVEContainerType ( VT ) , Op , DAG ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , CastResult ) ) ; return ; } if ( VT != <STR_LIT> || ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) ) return ; Op = SDValue ( DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Op , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; } SDValue Val ; if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg (

) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumVecs + <NUM_LIT> ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , VLD -> getDebugLoc ( ) , SDTys , Ops , <NUM_LIT> , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI


<s> if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 ,


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; unsigned CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( Opcode != <STR_LIT> ) CallType = Opcode ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } MFI -> setAdjustsStack ( true ) ; SDValue Flag = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , dl , ReturnReg ,


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget . isTargetGlibc ( ) ) TargetLowering ::


<s> gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode


<s> pcum -> aapcs_reg = gen_rtx_REG ( mode , V0_REGNUM + nvrn ) ; } else { rtx par ; int i ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tmp = gen_rtx_REG ( pcum -> aapcs_vfp_rmode , V0_REGNUM + nvrn + i ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = tmp ; } pcum -> aapcs_reg = par ; } return ; } else { pcum -> aapcs_nextnvrn = NUM_FP_ARG_REGS ; goto on_stack ; } } ncrn = pcum -> aapcs_ncrn ; nregs = size / UNITS_PER_WORD ; if ( allocate_ncrn && ( ncrn + nregs <= NUM_ARG_REGS ) ) { gcc_assert ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || nregs == <NUM_LIT> ) ; if ( nregs == <NUM_LIT> && ncrn % <NUM_LIT> && aarch64_function_arg_alignment ( mode , type ) == <NUM_LIT> * BITS_PER_UNIT ) { ++ ncrn ; gcc_assert ( ncrn + nregs <= NUM_ARG_REGS ) ; } if ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || GET_MODE_CLASS ( mode ) == MODE_INT ) pcum -> aapcs_reg = gen_rtx_REG ( mode , R0_REGNUM + ncrn ) ; else { rtx par ; int i ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tmp = gen_rtx_REG ( word_mode , R0_REGNUM + ncrn + i ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * UNITS_PER_WORD ) ) ; XVECEXP ( par , <NUM_LIT> , i


<s> bool IsImm8 = int8_t ( Imm ) == Imm ; bool IsImm16 = int16_t ( Imm & ~ <NUM_LIT> ) == Imm ; if ( std :: is_same < int8_t , std :: make_signed_t < T >> :: value ) return IsImm8 || uint8_t ( Imm ) == Imm ; if ( std :: is_same < int16_t , std :: make_signed_t < T >> :: value ) return IsImm8 || IsImm16 || uint16_t ( Imm & ~


<s> bool aarch64_sve_dup_immediate_p ( rtx x ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( val & <NUM_LIT> ) return IN_RANGE ( val , -


<s> if ( Res . getSymB ( ) != nullptr ) return false ; if ( Res . getConstant ( ) != <NUM_LIT> ) return ABI . IsN32 ( ) || ABI . IsN64 ( ) ; return


<s> return ( uint32x4_t ) __builtin_aarch64_uminv4si ( ( int32x4_t )


<s> Vec = concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } else { Vec = DAG . getConstant ( Ones , dl , <STR_LIT> ( <STR_LIT> , NumElts ) ) ; } return DAG . getBitcast ( VT ,


<s> DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , getSetCCResultType ( Ty ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Cond , Op . getOperand ( <NUM_LIT> ) , Op . getOperand


<s> return Kind == Immediate && isUInt < <NUM_LIT>


<s> parts [ <NUM_LIT> ] = gen_rtx_REG ( upper_mode , REGNO ( operand ) + <NUM_LIT> ) ; } else if ( offsettable_memref_p ( operand ) ) { operand = adjust_address ( operand , DImode , <NUM_LIT> ) ; parts [ <NUM_LIT> ] = operand ; parts [ <NUM_LIT> ] = adjust_address ( operand , upper_mode , <NUM_LIT> ) ; } else if ( GET_CODE ( operand ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long l [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , operand ) ; real_to_target ( l , & r , mode ) ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & ( ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) + ( ( ( ( HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) << <NUM_LIT> ) , DImode ) ; else parts [ <NUM_LIT> ] = immed_double_const ( l [ <NUM_LIT> ] , l [ <NUM_LIT> ] , DImode ) ; if ( upper_mode == SImode ) parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; else if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & ( ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) + ( ( ( ( HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) << <NUM_LIT> ) , DImode ) ; else parts [ <NUM_LIT> ] = immed_double_const ( l [ <NUM_LIT> ] , l [ <NUM_LIT> ] , DImode ) ; } else gcc_unreachable (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( StoreInst -> killsRegister ( <STR_LIT> ) ) StoreInst -> clearRegisterKills ( <STR_LIT> , & TRI ) ; if ( StoreInst -> killsRegister ( PACStack :: CR ) ) StoreInst -> clearRegisterKills ( PACStack :: CR , & TRI ) ; break ; default : break ; } } ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addUse ( PACStack :: CR ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString (

) == <STR_LIT> ) insertCollisionProtection ( MBB , MBBI , DL , MachineInstr :: FrameSetup ) ;


<s> case CONST : operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case PLUS : arg1 = XEXP ( addr , <NUM_LIT> ) ; arg2 = XEXP ( addr , <NUM_LIT> ) ; if ( CONSTANT_P ( arg1 ) ) base = arg2 , offset = arg1 ; else base = arg1 , offset = arg2 ; gcc_assert ( GET_CODE ( base ) == REG ) ; if ( GET_CODE ( offset ) == REG ) { int reg_offset = REGNO ( offset ) ; int reg_base = REGNO ( base ) ; int reg_dest = REGNO ( operands [ <NUM_LIT> ] ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest + <NUM_LIT> , reg_base , reg_offset ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest , reg_dest + <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest + <NUM_LIT> , reg_dest + <NUM_LIT> ) ; } else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; if ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( base ) ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands


<s> int arm_attr_length_move_neon ( rtx_insn * insn ) { rtx reg , mem , addr ; int load ; machine_mode mode ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ <NUM_LIT> ] ) && REG_P ( recog_data . operand [ <NUM_LIT> ] ) ) { mode = GET_MODE ( recog_data . operand [ <NUM_LIT> ] ) ; switch ( mode ) { case E_EImode : case E_OImode : return <NUM_LIT> ; case E_CImode : return <NUM_LIT> ; case E_XImode : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } load = REG_P ( recog_data . operand [ <NUM_LIT> ] ) ; reg = recog_data . operand [ ! load ] ; mem = recog_data . operand [ load


<s> if ( CPEs [ J ] . RefCount == <NUM_LIT> && CPEs [ J ] . CPEMI ) { removeDeadCPEMI ( CPEs [ J ] . CPEMI ) ; CPEs [ J ] . CPEMI = nullptr ; MadeChange =


<s> } unsigned RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return false ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned Opc = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( LHSReg , getKillRegState ( LHSIsKill ) ) . addReg ( RHSReg , getKillRegState ( RHSIsKill ) ) ; return true


<s> if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( )


<s> BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize < <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( uint32_t ( ~ <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ) ; else if ( BitSize == <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( ~ uint32_t ( <NUM_LIT> ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2 ) . addImm ( - <NUM_LIT> ) ; } } else if ( BinOpcode ) BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; else if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> - BitSize ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . addOperand ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB )


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind , I ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( isa < FixedVectorType > ( ValTy ) && ISD == <STR_LIT> ) { const int AmortizationCost = <NUM_LIT> ; if ( VecPred == CmpInst :: BAD_ICMP_PREDICATE && I && I -> getType ( ) == ValTy ) { CmpInst :: Predicate CurrentPred ; if ( match ( I , m_Select ( m_Cmp ( CurrentPred , m_Value ( ) , m_Value ( ) ) , m_Value ( ) , m_Value ( ) ) ) ) VecPred = CurrentPred ; } if ( CmpInst :: isIntPredicate ( VecPred ) || VecPred == CmpInst :: FCMP_OLE || VecPred == CmpInst :: FCMP_OLT || VecPred == CmpInst :: FCMP_OGT || VecPred == CmpInst :: FCMP_OGE || VecPred == CmpInst :: FCMP_OEQ || VecPred == CmpInst :: FCMP_UNE ) { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const auto ValidFP16MinMaxTys = { <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) || ( ST -> hasFullFP16 ( ) && any_of ( ValidFP16MinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) ) return LT . first ; } static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost

} , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , {


<s> rtx reg = gen_rtx_REG ( Pmode , regno ) ; emit_move_insn ( reg


<s> SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue (


<s> const MCExpr * Expr ; if ( parseToken ( AsmToken :: Comma ) || check ( getParser ( ) . parseExpression ( Expr ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer (


<s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>


<s> for ( auto & MI : MBB ) { if ( <STR_LIT> ( MI . getDesc ( ) . TSFlags ) < <NUM_LIT> ) continue ; const DILocation * DI = MI . getDebugLoc ( ) ; if ( ! DI ) { DI = ReferenceDI ; } Location L = diToLocation ( DI ) ; DenseSet < unsigned > & Set = Seen [ L ] ; const std :: pair < DenseSet < unsigned > :: iterator , bool > TryInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; if ( ! TryInsert . second ) { unsigned BF , DF , CI = <NUM_LIT> ; DILocation :: decodeDiscriminator ( DI -> getDiscriminator ( ) , BF , DF , CI ) ; Optional < unsigned > EncodedDiscriminator = DILocation :: encodeDiscriminator ( MemOpDiscriminators [ L ] + <NUM_LIT> , DF , CI ) ; if ( ! EncodedDiscriminator ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << DI -> getFilename ( ) << <STR_LIT> << DI -> getLine ( ) << <STR_LIT> << DI -> getColumn ( ) << <STR_LIT> ) ; continue ; } ++ MemOpDiscriminators [ L ] ; DI = DI -> cloneWithDiscriminator ( EncodedDiscriminator . getValue ( ) ) ; assert ( DI && <STR_LIT> ) ; updateDebugInfo ( & MI , DI ) ; Changed = true ; std :: pair < DenseSet < unsigned > :: iterator , bool > MustInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; ( void ) MustInsert ; assert ( MustInsert . second


<s> MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG ) ) return DivRem8 ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI


<s> if ( ! MI ) return false ; if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) ==

Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> return Kind == <STR_LIT> || Kind == <STR_LIT> || Kind


<s> return ( int32x4_t ) __builtin_neon_vsubwsv4hi ( __a ,


<s> void <ISA_LIT>IntelInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << formatImm ( ( int64_t ) Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O <<


<s> if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return LOW_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return MIDDLE_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return HIGH_REGS ; else if ( regno == <NUM_LIT> ) return R15_TA_REG ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT>


<s> MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , FIdx , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , Store , FIdx , MachinePointerInfo


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRegs


<s> if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Val ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ) return

CreateTLSReg ( SRE , S , E , Is<ISA_LIT>64 ) ;


<s> static bool ContainsReg ( const ArrayRef < std :: pair < unsigned , bool >> & Regs , unsigned Reg ) { for ( const std :: pair < unsigned , bool > & R

: Regs ) if ( R . first == Reg ) return true ;


<s> tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( ) , cmpInst ) ; tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( ) , copyMoveM ) ; tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( ) , copyMoveD ) ; } MachineInstr * returnInstr = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; tzdcRecoveryMBB -> push_back ( returnInstr ) ; MachineInstr * MInop = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> )


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RET_REG || ( TARGET_SH2E


<s> if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return cfun -> machine -> frame . frame_size ==


<s> int i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order


<s> bool mips_const_vector_bitimm_clr_p ( rtx op , machine_mode mode ) { if ( GET_CODE ( op ) == CONST_VECTOR && op != CONSTM1_RTX ( mode ) ) { unsigned HOST_WIDE_INT val = ~ UINTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) ; int vlog2 = exact_log2 ( val & GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ) ; if ( vlog2 != - <NUM_LIT> ) { gcc_assert ( GET_MODE_CLASS ( mode


<s> if ( ! cfun ) return ix86_abi ; return cfun -> machine


<s> auto setCsectAlignment = [ this ] ( const GlobalObject * GO ) { if ( GO -> isDeclarationForLinker ( ) ) return ; SectionKind GOKind = getObjFileLowering ( ) . getKindForGlobal ( GO , TM ) ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GO , GOKind , TM ) ) ; Align GOAlign = getGVAlignment ( GO , GO -> getParent ( ) -> getDataLayout ( ) ) ; if ( GOAlign > Csect -> getAlignment ( ) ) Csect -> setAlignment ( GOAlign ) ; } ; for ( const auto & G : M . globals ( ) ) { if ( isSpecialLLVMGlobalArrayToSkip ( & G )


<s> uint64_t getPC32DBLTLSEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> ,


<s> Parser . Lex ( ) ; SMLoc StartInBrac = Tok . getLoc ( ) ; IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( <ISA_LIT>Operand * Err = ParseIntelExpression ( SM , End ) ) return Err ; const MCExpr * Disp ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } else { Disp = MCConstantExpr :: Create ( SM . getImm ( ) , getContext ( ) ) ; } if ( Tok . getString ( ) . startswith ( <STR_LIT> ) ) { const MCExpr * NewDisp ; if ( <ISA_LIT>Operand * Err = ParseIntelDotOperator ( Disp , NewDisp ) ) return Err ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm


<s> unsigned Bits , Scale ; switch ( Opc ) { case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; default : assert ( <NUM_LIT> ) ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; return MaxOffs


<s> return ( __m128d ) __builtin_ia32_cmpnlesd ( ( __v2df )


<s> return ( __m256i ) __builtin_ia32_pmovzxdq256 (


<s> if ( DEFAULT_ABI == ABI_V4 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM && flag_pic == <NUM_LIT> ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( DEFAULT_ABI == ABI_V4 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM && flag_pic == <NUM_LIT> ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_really_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( DEFAULT_ABI == ABI_DARWIN && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_really_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( TARGET_TOC && TARGET_MINIMAL_TOC ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( TARGET_SPE ) { global_regs [ SPEFSCR_REGNO ] = <NUM_LIT> ; fixed_regs [ <NUM_LIT> ] = call_used_regs [ <NUM_LIT> ] = call_really_used_regs [ <NUM_LIT> ] = <NUM_LIT> ; } if ( ! TARGET_ALTIVEC && ! TARGET_VSX ) { for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = <NUM_LIT> ; call_really_used_regs [ VRSAVE_REGNO ] = <NUM_LIT> ; } if ( TARGET_ALTIVEC || TARGET_VSX ) global_regs [ VSCR_REGNO ] = <NUM_LIT> ; if ( TARGET_ALTIVEC_ABI ) { for ( i = FIRST_ALTIVEC_REGNO ; i < FIRST_ALTIVEC_REGNO + <NUM_LIT> ; ++ i ) call_used_regs [ i ] = call_really_used_regs [ i ] = <NUM_LIT> ; if ( TARGET_XCOFF ) for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i < FIRST_ALTIVEC_REGNO + <NUM_LIT> ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ]


<s> const unsigned NumElts = VVT . getVectorNumElements ( ) ; const MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( VVT . is256BitVector ( ) || VVT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT ==


<s> MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int Off = Offset ; unsigned i = <NUM_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off


<s> getTargetStreamer ( ) . emitDirectiveCpreturn ( CpSaveLocation , CpSaveLocationIsRegister ) ; return


<s> SUnit * <ISA_LIT>PostRASchedStrategy :: pickNode


<s> return getImm3 ( insn ) << <NUM_LIT> | getImm2 (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) { if ( getRelocationModel ( ) == Reloc :: Default ) setRelocationModel (


<s> return ( __m64 ) __builtin_arm_wsllhi ( (


<s> return m16_check_op ( op , ( - <NUM_LIT> ) <<


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg

, getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> void addCCRAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> static inline void invertBccCondition ( MachineInstr * MI ) { assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = <STR_LIT> (


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> case <STR_LIT> : return SDValue ( SVOp , <NUM_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i !=


<s> DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand (


<s> if ( OffsetOp . isImm ( ) ) { O << OffsetOp . getImm ( ) ; } else { assert ( OffsetOp . isExpr ( ) && <STR_LIT> ) ; printExpr ( OffsetOp . getExpr


<s> <ISA_LIT>SetflagAluCombiner ( ) : MachineFunctionPass


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateVectorList ( unsigned RegNum , unsigned Count , unsigned NumElements , unsigned ElementWidth , RegKind RegisterKind , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_VectorList , Ctx ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList .


<s> static SDValue checkBoolTestSetCCCombine ( SDValue Cmp , <STR_LIT> & CC ) { if ( ! ( Cmp . getOpcode ( ) == <STR_LIT> || ( Cmp . getOpcode ( ) == <STR_LIT> && ! Cmp -> hasAnyUseOfValue ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue Op2 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue SetCC ; const ConstantSDNode * C = nullptr ; bool needOppositeCond = ( CC == <STR_LIT> ) ; bool checkAgainstTrue = false ; if ( ( C = dyn_cast < ConstantSDNode > ( Op1 ) ) ) SetCC = Op2 ; else if ( ( C = dyn_cast < ConstantSDNode > ( Op2 ) ) ) SetCC = Op1 ; else return SDValue ( ) ; if ( C -> getZExtValue ( ) == <NUM_LIT> ) { needOppositeCond = ! needOppositeCond ; checkAgainstTrue = true ; } else if ( C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; bool truncatedToBoolWithAnd = false ; while ( SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> ) { if ( SetCC . getOpcode ( ) == <STR_LIT> ) { int OpIdx = - <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand (


<s> DebugLoc DL = GSDN -> getDebugLoc ( ) ; const GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag , GV ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOLoFlag ) ; SDValue Ptr = LowerLabelRef ( GAHi , GALo , isPIC


<s> if ( ! got_helper_rtx ) { char name [ <NUM_LIT> ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup


<s> MVT VT = N . getSimpleValueType ( ) ; if ( ! getTargetShuffleMask ( N . getNode ( ) , VT , true , Ops , Mask , IsUnary ) ) return false ; SDValue V1 = Ops [ <NUM_LIT> ] ; SDValue V2 = IsUnary ? V1 : Ops [ <NUM_LIT> ] ; V1 = peekThroughBitcasts ( V1 ) ; V2 = peekThroughBitcasts ( V2 ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { Mask [ i ] = SM_SentinelUndef ; continue ; } if ( V . getOpcode ( ) != <STR_LIT>


<s> Register getFramePtr ( ) const { return FramePtr


<s> Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getVectorElementType ( ) , BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue (


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetReorder ( ) { setCanHaveModuleDir ( false


<s> void neg ( ) { asm_fprintf ( t_file , <STR_LIT> ,


<s> MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; MachineInstr * ExtDef = getDefIgnoringCopies ( LHS . getReg ( ) , MRI ) ; if ( ! ExtDef ) return None ; Ext = getExtendTypeForInst ( * ExtDef , MRI ) ; if ( Ext == <STR_LIT> ) return None ; ExtReg = ExtDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { Ext = getExtendTypeForInst ( * RootDef , MRI ) ; if ( Ext == <STR_LIT> ) return None ; ExtReg = RootDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Ext == <STR_LIT> && MRI . getType ( ExtReg ) . getSizeInBits


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & CTX ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands ,


<s> void <ISA_LIT>BankConflictHazardRecognizer :: AdvanceCycle ( ) { Accesses . clear


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) i ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( NumElts + i + Offset ) ) return false ; } return


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) { if ( ( Opcode == Instruction :: Load && isLegalMaskedGather ( SrcVTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && isLegalMaskedScatter ( SrcVTy , Align ( Alignment ) ) ) ) return <NUM_LIT> ; return BaseT :: getGatherScatterOpCost ( Opcode , SrcVTy , Ptr , VariableMask , Alignment , CostKind , I ) ; } assert ( SrcVTy -> isVectorTy ( ) && <STR_LIT> ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( cast < VectorType > ( Ptr -> getType ( ) ) -> getElementType ( ) ) ; assert ( PtrTy &&


<s> if ( ParseRegister ( Reg , DummyLoc , DummyLoc )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : case <STR_LIT> :: ARMV8_7A : case <STR_LIT> :: ARMV9A : case <STR_LIT> :: ARMV9_1A : case <STR_LIT> :: ARMV9_2A : case <STR_LIT> :: ARMV8R : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; } } else if ( NoCrypto ) { switch ( ArchKind ) { default : case <STR_LIT> :: ARMV8_1A : case <STR_LIT> :: ARMV8_2A : case <STR_LIT> :: ARMV8_3A : RequestedExtensions . push_back ( <STR_LIT> )


<s> case FRAME_POINTER_REGNUM : offset = <NUM_LIT> ; break ; case ARG_POINTER_REGNUM : offset = ( cfun -> machine -> frame . total_size - current_function_pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> frame . args_size ; return


<s> void MVEGatherScatterLowering :: lookThroughBitcast ( Value * & Ptr ) { if ( auto * BitCast = dyn_cast < BitCastInst > ( Ptr ) ) { Type * BCTy = BitCast -> getType ( ) ; Type * BCSrcTy = BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( BCTy -> getVectorNumElements ( ) == BCSrcTy -> getVectorNumElements ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA -> getReachingLocalUses ( LoLoop . Dec , <STR_LIT> , Uses ) ; if ( Uses . size ( ) > <NUM_LIT> || ! Uses . count ( LoLoop . End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoLoop . Revert = true ; } LoLoop . CheckLegality ( BBUtils . get ( ) ) ; Expand ( LoLoop ) ; return true


<s> if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , SlotAlign ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MPI , SlotAlign , MachineMemOperand :: MOLoad ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF ) , PtrVT ) ; Align CPAlignment = cast < ConstantPoolSDNode > ( FudgePtr ) -> getAlign ( ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Four , Zero ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , CPAlignment ) ; Chain = Fudge . getValue (


<s> assert ( RegOpcodes && <STR_LIT> ) ; return RegOpcodes [


<s> static void emitShadowCallStackEpilogue ( const TargetInstrInfo & TII , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( -

<NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( Input . getOperand ( <NUM_LIT> ) ) ; SDValue OrigVector = Input . getOperand ( <NUM_LIT> ) ; if ( Idx && VT == OrigVector . getValueType ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > NewMask ( NumElts , - <NUM_LIT> ) ; unsigned ResultInElt = NumElts / <NUM_LIT> ; ResultInElt -= Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; NewMask [ ResultInElt ] = Idx -> getZExtValue ( ) ; return DAG . getVectorShuffle ( VT , dl , OrigVector


<s> static SDValue PerformXORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI .


<s> if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } break ; case BDLMem : if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( HaveReg1 && HaveReg2 ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDRMem : if ( ! HaveReg1 || Reg1 . Group != RegGR ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } LengthReg = <STR_LIT> [ Reg1 . Num ] ; if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } break ; case BDVMem : if ( ! HaveReg1 || Reg1 . Group != RegV ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = <STR_LIT> [ Reg1 . Num ] ; if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } break ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) .


<s> return ( __mmask16 ) __builtin_ia32_kmovw ( ( __mmask16


<s> Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; assert ( getMemOffsetReg ( ) != <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemOffsetReg ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> return ( __m256d ) __builtin_ia32_movapd256_mask ( ( __v4df ) __A , ( __v4df ) _mm256_setzero_pd ( ) ,


<s> mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno )


<s> MCAsmBackend * llvm :: create<ISA_LIT>LEAsmBackend ( const Target & T , StringRef TT ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS (


<s> tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args ,


<s> auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> (


<s> if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool

( DAG . getMachineFunction ( ) ) , <STR_LIT> , <NUM_LIT> ) ;


<s> SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT>


<s> return ( uint32x4_t ) __builtin_neon_vrsrau_nv4si ( ( int32x4_t ) __a , (


<s> void printi16mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> return ( __m512i ) __builtin_ia32_vpclmulqdq_v8di ( ( __v8di ) __A , (


<s> if ( F -> hasFnAttribute ( <STR_LIT> ) && F -> hasFnAttribute ( <STR_LIT> ) ) { removeUseSoftFloat ( * F ) ; continue ; } if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , TM ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V


<s> static MCSubtargetInfo * createMandarinMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; InitMandarinMCSubtargetInfo ( X , TT , CPU


<s> bool isCoprocNum ( ) const { return Kind


<s> <STR_LIT> <ISA_LIT>InstrInfo :: getBranchInfo ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand (


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; Check ( S , DecodeGPRwithZRRegisterClass ( Inst , RegNo


<s> void <ISA_LIT>IntelInstPrinter :: printMemOffset ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & DispSpec = MI -> getOperand ( Op ) ; printOptionalSegReg ( MI , Op + <NUM_LIT> , O ) ; O << '[' ; if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; } else


<s> virtual int getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode


<s> static bool aarch64_could_trap_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false


<s> SDValue Op0Op0 = Op0 -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShAmount = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ! ShAmount ) return SDValue ( ) ; if ( Op0Op0 -> getOpcode ( ) != <STR_LIT> && Op0Op0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ExtendTy = cast < VTSDNode > ( Op0Op0 -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; unsigned TotalBits = ShAmount -> getZExtValue ( ) + ExtendTy . getSizeInBits ( ) ; if ( TotalBits == <NUM_LIT> || ( Op0Op0 -> getOpcode ( ) == <STR_LIT> && TotalBits <= <NUM_LIT> ) ) { SDValue Ops [ ] = { Op0Op0 -> getOperand ( <NUM_LIT> ) , Op0Op0 -> getOperand ( <NUM_LIT> ) , Op0Op0 -> getOperand ( <NUM_LIT> ) } ; DAG . MorphNodeTo ( Op0Op0 . getNode ( ) , <STR_LIT> , Op0Op0 -> getVTList ( ) , Ops , Op0Op0 -> getNumOperands ( ) ) ; return Op0Op0 ; } } } if ( ( Ty != <STR_LIT> ) && ( ( Ty != <STR_LIT> ) || ! Subtarget

-> hasDSPR2 ( ) ) ) return SDValue ( ) ;


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT


<s> bool <ISA_LIT>FrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> Register LsrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , LsrDestReg ) . addUse ( BicDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register TotalIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , TotalIterationsReg ) . addUse ( LsrDestReg , RegState :: Kill ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) ) . addUse ( TotalIterationsReg ) . addMBB (


<s> __builtin_ia32_pmovqb512mem_mask ( ( unsigned long long * ) __P , ( __v8di )


<s> auto CheckZeros = [ & ] ( int Shift , int Scale , bool Left ) { for ( int i = <NUM_LIT> ; i < Size ; i += Scale ) for ( int j = <NUM_LIT> ; j < Shift ; ++ j ) if ( ! Zeroable [ i + j + ( Left ? <NUM_LIT> : ( Scale - Shift ) ) ] ) return false ; return true ; } ; auto MatchShift = [ & ] ( int Shift , int Scale , bool Left , SDValue V ) { for ( int i = <NUM_LIT> ; i != Size ; i += Scale ) { unsigned Pos = Left ? i + Shift : i ; unsigned Low = Left ? i : i + Shift ; unsigned Len = Scale - Shift ; if ( ! isSequentialOrUndefInRange ( Mask , Pos , Len , Low + ( V == V1 ? <NUM_LIT> : Size ) ) ) return SDValue ( ) ; } int ShiftEltBits = VT . getScalarSizeInBits ( ) * Scale ; bool ByteShift = ShiftEltBits > <NUM_LIT> ; unsigned OpCode = Left ? ( ByteShift ? <STR_LIT> : <STR_LIT> ) : ( ByteShift ? <STR_LIT> : <STR_LIT> ) ; int ShiftAmt = Shift * VT . getScalarSizeInBits ( ) / ( ByteShift ? <NUM_LIT> : <NUM_LIT> ) ; Scale = ByteShift ? Scale / <NUM_LIT> : Scale ; MVT ShiftSVT = <STR_LIT> ( VT . getScalarSizeInBits (


<s> assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind

== k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ) && <STR_LIT> ) ;


<s> bool hasSPE ( ) const { return HasSPE


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo (


<s> bool isS17Imm ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > (


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask


<s> return __builtin_mve_vqshruntq_n_sv8hi ( __a ,


<s> } if ( DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOT_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_HI12 ) { return Addend >= <NUM_LIT> && ( Addend % Scale ) == <NUM_LIT> ; } else if ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF ) { return Addend


<s> if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( icode == CODE_FOR_altivec_lvx_v2df_2op || icode == CODE_FOR_altivec_lvx_v2di_2op || icode == CODE_FOR_altivec_lvx_v4sf_2op || icode == CODE_FOR_altivec_lvx_v4si_2op || icode == CODE_FOR_altivec_lvx_v8hi_2op || icode == CODE_FOR_altivec_lvx_v16qi_2op ) { rtx rawaddr ; if ( op0 == const0_rtx ) rawaddr = op1 ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; rawaddr = gen_rtx_PLUS ( Pmode , op1 , op0 ) ; } addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - <NUM_LIT> ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , addr ) ; if ( ! BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG ) { rtx temp = gen_reg_rtx ( tmode ) ; emit_insn ( gen_rtx_SET ( temp , addr ) ) ; rtx sel = swap_selector_for_mode ( tmode ) ; rtx vperm = gen_rtx_UNSPEC ( tmode , gen_rtvec ( <NUM_LIT> , temp , temp , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( target , vperm ) ) ; } else emit_insn ( gen_rtx_SET ( target , addr ) ) ; } else { if ( op0 == const0_rtx ) addr = gen_rtx_MEM ( blk ? BLKmode : tmode , op1 ) ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , gen_rtx_PLUS (


<s> bool hasAVX2 = Subtarget . hasAVX2 ( ) ; uint16_t validDomains = <NUM_LIT> ; if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = <NUM_LIT> ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? <NUM_LIT> : <NUM_LIT> ; return std :: make_pair (


<s> return ( int8x8_t ) __builtin_aarch64_sqrshrn_nv8hi (


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; HasFarJump = false ; Fn . RenumberBlocks ( ) ; AFI -> setAlign ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP . isEmpty ( ) ) { DoInitialPlacement ( Fn , CPEMIs ) ; if ( isThumb ) AFI -> setAlign ( <NUM_LIT> ) ; } AFI -> initConstPoolEntryUId ( CPEMIs . size ( ) ) ; InitialFunctionScan ( Fn , CPEMIs ) ; CPEMIs . clear ( ) ; RemoveUnusedCPEntries ( ) ; bool MadeChange = false ; while ( true ) { bool Change = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) Change |= HandleConstantPoolUser ( Fn , i ) ; DEBUG ( dumpBBs ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) Change |= FixUpImmediateBr ( Fn , ImmBranches [ i ] ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! Change ) break ; MadeChange = true ; } verify ( Fn ) ; if ( ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) && isThumb ) MadeChange |= UndoLRSpillRestore ( ) ; BBSizes . clear ( ) ; BBOffsets . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear


<s> BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , <STR_LIT> ) ; return true


<s> unsigned offsetReg = Op -> getReg ( ) ; Op -> Kind = k_MemoryReg ; Op -> Mem . Base


<s> SDValue Unused = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Chain = Unused . getValue ( <NUM_LIT> ) ; SDValue Glue = Chain .


<s> static __inline int __attribute__ ( ( __always_inline__ ) )


<s> case 'm' : if ( ! SelectADDRrr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ; break ; } OutOps . push_back


<s> static bool isUnscaledLdSt ( MachineInstr & MI


<s> bool supportsTailCall ( ) const { return


<s> } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , BasePtr -> getType ( ) , Offsets -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( Ty -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( <NUM_LIT> ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , BasePtr -> getType ( ) , Offsets -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( Ty -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) ,


<s> <ISA_LIT>ATTInstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) : MCInstPrinter ( MAI , MII , MRI ) { setAvailableFeatures ( STI . getFeatureBits (


<s> case <STR_LIT> : case <STR_LIT> : return combineSIntToFP ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineVTRUNC ( N , DAG ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineCVTPH2PS ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Subtarget -> isTargetCygMing ( ) ) { unsigned CallOp = Subtarget -> is64Bit ( ) ? <STR_LIT>


<s> MachineBasicBlock * NewBRTarget = BSI . BranchToFallThrough ? OrigFallThrough : OrigTarget ; BranchProbability ProbToNewTarget = ! BSI . MBPI ? BranchProbability :: getUnknown ( ) : BSI . MBPI -> getEdgeProbability ( ThisMBB , NewBRTarget ) ; MachineBasicBlock :: iterator InsertPoint = BSI . SplitBefore ; const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ThisMBB -> getIterator ( ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( ++ It , NewMBB ) ; NewMBB -> splice ( NewMBB -> end ( ) , ThisMBB , InsertPoint , ThisMBB -> end ( ) ) ; NewMBB -> transferSuccessors ( ThisMBB ) ; ThisMBB -> addSuccessor ( NewBRTarget , ProbToNewTarget ) ; ThisMBB -> addSuccessor ( NewMBB , ProbToNewTarget . getCompl ( ) ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( NewBROpcode ) ) . addReg ( BSI . SplitCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewBRTarget ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewMBB ) ; if ( BSI . MIToDelete ) BSI


<s> unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true


<s> unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , TempReg ) ; unsigned Flags = getKillRegState ( New . isDead ( ) ) ; addExclusiveRegPair ( MIB , New , Flags , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end


<s> case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) { TCC = <STR_LIT> ; break ; } isUnsigned = true ; case <STR_LIT> : case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) { TCC = <STR_LIT> ; break ; } isUnsigned = true ; case <STR_LIT> : case <STR_LIT> : TCC = <STR_LIT> ; break ; } <ISA_LIT>CC = DAG . getConstant ( TCC , <STR_LIT> ) ; DebugLoc dl = LHS . getDebugLoc ( ) ; return DAG . getNode ( ( isUnsigned ? <STR_LIT> : <STR_LIT>


<s> for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB


( ) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_vsx_dform_quad ( mode ) ; break ; case E_V2SImode : case E_V2SFmode


<s> if ( Opcode == <NUM_LIT> ) Opcode = <STR_LIT> ; SDValue Condition = DAG . getConstant ( Predicate , DL , MVT_CC ) ; <STR_LIT> InvOutCC = <STR_LIT> ( OutCC ) ; unsigned NZCV = <STR_LIT> ( InvOutCC ) ; SDValue NZCVOp = DAG . getConstant ( NZCV , DL , <STR_LIT> ) ; return DAG . getNode ( Opcode , DL , MVT_CC , LHS


<s> return ( __m64 ) __builtin_arm_wunpckeluh (


<s> bool <ISA_LIT>FunctionInfo :: isLiveInZExt ( unsigned VReg ) const { for ( const std :: pair < unsigned , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ; return false


<s> else if ( ( REG_P ( rs1 ) || GET_CODE ( rs1 ) == SUBREG ) && ( REG_P ( rs2 ) || GET_CODE ( rs2 ) == SUBREG ) ) { if ( mode == TFmode && ! ( TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || SPARC_SYMBOL_REF_TLS_P ( rs1 ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || SPARC_SYMBOL_REF_TLS_P ( rs1 ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ; else return


<s> REAL_VALUE_TYPE r ; for ( i = <NUM_LIT> ; i < <NUM_LIT>


<s> return true ; case FK_Data_2 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_4 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_8 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_BR24 ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return d


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsHigh = <STR_LIT> ( Reg ) ; MI . setDesc ( get ( IsHigh ? HighOpcode : LowOpcode ) ) ; if ( IsHigh && ConvertHigh ) MI . getOperand ( <NUM_LIT> ) . setImm ( uint32_t

( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> static SDValue initAccumulator ( SDValue In , const SDLoc & DL , SelectionDAG & DAG ) { SDValue InLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getConstant ( <NUM_LIT> , DL ,


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ; return


<s> if ( checkInFPOPrologue ( L ) ) return true ; FPOInstruction Inst ; Inst . Label = emitFPOLabel ( ) ; Inst . Op =


<s> vax_add_reg_cfa_offset ( insn , <NUM_LIT> , arg_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , <NUM_LIT> , frame_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , <NUM_LIT> , pc_rtx ) ; offset = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( mask & ( <NUM_LIT> << regno ) ) { vax_add_reg_cfa_offset ( insn , offset , gen_rtx_REG ( SImode , regno ) ) ; offset += <NUM_LIT> ; } add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; size = get_frame_size ( ) ; size -=


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = getSETCC ( <STR_LIT> , EFLAGS , DL , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , cpOut ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , Success ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , EFLAGS . getValue ( <NUM_LIT> ) ) ; return SDValue (


<s> if ( state -> insns_left == <NUM_LIT> ) mips_sim_next_cycle ( state ) ; state -> insns_left --


<s> unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy


<s> if ( dest_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( dest_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( src_mode ) { case E_DFmode : cvt = sext_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_df ; break ; case E_SFmode : cvt = sext_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode : if ( FLOAT128_IBM_P ( src_mode ) ) cvt = sext_optab ; else do_move = true ; break ; case E_SImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IEEE_P ( src_mode ) ) { if ( src_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( src_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( dest_mode ) { case E_DFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_df ; break ; case E_SFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode : if ( FLOAT128_IBM_P ( dest_mode ) ) cvt = trunc_optab ; else do_move = true ; break ; case E_SImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IBM_P ( dest_mode ) && FLOAT128_IBM_P ( src_mode ) ) do_move = true ; else gcc_unreachable ( ) ; if ( do_move ) emit_insn ( gen_rtx_SET ( dest , gen_rtx_FLOAT_EXTEND ( dest_mode , src ) ) ) ; else if ( TARGET_FLOAT128_HW && hw_convert ) emit_insn ( ( hw_convert ) ( dest , src ) ) ; else if ( cvt != unknown_optab ) { libfunc = convert_optab_libfunc ( cvt , dest_mode , src_mode ) ; gcc_assert ( libfunc != NULL_RTX ) ; dest2 = emit_library_call_value ( libfunc , dest , LCT_CONST , dest_mode , src , src_mode ) ; gcc_assert ( dest2 != NULL_RTX )


<s> return ( __m128i ) __builtin_ia32_vplzcntq_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_si128 ( ) ,


<s> int16x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t )


<s> return true ; } if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) { * base = XEXP ( addr


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! Check ( S , DecodeBFLabelOperand < false , true , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Address , Decoder ) ) || ! Check ( S , DecodeBFLabelOperand < false , false , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { return MCDisassembler :: Fail ; } else { Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Address , Decoder ) ) ) return


<s> const struct arm_fpu_desc * fpu_desc = & all_fpus [ ptr -> x_arm_fpu_index ] ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , TARGET_THUMB2_P ( flags ) ? <STR_LIT> : TARGET_THUMB_P ( flags ) ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT>


<s> OperandMatchResultTy parseBDXAddr64 ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> return ( __m128i ) __builtin_ia32_pmovqd128_mask ( ( __v2di ) __A , (


<s> static bool is<ISA_LIT>R6 ( const MCSubtargetInfo * STI ) { return STI -> getFeatureBits ( ) [ <STR_LIT> ]

|| STI -> getFeatureBits ( ) [ <STR_LIT> ] ;


<s> printUImmOperand < <NUM_LIT> > ( MI ,


<s> return Ctx . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind ::


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemNoOffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addPostIdxRegOperands ( Inst , <NUM_LIT>


<s> if ( length == strlen ( flag -> name ) && ! strncmp ( flag -> name , token , length ) ) return flag -> flag ; } error ( <STR_LIT> , option_name , token ) ; return <NUM_LIT>


<s> const char * fname = XSTR ( symbol , <NUM_LIT> ) ; size_t i ; for ( i = <NUM_LIT> ; i < n_deferred_plabels ; i ++ ) if ( strcmp ( fname , XSTR ( deferred_plabels [ i ] . symbol , <NUM_LIT> ) ) == <NUM_LIT> ) break ; if ( deferred_plabels == NULL || i == n_deferred_plabels ) { tree id ; if ( deferred_plabels == <NUM_LIT> ) deferred_plabels = ggc_alloc < deferred_plabel > ( ) ; else deferred_plabels = GGC_RESIZEVEC ( struct deferred_plabel , deferred_plabels , n_deferred_plabels + <NUM_LIT> ) ; i = n_deferred_plabels


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm16 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) .


<s> ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal > <NUM_LIT> ) return false ; Ext = getExtendTypeForNode ( N . getOperand ( <NUM_LIT> ) ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else { Ext = getExtendTypeForNode ( N ) ; if ( Ext == <STR_LIT> ) return


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; O << format ( <STR_LIT> , Op . getImm


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> - ( MO . getImm (


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( VecVT . is256BitVector ( ) || VecVT . is512BitVector ( ) ) { Vec = extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return


<s> tag_map -> get_or_insert ( new_tag ) . safe_push ( insn_info ) ; df_set_regs_ever_live ( new_regno , true ) ; map_changed = true ; return false ; } v -> safe_insert ( <NUM_LIT> , insn_info ) ; insn_info = v -> pop ( ) ; } while ( insn_info != vec_start


<s> unsigned getReg ( ) const override { assert ( Kind ==


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return <STR_LIT>


<s> LiveIntervals & LIs = G . getMetadata ( ) . LIS ; if ( Chains . count ( Ra ) ) { if ( Rd != Ra ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Ra , & TRI ) << <STR_LIT> << PrintReg ( Rd , & TRI ) << '\n' ; ) ; Chains . remove ( Ra ) ; Chains . insert ( Rd ) ; } } else { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Rd , & TRI ) << '\n' ; ) ; Chains . insert ( Rd ) ; } PBQPRAGraph :: NodeId node1 = G . getMetadata ( ) . getNodeIdForVReg ( Rd ) ; const LiveInterval & ld = LIs . getInterval ( Rd ) ; for ( auto r : Chains ) { if ( r == Rd ) continue ; const LiveInterval & lr = LIs . getInterval ( r ) ; if ( ld . overlaps ( lr ) ) { const PBQPRAGraph :: NodeMetadata :: OptionToRegMap * vRdAllowed = & G . getNodeMetadata ( node1 ) . getOptionRegs ( ) ; PBQPRAGraph :: NodeId node2 = G . getMetadata ( ) . getNodeIdForVReg ( r ) ; const PBQPRAGraph :: NodeMetadata :: OptionToRegMap * vRrAllowed = & G . getNodeMetadata ( node2 ) . getOptionRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; assert ( edge != G . invalidEdgeId ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed , vRrAllowed ) ; } PBQP :: Matrix costs ( G . getEdgeCosts ( edge


<s> if ( EVT ( NewVT ) != SplitEVTs [ i ] ) { unsigned ExtendOp = TargetOpcode :: G_ANYEXT ; if ( F . getAttributes ( ) . hasAttribute ( AttributeList :: ReturnIndex , Attribute :: SExt ) ) ExtendOp = TargetOpcode :: G_SEXT ; else if ( F . getAttributes ( ) . hasAttribute ( AttributeList :: ReturnIndex , Attribute :: ZExt ) ) ExtendOp = TargetOpcode :: G_ZEXT ; LLT NewLLT ( NewVT ) ; LLT OldLLT ( <STR_LIT> ( CurArgInfo . Ty ) ) ; CurArgInfo . Ty = EVT ( NewVT ) . getTypeForEVT ( Ctx ) ; if ( NewVT . isVector ( ) ) { if ( OldLLT . isVector ( ) ) { if ( NewLLT . getNumElements ( ) > OldLLT . getNumElements ( ) ) { if ( NewLLT . getNumElements ( ) != OldLLT . getNumElements ( ) * <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Undef = MIRBuilder . buildUndef ( { OldLLT } ) ; CurVReg = MIRBuilder . buildMerge ( { NewLLT } , { CurVReg , Undef . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ; } else { CurVReg = MIRBuilder . buildInstr ( ExtendOp , { NewLLT } , { CurVReg } ) . getReg ( <NUM_LIT> ) ; } } else if ( NewLLT . getNumElements ( ) == <NUM_LIT> ) { auto Undef = MIRBuilder . buildUndef ( {


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_O32_RegMask


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return CCAssignFnForNode ( CC , true


<s> return ( isGTorGE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == RHS && K == TrueVal


<s> rtx tmp2 = * ( const rtx * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? <NUM_LIT> : - <NUM_LIT> ; return INSN_LUID ( tmp ) - INSN_LUID (


<s> const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT>


<s> Known . One &= Known2 . One ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = Known . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero |= Mask ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero


<s> printS16ImmOperand ( MI , OpNo ) ; } else { if ( Subtarget . isDarwin ( ) ) O << <STR_LIT> ; printOp ( MI -> getOperand (


<s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM )


<s> return - <NUM_LIT> ; } ; unsigned Imm = getImm ( GPR ) ; if ( Imm == - <NUM_LIT> ) { LastVPTReg = <NUM_LIT> ; continue ; } unsigned NotImm = ~ Imm & <NUM_LIT> ; if ( LastVPTReg != <NUM_LIT> && LastVPTReg != VPR && LastVPTImm == Imm ) { Instr . getOperand ( PIdx + <NUM_LIT> ) . setReg ( LastVPTReg ) ; if ( MRI -> use_empty ( VPR ) ) { DeadInstructions . insert ( Copy ) ; if ( MRI -> hasOneUse ( GPR ) ) DeadInstructions . insert ( MRI -> getVRegDef ( GPR ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Instr ) ; } else if ( LastVPTReg != <NUM_LIT> && LastVPTImm == NotImm ) { Register NewVPR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto VPNot = BuildMI ( MBB , & Instr , Instr . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewVPR ) . addReg ( LastVPTReg ) ; addUnpredicatedMveVpredNOp ( VPNot ) ; Instr . getOperand ( PIdx + <NUM_LIT> ) . setReg ( NewVPR ) ; if ( MRI -> use_empty ( VPR ) ) { DeadInstructions . insert ( Copy ) ; if ( MRI -> hasOneUse ( GPR ) ) DeadInstructions . insert ( MRI -> getVRegDef ( GPR ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPNot << <STR_LIT> << Instr ) ; VPR =


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == <NUM_LIT> ) return base_align ; return min ( base_align , offset


<s> bool Micro<ISA_LIT>SizeReduce :: ReduceADDIUToADDIUR1SP ( MachineInstr * MI , const ReduceEntry & Entry ) { if ( ! ImmInRange ( MI , Entry ) ) return false ; if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! IsSP ( MI -> getOperand ( <NUM_LIT> ) )


<s> if ( I ^ J1 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; if ( I ^ J2 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; return


<s> uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register )