<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isRegMask ( ) ) ModifiedRegs . setBitsNotInMask ( MO . getRegMask ( ) ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) ModifiedRegs . set ( * AI ) ; } else { assert ( MO . isUse ( ) && <STR_LIT> ) ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid (


<s> return <NUM_LIT> - MI . getOperand ( Op ) .


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup )

. add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> __ev64_opaque__ t ; t = __ev_mwhssf ( a , b ) ; return __ev_subfssiaaw (


<s> MachineInstr * DPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DPRMI && SPRMI ) { MachineInstr * ECDef = elideCopies ( DPRMI ) ; if ( ECDef && ECDef -> isImplicitDef ( ) ) { MachineInstr * EC = elideCopies ( SPRMI ) ; if ( EC && EC -> isCopy ( ) && EC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SPRMI ) ; unsigned FullReg = SPRMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( FullReg ) << <STR_LIT> ) ; eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ; unsigned OpReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( OpReg ) ) break ; MachineInstr * Def = MRI -> getVRegDef ( OpReg ) ; if ( ! Def ) break ; if ( Def -> isImplicitDef ( ) ) ++ NumImplicit ; else NonImplicitReg = MI -> getOperand ( I ) . getReg ( ) ; } if ( NumImplicit == NumTotal - <NUM_LIT> ) return optimizeAllLanesPattern ( MI


<s> bool OptForSize = DAG . shouldOptForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 ( AndRHSVal ) ) { Src = AndLHS ; BitNo = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , dl , Src . getValueType ( ) ) ; } } } if ( ! Src . getNode ( ) ) return SDValue ( ) ; if ( Src . getValueType ( ) == <STR_LIT> || Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) == <STR_LIT> && DAG . MaskedValueIsZero ( BitNo , APInt ( BitNo . getValueSizeInBits ( ) , <NUM_LIT> ) ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , dl , Src . getValueType ( ) , BitNo ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src


<s> auto * Trunc = dyn_cast < Instruction > ( Builder . CreateTrunc ( V , TruncTy ) ) ; if ( Trunc ) NewInsts . insert ( Trunc ) ; return Trunc ; } ; for ( auto I : * Sinks ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; if ( auto * Call = dyn_cast < CallInst > ( I ) ) { for ( unsigned i = <NUM_LIT> ; i < Call -> getNumArgOperands ( ) ; ++ i ) { Value * Arg = Call -> getArgOperand ( i ) ; Type * Ty = TruncTysMap [ Call ] [ i ] ; if ( Instruction * Trunc = InsertTrunc ( Arg , Ty ) ) { Trunc -> moveBefore ( Call ) ; Call -> setArgOperand ( i , Trunc


<s> const TargetRegisterClass * RC = nullptr ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; NegOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; NegOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; NegOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto Neg = MIB . buildInstr ( NegOpc , { RC } , { Src2Reg } ) ; constrainSelectedInstRegOperands ( * Neg , TII , TRI , RBI ) ; auto SShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Neg } ) ; constrainSelectedInstRegOperands ( * SShl , TII , TRI , RBI ) ; I . eraseFromParent


<s> AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig >


<s> static bool GenerateSignBits ( Value * V ) { if ( auto * Arg = dyn_cast < Argument > ( V ) ) return Arg -> hasSExtAttr ( ) ; if ( ! isa < Instruction > ( V ) ) return false ; unsigned Opc = cast < Instruction > ( V )


<s> if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( <STR_LIT> ) != std :: string :: npos || TT . find ( <STR_LIT> ) != std :: string :: npos ) { <ISA_LIT>ABI = EABI ; IsSingleFloat = true ; <ISA_LIT>ArchVersion = <ISA_LIT>2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ; HasSwap = true ; HasCondMov = true ; } if ( NotABICall || isABI_EABI ( ) || ( TM . getRelocationModel ( ) == Reloc :: Static


<s> if ( VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> || N0 . getNumOperands ( ) != <NUM_LIT> || N1 . getNumOperands ( ) != <NUM_LIT> || ! N0 . getOperand ( <NUM_LIT> ) . isUndef ( ) || ! N1 . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > Mask ; int NumElts = VT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( int Elt : SVOp -> getMask ( ) ) Mask . push_back ( Elt < NumElts ? Elt : ( Elt - NumElts / <NUM_LIT> ) ) ; SDLoc DL ( N ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) ) ; return DAG . getVectorShuffle ( VT , DL , Concat , DAG .


<s> case <STR_LIT> : case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineFP_EXTEND ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineINT_TO_FP ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : return combineBR_CCMASK ( N , DCI ) ; case <STR_LIT> : return combineSELECT_CCMASK ( N , DCI ) ; case <STR_LIT> : return combineGET_CCMASK ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( )


<s> FunctionPass * llvm :: create<ISA_LIT>FPMoverPass ( TargetMachine &


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i


<s> if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false


<s> return ( __m128i ) __builtin_ia32_pmovsxwd128_mask ( ( __v8hi ) __A , ( __v4si ) _mm_setzero_si128 ( )


<s> bool <ISA_LIT>LinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; bool is<ISA_LIT>64 = TD -> getPointerSizeInBits ( ) == <NUM_LIT> ; <ISA_LIT>TargetStreamer & TS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( is<ISA_LIT>64 ) Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( is<ISA_LIT>64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_extracti64x2_512_mask ( ( __v8di ) __A , __imm , (

__v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemSrcValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Bits = <NUM_LIT> ; const MCOperand & RegOp = MI . getOperand ( OpIdx ) ; const MCOperand & ImmOp = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Bits |= ( getMachineOpValue ( MI , RegOp , Fixups , STI ) <<


<s> rtx dest = lowpart_subreg ( V4SImode , op , GET_MODE ( op ) ) ; op = gen_rtx_VEC_SELECT ( V4SImode , dest , mask ) ; rtx insn = gen_rtx_SET ( dest , op ) ; emit_insn ( insn


<s> dremap . target = gen_reg_rtx ( V4DImode ) ; dremap . op0 = gen_lowpart ( V4DImode , d -> op0 ) ; dremap . op1 = dremap . op0 ; dremap . one_operand_p = true ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned int cnt = <NUM_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( ( contents [ i ] & ( <NUM_LIT> << j ) ) != <NUM_LIT> ) dremap . perm [ <NUM_LIT> * i + cnt ++ ] = j ; for ( ; cnt < <NUM_LIT> ; ++ cnt ) dremap . perm [ <NUM_LIT> * i + cnt ] = <NUM_LIT> ; } dfinal = * d ; dfinal . op0 = gen_lowpart ( dfinal . vmode , dremap . target ) ; dfinal . op1 = dfinal . op0 ; dfinal . one_operand_p = true ; for ( i = <NUM_LIT> , j = <NUM_LIT>


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment

* , const MCAsmLayout & ) const override {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > registered_target


<s> return ( Attributes & ( KMergeMasked |


<s> void addMicro<ISA_LIT>MemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . add ( StMO ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? Register ( TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset


<s> return isInt < <NUM_LIT> > ( Value ) || ( isUInt < <NUM_LIT> > ( Value ) && isInt < <NUM_LIT> > ( static_cast < int32_t > (


<s> bool direct_extern_access = ( ix86_direct_extern_access && ! ( VAR_OR_FUNCTION_DECL_P ( exp ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( exp ) ) ) ) ; if ( ! direct_extern_access ) ix86_has_no_direct_extern_access = true ; return default_binds_local_p_3 ( exp , flag_shlib != <NUM_LIT> , true , direct_extern_access , ( direct_extern_access && ( !

flag_pic || ( TARGET_64BIT && HAVE_LD_PIE_COPYRELOC != <NUM_LIT> ) ) ) ) ;


<s> State = IES_ERROR ; break ; case IES_INTEGER : case IES_REGISTER : case IES_RPAREN : State = IES_RPAREN


<s> solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } fprintf ( asm_out_file , <STR_LIT> , name ) ; if ( ! ( flags & SECTION_DEBUG ) ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_EXCLUDE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( <STR_LIT>


<s> return isTargetWatchOS ( ) || ( isTargetIOS ( ) && ! getTargetTriple ( ) . isOSVersionLT


<s> if ( Swap ) std :: swap ( Op0 , Op1 ) ; auto SubNode = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; auto Shifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SubNode , DAG . getConstant ( Size - <NUM_LIT> , DL , <STR_LIT> ) ) ; auto Final = Shifted ; if ( Complement ) Final = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shifted , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ) { <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( )


<s> snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL ) ; switch_to_section (


<s> Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Cond = DAG . getSetCC ( dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue Hi , Lo ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Cond , Tmp3 , Tmp2 ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VT , Cond , Tmp1 , Tmp3 ) ; } else


<s> static bool or1k_pass_by_reference ( cumulative_args_t , machine_mode mode , const_tree type , bool ) { HOST_WIDE_INT size ; if ( type


<s> int64_t Offset = SignExtend64 < <NUM_LIT> > ( ( Insn >> <NUM_LIT> ) & <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rt = getReg ( Decoder , <STR_LIT> , Rt ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst .


<s> bool isU6ImmX2 ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) &&

( getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ; }


<s> const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( MachineBasicBlock * MBB : JTBBs ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) || Subtarget -> isPIP ( ) ) Expr

= MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ;


<s> } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { if ( Parser . getTok ( ) . getString ( ) != <STR_LIT> ) return Error ( DirectiveID . getLoc (


<s> auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>FastEmitStore ( EVT VT , const Value * Val , const <ISA_LIT>AddressMode & AM , bool Aligned ) { if ( isa < ConstantPointerNull > ( Val ) ) Val = Constant :: getNullValue ( TD . getIntPtrType ( Val -> getContext ( ) ) ) ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Val ) ) { unsigned Opc = <NUM_LIT> ; bool Signed = true ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; case <STR_LIT> : Opc = <STR_LIT> ;


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) Suffix = <STR_LIT> ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) Suffix = <STR_LIT> ; std :: string Name = Mang -> getMangledName ( GV , Suffix , Suffix [ <NUM_LIT> ] != '\0' ) ; if ( Subtarget -> isTargetCygMing ( ) ) DecorateCygMingName ( Name , GV ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) Name = <STR_LIT> + Name ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) HiddenGVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) FnStubs [ Name ] = Mang -> getMangledName ( GV ) ; if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; printOffset ( MO . getOffset ( ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { FnStubs [ Name + <STR_LIT> ] = Name ; Name += <STR_LIT> ; } if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O <<


<s> if ( I == StackPtrCopyInst ) continue ; Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ; if ( Classification != Convert ) continue ; if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp & ( SlotSize - <NUM_LIT> ) ) return ; StackDisp >>= Log2SlotSize ; assert ( ( size_t ) StackDisp < Context . ArgStoreVector . size ( ) && <STR_LIT> ) ; if ( Context . ArgStoreVector [ StackDisp ] != nullptr ) return ; Context . ArgStoreVector [ StackDisp ] = & * I ; for ( const MachineOperand & MO : I -> uses ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( RegInfo . isPhysicalRegister ( Reg ) ) UsedRegs . insert ( Reg ) ; } } -- I ; if ( I == MBB . end ( ) || ! I ->


<s> if ( SUBREG_P ( dest ) ) { rtx dest_subreg = SUBREG_REG ( dest ) ; rtx src_subreg = SUBREG_REG ( src ) ; return GET_MODE ( dest_subreg ) == GET_MODE ( src_subreg ) ; } return false


<s> void LLVMInitialize<ISA_LIT>AsmPrinter (


<s> CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ; return true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( )


<s> rtx fnmem , fn_reg , toc_reg ; if ( ! TARGET_POINTERS_TO_NESTED_FUNCTIONS ) error ( <STR_LIT> <STR_LIT> , <STR_LIT> ) ; fnmem = gen_const_mem ( Pmode , force_reg ( Pmode , fnaddr ) ) ; fn_reg = gen_reg_rtx ( Pmode ) ; toc_reg = gen_reg_rtx ( Pmode ) ; m_tramp = replace_equiv_address ( m_tramp , addr ) ; emit_move_insn ( fn_reg , MEM_PLUS ( fnmem , <NUM_LIT> ) ) ; emit_move_insn ( toc_reg , MEM_PLUS ( fnmem , regsize ) ) ; emit_move_insn ( MEM_PLUS ( m_tramp , <NUM_LIT> ) , fn_reg ) ; emit_move_insn ( MEM_PLUS ( m_tramp , regsize ) , toc_reg ) ; emit_move_insn ( MEM_PLUS ( m_tramp , <NUM_LIT> * regsize ) , ctx_reg ) ; } break ; case ABI_ELFv2 : case ABI_DARWIN


<s> RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( Tok . getString ( ) . lower ( ) ) ; if ( isParsingMSInlineAsm ( ) && isParsingIntelSyntax ( ) && ( RegNo == <STR_LIT> || RegNo == <STR_LIT> ) ) RegNo = <NUM_LIT> ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) { StringRef RegName = Tok . getString ( ) ; OnFailure ( ) ; if ( ! RestoreOnFailure ) { Parser . Lex ( ) ; } return Error ( StartLoc , <STR_LIT> + RegName + <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } } if ( RegNo == <STR_LIT> ) { Tokens . push_back ( Tok ) ; Parser . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: LParen ) ) return false ; Tokens . push_back ( Parser . getTok ( ) ) ; Parser . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) { OnFailure ( ) ; return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : OnFailure ( ) ; return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } Tokens . push_back ( IntTok ) ; Parser . Lex


<s> return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask


<s> SDValue Lo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> ,


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseAdrLabel ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; const MCExpr * Expr ; parseOptionalToken ( AsmToken :: Hash ) ; if ( getParser ( ) . parseExpression

( Expr ) ) return MatchOperand_ParseFail ;


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , GetGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT (

) , false , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S2 ( SDValue N , SDValue &


<s> bool isVecListThreeD ( ) const { if ( Kind != k_VectorList ) return false ; return VectorList . Count ==


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl ,


<s> unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( MFLoOpc


<s> DEBUG ( errs ( ) << <STR_LIT> << J << <STR_LIT> << BBOffsets [ J

] << <STR_LIT> << BBSizes [ J ] << <STR_LIT> ) ;


<s> if ( ArchID != <STR_LIT> && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } return <ISA_LIT>ArchFeature


<s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( TARGET_SHMEDIA ) { if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) || EXTRA_CONSTRAINT_C16 ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } if ( i == <NUM_LIT> || i == <NUM_LIT> ) return <NUM_LIT> ; if ( CONST_OK_FOR_K08 ( i ) ) return <NUM_LIT> ; if ( CONST_OK_FOR_I08 ( i ) ) return <NUM_LIT> ; return


<s> Value * <ISA_LIT>IREmitter :: visitTESTM ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ; } if ( IsRegLoc ) { EVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = Subtarget -> in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = Has<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { SMLoc ArchLoc = getLoc ( ) ; StringRef Arch , ExtensionString ; std :: tie ( Arch , ExtensionString ) = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) . split ( '+' ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == static_cast < unsigned > ( <STR_LIT>


<s> static __inline__ float __fsels ( float x , float


<s> fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> initialized ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> save_regs_offset ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , crtl -> is_leaf ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START ,


<s> rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) ||

( ! TARGET_MIPS16 && can_create_pseudo_p ( ) ) ) ) {


<s> static SDValue emitRepmovsB ( const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src


<s> void addRegVSRpEvenRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( VSRpRegs [ getVSRpEvenReg ( ) ] )


<s> MachineBasicBlock :: iterator MBI = searchBackwards ( p , I , MFI ) ; if ( MBI ) { MachineInstr * NewMI = postRAConvertToLEA ( MFI , MBI ) ; if ( NewMI ) { ++ NumLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ; MBI -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ; ) ; MFI -> erase ( MBI


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> static rtx expand_set_or_cpymem_prologue ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int align , int desired_alignment , bool issetmem ) { int i ; for ( i = <NUM_LIT> ; i < desired_alignment ; i <<= <NUM_LIT> ) { if ( align <= i ) { rtx_code_label * label = ix86_expand_aligntest ( destptr , i , false ) ; if ( issetmem ) { if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } else destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ; ix86_adjust_counter ( count , i ) ; emit_label ( label ) ; LABEL_NUSES ( label )


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo


<s> const char * prefix = <STR_LIT> ; const char * suffix = <STR_LIT> ; if ( TARGET_SPE ) { gcc_assert ( ( sel & SAVRES_REG ) == SAVRES_GPR ) ; if ( ( sel & SAVRES_SAVE ) ) prefix = info -> spe_64bit_regs_used ? <STR_LIT> : <STR_LIT> ; else prefix = info -> spe_64bit_regs_used ? <STR_LIT> : <STR_LIT> ; if ( ( sel & SAVRES_LR ) ) suffix = <STR_LIT> ; } else if ( DEFAULT_ABI == ABI_V4 ) { if ( TARGET_64BIT ) goto aix_names ; if ( ( sel & SAVRES_REG ) == SAVRES_GPR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else if ( ( sel & SAVRES_REG ) == SAVRES_FPR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else if ( ( sel & SAVRES_REG ) == SAVRES_VR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else abort (


<s> void <ISA_LIT>InstPrinter :: printLogicalImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint64_t Val ; A64Imms :: isLogicalImmBits ( RegWidth , MO . getImm ( ) , Val ) ; O << <STR_LIT> ; O . write_hex (


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return


<s> } else return SDValue ( ) ; if ( ! Clamp ) return SDValue ( ) ; MVT ScalarType ; int ShftAmt = <NUM_LIT> ; switch ( Clamp -> getSExtValue ( ) ) { case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> : ScalarType = <STR_LIT> ; ShftAmt = <NUM_LIT> ; break ; default : return SDValue ( ) ; } if ( Shft . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * N1 = isConstOrConstSplat ( Shft . getOperand ( <NUM_LIT> ) ) ; if ( ! N1 || N1 -> getSExtValue ( ) != ShftAmt ) return SDValue ( ) ; SDValue Mul = Shft . getOperand ( <NUM_LIT> ) ; if ( Mul . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Ext0 = Mul . getOperand ( <NUM_LIT> ) ; SDValue Ext1 = Mul . getOperand ( <NUM_LIT> ) ; if ( Ext0 . getOpcode ( ) != <STR_LIT> || Ext1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VecVT = Ext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VecVT . isPow2VectorType ( ) || VecVT . getVectorNumElements ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VecVT || VecVT . getScalarType ( ) != ScalarType || VT . getScalarSizeInBits ( ) < ScalarType . getScalarSizeInBits ( ) * <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Mul ) ; unsigned LegalLanes = <NUM_LIT> / ( ShftAmt + <NUM_LIT> ) ; EVT LegalVecVT = <STR_LIT> ( ScalarType , LegalLanes ) ; if ( VecVT . getSizeInBits ( ) < <NUM_LIT> ) { EVT ExtVecVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / VecVT . getVectorNumElements ( ) ) , VecVT . getVectorNumElements ( ) ) ; SDValue Inp0 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext0 . getOperand ( <NUM_LIT> ) ) ; SDValue Inp1 = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , Ext1 . getOperand ( <NUM_LIT> ) ) ; Inp0 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 ) ; Inp1 = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp1 ) ; SDValue VQDMULH = DAG . getNode ( <STR_LIT> , DL , LegalVecVT , Inp0 , Inp1 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , ExtVecVT , VQDMULH ) ; Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Trunc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Trunc ) ; } assert ( VecVT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> &&


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE


<s> bool isFixed = MFI . isFixedObjectIndex ( FI ) ; return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed , FrameReg ,


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_failure_address ( void * const


<s> struct import * new ; for ( new = imports_list ; new ; new = new -> next ) if ( new -> name == name ) return ; new = ( struct import * ) xmalloc ( sizeof


<s> for ( unsigned i = <NUM_LIT> , e = NumStores ; i != e ; ++ i ) { if ( LoadValue == StoreValue [ i ] && LoadOffset == StoreOffset [ i ] ) return true ; if ( StoreValue [ i ] == LoadValue ) { if ( StoreOffset [ i ] < LoadOffset ) { if ( int64_t ( StoreOffset [ i ] + StoreSize [ i ] ) > LoadOffset ) return true ; } else { if ( int64_t ( LoadOffset + LoadSize ) > StoreOffset [ i ] ) return


<s> IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '6' ) <ISA_LIT>ArchVersion = V6 ; else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } } } if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType =


<s> rtx first [ <NUM_LIT> ] , second [ <NUM_LIT> ] , third [ <NUM_LIT> ] ; rtvec v ; int i , j ; switch ( n ) { case <NUM_LIT> : switch ( mode ) { case V16SImode : cmode = V8SImode ; break ; case V16SFmode : cmode = V8SFmode ; break ; case V8DImode : cmode = V4DImode ; break ; case V8DFmode : cmode = V4DFmode ; break ; case V8SImode : cmode = V4SImode ; break ; case V8SFmode : cmode = V4SFmode ; break ; case V4DImode : cmode = V2DImode ; break ; case V4DFmode : cmode = V2DFmode ; break ; case V4SImode : cmode = V2SImode ; break ; case V4SFmode : cmode = V2SFmode ; break ; case V2DImode : cmode = DImode ; break ; case V2SImode : cmode = SImode ; break ; case V2DFmode : cmode = DFmode ; break ; case V2SFmode : cmode = SFmode ; break ; default : gcc_unreachable ( ) ; } if ( ! register_operand ( ops [ <NUM_LIT> ] , cmode ) ) ops [ <NUM_LIT> ] = force_reg ( cmode , ops [ <NUM_LIT> ] ) ; if ( ! register_operand ( ops [ <NUM_LIT> ] , cmode ) ) ops [ <NUM_LIT> ] = force_reg ( cmode , ops [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_CONCAT ( mode , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ) ; break ; case <NUM_LIT> : switch ( mode ) { case V4DImode : cmode = V2DImode ; break ; case V4DFmode : cmode = V2DFmode ; break ; case V4SImode : cmode = V2SImode ; break ; case V4SFmode : cmode = V2SFmode ; break ; default : gcc_unreachable ( ) ; } goto half ; case <NUM_LIT> : switch ( mode ) { case V8DImode : cmode = V2DImode ; hmode = V4DImode ; break ; case V8DFmode : cmode = V2DFmode ; hmode = V4DFmode ; break ; case V8SImode : cmode = V2SImode ; hmode = V4SImode ; break ; case V8SFmode : cmode = V2SFmode ; hmode = V4SFmode ; break ; default : gcc_unreachable ( ) ; } goto half ; case <NUM_LIT> : switch ( mode ) { case V16SImode : cmode = V2SImode ; hmode = V4SImode ; gmode = V8SImode ; break ; case V16SFmode : cmode = V2SFmode ; hmode = V4SFmode ; gmode = V8SFmode ; break ; default : gcc_unreachable ( ) ; } goto half ; half : i = n - <NUM_LIT> ; j = ( n >> <NUM_LIT> ) - <NUM_LIT> ; for ( ; i > <NUM_LIT> ; i -= <NUM_LIT> ,


<s> case UNORDERED : return AARCH64_VS ; case UNLT : return AARCH64_LT ; case UNLE : return AARCH64_LE ; case UNGT : return AARCH64_HI ; case UNGE : return AARCH64_PL ; default : return - <NUM_LIT> ; } break ; case E_CCmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_GE ; case GT : return AARCH64_GT ; case LE : return AARCH64_LE ; case LT : return AARCH64_LT ; case GEU : return AARCH64_CS ; case GTU : return AARCH64_HI ; case LEU : return AARCH64_LS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_SWPmode


<s> return ( N . getOpcode ( ) == <STR_LIT> || isValidPCRelNode < ConstantPoolSDNode > ( N ) || isValidPCRelNode < GlobalAddressSDNode > ( N ) || isValidPCRelNode < JumpTableSDNode > ( N ) ||

isValidPCRelNode < BlockAddressSDNode > ( N ) ) ;


<s> return ( __m128d ) __builtin_ia32_maxsd ( ( __v2df ) __A , ( __v2df )


<s> static SDValue LowerCMP_SWAP ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT T = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; Result -> sgx_type = Op -> sgx_type ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result


<s> AsmToken <STR_LIT> ( ) { const AsmToken & lexedToken = lexDefinite ( ) ; switch ( lexedToken . getKind ( ) ) { default : return lexedToken ; case AsmToken :: Error : SetError ( Lexer -> getErrLoc ( ) , Lexer -> getErr ( ) ) ; return lexedToken ; case AsmToken :: Identifier : { std :: string upperCase = lexedToken . getString ( ) . str ( ) ; std :: string lowerCase = LowercaseString ( upperCase ) ; StringRef lowerRef ( lowerCase ) ; unsigned regID = MatchRegisterName ( lowerRef ) ; if ( regID ) return AsmToken ( AsmToken :: Register , lexedToken . getString ( ) , static_cast < int64_t > ( regID


<s> bool hasSymbolicDisplacement ( ) const { return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( const auto * S = dyn_cast < MCSymbolELF > ( & A -> getSymbol (


<s> if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue OutChains [ <NUM_LIT> ] ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , dl , SDValue ( Hi64 , <NUM_LIT> ) , StNode -> getBasePtr ( ) , MachinePointerInfo ( ) , alignment ) ; EVT addrVT = StNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , StNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , dl , SDValue ( Lo64 , <NUM_LIT> ) , LoPtr , MachinePointerInfo ( ) , alignment ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = <ISA_LIT>MCExpr :: CreateLower16 ( Expr , Ctx ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = <ISA_LIT>MCExpr :: CreateUpper16 ( Expr , Ctx ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_<ISA_LIT>_PLT , Ctx ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: CreateExpr


<s> if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) . getRetAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( )


<s> size_t <ISA_LIT>LongBranchStub :: alignment ( ) const { return <NUM_LIT>


<s> if ( Memory . ShiftType == <STR_LIT> ) return true ; if ( Memory . ShiftType != <STR_LIT> || Memory


<s> static SDValue EmitTailCallStoreFPAndRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue OldRetAddr , SDValue OldFP , int SPDiff , bool is<ISA_LIT>64 , bool isDarwinABI , DebugLoc dl ) { if ( SPDiff ) { int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex


<s> return ; } Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . OffsetRegNum ) ) ; if ( ! Memory . OffsetRegNum ) { if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand ::


<s> int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) Offset -= getOffsetOfLocalArea ( ) ; return Offset


<s> bool isABI_N64 ( ) const { return <ISA_LIT>ABI


<s> if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , STI . getCPU ( ) ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsLittleEndian = TT . getArch ( ) ==


<s> Mask . push_back ( i + Half ) ; Mask . push_back ( i + NumElems + Half ) ; } return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask [ <NUM_LIT>


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case


<s> DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , GetGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL


<s> static bool isMOVSHDUPMask ( ArrayRef < int > Mask , EVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements


<s> break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_SysCR : OS << <STR_LIT> <<


<s> const BasicBlockInfo & BBI = BBInfo [ Block ] ; dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; }


<s> return createMachOStreamer ( Ctx , TAB , OS , Emitter , RelaxAll


<s> Op -> ShiftedImm . Val = Val ; Op -> ShiftedImm . ShiftAmount = ShiftAmount ; Op -> StartLoc = S ; Op -> EndLoc =


<s> return ( __m128i ) __builtin_ia32_psrav4si_mask ( ( __v4si ) __X , ( __v4si )


<s> switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; } Register Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; Register Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg || ! Src1Reg ) return false ; emitInst ( DivOpc ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) ; emitInst ( <STR_LIT> ) . addReg ( Src1Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Register ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= <NUM_LIT> ) || ( TARGET_ARCH64 && size <= <NUM_LIT> ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_record_value ( type , mode , <NUM_LIT> , <NUM_LIT> , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , <NUM_LIT> ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode


__v2di ) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr ::


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; } else { char buf [ <NUM_LIT> ] ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; } if ( TARGET_PROFILE_KERNEL && crtl -> profile ) { gcc_assert ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) ; gcc_assert ( ! TARGET_32BIT ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; if ( DEFAULT_ABI != ABI_ELFv2 && cfun -> static_chain_decl != NULL ) { asm_fprintf ( file , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] , reg_names [ <NUM_LIT> ] ) ; fprintf ( file , <STR_LIT>


<s> static Reloc :: Model getEffectiveRelocModel ( bool JIT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) || JIT ) return Reloc :: Static ; return *


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( ) ; else { assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; MAI = new <ISA_LIT>MCAsmInfoELF ( TheTriple


<s> SDLoc dl ( Op ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue SafeShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits - <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , dl , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , SafeShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VT , Ops1 ) ; } else


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 (


<s> break ; default : { unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } } unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> return StringRef ( BTIHint . Data , BTIHint


<s> return ( __m128i ) __builtin_ia32_pandd128_mask ( ( __v4si ) __A , ( __v4si )


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetMacho ( ) ) ; if ( Subtarget -> isTargetWin64 ( ) ) { if ( Subtarget -> isTargetCygMing ( ) ) { BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState


<s> BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( J -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB , true ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size ( ) == <NUM_LIT> ) { MachineBasicBlock & PrevMBB = * * ReturnMBB . pred_begin ( ) ; if ( PrevMBB . isLayoutSuccessor ( & ReturnMBB ) && PrevMBB . canFallThrough ( ) ) { PrevMBB . splice ( PrevMBB . end ( ) , & ReturnMBB ,


<s> MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( Ctx ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex


<s> if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset


<s> if ( ! emitExtractSubreg ( DstReg , SrcReg , I , MRI , MF ) ) return false ; I . eraseFromParent ( ) ; return true ; } bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && DstTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && HasAVX512 ) { if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false


<s> unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs


<s> if ( constant_op1 ) { if ( skip_op1 ) * skip_op1 = true ; return ix86_vec_cost ( mode , cost -> sse_op + ( speed ? <NUM_LIT> : COSTS_N_BYTES ( GET_MODE_UNIT_SIZE ( mode ) ) ) ) ; } count = <NUM_LIT> ; } else if ( TARGET_SSSE3 ) count = <NUM_LIT> ; return ix86_vec_cost ( mode , cost -> sse_op * count ) ; } else if ( code == ASHIFTRT && ( mode == V2DImode || mode == V4DImode ) && ! TARGET_XOP && ! TARGET_AVX512VL ) { int count = <NUM_LIT> ; if ( constant_op1 && op1_val == <NUM_LIT> && TARGET_SSE4_2 ) count = <NUM_LIT> ; else if ( constant_op1 ) count = <NUM_LIT> ; return ix86_vec_cost ( mode , cost -> sse_op * count ) ; } else return ix86_vec_cost ( mode , cost -> sse_op ) ; } if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) { if ( constant_op1 ) { if ( op1_val > <NUM_LIT> ) return cost -> shift_const + COSTS_N_INSNS ( <NUM_LIT> ) ; else return cost -> shift_const * <NUM_LIT> ; } else { if ( and_in_op1 ) return cost -> shift_var * <NUM_LIT> ; else return cost -> shift_var * <NUM_LIT> + COSTS_N_INSNS ( <NUM_LIT> ) ; } } else { if ( constant_op1 ) return cost -> shift_const ; else if ( shift_and_truncate ) { if ( skip_op0 ) * skip_op0 = * skip_op1 = true ; return cost ->


<s> Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( Fragment ->


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results ,


<s> bool isBrImm ( ) { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr


<s> } else { rtx reg = crtl -> profile ? gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) : pic_offset_table_rtx ; rtx insn = emit_insn ( gen_set_got ( reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( crtl -> profile ) emit_move_insn ( pic_offset_table_rtx


<s> case <NUM_LIT> : ShOp = <STR_LIT> ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; case <NUM_LIT> : ShOp = <STR_LIT> ; return ( imm5 == <NUM_LIT> ? <NUM_LIT> : imm5 ) ; case


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i ) ; if ( Idx >= <NUM_LIT> ) { if ( Idx < ( int ) NumElems ) Idx += NumElems ; else Idx -= NumElems ; } MaskVec . push_back ( Idx


<s> for ( BasicBlock & BB : Func ) { for ( Instruction & I : BB ) { if ( isAMXCast ( & I ) )


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( <STR_LIT> . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT

) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> bool hasPAuth ( ) const { return HasPAuth


<s> ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; MachineInstrBuilder MIB ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) { if ( CLI . IsPatchPoint ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; else return false ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; } for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB . addReg ( RegArgs [ II ] , RegState :: Implicit ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; return finishCall ( RetVT , CLI , NumBytes


<s> bool isMemImm8s4Offset ( ) const { if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . OffsetRegNum !=

<NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ;


<s> return new <ISA_LIT>PassConfig ( * this , PM


<s> else if ( VT == <STR_LIT> ) Op = Op64 ; else llvm_unreachable ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < AN -> getNumOperands ( ) ; ++ i ) Ops . push_back ( AN -> getOperand ( i ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( AN -> getOrdering ( ) , <STR_LIT> ) ) ; Ops . push_back ( AN -> getOperand


<s> long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( dg ) ) ; return res


<s> Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; } if ( ! Shift ) return Result ; if ( Imm ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> - Shift ) ) ; } if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Hi ) ) ; } if ( ( Lo = Remainder & <NUM_LIT> ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result ,


<s> assert ( STI . isTargetWindowsMSVC ( ) && <STR_LIT> ) ; assert ( STI . isTargetWin32 ( ) && <STR_LIT> ) ; assert ( STI . is32Bit ( ) && ! Uses64BitFramePtr && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FramePtr = TRI -> getFrameRegister ( MF ) ; unsigned BasePtr = TRI -> getBaseRegister ( ) ; WinEHFuncInfo & FuncInfo = * MF . getWinEHFuncInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI -> getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned UsedReg ; int EHRegOffset = getFrameIndexReference ( MF , FI , UsedReg ) ; int EndOffset = - EHRegOffset - EHRegSize ; FuncInfo . EHRegNodeEndOffset = EndOffset ; if ( UsedReg == FramePtr ) { unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if ( UsedReg == BasePtr ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , BasePtr ) , FramePtr , false , EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; assert ( <ISA_LIT>FI -> getHasSEHFramePtrSave ( ) ) ; int Offset = getFrameIndexReference ( MF , <ISA_LIT>FI -> getSEHFramePtrSaveIndex ( ) , UsedReg ) ; assert ( UsedReg == BasePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FramePtr ) , UsedReg , true , Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; }


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( SMLoc Loc ) { MCStreamer :: EmitWinEHHandlerData ( Loc ) ; EHStreamer . EmitUnwindInfo ( * this ,


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . add ( predOps

( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ;


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , TII . get ( Opcode


<s> const TargetRegisterClass * RC = NULL ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = &


<s> return ( __m128i ) __builtin_ia32_vpshrdv_v4si ( ( __v4si ) __A , (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) {


<s> <ISA_LIT>VectorConstantInfo :: <ISA_LIT>VectorConstantInfo ( BuildVectorSDNode * BVN ) { assert ( BVN -> isConstant ( ) && <STR_LIT> ) ; bool HasAnyUndefs


<s> insn = next_active_insn ( label ) ; if ( insn == <NUM_LIT> ) return <NUM_LIT> ; else if ( ( get_attr_length ( insn ) % <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadFPAndRetAddr ( SelectionDAG & DAG , int SPDiff , SDValue Chain , SDValue & LROpOut , SDValue & FPOpOut , bool isDarwinABI , DebugLoc dl ) { if ( SPDiff ) { EVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ?


<s> return nullptr ; case AtomicOrdering :: SequentiallyConsistent : if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return


<s> unsigned NumOps = VT . getVectorNumElements ( ) ; if ( NumOps != <NUM_LIT> && NumOps != <NUM_LIT> && NumOps != <NUM_LIT> && NumOps != <NUM_LIT> ) return false ; if ( ! isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [ i ] , NumOps , NumOps * <NUM_LIT> ) ) ||

( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ;


<s> static bool isDirective ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>


<s> AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . setPreservesCFG (


<s> const unsigned int stubNum = get<ISA_LIT>16HelperFunctionStubNumber ( Args ) ; const unsigned int maxStubNum = <NUM_LIT> ; assert ( stubNum <= maxStubNum ) ; const bool validStubNum [ maxStubNum + <NUM_LIT> ] = { true , true , true , false , false , true , true , false , false , true , true } ; assert ( validStubNum [ stubNum ] ) ; const char * result ; if ( RetTy -> isFloatTy ( ) ) { result = sf<ISA_LIT>16Helper [ stubNum ] ; } else if ( RetTy -> isDoubleTy ( ) ) { result = df<ISA_LIT>16Helper [ stubNum ] ; } else if ( StructType * SRetTy = dyn_cast < StructType > ( RetTy ) ) { if ( SRetTy -> getNumElements ( ) == <NUM_LIT> ) { if ( ( SRetTy -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) && ( SRetTy -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) ) { result = sc<ISA_LIT>16Helper [ stubNum ] ; } else if ( ( SRetTy -> getElementType ( <NUM_LIT> ) -> isDoubleTy ( ) ) && ( SRetTy -> getElementType ( <NUM_LIT> ) -> isDoubleTy ( ) ) ) { result = dc<ISA_LIT>16Helper [


, Zeroable , Subtarget , DAG ) ) return PSHUFB ;


<s> case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * I . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Depth = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; if ( Depth == <NUM_LIT> && IntrinID == <STR_LIT> ) { if ( MFReturnAddr ) { MIRBuilder . buildCopy ( { DstReg } , MFReturnAddr ) ; I . eraseFromParent ( ) ; return true ; } MFI . setReturnAddressIsTaken ( true ) ; MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; I . getParent ( ) -> addLiveIn ( <STR_LIT> ) ; MachineIRBuilder EntryBuilder ( MF ) ; EntryBuilder . setInstr ( * MF . begin ( ) -> begin ( ) ) ; EntryBuilder . buildCopy ( { DstReg } , { Register ( <STR_LIT> ) } ) ; MFReturnAddr = DstReg ; I . eraseFromParent ( ) ; return true ; } MFI . setFrameAddressIsTaken ( true ) ; Register FrameAddr ( <STR_LIT> ) ; while ( Depth -- ) { Register NextFrame = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto Ldr = MIRBuilder . buildInstr ( <STR_LIT> , { NextFrame } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Ldr , TII , TRI , RBI ) ; FrameAddr = NextFrame ; } if ( IntrinID == <STR_LIT> ) MIRBuilder . buildCopy ( { DstReg } , { FrameAddr } ) ; else { MFI . setReturnAddressIsTaken ( true ) ; MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { FrameAddr } ) . addImm ( <NUM_LIT> ) ; } I . eraseFromParent ( ) ; return true


<s> src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart ( word_mode , src ) ; emit_insn ( gen_aarch64_movlow_di ( mode , dst , src_lo ) ) ; emit_insn ( gen_aarch64_movhigh_di ( mode , dst , src_hi ) ) ; return ; } else if ( GP_REGNUM_P ( dst_regno ) && FP_REGNUM_P ( src_regno ) ) { dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; emit_insn ( gen_aarch64_movdi_low ( mode , dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_high ( mode , dst_hi , src ) ) ; return ; } } dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; src_lo = gen_lowpart ( word_mode ,


<s> if ( mask1 != ~ mask2 ) return false ; if ( mask2 == <NUM_LIT> || mask2 == HOST_WIDE_INT_M1U ) return false ; gcc_assert ( shft_amnt < GET_MODE_BITSIZE ( mode )


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget


<s> static bool DisassembleThumb1PushPop ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; if ( B -> DoPredicateOperands ( MI , Opcode , insn , NumOps ) ) OpIdx += <NUM_LIT> ; else { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } unsigned RegListBits = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << ( Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++ OpIdx


<s> void <ISA_LIT>ConstantIslands :: adjustBBOffsetsAfter ( MachineBasicBlock * BB ) { unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned I = BBNum + <NUM_LIT> , E = MF -> getNumBlockIDs ( ) ; I < E ; ++ I ) { unsigned Offset = BBInfo [ I - <NUM_LIT> ] . Offset + BBInfo [ I - <NUM_LIT> ] . Size ; BBInfo [ I ]


<s> static void rs6000_init_sched_context ( void * _sc , bool clean_p ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; if ( clean_p ) { sc -> cached_can_issue_more = <NUM_LIT> ; sc -> last_scheduled_insn


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) ++ GPRCnt ; else if ( ( VT >= <STR_LIT> && VT <= <STR_LIT> ) || VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ++ FPRCnt ; else return false ; if ( GPRCnt > <NUM_LIT> || FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg Registers [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; VT = <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = &


<s> if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; return true


<s> bool <ISA_LIT>LinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool is<ISA_LIT>64 = TD -> getPointerSizeInBits ( ) == <NUM_LIT> ; <ISA_LIT>TargetStreamer & TS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( is<ISA_LIT>64 ) Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I


<s> bool isAcceptableSymbolRef ( const MCExpr * Expr ) const { if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair

( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( N -> getOperand ( i ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; return


<s> if ( Subtarget -> isThumb1Only ( ) ) return PerformAddeSubeCombine ( N , DCI , Subtarget ) ; if ( DCI . isBeforeLegalize ( ) ) return SDValue (


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; if ( SDValue R = combinePTESTCC ( EFLAGS , CC , DAG ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC , DAG


<s> emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , temp , GEN_INT ( c & <NUM_LIT> ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( dest , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = sext_hwi ( c , <NUM_LIT> ) ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL


<s> const char * getPassName ( ) const override { return


<s> uint32_t Enc = <STR_LIT> ( ~ CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT>


<s> Inst . addOperand ( MCOperand :: CreateReg ( FCCRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool

isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> const int src_sz = GET_MODE_SIZE ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; char ext_start ; switch ( src_sz ) { case <NUM_LIT> : ext_start = 'y' ; break ; case <NUM_LIT> : ext_start = 'z' ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( dst_sz


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> || Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT> ) ; auto NodeType = ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT>


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget -> getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; unsigned BytesLeft = SizeVal & <NUM_LIT> ; unsigned NumMemOps = SizeVal >> <NUM_LIT> ; unsigned EmittedNumMemOps = <NUM_LIT> ; EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = <NUM_LIT> ; SDValue TFOps [ MAX_LOADS_IN_LDM ] ; SDValue Loads [ MAX_LOADS_IN_LDM ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps +=


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSPE4DisEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; uint32_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo +

<NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ;


<s> bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; if ( STI -> hardenSlsRetBr ( ) ) GenerateTBB = false ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } MadeChange |= AlignBlocks ( MF ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange =


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MI , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MI , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MI , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MI , get (


<s> Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty (


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getMcpu ( ) == <STR_LIT> )


<s> SmallVector < LoadInst * , <NUM_LIT> > Loads ; SmallVector < Instruction * , <NUM_LIT> > Writes ; for ( auto & I : * BB ) { if ( I . mayWriteToMemory ( ) ) Writes . push_back ( & I ) ; auto * Ld = dyn_cast < LoadInst > ( & I ) ; if ( ! Ld || ! Ld -> isSimple ( ) || ! Ld -> hasOneUse ( ) || ! isa < SExtInst > ( Ld -> user_back ( ) ) ) continue ; Loads . push_back ( Ld ) ; } using InstSet = std :: set < Instruction * > ; using DepMap = std :: map < Instruction * , InstSet > ; DepMap RAWDeps ; const auto Size = LocationSize :: unknown ( ) ; for ( auto Read : Loads ) { for ( auto Write : Writes ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( DT -> dominates ( Write , Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { LoadInst * Dominator = DT -> dominates ( Base , Offset ) ? Base : Offset ; LoadInst * Dominated = DT -> dominates ( Base , Offset ) ? Offset : Base ; if ( RAWDeps . count ( Dominated ) ) { InstSet & WritesBefore = RAWDeps [ Dominated ] ; for ( auto Before : WritesBefore ) { if ( DT -> dominates ( Dominator , Before ) ) return false ; } } return true ; } ; for ( auto * Base : Loads ) { for ( auto * Offset : Loads ) { if ( Base == Offset


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target


<s> if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DOUT << <STR_LIT> ; DEBUG ( AM12 . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM12 . BaseType == <STR_LIT> ) { if ( ! AM12 . Base . Reg . getNode ( ) ) AM12 . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM12 . IndexReg . getNode ( ) ) AM12 . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM12 , Base