<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBUtils -> isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBUtils -> adjustBBSize ( MBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> addSuccessor ( DestBB ) ; std :: next ( MBB -> getIterator ( ) ) -> removeSuccessor ( DestBB ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBUtils -> adjustBBSize ( MBB , TII -> getInstSizeInBytes ( MBB -> back ( ) ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: Default ) CM = RM == Reloc :: PIC_ ? CodeModel :: Medium : CodeModel :: Small ; X -> InitMCCodeGenInfo ( RM ,


<s> static SDValue convertIntLogicToFPLogic ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FPOpcode =


<s> static <ISA_LIT>ABIInfo EABI ( ) { return <ISA_LIT>ABIInfo ( ABI ::


<s> MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; bool IsNakedFunction = MF -> getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode


<s> TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result


<s> void addSImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr


<s> I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ; I |= Mantissa


<s> bool <ISA_LIT>PassConfig :: addInstSelector


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm (


<s> Triple :: OSType OS = TT . getOS ( ) ; return OS == Triple :: Darwin || OS == Triple ::


<s> return getTM < <ISA_LIT>TargetMachine


<s> break ; case CONST_INT : case CONST_DOUBLE : if ( flag_pic && ( lra_in_progress || reload_completed ) ) return true ; break ; default : return false ; } return false


<s> if ( ! VT . is512BitVector ( ) || ! Subtarget -> hasAVX512


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT>

) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ;


<s> unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = <STR_LIT> ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; if ( DCI . isBeforeLegalize ( ) || TruncVT != <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } assert ( InVT == <STR_LIT> && <STR_LIT> ) ; SDValue Cast = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue Shuf = DAG . getVectorShuffle ( <STR_LIT> , dl , Cast , Cast , { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ) ; return DAG . getNode ( <STR_LIT> ,


<s> MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts ,


<s> static inline bool quad_address_offset_p ( HOST_WIDE_INT offset ) { return ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && ( (


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI -> getOperand ( PIdx + <NUM_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? FramePtr :


<s> static bool arm_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == HFmode )

return ( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ;


<s> void * <ISA_LIT>JITInfo :: emitFunctionStub ( const Function * F , void * Fn , JITCodeEmitter & JCE ) { if ( Fn != ( void * ) ( intptr_t ) <ISA_LIT>32CompilationCallback && Fn != ( void * ) ( intptr_t ) <ISA_LIT>64CompilationCallback ) { JCE . startGVStub ( F , <NUM_LIT> * <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; EmitBranchToAt ( Addr , ( intptr_t ) Fn , false , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> * <NUM_LIT> ) ; return JCE . finishGVStub ( F ) ; } JCE . startGVStub ( F , <NUM_LIT> * <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; if ( is64Bit ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } else if ( TM . getSubtargetImpl ( ) -> isDarwinABI ( ) ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } else


<s> EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveLRPair , Reg ,


<s> void <ISA_LIT>LoadStoreOpt :: moveLiveRegsBefore ( const MachineBasicBlock & MBB , MachineBasicBlock :: const_iterator Before ) { if ( ! LiveRegsValid ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveOuts ( & MBB , true ) ; LiveRegPos = MBB . end ( ) ; LiveRegsValid = true ; } while ( LiveRegPos != Before ) { -- LiveRegPos ; LiveRegs . stepBackward (


<s> MVT RetVT ; if ( ! isTypeSupported ( I -> getType ( ) , RetVT ) ) return false ; if ( const auto * C = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { unsigned ResultReg = <NUM_LIT> ; uint64_t ShiftVal = C -> getZExtValue ( ) ; MVT SrcVT = RetVT ; bool IsZExt = ( I -> getOpcode ( ) == Instruction :: AShr ) ? false : true ; const Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = true ; Op0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = false ; Op0 = SExt -> getOperand ( <NUM_LIT> ) ; } } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( Op0 ) ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: AShr : ResultReg = emitASR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: LShr : ResultReg = emitLSR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; } if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ; return true ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op1Reg ) return false ; bool Op1IsKill = hasTrivialKill ( I -> getOperand


<s> snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , ( int ) strlen ( vector_type_name ) - <NUM_LIT> , vector_type_name , num_vectors ) ; tree vectype = acle_vector_types [ <NUM_LIT> ] [ type ] ; tree arrtype = build_array_type_nelts ( vectype , num_vectors ) ; gcc_assert ( TYPE_MODE_RAW ( arrtype ) == TYPE_MODE ( arrtype ) ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( <STR_LIT> ) , arrtype ) ; tree t = lang_hooks . types . simulate_record_decl ( input_location , buffer , make_array_slice ( & field ,


<s> } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , DL , IsTailCall , DAG ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; bool IsPICCall = ( IsN64 || IsPIC ) ; bool GlobalOrExternal = false , InternalLinkage = false ; SDValue CalleeLo ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( IsPICCall ) { InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ; if ( InternalLinkage ) Callee = getAddrLocal ( Callee , DAG , Has<ISA_LIT>64 ) ; else if ( LargeGOT ) Callee = getAddrGlobalLargeGOT ( Callee , DAG , <STR_LIT> , <STR_LIT> ) ; else Callee = getAddrGlobal ( Callee , DAG , <STR_LIT> ) ; } else Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( ) , <NUM_LIT> , <STR_LIT> ) ; GlobalOrExternal = true ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { if ( ! IsN64 && ! IsPIC ) Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , <STR_LIT> ) ; else if ( LargeGOT ) Callee = getAddrGlobalLargeGOT ( Callee , DAG , <STR_LIT> , <STR_LIT> ) ; else Callee = getAddrGlobal ( Callee , DAG , <STR_LIT> ) ; GlobalOrExternal = true ; } SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> , Chain ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; if ( IsTailCall ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; SDValue InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , NextStackOffsetVal , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> BB -> updateTerminator ( ) ; MF . RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF . CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) ; MF . RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor ( BB ) ; JTBB -> addSuccessor ( NewBB ) ; ++


<s> bool <ISA_LIT>TargetLowering :: shouldUseStrictFP_TO_INT ( EVT FpVT , EVT IntVT , bool IsSigned ) const { return ! IsSigned && FpVT == <STR_LIT>


<s> Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - <NUM_LIT> || MemOffset > <NUM_LIT> ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , true ) ; return false ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Expr = Op . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * SR = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( SR -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } else if ( ! isEvaluated ( Expr ) ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return llvm :: make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return llvm :: make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSBinFormatRepo ( ) ) return make_unique < TargetLoweringObjectFileRepo > ( ) ; if ( TT . isOSFreeBSD ( ) ) return llvm :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) return llvm :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSSolaris ( ) ) return llvm :: make_unique

< <ISA_LIT>SolarisTargetObjectFile > ( ) ;


) builtin = AARCH64_SIMD_BUILTIN_UNOP_lceilv2sfv2si ;


<s> assert ( TII && <STR_LIT> ) ; return new <ISA_LIT>HazardRecognizer970 ( *


<s> int cur_pos = <NUM_LIT> ; register const unsigned char * string = ( const unsigned char * ) string_param ; fprintf ( stream , <STR_LIT> , prefix ) ; for ( i = <NUM_LIT> ; i < len ; i ++ ) { register int c = string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream ) ; cur_pos ++ ; } else { fprintf ( stream , <STR_LIT> , c ) ; cur_pos += <NUM_LIT> ; } if ( cur_pos > <NUM_LIT> && i + <NUM_LIT> < len ) { cur_pos = <NUM_LIT>


<s> return ix86_function_value_1 ( NULL , NULL , mode


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS <<


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int FPDiff , SDLoc dl ) { if ( ! FPDiff ) return Chain ; int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , FPDiff - SlotSize , false ) ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( NewReturnAddrFI ) , false , false


<s> } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> <<


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig (


<s> unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return


<s> SDValue PackedOp = Op . getOperand ( <NUM_LIT> ) ; EVT OutVT = Op . getValueType ( ) ; EVT InVT = PackedOp . getValueType ( ) ; unsigned ToBits = OutVT . getVectorElementType ( )


<s> __inline__ static unsigned long long sh_media_MADDS_W ( unsigned long long mm , unsigned long long mn ) { unsigned long


<s> DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < <NUM_LIT> ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , <ISA_LIT>FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( !


<s> const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; <ISA_LIT>TargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - <NUM_LIT> ; ++ I ) assert ( Comp ( * I , * ( I +


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT>


<s> if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( RHSC * <NUM_LIT> < MFI . getObjectSize ( FI ) ) { if ( ! MFI . isFixedObjectIndex ( FI ) && MFI . getObjectAlign ( FI ) <

Align ( <NUM_LIT> ) ) MFI . setObjectAlignment ( FI , Align ( <NUM_LIT> ) ) ;


<s> GlobalBaseReg = <STR_LIT> ; if ( M -> getPICLevel ( ) == PICLevel :: Small ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MVT NVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NVT , N0 ) ) ; } case <STR_LIT> : return lowerUINT_TO_FP_v2i32 ( Op , DAG , Subtarget , dl ) ; case <STR_LIT> : case <STR_LIT> : return lowerUINT_TO_FP_vXi32 ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget . hasAVX512 ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout

( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) {


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , raw_ostream & OS , MCCodeEmitter * CE , bool RelaxAll ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C ,


<s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { bool Result = AsmPrinter :: doInitialization ( M ) ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; return Result


<s> ComdatThunks &= ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsNoComdat ( ) ; return MF . getSubtarget < <ISA_LIT>Subtarget >


<s> unsigned Lo = RegInfo . getSubReg ( Src , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Src , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , VR0 ) . addReg ( Lo , SrcKill ) ; TII . storeRegToStack ( MBB , I , VR0 , true , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , VR1 ) . addReg ( Hi


<s> auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc ) return false ; auto isHiRegIdx = [ ] ( unsigned Reg ) { if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ; return false ; } ; for ( const MachineOperand & MO : MI . explicit_operands ( ) ) { if ( ! MO . isReg


<s> assert ( I . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT>


<s> static bool sparc_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( decl && flag_delayed_branch && ( TARGET_ARCH64 || ! current_function_returns_struct )


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } <ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , const TargetOptions & Options , bool isLittle ) { std :: string Ret = <STR_LIT> ; if ( isLittle ) Ret +=


<s> unsigned <ISA_LIT>TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const { return ( DL . getTypeSizeInBits ( VecTy ) +


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; Register BaseReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) .

addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: mips , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mipsel , true > Y ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mips64 , true > A ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mips64el , true > B ( getThe<ISA_LIT>64elTarget (


<s> assert ( PendingConditionalInsts . size ( ) <= <NUM_LIT> ) ; for ( MCInst Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask


<s> EVT VT = Store -> getValue ( ) . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT MemVT = Store -> getMemoryVT ( ) ; auto Pg = getPredicateForFixedLengthVector ( DAG , DL , VT ) ; auto NewValue = convertToScalableVector ( DAG , ContainerVT , Store -> getValue ( ) ) ; if ( VT . isFloatingPoint ( ) && Store -> isTruncatingStore ( ) ) { EVT TruncVT = ContainerVT . changeVectorElementType ( Store -> getMemoryVT


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return false ; Imm = N ; if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N ) -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ; if ( ! CR ) return TM . getCodeModel ( ) == CodeModel :: Small ; return CR -> getUnsignedMax ( ) . ult


<s> va_list_gpr_counter_field = f_gpr ; va_list_fpr_counter_field = f_fpr ; DECL_FIELD_CONTEXT ( f_gpr ) = record ; DECL_FIELD_CONTEXT ( f_fpr ) = record ; DECL_FIELD_CONTEXT ( f_res ) = record ; DECL_FIELD_CONTEXT ( f_ovf ) = record ; DECL_FIELD_CONTEXT ( f_sav ) = record ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_gpr ; DECL_CHAIN ( f_gpr ) = f_fpr ; DECL_CHAIN ( f_fpr )


<s> MisspeculatingTaintReg = <STR_LIT> ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; UseControlFlowSpeculationBarrier = functionUsesHardeningRegister ( MF ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > EntryBlocks ; EntryBlocks . push_back ( & MF . front ( ) ) ; for ( const LandingPadInfo & LPI : MF . getLandingPads ( ) ) EntryBlocks . push_back ( LPI . LandingPadBlock ) ; for ( auto Entry : EntryBlocks ) insertSPToRegTaintPropagation ( Entry , Entry -> SkipPHIsLabelsAndDebug ( Entry -> begin ( ) ) ) ; for ( auto & MBB : MF ) Modified |=


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG , DebugLoc dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } SDValue FIPtr = DAG . CreateStackTemporary ( <STR_LIT> ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr ,

DAG . getConstant ( <NUM_LIT> , FIPtr . getValueType ( ) ) ) ;


<s> CPEBB -> setAlignment ( <NUM_LIT> ) ; } else CPEBB -> setAlignment ( getCPELogAlign ( CPEBB -> begin ( ) ) ) ; adjustBBOffsetsAfter ( CPEBB ) ; assert ( ! BBIsJumpedOver ( CPEBB ) &&


<s> if ( ! Subtarget -> is<ISA_LIT>64 ( ) ) return <ISA_LIT>AsmPrinter :: emitInstruction ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>AsmPrinter :: emitInstruction ( MI ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; MCSymbol * EndOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( EndOfSled , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; OutStreamer -> emitLabel ( EndOfSled ) ; recordSled ( BeginOfSled , * MI , SledKind :: FUNCTION_ENTER , <NUM_LIT> ) ; break ; } case TargetOpcode :: PATCHABLE_RET : { unsigned RetOpcode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst RetInst ; RetInst . setOpcode ( RetOpcode ) ; for ( const auto & MO : llvm :: drop_begin ( MI -> operands ( ) ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) RetInst . addOperand ( MCOp ) ; } bool IsConditional ; if ( RetOpcode == <STR_LIT> ) { IsConditional = true ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { break ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { IsConditional = false ; } else { EmitToStreamer ( * OutStreamer , RetInst ) ; break ; } MCSymbol * FallthroughLabel ; if ( IsConditional ) { FallthroughLabel = OutContext . createTempSymbol (


<s> return new Emitter < ObjectCodeEmitter > ( TM ,


<s> MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( MRI . isSSA ( ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( ! III . ZeroIsSpecialOrig ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; if ( MI . getOperand ( III . ZeroIsSpecialOrig ) . getReg ( ) != <STR_LIT> && MI . getOperand ( III . ZeroIsSpecialOrig )

. getReg ( ) != <STR_LIT> ) return false ;


<s> unsigned ID = MI -> getOperand ( OpNo ) . getImm ( ) ; O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << ID << <STR_LIT> ; } else { assert ( ! strcmp ( Modifier , <STR_LIT> ) && <STR_LIT> ) ; unsigned CPI = MI -> getOperand ( OpNo


<s> switch ( getLexer ( ) . getKind ( ) ) { default : { SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( parseSymbolicImmVal ( Expr ) ) return Error ( S , <STR_LIT> ) ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseVectorList ( Operands ) ; case AsmToken :: Identifier : { if ( isCondCode ) return parseCondCode ( Operands , invertCondCode ) ; if ( ! parseRegister ( Operands ) ) return false ; if ( ! parseOptionalShift ( Operands ) ) return false ; if ( ! parseOptionalExtend ( Operands ) ) return false ; const MCExpr * IdVal ; S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken ::


<s> EVT Ty = Op . getValueType ( ) ; if ( ABI . IsCheriPureCap ( ) ) { auto PtrInfo = MachinePointerInfo :: getCapTable ( DAG . getMachineFunction ( ) ) ; assert ( Ty . isFatPointer ( ) ) ; auto Result = getDataFromCapTable ( N , SDLoc ( N ) , Ty , DAG , DAG . getEntryNode ( ) , PtrInfo ) ; assert ( Result . getValueType ( ) == Ty ) ; return Result ; } if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc


<s> CC = <STR_LIT> ; } if ( CC != <STR_LIT> || VT . getScalarSizeInBits ( ) != <NUM_LIT> || Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < VT . getVectorNumElements ( ) ; I ++ ) { if ( ! Op0 . getOperand ( I ) . isUndef ( ) && ! ( isa < ConstantSDNode > ( Op0 . getOperand ( I ) ) && Op0 . getConstantOperandVal ( I ) == I ) ) return SDValue ( ) ; } SDValue Op1S = DCI . DAG . getSplatValue ( Op1 ) ; if ( ! Op1S ) return SDValue ( ) ; unsigned Opc ; switch ( VT . getVectorNumElements ( ) ) { case <NUM_LIT> : Opc = <STR_LIT>


<s> unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = fastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , Addr . Offset , <STR_LIT> ) ; Addr . Offset = <NUM_LIT>


<s> bool <ISA_LIT>FastISel :: selectAtomicCmpXchg ( const AtomicCmpXchgInst * I ) { assert ( TM . getOptLevel ( ) == CodeGenOpt :: None && <STR_LIT> ) ; auto * RetPairTy = cast < StructType > ( I -> getType ( ) ) ; Type * RetTy = RetPairTy -> getTypeAtIndex ( <NUM_LIT> ) ; assert ( RetPairTy -> getTypeAtIndex ( <NUM_LIT> ) -> isIntegerTy ( <NUM_LIT> ) && <STR_LIT> ) ; MVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const TargetRegisterClass * ResRC ; unsigned Opc , CmpOpc ; if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; CmpOpc = <STR_LIT> ; ResRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; CmpOpc = <STR_LIT> ; ResRC = & <STR_LIT> ; } else { return false ; } const MCInstrDesc & II = TII . get ( Opc ) ; const Register AddrReg = constrainOperandRegClass ( II , getRegForValue ( I -> getPointerOperand ( ) ) , II . getNumDefs ( ) ) ; const Register DesiredReg = constrainOperandRegClass ( II , getRegForValue ( I -> getCompareOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const Register NewReg = constrainOperandRegClass ( II , getRegForValue ( I -> getNewValOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const Register ResultReg1 = createResultReg ( ResRC ) ; const Register ResultReg2 = createResultReg ( & <STR_LIT> ) ; const Register ScratchReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addDef ( ResultReg1 ) . addDef ( ScratchReg ) . addUse ( AddrReg ) . addUse ( DesiredReg ) . addUse ( NewReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) ) . addDef ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) . addUse ( ResultReg1 ) . addUse ( DesiredReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResultReg2 ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; assert ( ( ResultReg1 + <NUM_LIT> ) == ResultReg2 && <STR_LIT> ) ; updateValueMap ( I , ResultReg1


<s> return __builtin_mve_vminaq_m_sv16qi ( __a ,


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , StringRef TT ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) .


<s> return ( uint32x4_t ) __builtin_aarch64_ld1v4si ( ( const


<s> } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear (


<s> EVT MemVT = MemIntrin -> getMemoryVT ( ) ; for ( SDNode * User : Ptr -> uses ( ) ) if ( User != N && User -> getOpcode ( ) == <STR_LIT> && cast < MemIntrinsicSDNode > ( User ) -> getBasePtr ( ) == Ptr && cast < MemIntrinsicSDNode > ( User ) -> getChain ( ) == Chain && cast < MemIntrinsicSDNode > ( User ) -> getMemoryVT ( ) . getSizeInBits ( ) == MemVT . getSizeInBits ( ) && ! User -> hasAnyUseOfValue ( <NUM_LIT> ) && User -> getValueSizeInBits ( <NUM_LIT> ) > VT . getSizeInBits ( ) ) { SDValue Extract = extractSubVector ( SDValue ( User , <NUM_LIT> ) , <NUM_LIT> , DAG , SDLoc ( N ) , VT . getSizeInBits ( ) ) ; Extract = DAG . getBitcast ( VT , Extract ) ; return DCI . CombineTo ( N , Extract , SDValue ( User , <NUM_LIT> ) ) ; } return SDValue (


<s> return ( uint16x8_t ) __builtin_neon_vcvtnuv8hf


<s> case AsmToken :: Exclaim : case AsmToken :: Tilde : if ( ! ParseExpression ( EVal ) ) break ; default : return Error ( S , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( TLSSym , S , E , is<ISA_LIT>64 ( ) ) ) ; } if ( ! TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken ::


<s> if ( getTargetMachine ( ) . getOptLevel ( ) == <NUM_LIT> ) return AtomicExpansionKind :: None ; return AtomicExpansionKind


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo * MFFrame = MF .


<s> static DecodeStatus DecodeT2Imm8S4 ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { if ( Val == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( INT32_MIN ) ) ; else { int imm = Val & <NUM_LIT> ; if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( imm * <NUM_LIT> ) ) ; } return MCDisassembler ::


<s> MachineBasicBlock :: iterator FrameSetup = Context . FrameSetup ; MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; FrameSetup -> getOperand ( <NUM_LIT> ) . setImm ( Context . ExpectedDist ) ; DebugLoc DL = FrameSetup -> getDebugLoc ( ) ; for ( int Idx = ( Context . ExpectedDist / <NUM_LIT> ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator MOV = * Context . MovVector [ Idx ] ; MachineOperand PushOp = MOV -> getOperand ( <STR_LIT> ) ; if ( MOV -> getOpcode ( ) == <STR_LIT> ) { unsigned PushOpcode = <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = <STR_LIT> ; } BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addOperand ( PushOp ) ; } else { unsigned int Reg = PushOp . getReg ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool SlowPUSHrmm = ST . isAtom ( ) || ST . isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const unsigned StackOffset = <NUM_LIT> ; bool IsLittleEndian = DAG . getDataLayout ( ) . isLittleEndian ( ) ; unsigned InIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ InIdx ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ InIdx ] . Flags . isSRet ( ) ) { if ( InIdx != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; int FrameIdx = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; SDValue FIPtr = DAG . getFrameIndex ( FrameIdx , <STR_LIT> ) ; SDValue Arg = DAG . getLoad ( <STR_LIT> , dl , Chain , FIPtr , MachinePointerInfo ( ) ) ; InVals . push_back ( Arg ) ; continue ; } if ( VA . isRegLoc ( ) ) { if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) ; Register VRegHi = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , VRegHi ) ; SDValue HiVal = DAG . getCopyFromReg ( Chain , dl , VRegHi , <STR_LIT> ) ; assert ( i + <NUM_LIT> < e ) ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; SDValue LoVal ; if ( NextVA . isMemLoc ( ) ) { int FrameIdx = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , StackOffset + NextVA . getLocMemOffset ( ) , true ) ; SDValue FIPtr = DAG . getFrameIndex ( FrameIdx , <STR_LIT> ) ; LoVal = DAG . getLoad ( <STR_LIT> , dl , Chain , FIPtr , MachinePointerInfo ( ) ) ; } else { unsigned loReg = MF . addLiveIn ( NextVA . getLocReg ( ) , & <STR_LIT> ) ; LoVal = DAG . getCopyFromReg ( Chain , dl , loReg , <STR_LIT> ) ; } if ( IsLittleEndian ) std :: swap ( LoVal , HiVal ) ; SDValue WholeValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoVal , HiVal ) ; WholeValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , WholeValue ) ; InVals . push_back ( WholeValue ) ; continue ; } Register VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) Arg = DAG . getNode (


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool isVecListTwoDAllLanes ( ) const { if ( ! isSingleSpacedVectorAllLanes ( ) ) return false ; return VectorList . Count ==


<s> void addMVEVecListOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCRegisterClass * RC_in = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; const MCRegisterClass * RC_out = ( VectorList . Count == <NUM_LIT> ) ? & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] : & <ISA_LIT>MCRegisterClasses [


<s> } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DEBUG ( errs ( ) << <STR_LIT> ; AM12 . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM12 . BaseType == <STR_LIT> ) { if ( ! AM12 . Base . Reg . getNode ( ) ) AM12 . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM12 . IndexReg . getNode ( ) ) AM12 . IndexReg =


<s> DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } UpdateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len ,


<s> return ( __m256i ) __builtin_ia32_vcvtph2w256_mask ( __A , ( __v16hi )


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) ; return Cmp


<s> } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList (


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t width = ( <NUM_LIT> - countLeadingZeros ( v ) ) - lsb ; assert ( MO . isImm ( ) && <STR_LIT> ) ; O << markup ( <STR_LIT> ) << '#' << lsb << markup ( <STR_LIT> ) << <STR_LIT> <<

markup ( <STR_LIT> ) << '#' << width << markup ( <STR_LIT> ) ;


<s> uint32_t insn = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; DecodeStatus result = decodeInstruction ( DecoderTableA6432 , MI , insn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } MI . clear ( ) ; Size =


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o


<s> assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasSVE ( ) || AFI -> hasCalculatedStackSizeSVE ( ) ) && <STR_LIT> ) ; return TFI . hasFP ( MF ) && ! hasStackRealignment

( MF ) && ! AFI -> getStackSizeSVE ( ) ;


<s> static SDValue LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT>


<s> Register Lo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Hi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Bitcast ) . addUse ( StoreVal ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Lo ) . addUse ( Bitcast ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Hi ) . addUse ( Bitcast ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Lo ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Lo ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Hi ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Hi ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; return BB


<s> return ( uint32x4_t ) __builtin_neon_vcgtv4sf


<s> static bool FoldMaskedShiftToScaledMask ( SelectionDAG & DAG , SDValue N , uint64_t Mask , SDValue Shift , SDValue X , <ISA_LIT>ISelAddressMode & AM ) { if ( Shift . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ) return true ; if ( ! N . hasOneUse ( ) || ! Shift . hasOneUse ( ) ) return true ; unsigned ShiftAmt = Shift . getConstantOperandVal ( <NUM_LIT> ) ; if ( ShiftAmt != <NUM_LIT> && ShiftAmt != <NUM_LIT> && ShiftAmt != <NUM_LIT> ) return true ; MVT VT = N . getSimpleValueType ( ) ; SDLoc DL ( N ) ; SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , DL , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW ,


<s> unsigned Temp = Reg1 ; Reg1 = Reg2 ; Reg2 = Temp ; } I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand :: CreateReg ( Reg1 ) ) ; I . addOperand ( MCOperand :: CreateReg ( Reg2 ) ) ; OutStreamer . EmitInstruction ( I , getSubtargetInfo (


<s> unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) && <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; MIB . addRegMask ( TRI -> getNoPreservedMask ( ) ) ; BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB , <NUM_LIT> ) ; thisMBB -> addSuccessor ( sinkMBB , <NUM_LIT> ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) , LabelReg ) ; if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg ) .


<s> if ( TARGET_DEBUG_B_MODE ) { GO_PRINTF ( <STR_LIT> ) ; GO_DEBUG_RTX ( xinsn ) ; } if ( iq2000_check_split ( xinsn , mode ) ) { return gen_rtx_LO_SUM ( Pmode , copy_to_mode_reg ( Pmode , gen_rtx_HIGH ( Pmode , xinsn ) ) , xinsn ) ; } if ( GET_CODE ( xinsn ) == PLUS ) { rtx xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; rtx xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; enum rtx_code code0 = GET_CODE ( xplus0 ) ; enum rtx_code code1 = GET_CODE ( xplus1 ) ; if ( code0 != REG && code1 == REG ) { xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; code0 = GET_CODE ( xplus0 ) ; code1 = GET_CODE ( xplus1 ) ; } if ( code0 == REG && REG_MODE_OK_FOR_BASE_P ( xplus0 , mode ) && code1 == CONST_INT && ! SMALL_INT ( xplus1 ) ) { rtx int_reg = gen_reg_rtx ( Pmode ) ; rtx ptr_reg = gen_reg_rtx ( Pmode ) ; emit_move_insn ( int_reg , GEN_INT ( INTVAL ( xplus1 ) & ~ <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , ptr_reg , gen_rtx_PLUS ( Pmode , xplus0 , int_reg ) ) ) ; return plus_constant ( Pmode , ptr_reg , INTVAL ( xplus1


<s> EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! BCVT . isVector ( ) || BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , true , ShuffleOps , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? SM_SentinelUndef : ShuffleMask [ Elt ] ; if ( Idx == SM_SentinelZero ) return EltVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , EltVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , EltVT ) ; if ( Idx == SM_SentinelUndef ) return DAG . getUNDEF ( EltVT ) ; assert ( <NUM_LIT> <= Idx && Idx < ( int ) ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? ShuffleOps [ <NUM_LIT> ] : ShuffleOps [ <NUM_LIT> ] ; unsigned AllowedUses = ( ShuffleOps . size ( ) > <NUM_LIT> && ShuffleOps [ <NUM_LIT> ] == ShuffleOps


<s> unsigned CC = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; PredicationCode = CC ; } } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT>


<s> if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; int QuarterSize = NumElems / <NUM_LIT> ; int HalfSize = QuarterSize * <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < QuarterSize ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , HalfSize ) ) return false ; for ( int i = QuarterSize ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i

] , NumElems , NumElems + HalfSize ) ) return false ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerCompactBranch ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; const unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; bool IsNakedFunction = MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) { TS . emitDirectiveSetNoReorder ( ) ; TS . emitDirectiveSetNoMacro ( )


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return ! G -> getGlobal ( ) -> isDeclaration ( ) && ! G -> getGlobal ( ) -> isWeakForLinker ( ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ITBlock . size ( ) > <NUM_LIT> ) S = SoftFail ; break ; default : break ; } unsigned CC ; if ( ! ITBlock . empty ( ) ) { CC = ITBlock . back ( ) ; if ( CC == <NUM_LIT> ) CC = <STR_LIT> ; ITBlock . pop_back ( ) ; } else CC = <STR_LIT> ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator I = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( I == MI . end ( ) ) break ; if ( OpInfo [ i ] . isPredicate ( ) ) { I = MI . insert ( I , MCOperand :: CreateImm ( CC ) ) ; ++ I ; if ( CC == <STR_LIT> ) MI . insert ( I , MCOperand :: CreateReg ( <NUM_LIT> ) ) ; else MI . insert ( I , MCOperand


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast


<s> static inline bool isAdvSIMDModImmType5 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( (


<s> if ( ! isSingleSpacedVectorAllLanes ( )


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask (


<s> } const AsmToken & Tok2 = Parser . getTok ( ) ; if ( Tok2 . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( IdVal == <NUM_LIT> ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) ) ; int RegNo = op -> getReg ( ) ; Operands . pop_back ( ) ; Operands . push_back ( <STR_LIT> ( RegNo , IdVal , S , E ) ) ; delete op ; return


<s> bool isISA3_0 ( ) const { return IsISA3_0


<s> assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> ,


<s> } SmallVector < Value * , <NUM_LIT> > Args ; if ( EscapeCall ) { auto Ops = EscapeCall -> arg_operands ( ) ; Args . append ( Ops . begin ( ) , Ops . end ( ) ) ; } Args . push_back ( RegNode ) ; Instruction * InsertPt = EscapeCall ; if ( ! EscapeCall ) InsertPt = F . getEntryBlock ( ) . getTerminator ( ) ; IRBuilder < > Builder ( & F . getEntryBlock ( ) , InsertPt ) ; Builder . CreateCall ( FrameEscape ,


<s> if ( RegNo == <NUM_LIT> ) Check ( S , MCDisassembler :: SoftFail ) ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ) ; return S


<s> bool hasITBlocks ( ) const { return HasITBlocks


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; IndirectTlsSegRefs = MF . getFunction ( ) . hasFnAttribute


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo

:: getGOT ( ) , false , false , <NUM_LIT> ) ;


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > SuccessorAccesses ; int CodesizeEstimate = - <NUM_LIT> ; for ( auto * Use : OtherAccesses ) { if ( DT -> dominates ( BaseAccess , Use ) ) { SuccessorAccesses . insert ( Use ) ; unsigned BaseOp = getBaseOperandIndex ( * Use ) ; if ( ! isLegalOrConvertableAddressImm ( Use -> getOpcode ( ) , Use -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) - IncrementOffset , TII , CodesizeEstimate ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! DT -> dominates ( Use , BaseAccess ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } if ( STI -> hasMinSize ( ) && CodesizeEstimate > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BaseAccess -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Increment -> dump ( ) ) ; Register NewBaseReg = Increment -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * BaseAccessPost = createPostIncLoadStore ( BaseAccess , IncrementOffset , NewBaseReg , TII , TRI ) ; BaseAccess -> eraseFromParent ( ) ; Increment -> eraseFromParent ( ) ; ( void ) BaseAccessPost ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BaseAccessPost -> dump (


<s> static char templ [ <NUM_LIT> ] ; struct simd_immediate_info info ; bool is_valid = aarch64_simd_valid_immediate ( const_unspec , & info ) ; gcc_assert ( is_valid && info . insn == simd_immediate_info :: PTRUE ) ; char element_char = sizetochar ( GET_MODE_BITSIZE ( info . elt_mode ) ) ; snprintf ( templ , sizeof ( templ ) , <STR_LIT> , element_char ,

svpattern_token ( info . u . pattern ) ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperandEA ( const MCInst * MI , int opNum , raw_ostream &


<s> rtx op0 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx op1 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ) ; op0 = nds32_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; op1 = nds32_legitimize_argument ( icode ,


<s> setLibcallName ( RTLIB :: SINTTOFP_I32_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SINTTOFP_I32_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UINTTOFP_I32_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UINTTOFP_I32_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OEQ_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OEQ_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UNE_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UNE_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OGE_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OGE_F64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OLT_F32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: OLT_F64


<s> Register <ISA_LIT>RegisterInfo :: getBaseRegister ( )


<s> case TYPE_IDIV : fprintf ( stderr , <STR_LIT> , priority , priority ) ; if ( priority >= <NUM_LIT> && priority < <NUM_LIT> ) priority >>= <NUM_LIT> ; break ; } } if ( is_dispatch_slot_restricted ( insn ) && reload_completed && current_sched_info

-> sched_max_insns_priority && rs6000_sched_restricted_insns_priority ) {


<s> else xstormy16_print_operand_address ( file , VOIDmode , x ) ; return ; case 'o' : case 'O' : { HOST_WIDE_INT xx = <NUM_LIT> ; if ( CONST_INT_P ( x ) ) xx = INTVAL ( x ) ; else output_operand_lossage ( <STR_LIT> ) ; if ( code == 'O' ) xx = - xx ; fprintf ( file , IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC , xx - <NUM_LIT> ) ; return ; } case 'b' : { HOST_WIDE_INT xx = <NUM_LIT> ; HOST_WIDE_INT l ; if ( CONST_INT_P ( x ) ) xx = INTVAL ( x ) ; else output_operand_lossage ( <STR_LIT> ) ; l = <NUM_LIT> - xx ; fputs ( IMMEDIATE_PREFIX , file ) ; fprintf ( file , HOST_WIDE_INT_PRINT_DEC , l ) ; return ; } case <NUM_LIT> : break ; default : output_operand_lossage ( <STR_LIT> ) ; return ; } switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO (


<s> int64_t Val = CE -> getValue ( ) ; return ( ( Val & <NUM_LIT> ) == <NUM_LIT> && Val >= - <NUM_LIT> && Val <= <NUM_LIT> ) ||


<s> SDValue TVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> return __builtin_ia32_rcpsh_mask ( __B , __A , _mm_setzero_ph ( ) , ( __mmask8 )


<s> if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { Info =


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; unsigned removed = <NUM_LIT> ; while ( I != REnd && removed < <NUM_LIT> ) { if ( I -> isDebugInstr ( ) ) { ++ I ; continue ; } if ( ! getAnalyzableBrOpc ( I -> getOpcode ( ) ) ) break ; I -> eraseFromParent ( ) ; I = MBB . rbegin (


<s> return decodeRegisterClass ( Inst , RegNo


<s> return ( int32x2_t ) __builtin_neon_vclsv2si


<s> if ( sched_verbose ) fprintf ( dump , <STR_LIT> ) ; if ( reload_completed && rs6000_sched_groups ) { if ( sel_sched_p ( ) ) return ; if ( rs6000_sched_insert_nops == sched_finish_none ) return ; if ( rs6000_sched_insert_nops == sched_finish_pad_groups ) n_groups = pad_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; else n_groups = redefine_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info ->


<s> MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB


<s> if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG ) ) return RV ; if ( Subtarget . hasCMov ( ) ) if ( SDValue RV

= combineIntegerAbs ( N , DAG ) ) return RV ;


<s> if ( ( Subtarget -> hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget -> hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumEltsIn128 ) ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> ) ; Opc = <STR_LIT> ; } if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( IdxVal , dl ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } N2 = DAG . getIntPtrConstant ( IdxVal << <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return Op ; } } if ( EltVT == <STR_LIT>


<s> } else { if ( TREE_CODE ( * node ) == FUNCTION_TYPE || TREE_CODE ( * node ) == METHOD_TYPE ) { if ( arm_isr_value ( args ) == ARM_FT_UNKNOWN ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; } } else if ( TREE_CODE ( * node ) == POINTER_TYPE && ( TREE_CODE ( TREE_TYPE ( * node ) ) == FUNCTION_TYPE || TREE_CODE ( TREE_TYPE ( * node ) ) == METHOD_TYPE ) && arm_isr_value ( args ) != ARM_FT_UNKNOWN ) { * node = build_variant_type_copy ( * node ) ; TREE_TYPE ( * node ) = build_type_attribute_variant ( TREE_TYPE ( * node ) , tree_cons ( name , args , TYPE_ATTRIBUTES ( TREE_TYPE ( * node ) ) ) ) ; * no_add_attrs = true ; } else { if ( flags & ( ( int ) ATTR_FLAG_DECL_NEXT | ( int ) ATTR_FLAG_FUNCTION_NEXT | ( int ) ATTR_FLAG_ARRAY_NEXT ) ) { * no_add_attrs = true ; return tree_cons ( name , args ,


<s> IPI != EndIPI ; ++ IPI ) { BasicBlock * CurBB = IPI -> first -> getParent ( ) ; if ( NewBB == CurBB ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; appendAndTransferDominatedUses ( NewPt , User , OpNo , IPI , InsertPts ) ; return true ; } BasicBlock * CommonDominator = DT . findNearestCommonDominator ( NewBB , CurBB ) ; if ( ! CommonDominator ) continue ; if ( CommonDominator != NewBB ) { assert ( CommonDominator != CurBB && <STR_LIT> ) ; NewPt = CommonDominator -> getTerminator ( )


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand


<s> case <STR_LIT> : DupMCID = & TII -> get ( <STR_LIT> ) ; MulMCID = & TII -> get ( <STR_LIT> ) ; break ; case <STR_LIT> : DupMCID = & TII -> get ( <STR_LIT> ) ; MulMCID = & TII -> get ( <STR_LIT> ) ; break ; case <STR_LIT> : RC = & <STR_LIT> ; DupMCID = & TII -> get ( <STR_LIT> ) ; MulMCID = & TII -> get ( <STR_LIT> ) ; break ; case <STR_LIT> : RC = & <STR_LIT> ; DupMCID = & TII -> get ( <STR_LIT> ) ; MulMCID = & TII -> get ( <STR_LIT> ) ; break ; case <STR_LIT> : RC = & <STR_LIT> ; DupMCID = & TII -> get ( <STR_LIT> ) ; MulMCID = & TII -> get ( <STR_LIT> ) ; break ; case <STR_LIT> : RC = & <STR_LIT> ; DupMCID = & TII -> get ( <STR_LIT> ) ; MulMCID = & TII -> get ( <STR_LIT> ) ; break ; } if ( ! shouldReplaceInstruction ( MI . getParent ( ) -> getParent ( ) , & TII -> get ( MI . getOpcode ( ) ) , DupMCID , MulMCID , * VecInstElemTable ) ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned MulDest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src0IsKill = getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned SrcReg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1IsKill = getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DupDest ; if ( MI . getNumOperands ( ) == <NUM_LIT> ) { unsigned SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2IsKill = getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned LaneNumber = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! reuseDUP ( MI , DupMCID -> getOpcode ( ) , SrcReg2 , LaneNumber , & DupDest ) ) { DupDest = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , MI , DL , * DupMCID , DupDest ) . addReg ( SrcReg2 , Src2IsKill ) . addImm ( LaneNumber ) ; } BuildMI ( MBB , MI , DL , * MulMCID , MulDest ) . addReg ( SrcReg0 , Src0IsKill ) . addReg ( SrcReg1 , Src1IsKill ) . addReg ( DupDest , Src2IsKill ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT>


<s> bool IsByte = std :: is_same < int8_t , std :: make_signed_t < T >> :: value || std :: is_same < int8_t , T > :: value ; if ( auto ShiftedImm = getShiftedVal < <NUM_LIT> > ( ) ) if ( ! ( IsByte && ShiftedImm -> second ) && <STR_LIT> < T > ( uint64_t ( ShiftedImm -> first ) << ShiftedImm -> second ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy ::


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor


<s> float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> reg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( arg . type ) == INTEGER_TYPE && TYPE_MODE ( arg . type ) == word_mode ) ; reg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - <NUM_LIT> * UNITS_PER_WORD ) ) ; } return reg ; } bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type && TREE_CODE ( arg . type ) == VECTOR_TYPE ) mode = type_natural_mode ( arg . type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) reg = function_arg_ms_64 ( cum , mode , arg . mode , arg . named , arg . type , bytes ) ; else reg = function_arg_64 ( cum , mode , arg . mode , arg . type , arg . named ) ; } else reg = function_arg_32 ( cum , mode , arg . mode , arg .


<s> default : return true ; case 'm' : if ( ! SelectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 )


<s> Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_gprmask , <NUM_LIT> ) ; Streamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> EmitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum


<s> rtx_insn * i , * n ; for ( i = insns ; i ; i = NEXT_INSN ( i ) ) if ( INSN_P ( i ) && INSN_CODE ( i ) == CODE_FOR_addsi3 && GET_CODE ( SET_DEST ( PATTERN ( i ) ) ) == REG && GET_CODE ( XEXP ( SET_SRC ( PATTERN ( i ) ) , <NUM_LIT> ) ) == REG && REGNO ( SET_DEST ( PATTERN ( i ) ) ) == REGNO ( XEXP ( SET_SRC ( PATTERN ( i ) ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( SET_SRC ( PATTERN ( i ) ) , <NUM_LIT> ) ) == CONST_INT ) { n = NEXT_INSN ( i ) ; if ( INSN_P ( n ) && INSN_CODE ( n ) == CODE_FOR_addsi3 && GET_CODE ( SET_DEST ( PATTERN ( n ) ) ) == REG && GET_CODE ( XEXP ( SET_SRC ( PATTERN ( n ) ) , <NUM_LIT> ) ) == REG && REGNO ( SET_DEST ( PATTERN ( n ) ) ) == REGNO ( XEXP ( SET_SRC ( PATTERN ( n ) ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( SET_SRC ( PATTERN ( n ) ) , <NUM_LIT> ) ) == CONST_INT ) { int ic = INTVAL ( XEXP ( SET_SRC ( PATTERN ( i )


<s> static SDValue combineFMinFMax ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; if ( ! DAG . getTarget ( ) . Options . UnsafeFPMath ) return SDValue


<s> auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Cond ) ; ( void ) SetI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SetI -> dump ( ) ) ; ++ NumSetCCsInserted ; return


<s> ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress ( GV , <NUM_LIT> , <NUM_LIT> ) ; else MIB . addExternalSymbol ( IntrMemName , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , isVarArg ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept


<s> SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( *

I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op


<s> aarch64_layout_frame ( ) ; return known_eq ( cfun -> machine ->


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; <STR_LIT> AddSub = Val < <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GAHi , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst ) return


<s> int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg (


<s> const MCExpr * Disp = MCConstantExpr :: create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <NUM_LIT> , <STR_LIT> , Out ) ; OrigSPOffset +=


<s> static DecodeStatus DecodeFixedPointScaleImm64 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Imm ) ) ; return


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B


<s> bool isVarArg = DAG . getMachineFunction ( ) . getFunction ( ) -> isVarArg ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; CCState CCInfo ( CC , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeReturn ( Op . getNode ( ) , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Op . getOperand ( i * <NUM_LIT> + <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) assert ( <NUM_LIT> && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT>


<s> static bool ix86_broadcast ( HOST_WIDE_INT v , unsigned int width , HOST_WIDE_INT & val_broadcast ) { wide_int val = wi :: uhwi ( v , HOST_BITS_PER_WIDE_INT ) ; val_broadcast = wi :: extract_uhwi ( val , <NUM_LIT> , width ) ; for ( unsigned int i = width ; i < HOST_BITS_PER_WIDE_INT ; i += width ) { HOST_WIDE_INT each = wi :: extract_uhwi ( val , i , width ) ; if ( val_broadcast != each ) return false ; } val_broadcast = sext_hwi ( val_broadcast , width ) ; return


<s> targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( <STR_LIT> , asm_out_file ) ; for ( idx = <NUM_LIT> ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_DIFF_ELT ( asm_out_file , body , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , <NUM_LIT> , idx ) , <NUM_LIT> ) ) , CODE_LABEL_NUMBER ( base ) ) ; } if ( TARGET_GAS ) fputs


<s> EVT VT = V2 . getValueType ( ) ; SDValue V1 = IsZero ? getZeroVector ( VT , Subtarget -> hasSSE2 ( ) , Subtarget -> hasAVX2 ( ) , DAG , V2 . getDebugLoc ( ) ) : DAG . getUNDEF ( VT ) ; unsigned NumElems = VT .


<s> const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( auto Ty : { v2s64 , v4s64 } ) setAction ( { G_MUL


<s> int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno


<s> unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( getLdStBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getLdStBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB


<s> vresult = vec_vpkswss ( vm1 , vm1 ) ; return ( ( __m64 ) __builtin_unpack_vector_int128 ( ( __vector __int128 ) vresult , <NUM_LIT> )


<s> Type * DestTy = I -> getType ( ) ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; bool isZExt = isa < ZExtInst > ( I ) ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT , DestEVT ; SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitIntExt ( SrcVT , SrcReg , DestVT , ResultReg , isZExt ) ) return false ; updateValueMap ( I , ResultReg ) ; return true


<s> MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ; auto TBL2 = MIRBuilder . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { RegSeq , IndexLoad -> getOperand ( <NUM_LIT> )