<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } enum { COFF = ( <NUM_LIT> << MCContext :: IsCOFF ) , ELF = ( <NUM_LIT> << MCContext :: IsELF ) , MACHO = ( <NUM_LIT> << MCContext :: IsMachO ) , WASM = ( <NUM_LIT> << MCContext :: IsWasm ) , } ; static const struct PrefixEntry { const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = llvm :: find_if ( PrefixEntries , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } uint8_t


<s> int code = GET_CODE ( x ) ; bool float_mode_p = FLOAT_MODE_P ( mode ) ; switch ( code ) { case CONST_INT : if ( SMALL_INT ( x ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case CONST_WIDE_INT : * total = <NUM_LIT> ; if ( ! SPARC_SIMM13_P ( CONST_WIDE_INT_ELT ( x , <NUM_LIT> ) ) ) * total += <NUM_LIT> ; if ( ! SPARC_SIMM13_P ( CONST_WIDE_INT_ELT ( x , <NUM_LIT> ) ) ) * total += <NUM_LIT> ; return true ; case HIGH : * total = <NUM_LIT> ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case MEM : if ( outer_code == ZERO_EXTEND ) { * total = sparc_costs -> int_zload - COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == SIGN_EXTEND ) { * total = sparc_costs -> int_sload - COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( float_mode_p ) { * total = sparc_costs -> float_load ; } else { * total = sparc_costs -> int_load ; } return true ; case PLUS : case MINUS : if ( float_mode_p ) * total = sparc_costs -> float_plusminus ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case FMA : { rtx sub ; gcc_assert ( float_mode_p ) ; * total = sparc_costs -> float_mul ; sub = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == NEG ) sub = XEXP ( sub , <NUM_LIT> ) ; * total += rtx_cost ( sub , mode , FMA , <NUM_LIT> , speed ) ; sub = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == NEG ) sub = XEXP ( sub , <NUM_LIT> ) ; * total += rtx_cost ( sub , mode , FMA , <NUM_LIT> , speed ) ; return true ; } case MULT : if ( float_mode_p ) * total = sparc_costs -> float_mul ; else if ( TARGET_ARCH32 && ! TARGET_HARD_MUL ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else { int bit_cost ; bit_cost = <NUM_LIT> ; if ( sparc_costs -> int_mul_bit_factor ) { int nbits ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; for ( nbits = <NUM_LIT> ; value != <NUM_LIT> ; value &= value - <NUM_LIT> ) nbits ++ ; } else nbits = <NUM_LIT> ; if ( nbits < <NUM_LIT> ) nbits =


<s> const PtrToIntOperator * SubRHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! SubLHS || ! SubRHS ) return nullptr ; if ( SubLHS -> getPointerAddressSpace ( ) != <NUM_LIT> || SubRHS -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; const auto * GOLHS = dyn_cast < GlobalObject > ( SubLHS -> getPointerOperand ( ) ) ; const auto * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ; if ( ! GOLHS || ! GVRHS ) return


<s> assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) ,


<s> return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII


<s> unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O <<


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelPLT ( ) const { assert ( m_pRelPlt != NULL


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'y' : { const char * RegName = <STR_LIT> ; if ( ! Subtarget . isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName << <STR_LIT> ; printOperand ( MI , OpNo , O ) ; return false ; } } } assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O <<


<s> } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base .


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI ,


<s> for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return


<s> static Target The<ISA_LIT>Target ; return


<s> SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE &&


<s> tau = ( ( v - sigma ) + w ) / c ; u = t + tau ; if ( nonfinite ( u ) ) return u ; z . dval [ <NUM_LIT> ] = u ; z . dval [ <NUM_LIT> ] = ( t - u ) + tau ; return z .


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT>


<s> case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onLShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onRShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onXor ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onAnd ( ) ; else return false ; return true


<s> break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = fastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , false , Addr . Offset , <STR_LIT> ) ; Addr . Offset


<s> const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , v4s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v4s32 , v2s64 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_FCONSTANT , s32 } ,


<s> MAI = new <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } break ; default : if ( TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( TT ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; break ; } unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MAI -> addInitialFrameState ( MCCFIInstruction :: createDefCfa ( nullptr


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget .


<s> return emitGlobalConstant ( DL , ACPC -> getPromotedGlobalInit ( ) ) ; } MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { MCSym = getCurExceptionSym ( ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( DotSym


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( hasBasePointer ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> )


<s> } if ( all_same && GET_MODE_SIZE ( inner_mode ) <= <NUM_LIT> ) { x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( target , gen_vec_duplicate ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; rtx index = GEN_INT ( one_var ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ; neon_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , one_var ) ) ; switch ( mode ) { case E_V8QImode : emit_insn ( gen_neon_vset_lanev8qi ( target , x , target , index ) ) ; break ; case E_V16QImode : emit_insn ( gen_neon_vset_lanev16qi ( target , x , target , index ) ) ; break ; case E_V4HImode : emit_insn ( gen_neon_vset_lanev4hi ( target , x , target , index ) ) ; break ; case E_V8HImode : emit_insn ( gen_neon_vset_lanev8hi ( target , x , target , index ) ) ; break ; case E_V2SImode : emit_insn ( gen_neon_vset_lanev2si ( target , x , target , index ) ) ; break ; case E_V4SImode : emit_insn ( gen_neon_vset_lanev4si ( target , x , target , index ) ) ; break ; case E_V2SFmode : emit_insn ( gen_neon_vset_lanev2sf ( target , x , target , index ) ) ; break ; case E_V4SFmode : emit_insn ( gen_neon_vset_lanev4sf ( target , x , target , index ) ) ; break ; case E_V2DImode : emit_insn ( gen_neon_vset_lanev2di ( target , x , target , index ) ) ; break ; default : gcc_unreachable ( ) ; } return ; } mem = assign_stack_temp ( mode ,


<s> LastEmittedMI = SU -> getInstr ( ) ; return ; } for ( TargetSchedModel :: ProcResIter PI = SchedModel -> getWriteProcResBegin ( SC ) , PE = SchedModel -> getWriteProcResEnd ( SC ) ; PI != PE ; ++ PI ) { if ( SchedModel -> getProcResource ( PI -> ProcResourceIdx ) -> BufferSize == <NUM_LIT> ) continue ; int & CurrCounter = ProcResourceCounters [ PI -> ProcResourceIdx ] ; CurrCounter += PI -> Cycles ; if ( ( CurrCounter > ProcResCostLim ) && ( CriticalResourceIdx == UINT_MAX || ( PI -> ProcResourceIdx != CriticalResourceIdx && CurrCounter > ProcResourceCounters [ CriticalResourceIdx ] ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SchedModel -> getProcResource ( PI -> ProcResourceIdx ) -> Name << <STR_LIT> ; ) ; CriticalResourceIdx = PI ->


<s> MVT IntEltVT = <STR_LIT> ( NumEltBits ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , DL , IntEltVT ) ; if ( EltVT . isFloatingPoint ( ) ) { Zero = DAG . getBitcast ( EltVT , Zero ) ; AllOnes = DAG . getBitcast ( EltVT , AllOnes ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V


<s> result = arm_rtx_costs_internal ( x , ( enum rtx_code ) code , ( enum rtx_code ) outer_code , current_tune -> insn_extra_cost , total , speed ) ; if ( dump_file && ( dump_flags


<s> setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( MF ) ; if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex (


<s> unsigned SubSizeInBits = SrcSizeInBits / <NUM_LIT> ; InVT = EVT :: getVectorVT ( Ctx , InVT , SubSizeInBits / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , SubSizeInBits / OutVT . getSizeInBits ( ) ) ; if ( SrcVT . is256BitVector ( ) && DstVT . is128BitVector ( ) ) { Lo = DAG . getBitcast ( InVT , Lo ) ; Hi = DAG . getBitcast ( InVT , Hi ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , Lo , Hi ) ; return DAG . getBitcast ( DstVT , Res ) ; } if ( SrcVT . is512BitVector ( ) && Subtarget . hasInt256 ( ) ) { Lo = DAG . getBitcast ( InVT , Lo ) ; Hi = DAG . getBitcast ( InVT , Hi ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , Lo , Hi ) ; SmallVector < int , <NUM_LIT> > Mask ; int Scale = <NUM_LIT> / OutVT . getScalarSizeInBits ( ) ; scaleShuffleMask ( Scale , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , Mask ) ; Res = DAG . getVectorShuffle ( OutVT , DL , Res , Res , Mask ) ; if ( DstVT . is256BitVector ( ) ) return DAG . getBitcast ( DstVT , Res ) ; EVT PackedVT = EVT :: getVectorVT ( Ctx , PackedSVT , NumElems ) ; Res = DAG . getBitcast ( PackedVT , Res ) ; return truncateVectorWithPACK ( Opcode , DstVT , Res , DL , DAG , Subtarget ) ; } assert ( SrcSizeInBits >= <NUM_LIT> && <STR_LIT> ) ; EVT PackedVT = EVT :: getVectorVT ( Ctx


<s> switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : { Register ExtReg = MRI . createGenericVirtualRegister ( LocTy ) ; MIRBuilder . buildSExt ( ExtReg , ValReg ) ; return ExtReg ; } case CCValAssign :: ZExt :


<s> auto Mapper = <STR_LIT> ( getAvailableFeatures ( ) ) ; std :: string Name = Mapper . toString ( Val ) ; O << StringRef ( Name ) . upper


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addAddrMode2Operands ( Inst , <NUM_LIT> ) ;


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( auto * CN = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc


<s> static bool isSRL16 ( const SDValue & Op ) { if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; if ( auto Const = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT>

) ) ) return Const -> getZExtValue ( ) == <NUM_LIT> ;


<s> auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT SrcVT = N . getValueType ( ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getScalarType ( ) , Size / SrcVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / SrcVT . getSizeInBits ( ) , DAG . getUNDEF ( SrcVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , DstVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; Opcode = getOpcode_EXTEND_VECTOR_INREG ( Opcode ) ; return DAG . getNode ( Opcode , DL , VT , ExOp ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits (


<s> M = getTargetVShiftByConstNode ( <STR_LIT> , dl , <STR_LIT> , M , <NUM_LIT> , DAG ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , M ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , M , R ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Op ) ; OpVSel = DAG . getNode ( <STR_LIT> , dl , VT , VSelM , Op ) ; OpVSel = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , VSelM ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , OpVSel , DAG . getNode ( <STR_LIT> , dl , VT , R , R ) , R ) ; return R ; } if ( VT . is256BitVector ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; SDValue V1 = Extract128BitVector ( R , <NUM_LIT> , DAG , dl ) ; SDValue V2 = Extract128BitVector ( R , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue Amt1 , Amt2 ; if ( Amt . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Amt1Csts ; SmallVector < SDValue , <NUM_LIT> > Amt2Csts ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) Amt1Csts . push_back ( Amt -> getOperand ( i ) ) ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) Amt2Csts . push_back ( Amt -> getOperand ( i ) ) ; Amt1 = DAG . getNode ( <STR_LIT> , dl , NewVT , & Amt1Csts [ <NUM_LIT> ] , NumElems / <NUM_LIT> ) ; Amt2 = DAG . getNode ( <STR_LIT> , dl , NewVT , & Amt2Csts [ <NUM_LIT> ] , NumElems / <NUM_LIT> ) ; } else


<s> diff = d -> perm [ <NUM_LIT> ] ; switch ( diff ) { case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ;


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> )


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> } else { uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; return DAG . getNode ( <STR_LIT> , DL


<s> return ( __A [ <NUM_LIT> ] > __B [ <NUM_LIT> ]


<s> } else { const MCExpr * AdjustExpr = nullptr ; if ( const <ISA_LIT>MCExpr * <ISA_LIT>Expr = dyn_cast < <ISA_LIT>MCExpr > ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ) ) { if ( <ISA_LIT>Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLSGD || <ISA_LIT>Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLSIE || <ISA_LIT>Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLSLDM ) { MCSymbol * Dot = getContext ( ) . createNamedTempSymbol ( ) ; Out . emitLabel ( Dot ) ; AdjustExpr = MCSymbolRefExpr :: create ( Dot , getContext ( ) ) ; } } auto * Expr = getTargetStreamer ( ) . addConstantPoolEntry ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , Inst . getLoc ( ) , AdjustExpr ) ; Inst . erase ( std :: prev ( Inst . end ( ) ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } Inst . setOpcode ( Opcode ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; return


<s> const MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = cast < FrameIndexSDNode > ( Loc ) -> getIndex ( ) ; int BFI = cast < FrameIndexSDNode > ( BaseLoc ) -> getIndex ( ) ; int FS = MFI -> getObjectSize ( FI ) ; int BFS = MFI -> getObjectSize ( BFI ) ; if ( FS != BFS || FS != ( int ) Bytes ) return false ; return MFI -> getObjectOffset ( FI ) == ( MFI -> getObjectOffset ( BFI ) + Dist * Bytes ) ; } if ( DAG . isBaseWithConstantOffset ( Loc ) && Loc . getOperand ( <NUM_LIT> ) == BaseLoc && cast < ConstantSDNode > ( Loc . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) == Dist * Bytes ) return true ; const TargetLowering & TLI = DAG . getTargetLoweringInfo (


<s> const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( STI . isGP32bit ( ) ) OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF ::


<s> else for ( int i = <NUM_LIT> ; i < nregs ; i ++ ) XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , regno + <NUM_LIT> *


<s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const <ISA_LIT>InstrInfo * AAII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( & ST ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , <NUM_LIT> > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { bool


<s> SDValue VAList = DAG . getLoad ( <STR_LIT> , dl , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG . getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , dl , NextPtr , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . getLoad ( VT , dl , InChain , VAList , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue V = DAG . getLoad ( <STR_LIT> , dl , InChain , VAList , MachinePointerInfo ( )


<s> unsigned Size = <NUM_LIT> << getFixupKindLog2Size ( Fixup . Kind ) ; assert ( Fixup . Offset + Size <= DF . getContents ( ) . size ( ) &&


<s> case Instruction :: Store : return <ISA_LIT>SelectStore ( I ) ; case Instruction :: Ret : return <ISA_LIT>SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return <ISA_LIT>SelectCmp ( I ) ; case Instruction :: ZExt : return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: Call : return <ISA_LIT>SelectCall ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction ::


<s> case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; default : gcc_assert ( mode == BLKmode || mode == VOIDmode ) ; return ( regno %


<s> return ELF :: R_<ISA_LIT>_PC_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PC_LO32 ; } } switch ( Fixup . getTargetKind ( ) ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_REFLONG ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_REFQUAD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REFLONG ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO32 ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF ::


<s> <ISA_LIT>MCExpr :: VariantKind SymLoc = <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) ; if ( ( uint32_t ) Fixup . getKind ( ) ==

<STR_LIT> && SymLoc == <ISA_LIT>MCExpr :: VK_GOT ) return true ;


<s> case ENCODING_RD : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RO : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Rv : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_I : if ( readOpcodeModifier ( insn ) ) return - <NUM_LIT> ; break ; case ENCODING_VVVV : if ( readVVVV ( insn ) ) return - <NUM_LIT> ; if ( fixupReg ( insn , & insn -> spec -> operands [ index ] ) ) return - <NUM_LIT> ; break ; case ENCODING_DUP : break ; default : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; } } return <NUM_LIT>


<s> rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef RegName = Tok . getString ( ) ; unsigned Encoding = StringSwitch < unsigned > ( RegName . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Encoding == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBankedReg ( Encoding ,


<s> static bool isVREVMask ( ArrayRef < int > M , EVT VT , unsigned BlockSize ) { assert ( ( BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] <

<NUM_LIT> ) BlockElts = BlockSize / EltSz ;


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const { return TLI


<s> insn -> vexSize = <NUM_LIT> ; } else { unconsumeByte ( insn ) ; } if ( insn -> vexSize == <NUM_LIT> ) { insn -> vexPrefix [ <NUM_LIT> ] = byte ; consumeByte ( insn , & insn -> vexPrefix [ <NUM_LIT> ] ) ; if ( insn -> mode == MODE_64BIT ) { insn -> rexPrefix = <NUM_LIT> | ( rFromVEX2of2 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) ; } switch ( ppFromVEX2of2 ( insn -> vexPrefix [ <NUM_LIT> ] ) ) { default : break ; case VEX_PREFIX_66 : hasOpSize = TRUE ; break ; } dbgprintf ( insn , <STR_LIT> , insn -> vexPrefix [ <NUM_LIT> ] , insn -> vexPrefix [ <NUM_LIT> ] ) ; } } else { if ( insn -> mode == MODE_64BIT ) { if ( ( byte & <NUM_LIT> ) == <NUM_LIT> ) { uint8_t opcodeByte ; if ( lookAtByte ( insn , & opcodeByte ) || ( ( opcodeByte & <NUM_LIT> ) == <NUM_LIT> ) ) { dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; } insn -> rexPrefix = byte ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; dbgprintf ( insn , <STR_LIT> , byte ) ; } else { unconsumeByte ( insn ) ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } } else { unconsumeByte ( insn ) ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } } if ( insn -> mode == MODE_16BIT ) { insn -> registerSize = ( hasOpSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> addressSize = ( hasAdSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> displacementSize = ( hasAdSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> immediateSize = ( hasOpSize ? <NUM_LIT> : <NUM_LIT> ) ; } else if ( insn -> mode == MODE_32BIT ) { insn -> registerSize = ( hasOpSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> addressSize = ( hasAdSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> displacementSize = ( hasAdSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> immediateSize = ( hasOpSize ? <NUM_LIT> : <NUM_LIT> ) ; } else if ( insn -> mode


<s> Function * <ISA_LIT>TargetLowering :: getSSPStackGuardCheck ( const Module &


<s> SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode (


<s> unsigned Reg = VA . getLocReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) return false ; if ( Outs [ I ] . Flags . isSwiftSelf ( ) || Outs [ I ] . Flags . isSwiftError ( ) ) return false ; } return true


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT>

) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ;


<s> if ( CurrentSection == nullptr ) CurrentSection = Streamer . getCurrentSectionOnly ( ) ; auto & Context = Streamer . getContext ( ) ; const MCConstantExpr * C = dyn_cast < MCConstantExpr > ( Value ) ; auto Itr = C ? CachedEntries . find ( C -> getValue ( ) ) : CachedEntries . end ( ) ; if ( Itr != CachedEntries . end ( ) ) return Itr -> second ; MCSymbol * CPEntryLabel = Context . createTempSymbol ( ) ; const auto SymRef = MCSymbolRefExpr :: create ( CPEntryLabel , Context ) ; if ( AdjustExpr ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Value


<s> if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth >


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [


<s> if ( Subtarget . hasAVX2 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; if ( Subtarget . hasBWI ( ) && Bits == <NUM_LIT>


<s> HOST_WIDE_INT size ; size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; return CEIL ( size ,


<s> return ; } Len /= EltSize ; Idx /= EltSize ; for ( int i = <NUM_LIT> ; i != Idx ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back ( i + NumElts ) ; for ( int i = Idx + Len ; i != ( int ) HalfElts ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = HalfElts ; i != ( int ) NumElts

; ++ i ) ShuffleMask . push_back ( SM_SentinelUndef ) ;


<s> virtual bool isFMAFasterThanMulAndAdd ( EVT ) const { return true


<s> else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( RegSize / VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; unsigned BinOp = <NUM_LIT> ; SDValue Root = matchBinOpReduction ( Extract , BinOp , { <STR_LIT> } ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Zext0 , Zext1 ; if ( ! detectZextAbsDiff ( Root , Zext0 , Zext1 ) ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue SAD = createPSADBW ( DAG , Zext0 , Zext1 , DL ) ; unsigned Stages = Log2_32 ( VT . getVectorNumElements ( ) ) ; MVT SadVT = SAD


<s> case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : case G_FSUB : case G_FMUL : case G_FDIV : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; } case G_FCONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping


<s> switch ( VT . getVectorNumElements ( ) ) { default : return EVT ( ) ; case <NUM_LIT> : return VT . changeVectorElementType ( <STR_LIT> ) ; case <NUM_LIT> : return VT . changeVectorElementType ( <STR_LIT> ) ; case <NUM_LIT> : return VT .


<s> unsigned size = ( <NUM_LIT> << len ) ; unsigned R = immr & ( size - <NUM_LIT> ) ; unsigned S = imms & ( size - <NUM_LIT> ) ; assert ( S != size - <NUM_LIT> && <STR_LIT> ) ; uint64_t pattern = ( <NUM_LIT> << ( S + <NUM_LIT> ) ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < R ; ++ i ) pattern = ror ( pattern , size ) ; while ( size != regSize ) { pattern |= ( pattern << size


<s> bool Found = false ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT>


<s> tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) { tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) { tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) { tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> + getReg (


getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ;


<s> for ( i = <NUM_LIT> ; i < nunits ; i ++ ) for ( j = <NUM_LIT> ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + <NUM_LIT> ) * usize - <NUM_LIT> - j ) ; mask = gen_rtx_CONST_VECTOR ( V16QImode , v ) ; return force_reg ( V16QImode ,


<s> Ops [ <NUM_LIT> ] . getAsInteger ( <NUM_LIT> , CRm ) ; Ops [ <NUM_LIT> ] . getAsInteger ( <NUM_LIT> , Op2 ) ; Bits = ( Op0 << <NUM_LIT> ) | ( Op1 << <NUM_LIT> ) | ( CRn << <NUM_LIT> ) | ( CRm << <NUM_LIT> ) | Op2 ; return Bits


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; Register List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; Register DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align


<s> regrename_analyze ( NULL ) ; compute_bb_for_insn ( ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; loop_optimizer_init ( AVOID_CFG_MODIFICATIONS ) ; FOR_EACH_LOOP ( loop , LI_FROM_INNERMOST ) { tag_map_t tag_map ( <NUM_LIT> ) ; record_loads ( tag_map , loop ) ; avoid_collisions ( tag_map ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> num ) ; tag_map . traverse < void * , dump_insn_list > ( NULL ) ; } tag_map . traverse < void * , free_insn_info > ( NULL ) ; } loop_optimizer_finalize ( ) ; free_dominance_info ( CDI_DOMINATORS )


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> && VectorList


<s> Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; HasRt = true ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; if ( HasRt ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder ,


<s> return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , RelocType , Log2Size , FixedValue ) ; } const MCSymbolData * SD = nullptr ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel && RelocType == MachO :: <ISA_LIT>_RELOC_VANILLA ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && SD && ! Writer -> doesSymbolRequireExternRelocation ( SD ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , RelocType , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , SD , FixedValue ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsExtern << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue & <NUM_LIT> ; break ; } MachO :: any_relocation_info MREPair ; MREPair . r_word0


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger (


<s> static MachineBasicBlock * getTargetMBB ( const MachineInstr & Br ) { for ( unsigned I = <NUM_LIT> , E = Br . getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { const MachineOperand & MO = Br .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned getShiftedImmShift ( ) const { assert ( Kind == k_ShiftedImm && <STR_LIT> ) ; return ShiftedImm . ShiftAmount


<s> static DecodeStatus DecodeJumpFR ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Reg = ( int ) fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [ Reg ] ) ) ; if ( CPURegsTable [ Reg ] == <STR_LIT> )


<s> if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; SrcReg = ANDReg ; } const MCInstrDesc & II = TII . get ( Opc ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg ) ; addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOStore , ScaleFactor , MMO


<s> MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget -> hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opcode , dl , MulVT , Hi0 , Hi1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget -> hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> ,


<s> const ELFRelocationEntry & B = * BP ; if ( A . Offset < B . Offset ) return <NUM_LIT> ; if ( A . Offset > B . Offset ) return - <NUM_LIT> ; assert ( B . Type != A . Type &&


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , StByValParamsPadding ( <NUM_LIT> ) , ArgRegsSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) ,

DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> if ( flag_pic && decl && ( ! flag_plt || lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) && ! targetm

. binds_local_p ( decl ) ) return true ;


<s> if ( Node -> hasOneUse ( ) ) { CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return ; } ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ) ; return ; } } SelectCode ( Node )


<s> unsigned MLxExpansion :: getDefReg ( MachineInstr * MI ) const { Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * UseMI = & * MRI -> use_instr_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) !=


<s> ZeroReg = <STR_LIT> ; } else { assert ( SubVT == <STR_LIT> ) ; NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , ZeroReg , SubVT ) ; MachineSDNode * Neg = CurDAG -> getMachineNode ( NegOpc , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = SDValue ( Neg , <NUM_LIT> ) ; } else return false ; } else { uint64_t MaskImm ; if ( ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) ) return false ; if ( countTrailingOnes ( MaskImm ) < Bits ) return false ; NewShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) NewShiftAmt = narrowIfNeeded ( CurDAG , NewShiftAmt ) ; else if ( VT == <STR_LIT> && NewShiftAmt -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; MachineSDNode * Ext = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewShiftAmt , SubReg ) ; NewShiftAmt = SDValue ( Ext , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , NewShiftAmt } ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops


<s> unsigned LL , SC , AND , NOR , ZERO , BEQ ; if ( Size == <NUM_LIT> ) { if ( isMicro<ISA_LIT> ) { LL = <STR_LIT> ; SC = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; } AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand


<s> int32_t lo = Imm & <NUM_LIT> ; NewImm = lo ; int Reg = <NUM_LIT> ; int SpReg = <NUM_LIT> ; rs . enterBasicBlock ( & MBB ) ; rs . forward ( II ) ; BitVector Candidates = RI . getAllocatableSet ( * II -> getParent ( ) -> getParent ( ) , & <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } int DefReg = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { DefReg = MO . getReg ( ) ; break ; } } BitVector Available = rs . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; unsigned FirstRegSaved = <NUM_LIT> , SecondRegSaved = <NUM_LIT> ; unsigned FirstRegSavedTo = <NUM_LIT> , SecondRegSavedTo = <NUM_LIT> ; Reg = Available . find_first ( ) ; if ( Reg == - <NUM_LIT> ) { Reg = Candidates . find_first ( ) ; Candidates . reset ( Reg ) ; if ( DefReg != Reg ) { FirstRegSaved = Reg ; FirstRegSavedTo = <STR_LIT> ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } } else Available . reset ( Reg ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Imm ) . addImm ( - <NUM_LIT> ) ; NewImm = <NUM_LIT> ; if ( FrameReg == <STR_LIT> ) { SpReg = Available . find_first ( ) ; if ( SpReg == - <NUM_LIT> ) { SpReg = Candidates . find_first ( ) ; if ( DefReg != SpReg ) { SecondRegSaved = SpReg ; SecondRegSavedTo = <STR_LIT> ; } if ( SecondRegSaved ) copyPhysReg ( MBB , II , DL , SecondRegSavedTo , SecondRegSaved , true ) ; } else Available . reset ( SpReg ) ; copyPhysReg ( MBB , II , DL , SpReg , <STR_LIT> , false ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg ( SpReg , RegState :: Kill ) . addReg ( Reg ) ; } else BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg (

FrameReg ) . addReg ( Reg , RegState :: Kill ) ;


<s> if ( Opcode == <STR_LIT> ) { assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , HI . getValue ( <NUM_LIT> ) ) ; Chain = DAG . getStore ( ecx . getValue ( <NUM_LIT> ) , DL , ecx , N -> getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LO , Tmp ) ) ; Results . push_back ( Chain ) ; return ; } SDValue Ops [ ] = { LO , HI } ; SDValue Pair = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; Results . push_back ( Pair ) ; Results . push_back (


<s> EVT VT = Vec . getValueType ( ) ; EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . isUndef ( ) ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , makeArrayRef ( Vec -> op_begin ( ) + IdxVal , ElemsPerChunk ) ) ; SDValue VecIdx = DAG . getIntPtrConstant ( IdxVal , dl


<s> switch ( ID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> :


<s> unsigned PtrCopy = MRI . createVirtualRegister ( MRI . getRegClass ( Ptr ) ) ; unsigned OldValCopy = MRI . createVirtualRegister ( MRI . getRegClass ( OldVal ) ) ; unsigned NewValCopy = MRI . createVirtualRegister ( MRI . getRegClass ( NewVal ) ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , PtrCopy ) . addReg ( Ptr ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , OldValCopy ) . addReg ( OldVal ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , NewValCopy ) . addReg ( NewVal ) ; BuildMI ( * BB , II , DL , TII -> get ( AtomicOp ) ) . addReg ( Dest , RegState :: Define | RegState :: EarlyClobber ) . addReg ( PtrCopy , RegState :: Kill ) . addReg ( OldValCopy , RegState :: Kill ) . addReg ( NewValCopy , RegState :: Kill ) . addReg ( Scratch , RegState :: EarlyClobber | RegState :: Define | RegState :: Dead | RegState :: Implicit ) ; MI . eraseFromParent (


<s> if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ?


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; auto UsePMADDWD = [ & ] ( SDValue Op ) { ShrinkMode Mode ; return Op . getOpcode ( ) == <STR_LIT> && canReduceVMulWidth ( Op . getNode ( ) , DAG , Mode ) && Mode != ShrinkMode :: MULU16 && ( ! Subtarget . hasSSE41 ( ) || ( Op -> isOnlyUserOf ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Op -> isOnlyUserOf ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) ; } ; SDValue MulOp , OtherOp ; if ( UsePMADDWD ( Op0 ) ) { MulOp = Op0 ; OtherOp = Op1 ; } else if ( UsePMADDWD ( Op1 ) ) { MulOp = Op1 ; OtherOp = Op0 ; } else return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT ,


<s> bool <ISA_LIT>TargetLowering :: preferIncOfAddToSubOfNot ( EVT VT


<s> virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const { return false


<s> if ( ( Done = SM . isValidEndState ( ) ) ) break ; return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; case AsmToken :: EndOfStatement : Done = true ; break ; case AsmToken :: Real : UpdateLocLex = false ; if ( ParseIntelDotOperator ( SM , End ) ) return true ; break ; case AsmToken :: At : case AsmToken :: String : case AsmToken :: Identifier : { SMLoc IdentLoc = Tok . getLoc ( ) ; StringRef Identifier = Tok . getString ( ) ; UpdateLocLex = false ; unsigned Reg ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( Reg , IdentLoc , End ) ) { if ( SM . onRegister ( Reg , ErrMsg ) ) return Error ( Tok . getLoc ( ) , ErrMsg ) ; break ; } if ( ( UpdateLocLex = ParseIntelNamedOperator ( Identifier , SM ) ) ) break ; InlineAsmIdentifierInfo Info ; const MCExpr * Val ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) { return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else if ( SM . onIdentifierExpr ( Val , Identifier , Info , false , ErrMsg ) ) { return Error ( IdentLoc , ErrMsg ) ; } else break ; } if ( unsigned OpKind = IdentifyIntelInlineAsmOperator ( Identifier ) ) { if ( OpKind == IOK_OFFSET ) return Error ( IdentLoc , <STR_LIT> <STR_LIT> ) ; if ( int64_t Val = ParseIntelInlineAsmOperator ( OpKind ) ) { if ( SM . onInteger ( Val , ErrMsg ) ) return Error ( IdentLoc , ErrMsg ) ; } else return true ; break ; } if ( Identifier . count ( '.' ) && PrevTK == AsmToken :: RBrac ) { if ( ParseIntelDotOperator ( SM , End ) ) return true ; break ; } if ( TK == AsmToken :: At && Parser . parseIdentifier ( Identifier ) ) return Error ( IdentLoc , <STR_LIT> ) ; if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , false , End ) ) return true ; else if ( SM . onIdentifierExpr ( Val , Identifier , Info , true , ErrMsg ) ) return Error ( IdentLoc , ErrMsg ) ; break ; } case AsmToken :: Integer : { SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal ( ) ; End = consumeToken ( ) ; UpdateLocLex = false ; if ( getLexer ( ) . getKind ( ) == AsmToken


<s> GOTDefUsePair & Pair = CandPairs [ Idx ] ; if ( ! BBI -> readsRegister ( Pair . DefReg , TRI ) && ! BBI -> modifiesRegister ( Pair . DefReg , TRI ) ) continue ; const MachineOperand * UseOp = hasPCRelativeForm ( * BBI ) ? & BBI -> getOperand ( <NUM_LIT> ) : nullptr ; if ( UseOp && UseOp -> isReg ( ) && UseOp -> getReg ( ) == Pair . DefReg && UseOp -> isUse ( ) && UseOp -> isKill ( ) ) { Pair . UseInst = BBI ; Pair . UseReg = BBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ValidPairs . push_back ( Pair ) ; } CandPairs . erase ( CandPairs . begin ( ) + Idx ) ; } } for ( auto Pair = ValidPairs . begin ( ) ; Pair != ValidPairs . end ( ) ; Pair ++ ) { assert ( Pair -> UseInst . isValid ( ) && Pair -> StillValid && <STR_LIT> ) ; MachineBasicBlock :: iterator BBI = Pair -> DefInst ; ++ BBI ; for ( ; BBI != Pair -> UseInst ; ++ BBI ) { if ( BBI -> readsRegister ( Pair -> UseReg , TRI ) || BBI -> modifiesRegister ( Pair -> UseReg , TRI ) ) { Pair -> StillValid = false ; break ; } } if ( ! Pair -> StillValid ) continue ; MachineOperand ImplDef = MachineOperand :: CreateReg ( Pair -> UseReg , true , true ) ; MachineOperand ImplUse = MachineOperand :: CreateReg ( Pair -> UseReg , false , true ) ; Pair -> DefInst -> addOperand ( ImplDef ) ; Pair -> UseInst -> addOperand ( ImplUse ) ; MCContext & Context = MF -> getContext ( ) ; MCSymbol * Symbol = Context . createTempSymbol ( Twine ( <STR_LIT> ) , false , false ) ; MachineOperand PCRelLabel = MachineOperand :: CreateMCSymbol ( Symbol , <STR_LIT> ) ; Pair -> DefInst -> addOperand ( * MF , PCRelLabel ) ; Pair -> UseInst -> addOperand ( * MF , PCRelLabel ) ; MadeChange |= true


<s> Load . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; Load . addOperand ( MCOperand :: CreateReg ( DestReg ) ) ; Load . addOperand ( MCOperand :: CreateReg ( BaseReg ) ) ; Load . addOperand ( MCOperand :: CreateImm ( Scale ) ) ; Load . addOperand ( MCOperand :: CreateReg


<s> default : return false ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT>


<s> return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; return CTX . getRegisterInfo ( ) -> getEncodingValue


<s> <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPV ) ; MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; OS << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; MCSym = OutContext . GetOrCreateSymbol ( OS . str ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment


<s> can_issue_more = issue_rate ; slot = <NUM_LIT> ; insn = get_next_active_insn ( prev_head_insn , tail ) ; group_end = false ; while ( insn != NULL_RTX ) { slot = ( issue_rate - can_issue_more ) ; group_insns [ slot ] = insn ; can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; if ( insn_terminates_group_p ( insn , current_group ) ) can_issue_more = <NUM_LIT> ; next_insn = get_next_active_insn ( insn , tail ) ; if ( next_insn == NULL_RTX ) return group_count + <NUM_LIT> ; group_end = ( can_issue_more == <NUM_LIT> || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; can_issue_more = force_new_group ( sched_verbose , dump , group_insns , next_insn , & group_end , can_issue_more


<s> if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * >


<s> case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return EmitBPOSGE32 ( MI , BB ) ; case <STR_LIT> : return EmitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return EmitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return EmitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return EmitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return EmitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT>


<s> AsmPrinter :: runOnMachineFunction ( MF ) ; return


<s> return ( __m128i ) __builtin_ia32_movdqa32load128_mask ( ( __v4si * ) __P ,


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , <ISA_LIT>Lowering ( * TM . getTargetLowering ( ) ) ,

<ISA_LIT>SubTarget ( * TM . getSubtargetImpl ( ) ) {


<s> return parseAddress ( Operands , BDVMem


<s> bool hasHBC ( ) const { return HasHBC


<s> static inline bool isGadgetEdge ( const Edge &


<s> else gcc_unreachable ( ) ; } if ( symbolic_operand ( src , VOIDmode ) ) { if ( ( TARGET_CMODEL_TINY && ( ! loongarch_global_symbol_p ( src ) || loongarch_symbol_binds_local_p ( src ) ) ) || ( TARGET_CMODEL_TINY_STATIC && ! loongarch_weak_symbol_p ( src ) ) ) { unsigned int align ; if ( LABEL_REF_P ( src ) ) align = <NUM_LIT> ; else if ( CONSTANT_POOL_ADDRESS_P ( src ) ) align = GET_MODE_ALIGNMENT ( get_pool_mode ( src ) ) ; else if ( TREE_CONSTANT_POOL_ADDRESS_P ( src ) ) { tree exp = SYMBOL_REF_DECL ( src ) ; align = TYPE_ALIGN ( TREE_TYPE ( exp ) ) ; align = loongarch_constant_alignment ( exp , align ) ; } else if ( SYMBOL_REF_DECL ( src ) ) align = DECL_ALIGN ( SYMBOL_REF_DECL ( src ) ) ; else if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( src ) && SYMBOL_REF_BLOCK ( src ) != NULL ) align = SYMBOL_REF_BLOCK ( src ) -> alignment ; else align = BITS_PER_UNIT ; if ( align % ( <NUM_LIT> * <NUM_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; } if ( TARGET_CMODEL_TINY || TARGET_CMODEL_TINY_STATIC || TARGET_CMODEL_NORMAL || TARGET_CMODEL_LARGE ) { if ( ! loongarch_global_symbol_p ( src ) || loongarch_symbol_binds_local_p ( src ) ) return <STR_LIT> ; else return <STR_LIT> ; } if ( TARGET_CMODEL_EXTREME ) { sorry ( <STR_LIT> ) ; gcc_unreachable ( ) ; } } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? <STR_LIT> : <STR_LIT> ; if ( dest_code == MEM ) { const char * insn = NULL ; insn = loongarch_output_move_index_float ( XEXP ( dest , <NUM_LIT> ) , GET_MODE ( dest ) , false ) ; if ( insn ) return insn ; return dbl_p ? <STR_LIT> : <STR_LIT> ; } } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) { const char * insn = NULL ; insn = loongarch_output_move_index_float ( XEXP ( src , <NUM_LIT> ) , GET_MODE ( src ) , true ) ; if ( insn ) return insn ; return dbl_p ? <STR_LIT> :


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS (


<s> fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) ,


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , false ) && shouldUseHorizontalOp ( Op0 == Op1 , DAG , Subtarget ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops

[ <NUM_LIT> ] . getValueType ( ) , Ops ) ;


<s> static __inline vec_uint4 spu_mhhadd ( vec_ushort8 a , vec_ushort8 b , vec_uint4 c ) { return ( ( vec_uint4 ) ( si_mpyhhau ( ( qword ) ( a ) , ( qword ) ( b ) ,


<s> virtual bool mayNeedRelaxation ( const MCInst & Inst )


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i + ( RHS ? NumElems : <NUM_LIT> ) ) ) return false ; return true


<s> CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( CurrentFnDescSym ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect


<s> O << <STR_LIT> ; printMemOffset ( MI , OpNo , O


<s> const MCRegisterInfo * MRI = OS . getContext ( ) . getRegisterInfo ( ) ; if ( FrameReg ) { FuncOS << <STR_LIT> << printFPOReg ( MRI , FrameReg ) << <STR_LIT> << FrameRegOff << <STR_LIT> ; } else { FuncOS << <STR_LIT> ; } FuncOS << <STR_LIT> ; for ( RegSaveOffset RO : RegSaveOffsets ) FuncOS << printFPOReg ( MRI , RO . Reg ) << <STR_LIT> << RO . Offset << <STR_LIT> ; CodeViewContext & CVCtx = OS . getContext ( ) . getCVContext ( ) ; unsigned FrameFuncStrTabOff = CVCtx . addToStringTable ( FuncOS . str ( ) ) . second ; unsigned MaxStackSize = <NUM_LIT> ; OS . emitAbsoluteSymbolDiff ( Label , FPO -> Begin , <NUM_LIT> ) ; OS . emitAbsoluteSymbolDiff ( FPO -> End , Label , <NUM_LIT> ) ; OS . EmitIntValue ( LocalSize , <NUM_LIT>


<s> uint64_t Imm = cast < const ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( )


<s> Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; DebugLabelSuffix = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> if ( VT == <STR_LIT> && ! all_of ( Mask , [ LaneSize ] ( int M ) { return M < LaneSize ; } ) ) if ( SDValue V = lowerShuffleAsLanePermuteAndSHUFP ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; bool AllLanes ; if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( ( Mask [ i ] % Size ) / LaneSize ) != ( i / LaneSize ) ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneCrossing [ <NUM_LIT> ] && LaneCrossing [ <NUM_LIT> ] ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneUsed [ <NUM_LIT> ] && LaneUsed [ <NUM_LIT> ] ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> ; i < Size


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get (

<STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasBWI ( )


<s> ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; if ( NeedsWinCFI && SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) { if ( HasWinCFI ) * HasWinCFI = true ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ThisVal ) . setMIFlag ( Flag ) ; } SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset == <NUM_LIT> ) return ; } BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( Offset ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlag ( Flag ) ; if ( NeedsWinCFI ) { if ( ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) || ( SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) ) { if ( HasWinCFI ) * HasWinCFI


<s> unsigned ICMPReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned LHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpInst :: Predicate Cond = static_cast < CmpInst :: Predicate > ( I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; switch ( Cond ) { case CmpInst :: ICMP_EQ : Instructions . emplace_back ( <STR_LIT> , Temp , LHS , RHS ) ; Instructions . emplace_back ( <STR_LIT> , ICMPReg , Temp , <NUM_LIT> ) ; break ; case CmpInst :: ICMP_NE : Instructions . emplace_back ( <STR_LIT> , Temp , LHS , RHS ) ; Instructions . emplace_back ( <STR_LIT> , ICMPReg , <STR_LIT> , Temp ) ; break ; case CmpInst :: ICMP_UGT : Instructions . emplace_back ( <STR_LIT> , ICMPReg , RHS , LHS ) ; break ; case CmpInst :: ICMP_UGE : Instructions . emplace_back ( <STR_LIT> , Temp , LHS , RHS ) ; Instructions . emplace_back ( <STR_LIT> , ICMPReg , Temp , <NUM_LIT> ) ; break ; case CmpInst :: ICMP_ULT : Instructions . emplace_back ( <STR_LIT> , ICMPReg , LHS , RHS ) ; break ; case CmpInst :: ICMP_ULE : Instructions . emplace_back ( <STR_LIT> , Temp , RHS , LHS ) ; Instructions . emplace_back ( <STR_LIT> , ICMPReg , Temp , <NUM_LIT> ) ; break ; case CmpInst :: ICMP_SGT : Instructions . emplace_back ( <STR_LIT> , ICMPReg , RHS , LHS ) ; break ; case CmpInst :: ICMP_SGE : Instructions . emplace_back ( <STR_LIT> , Temp , LHS , RHS ) ; Instructions . emplace_back ( <STR_LIT> , ICMPReg , Temp , <NUM_LIT> ) ; break ; case CmpInst :: ICMP_SLT : Instructions . emplace_back ( <STR_LIT> , ICMPReg , LHS , RHS ) ; break ; case CmpInst :: ICMP_SLE : Instructions . emplace_back ( <STR_LIT> , Temp , RHS , LHS ) ; Instructions . emplace_back ( <STR_LIT> , ICMPReg , Temp , <NUM_LIT> ) ; break ; default : return false ; } MachineIRBuilder B ( I ) ; for ( const struct Instr & Instruction : Instructions ) { MachineInstrBuilder MIB = B . buildInstr ( Instruction . Opcode , Instruction . Def , Instruction . LHS ) ; if ( Instruction . hasImm ( ) ) MIB . addImm ( Instruction . RHS ) ; else MIB . addUse ( Instruction . RHS ) ; if ( ! MIB . constrainAllUses ( TII , TRI , RBI ) ) return false ; } I . eraseFromParent


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { assert ( Offset <= INT_MAX && <STR_LIT> ) ; assert ( MI &&


<s> SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; Lower = DAG . getBitcast ( ExVT , Lower ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return DAG . getBitcast ( VT , Ex ) ; } ; APInt APIntShiftAmt ; if ( ! <STR_LIT> ( Amt , APIntShiftAmt ) ) return SDValue ( ) ; if ( APIntShiftAmt . uge ( VT . getScalarSizeInBits ( ) ) ) return DAG . getUNDEF ( VT ) ; uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; if ( SupportedVectorShiftWithImm ( VT , Subtarget , Op . getOpcode ( ) ) ) return getTargetVShiftByConstNode ( <ISA_LIT>Opc , dl , VT , R , ShiftAmt , DAG ) ; if ( ( ( ! Subtarget . hasXOP ( ) && VT == <STR_LIT> ) || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) ) && Op . getOpcode ( ) == <STR_LIT> ) return ArithmeticShiftRight64 ( ShiftAmt ) ; if ( VT == <STR_LIT> || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && VT == <STR_LIT> ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ShiftVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) { R = DAG . getNode ( <STR_LIT> , dl , VT , R ) ; return DAG . getNode ( <STR_LIT> , dl , VT , R , R ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) { SDValue Zeros = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; if ( VT . is512BitVector ( ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue CMP = DAG . getSetCC ( dl , <STR_LIT> , Zeros , R , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CMP ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Zeros , R ) ; } if ( VT == <STR_LIT> && Subtarget . hasXOP ( ) ) return


<s> return ConstantPools -> addEntry ( Streamer ,


<s> bool isCOP2AsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_COP2 && RegIdx . Index


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitBEConstant ( Value , <NUM_LIT> ,


<s> if ( ! ia64_spec_check_src_p ( src ) ) flags . is_branch = <NUM_LIT> ; return rtx_needs_barrier ( src , flags , pred ) ; } if ( ia64_spec_check_src_p ( src ) ) { gcc_assert ( REG_P ( XEXP ( src , <NUM_LIT> ) ) ) ; need_barrier = rtx_needs_barrier ( XEXP ( src , <NUM_LIT> ) , flags , pred ) ; src = XEXP ( src , <NUM_LIT> ) ; } need_barrier |= rtx_needs_barrier ( src , flags , pred ) ; dst = SET_DEST ( x ) ; if ( GET_CODE ( dst ) == ZERO_EXTRACT ) { need_barrier |= rtx_needs_barrier ( XEXP ( dst , <NUM_LIT> ) , flags , pred ) ; need_barrier |= rtx_needs_barrier ( XEXP ( dst , <NUM_LIT> ) , flags ,


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirective<ISA_LIT> ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID


<s> if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget -> hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( AlignVT , Lo ) ; Hi = DAG . getBitcast ( AlignVT , Hi ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , AlignVT , Hi , Lo , DAG . getConstant ( Rotation * Scale , DL , <STR_LIT> ) ) ) ; } assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - Rotation * Scale ; int HiByteShift = Rotation * Scale ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( HiByteShift , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoShift ,


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI ::


<s> static tree aarch64_builtin_reciprocal ( tree fndecl ) { if ( ! use_rsqrt_p ( ) ) return NULL_TREE ; return aarch64_builtin_rsqrt ( DECL_FUNCTION_CODE ( fndecl )


<s> SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; unsigned NumElems = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int Idx = N -> getMaskElt ( i ) ; if ( Idx >= ( int ) NumElems ) { unsigned Opc = V2 . getOpcode ( ) ; if ( Opc == <STR_LIT> || <STR_LIT> ( V2 . getNode ( ) ) ) continue ; if ( Opc != <STR_LIT> || ! <STR_LIT> ( V2 . getOperand ( Idx - NumElems ) ) ) return false ; } else if ( Idx >= <NUM_LIT> ) { unsigned Opc = V1 . getOpcode ( ) ; if ( Opc == <STR_LIT> || <STR_LIT> ( V1 . getNode ( ) ) ) continue ; if ( Opc != <STR_LIT> || ! <STR_LIT> ( V1 . getOperand ( Idx ) ) )


, <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } } ;


<s> int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? <NUM_LIT> : <NUM_LIT> ; booth_unit_size = <NUM_LIT> ; for ( j = <NUM_LIT> ; i && j < <NUM_LIT> ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , code , <NUM_LIT> , speed ) ; return true ; } * total = COSTS_N_INSNS (


<s> byte_len = ix86_min_insn_size ( insn ) ; path = get_insn_path ( insn ) ; group = get_insn_group ( insn ) ; imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , group_name [ group ] , path , byte_len ) ; fprintf ( file , <STR_LIT> , num_imm_operand , num_imm32_operand , num_imm64_operand