<s> ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb1Only ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment =


<s> static inline bool getBFCInvMask ( uint32_t insn , uint32_t & mask ) { uint32_t lsb = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint32_t msb = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint32_t Val = <NUM_LIT> ; if ( msb < lsb ) { DEBUG ( errs ( )


<s> emit_insn ( nds32_expand_store_multiple ( base_regno , count , * dst_base_reg , * dst_mem , update_base_reg_p , & new_base_reg ) ) ; if ( update_base_reg_p ) { * dst_base_reg = new_base_reg ; * dst_mem = gen_rtx_MEM ( SImode , *


<s> } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else { llvm_unreachable ( <STR_LIT> )


<s> case <STR_LIT> : addDSPCtrlRegOperands ( true , MI , MF ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> useOddSPReg ( ) ) { MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget -> isABI_FPXX ( ) && ! Subtarget -> hasMTHC1 ( ) ) MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) && MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) -> getGlobalIdentifier ( )

== <STR_LIT> ) emitMCountABI ( MI , MBB , MF ) ;


<s> return ( int32x4_t ) __builtin_neon_vqrshlsv4si ( __a ,


<s> if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; SmallVector < int , <NUM_LIT> > Unpckh ; createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred

) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> if ( ! TARGET_FLOAT ) { for ( i = V0_REGNUM ; i <= V31_REGNUM ; i ++ ) { fixed_regs [ i ]


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT . getVectorElementType ( ) != <STR_LIT> || ! TLI . isTypeLegal ( SrcVT ) ) return SDValue ( ) ; if ( Src . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SubVec = Src . getOperand ( <NUM_LIT> ) ; EVT SubVecVT = SubVec . getValueType ( ) ; if ( SubVec . getOpcode ( ) != <STR_LIT> || ! TLI . isTypeLegal ( SubVecVT ) || ! N -> getConstantOperandAPInt ( <NUM_LIT> ) . isMask ( SubVecVT . getVectorNumElements ( ) ) ) return SDValue ( ) ; EVT SetccVT = SubVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! TLI . isTypeLegal ( SetccVT ) || ! ( Subtarget . hasVLX ( ) || SetccVT . is512BitVector ( ) ) ) return SDValue ( ) ; if ( ! ( Subtarget . hasBWI ( ) || SetccVT . getScalarSizeInBits ( ) >= <NUM_LIT> ) ) return SDValue


<s> int NewImm = <NUM_LIT> ; bool ATUsed = false ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( StackSize ) { ATUsed = expandRegLargeImmPair ( <STR_LIT> , StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( NewReg


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , (

<NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , false ) ;


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveVariantPCS ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else if ( IsCOFF ) { if ( IDVal == <STR_LIT> ) parseDirectiveSEHAllocStack ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHPrologEnd ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveR19R20X ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFPLR ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFPLRX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveReg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveLRPair ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFReg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegPX


<s> case <STR_LIT> : case <STR_LIT> : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : return <NUM_LIT>


<s> int <ISA_LIT>AsmParser :: matchRegisterByNumber ( unsigned RegNum , StringRef Mnemonic ) { if ( RegNum > <NUM_LIT> ) return - <NUM_LIT> ; return getReg ( <STR_LIT> ,


<s> EnableTailMerge = ! get<ISA_LIT>Subtarget ( ) .


<s> return ( __m128 ) __builtin_ia32_cvtdq2ps128_mask ( ( __v4si ) __A , ( __v4sf ) _mm_setzero_ps ( )


<s> virtual const char * getPassName ( ) const { return


<s> if ( MI -> getOperand ( Op ) . isExpr ( ) ) return printOperand ( MI , Op , O ) ; O << markup ( <STR_LIT> ) << '$' << formatImm ( MI -> getOperand ( Op ) . getImm (

) & <NUM_LIT> ) << markup ( <STR_LIT> ) ;


<s> return Op . hasOneUse ( ) && <STR_LIT> ( * Op


<s> Op -> FPImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> unsigned regIdx = ConstExpr -> getValue ( ) ; if ( regIdx > <NUM_LIT> || MISCRegs [ regIdx ] == <STR_LIT> ) return false ; Op . Kind = k_Register ; Op . Reg . RegNum = MISCRegs [ regIdx ] ; return


<s> void A15SDOptimizer :: elideCopiesAndPHIs ( MachineInstr * MI , SmallVectorImpl < MachineInstr * > & Outs ) { std :: set < MachineInstr * > Reached ; SmallVector < MachineInstr * , <NUM_LIT> > Front ; Front . push_back ( MI ) ; while ( Front . size ( ) != <NUM_LIT> ) { MI = Front . back ( ) ; Front . pop_back ( ) ; if ( Reached . find ( MI ) != Reached . end ( ) ) continue ; Reached . insert ( MI ) ; if ( MI -> isPHI ( ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { unsigned Reg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( Reg ) ) { continue ; } MachineInstr * NewMI = MRI -> getVRegDef ( Reg ) ; if ( ! NewMI


<s> case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , Op . getDebugLoc ( ) ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( MemOp . getAlignment ( ) < Ty . getSizeInBits ( ) / <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlignment ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB ,


<s> O << <STR_LIT> ; printRegName ( O , BaseAddr . getReg ( ) ) ; unsigned OffsetVal = Offset . getImm ( ) ; if ( OffsetVal ) { O << <STR_LIT> << Offset . getImm ( ) ; } O << <STR_LIT>


<s> if ( CC == CallingConv :: GHC ) return nullptr ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( )


<s> return __builtin_mve_vcvtaq_m_uv8hi ( __inactive ,


<s> if ( ( MEM_P ( src1 ) || bcst_mem_operand ( src1 , mode ) ) && ( MEM_P ( src2 ) || bcst_mem_operand ( src2 , mode ) ) ) return false ; if ( ix86_swap_binary_operands_p ( code , mode , operands ) ) std :: swap ( src1 , src2 ) ; if ( MEM_P ( dst ) && ! rtx_equal_p ( dst


<s> static MachineInstr * createPostIncLoadStore ( MachineInstr * MI , int Offset , Register NewReg , const TargetInstrInfo * TII , const TargetRegisterInfo * TRI ) { MachineFunction * MF = MI -> getMF ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned NewOpcode = getPostIndexedLoadStoreOpcode ( MI -> getOpcode ( ) , Offset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; const MCInstrDesc & MCID = TII -> get ( NewOpcode ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI . constrainRegClass ( NewReg , TRC ) ; TRC = TII -> getRegClass ( MCID , <NUM_LIT> ,


<s> bool isImmSExti64i8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr


<s> return <STR_LIT> ; case <NUM_LIT> : return Opc == TargetOpcode :: G_SEXTLOAD ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Opc == TargetOpcode :: G_SEXTLOAD ?


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2sidi


<s> if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder VLLDM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( STI -> fixCMSE_CVE_2021_35465 ( ) ) { auto Bundler = MIBundleBuilder ( MBB , VLLDM ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; if ( STI -> hasFPRegs ( ) ) Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ) ; else Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addImm ( InlineAsm :: Extra_HasSideEffects ) ) ; finalizeBundle ( MBB , Bundler . begin ( ) , Bundler . end ( ) ) ; } for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT>

) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( SCALAR_FLOAT_TYPE_P ( t ) || INTEGRAL_TYPE_P ( t ) || POINTER_TYPE_P ( t ) ) { HOST_WIDE_INT s = tree_to_shwi ( TYPE_SIZE_UNIT ( t ) ) ; return s == <NUM_LIT> || s == <NUM_LIT> || s == <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT>


<s> return ( ( ( TARGET_ALIGN_DOUBLE || ( TARGET_FPU_DOUBLE && ( mode == DFmode || mode == DCmode ) && cum . arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( mode ) ) ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_WORD ) ? ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] + ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] & <NUM_LIT> ) ) : cum . arg_count [


<s> int i , k ; rtx rvec [ GP_ARG_NUM_REG + <NUM_LIT> ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == <NUM_LIT> || ( n_units == <NUM_LIT> && mode != BLKmode ) ) return gen_rtx_REG

( mode , GP_ARG_MIN_REG + align_words ) ;


<s> if ( KnownReg . Reg != DefReg && ! TRI -> isSuperRegister ( DefReg , KnownReg . Reg ) ) continue ; if ( IsCopy && KnownReg . Imm != <NUM_LIT> ) continue ; if ( IsMoveImm ) { if ( KnownReg . Imm != SrcImm ) continue ; MCPhysReg CmpReg = KnownReg . Reg ; if ( any_of ( MI -> implicit_operands ( ) , [ CmpReg ] ( MachineOperand & O ) { return ! O . isDead ( ) && O . isReg ( ) && O . isDef ( ) && O . getReg ( ) != CmpReg ; } ) ) continue ; } if ( IsCopy ) DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; else DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; NumCopiesRemoved ++ ; UsedKnownRegs . insert ( KnownReg . Reg ) ; RemovedMI = true ; break ; } } } if ( RemovedMI ) continue ; for ( unsigned RI = <NUM_LIT> ; RI < KnownRegs . size ( ) ; ) if ( MI -> modifiesRegister ( KnownRegs [ RI ] . Reg , TRI ) ) { std :: swap ( KnownRegs [ RI ] , KnownRegs [ KnownRegs . size ( ) - <NUM_LIT> ] ) ; KnownRegs . pop_back ( ) ; } else { ++ RI ; } if ( KnownRegs . empty ( ) ) break ; } if ( ! Changed ) return false ; for ( MCPhysReg KnownReg : UsedKnownRegs ) if ( ! MBB -> isLiveIn ( KnownReg ) ) MBB -> addLiveIn ( KnownReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * FirstUse << <STR_LIT> << * LastChange ) ; for ( MachineInstr & MMI : make_range ( FirstUse , PredMBB -> end ( ) ) )


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; const TargetRegisterClass & RC = * MRI . getRegClass ( DstReg ) ; assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , TRI .

getRegSizeInBits ( RC ) / <NUM_LIT> , false ) ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new <ISA_LIT>EB_AsmBackend ( T


<s> assert ( Section && <STR_LIT> ) ; if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( )


<s> if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT>


<s> if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return


<s> } const MCSymbol * A = nullptr ; if ( Target . getSymA ( ) ) A = & Target . getSymA ( ) -> getSymbol ( ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && A && ! Writer -> doesSymbolRequireExternRelocation ( * A ) && recordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ) return ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; const MCSymbol * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { Type = MachO :: GENERIC_RELOC_VANILLA ; } else { if ( A -> isVariable ( ) ) { int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( * A ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = MachO :: GENERIC_RELOC_VANILLA ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | (


<s> OperandMatchResultTy parseBDRAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , BDRMem ,


<s> <ISA_LIT>MCCodeEmitter ( TargetMachine & tm , MCContext & ctx , bool is64Bit ) : TM ( tm )

, TII ( * TM . getInstrInfo ( ) ) , Ctx ( ctx ) {


<s> static bool rs6000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_mode_ok_p [ mode


<s> int NewRetAddrLoc = SPDiff + <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( NewRetAddr ) , false , false , <NUM_LIT> ) ; if ( isDarwinABI ) { int NewFPLoc = SPDiff + <ISA_LIT>FrameLowering :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , MachinePointerInfo :: getFixedStack ( NewFPIdx ) , false , false , <NUM_LIT> ) ; } } return Chain


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PassManager ) { return new <ISA_LIT>PassConfig ( * this , & PassManager


<s> switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : lowerLongBranchLUi ( MI , OutMI )


<s> if ( pred == <NUM_LIT> || pred == <NUM_LIT> ) { unsigned opc = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( opc ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; } unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return DecodeMemBarrierOption ( Inst , imm , Address , Decoder ) ; } unsigned brtarget = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeT2BROperand ( Inst , brtarget , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getEHHandlerRegister (


<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false


, ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> for ( unsigned J = <NUM_LIT> , E = BBOffsets . size ( ) ; J != E ; ++ J ) { DOUT ( llvm :: dbgs ( ) << <STR_LIT> << J << <STR_LIT> << BBOffsets [ J ] << <STR_LIT> << BBSizes [


<s> SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; if ( ! EnableQuadPrecision || ( Op . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOpcode ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) , Op0 .


<s> std :: string HexString = utohexstr ( AI . getLimitedValue ( ) , true ) ; unsigned Size = HexString . size


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr & MI = * -- MBBI ; if ( CompleteCCUsers && ( MI . isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI . eraseFromParent (


<s> bool <ISA_LIT>TargetLowering :: useSoftFloat (


<s> auto AddrTy = Addr -> getValueType ( <NUM_LIT> ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , AddrTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , AddrTy ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc


<s> SDValue Cmp = N -> getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = N -> getOperand ( <NUM_LIT> ) ; SDValue TrueVal = N -> getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>cc = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; if ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV6T2Ops ( ) ) { SDValue R = PerformCMOVToBFICombine ( N , DAG ) ; if ( R ) return R ; } SDValue Res ; if ( CC == <STR_LIT> && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , TrueVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , Cmp ) ; } else if ( CC == <STR_LIT> && TrueVal == RHS ) { SDValue <ISA_LIT>cc ; SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , FalseVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , NewCmp ) ; } if ( CC == <STR_LIT> && LHS . getOpcode ( ) == <STR_LIT> && LHS -> hasOneUse ( ) ) { auto * LHS0C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS0C && LHS0C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) ) ; } } if ( ! VT . isInteger ( ) ) return SDValue ( ) ; if ( isNullConstant ( FalseVal ) ) { if ( CC == <STR_LIT> && isOneConstant ( TrueVal ) ) { if ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV5TOps ( ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( Size == <NUM_LIT> ) { Val = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Val ) . getReg ( <NUM_LIT> ) ; } } Val = MIRBuilder . buildBitcast ( VTy , Val ) . getReg ( <NUM_LIT> ) ; auto CTPOP = MIRBuilder . buildCTPOP ( VTy , Val ) ; Register HSum = CTPOP . getReg ( <NUM_LIT> ) ; unsigned Opc ; SmallVector < LLT > HAddTys ; if ( Ty . isScalar ( ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: scalar ( <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; HAddTys . push_back ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; HAddTys . push_back ( LLT :: fixed_vector


<s> static const <ISA_LIT>MCExpr * CreateHi ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_HI , Expr ,


<s> } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT>


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> off_t i ; for ( i = <NUM_LIT> ; ; i ++ ) { if ( orig [ i ] == '\0' && equiv [ i ] == '\0' ) return TRUE ; if ( orig [ i ] == '\0' || equiv [ i ] == '\0' ) return FALSE ; if ( orig [ i ] !=


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> return ( int16_t ) __builtin_aarch64_sqrdmlshhi ( __a ,


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) || ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) return nullptr ; return &


<s> if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; if ( OptStr . equals_lower ( <STR_LIT> ) ) Opt = <STR_LIT> ; else return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ISBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return


<s> Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isVector ( ) ) return Lower512IntUnary ( Op , DAG ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isScalarInteger ( ) ) { assert ( ! Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT SExtVT = SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Op ) ; SDValue V = DAG . getSExtOrTrunc ( Src , DL , SExtVT ) ; V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , DstVT ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts ; MVT SVT ; if ( SrcVT . isVector ( ) ) { NumElts = SrcVT . getVectorNumElements ( ) ; SVT = SrcVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , Src , DAG . getIntPtrConstant ( i , dl ) ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; NumElts = <NUM_LIT> ; SVT = <STR_LIT> ; } Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getBuildVector ( NewVT , dl , Elts ) ; SDValue ToV2F64 = DAG . getBitcast ( <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) && Subtarget . hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector (


<s> <ISA_LIT>MCExpr :: VariantKind Variant ; if ( isNonConstantExpr ( ImmWithLSL . Val , Variant ) ) { return Variant == <ISA_LIT>MCExpr :: VK_AARCH64_LO12 || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12 || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12_NC ||

Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC_LO12 ;


<s> Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Amt ) ; } if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) { SDValue Z = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , getUnpackl ( DAG , dl , VT , Amt , Z ) ) ; SDValue Hi = DAG . getBitcast ( <STR_LIT> , getUnpackh ( DAG , dl , VT , Amt , Z ) ) ; Lo = convertShiftLeftToScale ( Lo , dl , Subtarget , DAG ) ; Hi = convertShiftLeftToScale ( Hi , dl , Subtarget , DAG ) ; if ( Subtarget . hasSSE41 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; return DAG . getVectorShuffle ( VT , dl , DAG . getBitcast ( VT , Lo ) , DAG . getBitcast ( VT , Hi ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return SDValue (


<s> static Target The<ISA_LIT>Target ; return


<s> align = <NUM_LIT> ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c -> mode ) ) { int align_log = floor_log2 ( GET_MODE_SIZE ( c -> mode ) ) ; insn = emit_insn_after ( gen_align ( GEN_INT ( align_log ) ) , insn ) ; } align = GET_MODE_SIZE ( c -> mode ) ; insn = emit_label_after ( c -> label , insn ) ; insn = dump_constants_1 ( c -> mode , c -> value , insn ) ; next = c -> next ; free ( c


<s> mem_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_3 = operands [ <NUM_LIT> ] ; mem_3 = operands [ <NUM_LIT> ] ; reg_4 = operands [ <NUM_LIT> ] ; mem_4 = operands [ <NUM_LIT> ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) && REG_P ( reg_3 ) && REG_P ( reg_4 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) || REGNO ( reg_3 ) == REGNO ( reg_4 ) ) return false ; } else { mem_1 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; mem_3 = operands [ <NUM_LIT> ] ; reg_3 = operands [ <NUM_LIT> ] ; mem_4 = operands [ <NUM_LIT> ] ; reg_4 = operands [ <NUM_LIT> ] ; } if ( ! MEM_P ( mem_1 ) || aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) || MEM_VOLATILE_P ( mem_3 ) || MEM_VOLATILE_P ( mem_4 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_3 , & base_3 , & offset_3 ) ; if ( base_3 == NULL_RTX || offset_3 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_4 , & base_4 , & offset_4 ) ; if ( base_4 == NULL_RTX || offset_4 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) || ! rtx_equal_p ( base_2 , base_3 ) || ! rtx_equal_p ( base_3 , base_4 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; offval_3 = INTVAL ( offset_3 ) ; offval_4 = INTVAL ( offset_4 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( ( offval_1 != ( offval_2 + msize ) || offval_1 != ( offval_3 + msize * <NUM_LIT> ) || offval_1 != ( offval_4 + msize * <NUM_LIT> ) ) && ( offval_4 != ( offval_3 + msize ) || offval_4 != ( offval_2 + msize * <NUM_LIT> ) || offval_4 != ( offval_1 + msize * <NUM_LIT> ) ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) || reg_mentioned_p ( reg_2 , mem_2 ) || reg_mentioned_p ( reg_3 , mem_3 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( *


<s> bool isScaledSImm ( ) const { if ( isConstantImm ( ) && isShiftedInt < Bits , ShiftLeftAmount > ( getConstantImm


<s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment


<s> case 'f' : if ( Subtarget . hasSPE ( ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT>


<s> DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = Is64BitTarget ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64BitTarget ) : getADDrrOpcode ( Is64BitTarget ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; IsDarwin = TheTriple . isMacOSX ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O


<s> void <ISA_LIT>InstPrinter :: printSVEImm ( T Value , raw_ostream & O ) { typename std :: make_unsigned < T > :: type HexValue = Value ; if ( getPrintImmHex ( ) ) O << '#' << formatHex ( ( uint64_t ) HexValue ) ; else O << '#' << formatDec ( Value ) ; if ( CommentStream ) { if ( getPrintImmHex ( ) ) * CommentStream << '=' << formatDec ( HexValue ) << '\n' ; else * CommentStream << '=' << formatHex ( ( uint64_t ) Value


<s> Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Arg ) ; } CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , VT . getTypeForEVT ( * DAG . getContext ( ) ) , ES , std :: move ( Args ) ) ; return LowerCallTo ( CLI )


<s> inline SDValue getImm ( const SDNode * Node , uint64_t Imm ) const { return CurDAG -> getTargetConstant ( Imm , Node


<s> uint32_t getLdStmModeOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { <STR_LIT> Mode = ( <STR_LIT> ) MI . getOperand ( OpIdx ) . getImm ( ) ; switch ( Mode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI


<s> SDLoc DL ( Op ) ; assert ( Op . getValueType ( ) . isScalableVector ( ) && TLI . isTypeLegal ( Op . getValueType ( ) ) && <STR_LIT> ) ; EVT OutVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , OutVT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT>


<s> if ( TREE_CODE ( * node ) != FUNCTION_TYPE && TREE_CODE ( * node ) != FIELD_DECL && TREE_CODE ( * node ) != TYPE_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name


<s> Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> __inline__ static unsigned long long sh_media_LDLO_Q ( void * p ,


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != <NUM_LIT> ) O << <STR_LIT> ; if ( MI -> getOperand ( i ) . isReg ( ) ) printRegName ( O ,


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler ::


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformSRACombine ( N , DCI ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N )


<s> case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : case ENCODING_Rv : translateRegister ( mcInst , insn . opcodeRegister


<s> static void ix86_init_platform_type_builtins ( void ) { make_cpu_type_builtin ( <STR_LIT> , IX86_BUILTIN_CPU_INIT , INT_FTYPE_VOID


<s> unsigned Reg = VMRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> unsigned SrcOpc1 = Src1 . getOpcode ( ) ; EVT SrcVT0 = Src0 . getValueType ( ) ; EVT SrcVT1 = Src1 . getValueType ( ) ; if ( ! Src1 . isUndef ( ) && ( SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1 ) ) return SDValue ( ) ; switch ( SrcOpc0 ) { case <STR_LIT> : { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> : if ( SrcVT0 ==


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; MI -> getOperand ( PIdx + <NUM_LIT> ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; return true ; } return false


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( RC -> hasType ( <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) { setUsesTOCBasePtr ( * MBB -> getParent ( ) ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } unsigned BaseReg ; if ( MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; else BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( BaseReg ) . addImm ( BPOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin


<s> case Instruction :: Trunc : if ( ! selectCast ( I , <STR_LIT> ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , <STR_LIT> ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false


<s> if ( recog_memoized ( insn ) == CODE_FOR_tlscall ) return true ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_BASE || XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_UNIFIED ) ) return true ; } return false


<s> bool isBDXAddr64Disp12 ( ) const { return isMemDisp12 ( ADDR64Reg , true


<s> SDValue IdxVal = DAG . getIntPtrConstant ( SubVecNumElts * OpIdx , dl ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , Op . getOperand ( OpIdx ) , IdxVal ) ; } MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && V1 . getValueType ( ) . getVectorNumElements ( ) == NumElems / <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getSizeInBits ( ) >= <NUM_LIT> ) return Op ; bool IsZeroV1 = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsZeroV2 = <STR_LIT> ( V2 . getNode ( ) ) ; SDValue ZeroVec = getZeroVector ( ResVT , Subtarget , DAG , dl ) ; if ( IsZeroV1 && IsZeroV2 ) return ZeroVec ; SDValue ZeroIdx = DAG . getIntPtrConstant (


<s> int NumElts = Mask . size ( ) ; int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64Shuffle ( DL , Mask , Zeroable , V1


<s> default_encode_section_info ( decl , rtl , first ) ; if ( first && TREE_CODE ( decl ) == FUNCTION_DECL && ! TARGET_AIX && DEFAULT_ABI == ABI_AIX ) { rtx sym_ref = XEXP ( rtl , <NUM_LIT> ) ; size_t len = strlen ( XSTR ( sym_ref , <NUM_LIT> ) ) ; char * str = XALLOCAVEC ( char , len + <NUM_LIT> ) ; str [ <NUM_LIT> ] = '.' ; memcpy ( str + <NUM_LIT> , XSTR ( sym_ref , <NUM_LIT> ) , len


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinCFISaveLR (


<s> static bool isZeroImm ( const MachineOperand & op ) { return op . isImm ( ) && op . getImm ( ) ==


<s> unsigned int __i = ( unsigned short ) __w << <NUM_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE


<s> if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } NewVal = isNEONModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT>


<s> if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val <


<s> const <ISA_LIT>TargetLowering * <ISA_LIT>TargetLowering :: create ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) { if ( STI . in<ISA_LIT>16Mode ( ) ) return llvm

:: create<ISA_LIT>16TargetLowering ( TM , STI ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext


<s> unsigned AddressSpace = getAddressSpace ( ) ; int Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; const auto & GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; else if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB


<s> auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; if ( STI . in<ISA_LIT>16Mode ( ) )


<s> if ( Callee . getNode ( ) == Chain . getNode ( ) || ! Callee . hasOneUse ( ) ) return false ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Callee . getNode ( ) ) ; if ( ! LD || LD -> isVolatile ( ) || LD -> getAddressingMode ( ) != <STR_LIT> ||

LD -> getExtensionType ( ) != <STR_LIT> ) return false ;


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { switch ( SYSm ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O <<


<s> if ( strip_shift && GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) <= <NUM_LIT> ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , <NUM_LIT> ) ; if ( op != x ) return op


<s> else if ( TheTriple . isOSWindows ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoGNU ( ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MAI -> addInitialFrameState ( MCCFIInstruction :: cfiDefCfa ( nullptr


<s> SDValue zip2 = DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue fcvt_zip1 = DAG . getNode ( <STR_LIT> , dl , NewVT , zip1 ) ; SDValue fcvt_zip2 = DAG . getNode ( <STR_LIT> , dl , NewVT , zip2 ) ; SDValue concat = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , fcvt_zip1 , fcvt_zip2 ) ; Results . push_back ( concat


<s> unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = related_int_vector_mode ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( * this )

, TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , Subtarget ) {


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter ::


<s> bool isLegalMaskedStore ( Type * DataTy ,


<s> virtual void finalizePass ( ) { popTTIStack (


<s> SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Offset = i * ScalarSize ; SDValue Ptr = DAG . getMemBasePlusOffset ( Store -> getBasePtr ( ) , TypeSize :: Fixed ( Offset ) , DL ) ; SDValue Scl = DAG . getNode ( <STR_LIT> , DL , StoreSVT , StoredVal , DAG . getIntPtrConstant ( i , DL ) ) ; SDValue Ch = DAG . getStore ( Store -> getChain ( ) , DL , Scl , Ptr , Store -> getPointerInfo ( ) . getWithOffset ( Offset ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; Stores . push_back ( Ch ) ; } return DAG . getNode ( <STR_LIT> , DL ,


<s> int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , TFI , imm ) ; } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT>


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand ::


<s> Mode = <STR_LIT> ; } else if ( isAM4 && Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> ) { if ( isThumb2 ) return false ; Mode = <STR_LIT> ; } else if ( isAM4 && Offset == - <NUM_LIT> * ( int ) NumRegs ) { Mode = <STR_LIT> ; } else if ( Offset != <NUM_LIT> ) { if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase ; BaseKill = true ; } bool isDPR = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isDef = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; Opcode = getLoadStoreMultipleOpcode ( Opcode ) ; MachineInstrBuilder MIB = ( isAM4 ) ? BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( Mode ) ) . addImm ( Pred ) . addReg ( PredReg ) : BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( Mode , false , isDPR ? NumRegs << <NUM_LIT> : NumRegs ) )

. addImm ( Pred ) . addReg ( PredReg ) ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) || ( VT == <STR_LIT> && Subtarget . useAVX512Regs ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; UseOneConstNR = false ; unsigned Opcode = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Estimate = DAG . getNode ( Opcode , DL , VT , Op ) ; if ( RefinementSteps == <NUM_LIT> && ! Reciprocal ) Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Op , Estimate ) ; return Estimate ; } if ( VT . getScalarType ( ) == <STR_LIT> && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { assert ( Reciprocal && <STR_LIT> ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; if ( VT == <STR_LIT> ) { SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Undef , Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( MCID . TSFlags & <STR_LIT> ) { assert ( MCID . hasOptionalDef ( ) && <STR_LIT> ) ; assert ( MCID . NumOperands == Inst . getNumOperands ( ) && <STR_LIT> ) ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_MnemonicFail ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock


<s> Value * <ISA_LIT>IREmitter :: visitVGETLANEu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> return true ; } if ( IsZExt ) { unsigned Reg64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( Reg , getKillRegState ( true ) ) . addImm ( <STR_LIT> ) ; Reg = Reg64 ; } else { assert ( ( MI -> getOpcode ( ) == TargetOpcode :: COPY && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; } updateValueMap ( I ,


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( Opc , SDLoc ( N ) , N ->

getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> return std :: min ( DL . getABITypeAlignment ( ArgTy ) , DL .


<s> bool ELF<ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) return true ; return false


<s> assert ( ( SegReg || BaseReg || IndexReg ) && <STR_LIT> ) ; assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . XOR (


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmpgt ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A , c ,


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetConstant ( Pattern , DL ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , ErrorStr


<s> return getSubExpr ( ) -> FindAssociatedSection ( )


<s> unsigned Opcode = Instruction :: UserOp1 ; if ( const Instruction * I = dyn_cast < Instruction > ( Obj ) ) { if ( FuncInfo . StaticAllocaMap . count ( static_cast < const AllocaInst * > ( Obj ) ) || FuncInfo . MBBMap [ I -> getParent ( ) ] == FuncInfo . MBB ) { Opcode = I -> getOpcode ( ) ; U = I ; } } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; long TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator II = U -> op_begin ( ) + <NUM_LIT> , IE = U -> op_end ( ) ; II != IE ; ++ II , ++ GTI ) { const Value * Op = * II ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op )


<s> return ( ( qword ) ( vec_sub ( vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) ,

<NUM_LIT> ) , ( vec_short8 ) ( a ) ) ) ) ;


<s> MCInst Tmp ; Tmp . setOpcode ( Opc ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateReg (


<s> void <ISA_LIT>InstPrinter :: printInverseCondCode ( const MCInst * MI , unsigned OpNum


<s> assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( VecSize != <NUM_LIT> && VecSize != <NUM_LIT> ) ) return false ; Type * EltTy = VecTy -> getVectorElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr ,


<s> SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; AM . Scale =


<s> return ( __m128 ) __builtin_ia32_haddps ( ( __v4sf


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL3 = MI -> getDebugLoc ( ) ; MachineFunction :: iterator MBB ; MachineInstr * MIcmp = NULL ; MachineInstr * MItest = NULL ; for ( auto & Reg : functionCallArgs ) { MIcmp = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( getSlaveReg ( Reg ) ) ; MI -> getParent ( ) -> insert (


<s> ShuffleMask . push_back ( i + NElts / <NUM_LIT> ) ; ShuffleMask . push_back ( i + NElts + NElts /


<s> TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } if ( loadImmediate ( HiImmOp64 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; if ( has<ISA_LIT>32r2 ( ) ) { TOut . emitRR ( <STR_LIT> , FirstReg , <STR_LIT> , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , FirstReg , FirstReg , TmpReg , IDLoc , STI ) ; } else { TOut . emitRR ( <STR_LIT> , nextReg ( FirstReg ) , TmpReg , IDLoc , STI ) ; TOut . emitRR ( <STR_LIT> , FirstReg , <STR_LIT> , IDLoc , STI ) ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol (


<s> if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue Madd = DAG . getNode ( <STR_LIT> , DL , MAddVT , N0 , N1 ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , Madd , Zero ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Concat , Phi


<s> if ( any_offset_symbol_operand ( sym , mode ) ) addend = <NUM_LIT> ; else if ( aligned_offset_symbol_operand ( sym , mode ) ) { HOST_WIDE_INT addend_lo , addend_hi ; addend_lo = ( ( addend & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; addend_hi = addend - addend_lo ; if ( addend_lo != <NUM_LIT> ) { op1 = plus_constant ( mode , sym , addend_hi ) ; addend = addend_lo ; } else addend = <NUM_LIT> ; } else op1 = sym ; if ( reload_completed ) { gcc_assert ( addend == <NUM_LIT> ) ; if ( ia64_expand_load_address ( op0 , op1 ) ) return NULL_RTX ; } if ( addend ) { rtx subtarget = ! can_create_pseudo_p ( ) ? op0 : gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( subtarget ,


<s> std :: string <ISA_LIT>COFFTargetAsmInfo :: UniqueSectionForGlobal ( const GlobalValue * GV , SectionKind :: Kind kind ) const { switch ( kind ) { case SectionKind :: Text : return <STR_LIT> + GV -> getName ( ) ; case SectionKind :: Data : case SectionKind :: BSS : case SectionKind :: ThreadData : case SectionKind :: ThreadBSS : return <STR_LIT> + GV -> getName ( )


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { EVT ValTy = Addr . getValueType ( ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) ,


<s> return create<ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move


<s> d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; gcc_assert ( GET_CODE ( sel ) == CONST_VECTOR ) ; gcc_assert ( XVECLEN ( sel , <NUM_LIT> ) == nelt ) ; gcc_checking_assert ( sizeof ( d . perm ) == sizeof ( perm ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , <NUM_LIT> , i ) ; int ei = INTVAL ( e ) &


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreatePrefetch ( unsigned Val , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Prefetch , Ctx ) ; Op -> Prefetch . Val = Val ; Op -> StartLoc


<s> bool MandarinTargetMachine :: addCodeEmitter ( PassManagerBase & PM


<s> if ( Size != <NUM_LIT> ) OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Size - <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( HandleMismatchSym , OutContext ) ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( ReturnSym , OutContext ) ) , * STI ) ; OutStreamer -> EmitLabel ( HandleMismatchSym ) ; } OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; if ( Reg != <STR_LIT> ) OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( AccessInfo ) . addImm ( <NUM_LIT>


<s> if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == <NUM_LIT> || ( mask2 & ix86_isa_flags2 ) != <NUM_LIT> ) && ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type


<s> if ( SrcSize == <NUM_LIT> ) { EVT VecIdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ; EVT SplitVT = N1 . getValueType ( ) . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned SplitNumElts = SplitVT . getVectorNumElements ( ) ; Op1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , N1 , DAG . getConstant ( <NUM_LIT> , DL , VecIdxTy ) ) ; Op2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , N1 , DAG . getConstant ( SplitNumElts , DL , VecIdxTy ) ) ; } else { Op1 = SrcSize == <NUM_LIT> ? N1 : widenVec ( DAG , N1 , DL ) ; Op2 = DAG . getUNDEF ( WideVT ) ; } unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ; SmallVector < int , <NUM_LIT> > ShuffV ; if ( Subtarget . isLittleEndian ( ) ) for ( unsigned i = <NUM_LIT> ; i < TrgNumElts ; ++ i ) ShuffV . push_back ( i * SizeMult ) ; else for ( unsigned i = <NUM_LIT> ; i <= TrgNumElts ; ++ i ) ShuffV . push_back ( i * SizeMult - <NUM_LIT> ) ; for ( unsigned i = TrgNumElts ; i < WideNumElts ; ++ i )

ShuffV . push_back ( WideNumElts + <NUM_LIT> ) ;


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ArrayRef < int > OrigMask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; SmallVector < int , <NUM_LIT> > Mask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != <STR_LIT> || V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse


<s> } } } MachineInstr * VCTP = VCTPs . back ( ) ; TPNumElements = VCTP -> getOperand ( <NUM_LIT> ) ; Register NumElements = TPNumElements . getReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto CannotInsertWDLSTPBetween = [ ] ( MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator E ) { for ( ; I != E ; ++ I ) { if ( shouldInspect ( * I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * I ) ; return true ; } } return false ; } ; if ( CannotInsertWDLSTPBetween ( StartInsertPt , StartInsertBB -> end ( ) ) ) return false ; auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , Register NumElements ) { if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } auto IsValidSub = [ ] ( MachineInstr * MI , int ExpectedVecWidth ) { return - getAddSubImmediate ( * MI ) == ExpectedVecWidth ; } ; MBB = VCTP -> getParent ( ) ; if ( auto * Def = RDA . getUniqueReachingMIDef ( & MBB -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ; Ignore . insert ( VCTPs . begin ( ) , VCTPs . end ( ) ) ; if ( TryRemove ( Def , RDA , ElementChain , Ignore ) ) { bool FoundSub = false ; for ( auto * MI : ElementChain ) { if ( isMovRegOpcode ( MI -> getOpcode ( ) ) ) continue ; if ( isSubImmOpcode ( MI -> getOpcode ( ) ) ) { if ( FoundSub || ! IsValidSub ( MI


<s> if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( Inst -> getOperand ( <NUM_LIT> ) ) ; if ( ! II ) Row = Col = nullptr ; else { switch ( II -> getIntrinsicID ( ) ) { default : Row = Col = nullptr ; break ; case <STR_LIT> : case <STR_LIT> : { Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; } } } if ( ! Row ) { splitST ( Inst ) ; continue ; } IRBuilder < > Builder ( Inst ) ; LLVMContext & Ctx = Builder . getContext ( ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( Inst -> getOperand ( <NUM_LIT> ) , Type :: getInt8PtrTy ( Ctx ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Inst -> getOperand ( <NUM_LIT> ) } ; Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; } return


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineUnmergeValues ( MI , DeadInstrs , UpdatedDefs , Observer ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOpt :: mergeUpdateInsn ( MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator Update , bool IsPreIdx ) { assert ( ( Update -> getOpcode ( ) == <STR_LIT> || Update -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock :: iterator NextI = I ; if ( ++ NextI == Update ) ++ NextI ; int Value = Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode ( I -> getOpcode ( ) ) : getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB ; int Scale , MinOffset , MaxOffset ; getPrePostIndexedMemOpInfo ( * I , Scale , MinOffset , MaxOffset ) ; if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale )

. setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ;


<s> void <ISA_LIT>InstPrinter :: printU4ImmOperand ( const MCInst * MI , int


<s> case E_V8QImode : gen = gen_neon_vrev16v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev32v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev32v4hi ; break ; case E_V4SImode : gen = gen_neon_vrev64v4si ; break ; case E_V2SImode : gen = gen_neon_vrev64v2si ; break ; case E_V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case E_V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = <NUM_LIT> ; i < nelt ; i += diff + <NUM_LIT> ) for ( j = <NUM_LIT> ; j <= diff ; j += <NUM_LIT> ) { gcc_assert ( i + j <


<s> Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( Repeats . AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( Repeats . BytesLeft ( ) ) { unsigned Offset = Repeats . Size - Repeats . BytesLeft ( ) ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , dl , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , dl , SrcVT ) ) , DAG . getConstant (

Repeats . BytesLeft ( ) , dl , SizeVT ) , Align , isVolatile , AlwaysInline , false , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ;


<s> if ( POINTER_TYPE_P ( type ) && FUNC_OR_METHOD_TYPE_P ( TREE_TYPE ( type ) ) ) res = true ; else if ( RECORD_OR_UNION_TYPE_P ( type ) ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) res = res || chkp_type_has_function_pointer (


<s> bool <ISA_LIT>DAGToDAGISel :: MatchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) { SDValue Address = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == <NUM_LIT> && Subtarget -> isTargetELF ( ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) { case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> res . as_int [ <NUM_LIT> ] = m . as_int [ <NUM_LIT> ] << __count ; return ( res .


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBZDisplacementBits ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CBZDisplacementBits ; case


<s> return ( __m128 ) __builtin_ia32_loadlps ( ( __v4sf )


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; assert ( FIST . getNode ( ) && <STR_LIT> ) ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc

( ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ; } return true ; } ; if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc -> getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNOriginalMask ( Shuffle -> getMask ( ) , false ) || isVMOVNOriginalMask ( Shuffle -> getMask ( ) , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB

, MachineBasicBlock :: iterator I ) const {


<s> rtx next = plus_constant ( Pmode , XEXP ( pointer , <NUM_LIT> ) , amount ) ; return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next


<s> if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Id = getParser ( ) . getTok ( ) . getIntVal ( ) ; Kind = ( MCLOHType ) Id ; if ( ! isValidMCLOHType ( Kind ) || Id != Kind ) return TokError ( <STR_LIT> ) ; } else { StringRef Name = getTok ( ) . getIdentifier ( ) ; int Id = MCLOHNameToId ( Name ) ; if ( Id == - <NUM_LIT> ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } Lex ( ) ; int NbArgs = MCLOHIdToNbArgs ( Kind ) ; assert ( NbArgs != - <NUM_LIT> && <STR_LIT> ) ; SmallVector < MCSymbol * , <NUM_LIT> > Args ; for ( int Idx = <NUM_LIT> ; Idx < NbArgs


<s> case TargetOpcode :: G_ZEXTLOAD : { auto MMO = * MI . memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI . getMF ( ) -> getSubtarget ( ) ) ; if ( ! isPowerOf2_64 ( MMO -> getSize ( ) ) ) return


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>CC ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>CC ,


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( )


<s> static __inline__ double __fsel ( double x , double y , double z ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; int Val = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: createImm


<s> static DecodeStatus DecodeBitfieldMaskOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned msb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned lsb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( lsb > msb ) Check ( S , MCDisassembler :: SoftFail ) ; uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << (


<s> rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_unspec_cond ( tmp , code , pred_mode , pred , op0 , op1 ) ; emit_set_insn ( target , gen_rtx_AND ( pred_mode , gen_rtx_NOT ( pred_mode , tmp )


<s> if ( SYSmvalue == - <NUM_LIT> ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV7Ops ( ) && SYSmvalue >= <NUM_LIT> && SYSmvalue <= <NUM_LIT> ) return - <NUM_LIT> ; if ( Subtarget -> has8MSecExt ( ) && Flags . lower ( ) == <STR_LIT> ) { Flags = <STR_LIT> ; SYSmvalue |= <NUM_LIT> ; } if ( ! Subtarget -> has8MSecExt ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue > <NUM_LIT> ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV8MMainlineOps ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> ) ) return - <NUM_LIT> ; if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> auto Iter = llvm :: find_if ( MI . operands ( ) , [ ] ( MachineOperand & MO ) { return MO . isRegMask ( ) ; } ) ; if ( Iter == MI . operands_end ( ) )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned * , unsigned > * OpcodeTablePtr = NULL ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ; } if ( OpcodeTablePtr


<s> return <NUM_LIT> ; case <NUM_LIT> : if ( NumOps >= <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumOps == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && ( Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> || Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ) return <NUM_LIT> ; return


<s> SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction &


<s> return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; default : return SDValue ( )


<s> MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisDestReg ) . addReg ( StartDestReg ) . addMBB ( StartMBB ) . addReg ( NextDestReg ) . addMBB ( NextMBB ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisSrcReg ) . addReg ( StartSrcReg ) . addMBB ( StartMBB ) . addReg ( NextSrcReg ) . addMBB ( NextMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisCountReg ) . addReg ( StartCountReg ) . addMBB ( StartMBB ) . addReg ( NextCountReg ) . addMBB ( NextMBB ) ; if ( Opcode == <STR_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( ThisDestReg ) . addImm ( DestDisp + <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( ThisDestReg ) . addImm ( DestDisp ) . addImm ( <NUM_LIT> ) . addReg ( ThisSrcReg ) . addImm ( SrcDisp ) ; if ( EndMBB ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; MBB -> addSuccessor ( NextMBB ) ; } MBB = NextMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextDestReg ) . addReg ( ThisDestReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextSrcReg ) . addReg ( ThisSrcReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextCountReg ) . addReg ( ThisCountReg ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NextCountReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; DestBase = MachineOperand :: CreateReg ( NextDestReg , false ) ; SrcBase = MachineOperand :: CreateReg ( NextSrcReg , false ) ; Length &= <NUM_LIT> ; if ( EndMBB && ! Length ) DoneMBB -> addLiveIn ( <STR_LIT>