<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { if ( ( isa & deferred_isa_values ) == <NUM_LIT> && ( isa2 & deferred_isa_values2 ) == <NUM_LIT> ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = <NUM_LIT> ; if ( ix86_builtins_isa [ i ] . leaf_p ) DECL_ATTRIBUTES ( decl ) = build_tree_list ( get_identifier ( <STR_LIT> ) , NULL_TREE ) ; if ( ix86_builtins_isa [ i ] . nothrow_p ) TREE_NOTHROW ( decl


<s> emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow )


<s> void <ISA_LIT>PassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createTypePromotionPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare (


<s> assert ( C . isLegal ( DstDomain ) && <STR_LIT> ) ; double Cost = <NUM_LIT> ; for ( auto * MI : C . instructions ( ) ) Cost += Converters . lookup ( { DstDomain , MI -> getOpcode ( ) } ) -> getExtraCost ( MI , MRI ) ; return Cost


<s> return ( unsigned ) __builtin_ia32_vcvtsd2usi32 ( ( __v2df ) __A


<s> assert ( ( isa < LoadInst > ( VecInst ) || isa < ShuffleVectorInst > ( VecInst ) ) && <STR_LIT> ) ; Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Indices [ i ] , SubVecTy -> getVectorNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = VectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( )


<s> unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , dl ) ; bool Is64Bit = Subtarget . is64Bit ( ) ; MVT SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Result ) ; } else if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( const auto & A : F -> args ( ) ) { if ( A . hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain ,


<s> if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base =


<s> if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ; llvm_unreachable ( <STR_LIT> )


<s> if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) )


<s> if ( ent == NULL ) return NULL ; else return ( void * ) ( segment_base


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( )


<s> auto & STI = * RF . getSubtargetInfo ( ) ; bool Is16BitMode = STI . getFeatureBits ( ) [ <STR_LIT> ] ; return getRelaxedOpcode ( Inst , Is16BitMode ) == Inst


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ::

getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ;


<s> bool MadeChange = false ; if ( Buckets . empty ( ) ) return MadeChange ; SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( auto & Bucket : Buckets ) { if ( Bucket . Elements . size ( ) < DispFormPrepMinThreshold )


<s> if ( IsBigEndian ) { Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; }


<s> if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( IsDef && ! IsUse && VCTP && ! isVCTP ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) return true ; if ( ( Flags & <STR_LIT> ) == <NUM_LIT> && ! IsUse ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> } return true ; } switch ( I . getOpcode ( ) ) { default : break ; case Instruction :: FPToSI : case Instruction :: FPToUI : case Instruction :: SIToFP : case Instruction :: UIToFP : case Instruction :: FPTrunc : case Instruction :: FPExt : return ! ST -> hasFP<ISA_LIT>v8Base ( ) ; } if ( VT . isInteger ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) { switch ( ISD ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } if ( ! VT . isFloatingPoint ( ) ) return false ; if ( TLI -> useSoftFloat ( ) ) { switch ( I . getOpcode ( ) ) { default : return true ; case Instruction :: Alloca : case Instruction :: Load : case Instruction :: Store : case Instruction :: Select : case Instruction :: PHI : return false ; } } if ( I . getType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( I . getType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return


<s> punpcklwd_u ( uint32x2_t s , uint32x2_t t ) { return __builtin_loongson_punpcklwd_u ( s ,


<s> Value * <ISA_LIT>IREmitter :: visitPEXTRW ( const SDNode *


<s> PBQP :: PBQPNum sameParityMax = std :: numeric_limits < PBQP :: PBQPNum > :: min ( ) ; for ( unsigned j = <NUM_LIT> , je = vRrAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRrAllowed ) [ j ] ; if ( ! haveSameParity ( pRd , pRa ) ) if ( costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] != std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) && costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] > sameParityMax ) sameParityMax = costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] ; } for ( unsigned j = <NUM_LIT> , je = vRrAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRrAllowed ) [ j ] ; if ( haveSameParity ( pRd , pRa ) ) if ( sameParityMax > costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] ) costs [ i + <NUM_LIT> ] [ j + <NUM_LIT>


<s> struct cl_target_option * opts ; tree target_tree = NULL_TREE ; if ( current_function_decl ) target_tree = DECL_FUNCTION_SPECIFIC_TARGET ( current_function_decl ) ; if ( target_tree == NULL ) target_tree = target_option_default_node ; opts = TREE_TARGET_OPTION (


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo


<s> return __builtin_ia32_vcvtph2pd512_mask_round ( __A , _mm512_setzero_pd ( ) , ( __mmask8 ) -


<s> const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , TargetFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , TargetFlags ) ; } else


<s> LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( Subtarget . isDarwinABI ( ) ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut . getNode ( ) ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerF128Op ( SDValue Op , SelectionDAG & DAG , const char * LibFuncName , unsigned numArgs ) const { ArgListTy Args ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibFuncName , getPointerTy ( ) ) ; Type * RetTy = Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Type * RetTyABI = RetTy ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue RetPtr ; if ( RetTy -> isFP128Ty ( ) ) { ArgListEntry Entry ; int RetFI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; RetPtr = DAG . getFrameIndex ( RetFI


<s> rtx_code_label * tmp_label = gen_label_rtx ( ) ; char label_buf [ <NUM_LIT> ] ; char buffer [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( label_buf , dest , CODE_LABEL_NUMBER ( tmp_label ) ) ; const char * label_ptr = targetm . strip_name_encoding


<s> if ( ! isMemCpySmall ( Len , Alignment ) ) return false ; int64_t UnscaledOffset = <NUM_LIT> ; Address OrigDest = Dest ; Address OrigSrc = Src ; while ( Len ) { MVT VT ; if ( ! Alignment || Alignment >= <NUM_LIT> ) { if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { VT = <STR_LIT> ; } } else


<s> if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) &&


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addVecListOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAlignedMemoryOperands ( Inst


<s> if ( Fn != ( void * ) ( intptr_t ) <ISA_LIT>CompilationCallback ) { if ( IsPIC ) { intptr_t LazyPtr = getIndirectSymAddr ( Fn ) ; if ( ! LazyPtr ) { LazyPtr = ( intptr_t ) emitGlobalValueIndirectSym ( ( GlobalValue * ) F , Fn , JCE ) ; if ( F ) DOUT << <STR_LIT> << LazyPtr << <STR_LIT> << F -> getName ( ) << <STR_LIT> ; else DOUT << <STR_LIT> << LazyPtr << <STR_LIT> << Fn << <STR_LIT> ; } JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( LazyPtr - ( Addr + <NUM_LIT> + <NUM_LIT> ) ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> ) ; } else { JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT>


<s> static SDValue combineConcatVectors ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; const TargetLowering & TLI = DAG .


<s> if ( ( Imm & <NUM_LIT> ) != <NUM_LIT> ) return false ; uint8_t OptionalPrefixBytes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; int i = <NUM_LIT> ; while ( i < <NUM_LIT> ) { uint8_t Byte = ( Imm >> i ) & <NUM_LIT> ; if ( Byte == <NUM_LIT> ) return true ; if ( ! llvm :: is_contained ( OptionalPrefixBytes , Byte )


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT>


<s> return isThumb ( ) && ! getSTI ( ) . getFeatureBits


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const


<s> } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs ,


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned <ISA_LIT>Reg = <STR_LIT> ; SDValue <ISA_LIT> = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>Reg , <STR_LIT> ) ; SDValue New<ISA_LIT> = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT> , Size ) ; Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , New<ISA_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ <NUM_LIT> ] = { NewVal , Chain } ; return DAG . getMergeValues ( Ops


<s> case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; Align Alignment = GV -> getPointerAlignment ( CurDAG -> getDataLayout ( ) ) ; MaxDisplacement = std :: min ( ( int ) Alignment . value ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase =


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS , bool little ) : <ISA_LIT>ArchVersion ( <ISA_LIT>1 ) , <ISA_LIT>ABI ( O32 ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasMulDivAdd ( false ) , HasMinMax ( false ) , HasSwap ( false ) , HasBitCount ( false ) { std :: string CPU = <STR_LIT> ; <ISA_LIT>ArchVersion =


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , dl , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false ,


<s> std :: tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg ( SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , CvtDesc , DstReg ) . addReg (


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == <NUM_LIT> ) return AM . Base . Reg ; Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT>


<s> static SDValue getV4<ISA_LIT>ShuffleImm8ForMask ( ArrayRef < int > Mask ,

const SDLoc & DL , SelectionDAG & DAG ) {


<s> if ( Sym . getSection ( ) . getKind ( ) . isMergeableCString ( ) || Sym . getSection ( ) . getKind ( ) . isMergeableConst ( )


<s> return ( Val < <NUM_LIT> ) || ( Val >= Low && Val


<s> static bool mep_general_copro_reg ( rtx x ) { while ( GET_CODE ( x ) == SUBREG ) x = XEXP ( x


<s> const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( B -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) { } return ! I -> isBarrier (


<s> ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SuperReg ) ; else for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode (


<s> default : report_fatal_error ( <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS8 ; break ; } break ; case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS16 ; break ; } break ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_SBREL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ : Type = ELF :: R_<ISA_LIT>_TLS_DESCSEQ ; break ; } break ; case <STR_LIT> : case <STR_LIT>


<s> static inline bool isImmHL ( uint64_t Val ) { return ( Val & ~


<s> if ( data -> function_descriptor ) fprintf ( data -> file , <STR_LIT> , buffer , name ) ; else fprintf ( data -> file , <STR_LIT> , buffer , name ) ; } if ( data -> function_descriptor ) fputs ( <STR_LIT> , data -> file ) ; else fputs ( <STR_LIT> , data -> file ) ; RS6000_OUTPUT_BASENAME ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } else if ( DECL_WEAK ( n -> decl ) && ! data -> function_descriptor ) ASM_WEAKEN_DECL ( data -> file , n -> decl , name , NULL ) ; } else { if ( dollar_inside ) { if ( data -> function_descriptor ) fprintf ( data -> file , <STR_LIT> , buffer , name ) ; else fprintf ( data -> file , <STR_LIT> , buffer , name ) ; } if ( data -> function_descriptor ) fputs ( <STR_LIT> , data -> file ) ; else fputs ( <STR_LIT> , data -> file ) ; RS6000_OUTPUT_BASENAME ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } if ( data -> function_descriptor ) fputs ( <STR_LIT>


<s> if ( ! ( STI . getFeatureBits ( ) & Feature ) ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ; } AssemblerOptions . back ( ) -> setFeatures


<s> Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) && ! ( MI . mayLoad ( ) && ! UsedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) && ! mayAlias ( MI , MemInsns , AA ) ) { Flags . setMergeForward ( false


<s> if ( Demanded . countPopulation ( ) == Size ) return false ; unsigned NewOpc ; switch ( Op . getOpcode ( ) ) { default : return false ; case <STR_LIT> : NewOpc = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewOpc = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewOpc = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; } ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; uint64_t Imm = C -> getZExtValue


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { CalleeFn = dyn_cast < Function > ( G -> getGlobal ( ) ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; CalleeFn = M -> getFunction ( E -> getSymbol ( ) ) ; } if ( ! CalleeFn ) return <NUM_LIT> ; assert ( CalleeFn -> hasStructRetAttr ( ) && <STR_LIT> ) ; const PointerType * Ty = cast < PointerType > ( CalleeFn -> arg_begin ( ) -> getType ( ) ) ; const Type * ElementTy = Ty


<s> const MCPhysReg * <ISA_LIT>BaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i64gather_epi64 ( __m256i src , long long int const * base , __m256i index , __m256i mask , const int scale ) { return ( __m256i ) __builtin_ia32_gatherdiv4di ( ( __v4di ) src , base , ( __v4di ) index , (


<s> if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG


<s> if ( ! Register :: isVirtualRegister ( * I ) ) continue ; MachineInstr * Def = MRI -> getVRegDef ( * I ) ; if ( ! Def ) continue ; elideCopiesAndPHIs ( Def , DefSrcs ) ; for ( MachineInstr * MI : DefSrcs ) { if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; Register DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> WidenedLoad ( SmallVectorImpl < LoadInst * > & Lds , LoadInst * Wide ) : NewLd ( Wide ) { for ( auto * I : Lds )


<s> else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { return Op ; } return SDValue ( )


<s> MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefKind = isDarwin ? MCSymbolRefExpr :: VK_<ISA_LIT>_DARWIN_LO16 : MCSymbolRefExpr :: VK_<ISA_LIT>_GAS_LO16 ; else if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefKind = isDarwin ? MCSymbolRefExpr :: VK_<ISA_LIT>_DARWIN_HA16 : MCSymbolRefExpr :: VK_<ISA_LIT>_GAS_HA16 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_None ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind


<s> static DecodeStatus DecodeBFAfterTargetOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { uint64_t LocImm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Val = LocImm + ( <NUM_LIT> << Val ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + Val + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand


<s> APInt KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; uint64_t Masks [ ] = { KnownZero [ <NUM_LIT> ] . getZExtValue ( ) , KnownZero [ <NUM_LIT> ] . getZExtValue ( ) } ; unsigned High , Low ; if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else return Op ; SDValue LowOp = Ops [ Low


<s> __arm_urshr ( uint32_t value , const int shift ) { return __builtin_mve_urshr_si ( value , shift


<s> <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; bool Unsigned = false ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned =


<s> SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , ParmReg , TGA ) ; Chain = DAG . getCopyToReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , TLSAddr ) ; return DAG . getCopyFromReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , PtrVT ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister ( is64bit ? <STR_LIT> :


<s> OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == <STR_LIT> ) MCInstLowering . LowerCPLOAD ( MI


<s> return createELFStreamer ( Ctx , std :: move ( MAB ) , std :: move ( OW ) , std


<s> bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) ( c ) ; dd . d [ <NUM_LIT> ] = cc . d [ <NUM_LIT> ] - aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = cc . d [ <NUM_LIT> ] - aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] ; return ( ( qword ) (


<s> printShiftOperand ( <STR_LIT> , MI , OpNum ,


<s> MachineOperand RegOp0 = getLdStRegOp ( * RtMI ) ; MachineOperand RegOp1 = getLdStRegOp ( * Rt2MI ) ; if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { Register Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } unsigned int MatchPairOpcode = getMatchingPairOpcode ( Opc ) ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( MatchPairOpcode ) ) ; if ( <ISA_LIT>InstrInfo :: isPreLdSt ( * RtMI ) ) MIB . addReg ( BaseRegOp . getReg ( ) , RegState :: Define ) ; MIB . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * Paired } ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; Register DstRegX = DstMO . getReg ( ) ; Register DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIBSXTW ) ->


<s> static bool checkValueMapping ( const RegisterBankInfo :: ValueMapping & VM , RegisterBankInfo :: PartialMapping * BreakDown ) { return VM . NumBreakDowns == <NUM_LIT>


<s> unsigned MinSlotSize = Subtarget -> isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; auto PtrMemVT = getPointerMemTy ( DAG . getDataLayout ( ) ) ; SDValue VAList = DAG . getLoad ( PtrMemVT , DL , Chain , Addr , MachinePointerInfo ( V ) ) ; Chain = VAList . getValue ( <NUM_LIT> ) ; VAList = DAG . getZExtOrTrunc ( VAList , DL , PtrVT ) ; if ( VT . isScalableVector ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( Align && * Align > MinSlotSize ) { VAList = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Align -> value ( ) - <NUM_LIT> , DL , PtrVT ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( - ( int64_t ) Align -> value ( ) , DL , PtrVT ) ) ; } Type * ArgTy = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = std :: max ( ArgSize , MinSlotSize ) ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; VANext = DAG . getZExtOrTrunc ( VANext , DL , PtrMemVT ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr ,


<s> if ( opts -> x_flag_omit_frame_pointer ) opts -> x_flag_omit_leaf_frame_pointer = false ; else if ( opts -> x_flag_omit_leaf_frame_pointer ) opts -> x_flag_omit_frame_pointer = <NUM_LIT> ; if ( ! opts -> x_optimize_size ) { if ( opts -> x_align_loops <= <NUM_LIT> ) opts -> x_align_loops = aarch64_tune_params . loop_align ; if ( opts -> x_align_jumps <= <NUM_LIT> ) opts -> x_align_jumps = aarch64_tune_params . jump_align ; if ( opts -> x_align_functions <= <NUM_LIT> ) opts -> x_align_functions = aarch64_tune_params . function_align ; } aarch64_pcrelative_literal_loads =


<s> if ( Op . getOpcode ( ) == <STR_LIT> && VT . getVectorElementType ( ) . getSizeInBits ( ) == OpVT . getVectorElementType ( ) . getSizeInBits ( ) ) { return DAG . getBitcast ( VT


<s> for ( const FPOInstruction & Inst : FPO -> Instructions ) { switch ( Inst . Op ) { case FPOInstruction :: PushReg : FSM . CurOffset += <NUM_LIT> ; FSM . SavedRegSize += <NUM_LIT> ; FSM . RegSaveOffsets . push_back ( { Inst . RegOrOffset , FSM . CurOffset } ) ; break ; case FPOInstruction :: SetFrame : FSM . FrameReg = Inst . RegOrOffset ; FSM . FrameRegOff = FSM . CurOffset ; break ; case FPOInstruction :: StackAlloc : FSM . CurOffset += Inst . RegOrOffset ; FSM . LocalSize += Inst . RegOrOffset ; if ( FSM . FrameReg ) continue ; break ; } FSM . emitFrameDataRecord ( OS , Inst . Label ) ; } OS . EmitValueToAlignment ( <NUM_LIT> ,


<s> return ( uint64x1_t ) __builtin_neon_vshru_ndi ( ( int64x1_t )


<s> if ( Fast ) { * Fast = ! Subtarget -> isCyclone ( ) || VT . getStoreSize (

) != <NUM_LIT> || Align <= <NUM_LIT> || VT == <STR_LIT> ;


<s> Value * SP = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , { } ) ; Builder . CreateStore ( SP , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; StateFieldIndex = <NUM_LIT> ; ParentBaseState = UseStackGuard ? - <NUM_LIT> : - <NUM_LIT> ; insertStateNumberStore ( & * Builder . GetInsertPoint ( ) , ParentBaseState ) ; Value * LSDA = emitEHLSDA ( Builder , F ) ; LSDA = Builder . CreatePtrToInt ( LSDA , Int32Ty ) ; if ( UseStackGuard ) { Cookie = TheModule -> getOrInsertGlobal ( <STR_LIT> , Int32Ty ) ; Value * Val = Builder . CreateLoad ( Int32Ty , Cookie , <STR_LIT> ) ; LSDA = Builder . CreateXor ( LSDA , Val ) ; } Builder . CreateStore ( LSDA , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; if ( UseStackGuard ) { Value * Val = Builder . CreateLoad ( Int32Ty , Cookie ) ; Value * FrameAddr = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * FrameAddrI32 = Builder . CreatePtrToInt ( FrameAddr , Int32Ty ) ; FrameAddrI32 = Builder . CreateXor ( FrameAddrI32 , Val ) ; Builder . CreateStore ( FrameAddrI32 ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHEpilogStart ( SMLoc


<s> type = TYPE_MOFFS16 ; break ; case <NUM_LIT> : type = TYPE_MOFFS32 ; break ; case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } else if ( type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || type == TYPE_IMM64 ) { uint32_t Opcode = mcInst . getOpcode ( ) ; switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32


<s> DefaultAltIdx = <STR_LIT> ; return true ; } if ( Opt == <STR_LIT> ) { DefaultAltIdx = <STR_LIT> ; return true ; } return false


<s> void <ISA_LIT>TargetAsmStreamer :: emitInst ( uint32_t Inst , char Suffix ) { OS << <STR_LIT> ; if ( Suffix ) OS << <STR_LIT>


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand (


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( ContainerVT . isInteger ( ) && ( VT != ContainerVT ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load .


<s> uint64_t FeatureBits = Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ( FeatureBits & <STR_LIT> ) == <NUM_LIT> || ( FeatureBits & <STR_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( Imm


<s> bool isAddSubShifter ( ) const { if ( ! isShifter ( ) ) return false ; unsigned Val = Shifter . Val ; return <STR_LIT> ( Val ) == <STR_LIT> && ( <STR_LIT> ( Val ) == <NUM_LIT> || <STR_LIT> ( Val )


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> needsAsyncDwarfUnwindInfo ( ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex

( CFIIndex ) . setMIFlags ( MachineInstr :: FrameDestroy ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask (


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ NumOpsAdded ; } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; int64_t CondVal = insn >> <STR_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( CondVal == <NUM_LIT> ? <NUM_LIT> : CondVal ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NumOpsAdded += <NUM_LIT> ; unsigned RegListBits = insn & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++


<s> return __builtin_aarch64_floatunshihf_us (


<s> rtx symbol ; if ( mem != NULL_RTX && GET_CODE ( mem ) == MEM && GET_CODE ( symbol = XEXP ( mem , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_FLAGS ( symbol ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) { const char * name2 ; int p2align = <NUM_LIT> ; bss100_section ( ) ; while ( align > <NUM_LIT> ) { align /= <NUM_LIT> ; p2align ++ ; } name2 = default_strip_name_encoding ( name ) ; if ( global ) fprintf ( stream , <STR_LIT> , name2 ) ; if ( p2align ) fprintf ( stream , <STR_LIT> , p2align ) ; fprintf ( stream , <STR_LIT> , name2 ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; return ; } if ( ! global ) { fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT>


<s> switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Length ; break ; case IOK_SIZE : CVal = Info . Size ; break ; case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc , Len , CVal ) ) ; const MCExpr * Imm = MCConstantExpr :: Create (


<s> switch ( arm_tune ) { case TARGET_CPU_cortexa7 : cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock


<s> bool Res = AssignFn ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ; StackSize = State . getNextStackOffset ( ) ; static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( ! Info . IsFixed ) NumXMMRegs = State . getFirstUnallocated ( XMMArgRegs ) ; return


<s> enum machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , flags


<s> assert ( ( Imm & <NUM_LIT> ) == Imm && <STR_LIT> ) ; switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> return ( ( insn >> <STR_LIT> ) & <NUM_LIT> ) << <NUM_LIT> | ( ( insn >> <STR_LIT> ) &


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ST -> isLittle ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; if ( Op . isUndef ( ) ) return DAG . getUNDEF ( VT ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> void <ISA_LIT>AsmPrinter :: printPICLabel ( const MachineInstr * MI , unsigned Op , raw_ostream & O ) { PrintPICBaseSymbol ( O ) ; O << '\n' ; PrintPICBaseSymbol (


<s> else if ( isa < <ISA_LIT>MCExpr > ( getImm ( ) ) ) { const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > (


<s> if ( ! link ) return false ; for ( ; link ; link = link -> next ) { if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( def ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_use_insn = DF_REF_INSN ( swap_link -> ref


<s> static __inline unsigned long long sh_media_MCMPGT_UB ( unsigned long long mm , unsigned long long mn ) { typedef float v8qi __attribute__ ( ( mode ( V8QI )


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div16qi ( (


<s> OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : return nullptr ; case AtomicOrdering :: SequentiallyConsistent : if ( ! IsStore ) return


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int Imm = CE -> getValue ( ) ; bool isAdd = Imm >= <NUM_LIT>


<s> static void rs6000_function_specific_restore ( struct gcc_options * opts , struct gcc_options


<s> DenseMap < Instruction * , Instruction * > NewPredicates ; for ( auto * I : MaskedInsts ) { <STR_LIT> ID = I -> getIntrinsicID ( ) ; unsigned PredOp = ID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto * Predicate = dyn_cast < Instruction > ( I -> getArgOperand ( PredOp ) ) ; if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; VectorType * VecTy = getVectorType ( I ) ; Value * NumElements = ComputeElements ( TripCount , VecTy ) ; if ( ! NumElements ) continue ; if ( ! isTailPredicate ( Predicate , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << *


<s> const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg ( ) ) ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( Subtarget . hasMTHC1 ( ) ) { BuildMI ( MBB , I , dl , get ( isMicro<ISA_LIT> ? ( FP64 ? <STR_LIT> : <STR_LIT> ) : ( FP64 ? <STR_LIT> : <STR_LIT> ) ) , DstReg ) . addReg ( DstReg )


<s> return __builtin_mve_vsubq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a , __b ,


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return


<s> static AddressingMode getLoadStoreAddrMode ( bool HasVector , Type * Ty ) { if ( HasVector ) return AddressingMode ( false ,


<s> return ia64_function_arg_1 ( cum , mode , type , named


<s> Terminators . clear ( ) ; Terminators . reserve ( NumBlocks ) ; BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( MI ) ; ++ MI


<s> } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == HIGH ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } * win =


<s> if ( LdSt -> getNumOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt -> getOperand ( <NUM_LIT> ) . isImm ( ) || ! ( LdSt -> getOperand ( <NUM_LIT> ) . isImm ( ) && LdSt -> getOperand ( <NUM_LIT> ) . getImm ( ) == LPAC :: ADD ) ) return false ; switch ( LdSt -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; } BaseReg = LdSt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = LdSt -> getOperand ( <NUM_LIT> ) . getImm


<s> void <ISA_LIT>GISelUtils :: changeVectorFCMPPredTo<ISA_LIT>CC ( const CmpInst :: Predicate P , <STR_LIT> & CondCode , <STR_LIT> & CondCode2 , bool & Invert ) { Invert = false ; switch ( P ) { default : changeFCMPPredTo<ISA_LIT>CC ( P , CondCode , CondCode2 ) ; break ; case CmpInst :: FCMP_UNO : Invert = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_ORD : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : case CmpInst :: FCMP_ULT : case CmpInst :: FCMP_ULE : case CmpInst :: FCMP_UGT


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign ,


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mullo_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = a * b ; return ( __m64 ) ( ( __vector long


<s> MCAsmParser & Parser = getParser ( ) ; bool HasExistingPersonality = UC . hasPersonality ( ) ; const MCExpr * IndexExpression ; SMLoc IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( IndexExpression ) || parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) { return true ; } UC . recordPersonalityIndex ( L ) ; if ( ! UC . hasFnStart ( ) ) { return Error ( L , <STR_LIT> ) ; } if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return true ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return true ; } if ( HasExistingPersonality ) { Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes (


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> )


<s> ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; const Constant * C = CP -> getConstVal ( ) ; if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { if ( Subtarget . hasPCRelativeMemops ( ) ) { SDLoc DL ( CP ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ConstPool = DAG . getTargetConstantPool ( C , Ty , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , ConstPool ) ; } setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , GA ) ; } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag ,


<s> if ( ! VT . is256BitVector ( ) ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDValue Narrow = N -> getOperand ( <NUM_LIT> ) ; EVT NarrowVT = Narrow -> getValueType ( <NUM_LIT> ) ; if ( ! NarrowVT . is128BitVector ( ) ) return SDValue ( ) ; if ( Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Narrow -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Narrow -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Narrow ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT WideVT = N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( WideVT != VT ) return


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ImmediateOffset ) return <STR_LIT> ; return <STR_LIT>


<s> static bool CC_<ISA_LIT>O32_FP64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const uint16_t F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; return CC_<ISA_LIT>O32 ( ValNo , ValVT , LocVT , LocInfo ,


<s> if ( ElementBits < <NUM_LIT> ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getNode ( <STR_LIT> , DL , FpVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , FpVT , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> gcc_assert ( flag_delayed_branch ) ; operands [ <NUM_LIT> ] = call_operand ; if ( sparc_leaf_function_p || TARGET_FLAT ) { gcc_assert ( ! ( LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence ) ) ; if ( final_sequence ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; if ( final_sequence ) { rtx_insn * delay ; rtx pat ; delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; pat = PATTERN ( delay ) ; PATTERN ( delay ) = gen_blockage ( ) ; INSN_CODE ( delay ) = - <NUM_LIT> ; final_scan_insn ( delay , asm_out_file , optimize , <NUM_LIT> , NULL ) ; INSN_LOCATION ( delay )


<s> SMLoc getOffsetLoc ( ) const { return OffsetLoc


<s> initSubtargetFeatures ( CPU , FS ) ; return * this


<s> void <ISA_LIT>InstrPostProcess :: postProcessInstruction ( std :: unique_ptr < Instruction > & Inst , const MCInst & MCI ) { setMemBarriers ( Inst ,


<s> if ( OutStreamer . hasRawTextSupport ( ) ) return ; Subtarget -> getMReginfo ( ) . emit<ISA_LIT>ReginfoSectionCG ( OutStreamer , getObjFileLowering ( )


<s> if ( MBB . getNumber ( ) > <NUM_LIT> ) { auto & BS = BlockSizes [ MBB . getNumber ( ) - <NUM_LIT> ] ; BS . first -= BS


<s> if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Res = parseBaseRegImm ( Operands ) ; if ( Res == MatchOperand_Success ) return false ; else if ( Res == MatchOperand_ParseFail ) return true ; } Res = parseImmediate ( Operands ) ; if ( Res == MatchOperand_Success ) return false ; else if ( Res == MatchOperand_ParseFail ) return true ; Error ( getLoc ( ) ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; int64_t Flags = <NUM_LIT> ; if ( Parser . parseAbsoluteExpression ( Flags ) ) return TokError ( <STR_LIT> ) ; getTargetStreamer ( ) . emit<ISA_LIT>HackSTOCG ( Sym


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg


<s> return BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm


<s> if ( N . getOpcode ( ) != <STR_LIT> ) { if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> ) { RHSC /= Scale ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getRegister ( <NUM_LIT>


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv4hi (


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useLoc , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { <ISA_LIT>TargetStreamer * S = new <ISA_LIT>TargetAsmStreamer (


<s> bool & Interesting = ValueEntry -> first ; SmallVector < ValueBit , <NUM_LIT> > & Bits = ValueEntry -> second ; Bits . resize ( NumBits ) ; switch ( V . getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned RotAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) Bits [ i ] = LHSBits [ i < RotAmt ? i + ( NumBits - RotAmt ) : i - RotAmt ] ; return std :: make_pair ( Interesting = true , & Bits ) ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; for ( unsigned i = ShiftAmt ; i < NumBits ; ++ i ) Bits [ i ] = LHSBits [ i - ShiftAmt ] ; for ( unsigned i = <NUM_LIT> ; i < ShiftAmt ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return std :: make_pair ( Interesting = true , & Bits ) ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; const auto & LHSBits = * getValueBits ( V .


<s> } if ( Subtarget -> has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size <


<s> { machine_mode mode = GET_MODE ( dest ) ; rtx tmp_reg = gen_reg_rtx ( mode ) ; rtx tp = aarch64_load_tp ( NULL ) ; if ( mode == ptr_mode ) { if ( mode == DImode ) emit_insn ( gen_tlsie_small_di ( tmp_reg , imm ) ) ; else { emit_insn ( gen_tlsie_small_si ( tmp_reg , imm ) ) ; tp = gen_lowpart ( mode , tp ) ; } } else { gcc_assert ( mode == Pmode ) ; emit_insn ( gen_tlsie_small_sidi ( tmp_reg , imm ) ) ; } emit_insn ( gen_rtx_SET ( mode , dest , gen_rtx_PLUS ( mode , tp , tmp_reg ) ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUIV , imm ) ; return ; } case SYMBOL_SMALL_TPREL : { rtx tp = aarch64_load_tp ( NULL ) ; if ( GET_MODE ( dest ) != Pmode ) tp = gen_lowpart ( GET_MODE ( dest ) , tp ) ; emit_insn ( gen_tlsle_small ( dest , tp , imm ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUIV ,


<s> unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII ->

get ( TargetOpcode :: IMPLICIT_DEF ) , Out ) ;


<s> Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , NULL , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy


<s> for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> + i ) ) { FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; Bundles = & getAnalysis < EdgeBundles > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false


<s> return ( float32x4_t ) __builtin_neon_vmaxfv4sf ( __a ,


<s> using namespace <ISA_LIT>PACKey ; switch ( K ) { case IA : case IB : return <STR_LIT> ; case DA : case DB : return <STR_LIT>


<s> bool Is128 = VecIntVT == <STR_LIT> ; EVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getValueType ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned NumElts = VecIntVT . getVectorNumElements ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; SDValue CstLow = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue CstLowArray [ ] = { CstLow , CstLow , CstLow , CstLow , CstLow , CstLow , CstLow , CstLow } ; SDValue VecCstLow = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstLowArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue CstHigh = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue CstHighArray [ ] = { CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh } ; SDValue VecCstHigh = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstHighArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue CstShift = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue CstShiftArray [ ] = { CstShift , CstShift , CstShift , CstShift , CstShift , CstShift , CstShift , CstShift } ; SDValue VecCstShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstShiftArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { EVT VecI16VT = Is128


<s> return ( __m128 ) __builtin_ia32_gathersiv4sf ( src , base , ( __v4si ) index , mask


<s> inline unsigned createNEONModImm ( unsigned OpCmode , unsigned


<s> llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == nullptr ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction


<s> <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) O << <STR_LIT> <<


<s> CannotTailPredicate = ! ValidateMVEInst


<s> static void errorUnsupported ( SelectionDAG & DAG , const SDLoc & dl , const char *


<s> const InstrItineraryData * getInstrItineraryData


<s> SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget


<s> Inst . addOperand ( MCOperand :: createImm ( MCE


<s> const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) return ReduceSpecial ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop )


<s> bool isUImm16 ( ) const { return ( isConstantImm ( ) && isUInt < <NUM_LIT> > (


<s> static void emitPostSt ( MachineBasicBlock * BB , MachineInstr * Pos , const TargetInstrInfo * TII , const DebugLoc & dl , unsigned StSize , unsigned Data , unsigned AddrIn , unsigned AddrOut , bool IsThumb1 , bool IsThumb2 ) { unsigned StOpc = getStOpcode ( StSize , IsThumb1 , IsThumb2 ) ; assert ( StOpc != <NUM_LIT> && <STR_LIT> ) ; if ( StSize >= <NUM_LIT> ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . addReg ( Data ) ) ; } else if ( IsThumb1 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; MachineInstrBuilder MIB = BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) ; MIB = AddDefaultT1CC (


<s> Value * <ISA_LIT>IREmitter :: visitVSLI (


<s> void mips16_expand_set_fcsr ( rtx newval ) { if ( ! mips16_set_fcsr_stub ) mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ( ) ; rtx fn = mips16_stub_call_address ( mips16_set_fcsr_stub )


<s> raw_svector_ostream OS ( Str ) ; OS << <STR_LIT> << <STR_LIT> << StringRef ( getRegisterName ( reg ) ) . lower ( ) << <STR_LIT> << ( ( reg == <STR_LIT> || reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; OutStreamer . EmitRawText ( OS .


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target


<s> void llvm :: emitFrameOffset ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , StackOffset Offset , const TargetInstrInfo * TII , MachineInstr :: MIFlag Flag , bool SetNZCV , bool NeedsWinCFI , bool * HasWinCFI ) { int64_t Bytes


<s> if ( GET_CODE ( PATTERN ( in_insn ) ) == UNSPEC_VOLATILE ) return


<s> return create<ISA_LIT>AsmBackend ( T , STI , MRI ,


<s> int OpNum = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT8 ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT16 ) ; } for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( )


<s> return ( pUpper16 & ~ <NUM_LIT> ) | ( ( pOffset >>

<NUM_LIT> ) & <NUM_LIT> ) | ( sign << <NUM_LIT> ) ;


<s> return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , false , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , false , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true


<s> const TargetMachine * TM = & MF -> getTarget ( ) ; const TargetInstrInfo * TII = TM -> getInstrInfo ( ) ; const TargetRegisterInfo * TRI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr -> getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx ) { MachineOperand & MO = Instr -> getOperand ( OpIdx ) ; const TargetRegisterClass * OpRegCstraints = Instr -> getRegClassConstraint ( OpIdx ,


<s> double Closure :: calculateCost ( RegDomain DstDomain ) const { assert ( isLegal ( DstDomain )


<s> <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPUDirectives [ Directive ] ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc


<s> report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : { const uint8_t SignAndSizeForHalf16 = EncodedSignednessIndicator | <NUM_LIT> ; switch ( Modifier ) { default : report_fatal_error ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return { XCOFF :: RelocationType :: R_TOC , SignAndSizeForHalf16 } ; case MCSymbolRefExpr :: VK_<ISA_LIT>_U : return { XCOFF :: RelocationType :: R_TOCU , SignAndSizeForHalf16 } ; case MCSymbolRefExpr :: VK_<ISA_LIT>_L : return { XCOFF :: RelocationType :: R_TOCL , SignAndSizeForHalf16 } ; } } break ; case <STR_LIT> : return { XCOFF :: RelocationType :: R_RBR , EncodedSignednessIndicator | <NUM_LIT> } ; case <STR_LIT>


<s> if ( TT . getArch ( ) == Triple :: x86_64 ) return std :: make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return std :: make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSBinFormatCOFF ( ) ) return std :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; return std :: make_unique < <ISA_LIT>ELFTargetObjectFile > (


<s> else if ( ready_nested_str ) nested_type = NDS32_NESTED_READY ; else if ( nested_str ) nested_type = NDS32_NESTED ; else if ( critical_str ) nested_type = NDS32_CRITICAL ; else nested_type = NDS32_NOT_NESTED ; id_str = strstr ( target_str , <STR_LIT> ) ; if ( id_str == NULL ) error ( <STR_LIT> ) ; id_str = strtok ( id_str , <STR_LIT> ) ; value_str = strtok ( NULL , <STR_LIT> ) ; value_str = strtok ( value_str , <STR_LIT> ) ; while ( value_str != NULL ) { int i ; i = atoi ( value_str ) ; if ( i < <NUM_LIT> || i > <NUM_LIT> ) error ( <STR_LIT> ) ; nds32_isr_vectors [ i ] . category


<s> if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst ; if ( IsStrict ) SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , SDValue ( BV , <NUM_LIT> ) } ) ; else SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , Op0 -> getOperand ( <NUM_LIT> ) , MaskConst ) ; SDValue Res = DAG . getBitcast


<s> if ( ( R == <ISA_LIT>InstrInfo :: BT_None ) || ( R == <ISA_LIT>InstrInfo :: BT_NoBranch ) ) return std :: make_pair ( R , ( MachineInstr * ) NULL ) ; if ( R != <ISA_LIT>InstrInfo :: BT_CondUncond ) { if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , ( MachineInstr * ) NULL ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; } assert ( ( TrueBB == & Dst ) || ( FalseBB == & Dst ) ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Cond , BranchInstrs [ <NUM_LIT> ] ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) && ( FalseBB == & Dst ) )

return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Uncond , BranchInstrs [ <NUM_LIT> ] ) ;


<s> if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( ( off1 <= off2 ) && ( off1


<s> Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = <STR_LIT> ( M


<s> ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t )


<s> virtual bool isDeadInstruction ( const MachineInstr * MI ) const { return


<s> unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ; return flags & ( CP_READ_MEMORY


<s> MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII . getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII . getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII . loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } else { unsigned LAOpcode = TII . getOpcodeForOffset ( <STR_LIT> , HighOffset ) ; if ( LAOpcode ) BuildMI ( MBB , MI , DL , TII . get ( LAOpcode ) , ScratchReg ) . addReg ( BasePtr ) . addImm ( HighOffset ) . addReg ( <NUM_LIT> ) ; else { TII . loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( BasePtr ) ; } MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! TheTriple . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; if ( Type == -


<s> SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleHigh128VectorInsertLow ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , V , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleLow128VectorInsertHigh ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG ,


<s> BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps +


<s> OperandMatchResultTy ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const MCExpr * OffsetExpr ; int64_t OffsetVal ; SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) || ! OffsetExpr -> evaluateAsAbsolute ( OffsetVal ) ) { reportParseError ( ExprLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return


<s> void <ISA_LIT>InstPrinter :: printSHFMask ( const MCInst * MI , int opNum , raw_ostream & O ) { llvm_unreachable ( <STR_LIT> )


<s> cast < Function > ( CxxLongjmpUnwind . getCallee ( ) -> stripPointerCasts ( ) ) -> setCallingConv ( CallingConv :: <ISA_LIT>_StdCall ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { StringRef PersonalityName = PersonalityFn -> getName ( ) ; UseStackGuard = ( PersonalityName == <STR_LIT> ) ; RegNodeTy = getSEHRegistrationType ( ) ; RegNode = Builder . CreateAlloca ( RegNodeTy ) ; if ( UseStackGuard ) EHGuardNode = Builder . CreateAlloca ( Int32Ty ) ; Value * SP = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> , { Type :: getInt8PtrTy ( F -> getContext ( ) ) } ) , { } ) ; Builder . CreateStore ( SP , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; StateFieldIndex = <NUM_LIT> ; ParentBaseState = UseStackGuard ? - <NUM_LIT> : - <NUM_LIT> ; insertStateNumberStore ( & * Builder . GetInsertPoint ( ) , ParentBaseState ) ; Value * LSDA = emitEHLSDA ( Builder , F ) ; LSDA = Builder . CreatePtrToInt ( LSDA , Int32Ty ) ; if ( UseStackGuard ) { Cookie = TheModule -> getOrInsertGlobal ( <STR_LIT> , Int32Ty ) ; Value * Val = Builder . CreateLoad ( Int32Ty , Cookie , <STR_LIT> ) ; LSDA = Builder . CreateXor ( LSDA , Val ) ; } Builder . CreateStore ( LSDA , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; if ( UseStackGuard ) { Value * Val = Builder . CreateLoad ( Int32Ty , Cookie ) ; Value * FrameAddr = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> , Builder . getInt8PtrTy ( TheModule -> getDataLayout ( ) . getAllocaAddrSpace ( ) ) ) , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * FrameAddrI32 = Builder . CreatePtrToInt ( FrameAddr , Int32Ty ) ; FrameAddrI32 = Builder . CreateXor ( FrameAddrI32 , Val ) ; Builder . CreateStore ( FrameAddrI32 , EHGuardNode ) ; } Link = Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ; linkExceptionRegistration ( Builder , PersonalityFn ) ; SehLongjmpUnwind = TheModule -> getOrInsertFunction ( UseStackGuard ? <STR_LIT> : <STR_LIT> , FunctionType :: get ( Type :: getVoidTy ( TheModule -> getContext ( ) ) , Int8PtrType , false ) ) ; cast < Function > ( SehLongjmpUnwind . getCallee ( ) -> stripPointerCasts ( ) ) -> setCallingConv ( CallingConv :: <ISA_LIT>_StdCall ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } for ( BasicBlock & BB : * F ) { Instruction * T = BB . getTerminator ( ) ; if ( ! isa < ReturnInst > ( T ) ) continue ; Builder . SetInsertPoint


<s> bool <ISA_LIT>BaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ; return false


<s> const BlockAddress * <ISA_LIT>ConstantPoolValue :: getBlockAddress (


<s> split_const ( op , & sym , & addend ) ; if ( SYMBOL_REF_P ( sym ) ) return SYMBOL_REF_TLS_MODEL ( sym ) ; return TLS_MODEL_NONE


<s> return ( vector signed char ) __builtin_altivec_vpkshss ( ( vector signed short )


<s> if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + <NUM_LIT> ; } if ( insn_type == TYPE_SHIFT ) return cost


<s> <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( LI -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = TD . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand ,


<s> RegisterTarget < Triple :: sparc , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcv9 , true > Y ( The<ISA_LIT>V9Target ,


<s> return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv ::


<s> if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ; Type * Ty = User -> getOperand ( <NUM_LIT> ) -> getType ( ) ; return ! ( isFMAFasterThanFMulAndFAdd ( * F , Ty ) && isOperationLegalOrCustom ( <STR_LIT> , getValueType ( DL , Ty ) ) && (

Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ;


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address


<s> } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; return


<s> inline bool isImmSExti64i8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT>


<s> static bool csky_legitimate_constant_p ( machine_mode mode , rtx


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget


<s> assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) == <NUM_LIT>


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { Register NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zero64 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) ,

NewIn128 ) . addReg ( In128 ) . addReg ( Zero64 ) . addImm ( <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg

++ ) if ( save_reg_p ( first_reg ) ) break ;


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout


<s> bool isCmseNSEntryFunction ( ) const { return IsCmseNSEntry


<s> } if ( Subtarget -> isABI_O32 ( ) ) { if ( RegVT == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; if ( RegVT == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , VA . getLocReg ( ) + <NUM_LIT> , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordLoadArgsFI ( FI , - ( ArgSize + ( FirstStackArgLoc + VA . getLocMemOffset ( ) ) ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Copy , Chain ) ; } if ( ( isVarArg ) && ( Subtarget -> isABI_O32 ( )


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( * MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout (


<s> else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) , OpFlag ) ; DebugLoc DL = JT -> getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Result ) ; } return Result


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( Func -> hasFnAttribute (