<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; bool isKill = true ; if ( Reg == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn


<s> break ; default : gcc_unreachable ( ) ; break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ <NUM_LIT> ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ <NUM_LIT> ] , tmp ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , gen_lowpart ( GET_MODE ( operands [ <NUM_LIT> ] ) , dest ) ) ; return ; } switch ( imode ) { case V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpFunc = gen_loongson_pcmpgtb ; break ; case


<s> int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveR19R20X ( Offset ) ; return false


<s> x = strip_offset_and_salt ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > <NUM_LIT> ) return false ; if ( maybe_ne ( offset , <NUM_LIT> ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x ) ) return false ; if ( SYMBOL_REF_P ( x ) && ! SYMBOL_REF_TLS_MODEL ( x ) ) return true ; if ( LABEL_REF_P ( x ) ) return true ; return false


<s> virtual const <ISA_LIT>BaseInstrInfo * getInstrInfo ( ) const { return InstrInfo . get (


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return true ; if ( ! cum )


<s> bool <ISA_LIT>ATTAsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { RegNo = <NUM_LIT> ; const AsmToken & TokPercent = Parser . getTok ( ) ; assert ( TokPercent . is ( AsmToken :: Percent ) && <STR_LIT> ) ; StartLoc = TokPercent . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , Tok . getEndLoc ( ) ) ) ; RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( LowercaseString ( Tok . getString ( ) ) ) ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) return Error ( StartLoc , <STR_LIT> + Tok . getString ( ) + <STR_LIT> , SMRange ( StartLoc , Tok . getEndLoc ( ) ) ) ; } if ( RegNo == <NUM_LIT> && ( Tok . getString ( ) == <STR_LIT> || Tok . getString


<s> else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( Address ) ) { O << formatHex ( ( uint64_t ) Address ) ; }


<s> if ( Signed && isPow2Splat ( Op . getOperand ( <NUM_LIT> ) , SplatVal , Negated ) ) { SDValue Pg = getPredicateForScalableVector ( DAG , dl , VT ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , Pg , Op -> getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Log2_64 ( SplatVal ) , dl , <STR_LIT> ) ) ; if ( Negated ) Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , Res ) ; return Res ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) return LowerToPredicatedOp ( Op , DAG , PredOpcode ) ; EVT WidenedVT ; if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( )


<s> static bool mayAlias ( MachineInstr * MIa , SmallVectorImpl < MachineInstr * > & MemInsns , const <ISA_LIT>InstrInfo * TII ) { for ( auto & MIb : MemInsns ) if ( mayAlias ( MIa , MIb , TII ) ) return true ; return false


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> getFrameLowering ( ) -> getTOCSaveOffset ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; } } else if ( CalleeMO . isGlobal ( ) ) { const GlobalValue * GValue = CalleeMO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: create ( MOSymbol , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( SymVar ) ) ; EncodedBytes += <NUM_LIT>


<s> return ( __m512i ) __builtin_ia32_prolq512_mask ( ( __v8di ) __A , __B , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 )


<s> if ( ! MO . isReg ( ) ) continue ; unsigned R = MO . getReg ( ) - <STR_LIT> ; if ( R < <NUM_LIT> ) { if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: <ISA_LIT>_RegCall ) { assert ( MO . isDef ( ) && MO . isImplicit ( ) ) ; } STReturns |= <NUM_LIT> << R ; } } unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ; while ( StackTop > <NUM_LIT> ) popReg ( ) ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) pushReg ( N -


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT>


<s> static int rs6000_compute_pressure_classes ( enum reg_class * pressure_classes ) { int n ; n = <NUM_LIT> ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++


<s> if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm * <NUM_LIT> ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT>


<s> static MachineBasicBlock * emitBlockAfter ( MachineBasicBlock * MBB ) { MachineFunction & MF = * MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = MF . CreateMachineBasicBlock ( MBB


<s> assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( VT


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue (


<s> SDValue EltVal = StVal . getOperand ( I ) ; if ( ! isNullConstant ( EltVal ) && ! isNullFPConstant ( EltVal ) ) return SDValue ( ) ; } SDLoc DL ( & St ) ; unsigned ZeroReg ; EVT ZeroVT ; if ( VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { ZeroReg = <STR_LIT> ; ZeroVT = <STR_LIT> ; } else { ZeroReg = <STR_LIT> ; ZeroVT = <STR_LIT> ; } SDValue SplatVal = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , ZeroReg , ZeroVT ) ; return splitStoreSplat ( DAG , St


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; Len &= <NUM_LIT> ; Idx &= <NUM_LIT> ; if ( <NUM_LIT> != ( Len % EltSize ) || <NUM_LIT> != ( Idx % EltSize ) ) return ; if ( Len == <NUM_LIT> ) Len = <NUM_LIT> ; if ( ( Len + Idx ) > <NUM_LIT> ) { ShuffleMask . append ( NumElts , SM_SentinelUndef ) ; return ; } Len /=


<s> Value * <ISA_LIT>IREmitter :: visitSBB ( const


<s> EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RM = DAG . getTarget ( ) . getRelocationModel ( ) ; CodeModel :: Model CM = DAG . getTarget ( ) . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , RM , CM ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor +


<s> if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( recog_op_alt [ opno ] [ which_alternative ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; result = true ; } else if ( GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) ==

SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( op , <NUM_LIT> ) ) ) {


<s> int regno , i , ok_p ; enum machine_mode mode1 , mode2 ; if ( d30v_branch_cost_string ) d30v_branch_cost = atoi ( d30v_branch_cost_string ) ; if ( d30v_cond_exec_string ) d30v_cond_exec = atoi ( d30v_cond_exec_string ) ; for ( mode1 = VOIDmode ; ( int ) mode1 < NUM_MACHINE_MODES ; mode1 = ( enum machine_mode ) ( ( int ) mode1 + <NUM_LIT> ) ) { int size = GET_MODE_SIZE ( mode1 ) ; int large_p = size > UNITS_PER_WORD ; int int_p = GET_MODE_CLASS ( mode1 ) == MODE_INT ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( mode1 == VOIDmode ) ok_p = FALSE ; else if ( GPR_P ( regno ) ) { if ( ! large_p ) ok_p = TRUE ; else ok_p = ( ( ( regno - GPR_FIRST ) & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( FLAG_P ( regno ) ) ok_p = ( mode1 == CCmode ) ; else if ( CR_P ( regno ) ) ok_p = int_p && ! large_p ; else if ( ACCUM_P ( regno ) ) ok_p = ( mode1 == DImode ) ; else if ( SPECIAL_REG_P ( regno ) ) ok_p = ( mode1 == SImode ) ; else ok_p = FALSE ; hard_regno_mode_ok [ ( int ) mode1 ] [ regno ] = ok_p ; } for ( mode2 = VOIDmode ; ( int ) mode2 <= NUM_MACHINE_MODES ; mode2 = ( enum machine_mode ) ( ( int ) mode2 + <NUM_LIT> ) ) { if ( mode1 == mode2 ) ok_p = TRUE ; else if ( GET_MODE_CLASS ( mode1 ) == MODE_INT && GET_MODE_SIZE ( mode1 ) <= UNITS_PER_WORD && GET_MODE_CLASS ( mode2 ) == MODE_INT && GET_MODE_SIZE ( mode2 ) <= UNITS_PER_WORD ) ok_p = TRUE ; else ok_p = FALSE ; modes_tieable_p [ ( ( int ) mode1 * ( NUM_MACHINE_MODES ) ) + (


<s> inline const char * getShiftOpcStr ( ShiftOpc Op ) { switch ( Op ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> else if ( litmsk == <NUM_LIT> ) result = vec_xxpermdi ( __B , __A , <NUM_LIT> ) ; else if ( litmsk == <NUM_LIT> ) result = vec_xxpermdi ( __B , __A , <NUM_LIT> ) ; else if ( litmsk == <NUM_LIT> ) result = vec_xxpermdi


<s> static unsigned int longformBranchOpcode ( unsigned int Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> const ArrayRef < MCPhysReg > IntArgRegs = Subtarget . getABI ( ) . GetByValArgRegs ( ) ; const MCPhysReg * ShadowRegs = Subtarget . isABI_O32 ( ) ? IntArgRegs . data ( ) : <ISA_LIT>64DPRegs ; assert ( ! ( Align % RegSizeInBytes ) && <STR_LIT> <STR_LIT> ) ; FirstReg = State -> getFirstUnallocated ( IntArgRegs . data ( ) , IntArgRegs . size ( ) ) ; if ( ( Align > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg ] ) ; ++ FirstReg ; } Size = RoundUpToAlignment ( Size , RegSizeInBytes ) ; for ( unsigned I = FirstReg ; Size > <NUM_LIT> && (


<s> if ( Subtarget . isDarwinABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( VarArgsNumGPR , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( VarArgsNumFPR , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( VarArgsStackOffset , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset =


<s> if ( ( hasQPX ( ) || isBGQ ( ) ) && ! isQPXStackUnaligned ( )


<s> if ( REGNO ( hard_reg ) == ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ) { if ( current_function_is_leaf && ! sh_pr_n_sets ( ) && ! ( TARGET_SHCOMPACT && ( ( current_function_args_info . call_cookie &

~ CALL_COOKIE_RET_TRAMP ( <NUM_LIT> ) ) || current_function_has_nonlocal_label ) ) ) x = hard_reg ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo


<s> return ( int32x2_t ) __builtin_aarch64_srsra_nv2si ( __a ,


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo


<s> void <ISA_LIT>TargetStreamer :: emitFnStart ( ) { llvm_unreachable ( <STR_LIT>


<s> assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / <NUM_LIT> ; EVT ByteVT = EVT :: getVectorVT ( Ctx , <STR_LIT>

, ElementCount :: getScalable ( ByteSize ) ) ;


<s> return isCommutedSHUFPMask ( M , N -> getValueType ( <NUM_LIT> )


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr >


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return LowerCONCAT_VECTORSvXi1 ( Op , Subtarget , DAG ) ; assert ( ( VT . is256BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> ) || ( VT . is512BitVector ( ) && ( Op . getNumOperands ( ) == <NUM_LIT> || Op . getNumOperands ( ) == <NUM_LIT> ) ) ) ; return LowerAVXCONCAT_VECTORS ( Op ,


<s> struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( current_function_varargs || current_function_stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = <NUM_LIT> ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( current_function_args_size <= <NUM_LIT> && current_function_args_size !=


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTarget26OpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerVSETCC ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isScalableVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return LowerFixedLengthVectorSetccToSVE ( Op , DAG ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT CmpVT = LHS . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } const bool FullFP16 = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> MachineFunction :: iterator EndMBB = MF . end ( ) ; for ( ; MBBI != EndMBB ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB ->


<s> FunctionPass * llvm :: create<ISA_LIT>JITCodeEmitterPass ( <ISA_LIT>TargetMachine &


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( isCyclone ( ) ) Policy . DisableLatencyHeuristic


<s> StringRef FPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = StringSwitch < unsigned > ( FPU ) . Default ( <STR_LIT> ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return


<s> if ( <ISA_LIT>ScalarSSEf64 && I -> getType ( ) -> isDoubleTy ( ) && I -> getOperand ( <NUM_LIT> )


<s> TrueImm = ~ TrueImm ; Opc = <STR_LIT> ; } else if ( TrueVal . getNode ( ) -> hasOneUse ( ) && ( Subtarget -> hasV6T2Ops ( ) || <STR_LIT> ( TrueImm ) ) ) { Opc = <STR_LIT> ; } if ( Opc ) { SDValue True = CurDAG -> getTargetConstant ( TrueImm , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , True , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> ,


<s> bool <ISA_LIT>TargetLowering :: getSafeStackPointerLocation ( unsigned & AddressSpace , unsigned & Offset ) const { if ( ! Subtarget -> isTargetAndroid ( )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> return ( uint8x8_t ) __builtin_neon_vcgtv8qi


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopPreIncPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt ::

None ) addPass ( createHardwareLoopsPass ( ) ) ;


<s> imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Q = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Q ) { if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT>


<s> for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , v4s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v4s32 , v2s64 } ) setAction


<s> auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeGPRRegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Ry + Imm5 ] ) ) ; return MCDisassembler


<s> void MandarinTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDLoc dl ( N ) ; RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> )


<s> if ( ParsingInlineAsm ) if ( IDInfo . isKind ( InlineAsmIdentifierInfo :: IK_EnumVal ) ) return onInteger ( IDInfo . Enum . EnumVal , ErrMsg ) ; if ( auto * CE = dyn_cast < MCConstantExpr > ( SymRef ) ) return onInteger ( CE -> getValue ( ) , ErrMsg ) ; PrevState = State ; bool HasSymbol = Sym != nullptr ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_INIT : case IES_LBRAC : MemExpr = true ; State = IES_INTEGER ; Sym = SymRef ; SymName = SymRefName ; IC . pushOperand ( IC_IMM ) ; if ( ParsingInlineAsm ) Info = IDInfo ; break ; } if ( HasSymbol ) ErrMsg = <STR_LIT> ; return


<s> Value * <ISA_LIT>IREmitter :: visitKORTEST ( const


<s> assert ( IsCheriPureCap ( ) ) ; return MCTargetOptions :: cheriCapabilityTableABI


<s> if ( rs6000_abi_string == <NUM_LIT> ) return ; else if ( ! strcmp ( rs6000_abi_string , <STR_LIT> ) ) rs6000_altivec_abi = <NUM_LIT> ; else if ( ! strcmp ( rs6000_abi_string


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelDyn ( ) const { assert ( m_pRelDyn != NULL ) ; return * m_pRelDyn


<s> if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> const std :: string & <ISA_LIT>To<ISA_LIT>Stub


<s> setISALevelAndRevisionFromPredicates ( P ) ; setGPRSizeFromPredicates ( P ) ; setCPR1SizeFromPredicates ( P ) ; setASESetFromPredicates ( P ) ; setFpAbiFromPredicates ( P


<s> return ( __m256i ) __builtin_ia32_punpcklwd256_mask ( ( __v16hi ) __A , ( __v16hi ) __B , (


<s> return __builtin_mve_vmaxq_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a ,


<s> unsigned NewOpc = <NUM_LIT> ; unsigned Limit = isAM5 ? <NUM_LIT> : ( isAM2 ? <NUM_LIT> : <NUM_LIT> ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( isMatchingDecrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( ! isAM5 && isMatchingIncrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , AddSub ) ; MBB . erase ( PrevMBBI ) ; } } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , AddSub ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; } } if ( ! DoMerge ) return false ; unsigned Offset = <NUM_LIT> ; if ( isAM2 ) Offset = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; else if ( ! isAM5 ) Offset = AddSub == <STR_LIT> ? - Bytes : Bytes ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT>


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT>


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: ZPR : LdrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT>


<s> case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } if ( Subtarget . isPICStyleGOT ( ) || Subtarget . isPICStyleStubPIC ( ) ) return ; GlobalAddressSDNode * GA


<s> const AsmToken & RegTok = Parser . getTok ( ) ; int RegNo = tryParseRegister ( ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , RegTok . getLoc ( ) , RegTok . getEndLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorIndex ( MCE -> getValue (


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , TLI -> getPointerTy ( ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } } Base =


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { assert ( MBB . getParent ( ) && <STR_LIT> ) ; const MachineFunction & MF = * MBB .


<s> unsigned getNumFixupKinds ( ) const override { return


<s> static DecodeStatus decodePC32DBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void *


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( const MachineFunction & MF


<s> if ( LoopCount -> getOpcode ( ) == <STR_LIT> || LoopCount -> getOpcode ( )

== <STR_LIT> ) TripCount = LoopCount -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> MachineBasicBlock * SecondInsertedMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FirstInsertedMBB ) ; F -> insert ( It , SecondInsertedMBB ) ; F -> insert ( It , SinkMBB ) ; FirstInsertedMBB -> addLiveIn ( <STR_LIT> ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! SecondCascadedCMOV . killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( SecondCascadedCMOV , ThisMBB , TRI ) ) { SecondInsertedMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( FirstCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FirstInsertedMBB ) ; ThisMBB -> addSuccessor (


<s> return ! ( ST -> isAtom ( ) || ST -> isSLM


<s> void addExternalFunction ( MCSymbol * Symbol


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rn == <NUM_LIT> || Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> unsigned <ISA_LIT>TTI :: getMaximumUnrollFactor ( ) const { if ( ST -> isCortexA57 ( ) || ST ->


<s> case <STR_LIT> : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( )


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode


<s> if ( ! LoadI ) continue ; Value * PtrValue = LoadI -> getPointerOperand ( ) ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE . getSCEV ( PtrValue ) ; const SCEVAddRecExpr * LSCEVAddRec = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ; if ( ! LSCEVAddRec || ! LSCEVAddRec -> isAffine ( ) ) continue ; LoadI -> setMetadata ( FALKOR_STRIDED_ACCESS_MD , MDNode :: get ( LoadI -> getContext ( ) , { } ) ) ; ++ NumStridedLoadsMarked ; DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ) ; MadeChange = true ; } } return


<s> HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv =


<s> MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . storeRegToStackSlotNoUpd ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return


<s> static int sparc_tls_symbol_ref_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { return SPARC_SYMBOL_REF_TLS_P ( *


<s> if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1


<s> else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; Result . getNode ( ) -> setTrapInfo ( Op -> getTrapInfo ( ) ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT )


<s> switch ( insn -> spec -> modifierType ) { default : unreachable ( <STR_LIT> ) ; case MODIFIER_NONE : unreachable ( <STR_LIT> ) ; case MODIFIER_OPCODE : insn -> opcodeModifier = insn -> opcode - insn -> spec -> modifierBase ; break ; case MODIFIER_MODRM : insn -> opcodeModifier = insn -> modRM


<s> if ( from_size == <NUM_LIT> && ( <NUM_LIT> * to_nregs ) != to_size ) return true ; if ( to_size == <NUM_LIT> && ( <NUM_LIT> * from_nregs ) != from_size ) return true ; return false ; } else return false ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == <NUM_LIT> || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == <NUM_LIT> || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == <NUM_LIT> || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == <NUM_LIT> || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == <NUM_LIT> ) ) return true ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + <NUM_LIT> ) / <NUM_LIT> ; if ( hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] > num_regs || hard_regno_nregs [ FIRST_FPR_REGNO ]


<s> rtx end_addr = gen_reg_rtx ( Pmode ) ; rtx line_length = gen_reg_rtx ( Pmode ) ; rtx r_tramp , tmp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; r_tramp = force_reg ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; if ( ! TARGET_64BIT ) { tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , r_tramp ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( start_addr , r_tramp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , TRAMPOLINE_CODE_SIZE - <NUM_LIT> ) ) ; emit_insn ( gen_andsi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , <NUM_LIT> ) ) ) ; tmp = adjust_address ( m_tramp , Pmode


<s> DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ; concatSubVector ( Vec , InVec , VecElems , Builder ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , UndefValue :: get ( Vec [ <NUM_LIT> ] -> getType ( ) ) , VPShuf ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) TempVector [ i ] = Builder . CreateShuffleVector ( Vec [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , Vec [ i ] , VPAlign [ <NUM_LIT> ] ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( TempVector [ ( i + <NUM_LIT> )

% <NUM_LIT> ] , TempVector [ i ] , VPAlign [ <NUM_LIT> ] ) ;


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { llvm_unreachable ( <STR_LIT> )


<s> return buildEOR ( MBB , DL , MI ) . addReg ( Dst , RegState :: Define ) . addReg ( Dst ) . addReg ( Src ) . addImm


<s> reportParseError ( <STR_LIT> ) ; return false ; } Options . setMacro ( ) ; Parser . Lex (


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> )


<s> if ( Register :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsVFReg = ( MI . getNumOperands ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! ConvertibleImmForm && ! instrHasImmForm ( Opc , IsVFReg , III , true ) ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { Register Reg = MI . getOperand ( i ) . getReg ( ) ; MachineInstr * DefMI = getDefMIPostRA ( Reg , MI , SeenIntermediateUse ) ; if ( DefMI )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> ET = getShiftExtendType ( ) ; bool IsSigned = ET == <STR_LIT> || ET ==


<s> <STR_LIT> SVT = VT . getSimpleVT ( ) . SimpleTy ; switch ( SVT ) { case <STR_LIT> : case


<s> emitInst ( Opc , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } else if ( isUInt < <NUM_LIT> > ( Imm ) ) { emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


enum machine_mode mode ATTRIBUTE_UNUSED ) {


<s> MachineFunction * MF = MBB -> getParent ( ) ; ++ MBB ; return MBB != MF -> end ( ) && ! MBB -> empty ( ) && & * MBB ->


<s> if ( Idx == - <NUM_LIT> ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONShuffleTbl [ Idx ] . Cost ; } if ( Kind == TTI :: SK_Alternate ) { static const CostTblEntry < <STR_LIT> > NEONAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost (


<s> <STR_LIT> CC = getCompareCC ( Predicate ) ; <STR_LIT> ExtraCC = <STR_LIT> ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_UEQ : ExtraCC = <STR_LIT> ; CC = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : ExtraCC = <STR_LIT> ; CC = <STR_LIT> ; break ; } assert ( ( CC != <STR_LIT> ) && <STR_LIT> ) ; if ( ExtraCC != <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( ExtraCC ) . addMBB ( TBB ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const auto * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( Target ) ; if ( FuncInfo . BPI ) { auto BranchProbability = FuncInfo . BPI -> getEdgeProbability ( BI -> getParent ( ) , Target -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( Target , BranchProbability ) ; } else FuncInfo . MBB -> addSuccessorWithoutProb ( Target ) ; return true ; } else { <STR_LIT> CC = <STR_LIT> ; if ( foldXALUIntrinsic ( CC , I , BI -> getCondition ( ) ) ) { unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( ! CondReg ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } unsigned CondReg = getRegForValue ( BI


<s> inline const char * getShiftOpcStr ( ShiftOpc Op ) { switch ( Op ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( IsUnscaled ) Offset /= OffsetStride ; return Offset <= <NUM_LIT> && Offset


<s> if ( ! N -> isExpandingLoad ( ) && VT . getVectorNumElements ( ) <= <NUM_LIT> ) return Op ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; SDValue Src0 = N -> getSrc0 ( ) ; Src0 = ExtendToType ( Src0 , WideDataVT , DAG ) ; MVT MaskEltTy = Mask . getSimpleValueType ( ) . getScalarType ( ) ; assert ( ( MaskEltTy == <STR_LIT> || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( MaskEltTy ,


<s>
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
if
(
RegInfo
->
hasBasePointer
(
MF
)
)
SavedRegs
.
set
(
RegInfo
->
getBaseRegister
(
)
)
;
if
(
RegInfo
->
needsStackRealignment
(
MF
)
&&
!
RegInfo
->
hasBasePointer
(
MF
)
)
SavedRegs
.
set
(
<STR_LIT>
)
;
unsigned
NumGPRSpilled
=
<NUM_LIT>
;
unsigned
NumFPRSpilled
=
<NUM_LIT>
;
bool
ExtraCSSpill
=
false
;
bool
CanEliminateFrame
=
true
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
i
+=
<NUM_LIT>
)
{
assert
(
CSRegs
[
i
+
<NUM_LIT>
]
&&
<STR_LIT>
)
;
const
unsigned
OddReg
=
CSRegs
[
i
]
;
const
unsigned
EvenReg
=
CSRegs
[
i
+
<NUM_LIT>
]
;
assert
(
(
<STR_LIT>
.
contains
(
OddReg
)
&&
<STR_LIT>
.
contains
(
EvenReg
)
)
^
(
<STR_LIT>
.
contains
(
OddReg
)
&&
<STR_LIT>
.
contains
(
EvenReg
)
)
&&
<STR_LIT>
)
;
const
bool
OddRegUsed
=
SavedRegs
.
test
(
OddReg
)
;
const
bool
EvenRegUsed
=
SavedRegs
.
test
(
EvenReg
)
;
if
(
!
OddRegUsed
&&
!
EvenRegUsed
)
{
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
UnspilledCSGPRs
.
push_back
(
OddReg
)
;
UnspilledCSGPRs
.
push_back
(
EvenReg
)
;
}
else
{
UnspilledCSFPRs
.
push_back
(
OddReg
)
;
UnspilledCSFPRs
.
push_back
(
EvenReg
)
;
}
continue
;
}
unsigned
Reg
=
<STR_LIT>
;
if
(
OddRegUsed
^
EvenRegUsed
)
{
Reg
=
OddRegUsed
EvenReg
:
OddReg
;
SavedRegs
.
set
(
Reg
)
;
}
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
OddReg
,
RegInfo
)
)
;
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
EvenReg
,
RegInfo
)
)
;
assert
(
(
(
OddReg
==
<STR_LIT>
&&
EvenReg
==
<STR_LIT>
)
||
(
RegInfo
->
getEncodingValue
(
OddReg
)
+
<NUM_LIT>
==
RegInfo
->
getEncodingValue
(
EvenReg
)
)
)
&&
<STR_LIT>
)
;
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
NumGPRSpilled
+=
<NUM_LIT>
;
if
(
Reg
!=
<STR_LIT>
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
ExtraCSSpill
=
true
;
}
else
NumFPRSpilled
+=
<NUM_LIT>
;
CanEliminateFrame
=
false
;
}
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
CFSize
=
MFI
->
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
(
NumGPRSpilled
+
NumFPRSpilled
)
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize


<s> inline bool CC_<ISA_LIT>_AnyReg_Error ( unsigned & , MVT & , MVT & , CCValAssign :: LocInfo & , <STR_LIT> & , CCState & ) { llvm_unreachable ( <STR_LIT> \ <STR_LIT> ) ; return false


<s> Warning ( Loc , <STR_LIT> <STR_LIT> ) ; Note ( SMLoc ( ) , <STR_LIT> <STR_LIT>


<s> static DecodeStatus DecodeGPRMM16RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> bool EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MachineInstr & MI = * I ; for ( auto & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) - <STR_LIT> ; if ( Reg >= <NUM_LIT> ) continue ; if ( MO . isDef ( ) ) { Defs . set ( Reg ) ; if ( ! LPR . contains ( MO . getReg ( ) ) ) MO . setIsDead ( ) ; } else Uses . push_back ( & MO ) ; } for ( auto * MO : Uses ) if ( Defs . test ( getFPReg ( * MO ) ) || ! LPR . contains ( MO -> getReg ( ) ) ) MO -> setIsKill ( ) ; LPR . stepBackward ( MI


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> static bool indirectable_constant_address_p ( rtx x , bool indirect ATTRIBUTE_UNUSED ) { return CONSTANT_ADDRESS_P ( x )


<s> unsigned BranchOffset = Offset & <NUM_LIT> ; BranchOffset = SignExtend32 < <NUM_LIT> > ( BranchOffset << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset


<s> CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { llvm_report_error ( <STR_LIT> ) ; } if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; } SDValue Val ; if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } Val = DAG . getNode ( <STR_LIT> , dl , CopyVT , Val ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) { Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } InVals . push_back ( Val )


<s> assert ( Kind == k_Barrier && <STR_LIT> ) ; return StringRef ( Barrier . Data , Barrier .


<s> unsigned NumElem = VTy -> getVectorNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ; int SplitCost = getScalarizationOverhead ( Src , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost (


<s> static bool nds32_expand_movmemsi_loop_unknown_size ( rtx dstmem , rtx srcmem , rtx size , rtx alignment ) { rtx dst_base_reg , src_base_reg ; rtx dst_itr , src_itr ; rtx dstmem_m , srcmem_m , dst_itr_m , src_itr_m ; rtx dst_end ; rtx size_least_3_bit ; rtx double_word_end ; rtx double_word_mode_loop , byte_mode_entry , byte_mode_loop , end_label ; rtx tmp ; rtx mask_least_3_bit ; int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & <NUM_LIT> ) == <NUM_LIT> ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return <NUM_LIT> ; if ( TARGET_REDUCED_REGS ) start_regno = <NUM_LIT> ; else start_regno = <NUM_LIT> ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; mask_least_3_bit = GEN_INT ( ~ <NUM_LIT> ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_entry = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; end_label = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , <NUM_LIT> ) ) ; size_least_3_bit = expand_binop ( SImode , and_optab , size , mask_least_3_bit , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_cmp_and_jump_insns ( size_least_3_bit , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , byte_mode_entry ) ; double_word_end = expand_binop ( Pmode , add_optab , dst_base_reg , size_least_3_bit , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_label ( double_word_mode_loop )


<s> if ( ! TEST_HARD_REG_BIT ( live_regs_mask , PR_REG ) ) { rtx rr = gen_rtx_REG ( SImode , PR_REG ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_use ( rr ) ; return ; } int pr_offset = rounded_frame_size ( d ) ; emit_insn ( GEN_MOV ( tmp , GEN_INT ( pr_offset ) ) ) ; if ( frame_pointer_needed ) emit_insn ( GEN_ADD3 ( tmp , tmp , hard_frame_pointer_rtx )


<s> static SDValue detectSSatPattern ( SDValue In , EVT VT , bool MatchPackUS = false ) { unsigned NumDstBits = VT . getScalarSizeInBits ( ) ; unsigned NumSrcBits = In . getScalarValueSizeInBits ( ) ; assert ( NumSrcBits > NumDstBits && <STR_LIT> ) ; auto MatchMinMax = [ ] ( SDValue V , unsigned Opcode , const APInt & Limit ) -> SDValue { APInt C ; if ( V . getOpcode ( ) == Opcode && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) . getNode ( )

, C ) && C == Limit ) return V . getOperand ( <NUM_LIT> ) ;


<s> } else { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP )


<s> inline vector signed char vec_sld ( vector signed char a1 , vector signed char a2 , const char a3 ) { return ( vector signed char ) __builtin_altivec_vsldoi_4si ( ( vector signed int

) a1 , ( vector signed int ) a2 , a3 ) ;


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) { unsigned Reg1 =


<s> if ( Register :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ; return MIB . addReg ( Reg


<s> setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn =


<s> void EmitThumbFunc ( MCSymbol * Func ) { getAssembler ( ) . setIsThumbFunc ( Func ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Func ) ; SD . setFlags ( SD . getFlags


<s> static MCStreamer * createMCStreamer ( const Triple & TT , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr <

MCCodeEmitter > && Emitter , bool RelaxAll ) {


<s> MVT SrcVT = RetVT ; bool IsZExt = ( I -> getOpcode ( ) == Instruction :: AShr ) ? false : true ; const Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = true ; Op0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = false ; Op0 = SExt -> getOperand ( <NUM_LIT> ) ; } } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( Op0 ) ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: AShr : ResultReg = emitASR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: LShr : ResultReg = emitLSR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; } if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAME_TO_ARGS_OFFSET ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo -> getSlotSize (


<s> int arm_reg0 = REGNO ( operands [ <NUM_LIT> ] ) ; rtx ops [ <NUM_LIT> ] ; gcc_assert ( arm_reg0 != IP_REGNUM ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , arm_reg0 ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , ops ) ; return


<s> return ( __m256i ) __builtin_ia32_pmovsqd512_mask ( ( __v8di ) __A , ( __v8si )


<s> rtx_insn * def_insn ; df_ref use , def ; struct df_link * defs ; newx = NULL_RTX ; if ( UNARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; if ( op0 != XEXP ( x , <NUM_LIT> ) ) newx = simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ; } else if ( BINARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; op1 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; if ( op0 != XEXP ( x , <NUM_LIT> ) || op1 != XEXP ( x , <NUM_LIT> ) ) newx = simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , op1 ) ; } else if ( GET_CODE ( x ) == LO_SUM ) { op0 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; if ( GET_CODE ( op0 ) == HIGH ) newx = XEXP ( x , <NUM_LIT> ) ; } else if ( REG_P ( x ) ) { use = df_find_use ( insn , regno_reg_rtx [ REGNO ( x ) ] ) ; gcc_assert ( use ) ; defs = DF_REF_CHAIN ( use ) ; if ( defs && defs -> next == NULL ) { def = defs -> ref ; if ( DF_REF_IS_ARTIFICIAL ( def ) ) { if ( x == stack_pointer_rtx && DF_REF_BB ( def ) == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) newx = virtual_incoming_args_rtx ; } else if ( dominated_by_p ( CDI_DOMINATORS , DF_REF_BB ( use ) , DF_REF_BB ( def ) ) ) { def_insn = DF_REF_INSN ( def ) ; if ( NONJUMP_INSN_P ( def_insn ) ) { set = single_set ( def_insn ) ; if ( set && rtx_equal_p ( SET_DEST ( set ) , x ) ) { note = find_reg_equal_equiv_note ( def_insn ) ; if ( note ) newx = XEXP ( note , <NUM_LIT> ) ; else newx = SET_SRC ( set ) ; newx = r10k_simplify_address ( newx


<s> const_rtx x = * iter ; if ( REG_P ( x ) && REGNO ( x ) != LO_REGNO && REGNO ( x

) != HI_REGNO && reg_set_p ( x , prev ) ) return false ;


<s> if ( ! And -> hasOneUse ( ) ) return ; SDValue Zero = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Zero ) || ! cast < ConstantSDNode > ( Zero ) -> isNullValue ( ) || And -> getOpcode ( ) != <STR_LIT> ) return ; SDValue X = And . getOperand ( <NUM_LIT> ) ; auto C = dyn_cast < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return ; auto Range = getContiguousRangeOfSetBits ( C -> getAPIntValue ( ) ) ; if ( ! Range ) return ; SDNode * NewN ; SDLoc dl ( N ) ; auto EmitShift = [ & ] ( unsigned Opc , SDValue Src , unsigned Imm ) -> SDNode * { if ( Subtarget -> isThumb2 ( ) ) { Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; }


<s> if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> +


<s> bool FixupLEAPass :: processBasicBlock ( MachineFunction & MF , MachineFunction :: iterator MFI ) { for ( MachineBasicBlock :: iterator I = MFI -> begin ( ) ; I !=

MFI -> end ( ) ; ++ I ) processInstruction ( I , MFI ) ;


<s> while ( value ) { count ++ ; value &= value


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI


<s> default : return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Sign *= - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || !

MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ;


<s> if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ; switch ( N -> getOpcode


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addReg ( <NUM_LIT> )

. addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> * low_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode ) ; * high_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_highpart_offset ( DImode ,


<s> MachineBasicBlock * BrBB = FuncInfo . MBB ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( isValueAvailable ( CI ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } Register CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg , <ISA_LIT>Pred ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( Subtarget -> hasSPE ( ) ? <STR_LIT> : <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return true


<s> if ( MBBI != MBB . instr_end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; OpCode = <STR_LIT> ; MIFlags = MachineInstr :: FrameSetup ; auto NextMBBI = std :: next ( MBBI ) ; MBBI -> eraseFromParent ( ) ; MBBI = NextMBBI ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( OpCode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII . get ( OpCode )


<s> void <ISA_LIT>CondBrFolding :: fixupModifiedCond ( MachineBasicBlock * MBB ) { TargetMBBInfo * MBBInfo = getMBBInfo ( MBB ) ; if ( ! MBBInfo -> Modified ) return ; MachineInstr * BrMI = MBBInfo -> BrInstr ; <STR_LIT> CC = MBBInfo -> BranchCode ; MachineInstrBuilder MIB = BuildMI ( * MBB , BrMI , MBB -> findDebugLoc ( BrMI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MBBInfo -> TBB ) . addImm ( CC ) ; BrMI -> eraseFromParent ( ) ; MBBInfo -> BrInstr = MIB . getInstr (


<s> float temp = __A [ <NUM_LIT> ] ; return


<s> unsigned insertAfter = SIndex ; MachineBasicBlock :: iterator Loc = MemOps [ SIndex ] . MBBI ; DebugLoc dl = Loc -> getDebugLoc ( ) ; const MachineOperand & PMO = Loc -> getOperand ( <NUM_LIT> ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : get<ISA_LIT>RegisterNumbering ( PReg ) ; unsigned Count = <NUM_LIT> ; for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> static void CreateLoadIns ( IRBuilder < NoFolder > & IRB , Instruction * Acc , LoadInst * * VecLd ) { const Type * AccTy = Acc ->


<s> static int xstormy16_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return ( CONST_INT_P ( x ) ? <NUM_LIT> : GET_CODE (


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : { assert ( VT . getScalarType ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; Known . Zero . setBitsFrom ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) break ; KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } if ( isTargetShuffle ( Opc ) ) { bool IsUnary ; SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( getTargetShuffleMask ( Op . getNode ( ) , VT . getSimpleVT ( ) , true , Ops , Mask , IsUnary ) ) { unsigned NumOps = Ops . size ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Mask . size ( ) == NumElts ) { SmallVector < APInt , <NUM_LIT> > DemandedOps ( NumOps , APInt ( NumElts , <NUM_LIT> ) ) ; Known . Zero . setAllBits ( ) ; Known . One . setAllBits ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( ! DemandedElts [ i ] ) continue ; int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { Known . resetAll ( ) ; break ; } else if ( M == SM_SentinelZero ) { Known . One . clearAllBits ( ) ; continue ; } assert ( <NUM_LIT> <= M && ( unsigned ) M < ( NumOps * NumElts ) && <STR_LIT> ) ; unsigned OpIdx = ( unsigned ) M / NumElts ; unsigned EltIdx = ( unsigned ) M % NumElts ; if ( Ops [ OpIdx ] . getValueType ( ) != VT ) { Known . resetAll ( ) ; break ; } DemandedOps [ OpIdx ] . setBit ( EltIdx ) ; } for ( unsigned i = <NUM_LIT> ; i != NumOps && ! Known . isUnknown ( ) ; ++ i ) { if ( ! DemandedOps [ i ] ) continue ; KnownBits Known2 = DAG . computeKnownBits ( Ops [ i ] , DemandedOps [ i ] , Depth +


<s> return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( &


<s> return ( _U_Qfcmp ( a , b , <NUM_LIT> ) !=


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler ::


<s> return parseAddress ( Operands , <STR_LIT>


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return Reserved


<s> static DecodeStatus DecodeVFRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo


<s> rtx src = operands [ <NUM_LIT> ] ; rtx base ; machine_mode cur_mode = BLKmode , next_mode ; bool speed_p = ! optimize_function_for_size_p ( cfun ) ; int max_num_moves = ( speed_p ? <NUM_LIT> : AARCH64_CALL_RATIO ) / <NUM_LIT> ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; n = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( ( n / <NUM_LIT> ) + ( n % <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) > max_num_moves ) return false ; base = copy_to_mode_reg ( Pmode , XEXP ( dst , <NUM_LIT> ) ) ; dst = adjust_automodify_address ( dst , VOIDmode , base , <NUM_LIT> ) ; base = copy_to_mode_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; src = adjust_automodify_address ( src , VOIDmode , base , <NUM_LIT> ) ; n = n * BITS_PER_UNIT ; const int copy_limit = GET_MODE_BITSIZE ( TImode ) ; while ( n > <NUM_LIT> ) { opt_scalar_int_mode mode_iter ; FOR_EACH_MODE_IN_CLASS ( mode_iter , MODE_INT ) if ( GET_MODE_BITSIZE ( mode_iter . require ( ) ) <= MIN ( n , copy_limit

) ) cur_mode = mode_iter . require ( ) ;


<s> bool isMM16AsmRegMoveP ( ) const { if ( ! ( isRegIdx ( ) && RegIdx . Kind


<s> else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onRShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onXor ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onAnd


<s> if ( Call -> onlyReadsMemory ( ) ) return false ; BasicBlock * JoinBB = llvm :: SplitBlock ( & CurrBB , Call -> getNextNode ( ) , this ) ; IRBuilder < > Builder ( JoinBB , JoinBB -> begin ( ) ) ; PHINode * Phi = Builder . CreatePHI ( Call -> getType ( ) , <NUM_LIT> ) ; Call -> replaceAllUsesWith ( Phi ) ; BasicBlock * LibCallBB = BasicBlock :: Create ( CurrBB . getContext ( ) , <STR_LIT> , CurrBB . getParent ( ) , JoinBB ) ; Builder . SetInsertPoint ( LibCallBB ) ; Instruction * LibCall = Call -> clone ( ) ; Builder . Insert ( LibCall ) ; Builder . CreateBr ( JoinBB ) ; Call -> addAttribute ( AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; CurrBB . getTerminator ( ) -> eraseFromParent ( ) ; Builder . SetInsertPoint ( & CurrBB ) ; Value * FCmp = Builder . CreateFCmpOEQ ( Call , Call ) ; Builder . CreateCondBr ( FCmp , JoinBB , LibCallBB ) ; Phi -> addIncoming ( Call , & CurrBB ) ; Phi -> addIncoming ( LibCall , LibCallBB


<s> bool <ISA_LIT>GOT :: reserveTLSLdmEntry ( ) { if ( m_HasTLSLdmSymbol ) return false ; m_HasTLSLdmSymbol = true ; m_MultipartList . back ( ) . m_TLSNum += <NUM_LIT> ; m_MultipartList . back ( ) . m_TLSDynNum += <NUM_LIT> ; return true


<s> return ( ( __m128 ) ( __vector unsigned long long ) { ( ( __vector unsigned long long ) __vf1 ) [ <NUM_LIT> ] ,

( ( __vector unsigned long long ) __A ) [ <NUM_LIT> ] } ) ;


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = macho :: RIT_Vanilla ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) macho :: RIT_Difference : ( unsigned ) macho :: RIT_Generic_LocalDifference ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == macho :: RIT_Difference || Type == macho :: RIT_Generic_LocalDifference ) { macho ::


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> if ( NeedTrunc ) { Op0Reg = emitAND_ri ( <STR_LIT> , Op0Reg , Op0IsKill , Mask ) ; Op1Reg = emitAND_ri ( <STR_LIT> , Op1Reg , Op1IsKill , Mask ) ; Op0IsKill = Op1IsKill = true ; } unsigned ResultReg = FastEmitInst_rr ( Opc , RC , Op0Reg , Op0IsKill , Op1Reg , Op1IsKill ) ; if ( NeedTrunc ) ResultReg = emitAND_ri ( <STR_LIT> , ResultReg , true , Mask ) ; return


<s> ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MemSDNode * LoadNode = cast < MemSDNode > ( N ) ; if ( ( ! LoadNode -> isVolatile ( ) && ! LoadNode -> isAtomic ( ) ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : ReplaceExtractSubVectorResults ( N , Results , DAG ) ; return ; case <STR_LIT> : case <STR_LIT> : return ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , V ) ) ; return ; } case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , V ) ) ; return ; } case <STR_LIT>


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { return VRegs . empty ( )


<s> static bool arm_cxx_key_method_may_be_inline (


<s> static rtx function_arg_union_value ( int size , machine_mode mode , int slotno , int regno ) { int nwords = CEIL_NWORDS ( size ) , i ; rtx regs ; if ( nwords == <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> ) nwords = <NUM_LIT> ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = <NUM_LIT> ; i < nwords ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode ,

regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ;


<s> std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return


<s> static DecodeStatus DecodeXSeqPairsClassRegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Addr , const MCDisassembler * Decoder ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , TargetTriple ( TT ) , Is<ISA_LIT>64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TM ( TM ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( )


<s> if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; } return MO . getImm ( ) >>


<s> const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , RA ) . addReg ( TargetReg


<s> Keyword = StringSwitch < StringRef > ( Keyword . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Keyword ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Keyword , Tok . getLoc ( ) , getContext


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv8hi (


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter (


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; Register Reg = MO . getReg ( ) ; assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT>


<s> if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSSE3 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE41 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = SSE42 ; ToggleFeature ( <STR_LIT> ) ; } bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasCLMUL = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasFMA3 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasMOVBE = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasPOPCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasAES = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT>


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT


<s> close ( fd ) ; if ( n > <NUM_LIT> ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) if ( av -> a_type == AT_PLATFORM ) { cpu = ( const char * ) av -> a_un . a_val ; break ; } } if ( cpu != NULL ) { size_t i , j ; char * s ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_supported_cpu_names ) ; i ++ ) if ( ! strcmp ( cpu , rs6000_supported_cpu_names


<s> lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > (


<s> SDValue Extend = BV -> getOperand ( <NUM_LIT> ) ; unsigned ExtendOpcode = Extend . getOpcode ( ) ; bool IsSExt = ExtendOpcode == <STR_LIT> || ExtendOpcode == <STR_LIT> || ExtendOpcode == <STR_LIT> ; if ( ! IsSExt && ExtendOpcode != <STR_LIT> && ExtendOpcode != <STR_LIT> && ExtendOpcode != <STR_LIT> ) return SDValue ( ) ; EVT PreExtendType = calculatePreExtendType ( Extend ) ; if ( PreExtendType == <STR_LIT> || PreExtendType . getSizeInBits ( ) != VT . getScalarSizeInBits ( ) / <NUM_LIT> ) return SDValue ( ) ; for ( SDValue Op : drop_begin ( BV -> ops ( ) ) ) { unsigned Opc = Op . getOpcode ( ) ; bool OpcIsSExt = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( OpcIsSExt != IsSExt || calculatePreExtendType ( Op ) != PreExtendType ) return SDValue ( ) ; } EVT PreExtendVT = VT . changeVectorElementType ( PreExtendType ) ; EVT PreExtendLegalType = PreExtendType . getScalarSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : PreExtendType ; SDLoc DL ( BV ) ; SmallVector < SDValue , <NUM_LIT>


<s> static DecodeStatus DecodeSORegMemOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; <STR_LIT> ShOp = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT>


<s> MCSymbolELF * Sym = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; const MCExpr * Expr ; if ( parseToken ( AsmToken :: Comma ) || check ( getParser ( ) . parseExpression ( Expr ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer * TStreamer = static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer


<s> break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( requiresRegisterScavenging ( MF ) ) { const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; SReg = findScratchRegister ( II , RS , is64Bit ? G8RC : GPRC , SPAdj ) ; } else SReg = is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII .


<s> if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return GET_MODE_CLASS (


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> Instruction * SVEExpandLibCall :: CreateCall ( <STR_LIT> Id , Type * RetTy , ArrayRef < Value * > Ops ) { auto Callee = <STR_LIT> ( F -> getParent ( ) , Id , Ops [ <NUM_LIT>


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode . size ( ) == <NUM_LIT> ) { switch ( ConstraintCode [ <NUM_LIT> ] ) { default : break ; case 'Q'


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT>


<s> MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) &&


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> get<ISA_LIT>RegisterNumbering ( MO . getReg (


<s> SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarry_u64 ( unsigned char __CF , unsigned long long __X , unsigned long long __Y , unsigned long long * __P ) { return __builtin_ia32_addcarryx_u64 ( __CF , __X , __Y ,


<s> return TFI -> hasFP ( MF ) ? ( <STR_LIT> ) : ( <STR_LIT> )


<s> bool matchFoldMergeToZext ( MachineInstr & MI , MachineRegisterInfo & MRI ) { auto & Merge = cast < GMerge > ( MI ) ; LLT SrcTy = MRI . getType ( Merge . getSourceReg ( <NUM_LIT> ) ) ; if ( SrcTy != LLT :: scalar ( <NUM_LIT> ) || Merge . getNumSources ( ) != <NUM_LIT> ) return false ; return mi_match ( Merge . getSourceReg ( <NUM_LIT> ) , MRI , m_SpecificICst ( <NUM_LIT> )


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( bool


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { rtx ( * gen ) ( rtx , rtx ) ; gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; switch ( src_mode ) { case V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case V2DImode


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case