<s> if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = GetAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastOpc == UncondBrOpc ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond


<s> if ( SDValue V = PerformVQDMULHCombine ( N , DCI . DAG ) ) return V ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue XOR = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Const = isConstOrConstSplat ( XOR -> getOperand ( <NUM_LIT> ) , false , true ) ; if ( ! Const || ! Const -> isOne ( ) ) return SDValue ( ) ; SDValue Cond = XOR -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT>


<s> if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { assert ( Directive < sizeof ( CPUDirectives ) / sizeof ( * CPUDirectives ) && <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; } const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel (


<s> if ( isUInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; } return <STR_LIT>


<s> Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) . addReg ( SrcPhiReg ) . addImm ( <NUM_LIT> )

. addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> MVT InVT = <STR_LIT> ( <STR_LIT> ( InBytes * <NUM_LIT> ) , <STR_LIT> / InBytes ) ; Op0 = DAG . getNode ( <STR_LIT> , DL , InVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , DL , InVT , Op1 ) ; SDValue Op ; if ( P . Opcode == <STR_LIT> ) { SDValue Op2 = DAG . getConstant ( P . Operand , DL , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , InVT , Op0 , Op1 , Op2 ) ; } else if ( P . Opcode == <STR_LIT> ) { MVT OutVT = <STR_LIT> ( <STR_LIT> ( P . Operand * <NUM_LIT> ) , <STR_LIT> / P . Operand ) ; Op = DAG . getNode ( <STR_LIT> , DL , OutVT , Op0 , Op1 ) ; } else { Op = DAG . getNode ( P . Opcode , DL , InVT , Op0


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; } return DAG . getStore ( Chain , dl , Arg , PtrOff , PseudoSourceValue :: getStack


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> static int64_t ApplyDisplacementBounds ( int64_t Displacement


<s> ++ MFI ) { MachineBasicBlock * MBB = MFI ; unsigned BlockSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset


<s> if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex )

. addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> OptForSize = F -> hasFnAttr ( Attribute :: OptimizeForSize ) ; DEBUG ( BB -> dump ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) PreprocessForRMW ( ) ; PreprocessForFPConvert ( ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; Indent = <NUM_LIT> ; SelectRoot ( * CurDAG ) ; DEBUG ( errs (


<s> HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { if ( ! MinimizeSize ) return false ; if ( ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlignment ( ) < <NUM_LIT> ) return false ; bool IsStore = Entry . WideOpc == <STR_LIT> ; Register Rt = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; Register Rn = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Register PredReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( Rt ) ) ; assert ( is<ISA_LIT>LowRegister ( Rn ) ) ; if ( Offset != <NUM_LIT> ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; auto MIB = BuildMI ( MBB , MI , dl , TII -> get ( Entry . NarrowOpc1 ) ) . addReg ( Rn , RegState :: Define ) . addReg ( Rn ) . addImm ( PredImm ) . addReg ( PredReg ) . addReg ( Rt , IsStore ? <NUM_LIT> : RegState :: Define ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; MI -> eraseFromBundle ( ) ; ++ NumLdSts ; return true ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; break ; case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT>


<s> static SDValue performLastTrueTestVectorCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( ! Subtarget -> hasSVE ( ) || DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; EVT OpVT = SetCC . getValueType ( ) ; if ( ! OpVT . isScalableVector ( ) || OpVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = N -> getOperand (


<s> static __inline void si_heqi ( qword a , unsigned int b ) { union { vector unsigned int v ; unsigned int i [ <NUM_LIT>


<s> if ( optimize_size || optimize < <NUM_LIT> ) return false ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return nds32_expand_setmem_loop_v3m ( dstmem , size , value ) ; if ( nds32_expand_setmem_unroll ( dstmem , size , value ,

align , expected_align , expected_size ) ) return true ;


<s> static bool BBHasFallthrough ( MachineBasicBlock * MBB ) { MachineFunction :: iterator MBBI ( MBB ) ; auto NextBB = std :: next ( MBBI ) ; if ( NextBB == MBB -> getParent ( )


<s> void <ISA_LIT>TargetStreamer :: emitArch ( unsigned Arch


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF


<s> if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo


<s> FuncInfo -> setVarArgsFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; } assert ( ! ( Subtarget . useSoftFloat ( ) && TheFunction . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && <STR_LIT> ) ; if ( is64Bit ( ) ) { ArrayRef < MCPhysReg > ArgGPRs = get64BitArgumentGPRs ( CallConv , Subtarget ) ; ArrayRef < MCPhysReg > ArgXMMs = get64BitArgumentXMMs ( TheMachineFunction , CallConv , Subtarget ) ; unsigned NumIntRegs = CCInfo . getFirstUnallocated ( ArgGPRs ) ; unsigned NumXMMRegs = CCInfo . getFirstUnallocated ( ArgXMMs ) ; assert ( ! ( NumXMMRegs && ! Subtarget . hasSSE1 ( ) ) && <STR_LIT> ) ; if ( isWin64 ( ) ) { int HomeOffset = FrameLowering . getOffsetOfLocalArea ( ) + <NUM_LIT> ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , NumIntRegs * <NUM_LIT> + HomeOffset , false ) ) ; if ( NumIntRegs < <NUM_LIT> ) FuncInfo -> setVarArgsFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) ) ; } else { FuncInfo -> setVarArgsGPOffset ( NumIntRegs * <NUM_LIT> ) ; FuncInfo -> setVarArgsFPOffset ( ArgGPRs . size ( ) * <NUM_LIT> + NumXMMRegs * <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateStackObject ( ArgGPRs . size ( ) * <NUM_LIT> + ArgXMMs . size ( ) * <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { Register XMMReg = TheMachineFunction . addLiveIn ( Reg


<s> if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V1 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue Unpack = lowerShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Unpack ; if ( ! IsBlendSupported && Subtarget . hasSSSE3 ( ) ) { bool V1InUse ,


<s> aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , - delta


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI


<s> if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass


<s> static inline unsigned decodeRotate ( uint32_t insn ) { unsigned rotate = slice ( insn , <NUM_LIT> ,


<s> decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Chain


<s> break ; case <STR_LIT> : return instCombineConvertFromSVBool ( IC , II ) ; case <STR_LIT> : return instCombineSVEDup ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC ,


<s> if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && countPopulation ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Align , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL


<s> emit_cmp_and_jump_insns ( align_rtx , const2_rtx , GTU , NULL , Pmode , <NUM_LIT> , align_3_label ) ; } else { align_rtx = expand_binop ( Pmode , and_optab , scratch1 , const2_rtx , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; } mem = change_address ( src , QImode , out ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; if ( align != <NUM_LIT> ) { emit_label ( align_2_label ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; emit_label ( align_3_label ) ; } emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; } emit_label ( align_4_label ) ; mem = change_address ( src , SImode , out ) ; emit_move_insn ( scratch , mem ) ; emit_insn ( ix86_gen_add3 ( out , out , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addsi3 ( tmpreg , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_one_cmplsi2 ( scratch , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> , SImode , <NUM_LIT> , align_4_label ) ; if ( TARGET_CMOVE ) { rtx reg = gen_reg_rtx


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMatrixRegister ( unsigned RegNum , unsigned ElementWidth , MatrixKind Kind , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MatrixRegister , Ctx ) ; Op -> MatrixReg . RegNum = RegNum ; Op -> MatrixReg . ElementWidth = ElementWidth ; Op -> MatrixReg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc =


<s> void addDPRRegListOperands ( MCInst & Inst , unsigned N ) const { addRegListOperands ( Inst ,


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return <NUM_LIT> ; case vec_perm : if ( TARGET_VSX ) return <NUM_LIT> ; else return <NUM_LIT> ; case vec_promote_demote : if ( TARGET_VSX ) return <NUM_LIT> ; else return <NUM_LIT> ; case cond_branch_taken : return <NUM_LIT> ; case unaligned_load : case vector_gather_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return


<s> unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT>


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new <ISA_LIT>AsmBackendDarwin ( T , TT , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>AsmBackendWinCOFF ( T , TT ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new <ISA_LIT>AsmBackendELF ( T , TT , OSABI ,


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; bool isAdd = MO1 . getImm ( )


<s> if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ; return false


<s> subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , NONCONST ) { rtx x = * iter ; if ( GET_CODE ( x ) == TRUNCATE ) { rtx reg = XEXP ( x , <NUM_LIT> ) ; machine_mode reg_mode = GET_MODE ( reg ) ; if ( REG_P ( reg ) && GET_MODE_SIZE ( reg_mode ) > <NUM_LIT> ) { int offset = subreg_lowpart_offset ( DImode , reg_mode ) ; XEXP ( x , <NUM_LIT> ) = simplify_subreg ( DImode ,


<s> int getPICBasePointerSaveIndex ( ) const { return PICBasePointerSaveIndex


<s> else Ret += <STR_LIT> ; if ( TT . isOSIAMCU ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ( ! TT . isArch64Bit ( ) && TT . isOSWindows ( ) ) || TT . isOSIAMCU ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } const <ISA_LIT>Subtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) { SDValue Op0 = ShAmt . getOperand ( <NUM_LIT> ) ; Op0 = DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , <STR_LIT> , Op0 ) ; ShAmt = getShuffleVectorZeroOrUndef ( Op0 , <NUM_LIT> , true , & Subtarget , DAG ) ; } else { SmallVector < SDValue , <NUM_LIT> > ShOps ; ShOps . push_back ( ShAmt ) ; if ( SVT == <STR_LIT> ) { ShOps . push_back ( DAG . getConstant ( <NUM_LIT> , SVT ) ) ; ShOps . push_back ( DAG . getUNDEF ( SVT ) ) ; } ShOps . push_back ( DAG . getUNDEF ( SVT ) ) ; MVT BVT = SVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ShAmt = DAG . getNode ( <STR_LIT> , dl , BVT , ShOps ) ; } MVT EltVT = VT


<s> auto Inst = WinEH :: Instruction ( UnwindCode , Label , Reg , Offset ) ; if ( InEpilogCFI ) CurFrame -> EpilogMap [ CurrentEpilog ] .


<s> SDValue <ISA_LIT>TargetLowering :: EmitCmp ( SDValue Op0 , SDValue Op1 , unsigned <ISA_LIT>CC , const SDLoc & dl , SelectionDAG & DAG ) const { if ( isNullConstant ( Op1 ) ) return EmitTest ( Op0 , <ISA_LIT>CC , dl , DAG , Subtarget ) ; EVT CmpVT = Op0 . getValueType ( ) ; if ( CmpVT . isFloatingPoint ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op1 ) ; assert ( ( CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> ) && <STR_LIT> ) ; if ( CmpVT == <STR_LIT> && ! Subtarget . isAtom ( ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { ConstantSDNode * COp0 = dyn_cast < ConstantSDNode > ( Op0 ) ; ConstantSDNode * COp1 = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT>


<s> SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getScatterNode ( IntrData -> Opc0 , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case PREFETCH : { SDValue Hint = Op . getOperand ( <NUM_LIT> ) ; unsigned HintVal = cast < ConstantSDNode > ( Hint ) -> getZExtValue ( ) ; assert ( ( HintVal == <NUM_LIT> || HintVal == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opcode = ( HintVal == <NUM_LIT> ? IntrData -> Opc1 : IntrData -> Opc0 ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getPrefetchNode ( Opcode , Op , DAG , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case RDTSC : { SmallVector < SDValue , <NUM_LIT> > Results ; getReadTimeStampCounter ( Op . getNode ( ) , dl , IntrData -> Opc0 , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , dl ) ; } case RDPMC : case XGETBV : { SmallVector < SDValue , <NUM_LIT> > Results ; expandIntrinsicWChainHelper ( Op . getNode ( ) , dl , DAG , IntrData -> Opc0 , <STR_LIT> , Subtarget , Results ) ; return DAG . getMergeValues ( Results , dl ) ; } case XTEST : { SDVTList VTs = DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue InTrans = DAG . getNode ( IntrData -> Opc0 , dl , VTs , Op . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = getSETCC ( <STR_LIT> , InTrans , dl , DAG ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , dl , Op -> getValueType ( <NUM_LIT> ) , SetCC ) ; return DAG . getNode ( <STR_LIT> , dl , Op -> getVTList ( ) , Ret , SDValue ( InTrans . getNode ( ) , <NUM_LIT> ) ) ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToTruncate = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * MemIntr = dyn_cast < MemIntrinsicSDNode > ( Op ) ; assert ( MemIntr && <STR_LIT> ) ; EVT MemVT = MemIntr -> getMemoryVT (


<s> bool isCK807 ( ) const { return <ISA_LIT>ProcFamily


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return Table


<s> __vector unsigned long long __a = ( __vector


<s> bool hasSwap ( ) const { return HasSwap


<s> return ExtVal . getValueType ( ) . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( ExtVal . getValueType (

) , Subtarget -> useSVEForFixedLengthVectors ( ) ) ;


<s> static void StoreTailCallArgumentsToStackSlot ( SelectionDAG & DAG , SDValue Chain , const SmallVector < TailCallArgumentInfo , <NUM_LIT> > & TailCallArgs , SmallVector < SDValue , <NUM_LIT> > & MemOpChains , SDLoc dl ) { for ( unsigned i = <NUM_LIT> , e = TailCallArgs . size ( ) ; i != e ; ++ i ) { SDValue Arg = TailCallArgs [ i ] . Arg ; SDValue FIN = TailCallArgs [ i ]


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> ,


<s> Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true


<s> MVT WVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * VT . getVectorNumElements ( ) ) ; if ( VT != <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WVT ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! DAG . MaskedValueIsZero ( N1 , Mask17 ) || ! DAG . MaskedValueIsZero


<s> static inline bool isDef32 ( const SDNode & N ) { unsigned Opc = N . getOpcode ( ) ; return Opc != <STR_LIT> && Opc != TargetOpcode :: EXTRACT_SUBREG && Opc !=


<s> return IC . replaceInstUsesWith ( II , Extract ) ; } auto * IntrPG = dyn_cast < IntrinsicInst > ( Pg ) ; if ( ! IntrPG ) return None ; if ( IntrPG -> getIntrinsicID ( ) != <STR_LIT> ) return None ; const auto PTruePattern = cast < ConstantInt > ( IntrPG -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Idx ; switch ( PTruePattern ) { default : return None ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; } if ( IsAfter ) ++ Idx ; auto * PgVTy = cast < ScalableVectorType > ( Pg -> getType ( ) ) ; if ( Idx >= PgVTy -> getMinNumElements ( ) ) return None ; auto * IdxTy = Type :: getInt64Ty ( II . getContext ( ) ) ; auto * Extract = ExtractElementInst :: Create ( Vec , ConstantInt :: get ( IdxTy , Idx ) ) ; Extract -> insertBefore ( & II ) ; Extract -> takeName (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) .


<s> HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions =


<s> bool <ISA_LIT>TTIImpl :: forceScalarizeMaskedGather ( VectorType * VTy , Align Alignment ) { unsigned NumElts = cast < FixedVectorType > ( VTy ) -> getNumElements


<s> EVT VT = V128Reg . getValueType ( ) ; unsigned WideSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT NarrowTy = <STR_LIT> ( EltTy , WideSize / <NUM_LIT> ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , SDLoc ( V128Reg ) ,


<s> Relocation :: Type type = pRelocation . type ( ) ; if ( type >= sizeof ( <ISA_LIT>_64ApplyFunctions ) / sizeof ( <ISA_LIT>_64ApplyFunctions


<s> } x ; x . q = q ; return ( x . l [ <NUM_LIT> ]


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( VT == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UaddLV ) ; return UaddLV ; } else if ( VT == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UaddLV ) ; } if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; EVT VT8Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getBitcast ( VT8Bit , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , VT8Bit , Val ) ; unsigned EltSize = <NUM_LIT> ; unsigned NumElts = VT . is64BitVector ( ) ? <NUM_LIT> : <NUM_LIT> ; while ( EltSize != VT . getScalarSizeInBits ( ) ) { EltSize *= <NUM_LIT> ; NumElts /= <NUM_LIT> ; MVT WidenVT = <STR_LIT> ( <STR_LIT> ( EltSize ) , NumElts ) ; Val = DAG . getNode ( <STR_LIT> , DL , WidenVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Val ) ; } return Val


<s> case TYPE_FCMPD : case TYPE_FCONSTS : case TYPE_FCONSTD : case TYPE_FMULS : case TYPE_FMACS : case TYPE_FMULD : case TYPE_FMACD : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_F_MRC : case TYPE_F_MRRC : case TYPE_F_FLAG : case TYPE_F_LOADS : case TYPE_F_STORES : return true ; default : return false


<s> auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable

( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ;


<s> if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , SSatVal ) ; if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; return SDValue (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm


<s> InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = nullptr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII . get ( ) , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr


<s> const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; assert ( MFI . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; }


<s> unsigned DstReg = getRegTy ( SrcReg , MF ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( MVT ( getRegTy ( SrcReg , MF ) ) . isFatPointer ( ) ) DstReg = <STR_LIT> ; BuildMI ( * MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; I -> getOperand ( <NUM_LIT> ) . setReg (


<s> return checkBitcastSrcVectorSize ( Src . getOperand ( <NUM_LIT> ) , Size , AllowTruncate ) && checkBitcastSrcVectorSize ( Src . getOperand ( <NUM_LIT> ) , Size , AllowTruncate ) ; } return false


<s> if ( TARGET_ARCH64 && GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) != <NUM_LIT> ) return ! reg_classes_intersect_p ( rclass , FP_REGS ) ; return true


<s> void <ISA_LIT>BaseTargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) { PM . add ( createBasicTargetTransformInfoPass ( this ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass ( this


<s> MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; O << '\n' ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { O << * Stubs [ i ] . first << <STR_LIT> ; O << * Stubs [ i ] .


<s> return ( __m256i ) __builtin_ia32_expandloaddi256_maskz ( ( __v4di * ) __P , ( __v4di ) _mm256_setzero_si256 ( ) , (


<s> enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_USE_SAHF && ! optimize_size ) return <NUM_LIT> ; ix86_fp_comparison_codes ( code , & bypass_code ,


<s> Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X


<s> if ( ! CE ) return true ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value


<s> emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow ) , wide )


<s> DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t


<s> case CONST : x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( ! CONST_INT_P ( x ) ) ; } switch ( GET_CODE ( x ) ) { case LABEL_REF : case SYMBOL_REF : return true ; case UNSPEC : return XINT ( x , <NUM_LIT> ) == UNSPEC_CONST || XINT ( x , <NUM_LIT> ) == UNSPEC_PID_ADDR ; default : gcc_unreachable ( ) ; } break ; case LABEL_REF : case SYMBOL_REF : return true ; case CONST_DOUBLE : return ( rx_max_constant_size == <NUM_LIT> || rx_max_constant_size == <NUM_LIT> ) ; case CONST_VECTOR : return false ; default : gcc_assert ( CONST_INT_P ( x


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri


<s> if ( S -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ,


<s> if ( PrevVCMP ) { if ( MachineOperand * MO = Instr . findRegisterUseOperand ( PrevVCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , true ) ) { PrevVCMPResultKiller = MO ; } } if ( getVPTInstrPredicate ( Instr ) != <STR_LIT> ) continue ; if ( ! IsVCMP ( Instr . getOpcode ( ) ) ) { if ( IsWritingToVCCR ( Instr ) ) PrevVCMP = nullptr ; continue ; } if ( ! PrevVCMP || ! IsVPNOTEquivalent ( Instr , * PrevVCMP ) ) { PrevVCMP = & Instr ; continue ; } Register PrevVCMPResultReg = PrevVCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & Instr , Instr . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( Instr . getOperand ( <NUM_LIT> ) ) . addReg ( PrevVCMPResultReg ) ; addUnpredicatedMveVpredNOp ( MIBuilder ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Instr . dump


<s> case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case


<s> mips_split_move ( dest , src , mips_insn_split_type


<s> if ( GET_MODE_CLASS ( mode ) != MODE_CC ) mode = SELECT_CC_MODE ( comp_code , XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ; return aarch64_get_condition_code_1 ( mode


<s> SDValue Setcc = DAG . getNode ( <STR_LIT> , dl , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG


<s> Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args

) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ;


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address , const void *


<s> <ISA_LIT>FI -> setCallsEhReturn ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT Ty = <STR_LIT> ; unsigned OffsetReg = <STR_LIT> ; unsigned AddrReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain


<s> VA . convertToReg ( <STR_LIT> ) ; } } } if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset (


<s> __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4v2si ( ( __builtin_aarch64_simd_si * ) __a


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) { if ( ST -> hasNEON ( ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; else if ( isLegalMVEShuffleOp ( PFEntry ) ) { unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned PFEntryLHS = PerfectShuffleTable [ LHSID ] ; unsigned PFEntryRHS = PerfectShuffleTable [ RHSID ] ; if ( isLegalMVEShuffleOp ( PFEntryLHS ) && isLegalMVEShuffleOp ( PFEntryRHS ) ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } } } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( ST -> hasNEON ( ) && VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ; if ( ST -> hasMVEIntegerOps ( ) ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEUsingMovs ( Op ,


<s> return __builtin_mve_vmaxvq_p_uv8hi ( __a ,


AfterCSRPopSize , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI , & HasWinCFI ) ;


<s> if ( MF ) callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; static const TargetRegisterClass * const CalleeSavedRegClasses32Bit [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClasses64Bit [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const CalleeSavedRegClassesWin64 [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; if ( Is64Bit


<s> static DecodeStatus DecodeMSACtrlRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAM3Offset ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { AsmToken Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * Offset ; SMLoc E ; if ( getParser ( ) . ParseExpression ( Offset , E ) ) return MatchOperand_ParseFail ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Offset ) ; if ( ! CE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) Val = INT32_MIN ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S , E ) ) ; return MatchOperand_Success ; } bool haveEaten = false ; bool isAdd = true ; if ( Tok . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; haveEaten =


<s> bool isTargetKFreeBSD ( ) const { return TargetTriple . isOSKFreeBSD


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * )


<s> SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Chain = DAG . getStore ( Chain , DL , Entry . Node , FIPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Entry . Node = FIPtr ; Entry . Ty = PointerType :: getUnqual ( ArgTy ) ; } Args . push_back (


<s> return LPCC :: ICC_VC ; case LPCC :: ICC_PL : return LPCC :: ICC_MI ; case LPCC :: ICC_MI : return LPCC :: ICC_PL ; case LPCC :: ICC_GE : return LPCC :: ICC_LT ; case LPCC :: ICC_LT : return LPCC :: ICC_GE ; case LPCC :: ICC_GT : return LPCC :: ICC_LE ; case LPCC :: ICC_LE : return LPCC :: ICC_GT


<s> Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: CreateExpr ( MCSym ) ; assert ( Offset > <NUM_LIT> ) ; const MCConstantExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , * Ctx ) ; const MCBinaryExpr * AddExpr = MCBinaryExpr :: CreateAdd ( MCSym ,


<s> bool <ISA_LIT>ConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return true


<s> uint32_t getAddrMode3OffsetOpValue ( const MachineInstr & MI , unsigned OpIdx ) const { return <NUM_LIT>


<s> MF -> insert ( MBBI , NewBB ) ; for ( const MachineBasicBlock :: RegisterMaskPair & RegMaskPair : BB -> liveins ( ) ) NewBB -> addLiveIn ( RegMaskPair ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB


<s> return ( __m128d ) __builtin_ia32_sqrtsd_mask_round ( ( __v2df ) __B , ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( ) ,


<s> Type * V256I32Ty = VectorType :: get ( Builder . getInt32Ty ( ) , <NUM_LIT> , false ) ; AllocaInst * AllocaRes = new AllocaInst ( V256I32Ty , AllocaAS , <STR_LIT> , & F -> getEntryBlock ( ) . front ( ) ) ; BasicBlock :: iterator Iter = AllocaRes -> getIterator (


<s> const_ix86_first_cycle_multipass_data_t data = ( const_ix86_first_cycle_multipass_data_t ) _data ; unsigned int i = <NUM_LIT> ; sbitmap_iterator sbi ; gcc_assert ( bitmap_last_set_bit ( data -> ready_try_change


<s> if ( ! MaybeBit ) return false ; int32_t Bit = MaybeBit -> Value . exactLogBase2 ( ) ; if ( Bit < <NUM_LIT> ) return false ; Register TestReg = AndInst . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitTestBit ( TestReg , Bit , Invert , DstMBB , MIB ) ; return


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG .

getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ;


<s> ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregoiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregoiv4si (


<s> bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( ANDIVal , dl ) , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += selectI64ImmInstrCount ( Mask ) + <NUM_LIT> ; SDValue MaskVal = SDValue ( selectI64Imm ( CurDAG , dl , Mask ) , <NUM_LIT> ) ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ,

ExtendToInt64 ( Res , dl ) , MaskVal ) , <NUM_LIT> ) ;


<s> Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . vol = true ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc =


<s> unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> )


<s> return __builtin_loongson_pandn_uh ( s ,


<s> case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : break ; case <STR_LIT> : emitConstPoolInstruction ( MI ) ; break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> : emitMOVi32immInstruction ( MI ) ; break ; case <STR_LIT> : emitMOVi2piecesInstruction ( MI ) ; break ; case <STR_LIT> : emitLEApcrelJTInstruction ( MI ) ; break ; case


<s> emit_insn ( gen_ashlsi3 ( tmp_gpr_si , element_si , const2_rtx ) ) ; emit_insn ( VECTOR_ELT_ORDER_BIG ? gen_vextuwlx ( dest_si , tmp_gpr_si , src ) : gen_vextuwrx ( dest_si , tmp_gpr_si , src ) ) ; } return ; } gcc_assert ( REG_P ( tmp_altivec ) ) ; if ( scalar_size == <NUM_LIT> ) { if ( ! VECTOR_ELT_ORDER_BIG ) { emit_insn ( gen_xordi3 ( tmp_gpr , element , const1_rtx ) ) ; element2 = tmp_gpr ; } else element2 = element ; emit_insn ( gen_rtx_SET ( tmp_gpr , gen_rtx_AND ( DImode , gen_rtx_ASHIFT ( DImode , element2 , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { if ( ! VECTOR_ELT_ORDER_BIG ) { rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( mode ) - <NUM_LIT> ) ; emit_insn ( gen_anddi3 ( tmp_gpr , element , num_ele_m1 ) ) ; emit_insn ( gen_subdi3 ( tmp_gpr , num_ele_m1 , tmp_gpr ) ) ; element2 = tmp_gpr ; } else element2 = element ; emit_insn ( gen_ashldi3 ( tmp_gpr , element2 , GEN_INT ( bit_shift ) ) ) ; } if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_splat_v2di ( tmp_altivec , tmp_gpr ) ) ; else if ( can_create_pseudo_p ( ) ) emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_gpr , tmp_gpr ) ) ; else { rtx tmp_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; emit_move_insn ( tmp_di , tmp_gpr ) ; emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_di , tmp_di ) ) ; } switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_vslo_v2df ( dest , src , tmp_altivec ) ) ; return ; case E_V2DImode


<s> void LLVMInitializePowerPCAsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > B ( getThe<ISA_LIT>64Target (


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeList Attrs = MF . getFunction ( ) . getAttributes ( ) ; return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) && ! Attrs . hasAttrSomewhere ( Attribute

:: SwiftAsync ) && MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: SwiftTail ;


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI -> getRegisterInfo ( ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; assert ( RI -> regsOverlap ( RegToPrint , Reg ) ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint , isVector ? <STR_LIT> : <STR_LIT>


<s> const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; bool IsN64 = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI ->


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++


<s> return ( __m128i ) vec_adds ( ( __v16qi )


<s> bool has<ISA_LIT>64r5 ( ) const { return <ISA_LIT>ArchVersion >= <ISA_LIT>64r5


<s> case CodeModel :: Tiny : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( gettBLXrOpcode ( * MBB -> getParent ( ) ) ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit


<s> assert ( ( State -> getCallOrPrologue ( ) == Prologue || State -> getCallOrPrologue ( ) == Call ) && <STR_LIT> ) ; if ( ( ! State -> isFirstByValRegValid ( ) ) && ( <STR_LIT> <= reg ) && ( reg <= <STR_LIT> ) ) { if ( Subtarget -> isAAPCS_ABI ( ) && Align > <NUM_LIT> ) { unsigned AlignInRegs = Align / <NUM_LIT> ; unsigned Waste = ( <STR_LIT> - reg ) % AlignInRegs ; for ( unsigned i = <NUM_LIT> ; i < Waste ; ++ i ) reg = State -> AllocateReg ( GPRArgRegs , <NUM_LIT> ) ; } if ( reg != <NUM_LIT> ) { State -> setFirstByValReg ( reg )


<s> State = IES_ERROR ; break ; case IES_INTEGER : case IES_OFFSET : case IES_REGISTER : case IES_RBRAC : case IES_RPAREN : State = IES_RPAREN ; IC . pushOperator


<s> if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) rclass = to ; if ( rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS ) ret = ( rs6000_memory_move_cost ( mode , rclass , false ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , false ) ) ; else if ( rclass == CR_REGS ) ret = <NUM_LIT> ; else if ( ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names [ from ] , reg_class_names [ to ] ) ; dbg_cost_ctrl


<s> EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; if ( ArgTy -> isFP128Ty ( ) ) { int FI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Chain = DAG . getStore ( Chain , DL , Entry . Node , FIPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Entry . Node =


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; unsigned FCFOp = ( Subtarget . hasFPCVT ( ) && Op . getValueType ( ) == <STR_LIT> ) ? ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) : ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT FCFTy = ( Subtarget . hasFPCVT ( ) && Op . getValueType ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Subtarget . hasFPCVT ( ) ) || ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; DCI . AddToWorklist ( Src . getNode ( ) ) ; } else if ( Src . getValueType ( ) != <STR_LIT> ) { return SDValue ( ) ; } unsigned FCTOp = Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Tmp = DAG . getNode ( FCTOp , dl , <STR_LIT> , Src ) ; SDValue FP = DAG . getNode ( FCFOp , dl , FCFTy , Tmp ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! Subtarget . hasFPCVT ( ) ) { FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FP , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; DCI . AddToWorklist ( FP . getNode ( ) ) ; } return FP ; } return SDValue ( )


<s> Register SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) ,


<s> return ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; int Val = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , cast < FixedVectorType > ( VecTy ) , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , cast < FixedVectorType > ( VecTy ) , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices


<s> bool <ISA_LIT>TargetLowering :: getIndexedAddressParts ( SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , bool & IsInc , SelectionDAG & DAG ) const { if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand


<s> static bool MayFoldVectorLoad ( SDValue V ) { if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> && V . getNumOperands ( ) == <NUM_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) V


<s> case <STR_LIT> : { SDValue IntRes = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) ) ; IntRes = DAG . getNode ( <STR_LIT> , DL , VT , IntRes , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getSetCC ( DL , <STR_LIT> , IntRes , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; } case <STR_LIT> : { SDValue IntRes = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; IntRes = DAG . getNode ( <STR_LIT> , DL , VT , IntRes , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getSetCC ( DL , <STR_LIT> , IntRes , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; } case <STR_LIT> : { SDValue IntRes = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; IntRes = DAG . getNode ( <STR_LIT> , DL , VT , IntRes , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getSetCC ( DL , <STR_LIT> , IntRes , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto SrcOperand = N -> getOperand ( <NUM_LIT> ) ; auto SizeOperand = N -> getOperand ( <NUM_LIT> ) ; if ( SrcOperand -> getOpcode ( ) != <STR_LIT> ) break ; unsigned SrcIID = cast < ConstantSDNode > ( SrcOperand -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( SrcIID != <STR_LIT> && SrcIID != <STR_LIT> && SrcIID != <STR_LIT> && SrcIID != <STR_LIT> ) { break ; } if ( ! DAG . isEqualTo ( SizeOperand , SrcOperand -> getOperand ( <NUM_LIT> ) )


<s> SDLoc dl ( Op ) ; assert ( ( ! N -> isCompressingStore ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isCompressingStore ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; if ( ! N -> isCompressingStore ( ) && VT . getVectorNumElements ( ) <= <NUM_LIT> ) return Op ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; MVT MaskEltTy = Mask . getSimpleValueType ( ) . getScalarType ( ) ; assert ( ( MaskEltTy == <STR_LIT> || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( MaskEltTy , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; if ( MaskEltTy != <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) , Mask ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , Mask , N -> getMemoryVT (

) , N -> getMemOperand ( ) , N -> isTruncatingStore ( ) , N -> isCompressingStore ( ) ) ;


<s> case TYPE_ALU : if ( movd44_insn_p ( producer ) ) def_reg = extract_movd44_odd_reg ( producer ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( INSN_CODE ( producer ) == CODE_FOR_divmodsi4 || INSN_CODE ( producer ) == CODE_FOR_udivmodsi4 ) def_reg = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD


<s> if ( ! VT1 . isScalarInteger ( ) || ! VT2 . isScalarInteger ( ) ) return false ; unsigned NumBits1 = VT1


<s> size = ( size + va_granularity - <NUM_LIT> ) & ~ ( va_granularity - <NUM_LIT> ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE |


<s> return MatchOperand_Success ; } ; SMLoc S = getLoc ( ) ; auto LCurly = getTok ( ) ; Lex ( ) ; if ( parseOptionalToken ( AsmToken :: RCurly ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateMatrixTileList ( <NUM_LIT> , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( getTok ( ) . getString ( ) . equals_insensitive ( <STR_LIT> ) ) { Lex ( ) ; if ( parseToken ( AsmToken :: RCurly , <STR_LIT> ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: CreateMatrixTileList ( <NUM_LIT> , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } SMLoc TileLoc = getLoc ( ) ; unsigned FirstReg , ElementWidth ; auto ParseRes = ParseMatrixTile ( FirstReg , ElementWidth ) ; if ( ParseRes != MatchOperand_Success ) { getLexer ( ) . UnLex ( LCurly ) ; return ParseRes ; } const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned PrevReg = FirstReg ; SmallSet < unsigned , <NUM_LIT> > DRegs ; <ISA_LIT>Operand :: ComputeRegsForAlias ( FirstReg , DRegs , ElementWidth ) ; SmallSet < unsigned , <NUM_LIT> > SeenRegs ; SeenRegs . insert ( FirstReg ) ; while ( parseOptionalToken ( AsmToken :: Comma ) ) { TileLoc = getLoc ( ) ; unsigned Reg , NextElementWidth ; ParseRes = ParseMatrixTile ( Reg , NextElementWidth ) ; if ( ParseRes != MatchOperand_Success ) return ParseRes ; if ( ElementWidth != NextElementWidth ) { Error ( TileLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( RI -> getEncodingValue ( Reg ) <= ( RI -> getEncodingValue ( PrevReg ) ) ) Warning ( TileLoc , <STR_LIT> ) ; if ( SeenRegs . contains ( Reg ) ) Warning ( TileLoc , <STR_LIT> ) ; else { SeenRegs . insert ( Reg ) ; <ISA_LIT>Operand :: ComputeRegsForAlias ( Reg , DRegs , ElementWidth ) ; } PrevReg = Reg


<s> return DCI . CombineTo ( N , Res1 , CarryOut ) ; } if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> void <ISA_LIT>GNULDBackend :: addNonPICBranchSym ( ResolveInfo


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case <STR_LIT>


<s> __o = __builtin_aarch64_ld3rv4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregciv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregciv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregciv4sf ( __o , <NUM_LIT> ) ; return


<s> bool selectBDXAddr12Only ( SDValue Addr , SDValue & Base , SDValue & Disp


<s> case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( ) == CombineOpcode ) break ; continue ; } break ; } if ( ! V . hasOneUse ( ) ) return false ; DCI . CombineTo ( N . getNode ( ) , N . getOperand ( <NUM_LIT> ) , true ) ; SDValue Old = V ; SmallVector < int , <NUM_LIT> > VMask = getPSHUFShuffleMask ( V ) ; for ( int & M : Mask ) M = VMask [ M ] ; V = DAG . getNode ( V . getOpcode ( ) , DL , <STR_LIT> , V . getOperand ( <NUM_LIT> ) , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; if ( Old != V ) DCI . CombineTo ( Old .


<s> CPU = <STR_LIT> ( TT , CPU ) ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> getThumbBLXTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue (

MI , OpIdx , <STR_LIT> , Fixups , STI ) ;


<s> unsigned CmpXchgNbWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned OpWidth = MemType -> getPrimitiveSizeInBits ( ) ; if ( OpWidth == CmpXchgNbWidth ) return true ; return false


<s> static unsigned getCRBitValue ( unsigned CRBit ) { unsigned Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; assert ( Ret != <NUM_LIT> && <STR_LIT> ) ; return Ret


<s> static bool printModifiedFPRAsmOperand ( const MachineOperand & MO , const TargetRegisterInfo * TRI , char RegType , raw_ostream & O ) { if ( ! MO . isReg ( ) )


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( )


<s> get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; if ( rounded_size <= ( HOST_WIDE_INT_1 << <NUM_LIT> ) ) emit_insn ( gen_rtx_SET ( sr . reg , plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size -


<s> return ( int32x4_t ) __builtin_neon_vmvnv4si (


<s> const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ) return RegStructReturn ; return StackStructReturn


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mfspr_di :


<s> for ( auto * V : AllValues ) { if ( auto * I = dyn_cast < Instruction > ( V ) ) { if ( I -> mayWriteToMemory (


<s> return isMemDisp12 ( BDMem , ADDR64Reg


<s> return <STR_LIT> ; } virtual bool runOnMachineFunction ( MachineFunction & MF ) ; virtual void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; virtual void EmitFunctionEntryLabel ( ) ; virtual void EmitFunctionBodyStart ( ) ; virtual void EmitFunctionBodyEnd ( ) ; virtual bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = <NUM_LIT> ) ; void EmitStartOfAsmFile ( Module & M ) ; void EmitEndOfAsmFile ( Module & M ) ; void PrintDebugValueComment ( const MachineInstr * MI , raw_ostream


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( Opcode , DL , { LoadVT


<s> if ( AreAliased ( AA , Aliases , MACCandidates ) ) continue ; PMACPairList PMACPairs = CreateParallelMACPairs ( MACCandidates ) ; Changed = InsertParallelMACs ( R , PMACPairs ) || Changed ; } LLVM_DEBUG ( if ( Changed ) dbgs ( ) << <STR_LIT> ; Header -> dump ( ) ; ) ; return Changed


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind


<s> if ( TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( arm_libcall_uses_aapcs_base ( libcall ) ) return gen_rtx_REG ( mode


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FuncInfo -> Fn -> getName ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << <STR_LIT> << TBB -> getName ( ) << <STR_LIT> << TProb << <STR_LIT> << <STR_LIT> << FBB -> getName ( ) << <STR_LIT> << FProb << <STR_LIT> ) ; const BasicBlockSDNode * BBDN = cast < BasicBlockSDNode > ( DestMBB ) ; if ( BBDN -> getBasicBlock ( ) -> getBasicBlock ( )

!= TBB ) std :: swap ( TProb , FProb ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( LoExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false


<s> unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Has64BitPointers = Subtarget -> has64BitPointers ( ) ; EVT SPTy = Has64BitPointers ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Subtarget -> is64Bit ( ) ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys ,


<s> if ( ToW == <NUM_LIT> && isNEONi64splat ( )


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY_TO_REGCLASS ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = TmpReg ; } unsigned DestReg = createResultReg ( & <STR_LIT> ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) if ( IsSigned )


<s> if ( COMPLEX_FLOAT_TYPE_P ( t ) ) return false ; if ( TYPE_SIZE ( t ) != TYPE_SIZE ( b ) ) return false ; return supported_simd_type (


<s> if ( MEM_P ( dest ) ) return gen_altivec_stvx_v4si_internal ( dest , src ) ; else return gen_altivec_lvx_v4si_internal ( dest , src


<s> rtl_opt_pass * make_pass_constant_pool_broadcast ( gcc :: context * ctxt ) { return new pass_constant_pool_broadcast ( ctxt )


<s> Parser . Lex ( ) ; const MCExpr * subExpr ; if ( Parser . parseParenExpression ( subExpr , EndLoc ) ) return false ; bool isPIC = getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ; switch ( VK ) { default : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : VK = ( hasGOTReference ( subExpr ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC10 : ( isPIC ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT10 : VK ) ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : VK = ( hasGOTReference ( subExpr ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 : ( isPIC ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT22 : VK ) ) ; break ; } EVal = <ISA_LIT>MCExpr :: Create ( VK , subExpr ,


<s> if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( <STR_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <STR_LIT> ) . getReg ( ) ; return


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cgen_insns ) ; i ++ ) if ( ( cgen_insns [ i ] . groups & GROUP_KNOWN_CODE ) == <NUM_LIT> && mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] >= <NUM_LIT> ) { tree ret_type = void_type_node ; tree bi_type ; if ( i > <NUM_LIT> && cgen_insns [ i ] . intrinsic == cgen_insns [ i - <NUM_LIT> ] . intrinsic ) continue ; if ( cgen_insns [ i ] . cret_p ) ret_type = mep_cgen_regnum_to_type ( cgen_insns [ i ] . regnums [ <NUM_LIT> ] . type ) ; bi_type = build_function_type_list ( ret_type


<s> if ( ! LaneC || LaneC -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; } LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> )


<s> SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; SDValue Vcarryin = N -> getOperand ( <NUM_LIT> ) ; SDNodeTreeBuilder b ( & DAG , dl ) ; if ( DCI . isBeforeLegalize ( ) && ( ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) || ( Subtarget -> hasAVX ( ) && VT == <STR_LIT> ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( ) ) ; SDValue Ret = LongStreamAddition ( VT , V1 , V2 , Vcarryin , b ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Ret . dumpr ( ) ) ; return Ret ; } return SDValue


<s> static bool getTargetConstantBitsFromNode ( SDValue Op , unsigned EltSizeInBits , SmallBitVector & UndefElts , SmallVectorImpl < APInt > & EltBits ) { assert ( UndefElts . empty ( ) && <STR_LIT> ) ; assert ( EltBits . empty ( ) && <STR_LIT> ) ; Op = peekThroughBitcasts ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; assert ( ( SizeInBits % EltSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = SizeInBits / EltSizeInBits ; APInt UndefBits ( SizeInBits , <NUM_LIT> ) ; APInt MaskBits ( SizeInBits , <NUM_LIT> ) ; auto SplitBitData = [ & ] ( ) { UndefElts = SmallBitVector ( NumElts , false ) ; EltBits . resize ( NumElts , APInt ( EltSizeInBits , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { APInt UndefEltBits = UndefBits . lshr ( i * EltSizeInBits ) ; UndefEltBits = UndefEltBits . zextOrTrunc ( EltSizeInBits ) ; if ( UndefEltBits . isAllOnesValue ( ) ) { UndefElts [ i ] = true ; continue ; } APInt Bits = MaskBits . lshr ( i * EltSizeInBits ) ; Bits = Bits . zextOrTrunc ( EltSizeInBits ) ; EltBits [ i ] = Bits . getZExtValue ( ) ; } return true ; } ; auto ExtractConstantBits = [ SizeInBits ] ( const Constant * Cst , APInt & Mask , APInt & Undefs ) { if ( ! Cst ) return false ; unsigned CstSizeInBits = Cst -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( isa < UndefValue > ( Cst ) ) { Mask = APInt :: getNullValue ( SizeInBits ) ; Undefs = APInt :: getLowBitsSet ( SizeInBits , CstSizeInBits ) ; return true ; } if ( auto * CInt = dyn_cast < ConstantInt > ( Cst ) ) { Mask = CInt -> getValue ( ) . zextOrTrunc ( SizeInBits ) ; Undefs = APInt :: getNullValue ( SizeInBits ) ; return true


<s> const <ISA_LIT>InstrInfo * TII = getInstrInfo ( ) ; if ( RxSBG . Rotate != <NUM_LIT> ) Mask = ( Mask << RxSBG . Rotate ) | ( Mask


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value


<s> set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , <STR_LIT> ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( TARGET_PPC_GPOPT ) set_optab_libfunc ( sqrt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , mode , <STR_LIT> )


<s> Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getCondCode ( ) ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Add

, DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> bool isAligned = ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg ,


<s> static bool mips_can_inline_p ( tree caller , tree callee ) { if ( mips_get_compress_mode ( callee ) != mips_get_compress_mode ( caller ) ) return false ; return default_target_can_inline_p ( caller , callee )


<s> vrev16_p8 ( poly8x8_t a ) { return __builtin_shuffle ( a , ( uint8x8_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> auto Load = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Register ( <STR_LIT> ) } ) . addImm ( <NUM_LIT> ) ; MIB . buildInstr ( getBLRCallOpcode ( MF ) , { } , { Load } ) . addDef ( <STR_LIT> , RegState :: Implicit ) . addRegMask ( TRI . getTLSCallPreservedMask ( ) ) ; MIB . buildCopy ( I . getOperand ( <NUM_LIT> )

. getReg ( ) , Register ( <STR_LIT> ) ) ;


<s> EVT VT = Op . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; assert ( ( NumElems % <NUM_LIT> ) == <NUM_LIT> && ( SizeInBits % <NUM_LIT>


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( )


<s> if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) ) return true ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; else if ( auto * Cast = dyn_cast < CastInst > ( V ) ) { if ( isa < ZExtInst > ( Cast ) ) return Cast -> getDestTy ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ; else if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return Trunc -> getDestTy ( ) -> getScalarSizeInBits ( ) <= TypeSize ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! isa < BinaryOperator > ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false