<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; } else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ; if ( LS ) { if ( LS -> getMemoryVT ( ) == <STR_LIT> && Subtarget -> has<ISA_LIT>4_32r2 ( ) ) return false ; if ( LS -> getMemoryVT ( ) == <STR_LIT> && Subtarget -> has<ISA_LIT>4_32r2 ( ) ) return false ; } } Base = Addr


<s> bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL


<s> ParseDirective ( AsmToken DirectiveID ) { return


<s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; MBB . addSuccessor ( TargetBB


<s> return ( __m64 ) __builtin_arm_wqmulwm ( ( __v2si ) a , ( __v2si )


<s> if ( Ext . getOpcode ( ) != <STR_LIT> || ! Ext . hasOneUse ( ) ) return SDValue ( ) ; SDValue SetCC = Ext . getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) != <STR_LIT> || ! SetCC . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC = ( <STR_LIT> ) SetCC . getConstantOperandVal ( <NUM_LIT> ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = SetCC . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue CmpOp0 = Cmp . getOperand ( <NUM_LIT>


<s> if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl =


<s> EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT>

, CallingConv :: C , false , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> bool isScalarFPTypeInSSEReg ( MVT VT ) const { return ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) || ( VT == <STR_LIT>


<s> std :: string Ret ; Ret += <STR_LIT> ; Ret +=


<s> ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o ,


<s> sprintf ( l1size , <STR_LIT> , l1_sizekb ) ; sprintf ( line , <STR_LIT> , l1_line ) ; sprintf ( l2size , <STR_LIT> , l2_sizekb ) ; return concat ( l1size , <STR_LIT> , line , <STR_LIT> , l2size , <STR_LIT> ,


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : case AtomicRMWInst :: Add : case AtomicRMWInst :: Sub : return false ; case AtomicRMWInst :: Or : case AtomicRMWInst :: And : case AtomicRMWInst :: Xor : return ! AI -> use_empty ( ) ; case AtomicRMWInst :: Nand : case AtomicRMWInst :: Max


<s> unsigned ElemBytes = VT . getVectorElementType ( ) . getStoreSize ( ) ; if ( ElemBytes <= <NUM_LIT> ) { Opcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EVT InVT = VT . changeVectorElementTypeToInteger ( ) ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( ElemBytes * <NUM_LIT> ) , <STR_LIT> / ElemBytes / <NUM_LIT> ) ; if ( VT != InVT ) { Op1 = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , InVT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; } SDValue Op = DAG . getNode ( Opcode , SDLoc ( N )


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI == <ISA_LIT>Subtarget :: N64 ? <NUM_LIT> : ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) .

isTargetNaCl ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) {


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } int64_t Imm = CI -> getZExtValue


<s> if ( arg . end_marker_p ( ) ) return NULL ; return loongarch_get_arg_info ( & info , cum , arg . mode ,


<s> AlignFragment * align = NULL ; if ( pFrom . getSection ( ) . align ( ) > <NUM_LIT> ) { unsigned int alignment = pFrom . getSection ( ) . align ( ) ; align = new AlignFragment ( alignment , <NUM_LIT> , <NUM_LIT> , alignment - <NUM_LIT> ) ; align -> setOffset ( offset ) ; align -> setParent ( & pTo ) ; pTo . getFragmentList ( ) . push_back ( align ) ; offset += align -> size ( ) ; } SectionData :: FragmentListType & from_list = pFrom . getFragmentList ( ) ; SectionData :: FragmentListType & to_list = pTo . getFragmentList ( ) ; SectionData :: FragmentListType :: iterator frag , fragEnd = from_list . end ( ) ; for ( frag = from_list . begin ( ) ; frag != fragEnd ; ++ frag ) { frag -> setParent ( & pTo ) ; frag -> setOffset (


<s> Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget . useSoftFloat ( ) && ! ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget . hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue ( <NUM_LIT> ) ; return DAG . getLoad ( ArgVT , dl , Chain , VAARG , MachinePointerInfo


<s> if ( fpB == llvm :: <STR_LIT> ) return true ; if ( fpB == llvm :: <STR_LIT> && fpA == llvm :: <STR_LIT> ) return true ; if ( fpB != llvm :: <STR_LIT> )


<s> assert ( isReg ( ) && <STR_LIT> ) ; return Reg .


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget * Subtarget = & MF -> getSubtarget < <ISA_LIT>Subtarget >


<s> } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { Register XMMReg = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveXMMRegs . push_back ( DAG . getCopyFromReg ( Chain , DL , XMMReg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Offset = FuncInfo -> getVarArgsGPOffset ( ) ; for ( SDValue Val : LiveGPRs ) { SDValue FIN = DAG . getNode ( <STR_LIT> , DL , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) , RSFIN , DAG . getIntPtrConstant ( Offset , DL ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FuncInfo -> getRegSaveFrameIndex ( ) , Offset ) ) ; MemOps . push_back ( Store ) ; Offset += <NUM_LIT> ; } if ( ! LiveXMMRegs . empty ( ) ) { SmallVector < SDValue , <NUM_LIT> > SaveXMMOps ; SaveXMMOps . push_back ( Chain ) ; SaveXMMOps . push_back ( ALVal ) ; SaveXMMOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getRegSaveFrameIndex ( ) , DL , <STR_LIT> ) ) ; SaveXMMOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) ) ; llvm :: append_range ( SaveXMMOps


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( &


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) ) , TT , CPU , FS , Options

, RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) {


<s> static unsigned getFPReg ( const MachineOperand & MO ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO .


<s> const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( auto & OrigArg : OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , CallConv ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) SplitArgs . back ( ) . Flags . setZExt ( ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask (


<s> StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; Args . push_back ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; if ( Idx + <NUM_LIT> == NbArgs ) break ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> + Twine ( IDVal ) + <STR_LIT> ) ) return true ; } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> + Twine ( IDVal ) +


<s> FunctionPass * llvm :: createShadowCallStackPass ( ) { return new ShadowCallStack


<s> } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Size ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setHasWinAlloca ( true ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ; if ( Align ) { SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , SP ) ; } Result = SP ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , SDValue ( ) , dl ) ; SDValue Ops [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues (


<s> save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ; for ( i = cum -> regno ; i < max ; i ++ ) { mem = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( word_mode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( ix86_varargs_fpr_size ) { machine_mode smode ; rtx_code_label * label ; rtx test ; label = gen_label_rtx (


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Enable<ISA_LIT>TailCalls && ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return ! Subtarget -> isThumb1Only


<s> Opc = isThumb ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = isThumb ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = isThumb ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr ,


<s> } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugInstr ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; llvm :: sort ( Candidates , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates ) { if ( Candidate -> CanMergeToLSMulti || Candidate -> CanMergeToLSDouble ) { MachineInstr * Merged = MergeOpsUpdate ( * Candidate ) ; if ( Merged ) { Changed = true ; unsigned Opcode = Merged -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MergeBaseUpdateLSDouble ( * Merged ) ; else MergeBaseUpdateLSMultiple ( Merged )


<s> SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP


<s> if ( Dest -> getNumber ( ) <= Src -> getNumber ( ) ) { BranchSize = BrOffset ; MaxAlign = std :: max ( MaxAlign , Src -> getAlignment ( ) ) ; int DestBlock = Dest -> getNumber ( ) ; BranchSize += BlockSizes [ DestBlock ] . first ; for ( unsigned i = DestBlock + <NUM_LIT> , e = Src -> getNumber ( ) ; i < e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxAlign = std :: max ( MaxAlign , Fn . getBlockNumbered ( i ) -> getAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( DestBlock >= FirstImpreciseBlock ) ; } else { unsigned StartBlock = Src -> getNumber ( ) ; BranchSize = BlockSizes [ StartBlock ] . first - BrOffset ; MaxAlign = std :: max ( MaxAlign , Dest -> getAlignment ( ) ) ; for ( unsigned i = StartBlock + <NUM_LIT> , e = Dest -> getNumber ( ) ; i != e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxAlign = std :: max ( MaxAlign , Fn . getBlockNumbered ( i )


<s> if ( none_of ( Defs , isa < Instruction , Value * > ) ) return false ; for ( Value * V : Defs ) if ( ! isa < PHINode > ( V ) && ! isa < Constant > ( V ) && ! isa < Argument > ( V ) && ! isa < CallInst > ( V ) ) return false ; for ( Value * V : Defs ) if ( const PHINode * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { User * First = dyn_cast < User > ( Pair . first ) ; User * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: intRegClass ( unsigned Size ) const { return &


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) , InstInfo ( <NUM_LIT> ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> static std :: pair < unsigned , const TargetRegisterClass * > parseRegisterNumber ( StringRef Constraint , const TargetRegisterClass * RC , const unsigned * Map ) { assert ( * ( Constraint . end ( )


<s> static void iq2000_annotate_frame_insn ( rtx insn , rtx dwarf_pattern ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern


<s> int base ; int i ; strcpy ( pattern , <STR_LIT> ) ; p = strlen ( pattern ) ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) ; base = ( REGNO ( operands [ <NUM_LIT> ] ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < XVECLEN ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; i ++ ) { p += sprintf ( & pattern [ p ] , <STR_LIT> , base + i ) ; } strcpy ( & pattern [ p ] , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT>


<s> static int xbbo_next_reg_cluster ( int regno_start , int * sp_offset , bool do_store ) { int regno , nregs , i ; rtx addr ; rtx_insn * insn ; nregs = <NUM_LIT> ; for ( ; regno_start <= LAST_GP_REGNUM ; ) if ( TEST_HARD_REG_BIT ( cfun -> machine -> save_mask , regno_start ) ) break ; else regno_start ++ ; for ( regno = regno_start ; regno <= LAST_GP_REGNUM ; ) if ( TEST_HARD_REG_BIT ( cfun -> machine -> save_mask , regno ) ) { regno ++


<s> unsigned InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++ I ; MI . removeFromParent ( ) ; LIS -> repairIntervalsInRange ( & MBB , First ,


<s> else AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; else if ( DestRC == <STR_LIT> ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; else return false ; return


<s> const LLT CastPtrTy = PtrTy . isVector ( ) ? LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) : LLT :: scalar ( <NUM_LIT> ) ; auto PtrToInt = MIB . buildPtrToInt ( CastPtrTy , AddOp1Reg ) ; if ( PtrTy . isVector ( ) ) MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; else MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . setDesc ( TII . get ( TargetOpcode :: G_ADD ) ) ; MRI . setType (


<s> OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm =


<s> if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return


<s> auto * SplatValue = IntrI -> getOperand ( <NUM_LIT> ) ; return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; auto IsUnitDup = [ ] ( auto * I ) { auto * IntrI = dyn_cast < IntrinsicInst > ( I ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; auto * SplatValue = IntrI -> getOperand ( <NUM_LIT> ) ; return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; if ( IsUnitDup ( OpMultiplicand ) || IsUnitDupX ( OpMultiplicand ) ) std :: swap ( OpMultiplier , OpMultiplicand ) ; if ( IsUnitDupX ( OpMultiplier ) ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } else if ( IsUnitDup ( OpMultiplier ) ) { auto * DupInst = cast < IntrinsicInst > ( OpMultiplier ) ; auto * DupPg = DupInst -> getOperand ( <NUM_LIT> ) ; if ( OpPredicate == DupPg ) { OpMultiplicand -> takeName (


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { if ( ! arm_valid_target_attribute_rec ( args ,


<s> if ( SimplifyDemandedVectorElts ( Mask , DemandedElts , MaskUndef , MaskZero , TLO , Depth + <NUM_LIT> ) ) return true ; SDValue BC = peekThroughOneUseBitcasts ( Mask ) ; EVT BCVT = BC . getValueType ( ) ; auto * Load = dyn_cast < LoadSDNode > ( BC ) ; if ( ! Load ) return false ; const Constant * C = getTargetConstantFromNode ( Load ) ; if ( ! C ) return false ; Type * CTy = C -> getType ( ) ; if ( ! CTy -> isVectorTy ( ) || CTy -> getPrimitiveSizeInBits ( ) != Mask . getValueSizeInBits ( ) ) return false ; unsigned NumCstElts = cast < FixedVectorType > ( CTy ) -> getNumElements ( ) ; if ( NumCstElts != NumElts && NumCstElts != ( NumElts * <NUM_LIT> ) ) return false ; unsigned Scale =


<s> static bool isEAXLiveIn ( MachineBasicBlock & MBB ) { for ( MachineBasicBlock :: RegisterMaskPair RegMask : MBB . liveins ( ) ) { unsigned Reg = RegMask


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR64DecoderTable [ RegNo ] ; if ( Register == <STR_LIT> ) Register = <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS


<s> else return CC_<ISA_LIT>_64_C ; } if ( CC == CallingConv :: <ISA_LIT>_FastCall ) return CC_<ISA_LIT>_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_<ISA_LIT>_32_FastCC ; else return


<s> ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ; return


<s> return ( uint16x4_t ) __builtin_neon_vld1_lanev4hi ( ( const __builtin_neon_hi * ) __a


<s> if ( MO . isExpr ( ) ) { O << * MO . getExpr ( ) ; return ; } int32_t OffImm = ( int32_t ) MO . getImm ( ) ; if ( OffImm == INT32_MIN ) O <<


<s> bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ; if ( might_split_p


<s> HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false


<s> MCInst Noop ; Subtarget -> getInstrInfo ( ) -> getNoop ( Noop ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) OutStreamer -> EmitInstruction ( Noop , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , Kind


<s> auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; const <ISA_LIT>Subtarget * Subtarget ; for ( Function & Func : M ) { if ( ! Func . isDeclaration ( ) ) continue ; if ( ! isMASSVFunc ( Func . getName ( ) ) ) continue ; SmallVector < User * , <NUM_LIT> > MASSVUsers ( Func . users ( ) ) ; for ( auto * User : MASSVUsers ) { auto * CI = dyn_cast <


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv2di ( ( int64x2_t )


<s> odd = d -> perm [ <NUM_LIT> ] ; if ( odd != <NUM_LIT> && odd != <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != <NUM_LIT> * i + odd ) return false ; if ( d -> vmode == E_V32HImode && d -> testing_p && ! TARGET_AVX512BW


<s> <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; SDValue NotOp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; SDValue NotOp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , NotOp1 ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , NotOp0 , Op1 ) ; case <STR_LIT> : case <STR_LIT>


<s> return ( __m256 ) __builtin_ia32_vfmaddps256 ( - ( __v8sf ) __A ,


<s> static bool getConstantValueForReg ( unsigned Reg , MachineRegisterInfo & MRI , unsigned & Val ) { MachineInstr * Def = MRI . getVRegDef ( Reg ) ; if ( ! Def ) return false ; if ( Def -> isCopy ( ) ) { Reg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto It = find_if_not ( MRI . reg_nodbg_instructions ( Reg ) , [ ] ( const MachineInstr & MI ) { return MI . isCopy ( ) ; } ) ; if ( It == MRI . reg_instr_nodbg_end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Def = & * It ; } if ( Def -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { LLVM_DEBUG ( dbgs ( ) <<


<s> return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU , false


<s> else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; if ( Subtarget -> isTargetWindows ( ) && Addr . getGlobalValue ( ) && Addr . getGlobalValue ( ) -> hasExternalWeakLinkage ( ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing (


<s> unsigned NSlots ; if ( MCID && mustComeFirst ( MCID , NSlots ) && CurSlots ) return true ; return ScoreboardHazardRecognizer :: ShouldPreferAnother (


<s> SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> ) , <NUM_LIT> , false , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { bool is64 = getPointerSize ( ) ==


<s> LiveIntervals & LIs = G . getMetadata ( ) . LIS ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; LLVM_DEBUG ( MF . dump ( ) ) ; for ( const auto & MBB : MF ) { Chains . clear ( ) ; for ( const auto & MI : MBB ) { for ( auto r : Chains ) { SmallVector < unsigned , <NUM_LIT> > toDel ; if ( regJustKilledBefore ( LIs , r , MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( r , TRI ) << <STR_LIT> ; MI . print ( dbgs ( ) ) ; ) ; toDel . push_back ( r ) ; } while ( ! toDel . empty ( ) ) { Chains . remove ( toDel . back ( ) ) ; toDel . pop_back ( ) ; } } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( addIntraChainConstraint ( G , Rd , Ra ) ) addInterChainConstraint ( G , Rd , Ra ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand (


<s> bool ISASupported = ! Subtarget -> has<ISA_LIT>32r6 ( ) && ! Subtarget -> inMicro<ISA_LIT>Mode ( ) && Subtarget -> has<ISA_LIT>32 ( ) ; TargetSupported = ISASupported && TM . isPositionIndependent ( ) && getABI ( ) . IsO32 ( ) ; UnsupportedFPMode = Subtarget -> isFP64bit (


<s> Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; } } return nullptr ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT> ) return nullptr ; SDValue Reg0 = CurDAG -> getRegister


<s> if ( CSI . empty ( ) ) return false ; static LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses ,


<s> BusyRegs . push_back ( convReg ( ShadowReg , <NUM_LIT> ) ) ; BusyRegs . push_back ( convReg ( ScratchReg , <NUM_LIT>


<s> __builtin_sh_media_PREFO ( mm + s , <NUM_LIT>


<s> MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent


<s> if ( aarch64_expand_sve_vec_cmp_float ( pred , GET_CODE ( ops [ <NUM_LIT> ] ) , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , true ) ) std :: swap ( ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ; } else aarch64_expand_sve_vec_cmp_int ( pred , GET_CODE ( ops [ <NUM_LIT> ] ) , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ; if ( ! aarch64_sve_reg_or_dup_imm ( ops [ <NUM_LIT> ] , data_mode ) ) ops [ <NUM_LIT> ] = force_reg ( data_mode , ops [ <NUM_LIT> ] ) ; if ( register_operand ( ops [ <NUM_LIT> ] , data_mode ) || ! aarch64_simd_reg_or_zero ( ops [ <NUM_LIT> ] , data_mode ) ) ops [


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> int aarch64_host_wide_int_compare ( const void * x , const void * y ) { return wi :: cmps ( * ( ( const HOST_WIDE_INT * ) x ) , * ( ( const HOST_WIDE_INT * )


<s> if ( TII -> analyzeBranch ( * HBB , TBB , FBB , HeadCond ) ) { continue ; } if ( ! TBB || TBB == HBB ) { continue ; } SmallVector < MachineOperand , <NUM_LIT> > TrueCond ; MachineBasicBlock * TBB_TBB = nullptr , * TBB_FBB = nullptr ; if ( TII -> analyzeBranch ( * TBB , TBB_TBB , TBB_FBB , TrueCond ) ) { continue ; } MachineInstr * HeadCmpMI = findSuitableCompare ( HBB ) ; if ( ! HeadCmpMI ) { continue ; } MachineInstr * TrueCmpMI = findSuitableCompare ( TBB ) ; if ( ! TrueCmpMI ) { continue ; } <STR_LIT> HeadCmp ; if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm


<s> static SDValue LowerVECTOR_SHUFFLEv32i8 ( ShuffleVectorSDNode * SVOp , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { MVT VT = SVOp -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasInt256 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero && ! V2IsAllZero ) { CommuteVectorShuffleMask ( MaskVals , <NUM_LIT> ) ; V1 = V2 ; } SmallVector < SDValue , <NUM_LIT> >


<s> return ( __m128i ) __builtin_ia32_vpperm ( ( __v16qi ) __A , ( __v16qi )


<s> bool isInRequiredFeatures ( FeatureBitset TestFeatures ) const { return ( FeaturesRequired & TestFeatures )


<s> static SDValue performCSELCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ) return N -> getOperand ( <NUM_LIT> ) ; return performCONDCombine ( N , DCI ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ForLoadFold ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeSImmWithOffsetAndScale ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { int32_t Imm = SignExtend32 < Bits > ( Value ) * ScaleBy ; Inst . addOperand ( MCOperand :: createImm ( Imm + Offset ) ) ; return MCDisassembler :: Success


<s> MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget -> hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI -> eraseFromParent ( ) ; return EndMBB


<s> if ( ! SMALL_OPERAND ( step1 ) ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , adjust ) ; adjust = MIPS_EPILOGUE_TEMP ( Pmode ) ; } if ( ! TARGET_MIPS16 ) target = stack_pointer_rtx ; emit_insn ( gen_add3_insn ( target , base , adjust ) ) ; } if ( target != stack_pointer_rtx ) emit_move_insn ( stack_pointer_rtx , target ) ; if ( TARGET_ABICALLS && TARGET_NEWABI && ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; mips_for_each_saved_reg ( cfun -> machine -> frame . total_size - step2 , mips_restore_reg ) ; if ( step2 > <NUM_LIT> ) emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; if ( current_function_calls_eh_return ) { if ( TARGET_MIPS16 ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , stack_pointer_rtx ) ; emit_insn ( gen_add3_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , MIPS_EPILOGUE_TEMP ( Pmode ) , EH_RETURN_STACKADJ_RTX ) ) ; emit_move_insn ( stack_pointer_rtx , MIPS_EPILOGUE_TEMP ( Pmode ) ) ; } else emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx


<s> if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> ) ShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasBMI2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && ShiftAmt . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShiftAmt . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( ShiftAmt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == Size ) return false ; SDValue NewShiftAmt ; if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> || ShiftAmt -> getOpcode ( ) == <STR_LIT> ) { SDValue Add0 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; SDValue Add1 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Add1 ) && cast < ConstantSDNode > ( Add1 ) -> getZExtValue ( ) % Size == <NUM_LIT> ) { NewShiftAmt = Add0 ; } else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Add0 ) && cast < ConstantSDNode > ( Add0 ) -> getZExtValue ( ) != <NUM_LIT> && cast < ConstantSDNode > ( Add0 ) -> getZExtValue ( ) % Size == <NUM_LIT> ) { EVT SubVT = ShiftAmt . getValueType ( ) ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , DL , SubVT ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = Neg ; insertDAGNode ( * CurDAG , OrigShiftAmt , Zero ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , Neg ) ; } else return false ; } else return false ; if ( NewShiftAmt . getValueType ( ) != <STR_LIT> ) { NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; } NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt , CurDAG -> getConstant ( Size - <NUM_LIT> , DL , <STR_LIT> ) ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegD ) ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ; else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; } return Binary


<s> bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FixupLocsForFn . size ( ) << <STR_LIT> ) ; for ( AESFixupLocation & FixupLoc : FixupLocsForFn ) { insertAESFixup ( FixupLoc , TII , TRI ) ; Changed |= true ; } return


<s> if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ( Rt & <NUM_LIT> ) || Rt == <NUM_LIT> || Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) )


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const { return isTargetWatchOS ( ) || ( isTargetIOS ( ) && ! getTargetTriple ( ) .

isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> if ( auto * RotateConst = BVAmt -> getConstantSplatNode ( ) ) { uint64_t RotateAmt = RotateConst -> getAPIntValue ( ) . getZExtValue ( ) ; assert ( RotateAmt < EltSizeInBits && <STR_LIT> ) ; if ( RotateAmt == <NUM_LIT> ) return R ; SDValue SHL = getTargetVShiftByConstNode ( <STR_LIT> , DL , VT , R , RotateAmt , DAG ) ; SDValue SRL = getTargetVShiftByConstNode ( <STR_LIT> , DL , VT , R , EltSizeInBits - RotateAmt , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SHL , SRL ) ; } } if ( Subtarget . hasAVX2 ( ) ) { SDValue AmtR = DAG . getConstant ( EltSizeInBits , DL , VT ) ; AmtR = DAG . getNode ( <STR_LIT> , DL , VT , AmtR , Amt ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , VT , R , Amt ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , VT , R , AmtR ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SHL , SRL ) ; } Amt = convertShiftLeftToScale ( Amt , DL , Subtarget , DAG ) ; assert ( Amt && <STR_LIT> ) ; static const int OddMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue R13 = DAG . getVectorShuffle ( VT , DL , R , R , OddMask ) ; SDValue Amt13 = DAG . getVectorShuffle ( VT , DL , Amt , Amt , OddMask ) ; SDValue Res02 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , R ) , DAG . getBitcast ( <STR_LIT> , Amt ) ) ; SDValue Res13 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , R13 ) , DAG . getBitcast ( <STR_LIT> , Amt13 ) ) ; Res02 = DAG . getBitcast ( VT , Res02


<s> U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg


<s> addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2AddrModeImm8s4 ( Inst , addr , Address , Decoder )


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; else return TargetTransformInfoImplBase :: isLSRCostLess ( C1 ,


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (

) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) { MBB . addLiveIn ( NextReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( NextReg ) . addReg ( <STR_LIT> ) . addImm ( ( NextReg - R4BaseReg ) * <NUM_LIT> ) ) ; } llvm :: prior ( MI ) -> addRegisterKilled ( <STR_LIT> ,


<s> static SDValue emitSETCC ( SelectionDAG & DAG , SDLoc DL , SDValue Glue , unsigned CCValid , unsigned CCMask ) { IPMConversion Conversion = getIPMConversion ( CCValid , CCMask ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; if ( Conversion . XORValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . XORValue , <STR_LIT> ) ) ; if ( Conversion . AddValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . AddValue , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . Bit , <STR_LIT> ) ) ; if ( Conversion . Bit != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return Result


<s> std :: pair < OutputIt1 , OutputIt2 > copy_if_else ( InputIt First , InputIt Last , OutputIt1 d1 , OutputIt2 d2 , UnaryPredicate Predicate ) { for ( InputIt I = First ; I != Last ; ++ I ) { if ( Predicate ( * I ) ) { * d1 = * I ; d1 ++ ; }


<s> if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 ,


<s> void VarArgsLoweringHelper :: lowerVarArgsParameters ( SDValue & Chain , unsigned StackSize ) { FuncInfo -> setVarArgsFrameIndex ( <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( <NUM_LIT> ) ; if ( FrameInfo . hasVAStart ( ) )

createVarArgAreaAndStoreRegisters ( Chain , StackSize ) ;


<s> return ( __m128 ) __builtin_ia32_vfmaddss3_mask ( ( __v4sf ) __W , - ( __v4sf ) __A , - (


<s> if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || SrcOpIdx1 == KMaskOp ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || SrcOpIdx2 == KMaskOp ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx1 = SrcOpIdx1 ; unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = LastCommutableVecOp ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ; unsigned Op2Reg = MI . getOperand ( CommutableOpIdx2 ) . getReg ( ) ; for ( CommutableOpIdx1 = LastCommutableVecOp ; CommutableOpIdx1 >= FirstCommutableVecOp ; CommutableOpIdx1 -- ) { if ( CommutableOpIdx1 == KMaskOp ) continue ; if ( Op2Reg != MI . getOperand ( CommutableOpIdx1 ) . getReg ( )


<s> return <NUM_LIT> ; case SP_REG : return <NUM_LIT> ; case BP_REG : return <NUM_LIT> ; case SI_REG : return <NUM_LIT> ; case DI_REG : return <NUM_LIT> ; default : break ; } if ( IN_RANGE ( regno , FIRST_STACK_REG , LAST_STACK_REG ) ) return regno - FIRST_STACK_REG ; if ( IN_RANGE ( regno , FIRST_SSE_REG , LAST_SSE_REG ) ) return regno - FIRST_SSE_REG ; if ( IN_RANGE ( regno , FIRST_MMX_REG , LAST_MMX_REG ) ) return regno - FIRST_MMX_REG ; if ( IN_RANGE ( regno , FIRST_REX_SSE_REG , LAST_REX_SSE_REG ) ) return regno - FIRST_REX_SSE_REG ; if ( IN_RANGE ( regno , FIRST_REX_INT_REG ,

LAST_REX_INT_REG ) ) return regno - FIRST_REX_INT_REG ;


<s> SDValue MaskedShamt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeft1Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeft1Hi , Not ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftRightHi = DAG . getNode ( IsSRA ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Hi , MaskedShamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops ,


<s> static unsigned int mips_multi_last_index


<s> if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 )


<s> } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT>


<s> vld1_dup_s8 ( const int8_t * __a ) { return ( int8x8_t ) __builtin_neon_vld1_dupv8qi ( ( const __builtin_neon_qi * )


<s> TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( )


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveR19R20X ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset ) )


<s> if ( ArgFlags . isInReg ( ) && ! Subtarget . isLittle ( ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs


<s> MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , CPI , <NUM_LIT>


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT NewTy ; const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpTy == <STR_LIT> )


<s> static void translateImmediate ( MCInst & mcInst , uint64_t


<s> EVT VT = Op . getNode ( ) -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT == <STR_LIT> ? <STR_LIT> : ValVT ) ; if ( ValVT == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( ) ; MinReservedArea = std :: max ( MinReservedArea , LinkageSize ) ; MinReservedArea = EnsureStackAlignment ( Subtarget . getFrameLowering ( ) , MinReservedArea ) ; FuncInfo -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const MCPhysReg GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ; static const MCPhysReg FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; if ( useSoftFloat ( ) ) NumFPArgRegs = <NUM_LIT> ; FuncInfo -> setVarArgsNumGPR ( CCInfo . getFirstUnallocated ( GPArgRegs ) ) ; FuncInfo -> setVarArgsNumFPR ( CCInfo . getFirstUnallocated ( FPArgRegs ) ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; FuncInfo -> setVarArgsStackOffset ( MFI . CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ; FuncInfo -> setVarArgsFrameIndex ( MFI . CreateStackObject ( Depth ,


<s> vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , cc , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; cc . v = ( vec_double2 ) (


<s> Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false ; } else if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false ; } Imm12 = Offset ; } } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm12 , Fixups , STI ) ; uint32_t Binary = Imm12 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg << <NUM_LIT> )


<s> if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( STI . hasLoadStoreOnCond2 ( ) && getConditionalLoadImmediate


<s> bool IsShortVector ( unsigned ValNo ) { return ArgIsShortVector [ ValNo


<s> assert ( Op . getValueType ( ) . is128BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op .


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * ) const { const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; bool isPIC = MF . getTarget ( ) . getRelocationModel ( )


<s> { <STR_LIT> , <STR_LIT> , MASK_64BIT } , { <STR_LIT> , <STR_LIT> , OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF \ | MASK_POWERPC64 } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , OPTION_MASK_ALTIVEC } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { NULL , <STR_LIT> , <NUM_LIT> } } ; const char * cpu_id = <STR_LIT> ; size_t i ; rs6000_file_start ( ) ; darwin_file_start ( ) ; if ( rs6000_default_cpu != <NUM_LIT> && rs6000_default_cpu [ <NUM_LIT> ] != '\0' ) cpu_id = rs6000_default_cpu ; if ( OPTION_SET_P ( rs6000_cpu_index ) ) cpu_id = processor_target_table [ rs6000_cpu_index ] . name ; i = <NUM_LIT> ; while ( mapping [ i ] . arg != NULL && strcmp ( mapping [ i ] . arg , cpu_id ) != <NUM_LIT> &&

( mapping [ i ] . if_set & rs6000_isa_flags ) == <NUM_LIT> ) i ++ ;


<s> vmls_f32 ( float32x2_t a , float32x2_t b , float32x2_t c ) { return a - b *


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > <NUM_LIT> ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; <ISA_LIT>RegSet LoRegsToRestore ; <ISA_LIT>RegSet HiRegsToRestore ; <ISA_LIT>RegSet CopyRegs ; for ( CalleeSavedInfo I : CSI ) { unsigned Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) { LoRegsToRestore [ Reg ] = true ; } else if ( <STR_LIT> . contains ( Reg ) && Reg != <STR_LIT> ) { HiRegsToRestore [ Reg ] = true ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( <STR_LIT> . contains ( Reg ) ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs [ Reg ] = true ; } auto Terminator = MBB . getFirstTerminator ( ) ; if ( Terminator != MBB . end ( ) && Terminator -> getOpcode ( ) == <STR_LIT> ) { CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; CopyRegs [ <STR_LIT> ] = true ; for ( auto Op : Terminator -> implicit_operands ( ) ) { if ( Op . isReg ( ) ) CopyRegs [ Op .


<s> static bool IsBitwiseBinaryOperator ( unsigned Opcode ) { switch ( Opcode ) { default : return Instruction :: isShift


<s> if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass (

create<ISA_LIT>GlobalBaseRegPass ( ) ) ;


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant

, Size , inferAlignFromPtrInfo ( MF , MPO ) ) ;


<s> unsigned NewImm = Imm ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { ShuffleMask . push_back ( NewImm % NumLaneElts + l ) ; NewImm /=


<s> if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && getInstrPredicate ( MI ,

MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ;


<s> if ( InputVector . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && ! DCI . isBeforeLegalize ( ) ) return ExtractBitFromMaskVector ( N , DAG ) ; if ( InputVector . getNode ( ) -> getOpcode ( ) == llvm :: <STR_LIT> && InputVector . getNode ( ) -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( InputVector ) , N -> getValueType ( <NUM_LIT> ) , InputVector . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( )


<s> void <ISA_LIT>DCInstruction :: translateCMPXCHG ( unsigned MemOpType , unsigned CmpReg ) { Value * PointerOperand = translateCustomOperand ( MemOpType , <NUM_LIT> ) ; Value * CmpVal = getReg ( CmpReg ) ; Value * Operand2 = getReg (


<s> else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true ; } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; return CurDAG -> getTargetNode ( Opcode , Op . getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } return NULL


<s> CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( CurrentFnDescSym ) ) ; FnDescSec -> setAlignment ( Align ( Subtarget -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect ( FnDescSec ) ; return AsmPrinter :: SetupMachineFunction (


<s> case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFunnelShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerEXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerStore ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFaddFsub ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op


<s> return __builtin_loongson_pmulhuh ( s


<s> } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = <STR_LIT> ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { Register CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY )

, CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isSVR4ABI


<s> return handleSlot ( [ this ] ( auto & I ) -> bool { return TII -> HasLoadDelaySlot ( I ) ; } , [ this ] ( auto & IInSlot


<s> if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue Op2 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue SetCC ; const ConstantSDNode * C = nullptr ; bool needOppositeCond = ( CC == <STR_LIT> ) ; bool checkAgainstTrue = false ; if ( ( C = dyn_cast < ConstantSDNode > ( Op1 ) ) ) SetCC = Op2 ; else if ( ( C = dyn_cast < ConstantSDNode > ( Op2 ) ) ) SetCC = Op1 ; else return SDValue ( ) ; if ( C -> getZExtValue ( ) == <NUM_LIT> ) { needOppositeCond = ! needOppositeCond ; checkAgainstTrue = true ; } else if ( C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; bool truncatedToBoolWithAnd = false ; while ( SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> ) { if ( SetCC . getOpcode ( ) == <STR_LIT> ) { int OpIdx = - <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( OpIdx < <NUM_LIT> ) break ; SetCC = SetCC . getOperand ( OpIdx ) ; truncatedToBoolWithAnd = true ; } else SetCC = SetCC . getOperand ( <NUM_LIT> ) ; } switch ( SetCC . getOpcode ( ) ) { case <STR_LIT> : if ( checkAgainstTrue && ! truncatedToBoolWithAnd ) break ; assert ( <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : CC = <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) ; if ( needOppositeCond ) CC = <STR_LIT> ( CC ) ; return SetCC . getOperand ( <NUM_LIT> ) ; case <STR_LIT>


<s> if ( WinEH :: FrameInfo * CurFrame = getCurrentWinFrameInfo ( ) ) EHStreamer . EmitUnwindInfo ( *


<s> inline bool isVpred ( uint8_t op ) { return isVpred ( static_cast < OperandType > ( op


<s> } unsigned CPI = getCombinedIndex ( CPEMI ) ; assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [


<s> return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) !=


<s> bool hasSlowLoadDSubregister ( ) const { return SlowLoadDSubregister


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT ,


<s> int64x1x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; return


<s> case AsmToken :: String : break ; } const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } MFI -> setAdjustsStack ( true


<s> return ( __m128 ) __builtin_ia32_cmpnless ( ( __v4sf ) __A ,


<s> unsigned getPointerWidth ( ) { if ( is16BitMode ( ) ) return <NUM_LIT> ; if ( is32BitMode ( ) )


<s> return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , Flags , MFI .


<s> MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if (

auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> int64_t Imm = <NUM_LIT> ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> )


<s> return recog_memoized ( insn ) >= <NUM_LIT> && get_attr_cannot_copy


<s> MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F

, TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( F , TM ) ) ;


<s> if ( Subtarget -> isMClass ( ) ) has64BitAtomicStore = false ; else if ( Subtarget -> isThumb ( ) ) has64BitAtomicStore = Subtarget -> hasV7Ops ( ) ; else has64BitAtomicStore = Subtarget -> hasV6Ops ( ) ; unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == <NUM_LIT> && has64BitAtomicStore ? AtomicExpansionKind :: Expand : AtomicExpansionKind


<s> int64x1x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t


<s> if ( ! FrameSize || FrameSize > Subtarget . getRedZoneSize ( ) ) return false ; if ( hasFP ( MF ) || RegInfo -> hasBasePointer ( MF ) ) return false ; if ( FI -> hasFastCall ( ) || FI -> usesPICBase ( )


<s> void <ISA_LIT>InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) ; MBB . insert ( MBB . end


<s> unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; saveLROnStack ( MBB , It ) ; unsigned StackAlignment = Subtarget . getStackAlignment ( ) . value ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo (


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo )


<s> APInt MaskInt64 ( <NUM_LIT> , I64String , <NUM_LIT> ) ; SDValue MaskNode64 = DAG -> getConstant ( MaskInt64 , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Pool ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) Pool . push_back ( MaskNode64 ) ; return BUILD_VECTOR ( NumType


<s> while ( ! MI . getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands ( ) && <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } bool IsSafe = false ; for ( MachineBasicBlock :: iterator I = CmpInstr , E = CmpInstr -> getParent ( ) -> end ( ) ; ! IsSafe && ++ I != E ; ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! IsSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { IsSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { IsSafe = true ; break ; } unsigned Opc = Instr . getOpcode ( ) ; <STR_LIT> CC ; switch ( Opc ) { default : return false ; case <STR_LIT> : CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNs ( const SDNode * N


<s> if ( ! global_offset_table ) global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; temp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp , global_offset_table ) ; return


<s> case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind , const MCExpr * Expr , MCContext &


<s> if ( pSym . isDyn ( ) || pSym . isUndef ( ) || pFactory . getTarget ( ) . isSymbolPreemptible


<s> enum machine_mode mode = GET_MODE ( x ) == VOIDmode ? GET_MODE ( y ) : GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ? DFmode : DImode ; if ( ! mmix_valid_comparison ( code , mode , x ) ) return NULL_RTX ; cc_reg = gen_reg_rtx ( ccmode ) ; if ( ! REG_P ( x ) && ! REG_P ( y ) ) x = force_reg ( mode , x ) ; if ( ! REG_P ( y ) && ( GET_CODE ( y ) != CONST_INT || ! CONST_OK_FOR_LETTER_P ( INTVAL ( y )

, 'I' ) ) ) y = force_reg ( mode , y ) ;


<s> op [ <NUM_LIT> ] = copy_to_mode_reg ( Pmode , op [ <NUM_LIT> ] ) ; bool blk = ( icode == CODE_FOR_altivec_lvlx || icode == CODE_FOR_altivec_lvlxl || icode == CODE_FOR_altivec_lvrx || icode == CODE_FOR_altivec_lvrxl ) ; if ( icode == CODE_FOR_altivec_lvx_v1ti || icode == CODE_FOR_altivec_lvx_v2df || icode == CODE_FOR_altivec_lvx_v2di || icode == CODE_FOR_altivec_lvx_v4sf || icode == CODE_FOR_altivec_lvx_v4si || icode == CODE_FOR_altivec_lvx_v8hi || icode == CODE_FOR_altivec_lvx_v16qi ) { rtx rawaddr ; if ( op [ <NUM_LIT> ] == const0_rtx ) rawaddr = op [ <NUM_LIT> ] ; else { op [ <NUM_LIT> ] = copy_to_mode_reg ( Pmode , op [ <NUM_LIT> ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - <NUM_LIT> ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma )


<s> if ( TT . isOSDarwin ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( Options . MCOptions . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>TargetMachine :: <ISA_LIT>_ABI_ELFv1 ; else if ( Options . MCOptions . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>TargetMachine :: <ISA_LIT>_ABI_ELFv2 ; assert ( Options . MCOptions . getABIName ( ) . empty ( ) && <STR_LIT> ) ; if ( TT . isMacOSX ( ) ) return <ISA_LIT>TargetMachine :: <ISA_LIT>_ABI_UNKNOWN ; switch ( TT . getArch ( ) ) { case Triple :: ppc64le : return <ISA_LIT>TargetMachine


<s> <ISA_LIT>CCState ( CallingConv :: ID CC , bool isVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & locs ,

LLVMContext & C , ParmContext PC ) : CCState ( CC , isVarArg , MF , locs , C ) {


<s> return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> )