<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return <NUM_LIT> && VT1 == <STR_LIT> &&


<s> } else if ( getChunk ( UImm , <NUM_LIT> ) == getChunk ( UImm , <NUM_LIT> ) ) { uint64_t OrrImm = replicateChunk ( UImm , <NUM_LIT> , <NUM_LIT> ) ; if ( tryOrrMovk ( UImm , OrrImm , MI , MBB , MBBI , TII , <NUM_LIT> ) ) return true ; OrrImm = replicateChunk ( UImm , <NUM_LIT> , <NUM_LIT> ) ; if ( tryOrrMovk ( UImm , OrrImm , MI , MBB , MBBI , TII , <NUM_LIT> ) ) return true ; } } if ( BitSize == <NUM_LIT> && tryToreplicateChunks ( UImm , MI , MBB , MBBI , TII ) ) return true ; if ( BitSize == <NUM_LIT> && trySequenceOfOnes ( UImm , MI , MBB , MBBI , TII ) ) return true ; bool isNeg = false ; if ( OneChunks > ZeroChunks ) { isNeg = true ; Imm = ~ Imm ; } unsigned FirstOpc ; if ( BitSize == <NUM_LIT> ) { Imm &= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; FirstOpc = ( isNeg ? <STR_LIT> : <STR_LIT> ) ; } else { FirstOpc = ( isNeg ? <STR_LIT> : <STR_LIT> ) ; } unsigned Shift = <NUM_LIT> ; unsigned LastShift = <NUM_LIT> ; if ( Imm != <NUM_LIT> ) { unsigned LZ = countLeadingZeros ( Imm ) ; unsigned TZ = countTrailingZeros ( Imm ) ; Shift = ( ( <NUM_LIT> - LZ ) / <NUM_LIT> ) * <NUM_LIT> ; LastShift = ( TZ / <NUM_LIT> ) * <NUM_LIT> ; } unsigned Imm16 = ( Imm >> Shift ) & Mask ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( FirstOpc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && Shift == LastShift ) ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , Shift ) ) ; if ( isNeg ) Imm = ~ Imm ; if ( Shift


<s> ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregoiv2sf ( __o , <NUM_LIT> ) ; return


<s> if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } } } unsigned OpIdx = Commute ? <NUM_LIT> : <NUM_LIT> ; Register Reg1 = UseMI . getOperand ( OpIdx ) . getReg ( ) ; bool isKill = UseMI . getOperand ( OpIdx ) . isKill (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) { unsigned EltSize = VT . getVectorElementType (


<s> int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg ,

SubIdx , Val , Pred , PredReg , MIFlags ) ;


<s> EVT CondVT = Cond . getValueType ( ) ; SDLoc DL ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( CondVT . isVector ( ) && <STR_LIT> ) ; bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros && FValIsAllZeros ) { if ( VT . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; } if ( TValIsAllZeros && ! FValIsAllZeros && Subtarget . hasAVX512 ( ) && Cond . hasOneUse ( ) && CondVT . getVectorElementType ( ) == <STR_LIT> ) { SDValue CondNew = DAG . getNOT ( DL , Cond , CondVT ) ; return DAG . getSelect ( DL , VT , CondNew , RHS , LHS ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros =


<s> SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; O << <STR_LIT> ; const Function * F = MF . getFunction ( ) ; OutStreamer . SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( F , Mang , TM ) ) ; EmitAlignment ( MF . getAlignment ( ) , F ) ; O << <STR_LIT> << CurrentFnName << '\n' ; printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; NumberForBB . clear ( ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { NumberForBB [ I -> getBasicBlock ( ) ] = BBNumber ++ ; } for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II ) ; ++


<s> SDValue Zero = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , VTs , None ) , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { Zero = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Zero , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ; } unsigned Opcode = N -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; unsigned FlagOpIndex = Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue EFLAGS = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , <STR_LIT> , N -> getOperand


<s> O << MI -> getOperand ( OpNo ) . getImm ( ) ; O << '(' ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ; O << ')'


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , STI . getFeatureBits ( ) , getContext ( ) ) ) ; Parser . Lex (


<s> GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = fastEmitZExtFromI1 ( <STR_LIT>


<s> Pass * llvm :: createMVEGatherScatterLoweringPass ( ) { return new MVEGatherScatterLowering


<s> cvtVSTwbFixed ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } AddDefaultPred ( LO16 ) ; AddDefaultPred ( HI16 ) ; } MI . eraseFromParent ( ) ; Modified = true ; } } MBBI = NMBBI ; } return Modified


<s> for ( unsigned i = <NUM_LIT> ; i != NumDstElts && ( MatchAny || MatchZero ) ; ++ i ) { if ( ! isUndefOrEqual ( Mask [ i * Scale ] , ( int ) i ) ) { MatchAny = MatchZero = false ; break ; } MatchAny &= isUndefInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; MatchZero &= isUndefOrZeroInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; } if ( MatchAny || MatchZero ) { assert ( MatchZero && <STR_LIT> ) ; unsigned SrcSize = std :: max ( <NUM_LIT> , NumDstElts * MaskEltSize ) ; MVT ScalarTy = MaskVT . isInteger ( ) ? MaskVT . getScalarType ( ) : <STR_LIT> ( MaskEltSize ) ; SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( MatchAny ? <STR_LIT> : <STR_LIT> ) ; if ( SrcVT . getVectorNumElements ( ) != NumDstElts ) Shuffle = getOpcode_EXTEND_VECTOR_INREG ( Shuffle ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasFP16 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; if ( MaskEltSize == <NUM_LIT> ) SrcVT = DstVT = MaskVT . changeVectorElementType ( <STR_LIT> ) ; else SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ,


<s> static DecodeStatus DecodeAddSubImmShift ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned S = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned ShifterVal = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned ImmVal = Imm & <NUM_LIT> ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( ShifterVal != <NUM_LIT> && ShifterVal != <NUM_LIT> ) return Fail ; if ( Datasize


<s> MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ; TmpInst . setOpcode ( Opcode


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MFI -> getStackSize ( ) ) && needsFP (


<s> static __inline unsigned long long sh_media_MADD_W ( unsigned long long mm , unsigned long


<s> return __builtin_loongson_pandn_ud ( s , t


<s> if ( Vec . getOpcode ( ) == <STR_LIT> ) return Result ; EVT VT = Vec . getValueType ( ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; SDValue VecIdx = DAG . getIntPtrConstant


<s> case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { auto MMO = * MI . memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI . getMF ( ) -> getSubtarget ( ) ) ; if ( ! isPowerOf2_64 ( MMO -> getSize ( ) ) ) return false ; bool isUnaligned = MMO -> getSize ( ) > MMO -> getAlignment ( ) ; if ( ! STI . systemSupportsUnalignedAccess ( )


<s> assert ( TII . getSubtarget ( ) . hasVFP2Base ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand (


<s> return Create ( VK_AARCH64_GOT_LO12 , Expr , Ctx


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target (


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) )


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( )


<s> } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = <NUM_LIT> , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg )


<s> Inst . addOperand ( MCOperand :: createReg ( XRegs [ getG8pReg ( )


<s> MachineInstrBuilder MIB = MIRBuilder . buildInstr ( <STR_LIT> ) ; assert ( MIB . getInstr ( ) && <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; if ( VReg ) { MIRBuilder . setInstr ( * MIB . getInstr ( ) , true ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; handleAssignments ( MIRBuilder , AssignFn , <STR_LIT> ( Val -> getType ( ) ) , VReg , [ & ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( PhysReg , ValReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit


<s> static void rs6000_option_override ( void


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ||

Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> target_flags |= ARM_FLAG_APCS_32 ; } if ( TARGET_APCS_STACK && ! TARGET_APCS_FRAME ) { warning ( <STR_LIT> ) ; target_flags |= ARM_FLAG_APCS_FRAME ; } if ( TARGET_POKE_FUNCTION_NAME ) target_flags |= ARM_FLAG_APCS_FRAME ; if ( TARGET_APCS_REENT && flag_pic ) error ( <STR_LIT> ) ; if ( TARGET_APCS_REENT ) warning ( <STR_LIT> ) ; if ( TARGET_ARM && write_symbols != NO_DEBUG && ! TARGET_APCS_FRAME && ( TARGET_DEFAULT & ARM_FLAG_APCS_FRAME ) ) warning ( <STR_LIT> ) ; if ( flag_pic ) arm_pic_register = TARGET_APCS_STACK ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_APCS_FLOAT ) warning ( <STR_LIT> ) ; arm_fast_multiply = ( insn_flags & FL_FAST_MULT ) != <NUM_LIT> ; arm_arch4 = ( insn_flags & FL_ARCH4 ) != <NUM_LIT> ; arm_arch5 = ( insn_flags & FL_ARCH5 ) != <NUM_LIT> ; arm_arch5e = ( insn_flags & FL_ARCH5E ) != <NUM_LIT> ; arm_is_xscale = ( insn_flags & FL_XSCALE ) != <NUM_LIT> ; arm_ld_sched = ( tune_flags & FL_LDSCHED ) != <NUM_LIT> ; arm_is_strong = ( tune_flags & FL_STRONG ) != <NUM_LIT> ; thumb_code = ( TARGET_ARM == <NUM_LIT> ) ; arm_is_6_or_7 = ( ( ( tune_flags & ( FL_MODE26 | FL_MODE32 ) ) && ! ( tune_flags & FL_ARCH4 ) ) ) != <NUM_LIT> ; arm_fpu = ( tune_flags & FL_CO_PROC ) ? FP_HARD : FP_SOFT3 ; if ( target_fp_name ) { if ( streq ( target_fp_name , <STR_LIT> ) ) arm_fpu_arch = FP_SOFT2 ; else if ( streq ( target_fp_name , <STR_LIT> ) ) arm_fpu_arch = FP_SOFT3 ; else error ( <STR_LIT> , target_fp_name ) ; } else arm_fpu_arch = FP_DEFAULT ; if ( TARGET_FPE && arm_fpu != FP_HARD ) arm_fpu = FP_SOFT2 ; if ( ( TARGET_SOFT_FLOAT || arm_fpu != FP_HARD ) && ( tune_flags & FL_MODE32 ) == <NUM_LIT> ) flag_schedule_insns = flag_schedule_insns_after_reload = <NUM_LIT> ; arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26 ; if ( structure_size_string != NULL ) { int size = strtol ( structure_size_string , NULL , <NUM_LIT> ) ; if ( size == <NUM_LIT> || size == <NUM_LIT> ) arm_structure_size_boundary = size ; else warning ( <STR_LIT> ) ; } if ( arm_pic_register_string != NULL ) { int pic_register = decode_reg_name ( arm_pic_register_string ) ; if ( ! flag_pic ) warning ( <STR_LIT> ) ; else if ( pic_register < <NUM_LIT> || call_used_regs [ pic_register ] || pic_register == HARD_FRAME_POINTER_REGNUM || pic_register == STACK_POINTER_REGNUM || pic_register >= PC_REGNUM ) error ( <STR_LIT> , arm_pic_register_string ) ; else arm_pic_register = pic_register ; } if ( TARGET_THUMB && flag_schedule_insns ) { flag_schedule_insns = <NUM_LIT>


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 ,


<s> } else if ( Lanes [ j ] != Mask [ i ] / LaneSize ) { return SDValue ( ) ; } int k = i % LaneSize ; if ( InLaneMask [ k ] < <NUM_LIT> ) { InLaneMask [ k ] = Mask [ i ] % LaneSize ; } else if ( InLaneMask [ k ] != Mask [ i ] % LaneSize ) { return SDValue ( ) ; } } MVT LaneVT = <STR_LIT> ( VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LaneMask ; LaneMask . resize ( NumLanes * <NUM_LIT> , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < NumLanes ; ++ i ) if ( Lanes [ i ] >= <NUM_LIT> ) { LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; } V1 = DAG . getBitcast ( LaneVT , V1 ) ; V2 = DAG . getBitcast ( LaneVT , V2 ) ; SDValue LaneShuffle = DAG . getVectorShuffle ( LaneVT , DL , V1 , V2 , LaneMask ) ; LaneShuffle = DAG . getBitcast ( VT , LaneShuffle ) ; SmallVector < int , <NUM_LIT> > NewMask ; NewMask . resize ( Size , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) NewMask [ i ] = ( i / LaneSize ) * LaneSize + Mask [ i ] % LaneSize ; assert ( ! is128BitLaneCrossingShuffleMask ( VT , NewMask


<s> insn = emit_move_insn ( dest , tempLR ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; } else if ( TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx tempLR = ( fromprolog ? gen_rtx_REG ( Pmode , LINK_REGISTER_REGNUM ) : gen_reg_rtx ( Pmode ) ) ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; rs6000_maybe_dead ( emit_insn ( gen_load_toc_v4_PIC_1 ( tempLR , symF ) ) ) ; rs6000_maybe_dead ( emit_move_insn ( dest , tempLR ) ) ; rs6000_maybe_dead ( emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest , symL , symF ) ) ) ; } else { rtx tocsym ; tocsym = gen_rtx_SYMBOL_REF ( Pmode , toc_label_name ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( tempLR , tocsym ) ) ; emit_move_insn ( dest , tempLR ) ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , dest ) ) ; } insn = emit_insn ( gen_addsi3 ( dest , temp0 , dest ) ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; } else if ( TARGET_ELF && ! TARGET_AIX && flag_pic == <NUM_LIT> && TARGET_MINIMAL_TOC ) { char buf [ <NUM_LIT> ] ; rtx realsym ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , <NUM_LIT> ) ; realsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; insn = emit_insn ( gen_elf_high ( dest , realsym ) ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; insn = emit_insn ( gen_elf_low ( dest , dest , realsym ) ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; } else { gcc_assert ( DEFAULT_ABI == ABI_AIX ) ; if ( TARGET_32BIT ) insn = emit_insn ( gen_load_toc_aix_si


<s> static DecodeStatus DecodeG8RC_NOX0RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst ,


<s> return __builtin_mve_vmulq_m_n_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a ,


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return ; libCall = ( ( N -> getOpcode ( ) == <STR_LIT> ) ? RTLIB :: FPTOSINT_F128_I64 : RTLIB :: FPTOUINT_F128_I64 ) ; Results . push_back ( LowerF128Op ( SDValue ( N , <NUM_LIT> ) , DAG , getLibcallName ( libCall ) , <NUM_LIT> ) ) ; return ; case <STR_LIT> : { assert ( Subtarget -> hasLeonCycleCounter ( ) ) ; SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getCopyFromReg ( Lo , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Lo , Hi } ; SDValue Pair = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; Results . push_back ( Pair ) ; Results . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return ; libCall = ( ( N -> getOpcode ( ) == <STR_LIT> ) ? RTLIB :: SINTTOFP_I64_F128 : RTLIB :: UINTTOFP_I64_F128 ) ; Results . push_back ( LowerF128Op ( SDValue ( N , <NUM_LIT> ) , DAG , getLibcallName ( libCall ) , <NUM_LIT> ) ) ; return ; case <STR_LIT> : { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; if ( Ld -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Ld -> getMemoryVT ( ) != <STR_LIT> ) return ; SDLoc dl ( N ) ; SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , dl , <STR_LIT> , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , <STR_LIT> , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadRes ) ; Results . push_back ( Res


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) && ! MF . getInfo < <ISA_LIT>MachineFunctionInfo


<s> static bool aarch64_simd_vector_alignment_reachable ( const_tree type , bool is_packed ) { if ( is_packed ) return false ; if ( tree_int_cst_compare ( TYPE_SIZE ( type ) , bitsize_int ( BIGGEST_ALIGNMENT ) ) >


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint ,


<s> <ISA_LIT>_64GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * pReloc . symInfo ( ) ) ; assert ( got_entry != NULL


<s> Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . DefaultBaseReg = DefaultBaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> Mem . FrontendSize = FrontendSize ; Res -> Mem . MaybeDirectBranchDest = MaybeDirectBranchDest ; Res -> UseUpRegs = UseUpRegs ; Res -> SymName = SymName ; Res -> OpDecl


<s> void llvm :: addPredicatedMveVpredNOp ( MachineInstrBuilder & MIB , unsigned Cond ) { MIB . addImm ( Cond ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addReg (


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) { rtx sub = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , <NUM_LIT> ) == UNSPEC_TOC ) return <NUM_LIT> ; } } } return <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( Subtarget -> hasLazyResolverStub ( GV ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else


<s> const uint32_t * RegMask = getTargetMachine ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } if ( ! Is64Bit ) BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( TargetOpcode :: COPY ) , mallocPtrVReg ) . addReg ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; BB -> addSuccessor ( bumpMBB ) ; BB -> addSuccessor (


<s> return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD | QCMP_GT ) !=


<s> static bool is_branch_slot_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { if ( get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; return true


<s> std :: pair < MachineInstr * , CmpInst :: Predicate > <ISA_LIT>InstructionSelector :: emitIntegerCompare ( MachineOperand & LHS , MachineOperand & RHS , MachineOperand & Predicate , MachineIRBuilder & MIRBuilder ) const { assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; MachineInstr * FoldCmp = tryFoldIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( FoldCmp ) return { FoldCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; unsigned CmpOpc = <NUM_LIT> ; Register ZReg ; LLT CmpTy = MRI . getType ( LHS . getReg ( ) ) ; assert ( ( CmpTy . isScalar ( ) || CmpTy . isPointer ( ) ) && <STR_LIT> ) ; if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) ) { CmpOpc = <STR_LIT> ; ZReg = <STR_LIT> ; } else if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) || CmpTy . isPointer ( ) ) { CmpOpc = <STR_LIT> ; ZReg = <STR_LIT> ; } else { return { nullptr , CmpInst :: Predicate :: BAD_ICMP_PREDICATE } ; } MachineInstr * ImmedCmp = tryOptArithImmedIntegerCompare ( LHS


<s> else if ( F . hasMinSize ( ) ) OptimizationGoal = <NUM_LIT> ; else if ( F . hasOptSize ( ) ) OptimizationGoal = <NUM_LIT> ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = <NUM_LIT> ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = <NUM_LIT> ; else OptimizationGoal = <NUM_LIT> ; if ( OptimizationGoals == - <NUM_LIT> ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = <NUM_LIT> ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> emitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> emitLabel (


<s> return __builtin_mve_vmvnq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) ,


<s> unsigned MaxInsts = Subtarget . restrictIT ( ) ? <NUM_LIT> : <NUM_LIT> ; return divideCeil ( NumInsts ,


<s> MEE = LastMI_GRNar ; } else { MII = FirstMI_GRNar ; MEE = LastMI_GR128 ; } BitVector PhysClobbered ( getNumRegs ( ) ) ; MEE ++ ; for ( ; MII != MEE ; ++ MII ) { for ( const MachineOperand & MO : MII -> operands ( ) ) if ( MO . isReg ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { for ( MCSuperRegIterator SI ( MO . getReg ( ) , this , true ) ; SI . isValid ( ) ; ++ SI ) if ( NewRC -> contains ( * SI ) ) { PhysClobbered . set ( * SI ) ; break ; } } } unsigned const DemandedFreeGR128 = <NUM_LIT> ; if ( PhysClobbered . count ( ) > ( NewRC -> getNumRegs

( ) - DemandedFreeGR128 ) ) return false ;


<s> MVT VMVT = TLI . getValueType ( DL , V -> getType ( ) , true ) . getSimpleVT ( ) ; if ( VMVT == <STR_LIT> ) return <NUM_LIT> ; if ( ( VMVT == <STR_LIT> ) || ( VMVT == <STR_LIT> ) ) { Register TempReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitIntExt ( VMVT , VReg , <STR_LIT> , TempReg ,


<s> if ( ForCodeSize || V . hasOneUse ( ) ) return true ; if ( Subtarget -> hasLSLFast ( ) && V . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( V ) ) return true ; if ( Subtarget -> hasLSLFast ( ) && V . getOpcode ( ) == <STR_LIT> ) { const SDValue LHS = V . getOperand ( <NUM_LIT> ) ; const SDValue RHS = V . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( LHS


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rn == <NUM_LIT> || Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn ,


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N

-> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo (


<s> return STI . getTargetTriple ( ) . getArchName (


<s> static DecodeStatus DecodeAS ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned sz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool cz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t simm32 = SignExtend64 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; DecodeStatus status ; if ( cz ) { status = DecodeI64RegisterClass ( MI , sz , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand ::


<s> uint64_t MaxIndex = <NUM_LIT> ; uint64_t RetElSize = RetVT . getVectorElementType ( ) . getSimpleVT ( ) . getStoreSize ( ) . getKnownMinSize ( ) ; ConstantSDNode * OffsetConst = dyn_cast < ConstantSDNode > ( Offset . getNode ( ) ) ; if ( nullptr == OffsetConst || OffsetConst -> getZExtValue ( ) > MaxIndex * RetElSize || OffsetConst -> getZExtValue ( ) % RetElSize ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType ( HwRetVt ) ; SDVTList VTs = DAG . getVTList ( HwRetVt , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Base , Offset , OutVT } ; SDValue Load = DAG . getNode ( Opcode , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( RetVT . isInteger ( ) && ( RetVT != HwRetVt ) ) Load = DAG

. getNode ( <STR_LIT> , DL , RetVT , Load . getValue ( <NUM_LIT> ) ) ;


<s> if ( MatchResult2 == Match_Success ) MatchResult = Match_Success ; else { <ISA_LIT>Operand * CCOut = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ; Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; delete CCOut ; } } else if ( MatchResult == Match_MnemonicFail ) { StringRef Mnemonic = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getToken ( ) ; if ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) == <STR_LIT> ) { StringRef MnemonicNoS = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; SMLoc NameLoc = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getStartLoc ( ) ; <ISA_LIT>Operand * OldMnemonic = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ; Operands . erase ( Operands . begin ( ) ) ; delete OldMnemonic ; Operands . insert ( Operands . begin ( ) , <ISA_LIT>Operand :: CreateToken ( MnemonicNoS , NameLoc ) ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , <ISA_LIT>Operand :: CreateCCOut ( <STR_LIT> , NameLoc ) ) ; MatchResult2 = MatchInstructionImpl ( Operands , Inst , ErrorInfo ) ; if ( MatchResult2 == Match_Success ) MatchResult = Match_Success ; else { <ISA_LIT>Operand * OldMnemonic = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ; Operands . erase ( Operands . begin ( ) ) ; delete OldMnemonic ; Operands . insert ( Operands . begin ( ) , <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc ) ) ; <ISA_LIT>Operand * CCOut = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ; Operands . erase ( Operands . begin ( ) + <NUM_LIT>


<s> mode = TYPE_MODE ( type ) ; if ( TARGET_AAPCS_BASED ) return aapcs_allocate_return_reg ( mode , type , func ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , func , <NUM_LIT> ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size %


<s> bool <ISA_LIT>FrameLowering :: keepFramePointer ( const MachineFunction & MF ) const { return MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> RegEnc |= ( CURegNum & <NUM_LIT> ) << ( Idx ++ * <NUM_LIT> ) ; } assert ( ( RegEnc & <NUM_LIT> ) == RegEnc && <STR_LIT> ) ; return RegEnc


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; bool In64BitMode = DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ; if ( ! In64BitMode && VT . getScalarType ( ) == <STR_LIT> ) { ConstVecVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ; Split = true ; } EVT EltVT = ConstVecVT . getScalarType ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { bool IsUndef = Values [ i ] < <NUM_LIT> && IsMask ; SDValue OpNode = IsUndef ? DAG . getUNDEF ( EltVT ) : DAG . getConstant ( Values [ i ] , dl , EltVT ) ; Ops . push_back ( OpNode ) ; if ( Split ) Ops . push_back ( IsUndef ? DAG . getUNDEF ( EltVT ) : DAG . getConstant ( <NUM_LIT> , dl , EltVT


<s> SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , VecLd , ML -> getPassThru ( ) ) ; return DCI . CombineTo ( ML , Blend , VecLd . getValue ( <NUM_LIT> ) , true ) ; } if ( ML -> getPassThru ( ) . isUndef ( ) ) return SDValue ( ) ; if ( <STR_LIT> ( ML -> getPassThru ( ) . getNode ( ) ) ) return SDValue ( ) ; SDValue NewML = DAG . getMaskedLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getOffset ( ) , ML -> getMask ( ) , DAG . getUNDEF ( VT ) , ML ->

getMemoryVT ( ) , ML -> getMemOperand ( ) , ML -> getAddressingMode ( ) , ML -> getExtensionType ( ) ) ;


<s> if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; return EltsFromConsecutiveLoads ( VT , Elts , dl ,


<s> if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc ==


<s> void thumb1_gen_const_int_rtl ( rtx dst , HOST_WIDE_INT op1 ) { thumb1_const_rtl t ( dst ) ; thumb1_gen_const_int_1 ( t


<s> bool isFPOnlySP ( ) const { return FPOnlySP


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return LowerVectorIntUnary ( Op , DAG )


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GO , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isData ( ) && IsGlobalInSmallSection (

GO , TM , Kind ) ) return SmallDataSection ;


<s> unsigned <ISA_LIT>TargetLowering :: getSRetArgSize ( SelectionDAG & DAG , SDValue Callee ) const { const Function * CalleeFn = nullptr ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { CalleeFn = dyn_cast < Function > ( G -> getGlobal ( ) ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; const char * CalleeName = E -> getSymbol ( ) ; CalleeFn = M -> getFunction ( CalleeName ) ; if ( ! CalleeFn && isFP128ABICall ( CalleeName ) ) return <NUM_LIT> ; } if ( ! CalleeFn ) return <NUM_LIT> ; assert ( CalleeFn -> hasStructRetAttr ( ) && <STR_LIT> ) ; PointerType * Ty = cast < PointerType > ( CalleeFn ->


<s> return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) ,


<s> void addFPImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> if ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF && MEM_P ( fnaddr ) && GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == SYMBOL_REF && ! local_symbolic_operand ( XEXP ( fnaddr , <NUM_LIT> ) , VOIDmode ) ) fnaddr = gen_rtx_MEM ( QImode , construct_plt_address ( XEXP ( fnaddr , <NUM_LIT> ) ) ) ; else if ( ! ( TARGET_X32 && MEM_P ( fnaddr ) && GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == ZERO_EXTEND && GOT_memory_operand ( XEXP ( XEXP ( fnaddr , <NUM_LIT> ) , <NUM_LIT> ) , Pmode ) ) && ( sibcall ? ! sibcall_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , word_mode ) : ! call_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , word_mode ) ) ) { fnaddr = convert_to_mode ( word_mode , XEXP ( fnaddr , <NUM_LIT> ) , <NUM_LIT> ) ; fnaddr = gen_rtx_MEM ( QImode , copy_to_mode_reg ( word_mode , fnaddr ) ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; vec [ vec_len ++ ] = call ; if ( pop ) { pop = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , pop ) ; pop = gen_rtx_SET ( stack_pointer_rtx , pop ) ; vec [ vec_len ++ ] = pop ; } if ( cfun -> machine -> no_caller_saved_registers && ( ! fndecl || ( ! TREE_THIS_VOLATILE ( fndecl ) && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( fndecl ) ) ) ) ) ) { static const char ix86_call_used_regs [ ] = CALL_USED_REGISTERS ; bool is_64bit_ms_abi = ( TARGET_64BIT && ix86_function_abi ( fndecl ) == MS_ABI ) ; char c_mask = CALL_USED_REGISTERS_MASK ( is_64bit_ms_abi ) ; for ( int i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ( ix86_call_used_regs [ i ] == <NUM_LIT> || ( ix86_call_used_regs [ i ] & c_mask ) ) && ! STACK_REGNO_P ( i ) && ! MMX_REGNO_P ( i ) ) clobber_reg ( & use , gen_rtx_REG ( GET_MODE ( regno_reg_rtx [ i ] ) , i ) ) ; } else if ( TARGET_64BIT_MS_ABI && ( ! callarg2 || INTVAL ( callarg2 ) != - <NUM_LIT> ) ) { unsigned i ; for ( i = <NUM_LIT> ; i < NUM_X86_64_MS_CLOBBERED_REGS


<s> return false ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } Register CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , MCRegister :: from ( <STR_LIT> ) ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } } MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , MCRegister :: from ( <STR_LIT> ) ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Start , Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( LRDef ) ; InsertBB = LRDef -> getParent ( ) ; return true ; } } if ( ! RDA . isSafeToDefRegAt ( Start , MCRegister :: from ( <STR_LIT> ) ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent (


<s> static void rs6000_emit_madd ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx


<s> RegisterTarget < Triple :: ppc64 , true > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: ppc64le , true > Z ( getThe<ISA_LIT>64LETarget ( ) , <STR_LIT> ,


<s> VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ) return ; MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase


<s> const unsigned DoShift = ro_Wextend -> getZExtValue ( ) & <NUM_LIT> ; assert ( ! ( ro_Wextend -> getZExtValue ( ) & ~ <NUM_LIT> ) ) ; if ( DoShift != <NUM_LIT> ) return nullptr ; if ( Signed ) Offset = Builder . CreateSExt ( Offset , Base -> getType ( ) ) ; else Offset = Builder . CreateZExt ( Offset , Base -> getType ( ) ) ; return Builder . CreateAdd ( Base , Offset ) ; } case <STR_LIT> :: AddrModeIndexed8 : case <STR_LIT> :: AddrModeIndexed16 : case <STR_LIT> :: AddrModeIndexed32 : case <STR_LIT>


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI ,


<s> void <ISA_LIT>InstPrinter :: printS16ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) MI -> getOperand ( OpNo ) . getImm ( ) ; else printOperand ( MI , OpNo , STI , O


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect = <STR_LIT> ; break ; } if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget ,


<s> return ( float32_t ) __builtin_neon_vget_lanev2sf ( __a ,


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; assert ( ( ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> )

+ ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ;


<s> const MCExpr * <ISA_LIT>_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const MCSymbol * Sym , const MCValue & MV , int64_t Offset ,

MachineModuleInfo * MMI , MCStreamer & Streamer ) const {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get (

<STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ;


<s> if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> << Align << '\n' ; } else if (


<s> Inst . addOperand ( MCOperand :: CreateReg ( Mem . Base ) ) ; addExpr ( Inst ,


<s> Value * <ISA_LIT>IREmitter :: visitWrapper ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> return nds32_expand_builtin_null_ftype_reg ( CODE_FOR_unspec_volatile_isync , exp , target ) ; case NDS32_BUILTIN_ISB : emit_insn ( gen_unspec_volatile_isb ( ) ) ; return target ; case NDS32_BUILTIN_MFSR : return nds32_expand_builtin_reg_ftype_imm ( CODE_FOR_unspec_volatile_mfsr , exp , target ) ; case NDS32_BUILTIN_MFUSR : return nds32_expand_builtin_reg_ftype_imm ( CODE_FOR_unspec_volatile_mfusr , exp , target ) ; case NDS32_BUILTIN_MTSR : return nds32_expand_builtin_null_ftype_reg_imm ( CODE_FOR_unspec_volatile_mtsr , exp , target ) ; case NDS32_BUILTIN_MTUSR : return nds32_expand_builtin_null_ftype_reg_imm ( CODE_FOR_unspec_volatile_mtusr , exp , target ) ; case NDS32_BUILTIN_SETGIE_EN : emit_insn ( gen_unspec_volatile_setgie_en ( ) ) ; return target ; case NDS32_BUILTIN_SETGIE_DIS : emit_insn ( gen_unspec_volatile_setgie_dis ( ) ) ; return target ; default : gcc_unreachable ( )


<s> unsigned RotAmt = getSOImmValRotate ( Arg ) ; if ( rotr32 ( ~ <NUM_LIT> , RotAmt ) & Arg ) return


<s> SavedRegs [ SavedRegIdx ++ ] = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; StackAdjust += OffsetSize ; InstrOffset += PushInstrSize ; } else if ( Opc == MoveInstr ) { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstReg != FramePtr || SrcReg != StackPtr ) return <NUM_LIT> ; StackAdjust = <NUM_LIT> ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; SavedRegIdx = <NUM_LIT> ; InstrOffset += MoveInstrSize ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( StackSize ) return <NUM_LIT> ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != StackPtr || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return <NUM_LIT> ; StackSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) / StackDivide ; SubtractInstrIdx += InstrOffset ; ExpectEnd = true ; } } uint32_t CompactUnwindEncoding = <NUM_LIT> ; StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoAt (


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned

ExtraPredCycles , BranchProbability Probability ) const {


<s> VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( Align - <NUM_LIT> , DL , VAList . getValueType ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align , DL , VAList . getValueType ( ) ) ) ; } unsigned ArgSizeInBytes = getDataLayout ( ) -> getTypeAllocSize ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( RoundUpToAlignment ( ArgSizeInBytes , ArgSlotSizeInBytes ) , DL , VAList . getValueType ( ) ) ) ; Chain = DAG . getStore ( VAListLoad . getValue ( <NUM_LIT> ) , DL , Tmp3 , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; if ( ! Subtarget . isLittle ( ) && ArgSizeInBytes < ArgSlotSizeInBytes ) { unsigned Adjustment = ArgSlotSizeInBytes


<s> assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ) return DAG . expandVAArg ( Op . getNode ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode = <NUM_LIT> ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else


<s> } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget -> isABI_FPXX ( ) && ! Subtarget -> hasMTHC1 ( ) ) MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) && MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) -> getGlobalIdentifier ( ) == <STR_LIT> ) emitMCountABI ( MI , MBB , MF ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isMCSymbol ( ) && MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) -> getName ( ) == <STR_LIT> ) emitMCountABI ( MI ,


<s> return ( __m64 ) __builtin_arm_wsubbss ( ( __v8qi )


<s> rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) ) return false ; REAL_VALUE_TYPE r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst0 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconst2 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconsthalf ) ) asm_fprintf ( f , <STR_LIT> ) ; else { const int buf_size


<s> if ( VT == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Ty , Alignment , AddressSpace , CostKind ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( auto * VTy = dyn_cast < ScalableVectorType > ( Ty ) ) if ( VTy -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; if ( CostKind == TTI :: TCK_CodeSize || CostKind == TTI :: TCK_SizeAndLatency ) return LT . first ; if ( CostKind != TTI :: TCK_RecipThroughput ) return <NUM_LIT> ; if ( ST -> isMisaligned128StoreSlow ( ) && Opcode == Instruction :: Store && LT . second . is128BitVector ( ) && ( ! Alignment || * Alignment < Align ( <NUM_LIT> ) ) ) { const int AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( useNeonVector ( Ty ) && Ty -> getScalarSizeInBits ( )

!= LT . second . getScalarSizeInBits ( ) ) {


<s> extern __inline __m256d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_i32gather_pd ( double const * base , __m128i index , const int scale ) { __v4df zero = _mm256_setzero_pd ( ) ; __v4df mask = _mm256_cmp_pd ( zero , zero , _CMP_EQ_OQ


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : { Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ShiftReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ShiftTy = MRI . getType ( ShiftReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy . isVector ( ) ) return false ; assert ( ! ShiftTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) != <NUM_LIT> || ShiftTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; auto * AmtMI = MRI . getVRegDef ( ShiftReg ) ; assert ( AmtMI && <STR_LIT> ) ; if ( AmtMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { MachineIRBuilder MIB ( I ) ; auto Trunc = MIB . buildInstr ( TargetOpcode :: COPY , { SrcTy } , { } ) . addReg ( ShiftReg , <NUM_LIT> , <STR_LIT> ) ; MRI . setRegBank ( Trunc . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( Trunc . getReg ( <NUM_LIT> ) ) ; } return true ; } case TargetOpcode :: G_STORE : return contractCrossBankCopyIntoStore ( I , MRI ) ; case TargetOpcode :: G_PTR_ADD : return convertPtrAddToAdd ( I , MRI ) ; case TargetOpcode :: G_LOAD : { Register DstReg = I . getOperand ( <NUM_LIT> )


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( TargetMachine & TM ) : TargetLowering ( TM , new TargetLoweringObjectFileELF ( ) ) { addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutOps [ ] = { OutLo , OutHi } ; return DAG . getMergeValues ( OutOps , <NUM_LIT>


<s> static MCDisassembler * create<ISA_LIT>elDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext &


<s> switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , get ( LoadOp ) , DestReg ) ; NewMI . addFrameIndex ( FrameIdx )


<s> int imm = Val & <NUM_LIT> ; if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const

TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> static inline unsigned char getAM5Offset


<s> return hasCMOV ( ) || hasSSE1 ( ) ||


<s> void addInstruction ( TagStoreInstr I ) { assert ( ( TagStores . empty ( ) || TagStores . back ( ) . Offset + TagStores . back ( ) . Size == I .


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegsViaCopy ( const MachineFunction * MF ) const { assert ( MF && <STR_LIT>


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) !=

CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ;


<s> return ( uint8x16_t ) __builtin_aarch64_rsubhn2v8hi ( ( int8x8_t ) __a , ( int16x8_t ) __b , (


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) , OpFlag ) ; SDLoc DL ( JT ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy


<s> unsigned <ISA_LIT>CodeEmitter :: getBranchTargetOpValueMM ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable ( <STR_LIT>


<s> bool nds32_use_load_post_increment ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; Vec = Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( )


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum , <NUM_LIT>


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MIPeepholeOptPass


<s> bool <ISA_LIT>AsmParser :: parseDirectiveLtorg ( SMLoc L


<s> SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC , DAG ) ) { SDValue Cond = DAG . getConstant ( CC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) ,

N -> getOperand ( <NUM_LIT> ) , Cond , Flags ) ;


<s> Value * HandlerI8 = Builder . CreateBitCast ( Handler , Builder . getInt8PtrTy ( ) ) ; Builder . CreateStore ( HandlerI8 , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ; Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Value * Next = Builder . CreateLoad ( LinkTy -> getPointerTo ( ) , FSZero ) ; Builder . CreateStore ( Next , Builder . CreateStructGEP ( LinkTy


<s> MachineOperand & brA = brInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & brB = brInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & andA = andInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & andB = andInstr -> getOperand ( <NUM_LIT> ) ; if ( andB . isReg ( ) ) { brA . ChangeToRegister ( andA . getReg ( ) , andA . isDef ( ) , andA . isImplicit ( ) , andA . isKill ( ) , andA . isDead ( ) , andA . isUndef ( ) , andA . isDebug ( ) ) ; brB . ChangeToRegister ( andB . getReg ( ) , andB . isDef ( ) , andB . isImplicit ( ) , andB . isKill ( ) , andB . isDead ( ) , andB . isUndef ( ) , andB . isDebug ( ) ) ; return true ; } else if ( andB .


<s> mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld ::

The<ISA_LIT>Target , mcld :: create<ISA_LIT>LDBackend ) ;


<s> ReverseIter End = MBB -> rend ( ) ; ReverseIter Br = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; if ( ( Br != End ) && ! Br -> isIndirectBranch ( ) && ( Br -> isConditionalBranch ( ) || ( Br -> isUnconditionalBranch ( )

&& IsPIC ) ) ) MBBInfos [ I ] . Br = & * ( ++ Br ) . base ( ) ;


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode


<s> unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; case <STR_LIT> : { DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; if ( KnownZero == <NUM_LIT> && KnownOne == <NUM_LIT>


<s> if ( ! Src0Reg ) return false ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( SrcVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg

( Src0Reg ) . addReg ( Src1Reg ) . addReg ( ZReg ) ;


<s> inline unsigned rotl32 ( unsigned Val , unsigned Amt ) { assert ( Amt < <NUM_LIT> && <STR_LIT> ) ; return ( Val << Amt ) | ( Val >> ( ( <NUM_LIT> - Amt


<s> static void aarch64_set_current_function ( tree fndecl ) { if ( ! fndecl || fndecl == aarch64_previous_fndecl ) return ; tree old_tree = ( aarch64_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( aarch64_previous_fndecl ) : NULL_TREE ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl )


<s> unsigned HOST_WIDE_INT mask = <NUM_LIT> ; for ( unsigned int shift = <NUM_LIT> ; shift < precision ; shift += <NUM_LIT>


<s> int64_t Shift = Bits - <NUM_LIT> ; int64_t MinVal = ( int64_t ( <NUM_LIT> ) << Shift ) * - Scale ; int64_t MaxVal = ( ( int64_t ( <NUM_LIT> ) << Shift ) - <NUM_LIT> )


<s> tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( <NUM_LIT> , tmp ) ) ; } return


<s> SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N )


<s> bool <ISA_LIT>InstrInfo :: copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const TargetRegisterClass * SrcRC ) const { if ( DestRC != SrcRC ) { return false ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI


<s> return ( int64x1_t ) { vcvtd_s64_f64 ( __a


<s> auto LookupByName = [ ] ( StringRef N ) { if ( IsSVEPrefetch ) { if ( auto Res = <STR_LIT> ( N ) ) return Optional < unsigned > ( Res -> Encoding ) ; } else if ( auto Res = <STR_LIT> ( N ) ) return Optional < unsigned > ( Res -> Encoding ) ; return Optional < unsigned > ( ) ; } ; auto LookupByEncoding = [ ] ( unsigned E ) { if ( IsSVEPrefetch ) { if ( auto Res = <STR_LIT> ( E ) ) return Optional < StringRef > ( Res -> Name ) ; } else if ( auto Res = <STR_LIT> ( E ) ) return Optional < StringRef > ( Res -> Name ) ; return Optional < StringRef > ( ) ; } ; unsigned MaxVal = IsSVEPrefetch ?


<s> assert ( ! Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , Op , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant (

<NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) , Align ( <NUM_LIT> ) , false , true , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> cmp_op1 = tmp ; new_code = swap_condition ( new_code ) ; break ; case UNORDERED : case LT : case LE : case EQ : break ; case ORDERED : if ( mode == SFmode ) emit_insn ( gen_cmpsf_un ( operands [ <NUM_LIT> ] , cmp_op0 , cmp_op1 ) ) ; else emit_insn ( gen_cmpdf_un ( operands [ <NUM_LIT> ] , cmp_op0 , cmp_op1 ) ) ; emit_insn ( gen_xorsi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT>


<s> static MCOperand create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VariantKind Kind , MCSymbol * Sym , MCContext & OutContext ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Sym , OutContext ) ; const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: create ( Kind ,


<s> Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Mem


<s> S = MCDisassembler :: SoftFail ; } if ( mask == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( pred & <NUM_LIT> ) { unsigned LowBit = mask & - mask ; unsigned BitsAboveLowBit = <NUM_LIT> & ( - LowBit << <NUM_LIT> ) ; mask ^=


<s> void <ISA_LIT>ConstantPoolValue :: dump ( ) const { errs ( ) << <STR_LIT>


<s> return __builtin_aarch64_reduc_smax_scal_v2df ( a


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target


<s> if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask


<s> default : Inst . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Res . setOpcode ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : unsigned opcode ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) opcode = Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else opcode = Inst . getOpcode ( ) == <STR_LIT> ?


<s> if ( MBBI == MBB . begin ( ) ) return ; MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes -= PI -> getOperand (


<s> for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand (

<NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> return MI . getOperand ( OpNo ) . getReg (


<s> MaskValue = <NUM_LIT> ; unsigned NumElems = BuildVector -> getNumOperands ( ) ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; if ( NumLanes > <NUM_LIT> ) return false ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { SDValue EltCond = BuildVector -> getOperand ( i ) ; SDValue SndLaneEltCond = ( NumLanes == <NUM_LIT> ) ? BuildVector -> getOperand ( i + NumElemsInLane ) : EltCond ; int Lane1Cond = - <NUM_LIT> , Lane2Cond = - <NUM_LIT> ; if ( isa < ConstantSDNode > ( EltCond ) ) Lane1Cond = ! isNullConstant ( EltCond ) ; if ( isa < ConstantSDNode > ( SndLaneEltCond ) ) Lane2Cond = ! isNullConstant ( SndLaneEltCond ) ; unsigned LaneMask = <NUM_LIT> ; if ( Lane1Cond == Lane2Cond || Lane2Cond < <NUM_LIT> ) LaneMask = ! Lane1Cond << i ; else if ( Lane1Cond < <NUM_LIT> ) LaneMask = ! Lane2Cond << i ; else return false ; MaskValue |= LaneMask ; if ( NumLanes == <NUM_LIT> ) MaskValue |= LaneMask << NumElemsInLane ; } return true


<s> rtx sh_movt_set_dest ( const_rtx pat ) { return GET_CODE ( pat ) == SET && arith_reg_dest ( XEXP ( pat , <NUM_LIT> ) , SImode ) && t_reg_operand ( XEXP ( pat , <NUM_LIT> ) , VOIDmode ) ?


<s> if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_cc_di


<s> bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; switch ( RC -> getSize ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? <STR_LIT>


<s> void SetInitialFrameRegister ( unsigned


<s> unsigned NumNOPBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( int32_t ) ID == ID && <STR_LIT> ) ; SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , <NUM_LIT> ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end


<s> AM . Disp = Offset ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || ( ( M == CodeModel :: Small || M == CodeModel :: Kernel ) && TM . getRelocationModel ( ) == Reloc :: Static ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol


<s> mips_multi_members [ i ] . operands [ op ]


<s> if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = dyn_cast_or_null < const MCSectionELF >


<s> if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } else { return


<s> return ( __m512i ) __builtin_ia32_gathersiv16si ( ( __v16si ) __v1_old , __addr , (


<s> bool can_be_rotated_to_negative_15bits ( HOST_WIDE_INT c ) { int rot = <NUM_LIT> ; bool res = can_be_rotated_to_lowbits ( ~ c , <NUM_LIT> , & rot ) ; return res && rot >


<s> HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasVNNI = false ; HasBITALG = false ; HasSHA = false ; HasPREFETCHWT1 = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasCLDEMOTE = false ; HasMOVDIRI = false ; HasMOVDIR64B = false ; HasPTWRITE = false ; HasMPX = false ; HasSHSTK = false ; HasSGX = false ; HasPCONFIG = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; HasWBNOINVD = false ; HasRDPID = false ; HasWAITPKG = false ; UseRetpoline = false ; UseRetpolineExternalThunk = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasPOPCNTFalseDeps = false ; HasLZCNTFalseDeps = false ; HasFastVariableShuffle = false ; HasFastPartialYMMorZMMWrite = false ; HasFast11ByteNOP = false ; HasFast15ByteNOP = false ; HasFastGather = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasMacroFusion =


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5S2Operand ( const MCInst * MI , unsigned Op , raw_ostream &


<s> if ( mode == SImode && code == ROTATE ) return ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> ) ; if ( ne > nb ) return false ; if ( sh < <NUM_LIT> ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> && ! ( code == LSHIFTRT && nb >= <NUM_LIT> - sh ) ) return true ; if ( code == LSHIFTRT ) sh = <NUM_LIT> - sh ; if ( nb == <NUM_LIT> || ne == <NUM_LIT> || ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( MI . definesRegister ( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } for ( int i = <NUM_LIT> , e = MI . getDesc ( ) . getNumDefs ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) && MO . isDef ( ) ) { assert ( ! MO . isImplicit ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ; MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( i ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( implicitlyDefinesOverlappingReg ( MO . getReg ( ) , MI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } unsigned


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) return make_unique < TargetLoweringObjectFileMachO > ( ) ; if ( TT . isOSWindows ( ) ) return make_unique < TargetLoweringObjectFileCOFF > ( ) ; return make_unique < <ISA_LIT>ElfTargetObjectFile > ( )


<s> df_ref ref ; for ( ref = DF_INSN_INFO_DEFS ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) )

if ( DF_REF_REGNO ( ref ) == regno ) return true ;


<s> return ( __m128i ) __builtin_ia32_psrldi128 ( ( __v4si


<s> Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) /


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString (


<s> LRU . addLiveOuts ( MBB ) ; std :: for_each ( MBB . rbegin ( ) , MBB . rend ( ) , [ & LRU ] ( MachineInstr & MI ) { LRU . accumulate ( MI ) ; } ) ; if ( ! LRU . available ( <STR_LIT> ) ) Flags |= MachineOutlinerMBBFlags ::


<s> HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP =


<s> void ELF<ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue

& Target , uint64_t & Value , bool & IsResolved ) {


<s> while ( <NUM_LIT> ) { if ( * sym == '*' ) sym ++ ; else if ( * sym == '@' && sym [ <NUM_LIT> ]


<s> Edges [ Graph -> getEdgeIndex ( E ) ] = Graph -> getNodeIndex ( * E . getDest ( ) ) ; EdgeValues [ Graph -> getEdgeIndex ( E ) ] = E . getValue ( ) ; } OptimizeCut ( Nodes . get ( ) , Graph -> nodes_size ( ) , Edges . get ( ) , EdgeValues . get ( ) , EdgeCuts . get ( ) , Graph -> edges_size ( ) ) ; for ( int I = <NUM_LIT> ; I < Graph -> edges_size ( ) ; ++ I ) if ( EdgeCuts [ I ] ) CutEdges . set ( I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CutEdges . count ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; FencesInserted += insertFences ( MF , * Graph , CutEdges ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> return __arm_vcmlaq_rot180_f32 ( __a ,


<s> Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if ( restrict_addressing_modes_for_nacl ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ,


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || TargetRegisterInfo :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Ops ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( ) ) Op =


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void ) Done


<s> Value * <ISA_LIT>IREmitter :: visitFMSTAT ( const SDNode * N


<s> bool J2 = ( Val & <NUM_LIT> ) ; if ( I ^ J1 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; if ( I ^ J2 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; return


<s> void printUImm12Offset ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI ,


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm12OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> if ( Shift . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) || ! Shift . hasOneUse ( ) ) return true ; int ScaleLog = <NUM_LIT> - Shift . getConstantOperandVal ( <NUM_LIT> ) ; if ( ScaleLog <= <NUM_LIT> || ScaleLog >= <NUM_LIT> || Mask != ( <NUM_LIT> << ScaleLog ) ) return true ; MVT VT = N . getSimpleValueType ( ) ; SDLoc DL ( N ) ; SDValue Eight = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue NewMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , DL , VT , X , Eight ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , Srl , NewMask ) ; SDValue ShlCount = DAG . getConstant ( ScaleLog , DL , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , And , ShlCount ) ; insertDAGNode ( DAG , N , Eight ) ; insertDAGNode ( DAG , N , Srl ) ; insertDAGNode ( DAG , N , NewMask ) ; insertDAGNode ( DAG , N , And ) ; insertDAGNode ( DAG , N , ShlCount ) ; insertDAGNode ( DAG , N , Shl ) ; DAG . ReplaceAllUsesWith ( N ,


<s> return create ( Kind , create ( CEK_None , create ( CEK_GPREL