<s> if ( t_reg_operand ( ops [ i ] , VOIDmode ) || negt_reg_operand ( ops [ i ] , VOIDmode ) ) op_is_t_count ++ ; else { set_of_reg op_set = sh_find_set_of_reg ( ops [ i ] , insn , prev_nonnote_insn_bb ) ; if ( op_set . set_src == NULL_RTX ) continue ; if ( t_reg_operand ( op_set . set_src , VOIDmode ) || negt_reg_operand ( op_set . set_src , VOIDmode ) || sh_is_logical_t_store_expr ( op_set . set_src , op_set . insn ) ) op_is_t_count ++ ; } } return op_is_t_count ==


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero (


<s> } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned IgnoredFrameReg ; int64_t Offset = getFrameIndexReference ( MF , Save . getFrameIdx ( ) , IgnoredFrameReg ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , SPOffsetFromCFA + Offset ) ) ; CFIIndexes . push_back (


<s> bool FoldedLoad = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; bool FoldedStore = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; if ( UnfoldLoad && ! FoldedLoad ) return <NUM_LIT> ; if ( UnfoldStore && ! FoldedStore ) return <NUM_LIT> ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second &


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_<ISA_LIT>_SaveList


<s> SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . getOpcode ( ) == <STR_LIT> ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; HasConstElts = true ; } if ( SplatIdx == - <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else Imm = DAG . getUNDEF ( VT ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) DstVec = DAG . getBitcast ( VT , Imm ) ; else { SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } for ( unsigned i = <NUM_LIT> , e = NonConstIdx . size ( ) ; i != e ; ++ i ) { unsigned InsertIdx = NonConstIdx [


<s> State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State = IES_LT ; IC . pushOperator


<s> return ( __m128 ) __builtin_ia32_divps ( ( __v4sf


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue BAGOTOffset = DAG . getTargetBlockAddress ( BA , ValTy , <NUM_LIT> , GOTFlag ) ; BAGOTOffset = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , BAGOTOffset ) ; SDValue BALOOffset = DAG . getTargetBlockAddress ( BA , ValTy , <NUM_LIT> , OFSTFlag ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , BAGOTOffset

, MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> return false ; case MEK_LO : case MEK_CALL_LO16 : AbsVal = SignExtend64 < <NUM_LIT> > ( AbsVal ) ; break ; case MEK_CALL_HI16 : case MEK_HI : AbsVal = SignExtend64 < <NUM_LIT> > ( ( AbsVal + <NUM_LIT> ) >> <NUM_LIT> ) ; break ; case MEK_HIGHER : AbsVal = SignExtend64 < <NUM_LIT> > ( ( AbsVal + <NUM_LIT> ) >> <NUM_LIT> ) ; break ; case MEK_HIGHEST : AbsVal = SignExtend64 < <NUM_LIT> > ( ( AbsVal + <NUM_LIT> ) >> <NUM_LIT> ) ; break ; case MEK_NEG : AbsVal = - AbsVal ; break ; } Res = MCValue :: get ( AbsVal ) ; return true ; } Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) &&


<s> return ix86_dirflag_mode_needed ( insn ) ; case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR


<s> } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocOption ( Val , S , E ) ) ; return MatchOperand_Success


<s> return ( __m256i ) __builtin_ia32_punpcklqdq256_mask ( ( __v4di ) __A , ( __v4di ) __B , ( __v4di ) _mm256_setzero_si256 ( ) ,


<s> case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECREDUCE ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_LOAD_SUB ( Op


<s> if ( ! VT1 . isScalarInteger ( ) || ! VT2 . isScalarInteger (


) ) _mm_srai_epi64 ( __m128i __A , const int __imm ) {


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream &


<s> bool <ISA_LIT>DagToDagISel :: SelectAddr ( SDNode * Parent , SDValue Addr , SDValue & Base , SDValue & Offset ) { return true


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( const Instruction * I ) { const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; const Value * Val = S -> getValueOperand ( ) ; const Value * Ptr = S -> getPointerOperand ( ) ; MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT , true ) ) return false ; unsigned Alignment = S -> getAlignment ( ) ; unsigned ABIAlignment = DL . getABITypeAlignment ( Val -> getType ( ) ) ; if ( Alignment == <NUM_LIT> ) Alignment = ABIAlignment ; bool Aligned = Alignment >=


<s> static void ready_reorder ( rtx * ready , int nready ) { SCHED_REORDER ( ready , nready


<s> const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = <STR_LIT> ( Desc . TSFlags ) ; if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( )


<s> virtual const char * getPassName ( )


<s> AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT>


<s> bool <ISA_LIT>BaseRegisterInfo :: canSimplifyCallFramePseudos ( MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects (


<s> Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset =


<s> Iter Filler :: replaceWithCompactBranch ( MachineBasicBlock & MBB , Iter Branch , DebugLoc DL ) { const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned NewOpcode = TII -> getEquivalentCompactForm ( Branch ) ; Branch = TII -> genInstrWithNewOpc ( NewOpcode , Branch ) ; std :: next ( Branch ) -> eraseFromParent


<s> assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget . isTarget64BitLP64 ( ) ? <STR_LIT>


<s> unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ; if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , DemandedElts , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs ,


<s> auto Info = std :: find_if ( Insts . begin ( ) , Insts . end ( ) , [ & ] ( InstInfo & Info ) { return Info . I == I ; } ) ; assert ( Info != Insts . end ( ) && <STR_LIT> ) ; Info -> SPAdjust += ExtraBytes


<s> if ( ix86_function_type_abi ( fntype ) == MS_ABI ) { size = int_size_in_bytes ( type ) ; if ( ( ! type || VECTOR_INTEGER_TYPE_P ( type ) || INTEGRAL_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( SCALAR_INT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) && ! COMPLEX_MODE_P ( mode ) && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || size == <NUM_LIT> ) ) return false ; return size != <NUM_LIT> && size != <NUM_LIT> && size != <NUM_LIT> && size != <NUM_LIT> ; } else { int needed_intregs , needed_sseregs ; return examine_argument ( mode , type , <NUM_LIT> , & needed_intregs , & needed_sseregs ) ; } } else { if ( mode == BLKmode ) return true ; size = int_size_in_bytes ( type ) ; if ( MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P ( type ) && size <= <NUM_LIT> ) return false ; if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { if ( size < <NUM_LIT> ) return false ; if ( size == <NUM_LIT> ) return TARGET_VECT8_RETURNS || ! TARGET_MMX ; if ( size == <NUM_LIT> ) return ! TARGET_SSE ; if ( size == <NUM_LIT> ) return ! TARGET_AVX ; if ( size == <NUM_LIT> ) return ! TARGET_AVX512F ; } if ( mode == XFmode ) return false ; if ( size > <NUM_LIT> ) return true ; gcc_assert ( mode != OImode ) ; return false


<s> uint32_t Banked = MI -> getOperand ( OpNum ) . getImm ( ) ; uint32_t R = ( Banked & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t SysM = Banked & <NUM_LIT> ; if ( R ) { O << <STR_LIT> ; switch ( SysM ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT>


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &


<s> MachineInstr & MI = * MBBI ; NextMBBI = std :: next ( MBBI ) ; if ( ! MI . mayLoad ( ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; bool AllDefsAreGPR = llvm :: all_of ( MI . defs ( ) , [ & ] ( MachineOperand & Op ) { return Op . isReg ( ) && ( <STR_LIT> . contains ( Op . getReg ( ) ) || <STR_LIT> . contains ( Op . getReg ( ) ) ) ; } ) ; bool HardenLoadedData = AllDefsAreGPR ; bool HardenAddressLoadedFrom = ! HardenLoadedData ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsAlreadyMasked . reset ( * AI ) ; if ( HardenLoadedData ) for ( auto Def : MI . defs ( ) ) { if ( Def . isDead ( ) ) continue ; Modified |= makeGPRSpeculationSafe ( MBB , NextMBBI , MI , Def . getReg ( ) ) ; } if ( HardenAddressLoadedFrom ) for ( auto Use : MI . uses ( ) ) { if ( ! Use . isReg


<s> if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; MachineInstrBuilder MIB ; if ( CM == CodeModel :: Small ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( ) , <NUM_LIT> ) ; MIB . addReg ( Reg ) ; } else return false ; } else { unsigned CallReg = <NUM_LIT> ; if ( Symbol ) { unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> ) ; CallReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , CallReg ) . addReg ( ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( Addr . getGlobalValue ( ) )

CallReg = materializeGV ( Addr . getGlobalValue ( ) ) ;


<s> unsigned getGPRCalleeSavedArea2Size (


<s> unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc )

, GlobalBaseReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ;


<s> unsigned Dummy ; if ( isFrameStoreOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy


<s> int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( PFI -> usesPICBase ( ) ) { HasGPSaveArea = true ; int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -=


<s> MVT T = Node -> getValueType ( <NUM_LIT> ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( T == <STR_LIT> && <STR_LIT> ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG


<s> NumElts = VT . getVectorNumElements ( ) ; } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; NumElts = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , Alignment ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; Operand = DAG . getNode ( <STR_LIT> , dl , LogicVT , Operand ) ; SDValue LogicNode = DAG . getNode ( LogicOp , dl ,


<s> if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( TLI . getTypeAction ( * DAG . getContext ( ) , StoreVT ) == TargetLowering :: TypeWidenVector && <STR_LIT> ) ; EVT WideVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , StoreVT ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> ( StVT , <NUM_LIT> ) ; StoredVal = DAG . getBitcast ( CastVT , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , StVT , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } assert ( Subtarget . hasSSE1 ( ) && <STR_LIT> ) ; SDVTList Tys = DAG . getVTList


<s> return ( poly64x1_t ) __builtin_neon_vset_lanedi ( ( __builtin_neon_di ) __a , (


<s> MEM_READONLY_P ( mem ) = <NUM_LIT> ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; insn = emit_insn ( pat ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == cfun -> machine -> pic_reg ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) { gcc_assert ( CONST_INT_P ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; return orig ; } if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg ) ; if ( CONST_INT_P ( offset ) ) { if ( ! arm_legitimate_index_p ( mode , offset , SET , <NUM_LIT> ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; offset = force_reg ( Pmode , offset ) ; } if ( CONST_INT_P ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; } if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ( GET_MODE_CLASS ( mode ) == MODE_INT || TARGET_SOFT_FLOAT ) ) { emit_insn ( gen_addsi3 ( reg , base , offset ) ) ; return reg ; } return gen_rtx_PLUS ( Pmode , base


<s> else if ( ! Subtarget . has<ISA_LIT>64 ( ) ) return CSR_O32_RegMask ; else if ( Subtarget . isABI_N32


<s> unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return <NUM_LIT> ; if ( Count == <NUM_LIT> ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; if ( VT == <STR_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) { auto * MaskN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( MaskN -> getZExtValue ( ) != RISBG . Mask ) { SDValue NewMask = CurDAG -> getConstant ( RISBG . Mask , VT ) ; N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewMask ) ; return SelectCode ( N ) ; } return <NUM_LIT> ; } } unsigned Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget . hasHighWord ( ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [


<s> if ( Vector ) { if ( ST -> hasNEON ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , Flags , MFI . getObjectSize ( FI ) , MFI .


<s> const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << '[' ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; O << ']' << markup ( <STR_LIT> ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || ( op == <STR_LIT> ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs << markup ( <STR_LIT> ) ; } O << ']' << markup ( <STR_LIT>


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _subborrow_u32 ( unsigned char __CF , unsigned int __X , unsigned int __Y , unsigned int * __P ) { return __builtin_ia32_sbb_u32 ( __CF , __X , __Y


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> void RecordRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target ,


<s> if ( TREE_THIS_VOLATILE ( cfun -> decl ) && ! ( m -> frame . nregs || m -> frame . nsseregs || frame_pointer_needed ) ) { rtx dummy_reg = gen_rtx_REG ( word_mode , TARGET_64BIT ? AX_REG : SI_REG ) ; rtx_insn * insn_push = emit_insn ( gen_push ( dummy_reg ) ) ; rtx_insn * insn_pop = emit_insn ( gen_pop ( dummy_reg ) ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) { m -> fs . cfa_offset -= UNITS_PER_WORD ; rtx x = plus_constant ( Pmode , stack_pointer_rtx , - UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn_push , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn_push ) = <NUM_LIT> ; x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn_pop , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn_pop ) = <NUM_LIT> ; } emit_insn ( gen_blockage ( ) ) ; } if ( size < ( <NUM_LIT> << PARAM_VALUE ( PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE ) ) ) { pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( NO_PROBE_SMALL_FRAME , true ) ; return ; } HOST_WIDE_INT probe_interval = get_probe_interval ( ) ; if ( size <= <NUM_LIT> * probe_interval ) { HOST_WIDE_INT i ; for ( i = probe_interval ; i <= size ; i += probe_interval ) { rtx insn = pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - probe_interval ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_stack_probe ( stack_pointer_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } HOST_WIDE_INT residual = ( i - probe_interval - size ) ; if ( residual ) pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( residual ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( PROBE_INLINE , residual != <NUM_LIT> ) ; } else { gcc_assert ( int_registers_saved ) ; struct scratch_reg


<s> bool isMoveWideMovAlias ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int UImm16 ,


<s> SelectRoot ( * CurDAG ) ; CurDAG -> RemoveDeadNodes ( )


<s> if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { int local_regparm , globals = <NUM_LIT> , regno ; for ( local_regparm = <NUM_LIT> ; local_regparm < REGPARM_MAX ; local_regparm ++ ) if ( fixed_regs [ local_regparm ] ) break ; if ( local_regparm == <NUM_LIT> && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = <NUM_LIT> ; if ( flag_split_stack ) { if ( local_regparm == <NUM_LIT> ) local_regparm = <NUM_LIT> ; else if ( local_regparm == <NUM_LIT> && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = <NUM_LIT> ; } for ( regno = AX_REG ; regno <= DI_REG ; regno ++ ) if ( fixed_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : <NUM_LIT> ; if ( local_regparm > regparm ) regparm =


<s> const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { unsigned ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( MRI . getType ( DstReg ) , DstRegBank ) ; if ( SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> && SrcSize > DstSize && TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { const TargetRegisterClass * SrcRC = getRegClassFromGRPhysReg ( SrcReg ) ; if ( DstRC != SrcRC


<s> assert ( ( VT . getSizeInBits ( ) != <NUM_LIT> || Is1BitVector ) && <STR_LIT> ) ; bool V1IsUndef = V1 . isUndef ( ) ; bool V2IsUndef = V2 . isUndef ( ) ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , DL , V1 , V2 , NewMask ) ; } int MaskUpperLimit = Mask . size ( ) * ( V2IsUndef ? <NUM_LIT> : <NUM_LIT> ) ; ( void ) MaskUpperLimit ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return - <NUM_LIT> <= M && M < MaskUpperLimit ; } ) && <STR_LIT> ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; if ( Zeroable . all ( ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( Mask , WidenedMask ) ) { MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; MVT NewVT = <STR_LIT> ( NewEltVT , VT . getVectorNumElements (


<s> if ( TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX && ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) && rclass != NO_REGS && INTEGER_CLASS_P ( rclass ) ) return ALL_SSE_REGS ; return NO_REGS


_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> constant = ( med_defect + max_defect ) * <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ; if ( constant < - <NUM_LIT> || constant > <NUM_LIT> ) abort ( ) ; constants [ i ] = constant ; calc_defect ( x_low , constant , factor ) ; calc_defect ( x_med , constant , factor ) ; calc_defect ( x_high , constant , factor ) ; } printf ( <STR_LIT> ) ; printf ( <STR_LIT> , BIAS ) ; printf ( <STR_LIT> , max_defect , max_defect_x ) ; printf ( <STR_LIT> , min_defect , min_defect_x ) ; printf ( <STR_LIT> , max_defect2 , max_defect2_x ) ; printf ( <STR_LIT> , min_defect2 , min_defect2_x ) ; printf ( <STR_LIT> , max_defect3 , max_defect3_val , max_defect3_x ) ; printf ( <STR_LIT> , min_defect3 , min_defect3_val , min_defect3_x ) ; printf ( <STR_LIT> , calc_defect ( <NUM_LIT> , constants [ <NUM_LIT> ] , factors [ <NUM_LIT> ] ) ) ; printf ( <STR_LIT> , calc_defect ( - <NUM_LIT> , constants [ steps ] , factors [


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( Imm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( Imm == <NUM_LIT> ) Inst . addOperand ( MCOperand


<s> else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_LDBL128 ) == RS6000_BTM_LDBL128 ) { if ( ! TARGET_HARD_FLOAT ) error ( <STR_LIT> , name , <STR_LIT> ) ; else error ( <STR_LIT> , name , TARGET_IEEEQUAD ? <STR_LIT> : <STR_LIT> ) ; } else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128_HW ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128 ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64 ) ) == ( RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64 ) ) error ( <STR_LIT> <STR_LIT> , name , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT> , name


<s> static const char * abi_str ( struct loongarch_abi abi ) { if ( abi . ext == ABI_EXT_BASE ) return ( const char * ) obstack_copy0 ( & msg_obstack , loongarch_abi_base_strings [ abi . base ] ,

strlen ( loongarch_abi_base_strings [ abi . base ] ) ) ;


<s> uint32_t getAddrMode2OpValue ( const MachineInstr & MI , unsigned OpIdx ) const { return


<s> vabdl_s32 ( int32x2_t a , int32x2_t b ) { int64x2_t result


<s> LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return DAG . getIntPtrConstant ( <NUM_LIT> * <NUM_LIT> ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_EXIT ( const MachineInstr & MI ) { EmitSled ( MI , SledKind :: FUNCTION_EXIT


<s> if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , N1 , CurDAG -> getConstant


<s> cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( mode == SFmode ) { if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } else if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } } } if ( TARGET_POWERPC64 && size == <NUM_LIT> ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( ! TARGET_POWERPC64 && size == <NUM_LIT> ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && ! altivec_p ) { cost = <NUM_LIT> ; icode = reg_addr [ mode ] . reload_fpr_gpr ; } } if ( icode != CODE_FOR_nothing ) { ret = true ; if ( sri ) { sri -> icode = icode ; sri -> extra_cost = cost ; } } return ret


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( IsELF64 , OSABI , EMachine ) ; return createELFObjectWriter ( MOTW ,


<s> auto * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; FuncInfo . EHRegNode = RegNode ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , FuncInfo


<s> static void aapcs_layout_arg ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type , bool named ) { int nregs , nregs2 ; int ncrn ; if ( pcum -> aapcs_arg_processed ) return ; pcum -> aapcs_arg_processed = true ; if ( ! named ) return ; if ( pcum -> pcs_variant != ARM_PCS_AAPCS ) { int slot = aapcs_select_call_coproc ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = slot ; if ( slot >= <NUM_LIT> ) { if ( ! pcum -> aapcs_cprc_failed [ slot ] ) { if ( aapcs_cp_arg_layout [ slot ] . allocate ( pcum , mode , type ) ) return ; pcum -> aapcs_cprc_failed [


<s> iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( GET_MODE ( reg ) , dwarf_mem


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) && ! Subtarget . isOSWindows ( ) ) return false ; return true


<s> OS << '$' << StringRef ( getRegisterName ( RegNo


<s> case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitEHSjLjLongJmp ( MachineInstr * MI , MachineBasicBlock * MBB ) const { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF


<s> if ( profiling ) { goto out ; } profiling ++ ; frompcindex = ( unsigned short * ) ( ( long ) frompcindex - ( long ) s_lowpc ) ; if ( ( unsigned long ) frompcindex > s_textsize ) { goto done ; } frompcindex = & froms [ ( ( long ) frompcindex ) / ( HASHFRACTION * sizeof ( * froms ) ) ] ; toindex = * frompcindex ; if ( toindex == <NUM_LIT> ) { toindex = ++ tos [ <NUM_LIT> ] . link ; if ( toindex >= tolimit ) { goto overflow ; } * frompcindex = toindex ; top = & tos [ toindex ] ; top -> selfpc = selfpc ; top -> count = <NUM_LIT> ; top -> link = <NUM_LIT> ; goto done ; } top = & tos [ toindex ] ; if ( top -> selfpc ==


<s> unsigned ToSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned FromSz = LdVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( Mld -> getSrc0 ( ) . getOpcode ( ) != <STR_LIT> ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT


<s> void printlea32mem ( const MachineInstr * MI , unsigned OpNo ) { printLeaMemReference ( MI


<s> void <ISA_LIT>ConstantPoolValue :: print ( raw_ostream & O ) const { if ( GV ) O << GV


<s> return ( REG_P ( op0 ) && REG_P ( op1 ) && ( ( INT_REG_OK_FOR_BASE_P ( op0 , strict ) && INT_REG_OK_FOR_INDEX_P ( op1 , strict ) ) || ( INT_REG_OK_FOR_BASE_P ( op1 , strict ) &&

INT_REG_OK_FOR_INDEX_P ( op0 , strict ) ) ) ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> bool hasDivideIn<ISA_LIT>Mode ( ) const { return HasHardwareDivideIn<ISA_LIT>


<s> { MO_GOT_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PIC_BASE_OFFSET , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_TLSGD , <STR_LIT> } , { MO_TLSLD , <STR_LIT> } , { MO_TLSLDM , <STR_LIT> } , { MO_GOTTPOFF , <STR_LIT> } , { MO_INDNTPOFF , <STR_LIT> } , { MO_TPOFF , <STR_LIT> } , { MO_DTPOFF , <STR_LIT> } , { MO_NTPOFF , <STR_LIT> } , { MO_GOTNTPOFF , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_DARWIN_STUB , <STR_LIT> } , { MO_DARWIN_NONLAZY

, <STR_LIT> } , { MO_DARWIN_NONLAZY_PIC_BASE , <STR_LIT> } , { MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE , <STR_LIT> } , { MO_TLVP , <STR_LIT> } , { MO_TLVP_PIC_BASE , <STR_LIT> } , { MO_SECREL , <STR_LIT> } } ;


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( GV -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isTargetNaCl64 ( ) ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC


<s> static SDValue combineZext ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT>


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBitfield64LSLOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return ( ( <NUM_LIT> - MO . getImm ( ) ) & <NUM_LIT> ) | ( <NUM_LIT> - MO


<s> case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case


<s> stubid = get_identifier ( stubname ) ; stubdecl = build_decl ( FUNCTION_DECL , stubid , build_function_type ( void_type_node , NULL_TREE ) ) ; DECL_SECTION_NAME ( stubdecl ) = build_string ( strlen ( secname ) , secname ) ; fprintf ( asm_out_file , <STR_LIT> , ( fpret ? ( GET_MODE ( retval ) == SFmode ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) , fnname ) ; need_comma = <NUM_LIT> ; for ( f = ( unsigned int ) fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> , need_comma ? <STR_LIT> : <STR_LIT> , ( f & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; need_comma = <NUM_LIT> ; } fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_start_function ( stubdecl , stubname ) ; if ( ! FUNCTION_NAME_ALREADY_DECLARED ) { fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , stubname ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , stubname ) ; fputs ( <STR_LIT> , asm_out_file ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; mips16_fp_args ( asm_out_file , fp_code , <NUM_LIT> ) ; if ( ! fpret ) { fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , fnname ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } else { fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> , fnname ) ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( GET_MODE ( retval ) == SFmode ) fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ FP_REG_FIRST + <NUM_LIT> ] ) ; else { if ( TARGET_BIG_ENDIAN ) { fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ FP_REG_FIRST + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ FP_REG_FIRST + <NUM_LIT> ] ) ; } else { fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ FP_REG_FIRST + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ FP_REG_FIRST + <NUM_LIT> ] ) ; } } fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; ASM_DECLARE_FUNCTION_SIZE ( asm_out_file , stubname , stubdecl ) ; if ( ! FUNCTION_NAME_ALREADY_DECLARED ) { fputs ( <STR_LIT> ,


<s> static SDValue MaterializeSETB ( SDLoc DL , SDValue EFLAGS , SelectionDAG & DAG , MVT VT ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,

DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ;


<s> bool <ISA_LIT>InstructionSelector :: tryOptAndIntoCompareBranch ( MachineInstr & AndInst , bool Invert , MachineBasicBlock * DstMBB , MachineIRBuilder & MIB ) const { assert ( AndInst . getOpcode ( ) == TargetOpcode ::


<s> unsigned Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) ; ++


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout


<s> SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT


<s> if ( ! poly_int_rtx_p ( x , & offset


<s> case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasAVX2 ( ) ) { int NumElems = VT . getVectorNumElements ( ) ; SDValue Idx0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Idx1 = DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , Idx0 , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , Idx1 , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; int ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; ; } case <STR_LIT> : case <STR_LIT> : { SDValue Tmp1 = getTargetVShiftNode ( <STR_LIT> , dl , VT , Op . getOperand


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR64DecoderTable [ RegNo


<s> SDValue Imm ; SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( ( VT . is256BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> ) || ( VT . is512BitVector ( )

&& ( Op . getNumOperands ( ) == <NUM_LIT> || Op . getNumOperands ( ) == <NUM_LIT> ) ) ) ;


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT>


<s> if ( DECL_USER_ALIGN ( fndecl ) ) return ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; DECL_ALIGN ( fndecl ) = FUNCTION_BOUNDARY_P ( TREE_TARGET_OPTION


<s> return ( __m512d ) __builtin_ia32_cvtqq2pd512_mask ( ( __v8di ) __A , ( __v8df ) _mm512_setzero_pd ( ) ,


<s> vst2_u16 ( uint16_t * __a , uint16x4x2_t val ) { __builtin_aarch64_simd_oi __o ; uint16x8x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u16 ( val . val [ <NUM_LIT> ] , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u16 ( val . val [ <NUM_LIT> ] , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) temp . val


<s> tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else if ( ! caller_tree ) ret = false ; else { struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts =


<s> getMangler ( ) . getNameWithPrefix (


<s> const MachineOperand & Op2 = OpList2 [ i ] ; DEBUG ( dbgs ( ) << <STR_LIT> << Op1 << <STR_LIT> << <STR_LIT> << Op2 << <STR_LIT> ) ; if ( Op1 . isIdenticalTo ( Op2 ) ) { if ( Op1 . isReg ( ) && TargetRegisterInfo :: isPhysicalRegister ( Op1 . getReg ( ) ) && ! ( Op1 . isUse ( ) && MRI -> isConstantPhysReg ( Op1 . getReg ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( Op1 . isReg ( ) && Op2 . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Op1 . getReg ( ) ) && TargetRegisterInfo :: isVirtualRegister ( Op2 . getReg ( ) ) ) { MachineInstr * Op1Def = MRI -> getVRegDef ( Op1 . getReg ( ) ) ; MachineInstr * Op2Def = MRI -> getVRegDef ( Op2 . getReg ( ) ) ; if ( TII -> produceSameValue ( * Op1Def , * Op2Def , MRI


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } else llvm_unreachable ( <STR_LIT>


<s> printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; unsigned RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) . addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , getCRFromCRBit ( DestReg ) ) . addReg ( RegO

, RegState :: Kill ) . addReg ( getCRFromCRBit ( DestReg ) , RegState :: Implicit ) ;


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) == <NUM_LIT> && INTEGRAL_MODE_P

( from ) && INTEGRAL_MODE_P ( to ) ) return false ;


<s> return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) ,


<s> rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > <NUM_LIT> ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ; addExpr ( Inst ,


<s> void addSystemPStateFieldOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; bool


<s> inline void vec_ste ( vector unsigned int a1 , int a2 , void * a3 ) { __builtin_altivec_stvewx ( ( vector signed int ) a1 , a2 , ( void *


<s> Ops . reserve ( NumOps - <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) Ops


<s> const InstructionSelector * getInstructionSelector


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter


<s> return __builtin_loongson_psllw_u ( s , amount


<s> return createMacroFusionDAGMutation (


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedScatter ( Type * DataType , Align Alignment ) { if ( ! ST -> hasAVX512 ( ) ) return false ; return isLegalMaskedGather ( DataType , Alignment


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > <ISA_LIT>Locs ; CCState CCInfo ( CallConv , IsVarArg , MF , <ISA_LIT>Locs , Context ) ; return CCInfo . CheckReturn ( Outs ,

CCAssignFnForReturn ( CallConv , IsVarArg ) ) ;


<s> static __inline qword si_orbi ( qword a , unsigned char b ) { return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar ( b )


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR (


<s> return new <ISA_LIT>PartialReduction


<s> bool <ISA_LIT>TTIImpl :: shouldFavorBackedgeIndex ( const Loop * L ) const { if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( )


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Ctx , std :: move ( MAB ) , std :: move


<s> arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float16x8_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; enum machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ]


<s> MachineBasicBlock :: iterator <ISA_LIT>InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> )


<s> Register <ISA_LIT>FunctionInfo :: getGlobalBaseRegUnchecked ( ) const { assert ( GlobalBaseReg ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! ResNode ) ResNode = tryRISBGZero ( Node ) ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : if ( ConstantSDNode * Op2 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Value = - Op2 -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || isInt < <NUM_LIT> > ( Value ) ) { SDValue Ops [ ] = { Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( int32_t ( Value ) , VT ) } ; Node = CurDAG -> MorphNodeTo ( Node , <STR_LIT> , Node -> getVTList ( ) , Ops , array_lengthof ( Ops ) ) ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node ->


<s> return ( ( vec_int4 ) ( si_mpys ( ( qword ) ( a ) , ( qword )


<s> mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , <NUM_LIT> , par_index ) = gen_rtx_SET ( VOIDmode , mem , reg


<s> unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == <NUM_LIT> ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt


<s> if ( ST . isThumb ( ) ) Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isThumb ( ) || ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else if ( ST . isAAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return


<s> return ( uint16x8_t ) __builtin_aarch64_ld1v8hi ( ( const __builtin_aarch64_simd_hi *


<s> return __builtin_aarch64_sqdmlal_nv2si ( __a ,


<s> CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent (


<s> const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , *


<s> unsigned NumElts = VT . is64BitVector ( ) ? <NUM_LIT> : <NUM_LIT> ; while ( EltSize != VT . getScalarSizeInBits ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , DL , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; Ops . push_back ( Res ) ; EltSize *= <NUM_LIT> ; NumElts /= <NUM_LIT> ; MVT WidenVT = <STR_LIT> ( <STR_LIT> ( EltSize ) , NumElts ) ; Res = DAG . getNode ( <STR_LIT> , DL , WidenVT , Ops ) ; } return


<s> SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , fmrrd ) ) ; if ( NextVA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg (

) , fmrrd . getValue ( <NUM_LIT> ) ) ) ;


<s> if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > <NUM_LIT> && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ; else return


<s> const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write ( OS , nopEncoding , Endian ) ; if ( Count & <NUM_LIT> ) OS << '\0' ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write ( OS , nopEncoding , Endian ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OS << '\0' ; break ; case <NUM_LIT> : OS . write ( <STR_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : OS . write ( <STR_LIT> , <NUM_LIT> ) ; break ; } return true


, V2 , Zeroable , Subtarget , DAG ) ) return PSHUFB ;


<s> assert ( Subtarget . isTargetDarwin ( ) && Subtarget . is64Bit ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; RTLIB :: Libcall LC = isF64 ? RTLIB :: SINCOS_STRET_F64 : RTLIB :: SINCOS_STRET_F32 ; const char * LibcallName = TLI . getLibcallName ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy ) : ( Type * ) FixedVectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue CosVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDVTList Tys = DAG . getVTList (


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS ,


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Lo = DAG . getNode ( ExtOpc , dl , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( ExtOpc , dl ,


<s> bool <ISA_LIT>FastISel :: SelectCall ( const Instruction * I , const char * IntrMemName = nullptr ) { const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledOperand ( ) ; if ( isa < InlineAsm > ( Callee ) ) return false ; if ( CI -> isTailCall ( ) ) return false ; CallingConv :: ID CC = CI -> getCallingConv ( ) ; FunctionType * FTy = CI -> getFunctionType ( ) ; bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Register , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CI -> arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( auto ArgI = CI -> arg_begin ( ) , ArgE = CI -> arg_end ( ) ; ArgI != ArgE ; ++ ArgI ) { if ( IntrMemName && ArgE - ArgI <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned ArgIdx = ArgI - CI


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( <STR_LIT> == RB . getID ( ) ) return Isload ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> == RB . getID ( ) ) return Isload ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= Align ( <NUM_LIT> ) ) return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= Align ( <NUM_LIT> ) ) return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; else return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> :


<s> last = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , ( get_probe_interval ( ) + dope ) ) ) ) ; } else { gcc_assert ( int_registers_saved ) ; HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; if ( sr . saved ) size -= UNITS_PER_WORD ; rounded_size = ROUND_DOWN ( size , get_probe_interval ( ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( get_probe_interval ( ) + dope ) ) ) ) ; if ( rounded_size <= ( HOST_WIDE_INT_1 << <NUM_LIT> ) ) emit_insn ( gen_rtx_SET ( sr . reg , plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr


<s> unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( ) - <NUM_LIT> ) ) ; if ( ! LastCorrectlyNumberedBB ) LastCorrectlyNumberedBB = & MBB ; } if ( LastCorrectlyNumberedBB ) MF -> RenumberBlocks


<s> return false ; } auto BinPrefix = F . getSectionPrefix ( ) . getValue ( ) ; auto & CPEntries = MF . getConstantPool ( ) -> getConstants ( ) ; SmallSet < int , <NUM_LIT> > CPIndices ; int Index = <NUM_LIT> ; for ( auto & E : CPEntries ) { if ( isIntraBin ( E , BinPrefix ) ) CPIndices . insert ( Index ) ; Index ++ ; } if ( CPIndices . empty ( ) ) return false ; std :: vector < MachineInstr * > Uses ; for ( auto & BB : MF ) { for ( auto & MI : BB


<s> assert ( StNode && StNode -> getOffset ( ) . isUndef ( ) && <STR_LIT> ) ; EVT MemVT = StNode -> getMemoryVT ( ) ; if ( MemVT . isVector ( ) && ! isMaskType ( MemVT ) ) return lowerToVVP ( Op , DAG ) ; SDValue BasePtr = StNode -> getBasePtr ( ) ; if ( isa < FrameIndexSDNode > ( BasePtr . getNode ( ) ) ) { return Op


<s> SDValue FrameAddr ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDNodeFlags Flags ; Flags . setNoUnsignedWrap ( true ) ; FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset , Flags ) , MachinePointerInfo ( ) ) ; } else { unsigned LRReg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT>


<s> if ( isNEONByteReplicate ( <NUM_LIT> ) ) return false ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE -> getValue ( ) ; return <STR_LIT> ( Value )


<s> switch ( MatchResult ) { default : break ; case Match_Success : if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; return true ; } while ( processInstruction ( Inst , Operands ) ) ; forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case


<s> for ( MachineBasicBlock & MBB : * MF ) { BlockInfo [ MBB . getNumber ( )


<s> else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) . getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; CPI = MCP -> getConstantPoolIndex ( NewCPV , MCPE . getAlign ( ) ) ; return PCLabelId


<s> case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DCI ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT>


<s> void <ISA_LIT>DAGToDAGISel :: EmitSpecialCodeForMain ( MachineBasicBlock * BB , MachineFrameInfo * MFI ) { const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( Subtarget -> isTargetCygMing ( ) ) { unsigned CallOp = Subtarget -> is64Bit (


<s> Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Opc = Old -> getOpcode ( ) ; int PIdx = Old -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( PIdx ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , Pred , PredReg ) ; } else { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Opc == <STR_LIT> || Opc ==


<s> MCStreamer * S ; if ( ! Triple ( TT ) . isOSNaCl ( ) ) S = create<ISA_LIT>ELFStreamer ( Context , MAB , OS , Emitter , STI , RelaxAll ) ; else S = create<ISA_LIT>NaClELFStreamer ( Context , MAB , OS , Emitter , STI , RelaxAll ) ; new <ISA_LIT>TargetELFStreamer ( * S


<s> if ( cfun -> is_thunk ) return ; fputs ( <STR_LIT> ,


<s> if ( RegNo != <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler


<s> emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , mem , vec ) , x ) ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , <NUM_LIT> )


<s> return decodeRegisterClass ( Inst , RegNo


<s> SDValue Root = matchBinOpReduction ( Extract , BinOp , { <STR_LIT> } ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Zext0 , Zext1 ; if ( ! detectZextAbsDiff ( Root , Zext0 , Zext1 ) ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue SAD = createPSADBW ( DAG , Zext0 , Zext1 , DL ) ; unsigned Stages = Log2_32 ( VT . getVectorNumElements ( ) ) ; MVT SadVT = SAD . getSimpleValueType ( ) ; if ( Stages > <NUM_LIT> ) { unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT ) , Mask ) ; SAD = DAG . getNode ( <STR_LIT> , DL , SadVT , SAD , Shuffle ) ; } } MVT Type = Extract -> getSimpleValueType ( <NUM_LIT>


<s> const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = k_MemoryZeroImmImm ; Op -> Mem . Base


<s> unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++


<s> void ELF<ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { if ( isByteSwappedFixup ( Fixup . getValue ( ) ) ) Value = ByteSwap_32 (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> hasExternalLinkage ( ) || GVar -> isWeakForLinker ( ) ) && TAI -> SectionKindForGlobal ( GVar ) != SectionKind :: RODataMergeStr ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasExternalLinkage ( ) ) { O << <STR_LIT> << name << '\n' ; O << <STR_LIT> << name << <STR_LIT> << Size << <STR_LIT> << Align ; } else if ( GVar -> hasLocalLinkage ( ) ) { O << TAI -> getLCOMMDirective ( ) << name << ',' << Size << ',' << Align ; } else if ( ! GVar -> hasCommonLinkage ( ) ) { O << <STR_LIT> << name << '\n' << TAI -> getWeakDefDirective ( ) << name << '\n' ; EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; } O << '\n' ; EmitGlobalConstant ( C ) ; return ; } else { O << <STR_LIT> << name << ',' << Size ; if ( Subtarget . isDarwin9 ( ) ) O << ',' << Align ; } if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; O << <STR_LIT> ; } O << '\n'


<s> return ( __m64 ) __builtin_arm_wunpckehsb ( (


<s> if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S


<s> return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute

:: SanitizeHWAddress ) , false ) . getBytes ( ) ;


<s> sri -> icode = ( in_p ? CODE_FOR_reload_noff_load : CODE_FOR_reload_noff_store ) ; sri -> extra_cost = <NUM_LIT> ; return NO_REGS ; } if ( mode == QImode && ( MAYBE_MASK_CLASS_P ( rclass ) || ( ! TARGET_64BIT && ! in_p && INTEGER_CLASS_P ( rclass ) && MAYBE_NON_Q_CLASS_P ( rclass ) ) ) ) { int regno


<s> return ; } fprintf ( asm_out_file , <STR_LIT> , name ) ; if ( ! ( flags & SECTION_DEBUG ) ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_EXCLUDE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs (


<s> static rtx gen_fr_restore_x ( rtx dest , rtx src , rtx offset ATTRIBUTE_UNUSED ) { return gen_fr_restore ( dest


<s> static bool matchShuffleWithPACK ( MVT VT , MVT & SrcVT , SDValue & V1 , SDValue & V2 , unsigned & PackOpcode , ArrayRef < int > TargetMask , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BitSize = VT . getScalarSizeInBits ( ) ; MVT PackSVT = <STR_LIT> ( BitSize * <NUM_LIT> ) ; MVT PackVT = <STR_LIT> ( PackSVT , NumElts / <NUM_LIT> ) ; auto MatchPACK = [ & ] ( SDValue N1 , SDValue N2 ) { SDValue VV1 = DAG . getBitcast ( PackVT , N1 ) ; SDValue VV2 = DAG . getBitcast ( PackVT , N2 ) ; if ( Subtarget . hasSSE41 ( ) || PackSVT == <STR_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( BitSize * <NUM_LIT> , BitSize ) ; if ( ( N1 . isUndef ( ) || DAG . MaskedValueIsZero ( VV1 , ZeroMask ) ) && ( N2 . isUndef ( ) || DAG . MaskedValueIsZero ( VV2 , ZeroMask ) ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } if ( ( N1 . isUndef ( ) || DAG . ComputeNumSignBits ( VV1 ) > BitSize ) && ( N2 . isUndef ( ) || DAG . ComputeNumSignBits ( VV2 ) > BitSize ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } return false ; } ; SmallVector < int , <NUM_LIT> > BinaryMask ; createPackShuffleMask ( VT , BinaryMask , false ) ; if ( isTargetShuffleEquivalent ( TargetMask , BinaryMask , V1 , V2 ) ) if ( MatchPACK ( V1 , V2 ) ) return true ; SmallVector < int , <NUM_LIT> > UnaryMask ; createPackShuffleMask ( VT , UnaryMask , true ) ; if ( isTargetShuffleEquivalent ( TargetMask , UnaryMask , V1 ) ) if ( MatchPACK ( V1 , V1 ) ) return true ; return false


<s> else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base_Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return


<s> Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case


<s> <ISA_LIT>Operand & Op = ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ; if ( ! IsVector && ! Op . isRegList ( ) ) return Error ( L , <STR_LIT> ) ; if ( IsVector && ! Op . isDPRRegList ( ) ) return Error ( L , <STR_LIT> ) ; getTargetStreamer ( ) . emitRegSave ( Op . getRegList (