<s> static SDValue combineExtractWithShuffle ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getVectorElementType ( ) ; unsigned SrcEltBits = SrcSVT . getSizeInBits ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; const APInt & IdxC = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; if ( IdxC . uge ( NumSrcElts ) ) return SDValue ( ) ; SDValue SrcBC = peekThroughBitcasts ( Src ) ; if ( <STR_LIT> == SrcBC . getOpcode ( ) ) { SDValue SrcOp = SrcBC . getOperand ( <NUM_LIT> ) ; if ( SrcOp . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , SrcOp ) ; EVT SrcOpVT = SrcOp . getValueType ( ) ; if ( SrcOpVT . isScalarInteger ( ) && VT . isInteger ( ) && ( SrcOpVT . getSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> ) { unsigned Scale = SrcOpVT . getSizeInBits ( ) / SrcEltBits ; unsigned Offset = IdxC . urem ( Scale ) * SrcEltBits ; if ( Offset == <NUM_LIT> ) { SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , SrcVT . getScalarType ( ) ) ; SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , VT ) ; return SrcOp ; } } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && SrcBC . hasOneUse ( ) ) { auto * MemIntr = cast < MemIntrinsicSDNode > ( SrcBC ) ; unsigned SrcBCWidth = SrcBC . getScalarValueSizeInBits ( ) ; if ( MemIntr -> getMemoryVT ( ) . getSizeInBits ( ) == SrcBCWidth && VT . getSizeInBits ( ) == SrcBCWidth ) { SDValue Load = DAG . getLoad ( VT , dl , MemIntr -> getChain ( ) , MemIntr -> getBasePtr ( ) , MemIntr -> getPointerInfo ( ) , MemIntr -> getOriginalAlign ( ) , MemIntr -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( MemIntr , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load


<s> bool <ISA_LIT>16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) ->


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ( ! SUBREG_P ( XEXP ( src , <NUM_LIT> ) ) || SUBREG_BYTE ( XEXP ( src , <NUM_LIT> ) ) != <NUM_LIT> || ! REG_P ( SUBREG_REG ( XEXP ( src , <NUM_LIT> ) ) ) ) && ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != QImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT || ! REG_P ( XEXP ( XEXP (

src , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , object :: mach :: CPUSubtype<ISA_LIT> st ) : <ISA_LIT>AsmBackend (


<s> bool nds32_n13_last_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT>


<s> REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_DOUBLE_P ( elt ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , &


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new <ISA_LIT>ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM ,


<s> void addCOP3AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getCOP3Reg ( ) )


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Op1 || Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 -> getOperand ( <NUM_LIT> ) , Op0 ->


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> ) , Subtarget , DAG , SDLoc ( N ) ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT .

getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) {


<s> if ( inMicro<ISA_LIT>Mode ( ) ) Inst . setOpcode ( has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( ! isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) return Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset . getImm ( ) ) ) ; } } Out . EmitInstruction ( Inst , * STI ) ; const MCInstrDesc & MCID = getInstDesc ( Inst . getOpcode ( ) ) ; if ( MCID . hasDelaySlot ( ) && AssemblerOptions . back ( ) -> isReorder ( ) ) TOut . emitEmptyDelaySlot (


<s> } if ( to == STACK_POINTER_REGNUM ) { if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . frame_size - cfun ->


<s> case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } if ( Need0FPrefix ) EmitByte ( <NUM_LIT> , CurByte , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte ,


<s> int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = Subtarget . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; emitSPAdjustment ( MF , MBB , MBBI , - NumBytes ) ; emitSPExtend ( MF , MBB , MBBI , - NumBytes ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION )


<s> if ( ! isUnary ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT>


<s> if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else


<s> unsigned FPReg = MRI . getLLVMRegNum ( FPPush . getRegister ( ) , true ) ; LRReg = getXRegFromWReg ( LRReg ) ; FPReg = getXRegFromWReg ( FPReg ) ; assert ( LRReg == <STR_LIT> && FPReg == <STR_LIT> && <STR_LIT> ) ; CompactUnwindEncoding |= CU :: UNWIND_ARM64_MODE_FRAME ; HasFP = true ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { assert ( StackSize == <NUM_LIT> && <STR_LIT> ) ; StackSize = std :: abs ( Inst . getOffset ( ) ) ; break ; } case MCCFIInstruction :: OpOffset : { unsigned Reg1 = MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; if ( i + <NUM_LIT> == e ) return CU :: UNWIND_ARM64_MODE_DWARF ; const MCCFIInstruction & Inst2 = Instrs [ ++ i ] ; if ( Inst2 . getOperation ( ) != MCCFIInstruction :: OpOffset ) return CU :: UNWIND_ARM64_MODE_DWARF ; unsigned Reg2 = MRI . getLLVMRegNum ( Inst2 . getRegister ( ) , true ) ; Reg1 = getXRegFromWReg ( Reg1 ) ; Reg2 = getXRegFromWReg ( Reg2 ) ; if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X19_X20_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X21_X22_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X23_X24_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X25_X26_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X27_X28_PAIR ; else { Reg1 = getDRegFromBReg ( Reg1 ) ; Reg2 = getDRegFromBReg ( Reg2 ) ; if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_D8_D9_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_D10_D11_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_D12_D13_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_D14_D15_PAIR ; else return CU :: UNWIND_ARM64_MODE_DWARF ; } break ; } } } if ( ! HasFP ) { if ( StackSize > <NUM_LIT> ) return CU :: UNWIND_ARM64_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_ARM64_MODE_FRAMELESS ; CompactUnwindEncoding |= encodeStackAdjustment


<s> if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getNode ( <STR_LIT> , DL , IntVT ,


<s> if ( LS != r - <NUM_LIT> ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( <NUM_LIT> ) << ( LS + <NUM_LIT> ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = getInt64CountDirect ( RImmWithOnes ) + <NUM_LIT> ; Count = std :: min ( Count , RCount ) ; } return Count


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( BaseReg ) ) return false ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_instr_iterator I = MRI . def_instr_begin ( BaseReg ) , E = MRI . def_instr_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = &


<s> return <STR_LIT> ( ( Imm >> <NUM_LIT> ) & <NUM_LIT>


<s> M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M


<s> unsigned getSOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr (


<s> return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) ,


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSet<ISA_LIT>64R2 ( ) { setCanHaveModuleDir ( false


<s> unsigned __int128 __res = ( unsigned __int128 ) __X * __Y ; * __P = ( unsigned long long ) (


<s> static Value * simplify<ISA_LIT>insertps ( const IntrinsicInst & II , InstCombiner :: BuilderTy & Builder ) { auto * CInt = dyn_cast < ConstantInt > ( II . getArgOperand ( <NUM_LIT> ) ) ; if ( ! CInt ) return nullptr ; auto * VecTy = cast < FixedVectorType > ( II . getType ( ) ) ; assert ( VecTy -> getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; uint8_t Imm = CInt -> getZExtValue ( ) ; uint8_t ZMask = Imm & <NUM_LIT> ; uint8_t DestLane = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t SourceLane = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; ConstantAggregateZero * ZeroVector = ConstantAggregateZero :: get ( VecTy ) ; if ( ZMask == <NUM_LIT> ) return ZeroVector ; int ShuffleMask [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Value * V1 = II . getArgOperand ( <NUM_LIT> ) ; if ( ZMask ) { if ( ( II . getArgOperand ( <NUM_LIT> ) == II . getArgOperand ( <NUM_LIT> ) ) || ( ZMask & ( <NUM_LIT> << DestLane ) ) ) { V1 = ZeroVector ; ShuffleMask [ DestLane ] = SourceLane ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ( ZMask >> i ) & <NUM_LIT> ) ShuffleMask [ i ] = i + <NUM_LIT> ; } else { return nullptr


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , dl , VT


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return &


<s> if ( static_cast < unsigned > ( M [ i ] ) != <NUM_LIT> * i + WhichResult ) return false ; } return true


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG


<s> <ISA_LIT>_MachoTargetObjectFile :: <ISA_LIT>_MachoTargetObjectFile ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue JT = Op . getOperand ( <NUM_LIT> ) ; SDValue Entry = Op . getOperand ( <NUM_LIT> ) ; int JTI = cast < JumpTableSDNode > ( JT . getNode ( ) ) -> getIndex ( ) ; auto * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setJumpTableEntryInfo ( JTI , <NUM_LIT> , nullptr


<s> if ( MI == MBB . end ( ) || EndbrOpcode != MI -> getOpcode ( ) ) { BuildMI ( MBB , MI , MBB . findDebugLoc ( MI


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering (


<s> SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , array_lengthof ( Ops ) , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> )


<s> if ( ST -> getDarwinDirective ( ) == <STR_LIT> ) { UP . Partial = UP . Runtime = true ; } BaseT :: getUnrollingPreferences ( L


<s> static DecodeStatus DecodetGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> return __builtin_ia32_ucomieq ( ( __v4sf ) __A , (


<s> i = <NUM_LIT> ; if ( ( num_regs & <NUM_LIT> ) != <NUM_LIT> ) { rtx reg , mem , insn ; reg = gen_rtx_REG ( SImode , regno ) ; if ( num_regs == <NUM_LIT> ) mem = gen_frame_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ; else mem = gen_frame_mem ( Pmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ) ; tmp = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; insn = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; tmp = gen_rtx_SET ( gen_frame_mem ( Pmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; i ++ ; regno ++ ; XVECEXP ( dwarf , <NUM_LIT> , i ) = tmp ; first = false ; } while ( i < num_regs ) if ( saved_regs_mask & ( <NUM_LIT> << regno ) ) { rtx reg1 , reg2 , mem1 , mem2 ; rtx tmp0 , tmp1 , tmp2 ; int regno2 ; for ( regno2 = regno + <NUM_LIT> ; ( saved_regs_mask & ( <NUM_LIT> << regno2 ) ) == <NUM_LIT> ; regno2 ++ ) ; reg1 = gen_rtx_REG ( SImode , regno ) ; reg2 = gen_rtx_REG ( SImode , regno2 ) ; if ( first ) { rtx insn ; first =


<s> if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > <NUM_LIT> ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < <NUM_LIT> || length >= <NUM_LIT> ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( <NUM_LIT> ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & <NUM_LIT> ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn ) >= <NUM_LIT> ) aligned_p


<s> switch ( abi . base ) { case ABI_BASE_LP64D : case ABI_BASE_LP64F : case ABI_BASE_LP64S


<s> static void nds32_relax_group ( void ) { rtx_insn * insn ; compute_bb_for_insn ( ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , SImode ) && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ) ) nds32_group_insns ( insn ) ; else if ( recog_memoized ( insn ) == CODE_FOR_tls_ie ) nds32_group_tls_insn ( insn ) ; else if ( TARGET_FPU_SINGLE && recog_memoized ( insn ) == CODE_FOR_move_addr && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ) ) { nds32_group_float_insns ( insn ) ; } } else if ( CALL_P ( insn ) && recog_memoized ( insn ) == CODE_FOR_tls_desc ) { nds32_group_tls_insn ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ; free_dominance_info (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS , bool is64Bit ) : IsV9 ( false ) , V8DeprecatedInsts ( false ) , IsVIS ( false ) , Is64Bit ( is64Bit ) { const char * CPU = <STR_LIT> ; if ( is64Bit ) { CPU =


<s> if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; MVT VT = <STR_LIT> ; switch ( Op . getValueType ( ) . getSimpleVT ( ) ) { default : break ; case <STR_LIT>


<s> static bool isSimpleReturn ( const MachineInstr


<s> if ( ! printSymbolicAddress ( MI -> getOperand ( OpNum ) , true , <STR_LIT> , O ) ) return false ; break ; case 'G' : if ( ! printSymbolicAddress ( MI -> getOperand ( OpNum ) , true , <STR_LIT> , O ) ) return false ; break ; case 'a' : return PrintAsmMemoryOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; } const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( printModifiedFPRAsmOperand ( MO , TRI , 'v' , O ) ) O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << '#' << MO . getImm ( ) ; break ; case MachineOperand :: MO_FPImmediate : assert ( MO . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) && <STR_LIT> ) ; O << <STR_LIT> ; break ; case MachineOperand :: MO_BlockAddress : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : return printSymbolicAddress ( MO , false


<s> rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer


<s> if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> << CPUDirectives [ Directive ] << '\n' ; bool Result = AsmPrinter :: doInitialization ( M ) ; assert ( MMI ) ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> ,


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) ,


<s> return false ; case 'y' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { Register Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; for ( MCSuperRegIterator SR ( Reg , TRI ) ; SR . isValid ( ) ; ++ SR ) { if ( ! <STR_LIT> . contains ( * SR ) ) continue ; bool Lane0 = TRI -> getSubReg ( * SR , <STR_LIT> ) == Reg ; O << <ISA_LIT>InstPrinter :: getRegisterName ( * SR ) << ( Lane0 ? <STR_LIT> : <STR_LIT> ) ; return false ; } } return true ; case 'B' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ~ ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ( MI -> getOperand ( OpNum ) . getImm ( ) & <NUM_LIT> ) ; return false ; case 'M' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; Register RegBegin = MO . getReg ( ) ; O << <STR_LIT> ; if ( <STR_LIT> . contains ( RegBegin ) ) { const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; Register Reg0 = TRI -> getSubReg ( RegBegin , <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg0 ) << <STR_LIT> ; RegBegin = TRI -> getSubReg ( RegBegin , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( RegBegin ) ; unsigned RegOps = OpNum + <NUM_LIT> ; while ( MI -> getOperand ( RegOps ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( RegOps ) . getReg ( ) ) ; RegOps ++ ; } O <<


<s> assert ( ( ByValSize < Offset + <NUM_LIT> ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned OffsetDW = ( Offset % <NUM_LIT> ) * <NUM_LIT> ; unsigned Shamt = isLittle ? OffsetDW : <NUM_LIT> - ( OffsetDW + LoadSize * <NUM_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; Val = Val . getNode ( ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Shift ) : Shift ; Offset += LoadSize ; Alignment = std :: min ( Alignment , LoadSize ) ; } RegsToPass . push_back ( std :: make_pair ( * Reg , Val ) ) ; return ; } } assert ( MemCpySize && <STR_LIT> ) ; SDValue Src = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; LastFI = MFI -> CreateFixedObject ( MemCpySize , LocMemOffset , true ) ; SDValue Dst = DAG . getFrameIndex ( LastFI , PtrTy ) ; ByValChain = DAG . getMemcpy ( ByValChain , dl , Dst , Src , DAG . getConstant ( MemCpySize , PtrTy ) , Alignment , false

, false , MachinePointerInfo ( <NUM_LIT> ) , MachinePointerInfo ( <NUM_LIT> ) ) ;


<s> return __builtin_ia32_comieq ( ( __v4sf ) __A , (


<s> SDValue <ISA_LIT>TargetLowering :: ExtractBitFromMaskVector ( SDValue Op , SelectionDAG & DAG ) const { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Vec ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT EltVT = Op . getSimpleValueType ( ) ; assert ( ( EltVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget -> hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; const TargetRegisterClass * rc = getRegClassFor ( VecVT ) ; if ( ! Subtarget -> hasDQI ( ) && ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> ) ) rc = getRegClassFor ( <STR_LIT> ) ; unsigned MaxSift = rc -> getSize ( ) * <NUM_LIT> - <NUM_LIT> ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( MaxSift


<s> return ( TARGET_AVX && TARGET_SSE_PARTIAL_REG_DEPENDENCY && TARGET_SSE_MATH &&

optimize && optimize_function_for_speed_p ( cfun ) ) ;


<s> MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { if ( ! MRI . hasOneUse ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP


<s> static void aarch64_parse_arch ( void ) { char * ext ; const struct processor * arch ; char * str = ( char * ) alloca ( strlen ( aarch64_arch_string ) + <NUM_LIT> ) ; size_t len ; strcpy ( str , aarch64_arch_string ) ; ext = strchr ( str , '+' ) ; if ( ext != NULL ) len = ext - str ; else len = strlen ( str ) ; if ( len == <NUM_LIT> ) { error ( <STR_LIT> , str ) ; return ; } for ( arch = all_architectures ; arch -> name != NULL


<s> bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> )

return parseDirectiveTLSDescCall ( Loc ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget


<s> static SDValue scalarizeVectorStore ( StoreSDNode * Store , MVT StoreVT , SelectionDAG & DAG ) { SDValue StoredVal = Store -> getValue ( ) ; assert ( StoreVT . is128BitVector ( ) && StoredVal . getValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; StoredVal = DAG . getBitcast ( StoreVT , StoredVal ) ; if ( Store -> isVolatile ( ) ) return SDValue ( ) ; MVT StoreSVT = StoreVT . getScalarType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; unsigned ScalarSize = StoreSVT . getStoreSize ( ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDLoc DL ( Store


<s> bool isToken ( ) const override { return Kind == TOKEN


<s> static SDValue LowerVectorExtend ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return SDValue ( ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT FromVT = Op . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ExtVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; if ( ToVT . getScalarType ( ) == <STR_LIT> && FromVT . getScalarType ( ) == <STR_LIT> ) ExtVT


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS , Is64Bit , IsLittleEndian ,


<s> bool isMLA = false ; bool isN0SExt = isSignExtended ( N0 , DAG ) ; bool isN1SExt = isSignExtended ( N1 , DAG ) ; if ( isN0SExt && isN1SExt ) NewOpc = <STR_LIT> ; else { bool isN0ZExt = isZeroExtended ( N0 , DAG ) ; bool isN1ZExt = isZeroExtended ( N1 , DAG ) ; if ( isN0ZExt && isN1ZExt ) NewOpc = <STR_LIT> ; else if ( isN1SExt || isN1ZExt ) { if ( isN1SExt && isAddSubSExt ( N0 , DAG ) ) { NewOpc = <STR_LIT> ; isMLA = true ; } else if ( isN1ZExt && isAddSubZExt ( N0 , DAG ) ) { NewOpc = <STR_LIT> ; isMLA = true ; } else if ( isN0ZExt && isAddSubZExt ( N1 , DAG ) ) { std :: swap ( N0 , N1 ) ; NewOpc = <STR_LIT> ; isMLA = true ; } } if ( ! NewOpc ) { if ( VT == <STR_LIT> ) return SDValue ( ) ; else return Op ; } } DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Op0 ; SDValue Op1 = SkipExtensionForVMULL ( N1 , DAG ) ; if ( ! isMLA ) { Op0 = SkipExtensionForVMULL ( N0 , DAG


<s> unsigned SubReg2 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MB == <NUM_LIT> && ME == <NUM_LIT> ) return nullptr ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg1 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( Reg2IsKill ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( ( MB


<s> void visitRet ( ReturnInst & RI ) { Value * RV = RI . getReturnValue ( ) ; if ( RV && isa < ConstantExpr > ( RV ) ) { ConstantCast C = { & RI , <NUM_LIT> , testI2P ( * cast < User > ( RV ) ) } ; if ( C . Origin ) { auto Src = getValueSource ( C . Origin -> getOperand ( <NUM_LIT> ) ) ; AllocOperands AO = getRangeForAllocation ( Src ) ; if ( AO != AllocOperands ( ) ) ConstantCasts . push_back (

pair < AllocOperands , ConstantCast > ( AO , C ) ) ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT

, FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes =


<s> __builtin_aarch64_st1v16qi ( ( __builtin_aarch64_simd_qi * ) a , ( int8x16_t )


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; int MaxMergeDistance = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE && ! BaseT :: isConstantStridedAccessLessThan ( SE , Ptr , MaxMergeDistance + <NUM_LIT> ) ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> static bool isRightAfterData ( MCFragment * CurrentFragment , const std :: pair < MCFragment * , size_t > & PrevInstPosition ) { MCFragment * F = CurrentFragment ; for ( ; isa_and_nonnull < MCDataFragment > ( F ) ; F = F -> getPrevNode ( ) ) if ( cast < MCDataFragment > ( F ) -> getContents ( ) . size ( ) != <NUM_LIT> ) break ; if ( auto * DF = dyn_cast_or_null < MCDataFragment > ( F ) ) return DF != PrevInstPosition . first || DF -> getContents ( ) . size ( ) != PrevInstPosition . second ; return false


<s> MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel (


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addOperand ( Base ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; return Reg


<s> return ( __m512i ) __builtin_ia32_expandloadhi512_maskz ( ( const __v32hi * ) __B , ( __v32hi ) _mm512_setzero_si512 ( )


<s> <ISA_LIT>CTRLoops ( ) : MachineFunctionPass


<s> return get_hard_reg_initial_val ( Pmode


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT>


<s> unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ <NUM_LIT> ]


<s> static tree aarch64_general_add_builtin ( const char * name , tree type , unsigned int code , tree attrs = NULL_TREE ) { code = ( code << AARCH64_BUILTIN_SHIFT ) |


<s> if ( Fast ) { * Fast = true ; } return true


<s> const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase


<s> case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_core ( str ) ; break ; default : gcc_unreachable ( ) ; } return false


<s> static void EmitLoad ( bool Is64Bit , unsigned DestReg , unsigned BaseReg , unsigned Scale , unsigned IndexReg , unsigned Offset , unsigned SegmentReg , MCStreamer & Out ) { MCInst Load ; Load . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; Load . addOperand ( MCOperand :: CreateReg ( DestReg ) ) ; Load . addOperand ( MCOperand :: CreateReg ( BaseReg ) ) ; Load . addOperand ( MCOperand :: CreateImm ( Scale ) ) ; Load . addOperand ( MCOperand :: CreateReg ( IndexReg ) ) ; Load . addOperand ( MCOperand ::


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; Value <<= Info .


<s> unsigned <ISA_LIT>TTI :: getShuffleCost ( ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) const { if ( Kind != SK_Reverse ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; unsigned Cost = <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) Cost = <NUM_LIT> ; return Cost * LT .


<s> static bool mips_no_speculation_in_delay_slots_p ( ) { return TARGET_CB_MAYBE


<s> fprintf ( stderr , <STR_LIT> ) ; return false ; } fprintf ( stderr , <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == REG && GEN_REG ( REGNO ( x ) , strict ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GEN_REG ( REGNO ( XEXP ( x , <NUM_LIT> ) ) , strict ) && const_in_range ( XEXP ( x , <NUM_LIT> ) , - <NUM_LIT> , <NUM_LIT> ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GEN_REG ( REGNO ( XEXP ( x , <NUM_LIT> ) ) , strict ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC || ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; } the_tag = mep_section_tag ( x ) ; if ( the_tag == 'f' ) { fprintf ( stderr , <STR_LIT>


<s> if ( CompareRHS -> getZExtValue ( ) == FalseVal -> getZExtValue ( ) ) Invert = ! Invert ; else if ( CompareRHS -> getZExtValue ( ) != TrueVal -> getZExtValue ( ) ) return false ; auto * NewCCValid = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; auto * NewCCMask = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! NewCCValid || ! NewCCMask ) return false ; CCValid = NewCCValid -> getZExtValue ( ) ; CCMask = NewCCMask -> getZExtValue ( ) ; if ( Invert ) CCMask ^= CCValid ; CCReg = CompareLHS -> getOperand ( <NUM_LIT> ) ; return true ; } if ( CompareLHS -> getOpcode ( ) == <STR_LIT> ) { auto * SRACount = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! SRACount || SRACount -> getZExtValue ( ) != <NUM_LIT> ) return false ; auto * SHL = CompareLHS -> getOperand ( <NUM_LIT> ) .


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> ,

<STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec

( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) {


<s> rtx op0 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( pat ) ; return target


<s> SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { Idx , -


<s> if ( Ty -> isHalfTy ( ) || Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) return true ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) return true ; return false


<s> switch ( OpSize ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; } break ; case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT>


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr .

getValueAsString ( ) . str ( ) : TargetFS ;


<s> args_byte_size += hfa_size ; fp_regs ++ ; } if ( ! cum -> prototype ) offset = <NUM_LIT> ; else if ( byte_size != offset ) int_regs += offset / UNITS_PER_WORD ; for ( ; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS ; i ++ ) { enum machine_mode gr_mode = DImode ; unsigned int gr_size ; if ( offset & <NUM_LIT> ) gr_mode = SImode ; else if ( byte_size - offset == <NUM_LIT> ) gr_mode = SImode ; loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( gr_mode , ( basereg + int_regs ) ) , GEN_INT ( offset ) ) ; gr_size = GET_MODE_SIZE ( gr_mode ) ; offset += gr_size ; if ( gr_size == UNITS_PER_WORD || ( gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == <NUM_LIT> ) ) int_regs ++ ; else if ( gr_size > UNITS_PER_WORD ) int_regs += gr_size / UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) { int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; if ( BYTES_BIG_ENDIAN && ( mode == BLKmode || ( type && AGGREGATE_TYPE_P ( type ) ) ) && byte_size < UNITS_PER_WORD && byte_size > <NUM_LIT> ) { rtx gr_reg = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , ( basereg + cum -> words + offset ) ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gr_reg ) ) ; } else return gen_rtx_REG ( mode , basereg + cum ->


<s> return isUndefInRange ( Mask , <NUM_LIT> , NumElts /


<s> SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; } SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; SDValue TotalVal ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal = ANDIVal ; else TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; if ( ! Res ) Res = TotalVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , TotalVal ) , <NUM_LIT> ) ; eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG .


<s> if ( AddrReg == <NUM_LIT> ) return false ; const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; AddrReg = constrainOperandRegClass ( II , AddrReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( AddrReg ) ; for ( auto * Succ : BI -> successors ( ) ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ Succ ] ) ; return


<s> rtx_insn * insn ; if ( high == low ) insn = emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_popm ( GEN_INT ( ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ) , gen_rx_popm_vector ( low , high ) ) ) ; add_pop_cfi_notes ( insn , high ,


<s> return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( isFP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Size = <NUM_LIT> ; if ( hasCOP3 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isGP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = TheTriple . getArch ( ) == Triple :: ppc64 ; if ( TheTriple . getOS ( ) == Triple

:: Darwin ) return new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 ) ;


<s> } for ( unsigned reg = <STR_LIT> ; reg < <STR_LIT> ; ++ reg ) { if ( ! MO . clobbersPhysReg ( reg ) ) return false ; } return


<s> assert ( Zeroable . size ( ) - Zeroable . count ( ) > <NUM_LIT> && <STR_LIT> ) ; SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op -> getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx ==


<s> return ( __m128i ) __builtin_ia32_vpcomgeuw ( ( __v8hi ) __A , ( __v8hi )


<s> assert ( ! MustBeFirstR && <STR_LIT> ) ; std :: swap ( LHS , RHS ) ; std :: swap ( CanNegateL , CanNegateR ) ; std :: swap ( MustBeFirstL , MustBeFirstR ) ; } bool NegateR ; bool NegateAfterR ; bool NegateL ; bool NegateAfterAll ; if ( Opcode == TargetOpcode :: G_OR ) { if ( ! CanNegateL ) { assert ( CanNegateR && <STR_LIT> ) ; assert ( ! MustBeFirstR && <STR_LIT> ) ; assert ( ! Negate ) ; std :: swap ( LHS , RHS ) ; NegateR = false ; NegateAfterR = true ; } else { NegateR = CanNegateR ; NegateAfterR = ! CanNegateR ; } NegateL = true ; NegateAfterAll = ! Negate ; } else { assert ( Opcode == TargetOpcode :: G_AND && <STR_LIT> ) ; assert ( ! Negate && <STR_LIT> ) ; NegateL = false ; NegateR = false ; NegateAfterR = false ; NegateAfterAll = false ; } <STR_LIT> RHSCC ; MachineInstr * CmpR = emitConjunctionRec ( RHS , RHSCC , NegateR , CCOp , Predicate , MIB ) ; if ( NegateAfterR ) RHSCC = <STR_LIT> ( RHSCC ) ; MachineInstr * CmpL = emitConjunctionRec ( LHS , OutCC , NegateL , CmpR -> getOperand ( <NUM_LIT> ) . getReg ( ) , RHSCC , MIB ) ; if ( NegateAfterAll ) OutCC = <STR_LIT> ( OutCC


<s> ArtCombiner . tryCombineMerges ( MI , DeadInstrs , UpdatedDefs ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> rtx op0 , op1 ; const struct cpu_cost_table * extra_cost = aarch64_tune_params -> insn_extra_cost ; int cost = <NUM_LIT> ; bool maybe_fma = ( outer == PLUS || outer == MINUS ) ; machine_mode mode = GET_MODE ( x ) ; gcc_checking_assert ( code == MULT ) ; op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( CONST_INT_P ( op1 ) && exact_log2 ( INTVAL ( op1 ) ) > <NUM_LIT> ) { if ( speed ) { if ( maybe_fma ) cost += extra_cost -> alu . arith_shift ; else cost += extra_cost -> alu . shift ; } cost += rtx_cost ( op0 , GET_CODE ( op0 ) , <NUM_LIT> , speed ) ; return cost ; } if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( op1 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ <NUM_LIT> ] . extend_add ; else cost += extra_cost -> mult [ <NUM_LIT> ] . extend ; } return cost ; } cost += rtx_cost ( op0 , MULT , <NUM_LIT> , speed ) + rtx_cost ( op1 , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ mode == DImode ] . add ; else cost += extra_cost -> mult [ mode ==


<s> static DecodeStatus decodeLRW16Imm8 ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) { Inst . addOperand ( MCOperand :: createImm ( ( Imm & <NUM_LIT> ) << <NUM_LIT> ) ) ; } else { uint64_t V = ( ( Imm ^ <NUM_LIT> )


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addr |= Rn << <NUM_LIT> ; unsigned load = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder


<s> break ; } SDValue Test ( DAG . getMachineNode ( Opc , DL , <STR_LIT> , Arg ) , <NUM_LIT> ) ; SDValue FNSTSW = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Test ) , <NUM_LIT> ) ; SDValue Extract = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , FNSTSW ) ; Extract = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getSetCC ( DL , ResultVT , Extract , DAG . getConstant ( <NUM_LIT> ,

DL , <STR_LIT> ) , <STR_LIT> :: SETLE ) ;


<s> if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) )


<s> return ( int8x8_t ) __builtin_neon_vld1_dupv8qi ( ( const __builtin_neon_qi *


<s> if ( ( GET_CODE ( op ) == ZERO_EXTRACT || GET_CODE ( op ) == SIGN_EXTRACT ) && XEXP ( op , <NUM_LIT> ) == const0_rtx && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == MULT && aarch64_is_extend_from_extract ( GET_MODE ( op ) , XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( op , <NUM_LIT> ) ) ) return XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) , INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) != <NUM_LIT> ) return XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) <= <NUM_LIT> ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op =


<s> unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( Val -> getScalarType ( ) -> isFloatingPointTy ( ) && Index == <NUM_LIT> ) return <NUM_LIT> ; } return TargetTransformInfo :: getVectorInstrCost ( Opcode ,


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; bool IsASHR = I . getOpcode ( ) == TargetOpcode :: G_ASHR ; unsigned Opc = <NUM_LIT> ; unsigned NegOpc = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForTypeOnBank ( Ty , RBI . getRegBank ( <STR_LIT> ) , RBI ) ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s>
const
MCOperand
&
MO2
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
const
MCOperand
&
MO3
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
printRegName
(
O
,
MO1
.
getReg
(
)
)
;
<STR_LIT>
ShOpc
=
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
O
<<
<STR_LIT>
<<
<STR_LIT>
(
ShOpc
)
;
if
(
ShOpc
==
<STR_LIT>
)
return
;
O
<<
' '
;
printRegName
(
O
,
MO2


<s> const <ISA_LIT>ELFDynamic & <ISA_LIT>GNULDBackend :: dynamic ( ) const { assert ( m_pDynamic != NULL


<s> static int aarch64_sched_adjust_priority ( rtx_insn * insn , int priority ) { rtx x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == SET ) { x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x

, <NUM_LIT> ) == UNSPEC_SHA1H ) return priority + <NUM_LIT> ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { expandHlt ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } unsigned Size = Desc . getSize ( ) ; switch ( Size )


<s> bool isImmWithLSL ( ) const { return Kind ==


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( SDValue V = combineTruncatedArithmetic ( N , DAG , Subtarget , DL ) ) return V ; if ( SDValue Avg = detectAVGPattern ( Src , VT , DAG , Subtarget , DL ) ) return Avg ; if ( SDValue PMAdd = detectPMADDUBSW ( Src , VT , DAG , Subtarget , DL ) ) return PMAdd ; if ( SDValue Val = combineTruncateWithSat ( Src , VT , DL , DAG , Subtarget ) ) return Val ; if ( SDValue V = combinePMULH ( Src , VT , DL , DAG , Subtarget ) ) return V ; if ( Src . getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) { SDValue BCSrc = Src . getOperand ( <NUM_LIT> ) ; if ( BCSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BCSrc ) ; } if ( SDValue V = combineVectorSignBitsTruncation ( N , DL , DAG


<s> case LTU : rtx geu ; if ( GET_CODE ( op0 ) == PLUS && ( rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) || rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCCmode ; else if ( code == LTU && GET_CODE ( op0 ) == NEG && GET_CODE ( geu = XEXP ( op0 , <NUM_LIT> ) ) == GEU && REG_P ( XEXP ( geu , <NUM_LIT> ) ) && ( GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) == CCCmode || GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) == CCmode ) && REGNO ( XEXP ( geu , <NUM_LIT> ) ) == FLAGS_REG && XEXP ( geu , <NUM_LIT> ) == const0_rtx && GET_CODE ( op1 ) == LTU && REG_P ( XEXP ( op1 , <NUM_LIT> ) ) && GET_MODE ( XEXP ( op1 , <NUM_LIT> ) ) == GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) && REGNO ( XEXP ( op1 , <NUM_LIT> ) ) == FLAGS_REG && XEXP ( op1 , <NUM_LIT> ) == const0_rtx ) return CCCmode ; else return CCmode ; case GTU : case LEU : return CCmode ; case GE


<s> MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isAtTop ( RegNo ) ) return ; unsigned STReg = getSTReg ( RegNo ) ; unsigned RegOnTop = getStackEntry ( <NUM_LIT> ) ; std :: swap ( RegMap [ RegNo ] , RegMap [ RegOnTop ] ) ; assert ( RegMap [ RegOnTop ] < StackTop


<s> void <ISA_LIT>InstrInfo :: storeRegToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState

( isKill ) ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI

. getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;


<s> return reinterpret_cast < const uint8_t * > (


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P (


<s> if ( ! IN_RANGE ( width , <NUM_LIT> , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - <NUM_LIT> ) ) return false ; if ( bitpos < <NUM_LIT> || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op )


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return


<s> Align <ISA_LIT>ConstantIslands :: getCPEAlign ( const MachineInstr & CPEMI ) { assert ( CPEMI . getOpcode ( ) == <STR_LIT> ) ; if ( ! AlignConstantIslands ) return Align ( <NUM_LIT> ) ; unsigned CPI = CPEMI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; assert ( CPI < MCP -> getConstants ( ) . size


<s> if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } if ( MInfo . CallConstructionID == MachineOutlinerNoLRSave ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState ::

Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { uint64_t ImmVal = CN


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; InstrumentMOVSBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , AccessSize , Ctx , Out ) ; EmitLabel ( Out


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl (


<s> bool is64Bit = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( maxCallFrameSize ) ; MBB . erase ( II


<s> if ( ! ( isRegIdx ( ) && RegIdx . Kind ) ) return false ; return ( RegIdx . Index == <NUM_LIT> || RegIdx . Index == <NUM_LIT> ||

( RegIdx . Index >= <NUM_LIT> && RegIdx . Index <= <NUM_LIT> ) ) ;


<s> MachineInstr * <ISA_LIT>CondBrTuning :: getOperandDef ( const MachineOperand & MO ) { if ( ! Register :: isVirtualRegister ( MO . getReg ( )


<s> assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; IsLeafFunction = false ; MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } const Function & CF = OF . Candidates . front ( ) . getMF ( ) -> getFunction ( ) ; bool ShouldSignReturnAddr = false ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { StringRef Scope = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) ShouldSignReturnAddr = true ; else if ( Scope . equals ( <STR_LIT> ) && ! IsLeafFunction ) ShouldSignReturnAddr = true ; } bool ShouldSignReturnAddrWithAKey = true ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { const StringRef Key = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( ( Key . equals_lower ( <STR_LIT> ) ||

Key . equals_lower ( <STR_LIT> ) ) && <STR_LIT> ) ;


<s> SmallVector < const Value * , <NUM_LIT> > Objs ; if ( getUnderlyingObjects ( MI , Objs ) ) { for ( SmallVector < const Value * , <NUM_LIT> > ::


<s> for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { PrevInstIsLFENCE = true ; continue ; } if ( MI . mayLoadOrStore ( ) && ! MI . isTerminator ( ) ) { if ( ! PrevInstIsLFENCE ) { BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; NumLFENCEsInserted ++ ; Modified = true ; } if ( OneLFENCEPerBasicBlock ) break ; } if ( MI . isTerminator ( ) && FirstTerminator == nullptr ) FirstTerminator = & MI ; if ( ! MI . isBranch ( ) || OmitBranchLFENCEs ) { PrevInstIsLFENCE =


<s> bool <ISA_LIT>LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> ) { SDValue CondSrc = Cond -> getOperand ( <NUM_LIT> ) ; if ( CondSrc -> getOpcode ( ) == <STR_LIT> ) Cond = CondSrc -> getOperand ( <NUM_LIT> ) ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; if ( <STR_LIT> ( LHS . getNode ( ) ) && <STR_LIT> ( RHS . getNode ( ) ) ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; if ( ! BUILD_VECTORtoBlendMask ( cast < BuildVectorSDNode > ( Cond ) , MaskValue ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { if ( Cond . getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) ShuffleMask [ i ] = - <NUM_LIT> ; else ShuffleMask [ i ] = i + NumElems * ( ( MaskValue >> i ) & <NUM_LIT> ) ; } return DAG . getVectorShuffle ( VT , dl , LHS , RHS , & ShuffleMask


<s> if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo & TRI = * Subtarget . getRegisterInfo ( ) ; LivePhysRegs LiveRegs ( TRI ) ; LiveRegs . addLiveIns ( * MBB ) ; const MCPhysReg * CSRegs = MF -> getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg


<s> else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( legitimate_constant_pool_address_p ( x ) ) { if ( TARGET_AIX && ( ! TARGET_ELF || ! TARGET_MINIMAL_TOC ) ) { rtx contains_minus = XEXP ( x , <NUM_LIT> ) ; rtx minus , symref ; const char * name ; while ( GET_CODE ( XEXP ( contains_minus , <NUM_LIT> ) ) != MINUS

) contains_minus = XEXP ( contains_minus , <NUM_LIT> ) ;


<s> assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ; if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const <ISA_LIT>Subtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) { SDValue Op0 = ShAmt . getOperand ( <NUM_LIT> ) ; Op0 = DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , <STR_LIT> , Op0 ) ; ShAmt = getShuffleVectorZeroOrUndef ( Op0 , <NUM_LIT> , true , & Subtarget , DAG ) ; } else { SmallVector < SDValue , <NUM_LIT> >


<s> return ( __m128i ) __builtin_ia32_vpcomequb ( ( __v16qi )


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) FuncInfo -> setSpillsCR ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( isXFormMemOp ( Opcode ) ) FuncInfo ->


<s> Uses . clear ( ) ; TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , ++ LastITMI -> getIterator ( ) ) ; Modified = true ; ++ NumITs


<s> static Optional < Instruction * > instCombineSVELD1 ( InstCombiner & IC , IntrinsicInst & II , const DataLayout & DL ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Value * Pred = II . getOperand ( <NUM_LIT> ) ; Value * PtrOp = II . getOperand ( <NUM_LIT> ) ; Type * VecTy = II . getType ( ) ; Value * VecPtr = Builder . CreateBitCast ( PtrOp , VecTy -> getPointerTo ( ) ) ; if ( isAllActivePredicate ( Pred ) ) { LoadInst * Load = Builder . CreateLoad ( VecTy , VecPtr ) ; return IC . replaceInstUsesWith ( II


<s> if ( ! FixupBWInsts ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; OptForSize = MF . getFunction ( ) -> optForSize ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; DEBUG ( dbgs ( ) <<


<s> if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0


<s> if ( TLI . isTypeLegal ( VT ) ) if ( SDValue AddSub = combineShuffleToAddSubOrFMAddSub ( N , Subtarget , DAG ) ) return AddSub ; if ( SDValue LD = combineToConsecutiveLoads ( VT , SDValue ( N , <NUM_LIT> ) , dl , DAG , Subtarget , true ) ) return LD ; if ( SDValue ShufConcat = combineShuffleOfConcatUndef ( N , DAG , Subtarget ) ) return ShufConcat ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Shuffle = combineTargetShuffle ( Op , DAG , DCI , Subtarget ) ) return Shuffle ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; APInt DemandedElts = APInt :: getAllOnes ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( Op , DemandedElts , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( SDValue BinOp = canonicalizeShuffleWithBinOps ( Op , DAG , SDLoc ( N ) ) ) return BinOp ; } return SDValue ( )


<s> Triple TheTriple ( TT ) ; unsigned RA = ( TheTriple . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ; <ISA_LIT>_MC :: InitLLVM2SEHRegisterMapping ( X ) ; return X


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> bool <ISA_LIT>DAGToDAGISel :: selectVectorAddr ( SDNode * Parent , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { <ISA_LIT>ISelAddressMode AM ; auto * Mgs = cast < <ISA_LIT>MaskedGatherScatterSDNode > ( Parent ) ; AM . IndexReg = Mgs -> getIndex ( ) ; AM . Scale = cast < ConstantSDNode > ( Mgs -> getScale ( ) ) -> getZExtValue ( ) ; unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) .


<s> SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl


<s> return APV -> isGlobalValue ( ) || APV -> isBlockAddress ( ) || APV -> isLSDA ( ) || APV


<s> Register Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; std :: pair < unsigned , unsigned > Opcodes = getMFHiLoOpc ( Src ) ; if ( ! Opcodes . first ) return false ; return expandCopyACC ( MBB , I , Opcodes . first


<s> static bool isAMXIntrinsic ( Value * I ) { auto * II = dyn_cast < IntrinsicInst > ( I ) ; if ( ! II ) return false ; if ( isAMXCast ( II ) ) return


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT


<s> unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg


<s> return ( __mmask16 ) __builtin_ia32_pcmpeqd512_mask ( ( __v16si ) __A ,


<s> static SDValue lowerUINT_TO_FP_v2i32 ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget , SDLoc & DL ) { if ( Op . getSimpleValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; assert ( N0 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; if ( Subtarget . hasAVX512 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue HalfWord = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfWordMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TWOHW = DAG . getConstantFP ( <NUM_LIT> << <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWord ) ; SDValue LO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ,


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } { const std :: string Func = FuncName ( AccessSize , IsWrite ) ; const MCSymbol * FuncSym = Ctx . GetOrCreateSymbol ( StringRef ( Func ) ) ; const MCSymbolRefExpr * FuncExpr = MCSymbolRefExpr :: Create ( FuncSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( FuncExpr ) ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; { MCInst Inst


<s> else if ( P . has<ISA_LIT>32r5 ( ) ) ISARevision = <NUM_LIT> ; else if ( P . has<ISA_LIT>32r3 ( ) ) ISARevision = <NUM_LIT> ; else if ( P . has<ISA_LIT>32r2 ( ) ) ISARevision = <NUM_LIT> ; else ISARevision = <NUM_LIT> ; } else { ISARevision = <NUM_LIT> ; if ( P . has<ISA_LIT>5 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>4 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>3 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>2 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>1 ( ) ) ISALevel = <NUM_LIT> ; else llvm_unreachable (


<s> break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG


<s> TargetRegistry :: RegisterAsmPrinter (


<s> char nat ; void * t = target -> ireg [ i - <NUM_LIT> ] . loc ; if ( t ) { unw_access_gr ( target , i , & ireg_buf [ i - <NUM_LIT> ] , & nat , <NUM_LIT> ) ; ireg_nat |= ( long ) nat << ( ( ( size_t ) & ireg_buf [ i - <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ) ; ireg_pr |= <NUM_LIT> << i ; } } target -> bsp = ( unsigned long ) ia64_rse_skip_regs ( ( unsigned long * ) target -> bsp , ( * target -> pfs_loc >> <NUM_LIT> ) & <NUM_LIT> ) ; if ( target -> bsp < target -> regstk_top ) target -> rnat = * ia64_rse_rnat_addr ( ( unsigned long * ) target -> bsp ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , rnat ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , bsp ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , psp ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , rp ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , pr ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , gp ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , pfs_loc ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , unat_loc ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , lc_loc ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , fpsr_loc ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context , eh_data ) ) ) ; asm volatile ( <STR_LIT> : : <STR_LIT> ( offsetof ( struct _Unwind_Context ,


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) SavedRegs .


<s> static void trackRegDefsUses ( const MachineInstr & MI , BitVector & ModifiedRegs , BitVector & UsedRegs , const TargetRegisterInfo * TRI ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isRegMask ( ) ) ModifiedRegs . setBitsNotInMask ( MO . getRegMask ( ) ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; if ( MO . isDef ( )


<s> MCInstLowering . Initialize ( Mang , & MF -> getContext (


<s> if ( Subtarget . hasVSX ( ) && RC == & <STR_LIT> ) return & <STR_LIT> ; return


<s> uint64_t C = RHSC -> getZExtValue ( ) ; if ( ! isLegalArithImmed ( C ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C - <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C - <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C - <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C - <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; } } } if ( ! isa < ConstantSDNode > ( RHS ) || ! isLegalArithImmed ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ) ) { SDValue TheLHS = isCMN ( LHS , CC ) ? LHS . getOperand ( <NUM_LIT> ) : LHS ; if ( getCmpOperandFoldingProfit ( TheLHS ) > getCmpOperandFoldingProfit ( RHS ) ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT : Type = ELF :: R_<ISA_LIT>_PLT32 ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_ABS_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_ABS ; break ; case <STR_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setISR ( ) ; return DAG . getNode ( <STR_LIT> ,


<s> if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf64 ) return false ; if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf32 ) return false ; if ( VT == <STR_LIT> ) return false ; return ( AllowI1 && VT == <STR_LIT> ) || TLI .


<s> Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Neg = MIB . buildInstr ( NegOpc , {


<s> if ( Subtarget -> hasV6T2Ops ( ) && isUInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addImm ( CI -> getSExtValue ( ) ) ) ; return DestReg ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align


<s> return isRegIdx ( ) && RegIdx . Kind

& RegKind_CCR && RegIdx . Index <= <NUM_LIT> ;


<s> return selectAddrRegImm16 ( Addr , Base , Offset ) || selectAddrDefault ( Addr , Base


<s> switch ( Kind ) { case FK_Data_4 : return ELF :: R_390_TLS_GD32 ; case FK_Data_8 : return ELF :: R_390_TLS_GD64 ; case <STR_LIT> : return ELF :: R_390_TLS_GDCALL ; } llvm_unreachable ( <STR_LIT>


<s> SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> void printcrbitm ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { unsigned CCReg = MI -> getOperand ( OpNo ) . getReg ( ) ; unsigned RegNo = enumRegToMachineReg (


<s> Optional < DestSourcePair > <ISA_LIT>16InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; return None


<s> Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy ->


<s> assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( imm ) ; SetHiMI -> eraseFromParent ( )


<s> Changed = true ; if ( ! DisableDelaySlotFiller && ( TM . getOptLevel ( ) != CodeGenOpt :: None ) ) { bool Filled = false ; if ( searchBackward ( MBB , I ) ) { Filled = true ; } else if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) { Filled = true ; } } else if ( searchForward ( MBB , I ) ) { Filled = true ; } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI ( I ) ; if ( InMicro<ISA_LIT>Mode && TII -> GetInstSizeInBytes ( std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode (


<s> machine_mode ccmode = SELECT_CC_MODE ( code , x , y ) ; return gen_reg_rtx (


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL ,

unsigned DestReg , unsigned SrcReg , bool KillSrc ) const {


<s> static const struct cc_conv cc_di_convs [ ] = { { NE , <STR_LIT> , <STR_LIT> } , { EQ , <STR_LIT> , <STR_LIT> } , { GE , <STR_LIT> , <STR_LIT> } , { GT , <STR_LIT> , <STR_LIT> } , { LE , <STR_LIT> , <STR_LIT> } , { LT , <STR_LIT> , <STR_LIT> } , { GTU , <STR_LIT> , <STR_LIT> } , { LEU , <STR_LIT> , <STR_LIT> } , CCEND } ; static const struct cc_type_conv cc_convs [ ] = { { CC_FUNmode , cc_fun_convs } , { CC_FPmode , cc_fp_convs } , { CC_FPEQmode , cc_fpeq_convs } , { CC_UNSmode , cc_uns_convs } , { CCmode , cc_signed_convs } , { DImode , cc_di_convs } } ; size_t i ; int j ; machine_mode mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; RTX_CODE cc = GET_CODE ( x ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cc_convs ) ; i ++ ) { if ( mode == cc_convs [ i ] . cc_mode ) { for ( j = <NUM_LIT> ; cc_convs [ i ] . convs [ j ] . cc != UNKNOWN ; j ++ ) if ( cc == cc_convs [ i ] . convs [ j ] . cc ) { const char * mmix_cc = ( reversed ? cc_convs [ i ] . convs [ j ] . reversed : cc_convs [ i ] . convs [ j ] . normal ) ; if ( mmix_cc == NULL ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , mmix_cc ) ; return ; } fatal_insn ( <STR_LIT> , x ) ; } } fatal_insn ( <STR_LIT> , x