<s> case <NUM_LIT> : pat = GEN_FCN ( icode ) ( cmp_result , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , GEN_INT ( cond ) ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( cmp_result , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , GEN_INT ( cond ) ) ; break ; default : gcc_unreachable ( ) ; } if ( builtin_type == MIPS_BUILTIN_CMP_ALL ) { cmp_value = - <NUM_LIT> ; target_if_equal = const1_rtx ; target_if_unequal = const0_rtx ; } else { cmp_value = <NUM_LIT> ; target_if_equal = const0_rtx ; target_if_unequal = const1_rtx ; if ( builtin_type == MIPS_BUILTIN_CMP_UPPER ) cmp_result = simplify_gen_subreg ( CCmode , cmp_result , CCV2mode , <NUM_LIT> ) ; else if ( builtin_type == MIPS_BUILTIN_CMP_LOWER ) cmp_result = simplify_gen_subreg ( CCmode , cmp_result , CCV2mode , <NUM_LIT> ) ; } emit_move_insn ( target , target_if_equal ) ; emit_insn ( pat ) ; label1 = gen_label_rtx ( ) ; label2 = gen_label_rtx ( ) ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( NE , GET_MODE ( cmp_result ) , cmp_result , GEN_INT ( cmp_value ) ) , gen_rtx_LABEL_REF ( VOIDmode


<s> SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane , dl ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( VLdLn ) , { MemOp } ) ; if ( ! IsLoad ) { ReplaceNode ( N , VLdLn ) ; return ; } SuperReg = SDValue ( VLdLn , <NUM_LIT> ) ; static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; unsigned Sub0 = is64BitVector ? <STR_LIT> : <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLdLn , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N )


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : break ; } const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; int64_t Val ; if ( ! Expr -> EvaluateAsAbsolute ( Val ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i !=


__artificial__ ) ) __vis_cmask32 ( long __A ) {


<s> if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == OOmode ) return ( TARGET_MMA && VSX_REGNO_P ( regno ) && ( regno & <NUM_LIT> ) == <NUM_LIT> ) ; if ( mode == XOmode ) return ( TARGET_MMA && FP_REGNO_P ( regno ) && ( regno & <NUM_LIT> ) == <NUM_LIT> ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & <NUM_LIT> ) == <NUM_LIT> ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || mode == TImode || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>0 ( ) { OS << <STR_LIT>


<s> BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr (


<s> static void process_epilogue ( ) { if ( block_num != n_basic_blocks - <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> ) ; need_copy_state = <NUM_LIT> ; } fprintf ( asm_out_file ,


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i + NumElems / <NUM_LIT> ) , i + NumElems ) ) return false ; return


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ( ImmValue & ~ ( ImmValue + <NUM_LIT> ) ) ) { Imm = CurDAG -> getTargetConstant ( ImmValue . countPopulation ( ) , EltTy


<s> void init ( Module & M ) { InsertedThunks = false


<s> break ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mep_intrinsic_insn ) ; i ++ ) mep_intrinsic_insn [ i ] = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cgen_insns ) ; i ++ ) if ( ( cgen_insns [ i ] . isas & mep_selected_isa ) != <NUM_LIT> ) { mep_intrinsic_chain [ i ] = mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] ; mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ]


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo (


<s> } } } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; Dead . insert ( I ) ; } for ( auto * I : Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; I -> eraseFromParent


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_rrrr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill , unsigned Op2 , bool Op2IsKill , unsigned Op3 , bool Op3IsKill ) { const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; unsigned ResultReg = createResultReg ( RC ) ; Op0 = constrainOperandRegClass ( II , Op0 , II . getNumDefs ( ) ) ; Op1 = constrainOperandRegClass ( II , Op1 ,


<s> ReuseLoadInfo RLI ; LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , RLI . Alignment ,

RLI . IsInvariant ? MachineMemOperand :: MOInvariant : MachineMemOperand :: MONone , RLI . AAInfo , RLI . Ranges ) ;


<s> addMemImm8OffsetOperands ( Inst , N )


<s> struct loongarch_address_info addr ; if ( loongarch_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr . reg ) ] ) ; loongarch_print_operand ( file , addr . offset , <NUM_LIT> ) ; return ; case ADDRESS_REG_REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr . reg ) ] , reg_names [ REGNO ( addr . offset ) ] ) ; return ; case ADDRESS_CONST_INT : fprintf ( file , <STR_LIT> , reg_names [ GP_REG_FIRST ] ) ; output_addr_const ( file


<s> EncodedBytes = <NUM_LIT> ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> getFrameLowering ( ) -> getTOCSaveOffset ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes


<s> return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && ( rs6000_function_arg_padding (

TYPE_MODE ( valtype ) , valtype ) == PAD_UPWARD ) ) ;


<s> bool <ISA_LIT>BaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ||


<s> MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; UserMI -> setDesc ( TII -> get ( U . getLongFormOpcode ( ) ) ) ; U . setMaxDisp ( U . getLongFormMaxDisp ( ) ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } } return <NUM_LIT>


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const


<s> if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; MVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; SDValue Elt = DAG . getConstant ( Val , CanonicalVT . getVectorElementType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ReqVT


<s> bool hasSymbolicDisplacement ( ) const { return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT> || JT !=


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 , TheTriple ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( is<ISA_LIT>64 , TheTriple ) ; unsigned Reg = is<ISA_LIT>64 ? <STR_LIT>


<s> MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . EmitInstruction ( Inst ,


<s> PrivateLabelPrefix = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling


<s> bool emit_nop = emit_cbcond_nop ( insn ) ; bool far = false ; const char * rval ; if ( delta < - <NUM_LIT> || delta > <NUM_LIT> ) far = true ; if ( far ) { if ( v9_form ) rval = <STR_LIT> ; else rval = <STR_LIT> ; } else { if ( emit_nop ) rval = <STR_LIT> ; else rval = <STR_LIT>


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) ) , AM ) . addImm ( CI -> getSExtValue ( ) ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> )


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst .

addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys ,


<s> BuildMI ( * MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Renamable ) . addUse ( TmpReg , RegState :: Kill

| RegState :: Renamable ) . addUse ( MisspeculatingTaintReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> unsigned getThumbCBTargetOpValue ( const MachineInstr & MI , unsigned


<s> Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Alignment = LD -> getAlign ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Alignment = LD -> getAlign ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Alignment >= Align ( <NUM_LIT> ) && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset


<s> RTLIB :: Libcall LC = Op . getOpcode ( ) == <STR_LIT> ? RTLIB :: ADD_F128 : RTLIB :: SUB_F128 ; return LowerF128Call ( Op , DAG , LC ) ; } assert ( ( Op . getValueType ( ) == <STR_LIT> || Op . getValueType ( ) == <STR_LIT>


<s> static int aarch64_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; bool fp = false ; if ( vectype != NULL ) fp = FLOAT_TYPE_P ( vectype ) ; const simd_vec_cost * simd_costs = aarch64_simd_vec_costs ( vectype ) ; switch ( type_of_cost ) { case scalar_stmt : return fp ? costs -> scalar_fp_stmt_cost : costs -> scalar_int_stmt_cost ; case scalar_load : return costs -> scalar_load_cost ; case scalar_store : return costs -> scalar_store_cost ; case vector_stmt : return fp ? simd_costs -> fp_stmt_cost : simd_costs -> int_stmt_cost ; case vector_load : return simd_costs -> align_load_cost ; case vector_store : return simd_costs -> store_cost ; case vec_to_scalar : return simd_costs -> vec_to_scalar_cost ; case scalar_to_vec : return simd_costs -> scalar_to_vec_cost ; case unaligned_load : case vector_gather_load : return simd_costs -> unalign_load_cost ; case unaligned_store : case vector_scatter_store : return simd_costs -> unalign_store_cost ; case cond_branch_taken : return costs -> cond_taken_branch_cost ; case cond_branch_not_taken : return costs -> cond_not_taken_branch_cost ; case vec_perm : return simd_costs -> permute_cost ; case vec_promote_demote : return fp ? simd_costs -> fp_stmt_cost : simd_costs ->


<s> case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerCompactBranch ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } if ( ( ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( ) == <STR_LIT> ) ) ) { unsigned RegPair = getMovePRegPairOpValue ( MI , <NUM_LIT> , Fixups , STI ) ; Binary = ( Binary & <NUM_LIT> ) | ( RegPair <<


<s> default : Inst . setLoc ( IDLoc ) ; Instructions . push_back ( Inst ) ; break ; case <STR_LIT> : if ( expandSET ( Inst , IDLoc , Instructions ) ) return true ; break ; } for ( const MCInst & I : Instructions ) { Out . emitInstruction ( I , getSTI ( ) ) ; } return false ; } case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [


<s> if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * GVSym ; else O << '(' << * GVSym << ')' ; P . printOffset ( MO . getOffset ( ) , O ) ; break ; } } switch ( MO . getTargetFlags ( )


<s> MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister (


<s> Inst . addOperand ( MCOperand :: createReg ( SaveLocation ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( GPReg ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> )


<s> bool <ISA_LIT>TargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = <NUM_LIT> ; if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) , RHSKnown ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } } } return


<s> void <ISA_LIT>InstPrinter :: printSystemPStateField ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << StringRef ( Name . str ( ) ) . upper


<s> return Expr -> findAssociatedFragment


<s> <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( )


<s> machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = <NUM_LIT> ; } else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno


<s> if ( WaterIsInRange ( UserOffset , WaterBB , U ) ) { if ( isThumb && ( BBOffsets [ WaterBB -> getNumber ( ) ] + BBSizes [ WaterBB -> getNumber ( ) ] ) % <NUM_LIT> != <NUM_LIT> ) { if ( ! WaterBBThatWouldPad ) { WaterBBThatWouldPad = WaterBB ; IPThatWouldPad = IP ; } } else { * NewMBB = AcceptWater ( WaterBB , IP


<s> while ( len >= <NUM_LIT> ) { emit_insn ( gen_movmem12b ( out , in , out , in ) ) ; len -= <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { emit_insn ( gen_movmem8b ( out , in , out , in ) ) ; len -= <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= <NUM_LIT> ; offset += <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( out , offset ) ) , reg ) ) ; len -= <NUM_LIT> ; offset += <NUM_LIT> ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( in ,


<s>
case
NearMissInfo
::
NearMissFeature
:
{
const
FeatureBitset
&
MissingFeatures
=
I
.
getFeatures
(
)
;
if
(
FeatureMissesSeen
.
count
(
MissingFeatures
)
)
break
;
FeatureMissesSeen
.
insert
(
MissingFeatures
)
;
if
(
MissingFeatures
.
test
(
Feature_Is<ISA_LIT>Bit
)
&&
!
has<ISA_LIT>
(
)
)
break
;
if
(
isThumb
(
)
&&
MissingFeatures
.
test
(
Feature_Is<ISA_LIT>Bit
)
&&
MissingFeatures
.
count
(
)
>
<NUM_LIT>
)
break
;
if
(
!
isThumb
(
)
&&
MissingFeatures
.
test
(
Feature_IsThumbBit
)
&&
MissingFeatures
.
count
(
)
>
<NUM_LIT>
)
break
;
if
(
!
isThumb
(
)
&&
MissingFeatures
.
test
(
Feature_IsThumb2Bit
)
&&
(
MissingFeatures
&
~
FeatureBitset
(
{
Feature_IsThumb2Bit
,
Feature_IsThumbBit
}
)
)
.
any
(
)
)
break
;
if
(
isMClass
(
)
&&
MissingFeatures
.
test
(
Feature_HasNEONBit
)
)
break
;
NearMissMessage
Message
;
Message
.
Loc
=
IDLoc
;
raw_svector_ostream
OS
(
Message
.
Message
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
,
e
=
MissingFeatures
.
size
(
)
;
i
!=
e
;
++
i
)
if
(
MissingFeatures
.
test
(
i
)
)
OS
<<
' '
<<
getSubtargetFeatureName
(
i
)
;
NearMissesOut
.
emplace_back
(
Message
)
;
break
;
}
case
NearMissInfo
::
NearMissPredicate
:
{
NearMissMessage
Message
;
Message
.
Loc
=
IDLoc
;
switch
(
I
.
getPredicateError
(
)
)
{
case
Match_RequiresNotITBlock
:
Message
.
Message
=
<STR_LIT>
;
break
;
case
Match_RequiresITBlock
:
Message
.
Message
=
<STR_LIT>
;
break
;
case
Match_RequiresV6
:
Message
.
Message
=
<STR_LIT>
;
break
;
case
Match_RequiresThumb2
:
Message
.
Message


<s> int <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * SrcVTy , Value * Ptr , bool VariableMask , unsigned Alignment ) { assert ( SrcVTy -> isVectorTy ( ) && <STR_LIT> ) ; unsigned VF = SrcVTy -> getVectorNumElements ( ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) -> getVectorElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ; if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy , VariableMask , Alignment , AddressSpace ) ; return getGSVectorCost ( Opcode , SrcVTy , Ptr , Alignment ,


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useDwarfDirectory ,

MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) {


<s> MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; GVSym -> setContainingCsect ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect ->


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4 ) ( si_from_int ( b ) )


<s> if ( SrcReg != <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) , FrameIdx ) ) ; } else { NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , false , false , isKill ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { if ( SrcReg != <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) , FrameIdx ) ) ; } else { NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , false , false , isKill ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> )


<s> if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_DEC ) ) \ REG_NOTES ( INSN ) = gen_rtx_EXPR_LIST ( REG_INC , \ XEXP ( XEXP ( EXP , <NUM_LIT> ) , <NUM_LIT> ) , \ REG_NOTES ( INSN ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ <NUM_LIT> ] , in [ <NUM_LIT> ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ <NUM_LIT> ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ <NUM_LIT> ] ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ <NUM_LIT> ] , in [ <NUM_LIT> ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in


<s> const TargetMachine & TM = MI -> getParent ( ) -> getParent ( ) -> getTarget ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && ( LastMI -> mayLoad ( ) || LastMI -> mayStore ( ) ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = llvm :: prior ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo ( ) ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls = <NUM_LIT> ; return Hazard


<s> void arm_output_fn_unwind ( FILE * f , bool prologue ) { if ( arm_except_unwind_info ( & global_options ) != UI_TARGET


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT>


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts )


<s> rtx tmpcount = gen_reg_rtx ( GET_MODE ( variable ) ) ; if ( GET_MODE ( variable ) == DImode ) emit_insn ( gen_anddi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value )


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) && ! Subtarget -> isTargetWindows


<s> int NumElts = Mask . size ( ) ; int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV32I16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV64I8Shuffle ( DL , Mask , Zeroable , V1


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INTDirectMove ( SDValue Op , SelectionDAG & DAG , const SDLoc & dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getSimpleValueType ( ) . SimpleTy , convertFPToInt ( Op , DAG ,


<s> FunctionPass * llvm :: create<ISA_LIT>LowerAMXTypePass ( ) { return new <ISA_LIT>LowerAMXTypeLegacyPass ( )


<s> void <ISA_LIT>TargetELFStreamer :: emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; if ( ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> <NUM_LIT> ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol


<s> __rv . __o = __builtin_neon_vld2di ( ( const __builtin_neon_di * )


<s> MVT VT = Op1 . getSimpleValueType ( ) ; MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , EVT ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , ULTOp1 . data ( )


<s> const <ISA_LIT>AuthMCExpr * <ISA_LIT>AuthMCExpr :: create ( const MCExpr * Expr , uint16_t Discriminator , <STR_LIT> Key , bool HasAddressDiversity , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>AuthMCExpr ( Expr , Discriminator , Key ,


<s> bool <ISA_LIT>16InstrInfo :: validImmediate ( unsigned Opcode , unsigned Reg , int64_t Amount ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( Amount ) ; case <STR_LIT> : if ( ( Reg == <STR_LIT> ) || ( Reg == <STR_LIT> ) ) return isInt < <NUM_LIT> > ( Amount ) ; return isInt < <NUM_LIT> > (


<s> LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset


<s> <ISA_LIT>MCAsmInfoGNUCOFF :: <ISA_LIT>MCAsmInfoGNUCOFF ( const Triple & Triple ) { assert ( Triple . isOSWindows ( ) && <STR_LIT> ) ; if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CodePointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling :: WinEH ; } else { ExceptionsType = ExceptionHandling :: DwarfCFI ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; AllowAtInName = true


<s> SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; EVT SubVT = <STR_LIT> ( ElType , NumElts ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT ) ; for ( unsigned i = Index , j = <NUM_LIT> ; i < ( Index + NumElts ) ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV1 , DAG . getIntPtrConstant ( i , dl ) ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT , SubVec , Elt , DAG .


<s> unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; high = ( highp ? <NUM_LIT>


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectPostStore ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand


<s> void <ISA_LIT>AsmParser :: cvtVSTwbFixed ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAlignedMemoryOperands ( Inst , <NUM_LIT>


<s> if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return Fail ; DecodeZPRRegisterClass ( Inst , Zdn , Addr , Decoder ) ; DecodeZPRRegisterClass ( Inst , Zdn , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return Success


<s> bool isMachineVerifierClean ( ) const


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , DstVT ) ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { EVT DestVT = <STR_LIT> ; SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , DestVT , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return


<s> AU . addRequired < VirtRegMap > ( ) ; AU . addRequired < LiveIntervals


<s> else if ( CSKY_TARGET_ARCH ( CK803 ) ) return ck803_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK807 ) || CSKY_TARGET_ARCH ( CK810 ) ) return ck807_ck810_rtx_costs ( x , code , outer_code , total ,


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X (


<s> if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Start , Mask [ i ] + l ) ) return false ; if ( Start >= ( int ) NumElts ) Start -= NumElts - NumLaneElts ; if ( Start <= ( int ) ( i + l ) ) return false ; Start -= i ; for ( ++ i ; i != NumLaneElts ; ++ i ) { int Idx = Mask [ i + l ] ; if ( ! isUndefOrInRange ( Idx , l , l + NumLaneElts ) && ! isUndefOrInRange ( Idx , l + NumElts , l + NumElts + NumLaneElts ) ) return false ; if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Idx ,


<s> virtual unsigned int execute ( function


<s> if ( PairedIsUnscaled ) { assert ( ! ( PairedOffset % getMemScale ( * Paired ) ) && <STR_LIT> ) ; PairedOffset /= MemSize ; } else { PairedOffset *= MemSize ; } } MachineInstr * RtMI , * Rt2MI ; if ( Offset == PairedOffset + OffsetStride ) { RtMI = & * Paired ; Rt2MI = & * I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = & * I ; Rt2MI = & * Paired ; } int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( TII -> isUnscaledLdSt ( RtMI -> getOpcode ( ) ) ) { assert ( ! ( OffsetImm % getMemScale ( * RtMI ) ) && <STR_LIT> ) ; OffsetImm /= getMemScale ( * RtMI ) ; } MachineInstrBuilder MIB ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . addOperand ( getLdStRegOp ( * RtMI ) ) . addOperand ( getLdStRegOp ( * Rt2MI ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * Paired ) ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; } else { DEBUG ( ( ( MachineInstr * ) MIB ) -> print


<s> } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } EmitAndCountInstruction ( LEA ) ; if ( needsPadding ) { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT>


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI ) { printInstruction (


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( )


<s> SDValue RHS = DAG . getAnyExtOrTrunc ( DAG . getBitcast ( IntTy , N -> getOperand ( <NUM_LIT> ) ) , DL , ExtIntTy ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue Splice = DAG . getNode ( <STR_LIT> , DL , ExtIntTy , LHS , RHS , Idx ) ; SDValue Trunc = DAG . getAnyExtOrTrunc ( Splice , DL , IntTy ) ; return DAG . getBitcast ( Ty , Trunc


<s> } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) SumV2Indices += i ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) NumV1OddIndices += i % <NUM_LIT> ; if ( NumV2OddIndices < NumV1OddIndices ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; } } } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return lower128BitVectorShuffle ( Op , V1


<s> if ( NumLoads > <NUM_LIT> ) return false ; if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI (


<s> const <ISA_LIT>RegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; if ( TRI -> getSubRegIndex ( NewSrcReg , OldSrc . getReg ( ) ) != TRI -> getSubRegIndex ( NewDestReg , OldDest . getReg ( ) ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewDestReg ) . addReg ( NewSrcReg , RegState :: Undef ) . addReg ( OldSrc . getReg ( ) , RegState :: Implicit ) ; for ( auto & Op : MI -> implicit_operands ( ) ) if ( Op . getReg ( ) != ( Op . isDef ( ) ? NewDestReg : NewSrcReg ) ) MIB . add ( Op ) ; return MIB


<s> inline vector unsigned short vec_packsu ( vector signed


<s> switch ( type ) { case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; } if ( ShOp == <STR_LIT> && imm == <NUM_LIT> ) ShOp = <STR_LIT> ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned shift ; if ( U ) shift = <STR_LIT> ( <STR_LIT> , imm , ShOp ) ; else shift = <STR_LIT> ( <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_pmovzxbd512_mask ( ( __v16qi ) __A , ( __v16si )

_mm512_undefined_si512 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>MCInstrAnalysis (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true


<s> for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator II = DefSrcs . begin ( ) , EE = DefSrcs . end ( ) ; II != EE ; ++ II ) { MachineInstr * MI = * II ; if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & I . getOperand ( ) ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVector < MachineOperand * , <NUM_LIT> > :: const_iterator I = Uses . begin ( ) , E = Uses . end (


<s> } Vec = { Imm } ; if ( isSVECpyImm ( Vec . D ) ) return false ; if ( isSVEMaskOfIdenticalElements < int32_t > ( Imm ) && isSVECpyImm ( Vec . S [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int16_t > ( Imm ) && isSVECpyImm ( Vec . H [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int8_t > ( Imm ) && isSVECpyImm ( Vec . B [ <NUM_LIT> ] ) ) return false ; return isLogicalImmediate ( Vec . D , <NUM_LIT>


<s> if ( skipFunction ( * F . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed


<s> } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else assert (


<s> Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; case <NUM_LIT> : Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( isa < ConstantInt > ( II -> getArgOperand ( <NUM_LIT> ) ) ) Row = Builder . getInt16 ( ( cast < ConstantInt > ( II -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ) / <NUM_LIT> ) ; else if ( isa < Instruction > ( II -> getArgOperand ( <NUM_LIT> ) ) ) { Builder . SetInsertPoint ( cast < Instruction > ( II -> getOperand ( <NUM_LIT> ) ) ) ; Row = Builder . CreateUDiv ( II -> getOperand ( <NUM_LIT> ) , Builder . getInt16 ( <NUM_LIT> ) ) ; cast < Instruction > ( Row ) -> moveAfter ( cast < Instruction > ( II -> getOperand ( <NUM_LIT> ) ) ) ; } else { IRBuilder < > NewBuilder ( getFirstNonAllocaInTheEntryBlock ( * II -> getFunction ( ) ) ) ; Row = NewBuilder . CreateUDiv ( II -> getOperand ( <NUM_LIT> ) , NewBuilder . getInt16 ( <NUM_LIT> ) ) ; } Col = II -> getArgOperand ( <NUM_LIT>


<s> if ( ( rotr32 ( <NUM_LIT> , RotAmt ) & V ) == V ) return ( rotr32 ( V , <NUM_LIT> -

RotAmt ) & <NUM_LIT> ) | ( ( RotAmt + <NUM_LIT> ) << <NUM_LIT> ) ;


<s> tree fields [ <NUM_LIT> ] ; return ( TARGET_NEWABI && TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) &&

mips_fpr_return_fields ( valtype , fields ) == <NUM_LIT> ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { assert ( <NUM_LIT> &&


<s> DebugLoc DL = MIB -> getDebugLoc ( ) ; int64_t Imm = MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Imm != <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; int StackAdjustment ; if ( Subtarget . is64Bit ( ) ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> || MIB -> getOpcode ( ) == <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> getUsesRedZone ( ) ) { MIB -> setDesc ( TII . get ( MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo


<s> ( void ) DstSz ; assert ( DstSz < SrcSz && SrcSz <= <NUM_LIT> && DstSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base ( ) ) && <STR_LIT> ) ; SDLoc Loc ( Op ) ; if ( SrcSz == <NUM_LIT> && Subtarget -> hasFP16 ( ) ) return Op ; RTLIB :: Libcall LC = RTLIB :: getFPROUND ( SrcVT , DstVT ) ; assert ( LC != RTLIB


<s> const LLT DstTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto LaneIdx = getSplatIndex ( MI ) ; if ( ! LaneIdx ) return false ; if ( * LaneIdx >= SrcTy . getNumElements ( ) ) return false ; if ( DstTy != SrcTy ) return false ; LLT ScalarTy = SrcTy . getElementType ( ) ; unsigned ScalarSize = ScalarTy . getSizeInBits ( ) ; unsigned Opc = <NUM_LIT> ; switch ( SrcTy . getNumElements ( ) ) { case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> )


<s> NonZeros |= ( uint64_t ) <NUM_LIT> << i ; ++ NumNonZero ; } } if ( NumNonZero <= <NUM_LIT> ) { SDValue Vec = NumZero ? getZeroVector ( ResVT , Subtarget , DAG , dl ) : DAG . getUNDEF ( ResVT ) ; if ( ! NumNonZero ) return Vec ; unsigned Idx = countTrailingZeros ( NonZeros ) ; SDValue SubVec = Op . getOperand ( Idx ) ; unsigned SubVecNumElts = SubVec . getSimpleValueType ( ) . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , SubVec , DAG . getIntPtrConstant ( Idx * SubVecNumElts , dl ) ) ; } if ( NumOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; ArrayRef < SDUse > Ops = Op -> ops ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( <NUM_LIT> , NumOperands / <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( NumOperands / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } assert ( NumNonZero == <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getVectorNumElements ( ) >= <NUM_LIT> ) return Op ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getUNDEF ( ResVT ) , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( NumElems / <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerToBT ( SDValue And , <STR_LIT> CC , DebugLoc dl , SelectionDAG & DAG ) const { if ( Subtarget -> isTargetNaCl ( ) ) return SDValue ( ) ; SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Zeros , Ones ; DAG . ComputeMaskedBits ( Op0 , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS


<s> rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX


<s> bool <ISA_LIT>InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = * MBB . getParent


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) { DebugLoc dl = GA -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry


<s> if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; } } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand (


<s> Error ( Reg . StartLoc , <STR_LIT> ) ; return true ; } else if ( Reg . Num == <NUM_LIT> ) { Error ( Reg . StartLoc ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> Inst . addOperand ( MCOperand :: createImm ( getCondCode ( ) )


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get


<s> return ( uint16x4x2_t ) { vtrn1_u16 ( a , b ) , vtrn2_u16 ( a , b


<s> Register BasePtr = TRI -> getBaseRegister ( ) ; if ( STI . isTarget64BitILP32 ( ) ) BasePtr =

get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ;


<s> return ResolveFrameIndexReference ( MF , FI , FrameReg ,


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> return ( __m256 ) __builtin_ia32_vpermt2varps256_mask ( ( __v8si ) __I , ( __v8sf ) __A , (


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) emit_window_save ( size_int_rtx ) ; else if ( size <= <NUM_LIT> ) { emit_window_save ( GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg =


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DataLayout DT = I -> getParent ( ) -> getParent ( ) -> getParent ( ) -> getDataLayout ( ) ; int TypeScale = computeScale ( DT . getTypeSizeInBits ( GEP -> getOperand ( <NUM_LIT> ) -> getType ( ) ) , DT . getTypeSizeInBits ( GEP -> getType ( ) ) / cast < FixedVectorType > ( GEP -> getType ( ) ) -> getNumElements ( ) ) ; if ( TypeScale == - <NUM_LIT> ) return nullptr ; if ( GEP -> hasOneUse ( ) ) { Value * Load = tryCreateIncrementingWBGatScat ( I , BasePtr , Offsets , TypeScale , Builder ) ; if ( Load != nullptr ) return Load ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; std :: pair < Value * , int64_t > Add = getVarAndConst ( Offsets , TypeScale ) ; if ( Add . first == nullptr ) return nullptr ; Value * OffsetsIncoming = Add . first ; int64_t Immediate = Add . second ; Instruction * ScaledOffsets = BinaryOperator :: Create ( Instruction :: Shl , OffsetsIncoming , Builder . CreateVectorSplat ( Ty -> getNumElements ( ) , Builder . getInt32 ( TypeScale ) ) , <STR_LIT> , I ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Add , ScaledOffsets , Builder . CreateVectorSplat ( Ty -> getNumElements ( ) , Builder . CreatePtrToInt ( BasePtr , cast < VectorType > ( ScaledOffsets -> getType ( ) ) -> getElementType ( ) ) ) , <STR_LIT> , I ) ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) return cast < IntrinsicInst > ( tryCreateMaskedGatherBase ( I , OffsetsIncoming , Builder , Immediate ) ) ; else return cast < IntrinsicInst > ( tryCreateMaskedScatterBase ( I


<s> return MI . modifiesRegister ( <STR_LIT> , NULL ) || MI . modifiesRegister


<s> if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; return SegmentOffset ( IRB , Offset , getAddressSpace (


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> SDValue NewConcat = DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ; ++ n ) { int MaskElt = SVN -> getMaskElt ( n ) ; int NewElt = - <NUM_LIT> ; if ( MaskElt < ( int ) HalfElts ) NewElt


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> if ( ShOpc == <STR_LIT> || ( ShOpc == <STR_LIT> && ! ShImm ) ) return ; O << <STR_LIT> ; assert ( ! ( ShOpc == <STR_LIT> &&


<s> assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; if ( const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { MCFixupKind Kind = ( MCFixupKind ) SExpr -> getFixupKind ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind ) ) ; return <NUM_LIT> ; } int64_t Res ; if ( Expr -> evaluateAsAbsolute ( Res ) ) return Res ; llvm_unreachable ( <STR_LIT> )


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , MaskVT ) ; else MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , MaskInReg , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; return SDValue ( Res , <NUM_LIT>


<s> break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I . getOperand ( op ) . getIndex ( ) ; if ( I . getOperand ( op ) . isJTI ( ) ) { JumpTableUserIndices . insert ( std :: make_pair ( CPI , CPUsers . size ( ) ) ) ; CPI = JumpTableEntryIndices [


<s> return ( __a - ( __b * __aarch64_vget_lane_any (


<s> void i386_pe_asm_lto_end ( void ) { debug_info_level =


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT>


<s> MachineOperand & MO = Iter -> getOperand ( j ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) SeenDef = true ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { if ( MO . isUse ( ) ) return false ; SeenDef = true ; } } if ( SeenDef ) return true ; ++ Iter ; while ( Iter != E && Iter -> isDebugValue ( ) ) ++ Iter ; } if ( Iter == E ) { for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugValue ( ) ) -- Iter ; bool SawKill = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand ( j ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) SawKill = true ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { if ( MO . isDef ( ) ) return


<s> return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ECX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RegNo - <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case


<s> unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( Rm == <NUM_LIT> ) S = MCDisassembler ::


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv8hi (


<s> case <STR_LIT> : case <STR_LIT> : UsedFlags . C = true ; break ; case <STR_LIT> : case <STR_LIT> : UsedFlags . N = true ; break ; case <STR_LIT> : case <STR_LIT> : UsedFlags . V = true ; break ; case <STR_LIT> : case <STR_LIT> : UsedFlags . Z = true ; case <STR_LIT> : case <STR_LIT> : UsedFlags . N = true ; UsedFlags . V


<s> r3 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r3 = gen_rtx_EXPR_LIST ( VOIDmode , r3 , GEN_INT ( <NUM_LIT> ) ) ; r5 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r5 = gen_rtx_EXPR_LIST ( VOIDmode , r5 , GEN_INT ( <NUM_LIT> ) ) ; r7 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r7 = gen_rtx_EXPR_LIST ( VOIDmode , r7 , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1 , r3 , r5 , r7 ) ) ; default : gcc_unreachable ( )


<s> dbgs ( ) << <STR_LIT> ; Header -> dump ( ) ; dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; bool Changed = false ; ReductionList Reductions = MatchReductions ( F , L , Header ) ; for ( auto & R : Reductions ) { ParallelMACList MACCandidates = MatchParallelMACs ( R ) ; if ( ! SetMemoryLocations ( MACCandidates ) ) continue ; Instructions Aliases = AliasCandidates ( Header , MACCandidates ) ; if ( AreAliased ( AA , Aliases ,


<s> break ; case ADDRESS_POST_INC_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_MODIFY_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_FP_IMM7U : output_asm_insn ( <STR_LIT> , operands ) ; break ; case ADDRESS_SP_IMM7U


<s> default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; if ( SwapArgs ) std :: swap


<s> pinsrh_3_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_pinsrh_3_s ( s ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size (


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetImmPre ( SDNode * Op , SDValue N , SDValue & Offset


<s> void aarch64_expand_sve_vec_cmp_int ( rtx target , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; if ( ! aarch64_sve_cmp_operand_p ( code , op1 ) ) op1 = force_reg ( data_mode ,


<s> static DecodeStatus DecodeT2AddrModeImm12 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode


<s> const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg , Op1IsKill , Mask ) ; Op1IsKill = true ; } unsigned ResultReg = fastEmitInst_rr ( Opc , RC , Op0Reg , Op0IsKill , Op1Reg , Op1IsKill ) ; if ( NeedTrunc ) ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , true , Mask ) ; return


<s> return ( __m128i ) __builtin_ia32_vphadduwq (


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> && Op1 . getOpcode ( ) != <STR_LIT> && Op1 . getOpcode ( ) != <STR_LIT> && Op2 . getOpcode


<s> ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregxiv2si


<s> icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op0 ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op1 ) ; start_sequence ( ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) { end_sequence ( ) ; return NULL_RTX


<s> case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; case Match_InvalidUImm8 : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; case Match_InvalidUImm16 : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> ) ; case Match_InvalidFloatRoundMode : ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ; case Match_InvalidWyde


<s> addPass ( new InstructionSelect ( ) ) ; return false


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crc32w ( unsigned int __C , unsigned short __V ) { return __builtin_ia32_crc32hi ( __C ,


<s> static HOST_WIDE_INT get_jump_table_size ( rtx insn ) { if ( JUMP_TABLES_IN_TEXT_SECTION || <NUM_LIT> ) { rtx body = PATTERN ( insn ) ; int elt = GET_CODE ( body ) == ADDR_DIFF_VEC ? <NUM_LIT>


<s> SDLoc dl ( N ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ) ; } } if ( SDValue V = combineParity ( N , DAG , Subtarget ) ) return V ; if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps ) && SrcOps . size ( ) == <NUM_LIT> ) { SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { APInt AllBits = APInt :: getAllOnesValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT>


<s> if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = <NUM_LIT> / Amt . getScalarValueSizeInBits ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio , e = Amt . getNumOperands ( ) ; i != e ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [ j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ; } if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Op . getOpcode ( ) ) ) return DAG . getNode (

<ISA_LIT>OpcV , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ;


<s> else if ( DEFAULT_ABI == ABI_V4 ) sprintf ( str , <STR_LIT> , sibcall ? <STR_LIT> : <STR_LIT> , z , arg , flag_pic ? <STR_LIT> : <STR_LIT> ) ; else if ( DEFAULT_ABI == ABI_DARWIN ) { gcc_checking_assert ( GET_CODE ( operands [ funop + <NUM_LIT> ] ) == CONST_INT ) ; int cookie = INTVAL ( operands [ funop + <NUM_LIT> ] ) ; if ( cookie & CALL_LONG ) { tree funname = get_identifier ( XSTR ( operands [ funop ] , <NUM_LIT> ) ) ; tree labelname = get_prev_label ( funname ) ; gcc_checking_assert ( labelname && ! sibcall ) ; sprintf ( str , <STR_LIT> , funop , IDENTIFIER_POINTER ( labelname ) ) ; } else sprintf ( str , <STR_LIT> , sibcall ? <STR_LIT> : <STR_LIT> , z , arg ) ; } else gcc_unreachable (


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < <NUM_LIT> ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck


<s> vld4_dup_s16 ( const int16_t * __a ) { int16x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o


<s> auto Fn = MI . getParent ( ) -> getParent ( ) -> getFunction ( ) ; auto Attr = Fn ->


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType

( ) . getSimpleVT ( ) != <STR_LIT> ) return TypeWidenVector ;


<s> static MachineInstr * genFusedMultiplyIdx ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root

, SmallVectorImpl < MachineInstr * > & InsInstrs , unsigned IdxMulOpd , unsigned MaddOpc , const TargetRegisterClass * RC ) {


<s> int m16_nuimm8_1 ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return m16_check_op ( op , - <NUM_LIT> , <NUM_LIT> ,


<s> MachineInstr * MI2 = MRI . getUniqueVRegDef ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AssocOpcode = Inst . getOpcode ( ) ; Commuted = MI1 -> getOpcode ( ) != AssocOpcode && MI2 -> getOpcode ( ) == AssocOpcode ; if ( Commuted ) std :: swap ( MI1 , MI2 ) ; if ( MI1 -> getOpcode ( ) == AssocOpcode && hasVirtualRegDefsInBasicBlock ( * MI1 , MBB ) && MRI . hasOneNonDBGUse ( MI1 -> getOperand ( <NUM_LIT> ) . getReg


<s> bool isSubregFoldable ( ) const override { return


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get (


<s> PBQPRAGraph :: NodeId node1 = G . getMetadata ( ) . getNodeIdForVReg ( Rd ) ; const LiveInterval & ld = LIs . getInterval ( Rd ) ; for ( auto r : Chains ) { if ( r == Rd ) continue ; const LiveInterval & lr = LIs . getInterval ( r ) ; if ( ld . overlaps ( lr ) ) { const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRdAllowed = & G . getNodeMetadata ( node1 ) . getAllowedRegs ( ) ; PBQPRAGraph :: NodeId node2 = G . getMetadata ( ) . getNodeIdForVReg ( r ) ; const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRrAllowed = & G . getNodeMetadata ( node2 ) . getAllowedRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; assert ( edge != G . invalidEdgeId ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_64BIT ) return false ; if ( TARGET_PORTABLE_RUNTIME ) return false ; return decl && targetm . binds_local_p


<s> Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI . getOperand


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { assert ( Offset <= INT_MAX &&


<s> if ( GET_CODE ( op0 ) == REG && GR_REGNO_P ( REGNO ( op0 ) ) ) { rtx out [ <NUM_LIT> ] ; gcc_assert ( ! no_new_pseudos ) ; if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == SUBREG && GET_MODE ( SUBREG_REG ( operands [ <NUM_LIT> ] ) ) == TImode ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GR_REGNO_P ( REGNO ( operands [ <NUM_LIT> ] ) ) ) ) { rtx op1 = operands [ <NUM_LIT> ] ; if ( GET_CODE ( op1 ) == SUBREG ) op1 = SUBREG_REG ( op1 ) ; else op1 = gen_rtx_REG ( TImode , REGNO ( op1 ) ) ; emit_move_insn ( gen_rtx_REG ( TImode , REGNO ( op0 ) ) , op1 ) ; return true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE ) { emit_move_insn ( gen_rtx_REG ( DImode , REGNO ( op0 ) ) , operand_subword ( operands [ <NUM_LIT> ] , WORDS_BIG_ENDIAN , <NUM_LIT> , mode ) ) ; emit_move_insn ( gen_rtx_REG ( DImode , REGNO ( op0 ) + <NUM_LIT> ) , operand_subword ( operands [ <NUM_LIT> ] , ! WORDS_BIG_ENDIAN , <NUM_LIT> , mode ) ) ; return true ; } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) operands [ <NUM_LIT> ] = spill_xfmode_rfmode_operand ( operands [ <NUM_LIT> ] , <NUM_LIT> , mode ) ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) ; out [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( op0 ) ) ; out [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( op0 ) + <NUM_LIT> ) ; emit_move_insn ( out [ <NUM_LIT> ] , adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ) ; emit_move_insn ( out [ <NUM_LIT> ] , adjust_address ( operands [ <NUM_LIT> ]


<s> if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT>


<s> TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & The<ISA_LIT>LETarget , & TheThumbLETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; for ( Target * T : { & The<ISA_LIT>BETarget , & TheThumbBETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend (


<s> if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OL != CodeGenOpt :: None ) { if ( ! FullFS . empty ( ) ) FullFS


<s> for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> << unsigned ( BBI . PostAlign ) <<

format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> if ( enough_regs_for_param ( cum , type , mode ) != <NUM_LIT> ) { last_parm_in_reg = <NUM_LIT> ; return gen_rtx_REG ( mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } if ( MIN_REG_FOR_PASSING_ARGS + cum -> ints > MAX_REG_FOR_PASSING_ARGS ) return NULL_RTX ; else { if ( enough_regs_for_param ( cum , type , mode ) != <NUM_LIT> ) { last_parm_in_reg = <NUM_LIT> ; return gen_rtx_REG ( mode , MIN_REG_FOR_PASSING_ARGS + cum


<s> SmallVector < SDValue , <NUM_LIT> > Res ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op0 ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op1 ( MaxFactor ) ; unsigned Factors = <NUM_LIT> ; Op0 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; Op1 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; for ( ; Factors < MaxFactor ; Factors *= <NUM_LIT> ) { VT = getDoubleWidthHalfCountVectorVT ( DAG , VT ) ; for ( unsigned i = Factors ; i > <NUM_LIT> ; -- i ) { Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtLoOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op1 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op1 [ i - <NUM_LIT> ] ) ; Op1 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtLoOpc , DL , VT , Op1 [ i - <NUM_LIT> ] ) ; } } for ( unsigned i = <NUM_LIT> ; i < Factors ; ++ i ) Res [ i ] = DAG . getNode ( Op . getOpcode ( ) , DL , VT , Op0 [ i ] , Op1 [ i ] ) ; for ( ; Factors > <NUM_LIT> ; Factors /= <NUM_LIT> ) { VT = getHalfWidthDoubleCountVectorVT ( DAG ,


<s> aarch64_print_hint_for_core_or_arch ( str , false


<s> } Type * ArgTy = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint64_t ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = <NUM_LIT> ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr , MachinePointerInfo ( V ) , false , false , <NUM_LIT> ) ; if ( NeedFPTrunc ) { SDValue WideFP = DAG . getLoad ( <STR_LIT> , DL , APStore , VAList , MachinePointerInfo ( ) , false


<s> void printqwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI ,


<s> if ( speed_p ) { if ( current_pass -> tv_id == TV_FWPROP ) return nds32_address_cost_speed_fwprop ( address


<s> static unsigned getLEArOpcode ( bool IsLP64 ) { return IsLP64 ? <STR_LIT> :


<s> <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( VT , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { unsigned Opc = VT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , VT , RepeatedMask , V1 , V2 , DAG ) ; } if ( SDValue Op = lowerVectorShuffleWithVALIGN ( DL , VT , Mask , V1 ,


<s> return ( __mmask8 ) __builtin_ia32_cmpq512_mask ( ( __v8di ) __X , (


<s> } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } if ( PointerType * Ty = dyn_cast < PointerType > ( Obj -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = GTI . getStructTypeOrNull ( ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > (


<s> bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT


<s> if ( TM . getOptLevel ( ) == CodeGenOpt ::


<s> SDValue <ISA_LIT>TargetLowering :: ExtractBitFromMaskVector ( SDValue Op , SelectionDAG & DAG ) const { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Vec ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT EltVT = Op . getSimpleValueType ( ) ; assert ( ( EltVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget -> hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl


<s> assert ( Current != - <NUM_LIT> ) ; Current = Set . V . find_next (


<s> } else { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; } report_fatal_error ( <STR_LIT>


<s> O << <STR_LIT> ; O . write_hex ( <STR_LIT> ( Val


<s> void <ISA_LIT>AsmParser :: setFpFormat ( StringRef Format ) { FpFormat = StringSwitch < FpFormatTy > ( Format . lower ( ) ) . Case ( <STR_LIT> , FP_FORMAT_S ) . Case ( <STR_LIT> , FP_FORMAT_D ) . Case ( <STR_LIT> , FP_FORMAT_L

) . Case ( <STR_LIT> , FP_FORMAT_W ) . Default ( FP_FORMAT_NONE ) ;


<s> bool vectorizePreventedSLForwarding ( void ) { return ST ->


<s> } if ( ( AM . BaseType == <STR_LIT> || AM . GV ) && ( ( AM . BaseType == <STR_LIT> && AM . Base . Reg ) || AM . IndexReg ) && AM . Disp > <NUM_LIT> ) { ++ NumFastIselNaClFailures ; return false ; } if ( ( AM . BaseType == <STR_LIT> ) && AM . Base . Reg && AM . IndexReg ) { ++ NumFastIselNaClFailures ; return


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE ->