<s> } if ( scalar_copy ) { start_sequence ( ) ; if ( ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( tmp , reg ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } else if ( TARGET_SSE4_1 ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , reg , <NUM_LIT> ) , tmp ) ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , reg , <NUM_LIT> ) , tmp ) ) ) ; } else { rtx vcopy = gen_reg_rtx ( V2DImode ) ; emit_move_insn ( vcopy , gen_rtx_SUBREG ( V2DImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; emit_move_insn ( vcopy , gen_rtx_LSHIFTRT ( V2DImode , vcopy , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_conversion_insns ( seq , insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , REGNO ( scopy ) , INSN_UID ( insn ) ) ; } } for ( ref = DF_REG_USE_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { if ( bitmap_bit_p ( conv , DF_REF_INSN_UID ( ref ) ) ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; rtx def_set = single_set ( insn ) ; gcc_assert ( def_set


<s> RegNo = <STR_LIT> ; IntVal = <NUM_LIT> ; } else if ( Name . startswith_insensitive ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = is<ISA_LIT>64 ( ) ? XRegs [ IntVal ] : RRegs [ IntVal ] ; } else if ( Name . startswith_insensitive ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = FRegs [ IntVal ] ; } else if ( Name . startswith_insensitive ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VSRegs [ IntVal ] ; } else if ( Name . startswith_insensitive ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VRegs [ IntVal ] ; } else if ( Name . startswith_insensitive ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = CRRegs [ IntVal ] ; } else return true ; getParser ( ) . Lex ( ) ; return


<s> default : debug ( <STR_LIT> ) ; return true ; case ENCODING_REG : translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_RM : return translateRM ( mcInst , operand , insn ) ; case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case


<s> bool <ISA_LIT>BaseInstrInfo :: analyzeSelect ( const MachineInstr * MI , SmallVectorImpl < MachineOperand > & Cond , unsigned & TrueOp , unsigned & FalseOp , bool & Optimizable ) const { assert ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; TrueOp = <NUM_LIT> ; FalseOp =


<s> case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 : return <STR_LIT> ; case VK_TPREL_LO12 : return <STR_LIT> ; case VK_TPREL_LO12_NC : return <STR_LIT> ; case VK_TLSDESC_LO12 : return <STR_LIT> ; case VK_ABS_PAGE : return <STR_LIT> ; case VK_GOT_PAGE : return <STR_LIT> ; case VK_GOT_LO12 : return <STR_LIT> ; case VK_GOTTPREL_PAGE : return <STR_LIT>


<s> CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: SExt


<s> bool <ISA_LIT>TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( Opc == <STR_LIT> && VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> ) return false ; if ( VT != <STR_LIT> ) return true ; switch ( Opc ) { default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeRROperand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1


<s> return hasSSE1 ( ) || ( hasPRFCHW ( ) && ! hasThreeDNow


<s> NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) | getUndefRegState ( isUndef ) ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } break ; case <STR_LIT> : case <STR_LIT> : if ( ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { const TargetRegisterClass * RC = RI . getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned StoreOpc , LoadOpc ; if ( RC == <STR_LIT> ) { LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> ) ; LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } if ( Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool isUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( StoreOpc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) | getUndefRegState ( isUndef ) ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> )


<s> <ISA_LIT>MCExpr :: VariantKind Kind = ( <ISA_LIT>MCExpr :: VariantKind ) MO . getTargetFlags ( ) ; const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create


<s> const DigitalABIInfo & getABI ( ) const { return


<s> bool UsedMask [ ] = { false , false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsmsk_u64 ( unsigned long long


<s> inline vector unsigned short vec_vpkuwum ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned short ) __builtin_altivec_vpkuwum ( ( vector signed int ) a1


<s> Parser . Lex ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned RegNo , RegKind ; if ( ! matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , RegKind , S , E ) ) ; ResTy = MatchOperand_Success ; } else { ResTy = parseMEMOperand ( Operands ) ; } if ( ResTy != MatchOperand_Success ) return ResTy ; if ( ! getLexer ( ) . is ( AsmToken :: RBrac ) )


<s> MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { unsigned NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zero64 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , NewIn128 ) . addReg ( In128 ) . addReg ( Zero64 ) . addImm ( <STR_LIT> ) ; In128 = NewIn128 ; } BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Dest ) . addReg ( In128 ) . addReg ( Src ) . addImm ( SubReg ) ; MI -> eraseFromParent (


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> :


<s> unsigned getVPTPred ( ) { unsigned Pred = <STR_LIT> ; if ( instrInVPTBlock ( ) ) Pred = VPTStates . back ( ) ; return Pred


<s> } uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; OW -> Write8 ( <NUM_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> if ( Subtarget -> isGP64bit ( ) ) { Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , VT ) , SDValue ( Carry , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , VT ) ) ; } SDNode * AddCarry = CurDAG -> getMachineNode ( ADDuOp , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT>

, LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent


<s> for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) insn -> call = <NUM_LIT> ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) == ITANIUM_CLASS_IALU ) { sd_iterator_def sd_it ; dep_t dep


<s> RegNo = <STR_LIT> + intVal ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = FloatRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal >= <NUM_LIT> && intVal <= <NUM_LIT> && ( intVal % <NUM_LIT> == <NUM_LIT> ) ) { RegNo = DoubleRegs [ intVal / <NUM_LIT> ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } } return false


<s> EVT EltTy = N0 . getValueType ( ) . getVectorElementType ( ) ; if ( EltTy != <STR_LIT> && EltTy != <STR_LIT> && EltTy != <STR_LIT> ) return SDValue ( ) ; int NumVecElts = N0 . getValueType ( ) . getVectorNumElements ( ) ; if ( NumVecElts != <NUM_LIT> && NumVecElts != <NUM_LIT> && NumVecElts != <NUM_LIT> ) return SDValue ( ) ; int NumExpectedSteps = APInt ( <NUM_LIT> , NumVecElts ) . logBase2 ( ) ; SDValue PreOp = N0 ; for ( int CurStep = <NUM_LIT> ; CurStep != NumExpectedSteps ; ++ CurStep ) { if ( PreOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue CurOp = PreOp . getOperand ( <NUM_LIT> ) ; SDValue Shuffle = PreOp . getOperand ( <NUM_LIT> ) ; if ( Shuffle . getOpcode ( ) != <STR_LIT> ) { CurOp = PreOp . getOperand ( <NUM_LIT> ) ; Shuffle = PreOp . getOperand ( <NUM_LIT> ) ; if ( Shuffle . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } if ( Shuffle . getOperand ( <NUM_LIT> ) != CurOp ) return SDValue ( ) ; int NumMaskElts = <NUM_LIT> << CurStep ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( Shuffle ) -> getMask ( ) ; for ( int i = <NUM_LIT> ; i < NumVecElts ; ++ i ) if ( ( i < NumMaskElts && Mask [ i ] != ( NumMaskElts + i ) ) || ( i >= NumMaskElts && ! ( Mask [ i ] < <NUM_LIT> ) ) ) return SDValue ( ) ; PreOp = CurOp ; } SDLoc DL ( N


<s> unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ; if ( VTSize == <NUM_LIT> ) return VT . isFloatingPoint ( ) ; return VTSize == <NUM_LIT> || VTSize == <NUM_LIT> || VTSize == <NUM_LIT>


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( get<ISA_LIT>TargetMachine


<s> switch ( Elt ) { case FixedType : if ( hasVectorParms ( ) ) { ParamsTypeInfo <<= XCOFF :: TracebackTable :: WidthOfParamType ; ParamsTypeInfo |= XCOFF :: TracebackTable :: ParmTypeIsFixedBits >> ShiftBits ; Bits += XCOFF :: TracebackTable :: WidthOfParamType ; } else { ParamsTypeInfo <<= <NUM_LIT> ; ++ Bits ; } break ; case ShortFloatingPoint : ParamsTypeInfo <<= XCOFF :: TracebackTable :: WidthOfParamType ; ParamsTypeInfo |= XCOFF :: TracebackTable :: ParmTypeIsFloatingBits >> ShiftBits ; Bits += XCOFF :: TracebackTable :: WidthOfParamType ; break ; case LongFloatingPoint : ParamsTypeInfo <<= XCOFF :: TracebackTable :: WidthOfParamType ; ParamsTypeInfo |= XCOFF :: TracebackTable :: ParmTypeIsDoubleBits >> ShiftBits ; Bits += XCOFF :: TracebackTable :: WidthOfParamType ; break ; case VectorChar : case VectorShort : case


<s> return ( __mmask8 ) __builtin_ia32_ucmpd256_mask ( ( __v8si ) __X , ( __v8si )


<s> return ( ( qword ) ( vec_mulo ( ( vec_ushort8 ) ( a ) , ( vec_ushort8


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModels ( GA , DAG


<s> if ( Subtarget . isGP64bit ( ) ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> )


<s> assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) * <NUM_LIT> ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1

, RegState :: Kill ) . addImm ( <NUM_LIT> - ShiftBits ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; bool CallsEHReturn = MF -> callsEHReturn ( ) ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) CC = CallingConv :: <ISA_LIT>_INTR ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) CASE_OBF_SAVE ( <NUM_LIT> ) case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit )


<s> LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT>


<s> const <ISA_LIT>MemoryFoldTableEntry * llvm :: lookupTwoAddrFoldTable ( unsigned RegOp ) { return lookupFoldTableImpl ( MemoryFoldTable2Addr ,


<s> return nds32_builtin_decl_impl ( code , initialize_p


<s> if ( TARGET_CPU_P ( PENTIUMPRO ) && ( alg == rep_prefix_4_byte || alg == rep_prefix_1_byte ) ) desired_align = <NUM_LIT> ; if ( optimize_size ) desired_align = <NUM_LIT> ; if ( desired_align < align ) desired_align = align ; if ( expected_size != - <NUM_LIT> && expected_size < <NUM_LIT> ) desired_align = align ; return


<s> bool <ISA_LIT>TTIImpl :: isFCmpOrdCheaperThanFCmpZero ( Type


<s> return isSImm < <NUM_LIT> , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> hasOrderedMemoryRef ( ) ) { ++ MBBI ; break ; } if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) { ++ MBBI ; break ; } if ( TII -> isLdStPairSuppressed ( MI ) ) { ++ MBBI ; break ; } LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , ScanLimit ) ; if ( Paired != E ) { ++ NumPairCreated ; if ( isUnscaledLdSt ( MI ) ) ++ NumUnscaledPairCreated ; MBBI = mergePairedInsns ( MBBI , Paired , Flags ) ; Modified = true ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] .


<s> dbgprintf ( insn , <STR_LIT> ) ; switch ( ( OperandEncoding ) op -> encoding ) { default : debug ( <STR_LIT> ) ; return - <NUM_LIT> ; case ENCODING_VVVV : insn -> vvvv = ( Reg ) fixupRegValue ( insn , ( OperandType ) op -> type , insn -> vvvv , & valid ) ; if ( ! valid ) return - <NUM_LIT> ; break ; case ENCODING_REG : insn -> reg = ( Reg ) fixupRegValue ( insn , ( OperandType ) op -> type , insn -> reg - insn -> regBase , & valid ) ; if ( ! valid ) return -


<s> case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerDivRem ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) ) return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND


<s> bool <ISA_LIT>AsmParser :: CreateMemForMSInlineAsm ( unsigned SegReg , const MCExpr * Disp , unsigned BaseReg , unsigned IndexReg , unsigned Scale , SMLoc Start , SMLoc End , unsigned Size , StringRef Identifier , const InlineAsmIdentifierInfo & Info , OperandVector & Operands ) { if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Label ) ) { if ( ! Size ) { Size = getPointerWidth ( ) ; InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ; } Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Info . Label . Decl ) ) ; return false ; } unsigned FrontendSize = <NUM_LIT> ; void * Decl = nullptr ; bool IsGlobalLV = false ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { FrontendSize = Info . Var . Type * <NUM_LIT> ; Decl = Info . Var . Decl ; IsGlobalLV = Info . Var . IsGlobalLV ; } if ( IsGlobalLV && ( BaseReg || IndexReg ) ) { Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End ) ) ; return false ; } BaseReg = BaseReg ?


<s> Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes ) ] ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOpCode ) , NewReg ) . addReg ( StateReg ) . addReg ( Reg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( )


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ; return


<s> cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree )

= save_target_globals_default_opts ( ) ;


<s> MCInst TmpInst = MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; uint16_t Bits = getBinaryCodeForInstr ( TmpInst


<s> FunctionPass * llvm :: create<ISA_LIT>FixupBWInsts


<s> } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 , r0 ) ) ) ; ok_label = gen_label_rtx ( ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , compare , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , ok_label ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( jump ) = ok_label ; add_int_reg_note ( jump , REG_BR_PROB , REG_BR_PROB_BASE - REG_BR_PROB_BASE / <NUM_LIT> ) ; lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( r0 , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_frame_store ( r0 , r1 , info -> lr_save_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_call_insn ( gen_call ( gen_rtx_MEM ( SImode , morestack_ref ) , const0_rtx , const0_rtx ) ) ; call_fusage = NULL_RTX ; use_reg ( & call_fusage , r12 ) ; add_function_usage_to ( insn , call_fusage ) ; emit_insn ( gen_frame_load ( r0 , r1 , info -> lr_save_offset ) ) ; insn = emit_move_insn ( lr , r0 ) ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_split_stack_return ( ) ) ; emit_label ( ok_label ) ; LABEL_NUSES ( ok_label ) = <NUM_LIT>


<s> bool hasBaseOrIndexReg ( ) const { return BaseType == FrameIndexBase || IndexReg . getNode ( ) != nullptr ||


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) return false ; Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) return false ; Opc = <STR_LIT> ; break ; default : return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstStore ( Opc , SrcReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr


<s> rtx base_rtx = stack_pointer_rtx ; rtx insn , reg , mem ; reg = gen_rtx_REG ( mode , regno ) ; mem = gen_rtx_PRE_MODIFY ( Pmode , base_rtx , plus_constant ( Pmode , base_rtx , - adjustment ) ) ; mem = gen_frame_mem ( mode


<s> return ( poly16x4_t ) __builtin_shuffle ( __a , ( uint16x4_t ) {


<s> <STR_LIT> Flags = Outs [ i ] . Flags ; EVT ArgVT = Outs [ i ] . VT ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { if ( ! isVarArg && ! is<ISA_LIT>64 ) { nAltivecParamsAtEnd ++ ; continue ; } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && DAG . getTarget ( ) . Options


<s> vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , adjust ) ) ; for ( i = <NUM_LIT> ; i < count - <NUM_LIT> ; i ++ ) XVECEXP ( vector , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == <NUM_LIT> ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; XVECEXP ( vector , <NUM_LIT> , count - <NUM_LIT> )


<s> { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , } ; unsigned Opcode = MI . getOpcode ( ) ; auto Found = VFMKMap . find ( Opcode ) ; if ( Found == VFMKMap . end ( ) ) report_fatal_error ( <STR_LIT> ) ; unsigned OpcodeUpper = ( * Found ) . second . first ; unsigned OpcodeLower = ( * Found ) . second . second ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) ) { if ( needsStackRealignment ( MF ) ) return true ; return MFI . getLocalFrameSize (


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI ) . addImm


<s> O << ( short ) MI -> getOperand ( OpNo


<s> static DecodeStatus DecodeVecShiftL8Imm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void *


<s> if ( const auto * V = dyn_cast < GlobalVariable > ( GV ) ) return V -> isConstant ( ) ; return isa < Function > (


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg


<s> static Mfix * create_csky_fix_barrier ( Mfix * fix , Mfix * fix_next , HOST_WIDE_INT max_address ) { rtx_barrier * barrier ; rtx_insn * from = ( fix ? fix -> insn : get_insns ( ) ) ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address = <NUM_LIT> ; Mfix * new_fix ; HOST_WIDE_INT count = ( fix ? fix -> address : <NUM_LIT> ) ; HOST_WIDE_INT max_count = max_address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = get_csky_barrier_cost ( from ) ; while ( from && count < max_count ) { int new_cost ; rtx_jump_table_data * table ; count += get_attr_length ( from ) ; if ( tablejump_p ( from ,


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && LHS . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> && LHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , LHS . getValueType ( ) , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , addV . getValueType ( ) ) , CC ) ; } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , addV . getValueType ( ) ) , CC ) ; } return SDValue


<s> MVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; unsigned CopyOpc = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( MBB , DL , TII . get ( CopyOpc ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , <STR_LIT> ) ; if ( ! ResultReg )


<s> static DecodeStatus DecodeCPURegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> ,


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( )


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAccessReg ( OperandVector & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken

:: Percent ) ) return MatchOperand_NoMatch ;


<s> unsigned NumLaneElems = NumElems / NumLanes ; if ( NumLaneElems != <NUM_LIT> && NumLaneElems != <NUM_LIT> ) return false ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool symetricMaskRequired = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) && ( EltSize == <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskVal ( NumLaneElems , - <NUM_LIT> ) ; unsigned HalfLaneElems = NumLaneElems / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElems ; l += NumLaneElems ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = Mask [ i + l ] ; unsigned RngStart = l + ( ( Commuted == ( i < HalfLaneElems ) ) ? NumElems : <NUM_LIT> ) ; if ( ! isUndefOrInRange ( Idx , RngStart , RngStart + NumLaneElems ) ) return false ; if ( ! symetricMaskRequired || Idx


<s> __v4sf mask = _mm_cmpeq_ps ( src , src ) ; return ( __m128 ) __builtin_ia32_gatherdiv4sf ( src , base ,


<s> unsigned RegNo ; int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; return false ; } return Error ( S , <STR_LIT> ) ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Identifier : case AsmToken :: Dot : case AsmToken :: Dollar : if ( ! ParseExpression ( EVal ) ) break ; default : return Error ( S , <STR_LIT> ) ; } Op = <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateFromMCExpr ( TLSSym , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back (


<s> if ( REG_P ( operands [ <NUM_LIT> ] ) && symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) { if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( REG_P ( operands [ <NUM_LIT> ] ) && symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) { if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( flag_pic && REG_P ( operands [ <NUM_LIT> ] ) && symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; if ( flag_pic && ( symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) || symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) ) debug_rtx ( insn ) ; return <STR_LIT> ; case E_HImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx ) return <STR_LIT> ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; case E_QImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx ) return <STR_LIT> ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugValue ( ) ) -- Iter ; bool SawKill = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand ( j ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg


<s> if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER ) continue ; if ( ( GET_CODE ( pat ) == UNSPEC && XINT ( pat , <NUM_LIT> ) == <NUM_LIT> ) || GET_CODE ( insn ) == CODE_LABEL ) { if ( b ) while ( bundle_pos < <NUM_LIT> ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } if ( GET_CODE ( insn ) != CODE_LABEL ) b = bundle + INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; else b = <NUM_LIT> ; bundle_pos = <NUM_LIT> ; continue ; } else if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , <NUM_LIT> ) == <NUM_LIT> ) { int t = INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; if ( b ) while ( bundle_pos < t ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( bundle_pos == <NUM_LIT> ) b = <NUM_LIT> ; if ( b && INSN_P ( insn ) ) { t = ia64_safe_type ( insn ) ; if ( asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) { while ( bundle_pos < <NUM_LIT> ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos


<s> return ( __mmask16 ) __builtin_ia32_ucmpd512_mask ( ( __v16si ) __A , (


<s> unsigned <ISA_LIT>MCCodeEmitter :: NEONThumb2LoadStorePostEncoder ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { if ( isThumb2 ( STI )


<s> return __builtin_ia32_ucomigt ( ( __v4sf ) __A ,


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table


<s> static StringRef computeDefaultCPU ( const Triple & TT , StringRef CPU ) { if ( CPU . empty ( ) && TT . isArm64e (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) .


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return <NUM_LIT> ; return MRI -> getUniqueVRegDef (


<s> return ( KnownAlignment ? MaxDisp : MaxDisp -


<s> if ( isa < Argument > ( V ) ) return true ; else if ( isa < LoadInst > ( V ) ) return true ; else if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; return false


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { unsigned NumOps = LoadMI -> getDesc ( )


<s> if ( Subtarget -> isFPOnlySP ( ) && VT == <STR_LIT> ) { FalseVal = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , FalseVal ) ; TrueVal = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , TrueVal ) ; SDValue TrueLow = TrueVal . getValue ( <NUM_LIT> ) ; SDValue TrueHigh = TrueVal . getValue ( <NUM_LIT> ) ; SDValue FalseLow = FalseVal . getValue ( <NUM_LIT> ) ; SDValue FalseHigh = FalseVal . getValue ( <NUM_LIT> ) ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseLow , TrueLow , <ISA_LIT>cc , CCR , Cmp ) ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseHigh , TrueHigh , <ISA_LIT>cc , CCR , duplicateCmp ( Cmp , DAG ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Low , High ) ; }


<s> void printU16ImmOperand ( const MachineInstr * MI , unsigned OpNo


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMVEPairVectorIndexOperand < <NUM_LIT> > ( Inst ,

index , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> void addPKHASRImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; Arg = EmitIntExt ( SrcVT , Arg , DestVT , false ) ; if ( Arg == <NUM_LIT> ) return false ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; Arg = EmitIntExt ( SrcVT , Arg


<s> return __builtin_loongson_pmovmskb_u (


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo &


<s> const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } } return BaseT :: getCmpSelInstrCost ( Opcode , ValTy


<s> enum machine_mode dest_mode = GET_MODE ( dest ) ; int vsel_insn_index = get_vsel_insn ( GET_MODE ( dest ) ) ; temp = gen_reg_rtx ( dest_mode ) ; t = gen_rtx_SET ( VOIDmode , temp , gen_rtx_UNSPEC ( dest_mode , gen_rtvec ( <NUM_LIT> , op2


<s> if ( AFI -> isThumbFunction ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned


<s> outliner :: OutlinedFunction <ISA_LIT>BaseInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { outliner :: Candidate & FirstCand = RepeatedSequenceLocs [ <NUM_LIT> ] ; unsigned SequenceSize = std :: accumulate ( FirstCand . front ( ) , std :: next ( FirstCand . back ( ) ) , <NUM_LIT> , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned FlagsSetInAll = <NUM_LIT> ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & FlagsSetInAll ] ( outliner :: Candidate & C ) { FlagsSetInAll &= C . Flags ; } ) ; auto CantGuaranteeValueAcrossCall = [ & TRI ] ( outliner :: Candidate & C ) { if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CantGuaranteeValueAcrossCall ) , RepeatedSequenceLocs . end ( ) ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = <NUM_LIT> ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; if ( C . LRU . available ( <STR_LIT> ) ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs


<s> unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; fork_execute ( argv [ <NUM_LIT> ] , argv , false ) ; obstack_free ( argv_obstack , NULL ) ; xputenv ( concat ( <STR_LIT> , epath , NULL ) ) ; xputenv ( concat ( <STR_LIT> , cpath , NULL


<s> return ( __m128i ) __builtin_ia32_psubw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> unsigned size = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; align *= <NUM_LIT> * size ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairSpacedRegisterClass ( Inst , Rd , Address


<s> SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( Symbol ) DestAddress = materializeExternalCallSym ( Symbol ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , <STR_LIT> ) ; emitInst ( TargetOpcode :: COPY , <STR_LIT> ) . addReg ( DestAddress


<s> return ( regno == <NUM_LIT> || regno ==


<s> return <ISA_LIT>Lowering -> SelectAddressRegReg ( N , Base , Index


<s> if ( Size >= <NUM_LIT> && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == <NUM_LIT> || DstAlign >= <NUM_LIT> ) && ( SrcAlign == <NUM_LIT> || SrcAlign >= <NUM_LIT> ) ) ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> hasAVX ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) return <STR_LIT> ; if ( Subtarget -> hasXMMInt ( ) ) return <STR_LIT> ; if ( Subtarget -> hasXMM ( ) ) return


<s> for ( i = <NUM_LIT> ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) if ( aapcs_cp_arg_layout [ i ] . is_call_candidate ( pcum , mode , type ) ) return i ; return - <NUM_LIT>


( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MIB ) ; MIB . addMBB ( NextBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII ->


<s> bool is<ISA_LIT>64 = ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ; unsigned Flavour = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; unsigned RA = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X = new MCRegisterInfo (


<s> static SDValue LowerToTLSGeneralDynamicModel64 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const EVT PtrVT ) { return GetTLSADDR ( DAG , DAG . getEntryNode ( ) , GA , NULL , PtrVT ,


<s> if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; } else AFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> ,


<s> return <ISA_LIT>Lowering -> SelectOptimalAddrMode ( Parent , N , Disp , Base


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return


<s> return produceCompactUnwindFrame ( MF ) ||


<s> AssemblerOptions . back ( ) -> setATRegIndex ( <NUM_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveSetNoAt (


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < AN -> getNumOperands ( ) ; ++ i ) Ops . push_back ( AN -> getOperand ( i ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( AN -> getOrdering ( ) , <STR_LIT> ) ) ; Ops . push_back ( AN ->


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups


return create<ISA_LIT>MachORelocationInfo ( Ctx ) ;


<s> static rtx mips_prepare_builtin_target ( enum insn_code icode , unsigned int op , rtx target ) { enum machine_mode mode ; mode = insn_data [ icode ] . operand [ op ] . mode ; if ( target == <NUM_LIT> || ! insn_data [ icode ] . operand [ op ] .

predicate ( target , mode ) ) target = gen_reg_rtx ( mode ) ;


<s> GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegName ( Reg ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( HasRegForVL ? RegName ( RegForVL ) : <STR_LIT> ) << <STR_LIT> ) ; if ( ! HasRegForVL || RegForVL != Reg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegName ( Reg ) << <STR_LIT> ) ; BuildMI ( MBB , I , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) ; HasRegForVL = true ; RegForVL = Reg ; Changed = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } if (


<s> unsigned ResultReg ; if ( Imm < <NUM_LIT> ) ResultReg = emitAddSub_ri ( false , VT , Op0 , Op0IsKill , - Imm ) ; else ResultReg = emitAddSub_ri ( true , VT , Op0 , Op0IsKill , Imm ) ; if ( ResultReg ) return ResultReg ; unsigned CReg = fastEmit_i ( VT , VT , <STR_LIT> , Imm ) ; if ( ! CReg ) return <NUM_LIT> ; ResultReg = emitAddSub_rr ( true , VT , Op0 , Op0IsKill , CReg , true ) ; return


<s> return new <ISA_LIT>PassConfig ( this ,


<s> return ( TARGET_32BIT && speed_p ) ? <NUM_LIT> :


<s> bool SelectArithShiftedRegister ( SDValue N , SDValue & Reg , SDValue


<s> bool <ISA_LIT>ElimCompare :: convertToBRCT ( MachineInstr * MI , MachineInstr * Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = MI -> getOpcode ( ) ; unsigned BRCT ; if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT>


<s> bool hasDominantValue = false ; bool isConstant = true ; DenseMap < SDValue , unsigned > ValueCounts ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; ValueCounts . insert ( std :: make_pair ( V , <NUM_LIT> ) ) ; unsigned & Count = ValueCounts [ V ] ; if ( ++ Count > ( NumElts / <NUM_LIT> ) ) { hasDominantValue = true ; Value = V ; } } if ( ValueCounts . size ( ) != <NUM_LIT> ) usesOnlyOneValue = false ; if ( ! Value . getNode ( ) && ValueCounts . size ( ) > <NUM_LIT> ) Value = ValueCounts . begin ( ) -> first ; if ( ValueCounts . size ( ) == <NUM_LIT> ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement && ! <STR_LIT> ( Value . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( hasDominantValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) { SDValue N ; if ( Value -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Value -> getOperand ( <NUM_LIT> ) ) ) { N = DAG . getNode ( <STR_LIT> , DL , VT , Value -> getOperand ( <NUM_LIT> ) , Value -> getOperand ( <NUM_LIT> ) ) ; } else N = DAG . getNode ( <STR_LIT> , DL , VT , Value ) ; if ( ! usesOnlyOneValue ) { for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { if ( Op . getOperand ( I ) == Value ) continue ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back (


<s> return new ( Ctx ) <ISA_LIT>MCExpr (


<s> } ; const DecodeTable Tables [ ] = { { DecoderTableVFP32 , false } , { DecoderTableVFPV832 , false } , { DecoderTableNEONData32 , true } , { DecoderTableNEONLoadStore32 , true } , { DecoderTableNEONDup32 , true } , { DecoderTablev8NEON32 , false } , { DecoderTablev8Crypto32 , false } , } ; for ( auto Table : Tables ) { Result = decodeInstruction ( Table . P , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( Table . DecodePred && ! DecodePredicateOperand ( MI , <NUM_LIT> , Address , this ) ) return MCDisassembler :: Fail ; return Result


<s> vrshr_n_u16 ( uint16x4_t __a , const int __b ) { return ( uint16x4_t ) __builtin_neon_vrshru_nv4hi ( (


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , <NUM_LIT> >


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction


<s> case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( __m128i ) __builtin_ia32_pandq128_mask ( ( __v2di ) __A , (


<s> if ( MEM_P ( mem ) ) { if ( ( MEM_EXPR ( mem ) && MEM_OFFSET_KNOWN_P ( mem ) && r10k_safe_mem_expr_p ( MEM_EXPR ( mem ) , MEM_OFFSET ( mem ) ) ) || r10k_safe_address_p (

XEXP ( mem , <NUM_LIT> ) , insn ) ) iter . skip_subrtxes ( ) ;


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( isZeroShuffle ( SVOp ) ) return getZeroVector ( VT , Subtarget , DAG , dl ) ; if ( SVOp -> isSplat ( ) ) { SDValue Broadcast = LowerVectorBroadcast ( Op , Subtarget , DAG ) ; if ( Broadcast . getNode ( ) ) return Broadcast ; } SDValue NewOp = LowerVectorIntExtend ( Op , Subtarget , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( VT . is128BitVector ( ) && Subtarget -> hasSSE2 ( ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode


<s> RelRelMap & getRelRelMap ( ) { return m_RelRelMap


<s> SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_ConversionFail : return true ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ; return


<s> SDValue Val ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : Val = performORCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this ) ; case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; N -> printrWithDepth ( dbgs ( )


<s> <ISA_LIT>HazardRecognizer :: <ISA_LIT>HazardRecognizer ( const MachineSchedContext * C ) : DAG


<s> } if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULADDX_OP2 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULSUBW_OP1 ) ; Found = true ; } if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULSUBW_OP2 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULSUBX_OP1 ) ; Found = true ; } if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULSUBX_OP2 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULADDWI_OP1 ) ; Found = true ; } break ; case <STR_LIT> : if ( canCombineWithMUL ( MBB , Root . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) { Patterns . push_back ( MachineCombinerPattern :: MC_MULADDXI_OP1 ) ; Found = true


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT ) , Subtype ( st ) { HasDataInCodeSupport = true


<s> static bool TableIsSorted ( const TableEntry * Table , unsigned NumEntries ) { for ( unsigned i = <NUM_LIT> ; i != NumEntries - <NUM_LIT> ; ++ i ) if ( ! ( Table [ i ] < Table [ i +


<s> bool BaseKill = BaseOP . isKill ( ) ; unsigned Bytes = getLSMultipleTransferSize ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; bool DoMerge = false ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = std :: prev ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode =


<s> if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; return SDValue ( )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ,


<s> HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return <NUM_LIT> ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_ALTIVEC && align >= <NUM_LIT> ) clear_step = <NUM_LIT> ; else if ( TARGET_POWERPC64 && align >= <NUM_LIT> ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { enum machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ( ! STRICT_ALIGNMENT && align >= <NUM_LIT> ) ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = SImode ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes =


<s> switch ( <STR_LIT> ( Imm ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> void printU6ImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { unsigned char value = MI -> getOperand ( OpNo )


<s> } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT>


<s> emitPopInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , isVarArg , true , & is<ISA_LIT>Area3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & is<ISA_LIT>Area2Register , <NUM_LIT> ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & is<ISA_LIT>Area1Register , <NUM_LIT> ) ; return


<s> if ( Subtarget . isTarget64BitILP32 ( ) ) StackReg

= get<ISA_LIT>SubSuperRegister ( StackReg , <NUM_LIT> ) ;


<s> if ( I == MBB -> begin ( ) ) { Visited . insert ( MBB ) ; goto queue_preds ; } else -- I ; check_block : Visited . insert ( MBB ) ; if ( I == MBB -> end ( ) ) goto queue_preds ; CheckPreds = true ; for ( MachineBasicBlock :: iterator IE = MBB -> begin ( ) ; ; -- I ) { unsigned Opc = I -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { CheckPreds = false ; break ; } if ( I != BI && clobbersCTR ( * I ) ) { LLVM_DEBUG ( dbgs ( ) << printMBBReference ( * MBB ) << <STR_LIT> << MBB -> getFullName ( ) << <STR_LIT> << * I << <STR_LIT> << printMBBReference ( * BI -> getParent ( ) ) << <STR_LIT> << BI -> getParent ( ) -> getFullName ( ) << <STR_LIT> << * BI << <STR_LIT> ) ; return false ; } if ( I == IE ) break ; } if ( ! CheckPreds && Preds . empty ( ) ) return true ; if ( CheckPreds ) { queue_preds : if ( MachineFunction :: iterator ( MBB ) == MBB -> getParent ( ) -> begin ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * BI -> getParent ( ) ) << <STR_LIT> << BI -> getParent ( ) -> getFullName ( ) << <STR_LIT> << * BI << <STR_LIT> ) ; return false ; } append_range ( Preds , MBB -> predecessors ( ) ) ; } do { MBB = Preds . pop_back_val ( ) ; if ( ! Visited . count ( MBB ) ) { I = MBB -> getLastNonDebugInstr ( ) ; goto


<s> bool sh2a_function_vector_p ( tree func ) { if ( TREE_CODE ( func )


<s> return ( int8x8_t ) __builtin_neon_vqnegv8qi (


<s> void addNEONi16splatOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( Value ) ; Inst . addOperand ( MCOperand :: createImm ( Value )


<s> if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II


<s> MachineBasicBlock * TargetMBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF -> getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return BB ; MachineBasicBlock * RestoreMBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs (


<s> MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUX32 ) return new ELF<ISA_LIT>_X32AsmBackend ( T


<s> IntelExprStateMachine ( int64_t imm , bool stoponlbrac , bool addimmprefix ) : State ( IES_PLUS ) , PrevState ( IES_ERROR ) , BaseReg ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , TmpReg ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , Imm ( imm ) , Sym ( <NUM_LIT> ) , StopOnLBrac (

stoponlbrac ) , AddImmPrefix ( addimmprefix ) {


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT ResVT = Op . getSimpleValueType ( ) ; assert ( ( In . getSimpleValueType ( ) . is256BitVector ( ) || In . getSimpleValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ; unsigned ElemsPerChunk = ResVT . getVectorNumElements ( ) ; if ( In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResVT , makeArrayRef ( In ->

op_begin ( ) + IdxVal , ElemsPerChunk ) ) ;


<s> return ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) ||


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasBWI ( ) && <STR_LIT> ) ; return splitAndLowerVectorShuffle ( DL , <STR_LIT> , V1


<s> else if ( size > <NUM_LIT> ) align2 = <NUM_LIT> ; fputs ( COMMON_ASM_OP , stream ) ; RS6000_OUTPUT_BASENAME ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED , size , align2 ) ; fputs ( rs6000_xcoff_visibility ( decl ) ,


<s> rtx aarch64_simd_vect_par_cnst_half ( machine_mode mode , bool high ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits / <NUM_LIT> ) ; int high_base = nunits / <NUM_LIT> ; int low_base = <NUM_LIT> ; int base ; rtx t1 ; int i ; if ( BYTES_BIG_ENDIAN ) base = high


<s> return __builtin_mve_vmladavaq_sv4si ( __a ,


<s> bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT> ( Imm ) ; if ( ! isImm ) Imm8 = get<ISA_LIT>RegisterNumbering ( MO . getReg (


<s> } else { if ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == <NUM_LIT> || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == <NUM_LIT> ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == <NUM_LIT> ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( REG_P ( op1 ) || can_create_pseudo_p ( ) ) ) { std :: swap ( op0 , op1


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF


<s> UseRev = true ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : std :: tie ( PredIdx , DOPIdx , SrcIdx ) = std :: make_tuple ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; break ; case <STR_LIT> : std :: tie ( PredIdx , DOPIdx , SrcIdx , Src2Idx ) = std :: make_tuple ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( DstReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { std :: tie ( PredIdx , DOPIdx , SrcIdx , Src2Idx ) = std :: make_tuple ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; UseRev = true ; } else if ( DstReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { std :: tie ( PredIdx , DOPIdx , SrcIdx , Src2Idx ) = std :: make_tuple ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; UseRev = true ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; } bool DOPRegIsUnique = false ; switch ( DType ) { case <STR_LIT> : case <STR_LIT> : DOPRegIsUnique = DstReg != MI . getOperand ( DOPIdx ) . getReg ( ) || MI . getOperand ( DOPIdx ) . getReg ( ) != MI . getOperand ( SrcIdx ) . getReg ( ) ; break ; case <STR_LIT> : DOPRegIsUnique = true ; break ; case <STR_LIT> : DOPRegIsUnique = DstReg != MI . getOperand ( DOPIdx ) . getReg ( ) || ( MI . getOperand ( DOPIdx ) . getReg ( ) != MI . getOperand ( SrcIdx ) . getReg ( ) && MI . getOperand ( DOPIdx ) . getReg ( ) != MI . getOperand ( Src2Idx ) . getReg ( ) ) ; break ; } if ( UseRev ) { int NewOpcode ; if ( ( NewOpcode = <STR_LIT> ( Opcode ) ) != - <NUM_LIT> ) Opcode = NewOpcode ; else if ( ( NewOpcode = <STR_LIT> ( Opcode ) ) != - <NUM_LIT> ) Opcode = NewOpcode ; } uint64_t ElementSize = TII -> getElementSizeForOpcode ( Opcode ) ; unsigned MovPrfx , MovPrfxZero ; switch ( ElementSize ) { case <STR_LIT> : case <STR_LIT> : MovPrfx = <STR_LIT> ; MovPrfxZero = <STR_LIT> ; break ; case <STR_LIT> : MovPrfx = <STR_LIT> ; MovPrfxZero =


<s> unsigned <ISA_LIT>TargetLowering :: GetAlignedArgumentStackSize ( unsigned StackSize , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; const TargetFrameLowering & TFI = * TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ; } return Offset


<s> static SDValue combineFaddFsub ( SDNode * N , SelectionDAG & DAG

, const <ISA_LIT>Subtarget & Subtarget ) {


<s> if ( Src -> isVectorTy ( ) && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) && Src -> getVectorNumElements ( ) < <NUM_LIT> ) { unsigned NumVecElts = Src -> getVectorNumElements ( ) ; unsigned NumVectorizableInstsToAmortize = NumVecElts *


<s> unsigned NumOfElm = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out . push_back ( Mask [ i ] + LowOffset ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out .

push_back ( Mask [ i ] + HighOffset + NumOfElm ) ;


<s> if ( Node -> getOpcode ( ) == <STR_LIT> ) { if ( Node -> getOperand ( <NUM_LIT> ) != Node -> getOperand ( <NUM_LIT> ) ) return false ; SDNodeFlags Flags = Node -> getFlags ( ) ; if ( ScalarBits == <NUM_LIT> && ! Flags . hasNoInfs ( ) && IsUnsigned ) return false ; unsigned Opcode ; switch ( ScalarBits ) { case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops { Node -> getOperand ( <NUM_LIT> )

, CurDAG -> getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ;


<s> case Triple :: IOS : case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple :: MacOSX : case Triple ::


<s> intptr_t RelocCST = <NUM_LIT> ; if ( Reloc == <STR_LIT> ) RelocCST = PICBaseOffset ; else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , RelocCST , NeedStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset (

) , Reloc , GV , RelocCST , NeedStub ) ;


OrigArg . Flags [ <NUM_LIT> ] , OrigArg . IsFixed ) ;


<s> static enum machine_mode rs6000_eh_return_filter_mode ( void


<s> auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; InEpilogCFI = true ; CurrentEpilog = S . emitCFILabel ( ) ; CurFrame -> EpilogMap [ CurrentEpilog ] . Condition


<s> unsigned NumElts = VecTy -> getVectorNumElements ( ) ; Type * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( NumElts % Factor == <NUM_LIT> && ( SubVecSize == <NUM_LIT> || SubVecSize == <NUM_LIT> ) ) return Factor ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor ,


<s> static inline unsigned decodeRs ( uint32_t


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDValue Vec = Op -> getOperand ( <NUM_LIT> ) ; bool BigEndian = ! DAG . getSubtarget ( ) . getTargetTriple ( ) . isLittleEndian ( ) ; MVT ResEltTy = ResTy == <STR_LIT> ? <STR_LIT>


<s> } if ( Res ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Res . getNode ( ) -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) ,


<s> Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> case JUMP_INSN : scanbody = PATTERN ( this_insn ) ; if ( GET_CODE ( scanbody ) == SET && GET_CODE ( SET_DEST ( scanbody ) ) == PC ) { if ( GET_CODE ( SET_SRC ( scanbody ) ) == LABEL_REF && XEXP ( SET_SRC ( scanbody ) , <NUM_LIT> ) == label && ! reverse ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else if ( GET_CODE ( SET_SRC ( scanbody ) ) == IF_THEN_ELSE ) fail = TRUE ; } else if ( GET_CODE ( scanbody ) == return_code && ! use_return_insn ( TRUE , NULL ) && ! optimize_size ) fail = TRUE ; else if ( GET_CODE ( scanbody ) == return_code ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else if ( GET_CODE ( scanbody ) == PARALLEL ) { switch ( get_attr_conds ( this_insn ) ) { case CONDS_NOCOND : break ; default : fail = TRUE ; break ; } } else fail = TRUE ; break ; case INSN : scanbody = PATTERN ( this_insn ) ; if ( ! ( GET_CODE ( scanbody ) == SET || GET_CODE ( scanbody ) == PARALLEL ) || get_attr_conds ( this_insn ) != CONDS_NOCOND ) fail = TRUE ; break ; default : break ; } } if ( succeed ) { if ( ( ! seeking_return ) && ( arm_ccfsm_state == <NUM_LIT> || reverse ) ) arm_target_label = CODE_LABEL_NUMBER ( label ) ; else { gcc_assert ( seeking_return || arm_ccfsm_state == <NUM_LIT> ) ; while ( this_insn && GET_CODE ( PATTERN ( this_insn ) ) == USE ) { this_insn = next_nonnote_insn ( this_insn ) ; gcc_assert ( ! this_insn || ( ! BARRIER_P ( this_insn ) && ! LABEL_P ( this_insn ) ) ) ; } if ( ! this_insn ) { extract_constrain_insn_cached ( insn ) ; arm_ccfsm_state = <NUM_LIT>


<s> __builtin_mve_vst1q_sv4si ( ( __builtin_neon_si * ) __addr ,


<s> rtx aarch64_ptrue_all ( unsigned int elt_size ) { rtx_vector_builder builder ( VNx16BImode , elt_size , <NUM_LIT> ) ; builder . quick_push ( const1_rtx ) ; for ( unsigned int i = <NUM_LIT> ; i < elt_size ; ++ i ) builder . quick_push


<s> DAG . getContext ( ) -> emitError ( <STR_LIT> ) ; return SDValue ( ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI . setReturnAddressIsTaken ( true ) ; Register Reg = MF . addLiveIn ( RA , getRegClassFor ( VT ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( Op )


<s> unsigned Align = TD -> getPreferredAlignmentLog ( GVar ) ; printVisibility ( name , GVar -> getVisibility ( ) ) ; SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } else { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: CommonLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; case GlobalValue :: GhostLinkage : cerr << <STR_LIT> ; abort (


<s> Register SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI . RemoveOperand ( ImpDefIdx ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> fprintf ( file , <STR_LIT> ) ; if ( TARGET_LINK_STACK ) { char name [ <NUM_LIT> ] ; get_ppc476_thunk_name ( name ) ; fprintf ( file , <STR_LIT> , name ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; } else { fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; } fprintf ( file , <STR_LIT> , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT>


<s> continue ; } if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , Subtarget ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig ) { Modified = true ; createFPFnStub ( F , & M , V , Subtarget


<s> tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; const char * str = c_getstr ( * args ) ; int quiet = fn_code == IA64_BUILTIN_NANQ ; REAL_VALUE_TYPE real ; if ( str && real_nan ( & real , str , quiet , TYPE_MODE ( type ) )


<s> IsPIC ( false ) , IsLittleEndian ( true


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_min_ss ( __m128 __A , __m128 __B ) { __v4sf a , b , c ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = vec_min ( a , b ) ; return ( vec_sel ( ( __v4sf ) __A


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _writegsbase_u32 ( unsigned int


<s> case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } break ; case CONST_DOUBLE : * total = COSTS_N_INSNS (


<s> return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op .

getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static MachineInstr * getLastNonPseudo ( MachineBasicBlock & MBB , const TargetInstrInfo * TII ) { MachineBasicBlock * FMBB = & MBB ; while ( ( FMBB = getBBFallenThrough ( FMBB , TII ) ) ) { for ( auto I = FMBB -> rbegin ( ) , E = FMBB -> rend ( ) ; I != E ; ++ I ) { if ( ! I -> isPseudo (


<s> MCObjectWriter * createObjectWriter ( raw_ostream &


<s> <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { if ( AddSub == <STR_LIT> )


<s> case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBH_OP1 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2


<s> static void create_complex_muldiv ( const char * name , built_in_function fncode , tree fntype ) { tree fndecl = add_builtin_function ( name , fntype ,

fncode , BUILT_IN_NORMAL , name , NULL_TREE ) ;


<s> void setFI ( unsigned FI ) { assert ( isFIBase ( ) && <STR_LIT> ) ; Base . FI


<s> switch ( MO . getReg ( ) ) { case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_BR : FixupKind = <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; } else llvm_unreachable ( <STR_LIT> )


<s> void printi256mem ( const MachineInstr * MI , unsigned


<s> if ( V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Src = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( ! SrcVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return SDValue ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( ! matchVectorShuffleAsVPMOV ( Mask , SwappedOps , <NUM_LIT> ) && ! matchVectorShuffleAsVPMOV ( Mask , SwappedOps ,