<s> DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , DL , AddiuSpImm ( Imm


<s> static rtx loongarch_got_load_tls_gd ( rtx dest , rtx sym ) { return gen_got_load_tls_gd ( Pmode ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = getFMA3Group ( MI . getOpcode ( ) , MI . getDesc ( ) . TSFlags ) ; if ( FMA3Group ) return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , FMA3Group -> isIntrinsic ( ) ) ; if ( <STR_LIT> ( Desc . TSFlags ) ) { unsigned CommutableOpIdx1 = Desc . getNumDefs (


<s> addPass ( createMicro<ISA_LIT>SizeReductionPass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( create<ISA_LIT>BranchExpansion ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return EVT ( <STR_LIT> ) ; case <STR_LIT> : return EVT ( <STR_LIT> ) ; case <STR_LIT> : return EVT ( <STR_LIT> ) ; case <STR_LIT> : return EVT ( <STR_LIT> ) ; case <STR_LIT> : return EVT ( <STR_LIT> ) ; case <STR_LIT> : return EVT ( <STR_LIT> ) ; case <STR_LIT>


<s> assert ( last -> getKind ( ) == Fragment :: Null ) ; tmp . splice ( tmp . end ( ) , list , first ) ; tmp . splice ( tmp . end ( ) , list , last ) ; } sort ( list , ExIdxFragmentComparator ( * m_pExData ) ) ; llvm :: StringRef cantUnwindRegion ( g_CantUnwindEntry , sizeof ( g_CantUnwindEntry ) ) ; SectionData :: FragmentListType :: iterator it = list . begin ( ) ; if ( it != list . end ( ) ) { Fragment * prevTextFrag = m_pExData -> getTupleByExIdx ( & * it ) -> getTextFragment ( ) ; uint64_t prevTextEnd = prevTextFrag -> getParent ( ) -> getSection ( ) . addr ( ) + prevTextFrag -> getOffset ( ) + prevTextFrag -> size ( ) ; ++ it ; while ( it != list . end ( ) ) { Fragment * currTextFrag = m_pExData -> getTupleByExIdx ( & * it ) -> getTextFragment ( ) ; uint64_t currTextBegin = currTextFrag -> getParent ( ) -> getSection ( ) . addr ( ) + currTextFrag -> getOffset ( ) ; if ( currTextBegin > prevTextEnd ) { RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . insert ( it , frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef :: Create ( * frag , <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( CreateLocalSymbolToFragmentEnd ( pModule , * prevTextFrag ) ) ; addExtraRelocation ( reloc ) ; } prevTextEnd = currTextBegin + currTextFrag -> size ( ) ; prevTextFrag = currTextFrag ; ++ it ; } RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . push_back ( frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef :: Create ( * frag , <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( CreateLocalSymbolToFragmentEnd ( pModule , * prevTextFrag ) ) ; addExtraRelocation ( reloc ) ; } list . splice ( list . begin ( ) , tmp , tmp . begin ( ) ) ; list . splice ( list . end ( ) , tmp , tmp . begin ( ) ) ; uint64_t offset = <NUM_LIT> ; for ( SectionData :: iterator it = sectData -> begin ( ) , end = sectData -> end ( ) ; it != end ; ++ it


<s> unsigned <ISA_LIT>TTIImpl :: getLoadStoreVecRegBitWidth ( unsigned


<s> case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N


<s> rawaddr = gen_rtx_PLUS ( Pmode , op2 , op1 ) ; } addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - <NUM_LIT> ) ) ; addr = gen_rtx_MEM ( tmode , addr ) ; op0 = copy_to_mode_reg ( tmode , op0 ) ; emit_insn ( gen_rtx_SET ( addr , op0 ) ) ; } else if ( icode == CODE_FOR_vsx_stxvrbx || icode == CODE_FOR_vsx_stxvrhx || icode == CODE_FOR_vsx_stxvrwx || icode == CODE_FOR_vsx_stxvrdx ) { truncrtx = gen_rtx_TRUNCATE ( tmode , op0 ) ; op0 = copy_to_mode_reg ( E_TImode , truncrtx ) ; if ( op1 == const0_rtx ) addr = gen_rtx_MEM ( Pmode , op2 ) ; else { op1 = copy_to_mode_reg ( mode1 , op1 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op2 , op1 ) ) ; } pat = GEN_FCN ( icode ) ( addr , op0 ) ; if ( pat ) emit_insn ( pat ) ; } else { if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , smode ) ) op0 = copy_to_mode_reg ( smode , op0 ) ; if ( op1 == const0_rtx ) addr = gen_rtx_MEM ( tmode , op2 ) ; else { op1 = copy_to_mode_reg ( mode1 , op1 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op2 , op1 ) ) ; } pat = GEN_FCN ( icode ) ( addr ,


<s> builtin_decls_data bdda [ ] = { { double_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , TYPE_MODE ( bdd -> type_node ) ) ; fndecl = aarch64_general_add_builtin ( bdd -> builtin_name , ftype , bdd -> function_code , attrs ) ; aarch64_builtin_decls [ bdd -> function_code ] =


<s> RegisterTarget < Triple :: x86 , true > X ( getThe<ISA_LIT>_32Target ( )


<s> int ia32_multipass_dfa_lookahead ( void ) { if ( reload_completed ) return ix86_issue_rate ( ) ; return <NUM_LIT>


<s> static bool pa_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return tls_referenced_p ( x )


<s> getAddrMode6AddressOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & Reg = MI . getOperand ( Op ) ; const MCOperand & Imm = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg . getReg (


<s> writebackLoad = true ; writebackReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Val & ( <NUM_LIT> << i ) ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , i , Address ,

Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static __inline__ TYPE \ NAME ( TYPE * _PTR , TYPE _VALUE ) \ { \ unsigned __int128 _TMP ; \ TYPE _RET ; \ __asm__ volatile ( <STR_LIT> \ <STR_LIT> OPCODE <STR_LIT> \ <STR_LIT> \ : <STR_LIT> ( _PTR [ <NUM_LIT>

] ) , <STR_LIT> ( _TMP ) , <STR_LIT> ( _RET ) \ : <STR_LIT> ( _VALUE ) , <STR_LIT> ( FC ) ) ; \ return _RET ; \ }


<s> if ( ImmNode . getOpcode ( ) == <STR_LIT> ) { if ( ImmNode . getValueType ( ) . getScalarSizeInBits ( ) != ScalarBits ) return false ; ImmNode = ImmNode . getOperand ( <NUM_LIT> ) ; } if ( ImmNode . getValueType ( ) . getScalarSizeInBits ( ) != ScalarBits ) return false ; APFloat ImmAPF ( <NUM_LIT> ) ; switch ( ImmNode . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ! isa < ConstantSDNode > ( ImmNode . getOperand ( <NUM_LIT> ) ) ) return false ; unsigned Imm = ImmNode . getConstantOperandVal ( <NUM_LIT> ) ; if ( ImmNode . getOpcode ( ) == <STR_LIT> ) Imm = <STR_LIT> ( Imm , ScalarBits ) ; ImmAPF = APFloat ( ScalarBits == <NUM_LIT> ? APFloat :: IEEEsingle ( ) : APFloat :: IEEEhalf ( ) , APInt ( ScalarBits , Imm ) ) ; break ; } case <STR_LIT> : { ImmAPF = APFloat ( <STR_LIT> ( ImmNode . getConstantOperandVal ( <NUM_LIT> ) ) ) ; break ; } default : return false ; } APFloat ToConvert = ImmAPF ; if ( FixedToFloat ) { if ( ! ImmAPF . getExactInverse ( & ToConvert ) ) return false ; } APSInt Converted ( <NUM_LIT> , false ) ; bool IsExact ; ToConvert . convertToInteger ( Converted , llvm :: RoundingMode :: NearestTiesToEven , & IsExact ) ; if ( ! IsExact || ! Converted . isPowerOf2 ( ) ) return false ; unsigned FracBits = Converted . logBase2 ( ) ; if ( FracBits > ScalarBits ) return false ; SmallVector < SDValue , <NUM_LIT> > Ops { VecVal , CurDAG -> getConstant ( FracBits , SDLoc ( N ) , <STR_LIT> ) } ; AddEmptyMVEPredicateToOps ( Ops , SDLoc ( N ) , Type ) ; unsigned int Opcode ; switch ( ScalarBits


<s> if ( E ) EVal = <ISA_LIT>MCExpr :: Create ( Variant , E , getParser ( ) .


<s> SDNode * <ISA_LIT>DagToDagISel :: Select ( SDNode


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand ::


<s> if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { if ( <NUM_LIT> * SrcVT . getSizeInBits ( ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> * VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Src . MinElt , dl , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy ) continue ; assert ( ShuffleVT . getVectorElementType ( ) == SmallestEltTy ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , ShuffleVT , Src . ShuffleVec ) ; Src . WindowScale = SrcEltTy . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; Src . WindowBase *= Src . WindowScale ; } DEBUG ( for ( auto Src : Sources ) assert ( Src . ShuffleVec . getValueType ( ) == ShuffleVT ) ; ) ; SmallVector < int , <NUM_LIT> > Mask ( ShuffleVT . getVectorNumElements ( ) , - <NUM_LIT> ) ; int BitsPerShuffleLane = ShuffleVT . getVectorElementType ( ) . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) { SDValue Entry = Op . getOperand


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; Register AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer (

MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ;


<s> z3 :: expr condition = implies ( variables . find ( LHS_name ) -> second , variables . find ( RHS_name ) -> second ) ; func_solver . add ( condition ) ; LHS_depth ++ ; RHS_depth ++ ; while ( LHS_depth < variables_depth [ LHS ] && RHS_depth < variables_depth [ RHS ] ) { LHS_name = LHS_name + <STR_LIT> ; RHS_name = RHS_name + <STR_LIT> ; z3 :: expr condition = ( variables . find ( LHS_name ) -> second == variables . find ( RHS_name ) -> second ) ; func_solver . add ( condition ) ; LHS_depth


<s> unsigned <ISA_LIT>FastISel :: emitASR_ri ( MVT RetVT , MVT SrcVT , unsigned Op0 , bool Op0IsKill , uint64_t Shift , bool IsZExt ) { assert ( RetVT . SimpleTy >= SrcVT . SimpleTy && <STR_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return <ISA_LIT>MaterializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill = true ; } return FastEmitInst_rii ( Opc , RC , Op0 , Op0IsKill , ImmR , ImmS


<s> MachineBasicBlock * DestBB = getDestBlock ( MI ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBlockInRange ( MI , NewDest , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> AnalyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( )

) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> int FI = std :: numeric_limits < int > :: max ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! Register :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode >


<s> static unsigned getStoreRegOpcode ( unsigned SrcReg , const TargetRegisterClass * RC , bool isStackAligned , const <ISA_LIT>Subtarget & STI ) { return getLoadStoreRegOpcode ( SrcReg , RC , isStackAligned , STI ,


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . is256BitVector ( ) && VT . isInteger ( ) && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = Extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 ) , DAG . getNode ( Op . getOpcode


<s> } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Lo_32 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( M0 ( <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Hi_32 ( NumBytes ) ) ; if ( MaybeAlign ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( M1 ( <NUM_LIT> - Log2_64 ( MaybeAlign . valueOrOne ( ) .


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( LoExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT>


<s> return ( x & ( ( <NUM_LIT> << shift ) - <NUM_LIT> ) ) == <NUM_LIT> && x < (

( unsigned ) <NUM_LIT> << ( shift + bits ) ) ;


<s> if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Callee ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName )


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm ( opc1 ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm (


<s> SmallVector < MachineInstr * , <NUM_LIT> > ToErase ; for ( auto * MI : C . instructions ( ) ) if ( Converters . find ( { Domain , MI -> getOpcode ( ) } ) -> second -> convertInstr ( MI , TII , MRI ) ) ToErase . push_back ( MI ) ; for ( Register Reg : C . edges ( ) ) { MRI -> setRegClass ( Reg , getDstRC ( MRI -> getRegClass ( Reg ) ,


<s> void <ISA_LIT>MCCodeEmitter :: EmitByte ( unsigned char C , raw_ostream & OS


<s> return ( __m128i ) __builtin_ia32_vcvtph2uw128_mask ( __A , ( __v8hi ) _mm_setzero_si128 ( ) , (


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> )

, NegVal , N -> getOperand ( <NUM_LIT> ) ) ;


<s> EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV ,


<s> static bool r10k_protected_bb_p ( basic_block bb , sbitmap protected_bbs ) { edge_iterator ei ; edge e ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( ! single_succ_p ( e -> src ) || ! bitmap_bit_p ( protected_bbs , e -> src -> index ) || ( e ->

flags & EDGE_COMPLEX ) != <NUM_LIT> ) return false ;


<s> return __arm_vcvtaq_m_u32_f32 ( __inactive ,


<s> inline vector signed char vec_vminsb ( vector signed char a1 , vector signed char a2 ) { return ( vector signed char ) __builtin_altivec_vminsb ( ( vector signed char ) a1


<s> bool isU16Imm ( ) const { return Kind == Expression || ( Kind ==

Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ) ; }


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>Lowering = Subtarget -> getTargetLowering ( ) ; if ( Subtarget -> hasROPProtect ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const int Result = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; FI -> setROPProtectionHashSaveIndex ( Result ) ; } SelectionDAGISel :: runOnMachineFunction (


<s> unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Op . Reg . RegNum = VM512Regs [ regIdx /


<s> SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] =


<s> if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitInstruction ( TmpInst , getSubtargetInfo ( ) ) ; if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> )


<s> void crx_expand_branch ( enum rtx_code code , rtx label ) { rtx tmp = crx_expand_compare ( code , VOIDmode ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp )


<s> const MCSymbolRefExpr * Sym2 = MCSymbolRefExpr :: create ( BB2 -> getSymbol ( ) , * Ctx ) ; const MCBinaryExpr * Sub = MCBinaryExpr :: createSub ( Sym1 , Sym2


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnes ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return


<s> case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : if ( ! add ) Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; case <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitRDSEED ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_LOAD_SUB ( SDValue Op , SelectionDAG & DAG ) const { auto & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( ! Subtarget . hasLSE ( ) && ! Subtarget . outlineAtomics ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; AtomicSDNode * AN = cast < AtomicSDNode > ( Op . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , dl , VT , DAG .

getConstant ( <NUM_LIT> , dl , VT ) , RHS ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) &&


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , wb , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeAddrMode6Operand ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { default : if ( Rm == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = ( AssignedReg ? MRI . getRegClass ( AssignedReg ) : ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , DestVT , ResultReg , IsZExt ) ) return false ; updateValueMap ( I , ResultReg ) ; return


<s> bool <ISA_LIT>TargetLowering :: areJTsAllowed ( const Function *


<s> SDValue NewBV = DAG . getBitcast ( <STR_LIT> , DAG . getBuildVector ( VT , DL , Ops ) ) ; SDValue Dup = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewBV ) ; return DAG . getBitcast ( VT , Dup ) ; } std :: bitset < <NUM_LIT> > Zeroable , Undefs ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Elt = Op . getOperand ( i ) ; Undefs [ i ] = Elt . isUndef ( ) ; Zeroable [ i ] = ( Elt . isUndef ( ) || <STR_LIT> ( Elt ) ) ; } assert ( Zeroable . size ( ) - Zeroable . count ( ) > <NUM_LIT> && <STR_LIT> ) ; SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op . getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [


<s> void addGPRMM16AsmRegMovePPairFirstOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsDereferenceable = LD -> isDereferenceable ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD -> getAlign ( ) ; RLI . AAInfo = LD -> getAAInfo ( ) ; RLI . Ranges = LD -> getRanges ( ) ; RLI . ResChain = SDValue ( LD , LD -> isIndexed ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> return ( ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTRNMask

( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) ) ;


<s> SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasBMI ( ) && ! Subtarget -> hasTBM ( ) ) return false ; if ( N0 -> getOpcode ( ) != <STR_LIT> && N0 -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! N0 -> hasOneUse ( ) ) return false ; if ( NVT != <STR_LIT> && NVT != <STR_LIT> ) return false ; ConstantSDNode * MaskCst = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftCst = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! MaskCst || ! ShiftCst ) return false ; uint64_t Mask = MaskCst -> getZExtValue ( ) ; if ( ! isMask_64 ( Mask ) ) return false ; uint64_t Shift = ShiftCst -> getZExtValue ( ) ; uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift == <NUM_LIT> && MaskSize == <NUM_LIT> ) return false ; if ( Shift + MaskSize > NVT . getSizeInBits ( ) ) return


<s> Value * <ISA_LIT>TargetLowering :: getIRStackGuard ( IRBuilderBase & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB ,


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> const uint8_t * THMToTHMStub :: getContent ( )


<s> auto MaybeImmed = getImmedFromMO ( Root ) ; if ( MaybeImmed == None ) return None


<s> SDLoc DL ( N ) ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG ) ) return DivRem8 ; if ( ! DCI . isBeforeLegalizeOps ( ) ) { if ( InVT == <STR_LIT> ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , VT ) ; return DAG . getSelect ( DL , VT , N0 , AllOnes , Zero ) ; } return SDValue ( ) ; } if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT ,


<s> static DecodeStatus DecodeACC64DSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> unsigned Slot = getSlot ( RegNo ) ; return Slot < StackTop && Stack


<s> if ( ! all_of ( GEP -> indices ( ) , [ ] ( Value * V ) {

return isa < Constant > ( V ) ; } ) ) return TTI :: TCC_Basic * <NUM_LIT> ;


<s> if ( isNullFPScalarOrVectorConst ( N -> getOperand ( <NUM_LIT> ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( SDValue NewVal = combineFneg ( N , DAG ,


<s> DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue VAList = DAG . getLoad ( <STR_LIT> , dl , InChain , VAListPtr , SV , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG . getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , dl , NextPtr , VAListPtr , SV , <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . getLoad ( VT , dl , InChain , VAList , NULL , <NUM_LIT> ) ; SDValue V = DAG . getLoad ( <STR_LIT> , dl , InChain , VAList , NULL , <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) , V . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , <NUM_LIT> ,


<s> const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( Mnemonic . upper ( ) + std :: string ( PRCTX -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( PRCTX -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } uint16_t PRCTX_Op2 = Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; assert ( PRCTX_Op2 && <STR_LIT> ) ; createSysAlias ( PRCTX -> Encoding << <NUM_LIT> | PRCTX_Op2 , Operands ,


<s> SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , Chain . getValue ( <NUM_LIT> ) , DL ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget . isTargetKnownWindowsMSVC ( ) || Subtarget . isTargetWindowsItanium ( ) || Subtarget . isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget . is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget . is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> , dl ) : ( Subtarget . isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> , dl ) : DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) ) ; SDValue res ; if ( GV -> getThreadLocalMode ( ) == GlobalVariable :: LocalExecTLSModel ) { res = ThreadPointer


<s> <ISA_LIT>ABIFlagsSection & getABIFlagsSection ( ) { return ABIFlagsSection


<s> unsigned <ISA_LIT>FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; const auto & WinEHXMMSlotInfo = <ISA_LIT>FI -> getWinEHXMMSlotInfo ( ) ; unsigned XMMSize = WinEHXMMSlotInfo . size ( ) * TRI -> getSpillSize ( <STR_LIT> ) ; unsigned UsedSize


<s> RestoreGPRRegs . HighGPR = High ; RestoreGPRRegs . GPROffset = Offs


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , this ) { Subtarget = & DefaultSubtarget ; initAsmInfo ( )


<s> unsigned Zeros = countTrailingZeros ( Imm ) ; assert ( Zeros < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CRRegs [ <NUM_LIT> - Zeros ] ) ) ; return MCDisassembler :: Success


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true


<s> case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction


<s> return ( __m128i ) __builtin_ia32_pcmpestrm128 ( ( __v16qi ) __X ,


<s> rtx result ; rtx op0 , op1 , acc ; producer = PATTERN ( producer ) ; consumer = PATTERN ( consumer ) ; if ( GET_CODE ( producer ) == COND_EXEC ) producer = COND_EXEC_CODE ( producer ) ; if ( GET_CODE ( consumer ) == COND_EXEC ) consumer = COND_EXEC_CODE ( consumer ) ; if ( GET_CODE ( producer ) != SET ) return <NUM_LIT> ; result = XEXP ( producer , <NUM_LIT> ) ; if ( GET_CODE ( consumer ) != SET ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( consumer , <NUM_LIT> ) ) == PLUS ) { if ( GET_CODE ( XEXP ( XEXP ( consumer , <NUM_LIT> ) , <NUM_LIT> ) ) != MULT ) return <NUM_LIT> ; op0 = XEXP ( XEXP ( XEXP ( consumer , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; op1 = XEXP ( XEXP ( XEXP ( consumer , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; acc = XEXP ( XEXP ( consumer , <NUM_LIT> ) , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( consumer , <NUM_LIT> ) ) == MINUS ) { if ( GET_CODE ( XEXP ( XEXP ( consumer , <NUM_LIT> ) , <NUM_LIT> )


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false , <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream


<s> RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i

) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> case <STR_LIT> : CC = ( <STR_LIT> ) User -> getConstantOperandVal ( <NUM_LIT> ) ; break ; case <STR_LIT> : CC = ( <STR_LIT> ) User -> getConstantOperandVal ( <NUM_LIT> ) ; break ; } switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return ( float32_t ) __builtin_neon_vget_lanev4sf ( __a ,


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned pos = getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) , Fixups ) ; unsigned sz = getMachineOpValue ( MI , MI . getOperand ( OpNo ) ,


<s> Value * <ISA_LIT>IREmitter :: visitMUL_IMM ( const SDNode * N


<s> break ; case MachineOperand :: MO_Register : if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ; OutStreamer -> emitInstruction ( CallInst , getSubtargetInfo ( ) ) ; } auto & Ctx = OutStreamer ->


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && IsComplex ) return NumVectorInstToHideOverhead ; return TargetTransformInfo :: getAddressComputationCost ( Ty , IsComplex


<s> if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( auto & CS : reverse ( CSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } return


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; else { assert ( MO . isImm ( ) && <STR_LIT> ) ; return static_cast < unsigned > ( MO . getImm ( ) ) ; } assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> expandStoreACC ( MBB , I , <NUM_LIT> ) ; break ; case <STR_LIT> : expandStoreACC ( MBB , I , <NUM_LIT> ) ; break ; case TargetOpcode :: COPY : if ( ! expandCopy ( MBB , I ) ) return false ; break ; default : return false ; } MBB . erase ( I ) ; return true


<s> default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F ->


<s> register unsigned shift ; for ( shift = <NUM_LIT> ; shift < <NUM_LIT> ; shift += <NUM_LIT> , type = TREE_TYPE ( type ) ) { switch ( TREE_CODE ( type ) ) { case ERROR_MARK : return qualifiers ; case ARRAY_TYPE : qualifiers |= ( <NUM_LIT> << shift ) ; break ; case FUNCTION_TYPE : case METHOD_TYPE : qualifiers |= ( <NUM_LIT> << shift ) ; break ; case POINTER_TYPE : case REFERENCE_TYPE : case OFFSET_TYPE : qualifiers |= ( <NUM_LIT> << shift ) ; break ; case RECORD_TYPE : return ( qualifiers | <NUM_LIT> ) ; case UNION_TYPE : case QUAL_UNION_TYPE : return ( qualifiers | <NUM_LIT> ) ; case ENUMERAL_TYPE : return ( qualifiers | <NUM_LIT> ) ; case VOID_TYPE : return ( qualifiers | <NUM_LIT> ) ; case INTEGER_TYPE : if ( TREE_TYPE ( type ) != <NUM_LIT> ) break ; if ( TYPE_PRECISION ( type ) <= CHAR_TYPE_SIZE ) return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; else if ( TYPE_PRECISION ( type ) <= SHORT_TYPE_SIZE ) return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; else if ( TYPE_PRECISION ( type ) <= INT_TYPE_SIZE ) return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; else return ( qualifiers | ( TYPE_UNSIGNED ( type ) ?


<s> ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands ( ) && <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = *


<s> Register Reg ; if ( parseRegister ( Reg ) ) return true ; if ( Reg . Group == RegGR ) RegNo = <STR_LIT> [ Reg . Num ] ; else if ( Reg . Group == RegFP ) RegNo = <STR_LIT> [ Reg . Num ] ; else return Error ( Reg . StartLoc , <STR_LIT> ) ; StartLoc = Reg


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst ) ; else Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; return DAG . getNode ( <STR_LIT> ,


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isGP64Bit (

) ) return DecodeGPR64RegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> static bool aarch64_modifies_global_state_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode


<s> bool mustAddCurrentAddress ( ) const { return AddCurrentAddress


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_storeu_epi32 ( void *


<s> assert ( Displacement >= MinAllowedDisplacement &&

Displacement <= MaxAllowedDisplacement ) ;


<s> SDValue Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; unsigned Scale = APInt ( <NUM_LIT> , Bits ) . exactLogBase2 ( ) - <NUM_LIT> ; const bool IsRegReg = SelectSVERegRegAddrMode ( Base , Scale , Base , Offset ) ; const unsigned Opc = ( IsRegReg ) ? Opc_rr : Opc_ri ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , Base , Offset , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType (


<s> else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand ::


<s> const MCSectionELF & ES = static_cast < const MCSectionELF & > ( Section ) ; return ES . getFlags (


<s> void VZeroUpperInserter :: processBasicBlock ( MachineBasicBlock & MBB ) { BlockExitState CurState = PASS_THROUGH ; BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = MBB . end ( ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { MachineInstr * MI = I ; bool IsReturnFrom<ISA_LIT>INTR = Is<ISA_LIT>INTR && MI -> isReturn ( ) ; bool IsControlFlow = MI -> isCall ( ) || MI -> isReturn ( ) ; if ( ( ! IsControlFlow || IsReturnFrom<ISA_LIT>INTR ) && CurState == EXITS_DIRTY ) continue ; if ( hasYmmReg ( MI ) ) { CurState = EXITS_DIRTY ; continue ; } if ( ! IsControlFlow || IsReturnFrom<ISA_LIT>INTR ) continue ; if ( MI -> isCall ( ) && ! callClobbersAnyYmmReg ( MI ) ) continue ; if ( CurState == EXITS_DIRTY ) { insertVZeroUpper ( I , MBB ) ; CurState = EXITS_CLEAN ; } else if ( CurState == PASS_THROUGH ) { BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = I ; CurState = EXITS_CLEAN ; } } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << getBlockExitStateName ( CurState ) << '\n' ) ; if ( CurState == EXITS_DIRTY ) for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; BlockStates [ MBB . getNumber ( ) ]


<s> return __builtin_mve_vqrdmlahq_n_sv4si ( __a ,


<s> if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , WidenedMask ) ) ; } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) SumV2Indices += i ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) NumV1OddIndices += i


<s> static TargetLoweringObjectFile * CreateTLOF ( const <ISA_LIT>TargetMachine & TM ) { if ( TM . getSubtargetImpl ( ) -> isDarwin ( ) ) return new <ISA_LIT>MachOTargetObjectFile ( ) ; return new TargetLoweringObjectFileELF (


<s> PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; AlignmentIsInBytes =


<s> unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( requiresRegisterScavenging ( MF ) ) { if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex , SPAdj , RS ) ; return ; } } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; MI . getOperand ( FIOperandNo ) . ChangeToRegister ( TFI -> hasFP ( MF ) ? ( is64Bit ? <STR_LIT> : <STR_LIT> ) : ( is64Bit ? <STR_LIT> : <STR_LIT> ) , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr )


<s> unsigned ShortestLength = <NUM_LIT> ; for ( InstSeqLs :: iterator S = SeqLs . begin ( ) ; S != SeqLs . end ( ) ; ++ S ) { ReplaceADDiuSLLWithLUi ( * S ) ; assert ( S -> size ( ) <= <NUM_LIT> ) ; if ( S -> size ( ) < ShortestLength ) { ShortestSeq = S ; ShortestLength = S -> size


<s> static machine_mode type_natural_mode ( const_tree type , const CUMULATIVE_ARGS * cum , bool in_return ) { machine_mode mode = TYPE_MODE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE && ! VECTOR_MODE_P ( mode ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) && TYPE_VECTOR_SUBPARTS ( type ) > <NUM_LIT> ) { machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( innermode == XFmode ) return mode ; if ( DECIMAL_FLOAT_MODE_P ( innermode ) ) return mode ; if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) mode = MIN_MODE_VECTOR_FLOAT ; else mode = MIN_MODE_VECTOR_INT ; FOR_EACH_MODE_FROM ( mode , mode ) if ( GET_MODE_NUNITS ( mode ) == TYPE_VECTOR_SUBPARTS ( type ) && GET_MODE_INNER ( mode ) == innermode ) { if ( size == <NUM_LIT> && ! TARGET_AVX512F && ! TARGET_IAMCU ) { static bool warnedavx512f ; static bool warnedavx512f_ret ; if ( cum && cum -> warn_avx512f && ! warnedavx512f ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx512f = true ; } else if ( in_return && ! warnedavx512f_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx512f_ret = true ; } return TYPE_MODE ( type ) ; } else if ( size == <NUM_LIT> && ! TARGET_AVX && ! TARGET_IAMCU ) { static bool warnedavx ; static bool warnedavx_ret ; if ( cum && cum -> warn_avx && ! warnedavx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx = true ; } else if ( in_return && ! warnedavx_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx_ret = true ; } return TYPE_MODE ( type ) ; } else if ( ( ( size == <NUM_LIT> && TARGET_64BIT ) || size == <NUM_LIT> ) && ! TARGET_SSE && ! TARGET_IAMCU ) { static bool warnedsse ; static bool warnedsse_ret ; if ( cum && cum -> warn_sse && ! warnedsse ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse = true ; } else if ( ! TARGET_64BIT && in_return && ! warnedsse_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse_ret = true ; } } else if ( ( size == <NUM_LIT> && ! TARGET_64BIT ) && ( ! cfun || cfun -> machine -> func_type == TYPE_NORMAL ) && ! TARGET_MMX && ! TARGET_IAMCU ) { static bool warnedmmx ; static bool warnedmmx_ret ; if ( cum && cum -> warn_mmx && ! warnedmmx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT>


<s> unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = Subtarget . isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else


<s> ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; return ret


<s> else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return nullptr ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; Done = true ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; LoadedVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , LoadedVal , SubReg ) , <NUM_LIT> ) ; } ReplaceUses ( SDValue ( N ,


<s> static DecodeStatus DecodeGPR64spRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT>


<s> unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction :: Load ) { if ( const auto * Entry = CostTableLookup ( AVX2InterleavedLoadTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } else { assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; if ( const auto * Entry = CostTableLookup ( AVX2InterleavedStoreTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices


<s> assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) || ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) ) FrameReg = <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; int Offset ; if ( <ISA_LIT>FI -> isOutArgFI ( FrameIndex ) || <ISA_LIT>FI -> isGPFI ( FrameIndex ) || <ISA_LIT>FI -> isDynAllocFI ( FrameIndex ) ) Offset = spOffset ; else Offset = spOffset + stackSize ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ( Offset >= <NUM_LIT> || Offset < - <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; int ImmHi = ( ( ( unsigned ) Offset & <NUM_LIT> ) >> <NUM_LIT> ) + ( ( Offset & <NUM_LIT> ) != <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) .


<s> int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 ) return <NUM_LIT> ; if ( USE_ALTIVEC_FOR_ARG_P ( cum , elt_mode , named ) ) { if ( TARGET_64BIT && ! cum -> prototype && ( ! cum -> libcall || ! FLOAT128_VECTOR_P ( elt_mode ) ) ) return <NUM_LIT> ; passed_in_gprs = false ; if ( cum -> vregno + n_elts > ALTIVEC_ARG_MAX_REG + <NUM_LIT> ) ret = ( ALTIVEC_ARG_MAX_REG + <NUM_LIT> - cum -> vregno ) * <NUM_LIT> ; } if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( mode , type ) ) return <NUM_LIT> ; align_words = rs6000_parm_start ( mode , type , cum -> words ) ; if ( USE_FP_FOR_ARG_P ( cum , elt_mode ) ) { unsigned long n_fpreg = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; if ( type && ( cum -> nargs_prototype <= <NUM_LIT> || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) return <NUM_LIT> ; passed_in_gprs = false ; if ( cum -> fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + <NUM_LIT> ) { int fpr = ( ( FP_ARG_MAX_REG + <NUM_LIT> - cum -> fregno ) * MIN ( <NUM_LIT> , GET_MODE_SIZE ( elt_mode ) ) ) ; int fpr_words = fpr / ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( align_words + fpr_words <

GP_ARG_NUM_REG ) passed_in_gprs = true ;


<s> bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get


<s> return ( __mmask16 ) __builtin_ia32_kmovw ( * ( __mmask16 * )


<s> static bool mips_valid_pointer_mode ( machine_mode mode


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> StringRef getPassName ( ) const override { return


<s> return __builtin_mve_vmlaldavxq_p_sv4si ( __a ,


<s> static SDValue getIndexFromUnindexedLoad ( LoadSDNode * Ld ) { if ( Ld -> isIndexed ( ) ) return SDValue ( ) ; SDValue Base = Ld -> getBasePtr ( ) ; if ( Base . getOpcode ( )


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn (


<s> return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype


<s> return ( __m128d ) __builtin_ia32_andnpd ( ( __v2df ) __A , (


<s> if ( ! ISA_HAS_LL_SC ) output_asm_insn ( <STR_LIT>


<s> if ( TM . getSubtargetImpl ( ) -> in<ISA_LIT>16Mode ( ) ) return llvm ::


<s> if ( Res != sets [ reg ] . end ( ) ) return & ( Res -> second ) ; return


<s> void <ISA_LIT>DCModule :: insertExternalWrapperAsm ( BasicBlock * InsertAtEnd , Value * ExternalFunc , Value *


<s> __builtin_ia32_pmovsqw128mem_mask ( ( unsigned int * ) __P , ( __v2di ) __A , __M


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && <STR_LIT> (

I -> getOpcode ( ) ) == <STR_LIT> ) break ;


<s> static void nds32_emit_load_store ( rtx reg , rtx mem , enum machine_mode mode , int offset


<s> const MCExpr * Expr = <NUM_LIT> ; MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr ::


<s> void <ISA_LIT>InstPrinter :: printThumbS4ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << MI -> getOperand ( OpNum )

. getImm ( ) * <NUM_LIT> << markup ( <STR_LIT> ) ;


<s> if ( ! isa < ScalableVectorType > ( Ty ) ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ; assert ( ( isa < ScalableVectorType > ( Ty ) && isa < ScalableVectorType > ( CondTy ) ) && <STR_LIT> ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; InstructionCost LegalizationCost = <NUM_LIT> ; if ( LT . first > <NUM_LIT> ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( Ty -> getContext ( ) ) ; unsigned CmpOpcode = Ty -> isFPOrFPVectorTy ( ) ? Instruction :: FCmp : Instruction :: ICmp ; LegalizationCost = getCmpSelInstrCost ( CmpOpcode , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) + getCmpSelInstrCost ( Instruction :: Select ,

LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ;


<s> } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getConstant ( C . ICmpType , DL , <STR_LIT> ) ) ; if ( C . Opcode == <STR_LIT> ) { bool RegisterOnly = ( bool ( C . CCMask & <STR_LIT> ) != bool ( C . CCMask & <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getConstant ( RegisterOnly , DL , <STR_LIT> ) ) ; } return DAG . getNode ( C . Opcode , DL , <STR_LIT> ,


<s> bool <ISA_LIT>PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false


<s> if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * target = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned CmpOpc ; if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiOpc ; else if ( ( ! ImmSigned && isUInt < <NUM_LIT> > ( imm ) ) || ( ImmSigned && isInt < <NUM_LIT>


<s> static SDValue LowerVectorCTLZ_AVX512CDI ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems > <NUM_LIT> || ( NumElems == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) ) return LowerVectorIntUnary ( Op , DAG ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector ( )


<s> } else { NonclearedFPRegs . push_back ( Reg ) ; } } } } bool passesFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; if ( passesFPReg ) assert ( STI -> hasFPRegs ( ) && <STR_LIT> ) ; MachineInstrBuilder VLSTM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( auto R : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) VLSTM . addReg ( R , RegState :: Implicit | ( LiveRegs . contains ( R ) ? <NUM_LIT> : RegState :: Undef ) ) ; for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add (


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Opcode == <STR_LIT> ) OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return false


<s> SDValue AddInputValue1 = AddValue . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue AddInputValue2 = AddValue . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubsInputValue = SubsNode -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( AddInputValue2 . getNode ( ) ) || ! isa < ConstantSDNode > ( SubsInputValue . getNode ( ) ) ) return SDValue ( ) ; <STR_LIT> ExtType ; if ( ! checkValueWidth ( SubsInputValue , MaskBits , ExtType ) || ! checkValueWidth ( AddInputValue2 , MaskBits , ExtType ) || ! checkValueWidth ( AddInputValue1 , MaskBits , ExtType ) ) return SDValue ( ) ; if ( ! isEquivalentMaskless ( CC , MaskBits , ExtType , cast < ConstantSDNode > ( AddInputValue2 . getNode ( ) ) -> getSExtValue ( ) , cast < ConstantSDNode

> ( SubsInputValue . getNode ( ) ) -> getSExtValue ( ) ) ) return SDValue ( ) ;


<s> unsigned computeState ( unsigned PrevState , unsigned CurState ) { if ( PrevState == ST_INIT ) return CurState ; if ( PrevState == ST_DIRTY || CurState == ST_DIRTY ) return ST_DIRTY ; if ( PrevState == ST_CLEAN && CurState == ST_CLEAN ) return ST_CLEAN ; return ST_UNKNOWN


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ; AFI -> setVarArgsFrameIndex ( FrameIndex


<s> static __inline qword si_chd ( qword a , int imm ) { union { vec_uint4 v ; unsigned short s [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> ,


<s> bool hasCn<ISA_LIT>P ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> case LABEL_REF : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode && ( ( CONST_DOUBLE_HIGH ( x ) == <NUM_LIT> && CONST_DOUBLE_LOW ( x ) < <NUM_LIT> ) || ( CONST_DOUBLE_HIGH ( x ) == - <NUM_LIT> && CONST_DOUBLE_LOW ( x ) < <NUM_LIT> && CONST_DOUBLE_LOW ( x ) >= - <NUM_LIT> ) ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case MEM : if ( outer_code == ZERO_EXTEND ) { * total = sparc_costs -> int_zload - COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == SIGN_EXTEND ) { * total = sparc_costs -> int_sload - COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( float_mode_p ) { * total = sparc_costs -> float_load ; } else { * total = sparc_costs -> int_load ; } return true ; case PLUS : case MINUS : if ( float_mode_p ) * total = sparc_costs -> float_plusminus ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case FMA : { rtx sub ; gcc_assert ( float_mode_p ) ; * total = sparc_costs -> float_mul ; sub = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == NEG ) sub = XEXP ( sub , <NUM_LIT> ) ; * total += rtx_cost ( sub , FMA , <NUM_LIT> , speed ) ; sub = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == NEG ) sub = XEXP ( sub , <NUM_LIT> ) ; * total += rtx_cost ( sub , FMA , <NUM_LIT> , speed ) ; return true ; } case MULT : if ( float_mode_p ) * total = sparc_costs -> float_mul ; else if ( TARGET_ARCH32 && ! TARGET_HARD_MUL ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else { int bit_cost ; bit_cost = <NUM_LIT> ; if ( sparc_costs -> int_mul_bit_factor ) { int nbits ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; for ( nbits = <NUM_LIT> ; value != <NUM_LIT> ; value &= value - <NUM_LIT> ) nbits ++ ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_DOUBLE && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == VOIDmode ) { rtx x1 = XEXP ( x , <NUM_LIT> ) ; unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW ( x1 ) ; unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH ( x1 ) ; for ( nbits = <NUM_LIT> ; value1 != <NUM_LIT> ; value1 &= value1 - <NUM_LIT> ) nbits ++ ; for ( ; value2 != <NUM_LIT> ; value2 &= value2 - <NUM_LIT> ) nbits ++ ; } else nbits = <NUM_LIT> ; if ( nbits < <NUM_LIT> ) nbits =


<s> bool <ISA_LIT>MCCodeEmitter :: isMicro<ISA_LIT> ( const MCSubtargetInfo


<s> static SDValue getMOVL ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int ,


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( create<ISA_LIT>ParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Align = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( Align ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> )


<s> static SDValue getTargetShuffleNode ( unsigned Opc , DebugLoc dl , EVT VT , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( F -> hasFnAttribute ( Attribute :: StackAlignment ) ) { if ( ! CanRealign ) DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; return CanRealign ; } unsigned StackAlignment = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; if ( MFI -> getMaxAlignment ( ) > StackAlignment ) { if ( ! CanRealign ) DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName (


<s> unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ; unsigned Offset = ( Insn &


<s> SDValue Arg = isFNEG ( DAG , N ) ; if ( ! Arg ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = Arg . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; SDLoc DL ( N ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; return DAG . getBitcast ( OrigVT , NewNode ) ; } bool CodeSize = DAG . getMachineFunction ( ) . getFunction (


<s> const bool IsPurecap = TT . getEnvironment ( ) == Triple :: CheriPurecap || Options . ABIName == <STR_LIT> ; unsigned SP = MRI . getDwarfRegNum ( IsPurecap ? <STR_LIT>


<s> uint64_t BString = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; return ( ( BString == <NUM_LIT> || BString == <NUM_LIT> ) && (


<s> if ( ( flags & OPTION_MASK_MFCRF ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_FPRND ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MFPGPR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P9_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY_ATOMIC ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CRYPTO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_FLOAT128_KEYWORD ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( define_p ) rs6000_define_or_undefine_macro ( true , <STR_LIT> ) ; else rs6000_define_or_undefine_macro ( false , <STR_LIT>


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; } for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>64Target } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEB ) ; for ( Target * T : { & The<ISA_LIT>elTarget , & The<ISA_LIT>64elTarget } ) TargetRegistry ::

RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEL ) ;


<s> ArrayRef < MachineConstantPoolEntry > Constants = MI . getParent ( ) -> getParent ( ) -> getConstantPool ( ) -> getConstants ( ) ; const MachineConstantPoolEntry & ConstantEntry = Constants [ Op . getIndex ( ) ] ; if ( ConstantEntry . isMachineConstantPoolEntry ( ) ) return nullptr ; const Constant * C =


<s> if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NegShift = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue NegShiftLeft = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Opc , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , NegShift ) ; return NegShiftLeft ; } return SDValue ( )


<s> static DecodeStatus DecodeMveVCTP ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address ,

Decoder ) ) ) return MCDisassembler :: Fail ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = <NUM_LIT> ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple


<s> bool hasNo<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = F . getFnAttribute ( <STR_LIT> ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) { resetTargetOptions (


<s> case FK_Data_2 : case FK_GPRel_4 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc (


<s> if ( ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return


<s> parse_codes result = PC_OK ; diag = & ovld_diag ; if ( ! advance_line ( ovld_file ) ) return PC_OK ; while ( result == PC_OK ) result = parse_ovld_stanza ( ) ; if ( result ==


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfo64bit ( ) { if ( ! Subtarget . is64Bit (


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG ) ) return DivRem8 ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ; return SDValue


<s> return ( int32x2_t ) __builtin_aarch64_srhaddv2si ( __a ,


<s> unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } else if ( ! UseSExt && isUInt < <NUM_LIT> > ( CI -> getZExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm (


<s> void <ISA_LIT>InstrInfo :: insertSelect ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DstReg , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo (


<s> liveInstrs . insert ( _liveInstrs . begin (


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; return