<s> if ( ! Reg . isVirtual ( ) ) return ; if ( EnclosedEdges . test ( Register :: virtReg2Index ( Reg ) ) ) return ; if ( ! MRI -> hasOneDef ( Reg ) ) return ; RegDomain RD = getDomain ( MRI -> getRegClass ( Reg ) , MRI -> getTargetRegisterInfo ( ) ) ; if ( Domain == NoDomain ) Domain


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadRetAddr ( SelectionDAG & DAG , SDValue & OutRetAddr , SDValue Chain , bool IsTailCall , bool Is64Bit , int FPDiff , SDLoc dl ) const { EVT VT = getPointerTy ( DAG . getDataLayout ( ) ) ; OutRetAddr = getReturnAddressFrameIndex ( DAG


<s> if ( mips_split_move_p ( dest , src , split_type ) ) mips_split_move ( dest , src , split_type


<s> <ISA_LIT>LegalizerInfo :: <ISA_LIT>LegalizerInfo ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>TargetMachine & TM ) : Subtarget ( STI ) , TM ( TM ) { setLegalizerInfo32bit ( ) ; setLegalizerInfo64bit ( ) ; setLegalizerInfoSSE1 ( ) ; setLegalizerInfoSSE2 ( ) ; setLegalizerInfoSSE41 ( ) ; setLegalizerInfoAVX ( ) ; setLegalizerInfoAVX2 ( ) ; setLegalizerInfoAVX512 ( ) ; setLegalizerInfoAVX512DQ ( ) ; setLegalizerInfoAVX512BW (


<s> op1 = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else gcc_unreachable ( ) ; temp = gen_reg_rtx ( vmode ) ; mask = ix86_build_signbit_mask ( vmode , <NUM_LIT> , <NUM_LIT> ) ; op1 = lowpart_subreg ( vmode , force_reg ( mode , op1 )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO , unsigned offset ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset


<s> if ( ST . getProcFamily ( ) != <ISA_LIT>Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > (


<s> auto & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) { ArgInfo & OutArg = OutArgs . back ( ) ; assert ( OutArg . Regs . size ( ) == <NUM_LIT> && MRI . getType ( OutArg . Regs [ <NUM_LIT> ] ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OutArg . Regs [ <NUM_LIT> ] = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , OutArg . Regs [ <NUM_LIT> ] ) . getReg ( <NUM_LIT> ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; OutArg . Ty = Type :: getInt8Ty ( Ctx ) ; } } SmallVector < ArgInfo , <NUM_LIT> > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; bool CanTailCallOpt = isEligibleForTailCallOptimization ( MIRBuilder , Info , InArgs , OutArgs ) ; if ( Info . IsMustTailCall && ! CanTailCallOpt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Info . IsTailCall = CanTailCallOpt ; if ( CanTailCallOpt ) return lowerTailCall ( MIRBuilder , Info , OutArgs ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info


<s> const TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT>

|| RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ;


<s> if ( ( AddConstant == <NUM_LIT> ) || ( CompConstant == MaxUInt - <NUM_LIT> && AddConstant < <NUM_LIT> ) || ( AddConstant >= <NUM_LIT> && CompConstant < <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant <= <NUM_LIT> && CompConstant < AddConstant ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( AddConstant == <NUM_LIT> ) || ( AddConstant >= <NUM_LIT> && CompConstant <= <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant <= <NUM_LIT> && CompConstant <= AddConstant ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( AddConstant >= <NUM_LIT> && CompConstant < <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant >= -

<NUM_LIT> && CompConstant < AddConstant + MaxUInt ) ) return true ;


<s> case <STR_LIT> : return instCombineSVEDup ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVECmpNE ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEVectorMul ( IC , II ) ; case <STR_LIT> : return instCombineSVETBL ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEUnpack ( IC , II ) ; } return


<s> if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSX ( ) && <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] =


<s> void \ readonly_data ( ) \ { \ if ( in_section != in_readonly_data ) \ { \ if ( flag_pic ) \ fprintf ( asm_out_file , <STR_LIT> , DATA_SECTION_ASM_OP ) ; \ else \

fprintf ( asm_out_file , <STR_LIT> , READONLY_DATA_ASM_OP ) ; \ in_section = in_readonly_data ; \ } \ }


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue (


<s> int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; return gen_rtx_CONST_VECTOR ( mode , v


<s> if ( pcs_variant != ARM_PCS_AAPCS ) { int i ; for ( i = <NUM_LIT> ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) if ( aapcs_cp_arg_layout [ i ] . is_return_candidate ( pcs_variant , TYPE_MODE ( type ) , type ) ) return i ; } return -


<s> bool SelectAddrImmOffs ( SDNode * Op , SDValue N , SDValue & Out ) const { Out = N ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; if ( HasFP && is<ISA_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! AFI -> isThumb1OnlyFunction (


<s> static DecodeStatus DecodeF4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address ,


<s> return ( __m64 ) __builtin_arm_wcmpeqb ( ( __v8qi ) __m1 ,


<s> Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue StoreChain = DAG . getEntryNode ( ) ; SDValue Ops [ ] = { StoreChain , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value , FIdx } ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; StoreChain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , <STR_LIT> , PtrInfo ) ; unsigned Offset = <NUM_LIT> * cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Idx = DAG . getConstant ( Offset , dl , FIdx . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , FIdx . getValueType ( ) , FIdx , Idx ) ; SDValue IntVal = DAG . getLoad ( <STR_LIT> , dl , StoreChain

, Idx , PtrInfo . getWithOffset ( Offset ) ) ;


<s> AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } InstrumentMOVSImpl ( AccessSize , Ctx ,


<s> void <ISA_LIT>TargetLowering :: saveVarArgRegisters ( CCState & CCInfo , SelectionDAG & DAG , const SDLoc & DL , SDValue & Chain ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool IsWin64 = Subtarget -> isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumGPRArgRegs = array_lengthof ( GPRArgRegs ) ; unsigned FirstVariadicGPR = CCInfo . getFirstUnallocated ( GPRArgRegs ) ; unsigned GPRSaveSize = <NUM_LIT> * ( NumGPRArgRegs - FirstVariadicGPR ) ; int GPRIdx = <NUM_LIT> ; if ( GPRSaveSize != <NUM_LIT> ) { if ( IsWin64 ) { GPRIdx = MFI . CreateFixedObject ( GPRSaveSize , - ( int ) GPRSaveSize , false ) ; if ( GPRSaveSize & <NUM_LIT> ) MFI . CreateFixedObject ( <NUM_LIT> - ( GPRSaveSize & <NUM_LIT> ) , - ( int ) alignTo ( GPRSaveSize , <NUM_LIT> ) , false ) ; } else GPRIdx = MFI . CreateStackObject ( GPRSaveSize ,


<s> return ( uint16x4_t ) __builtin_neon_vcgezv4hf (


<s> BasicBlock * BB = MemI -> getParent ( ) ; if ( ! BB ) return false ; BasicBlock * PredBB = L -> getLoopPredecessor ( ) ; BasicBlock * LatchBB = L -> getLoopLatch ( ) ; if ( ! PredBB || ! LatchBB ) return false ; iterator_range < BasicBlock :: phi_iterator > PHIIter = BB -> phis ( ) ; for ( auto & CurrentPHI : PHIIter ) { PHINode * CurrentPHINode = dyn_cast < PHINode > ( & CurrentPHI ) ; if ( ! CurrentPHINode ) continue ; if ( ! SE -> isSCEVable ( CurrentPHINode -> getType ( ) ) ) continue ; const SCEV * PHISCEV = SE -> getSCEVAtScope ( CurrentPHINode , L ) ; const SCEVAddRecExpr * PHIBasePtrSCEV = dyn_cast < SCEVAddRecExpr > ( PHISCEV ) ; if ( ! PHIBasePtrSCEV )


<s> virtual const char * getPassName ( )


<s> const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; bool ReqIndirectLoad = Func . hasFnAttribute ( <STR_LIT> ) && ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass


<s> void <ISA_LIT>AsmParser :: cvtLdrdPre ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ->

addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI . readsRegister ( Reg , TRI


<s> unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) for ( unsigned i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { unsigned Base = i + Imm ; int M = Base + l ; if ( Base >= NumLaneElts )


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable (


<s> const <ISA_LIT>TargetLowering * <ISA_LIT>TargetLowering :: create ( const <ISA_LIT>TargetMachine & TM


<s> case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc , Instructions


<s> return ( __m128i ) __builtin_ia32_vpcomfalsed ( ( __v4si ) __A , ( __v4si )


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg


<s> static void printUImmOperand ( const MCInst * MI , int


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT EltTy = VT . getVectorElementType ( ) ; if ( EltTy . isFloatingPoint ( ) || EltTy . getSizeInBits ( ) > <NUM_LIT> ) return Op ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( SDValue Lane : Op -> ops ( ) ) { if ( auto * CstLane = dyn_cast < ConstantSDNode > ( Lane


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , createMachOStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , createWinCOFFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } for ( Target * T : { & getThe<ISA_LIT>leTarget ( ) , & getThe<ISA_LIT>_32Target ( ) , & getTheARM64Target ( ) , & getTheARM64_32Target ( ) } ) TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend


<s> if ( ZeroIdx != - <NUM_LIT> ) { SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) { if ( Bytes [ I ] >= <NUM_LIT> ) { unsigned OpNo = unsigned ( Bytes [ I ] ) / <STR_LIT> ; unsigned Byte = unsigned ( Bytes [ I ] ) % <STR_LIT> ; if ( OpNo == ZeroVecIdx ) IndexNodes [ I ] = DAG . getConstant ( ZeroIdx , DL , <STR_LIT> ) ; else { unsigned BIdx = MaskFirst ? Byte + <STR_LIT> : Byte ; IndexNodes [ I ] = DAG . getConstant ( BIdx , DL , <STR_LIT> ) ; } } else IndexNodes [ I ] = DAG . getUNDEF ( <STR_LIT> ) ; } SDValue Mask = DAG . getBuildVector ( <STR_LIT> , DL , IndexNodes ) ; SDValue Src = ZeroVecIdx == <NUM_LIT> ? Ops [ <NUM_LIT> ] : Ops [ <NUM_LIT> ] ; if ( MaskFirst ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , Src , Mask ) ; else return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , Mask , Mask ) ; } } SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) if ( Bytes [ I ] >= <NUM_LIT> ) IndexNodes [ I ] =

DAG . getConstant ( Bytes [ I ] , DL , <STR_LIT> ) ;


<s> if ( RelocM == Reloc :: Static ) return false ; return ! GV -> hasLocalLinkage ( ) &&


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; } Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [


<s> return std :: max ( std :: min ( MaxAllowedDisplacement

, Displacement ) , MinAllowedDisplacement ) ;


<s> return Kind == k_Register && ! Reg . isVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> return ( __m256i ) __builtin_ia32_maskloadq256 ( ( const __v4di * )


<s> switch ( State ) { default : State = IES_ERROR ; break ; case IES_LPAREN : setType ( Type ) ; State =


<s> unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; bool Is32Bit = Size == <NUM_LIT> ; if ( auto Fns = selectArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectShiftedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS ,


<s> mask = ( cnt & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ; return ( ( qword ) ( vec_and ( vec_sro ( ( vec_uchar16 ) (


<s> StringRef getToken ( ) const { assert ( Kind == Token &&


<s> SDLoc DL ( Op ) ; MaskedGatherSDNode * MGT = cast < MaskedGatherSDNode > ( Op ) ; assert ( MGT && <STR_LIT> ) ; bool IsFixedLength = MGT -> getMemoryVT ( ) . isFixedLengthVector ( ) ; SDValue Index = MGT -> getIndex ( ) ; SDValue Chain = MGT -> getChain ( ) ; SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Mask = MGT -> getMask ( ) ; SDValue BasePtr = MGT -> getBasePtr ( ) ; <STR_LIT> ExtTy = MGT -> getExtensionType ( ) ; <STR_LIT> IndexType = MGT -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IdxNeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; bool ResNeedsSignExtend = ExtTy == <STR_LIT> || ExtTy == <STR_LIT> ; EVT VT = PassThru . getSimpleValueType ( ) ; EVT IndexVT = Index . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; if ( MemVT . getScalarSizeInBits ( ) <= IndexVT . getScalarSizeInBits ( ) ) { IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; } else { MemVT = getContainerForFixedLengthVector ( DAG , MemVT ) ; IndexVT = MemVT . changeTypeToInteger ( ) ; } InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } if ( PassThru -> isUndef ( ) || isZerosVector ( PassThru . getNode ( ) ) ) PassThru = SDValue ( ) ; if ( VT . isFloatingPoint ( ) && ! IsFixedLength ) { if ( PassThru ) { EVT PassThruVT = getPackedSVEVectorVT ( VT . getVectorElementCount


<s> bool <ISA_LIT>InstPrinter :: isV9 ( const MCSubtargetInfo & STI ) const { return ( STI . getFeatureBits ( ) [ <STR_LIT> ]


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC )


<s> } * fusion_pri = tmp - fusion * FIRST_PSEUDO_REGISTER - REGNO ( base ) ; tmp /= <NUM_LIT> ; off_val = ( int ) ( INTVAL ( offset ) ) ; if ( off_val >= <NUM_LIT> ) tmp -= ( off_val & <NUM_LIT> ) ; else tmp += ( ( -


<s> return ( __mmask8 ) __builtin_ia32_cmpq512_mask ( ( __v8di ) __X , ( __v8di )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ; } ; auto DistrubuteAddAddVecReduce = [ & ] ( SDValue N0 , SDValue N1 ) { if ( VT == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> && ! IsVecReduce ( N0 ) && IsVecReduce ( N1 . getOperand ( <NUM_LIT> ) ) && IsVecReduce ( N1 . getOperand ( <NUM_LIT> ) ) && ! isa < ConstantSDNode > ( N0 ) ) { SDValue Add0 = DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Add0 , N1 . getOperand ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) { unsigned N0RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N0 . getOperand ( N0RedOp ) ) ) { N0RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N0 . getOperand ( N0RedOp ) ) ) return SDValue ( ) ; } unsigned N1RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N1 . getOperand ( N1RedOp ) ) ) N1RedOp = <NUM_LIT> ; if ( ! IsVecReduce ( N1 . getOperand ( N1RedOp ) ) ) return SDValue ( ) ; SDValue Add0 = DAG . getNode ( <STR_LIT> , dl , VT , N0 . getOperand ( <NUM_LIT> - N0RedOp ) , N1 . getOperand ( <NUM_LIT> - N1RedOp ) ) ; SDValue Add1 = DAG . getNode ( <STR_LIT> , dl , VT , Add0 , N0 . getOperand ( N0RedOp ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Add1 , N1 . getOperand ( N1RedOp ) ) ; } return SDValue ( ) ; } ; if ( SDValue R = DistrubuteAddAddVecReduce ( N0 , N1 ) ) return R ; if ( SDValue R = DistrubuteAddAddVecReduce ( N1 , N0 ) ) return R ; auto DistrubuteVecReduceLoad = [ & ] ( SDValue N0 , SDValue N1 , bool IsForward ) { auto IsKnownOrderedLoad = [ & ] ( SDValue N0 , SDValue N1 ) { if ( N0 . getOpcode ( ) == <STR_LIT> ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) N1 = N1 . getOperand ( <NUM_LIT> ) ; LoadSDNode * Load0 = dyn_cast < LoadSDNode > ( N0 ) ; LoadSDNode * Load1 = dyn_cast < LoadSDNode > ( N1 ) ; if ( ! Load0 || ! Load1 || Load0 -> getChain ( ) != Load1 -> getChain ( ) || ! Load0 -> isSimple ( ) || ! Load1 -> isSimple ( ) || Load0 -> isIndexed ( ) || Load1 -> isIndexed ( ) ) return <NUM_LIT> ; auto BaseLocDecomp0 = BaseIndexOffset :: match ( Load0 , DAG ) ; auto BaseLocDecomp1 = BaseIndexOffset :: match ( Load1


<s> if ( mode == VOIDmode ) { gcc_assert ( operand . predicate == aarch64_any_register_operand ) ; mode = GET_MODE ( x ) ; } else if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) && VECTOR_MODE_P (

mode ) ) x = expand_vector_broadcast ( mode , x ) ;


<s> SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; EVT N10VT = N10 . getValueType ( ) ; if ( N00 -> getOpcode ( ) == <STR_LIT> && N01 -> getOpcode ( ) == <STR_LIT> && N10 -> getOpcode ( ) == <STR_LIT> && N11 -> getOpcode ( ) == <STR_LIT> && N00VT == N10VT ) { SDValue N00Source = N00 -> getOperand ( <NUM_LIT> ) ; SDValue N01Source = N01 -> getOperand ( <NUM_LIT> ) ; SDValue N10Source = N10 -> getOperand ( <NUM_LIT> ) ; SDValue N11Source = N11 -> getOperand ( <NUM_LIT> ) ; if ( N00Source == N10Source && N01Source == N11Source && N00Source . getValueType ( ) == VT && N01Source . getValueType ( ) == VT ) { assert ( N0 . getValueType ( ) == N1 . getValueType ( ) ) ; uint64_t N00Index = N00 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N01Index = N01 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N10Index = N10 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N11Index = N11 . getConstantOperandVal ( <NUM_LIT> ) ; if ( N00Index == N01Index && N10Index == N11Index && N00Index == <NUM_LIT> && N10Index == N00VT . getVectorNumElements ( ) ) return DAG . getNode ( N0Opc , dl , VT , N00Source , N01Source ) ; } } } if ( N -> getNumOperands ( ) == <NUM_LIT> && N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N -> getNumOperands ( ) != <NUM_LIT> || N1Opc


<s> static <ISA_LIT>MCExpr :: VariantKind PermittedModifiers [ ] = { <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0 , <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 , <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0 , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G0 , } ; unsigned NumModifiers = llvm :: array_lengthof ( PermittedModifiers ) ; return isMoveWideImm ( <NUM_LIT> ,


<s> return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> MVT SVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT

== <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ;


<s> if ( DataVT . isFloatingPoint ( ) ) Data = DAG . getNode ( <STR_LIT> , DL , DataVT . changeTypeToInteger ( ) , Data ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Data } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; } else { printOp ( MI -> getOperand ( OpNo ) , O


<s> FunctionPass * llvm :: create<ISA_LIT>SLSHardeningPass


<s> SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N1 ) ; SDValue N3 = DAG . getNode ( <STR_LIT> , DL , VT8Bit ,


<s> return lowerV2F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT>


<s> Parser . eatToEndOfStatement ( ) ; Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; if ( RegisterReqs . insert ( std :: make_pair ( Name , Reg ) )


<s> if ( Subtarget -> is64Bit ( ) ) return LowerCall_64 ( CLI , InVals ) ; return LowerCall_32 ( CLI


<s> int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset


<s> for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) { rtx tmp ; if ( GET_CODE ( insn ) != INSN && GET_CODE ( insn ) != JUMP_INSN ) continue ; tmp = PATTERN ( insn ) ; if ( GET_CODE ( tmp ) != SET ) continue ; tmp = SET_DEST ( tmp ) ; if ( GET_CODE ( tmp ) == REG && REGNO ( tmp ) == <NUM_LIT> ) { fcmp_count ++ ; continue ; } tmp = PATTERN ( insn ) ; if ( GET_CODE ( tmp ) == SET && SET_DEST ( tmp ) == pc_rtx && GET_CODE ( SET_SRC ( tmp ) ) == IF_THEN_ELSE && GET_CODE ( XEXP ( SET_SRC ( tmp ) , <NUM_LIT> ) ) == NE && GET_CODE ( XEXP ( XEXP ( SET_SRC ( tmp ) , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( XEXP ( SET_SRC ( tmp ) , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> ) { fbranch_count ++ ; continue ; } } for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) { rtx tmp , next ; if ( GET_CODE ( insn ) != INSN ) continue ; tmp = PATTERN ( insn )


<s> uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; EVT VecVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; return Index /


<s> static unsigned computeBytesPoppedByCalleeForSRet ( const <ISA_LIT>Subtarget * Subtarget , CallingConv :: ID CC , ImmutableCallSite * CS ) { if ( Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT (


<s> case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case NeoverseN2 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case Neoverse512TVB : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ThunderX3T110 : CacheLineSize =


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ( ! isThumb (


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( )

, CCInfo . getNextStackOffset ( ) , std :: max ( <NUM_LIT> , TotalArgRegsSaveSize ) ) ;


<s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0


<s> std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; std :: string SymName = <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) + <STR_LIT> + utostr ( Reg ) ; Sym = OutContext . getOrCreateSymbol ( SymName ) ; } EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create (


<s> static DecodeStatus DecodeDPR_VFP2RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; StackOffset Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + StackOffset :: getFixed ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( ! isInt < <NUM_LIT> > ( Offset . getFixed ( ) ) ) { report_fatal_error (


<s> if ( ! Subtarget . hasAVX ( ) || ( Factor != <NUM_LIT> && Factor != <NUM_LIT> ) ) return false ; if ( isa < LoadInst > ( Inst ) ) { WideInstSize = DL . getTypeSizeInBits ( Inst -> getType ( ) ) ; if ( cast < LoadInst > ( Inst ) -> getPointerAddressSpace ( ) ) return false ; } else WideInstSize = DL . getTypeSizeInBits ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( ShuffleElemSize == <NUM_LIT> && WideInstSize == <NUM_LIT> && Factor == <NUM_LIT> ) return true ; if ( ShuffleElemSize == <NUM_LIT> && isa < StoreInst > ( Inst ) && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ; if ( ShuffleElemSize == <NUM_LIT> && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ; return


<s> static void mips_file_end ( void ) { tree name_tree ; struct extern_list * p ; if ( extern_head ) { fputs ( <STR_LIT> , asm_out_file ) ; for ( p = extern_head ; p != <NUM_LIT> ; p = p -> next ) { name_tree = get_identifier ( p -> name ) ; if ( ! TREE_ASM_WRITTEN ( name_tree ) && TREE_SYMBOL_REFERENCED ( name_tree ) ) { TREE_ASM_WRITTEN ( name_tree ) = <NUM_LIT> ; if ( TARGET_IRIX && mips_abi == ABI_32 && p -> size == - <NUM_LIT> ) { fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , p


<s> MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer . SwitchSection ( Current ) ; MCSymbol * RealFnSym = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( RealFnSym ) ; CurrentFnSymForSize =


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } Regs . clear (


<s> return ( long long ) __builtin_ia32_vcvtsh2si64_round


<s> if ( TARGET_LONG_DOUBLE_128 ) { if ( ! TARGET_IEEEQUAD ) init_float128_ibm (


<s> if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = <NUM_LIT> ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + <NUM_LIT> ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = emit_frame_insn ( x ) ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * <NUM_LIT> ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - <NUM_LIT> ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( *


<s> Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString =


<s> static bool ia64_cannot_force_const_mem ( rtx x ) { return tls_symbolic_operand_type ( x ) !=


<s> bool hasSymbolicDisplacement ( ) const { return GV != nullptr || CP != nullptr || ES != nullptr || MCSym != nullptr || JT

!= - <NUM_LIT> || BlockAddr != nullptr ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && RegNum < <NUM_LIT> ) ; Binary |= <NUM_LIT> << RegNum ; } emitWordLE ( Binary


<s> } if ( get<ISA_LIT>Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true


<s> mips_va_arg ( valist , type ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ fprintf ( FILE , \ <STR_LIT> , \ TARGET_64BIT ? <STR_LIT> : <STR_LIT> , \ reg_names [ STACK_POINTER_REGNUM ] , \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; \

fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> if ( ! MI . isBranch ( ) ) { Info . CondBrs . clear ( ) ; break ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { Info . CondBrs . clear ( ) ; Info . UncondBr = & MI ; continue ; } if ( <STR_LIT> ( MI . getOpcode ( ) ) == <STR_LIT> ) { Info . CondBrs . clear ( ) ; Info . UncondBr = & MI ; continue ; } Info . CondBrs . push_back ( & MI ) ; } if ( Info . CondBrs . empty ( ) ) { ++ NumBranchesUntraced ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MBB . dump ( ) ) ; continue ; } Infos . push_back ( Info ) ; } return Infos


<s> int Size = Mask . size ( ) ; assert ( Size == ( int ) VT . getVectorNumElements ( ) && <STR_LIT> ) ; MVT ShiftVT ; SDValue V = V1 ; unsigned Opcode ; int ShiftAmt = matchShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , <NUM_LIT> , Zeroable , Subtarget ) ; if ( ShiftAmt < <NUM_LIT> ) { ShiftAmt = matchShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , Size , Zeroable , Subtarget ) ; V = V2 ; } if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( ShiftVT ) && <STR_LIT> ) ; V = DAG . getBitcast ( ShiftVT , V ) ; V = DAG . getNode ( Opcode , DL , ShiftVT , V

, DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ;


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [


<s> if ( isDead ( MI , DeadPhis ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextI ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { nextI = llvm :: next ( I ) ; MachineOperand & Use = I . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( UseMI == MI ) continue ; if ( Use . isDebug ( ) ) UseMI -> getOperand ( <NUM_LIT> ) . setReg ( <NUM_LIT> ) ; } } MI -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> ; i < DeadPhis . size ( ) ; ++ i ) { DeadPhis [ i ] -> eraseFromParent (


<s> struct cgraph_node * node ; function * fn ; FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL ) fn -> machine -> does_not_use_frame_header = ! needs_frame_header_p ( fn ) ; } FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL ) fn -> machine -> optimize_call_stack = ! callees_functions_use_frame_header ( fn ) && ! is_leaf_function ( fn ) ; } FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node ->


<s> if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case E_V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target , t3 , t2 ) ) ; break ; default : gcc_unreachable (


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { if ( OSType == Triple :: OSType :: UnknownOS


<s> else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createPICLabelUId ( ) ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = std :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = std :: prev ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . addOperand ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( std :: prev ( MachineFunction :: iterator ( NewIsland ) ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i


<s> bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e -> src == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( bb ) , & found ) ; else { int shortest_dist = - <NUM_LIT> ; bool found_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { int bb_dist = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( e -> src ) , & found_in_bb ) ; if ( found_in_bb ) { if ( shortest_dist < <NUM_LIT> ) shortest_dist = bb_dist ; else if ( bb_dist > <NUM_LIT> ) shortest_dist = MIN ( bb_dist , shortest_dist ) ; found = true ; } } distance = shortest_dist ; } } if ( ! found ) return


<s> const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static unsigned getRRMOpcodeVariant ( unsigned Opcode ) { switch ( Opcode ) { default : llvm_unreachable (


<s> return isShlFixedWidth ( <NUM_LIT> )


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool

MemcpyStrSrc , MachineFunction & MF ) const {


<s> bool isNotSingleFloat ( ) const { return !


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) || GVar -> hasDLLImportLinkage ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V


<s> bool <ISA_LIT>AsmParser :: parseSetPushDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( AssemblerOptions . back (


<s> case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , SelectionDAG & DAG ) const { if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } else { return <STR_LIT>


<s> unsigned int ccvt ; if ( TARGET_64BIT ) return ( ix86_function_type_abi ( type ) == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; ccvt = ix86_get_callcvt ( type ) ; regparm = ix86_regparm ; if ( ( ccvt & IX86_CALLCVT_REGPARM ) != <NUM_LIT> ) { attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return regparm ; } } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) return <NUM_LIT> ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) return <NUM_LIT> ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { int local_regparm , globals = <NUM_LIT> , regno ; for ( local_regparm = <NUM_LIT> ; local_regparm <


<s> auto InsertPt = MI . getIterator ( ) ; if ( FenceCallAndRet ) return ; mergePredStateIntoSP ( MBB , InsertPt , Loc , PS -> SSA .


<s> const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx / Scale ; if ( ( V0Opc != <STR_LIT> || V0BroadcastIdx != <NUM_LIT> ) && V0Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Scalar = V0 . getOperand ( V0BroadcastIdx ) ; if ( const int OffsetIdx = BroadcastIdx % Scale ) Scalar = DAG . getNode ( <STR_LIT> , DL , Scalar . getValueType ( ) , Scalar , DAG . getConstant ( OffsetIdx


<s> static DecodeStatus DecodeBitfieldMaskOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned msb = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned lsb = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( lsb > msb ) Check ( S , MCDisassembler :: SoftFail ) ; uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << ( msb + <NUM_LIT> ) ) - <NUM_LIT> ; uint32_t lsb_mask = ( <NUM_LIT> << lsb ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( ~ ( msb_mask ^ lsb_mask ) ) ) ; return S


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { Align Alignment = DL . getPrefTypeAlign ( GV -> getType ( ) ) ; if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Alignment ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( IsPositionIndependent ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( IsPositionIndependent


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * EVal ; switch ( getLexer ( ) . getKind (


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & ) const { return


<s> ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( end_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = reg2 ; strcpy ( tmp , <STR_LIT> ) ; output_asm_insn ( strcat ( tmp , & end_lab [ <NUM_LIT> ] ) , xops ) ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; if ( TARGET_64BIT && TARGET_LONG64 ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , end_lab


<s> MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . ToRemove . insert ( LoLoop . Dec ) ; LoLoop . ToRemove . insert ( End ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemNoOffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addPostIdxImm8Operands ( Inst , <NUM_LIT> ) ;


<s> if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; unsigned int nunits = GET_MODE_NUNITS ( vmode ) . to_constant ( ) ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , nunits , exp ) ; op [ opc ] = aarch64_endian_lane_rtx ( vmode , INTVAL ( op [ opc ] ) ) ; } case SIMD_ARG_CONSTANT : constant_arg : if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) { error ( <STR_LIT> , exp , opc + <NUM_LIT> - have_retval ) ; return const0_rtx ; } break ; case SIMD_ARG_STOP : gcc_unreachable ( ) ; } opc ++ ; } } switch ( opc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ]


<s> return ( __m128i ) __builtin_ia32_vcvttph2udq128_mask ( __C , (


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , Alignment , AddressSpace ) ; Cost += Factor * ( LT . first - <NUM_LIT> ) ; return Cost


<s> unsigned int call_properties ( const function_instance & )


<s> static __inline__ void sh_media_PREFO ( void * mm , int s


<s> int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( BitExtMI ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> rtx x = expand_vec_perm_const ( vmode , op0 , op1


<s> } else if ( MCSymbolSDNode * M = dyn_cast < MCSymbolSDNode > ( Callee ) ) { const auto * S = cast < MCSymbolXCOFF > ( M -> getMCSymbol ( ) ) ; GV = S -> getGlobalValue ( ) ; } if ( ! GV ) return false ; if ( CodeModel :: Medium == TM . getCodeModel ( ) || CodeModel :: Large == TM . getCodeModel ( ) ) return TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , GV ) ; if ( ! GV -> isStrongDefinitionForLinker ( ) ) return false ; if ( TM . getFunctionSections ( ) || GV -> hasComdat ( ) || Caller -> hasComdat ( ) || GV -> getSection ( ) != Caller -> getSection


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_illegal ( void * const TM_buff ) { texasru_t texasru = * _TEXASRU_PTR


<s> SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Glue = End . getValue ( <NUM_LIT> ) ; SDValue Ops [ ] = { End , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Glue } ; VTs = DAG . getVTList ( PtrVT


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; Value * Ptr = Constant :: getNullValue ( Type :: getInt8PtrTy ( * DAG . getContext ( ) , is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getIntPtrConstant ( <NUM_LIT> ) , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; unsigned char OperandFlags = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( model == TLSModel :: InitialExec ) { if ( is64Bit ) { OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { OperandFlags = isPIC ? <STR_LIT> : <STR_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) { if ( isPIC && ! is64Bit ) { Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , Offset ) ; } Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Offset

, MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> tmp = gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ; if ( reload_completed && ( ! TARGET_USE_MOV0 || optimize_size ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , <NUM_LIT> ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> ,


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , getContext


<s> if ( is_end ) emit_jump_insn ( gen_doloop_end_internal ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , tag ) ) ; else emit_insn ( gen_doloop_begin_internal ( operands [ <NUM_LIT> ] , operands [


<s> return ( __m256h ) __builtin_ia32_movaps256_mask ( ( __v8sf ) _mm256_conj_pch ( __A ) , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 )


<s> __inline__ static int sh_media_FMOV_SL ( float fg ) { int res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( fg ) ) ; return res


<s> MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; return NewMI ; } } if ( ! MI . isConvertibleTo3Addr ( ) ) return nullptr ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MVT ByteVecVT = <STR_LIT> ( <STR_LIT> , NumByteElts ) ; SDValue In = DAG . getBitcast ( ByteVecVT , Op ) ; SmallVector < SDValue , <NUM_LIT> > LUTVec ; for ( int i = <NUM_LIT> ; i < NumByteElts ; ++ i ) LUTVec . push_back ( DAG . getConstant ( LUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; SDValue InRegLUT = DAG . getBuildVector ( ByteVecVT , DL , LUTVec ) ; SDValue M0F = DAG . getConstant ( <NUM_LIT> , DL , ByteVecVT ) ; SDValue FourV = DAG . getConstant (


<s> if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; else if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; else return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; } return


<s> const char * getClearCacheBuiltinName ( ) const { return <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue


<s> case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return


<s> unsigned NumElems = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt (


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = <NUM_LIT> ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype


<s> return ( __m256i ) __builtin_ia32_cvttpd2dq512_mask ( ( __v8df ) __A , ( __v8si )


<s> std :: for_each ( MBB . rbegin ( ) , MBB . rend ( ) , [ & LRU ] ( MachineInstr & MI ) { LRU . accumulate ( MI ) ; } ) ; if ( ! LRU . available ( <STR_LIT> ) ) Flags |= MachineOutlinerMBBFlags ::


<s> int CCOpNum = Compare . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> CC = cast < CondCodeSDNode > ( Compare . getOperand ( CCOpNum ) ) -> get ( ) ; EVT InputVT = LHS . getValueType ( ) ; if ( InputVT != <STR_LIT> && InputVT != <STR_LIT> ) return SDValue ( ) ; if ( ConvOpts == SetccInGPROpts :: ZExtInvert || ConvOpts == SetccInGPROpts :: SExtInvert ) CC = <STR_LIT> ( CC , true ) ; bool Inputs32Bit = InputVT == <STR_LIT> ; if ( <STR_LIT> ( CC ) && Inputs32Bit ) { LHS = signExtendInputIfNeeded ( LHS ) ; RHS = signExtendInputIfNeeded ( RHS ) ; } else if ( <STR_LIT> ( CC ) && Inputs32Bit ) { LHS = zeroExtendInputIfNeeded ( LHS ) ; RHS = zeroExtendInputIfNeeded ( RHS ) ; } SDLoc dl ( Compare ) ; ConstantSDNode * RHSConst = dyn_cast < ConstantSDNode > ( RHS ) ; int64_t RHSValue = RHSConst ? RHSConst -> getSExtValue ( ) : INT64_MAX ; bool IsSext = ConvOpts == SetccInGPROpts :: SExtOrig || ConvOpts == SetccInGPROpts :: SExtInvert ; if ( IsSext && Inputs32Bit ) return get32BitSExtCompare ( LHS , RHS , CC , RHSValue , dl ) ; else if ( Inputs32Bit ) return get32BitZExtCompare ( LHS , RHS , CC


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFPOPushReg ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; unsigned


<s> SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT>

? <STR_LIT> : <STR_LIT> ) , DL , VT , RetVal ) ;


<s> if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( can_create_pseudo_p ( ) ) ) ) { base = loongarch_force_temporary ( dest , base ) ; loongarch_emit_move ( dest , loongarch_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; loongarch_emit_move ( dest


<s> bool isVecListTwoQAllLanes ( ) const { if ( ! isDoubleSpacedVectorAllLanes ( )


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetGINV ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetGINV (


<s> bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( <STR_LIT> ) ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI . CreateFixedObject ( - <NUM_LIT> * TCSPDelta


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S4 ( SDValue N , SDValue & Base ,


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u64 ( unsigned


<s> if ( getParser ( ) . parseAbsoluteExpression ( Off ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) .


<s> Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; T = <NUM_LIT> ; } } Relocator :: DWord X = ( S + A ) | T ; pReloc . target ( ) = helper_insert_val_movw_movt_inst ( pReloc . target ( ) + pReloc . addend ( )


<s> -- I ; } if ( I -> getOpcode ( ) != <STR_LIT> && ! isCondBranch ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; --


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger (


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ <NUM_LIT> ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { assert ( false && <STR_LIT> ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( RVLocs . size ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , & RetOps


<s> if ( auto Const = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Const -> getZExtValue ( ) == <NUM_LIT> ; return false


<s> cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getTargetConstant ( x86cc , DL , <STR_LIT> ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Ins ) , DL , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getTargetConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , IntVT , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ) ; SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ANDed ) ; return OneBitOfTruth ; } } } } return SDValue (


<s> Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo (


<s> const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( (

ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ;


<s> case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT>


<s> static SDValue GENLowerMUL ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT FullVT = getFullRegisterType ( VT ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp1 = b . SHL < <NUM_LIT> > ( A1 ) ; SDValue Tmp2 = b . SHL < <NUM_LIT> > ( A2 ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . OR ( b . AND ( Tmp1 , b . AND ( A2 , b . OR ( b . NOT ( A1 ) , b . NOT ( Tmp2 ) ) ) ) , b . AND ( A1 , b . AND ( Tmp2 , b . OR ( b . NOT ( Tmp1 ) , b . NOT ( A2 ) ) ) ) ) , b . AND ( A1 , A2 ) ) ; } llvm_unreachable ( <STR_LIT> ) ; return SDValue


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering . getPointerTy ( ) == <STR_LIT> ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthVectorIntExtendToSVE ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , Val . getValueType ( ) ) ; Val = convertToScalableVector ( DAG , ContainerVT , Val ) ; bool Signed = Op . getOpcode ( ) == <STR_LIT> ; unsigned ExtendOpc = Signed ? <STR_LIT> : <STR_LIT> ; switch ( ContainerVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( Mask [ i ] == SM_SentinelUndef ) continue ; if ( Mask [ i ] == SM_SentinelZero ) { if ( ! isUndefOrZero ( RepeatedMask [ i % LaneSize ] ) ) return false ; RepeatedMask [ i % LaneSize ] = SM_SentinelZero ; continue ; } if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; int LocalM = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] %


<s> bool hasFPUv3HalfWord ( ) const { return HasFPUv3HalfWord


<s> HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasVPCLMULQDQ = false ; HasGFNI = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasVBMI2 = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasVNNI = false ; HasBITALG = false ; HasSHA = false ; HasPREFETCHWT1 = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSHSTK = false ; HasIBT = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; HasWBNOINVD = false ; HasRDPID = false ; UseRetpoline = false ; UseRetpolineExternalThunk = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasPOPCNTFalseDeps = false ; HasLZCNTFalseDeps = false ; HasFastVariableShuffle = false ; HasFastPartialYMMorZMMWrite = false ; HasFast11ByteNOP = false ; HasFast15ByteNOP = false ; HasFastGather = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasMacroFusion = false ; HasERMSB = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; SlowTwoMemOps = false ; LEAUsesAG = false ; SlowLEA = false ; Slow3OpsLEA = false ; SlowIncDec =


<s> if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { int slot , credit ; bool jump_to_next = false ; rtx_insn * prev = prev_real_insn ( prev_active_insn ( barrier_or_label ) ) ; for ( slot = <NUM_LIT> , credit = ( <NUM_LIT> << ( CACHE_LOG - <NUM_LIT> ) ) + <NUM_LIT> ; credit >= <NUM_LIT> && prev && NONJUMP_INSN_P ( prev ) ; prev = prev_real_insn ( prev ) ) { jump_to_next = false ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( rtx_sequence * prev_seq = dyn_cast < rtx_sequence * > ( PATTERN ( prev ) ) ) { prev = prev_seq -> insn ( <NUM_LIT> ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next = true ; continue ; } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = <NUM_LIT> ; credit -= get_attr_length ( prev ) ; } if ( prev && jump_to_label_p ( prev ) ) { rtx_insn * x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN


<s> return DecodeMem ( Inst , insn , Address , Decoder

, false , DecodeQFPRegsRegisterClass ) ;


<s> break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : if ( ConstantSDNode * Op2 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Value = - Op2 -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || isInt < <NUM_LIT> > ( Value ) ) { SDValue Ops [ ] = { Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( int32_t ( Value ) , VT ) } ; Node = CurDAG -> MorphNodeTo ( Node , <STR_LIT> , Node -> getVTList ( ) , Ops , array_lengthof ( Ops ) ) ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; } break ; } } if ( ! ResNode ) ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ; if ( ResNode == NULL || ResNode == Node ) Node -> dump ( CurDAG ) ; else ResNode -> dump ( CurDAG ) ; errs ( )


<s> void <ISA_LIT>MCInstLower :: Initialize ( MCContext * C


<s> Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) return DAG . getMergeValues (


<s> void printDstIdx8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis ( const


<s> if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM ? PRFM -> Name : <STR_LIT> , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> if ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! RegInfo -> canRealignStack ( MF ) ) return ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! MRI . isPhysRegUsed ( <STR_LIT>


<s> RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && LD -> getOffset ( ) . getOpcode ( ) != <STR_LIT> ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD -> getAlignment ( ) ; RLI . AAInfo = LD -> getAAInfo ( ) ; RLI . Ranges = LD ->


<s> void InsertMul ( Instruction * I , ValueList & LHS ,


<s> if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI .

getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {


<s> <ISA_LIT>Operand * Mnemonic = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; if ( Mnemonic -> getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const AsmToken & Tok2 = Parser . getTok ( ) ; if ( Tok2 . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( IdVal == <NUM_LIT> ) IdVal = MCConstantExpr ::


<s> int FirstLoadedElt = LoadMask . find_first ( ) ; SDValue EltBase = peekThroughBitcasts ( Elts [ FirstLoadedElt ] ) ; LoadSDNode * LDBase = cast < LoadSDNode > ( EltBase ) ; EVT LDBaseVT = EltBase . getValueType ( ) ; bool IsConsecutiveLoad = true ; bool IsConsecutiveLoadWithZeros = true ; for ( int i = FirstLoadedElt + <NUM_LIT> ; i <= LastLoadedElt ; ++ i ) { if ( LoadMask [ i ] ) { SDValue Elt = peekThroughBitcasts ( Elts [ i ] ) ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . areNonVolatileConsecutiveLoads ( LD , LDBase , Elt . getValueType ( ) . getStoreSizeInBits ( ) / <NUM_LIT> , i - FirstLoadedElt ) ) { IsConsecutiveLoad = false ; IsConsecutiveLoadWithZeros = false ; break ; } } else if ( ZeroMask [ i ] ) { IsConsecutiveLoad = false ; } } auto CreateLoad = [ & DAG , & DL ] ( EVT VT , LoadSDNode * LDBase ) { SDValue NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , false , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd ; } ; if ( FirstLoadedElt == <NUM_LIT> && LastLoadedElt == ( int ) ( NumElems - <NUM_LIT> ) && ( IsConsecutiveLoad || IsConsecutiveLoadWithZeros ) ) { assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != EltVT . getSizeInBits ( ) * NumElems ) return SDValue ( ) ; if ( isAfterLegalize && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; if ( IsConsecutiveLoad ) return CreateLoad ( VT , LDBase ) ; if ( ! isAfterLegalize && NumElems == VT . getVectorNumElements ( )


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return &


<s> __builtin_ia32_aand64 ( ( long long *


<s> bool isImm0_15 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( )


<s> static unsigned int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : if ( aarch64_sve_data_mode_p ( mode ) ) return exact_div ( GET_MODE_SIZE ( mode ) , BYTES_PER_SVE_VECTOR ) . to_constant ( ) ; return CEIL ( lowest_size , UNITS_PER_VREG ) ; case PR_REGS : case PR_LO_REGS : case PR_HI_REGS


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperands ( const <ISA_LIT>RRIAddressMode & AM , SDValue & Base , SDValue & Disp , SDValue & Index ) { getAddressOperandsRI ( AM , Base , Disp ) ; Index = AM .


<s> void addPostRegAlloc ( ) override { if ( get<ISA_LIT>Subtarget ( ) . isCheri ( ) ) addPass


<s> NewMBB -> splice ( NewMBB -> begin ( ) , MBB , MI , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; return NewMBB


<s> } if ( IsAllOf && Subtarget . hasSSE41 ( ) ) { SDValue BC = peekThroughBitcasts ( Vec ) ; if ( BC . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( BC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { MVT TestVT = VecVT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue V = DAG . getBitcast ( TestVT , BC . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , <STR_LIT> , V , V ) ; } } if ( Vec . getOpcode ( ) == <STR_LIT> && VecVT == <STR_LIT> ) { SDValue VecOp0 = Vec . getOperand ( <NUM_LIT> ) ; SDValue VecOp1 = Vec . getOperand ( <NUM_LIT> ) ; bool SignExt0 = DAG . ComputeNumSignBits ( VecOp0 ) > <NUM_LIT> ; bool SignExt1 = DAG . ComputeNumSignBits ( VecOp1 ) > <NUM_LIT> ; if ( IsAnyOf && CmpBits == <NUM_LIT> && VecOp1 . isUndef ( ) ) { SDLoc DL ( EFLAGS ) ; SDValue Result = DAG . getBitcast ( <STR_LIT> , VecOp0 ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result ) ; Result = DAG . getZExtOrTrunc ( Result , DL , <STR_LIT> ) ; if ( ! SignExt0 ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( CmpBits >= <NUM_LIT> && Subtarget . hasInt256 ( ) && VecOp0 . getOpcode ( ) == <STR_LIT> && VecOp1 . getOpcode ( ) == <STR_LIT> && VecOp0 . getOperand ( <NUM_LIT> ) == VecOp1 . getOperand ( <NUM_LIT> ) && VecOp0 . getConstantOperandAPInt ( <NUM_LIT> ) == <NUM_LIT> && VecOp1 . getConstantOperandAPInt ( <NUM_LIT> ) == <NUM_LIT> && ( IsAnyOf || ( SignExt0 && SignExt1 ) ) ) { SDLoc DL ( EFLAGS ) ; SDValue Result = DAG . getBitcast ( <STR_LIT> , VecOp0 . getOperand ( <NUM_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL