<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg ; if ( Subtarget -> isTargetNaCl ( ) ) { FrameReg = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; } else { FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; } assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg


<s> if ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) > <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT>


<s> static bool rs6000_debug_mode_dependent_address ( const_rtx addr ) { bool ret = rs6000_mode_dependent_address


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> void <ISA_LIT>TTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . getDarwinDirective ( ) == <STR_LIT> ) { UP . Partial = UP


<s> static DecodeStatus DecodeMSA128HRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX


<s> SMLoc DummyLoc ; if ( ParseRegister ( Reg , DummyLoc , DummyLoc ) || Parser . parseEOL ( <STR_LIT> ) ) return addErrorSuffix ( <STR_LIT> ) ; return getTargetStreamer ( ) . emitFPOPushReg (


<s> <STR_LIT> <STR_LIT> ( unsigned Opc ) { switch ( Opc ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; return OptLevel >=


<s> if ( auto ShiftedImm = getShiftedVal < <NUM_LIT> > ( ) ) if ( ! ( IsByte && ShiftedImm -> second ) && <STR_LIT> < T > ( uint64_t ( ShiftedImm -> first ) << ShiftedImm -> second ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy


<s> * NewMBB = next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; BuildMI ( UserMBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( * NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator


<s> SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , Align ( <NUM_LIT> ) ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset ,


<s> if ( TARGET_ARCH64 ) { if ( SPARC_INT_REG_P ( regno ) || regno == FRAME_POINTER_REGNUM ) return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode


<s> unsigned Opc = N -> getOpcode ( ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; if ( Src2 . getOpcode ( ) == <STR_LIT> ) Src2 = SDValue ( SelectIndexedLoad ( Src2 . getNode ( ) ) , <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , Src1 , Src2 ) ; else if ( Opc == <STR_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , Src1 , Src2 ) ; else if ( Opc == <STR_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , Src1 , Src2 ) ; else return SelectCode ( N


<s> Name = ( Name [ <NUM_LIT> ] == 'r' ) ? Name . drop_front ( <NUM_LIT> ) : Name . drop_front ( ) ; switch ( Name . size ( ) ) { default : return - <NUM_LIT> ; case <NUM_LIT> : switch ( Name [ <NUM_LIT> ] ) { default : return - <NUM_LIT> ; case '0' : return <NUM_LIT> ; case '1' : return <NUM_LIT> ; case '2' : return <NUM_LIT> ; case '3' : return <NUM_LIT> ; case '4' : return <NUM_LIT> ; case '5' : return <NUM_LIT> ; case '6' : return <NUM_LIT> ; case '7' : return <NUM_LIT> ; case '8' : return <NUM_LIT> ; case '9' : return <NUM_LIT> ; } case <NUM_LIT> : if ( Name [ <NUM_LIT> ] != '1' ) return - <NUM_LIT> ; switch ( Name [ <NUM_LIT>


<s> bool NonRI = false , SpillsVRS = false ; if ( LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI


<s> break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_TRUNC : case TargetOpcode :: G_ANYEXT : { auto & Op0 = MI . getOperand ( <NUM_LIT> ) ; auto & Op1 = MI . getOperand ( <NUM_LIT> ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool isFPTrunc = ( Ty0 . getSizeInBits ( ) == <NUM_LIT> || Ty0 . getSizeInBits ( ) == <NUM_LIT> ) && Ty1 . getSizeInBits ( ) == <NUM_LIT> && Opc == TargetOpcode :: G_TRUNC ; bool isFPAnyExt = Ty0 . getSizeInBits ( ) == <NUM_LIT> && ( Ty1 . getSizeInBits ( ) == <NUM_LIT> || Ty1 . getSizeInBits ( ) == <NUM_LIT> ) && Opc == TargetOpcode :: G_ANYEXT ; getInstrPartialMappingIdxs ( MI , MRI , isFPTrunc || isFPAnyExt , OpRegBankIdx ) ; } break ; default : getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; break ; } SmallVector < const ValueMapping * , <NUM_LIT> > OpdsMapping (


<s> case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , false , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , true , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , false , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , false , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , true , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , false , MI , BB ) ; break ; case <STR_LIT> : return emitFEXT_CCRX16_ins ( <STR_LIT> , MI , BB ) ; break ; case <STR_LIT> : return emitFEXT_CCRXI16_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_CCRXI16_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT>


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false


<s> if ( SDValue Res = tryLowerToSLI ( Op . getNode ( ) , DAG ) ) return Res ; EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! BVN ) { LHS = Op . getOperand ( <NUM_LIT> ) ; BVN = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } if ( ! BVN ) return Op ; APInt DefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt UndefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( resolveBuildVector ( BVN , DefBits , UndefBits ) ) { SDValue NewOp


<s> static DecodeStatus DecodeVLD2DupInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = <NUM_LIT> << fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; align *= <NUM_LIT> * size ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateReg (


<s> const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( RC -> hasType ( <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MemOpndSlot = CurOp ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MF -> push_back ( restoreMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = getTargetMachine ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else


<s> static void getIntOperandsFromRegisterString ( StringRef RegString , SelectionDAG * CurDAG , const SDLoc & DL , std :: vector < SDValue > & Ops ) { SmallVector < StringRef , <NUM_LIT> > Fields ; RegString . split ( Fields ,


<s> StringRef getPassName ( ) const override { return


<s> for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents

[ i ] . Tag == Attribute ) return & Contents [ i ] ;


<s> return ( __m256i ) __builtin_ia32_pmovzxdq256_mask ( ( __v4si ) __X , ( __v4di ) __W , (


<s> static const MCPhysReg FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; if ( useSoftFloat ( ) ) NumFPArgRegs = <NUM_LIT> ; FuncInfo -> setVarArgsNumGPR ( CCInfo . getFirstUnallocated ( GPArgRegs ) ) ; FuncInfo -> setVarArgsNumFPR ( CCInfo . getFirstUnallocated ( FPArgRegs ) ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; FuncInfo -> setVarArgsStackOffset ( MFI -> CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateStackObject ( Depth , <NUM_LIT> , false ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; for ( unsigned GPRIndex = <NUM_LIT> ; GPRIndex != NumGPArgRegs ; ++ GPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( GPArgRegs [ GPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( GPArgRegs [ GPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , PtrVT ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) , FIN , PtrOff ) ; } for ( unsigned FPRIndex = <NUM_LIT> ; FPRIndex != NumFPArgRegs ; ++ FPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( FPArgRegs [ FPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( FPArgRegs [ FPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store


<s> if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) if ( Const -> isNegative ( ) ) return false ; if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) if ( Const -> isNegative ( ) ) return false ; bool NegImm = cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) -> isNegative ( ) ; bool IsDecreasing = ( ( Opc == Instruction :: Sub ) && ! NegImm ) || ( ( Opc == Instruction :: Add ) && NegImm ) ; if ( ! IsDecreasing


<s> if ( isa < SExtInst > ( Inst ) ) return true ; const BinaryOperator * BinOp = dyn_cast < BinaryOperator > ( Inst ) ; if ( BinOp && isa < OverflowingBinaryOperator > ( BinOp ) && ( BinOp -> hasNoUnsignedWrap ( ) || BinOp -> hasNoSignedWrap ( ) ) ) return true ; if ( isa < TruncInst > ( Inst ) && isa < SExtInst > ( Inst -> getOperand ( <NUM_LIT> ) ) ) { const Instruction * Opnd = cast < Instruction > (


<s> if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT>


<s> SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue VAList = DAG . getLoad ( <STR_LIT> , dl , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG . getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , dl , NextPtr , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . getLoad ( VT , dl , InChain , VAList , MachinePointerInfo ( )


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OS . write (


<s> int <ISA_LIT>ConstantPoolSymbol :: getExistingMachineCPValue ( MachineConstantPool * CP , unsigned Alignment ) { unsigned AlignMask = Alignment - <NUM_LIT> ; const std :: vector < MachineConstantPoolEntry > Constants = CP -> getConstants ( ) ; for ( unsigned i = <NUM_LIT> , e = Constants . size ( ) ; i != e ; ++ i ) { if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && ( Constants [ i ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * CPV = ( <ISA_LIT>ConstantPoolValue * ) Constants [ i ] . Val . MachineCPVal ; <ISA_LIT>ConstantPoolSymbol * APS = dyn_cast < <ISA_LIT>ConstantPoolSymbol > ( CPV


<s> MachineBasicBlock * <ISA_LIT>ConstantIslands :: splitBlockBeforeInstr ( MachineInstr & MI ) { MachineBasicBlock * OrigBB = MI . getParent ( ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) ,

WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSIReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSIReg ? <STR_LIT> : <STR_LIT>


<s> if ( ! TmpReg ) return true ; } emitRRI ( <STR_LIT> , TmpReg , ZeroReg , ImmValue , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( ABI . GetPtrAdduOp ( ) , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } if ( isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ) { warnIfNoMacro ( IDLoc ) ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits15To0 = ImmValue & <NUM_LIT> ; if ( ! Is32BitImm && ! isInt < <NUM_LIT> > ( ImmValue ) ) { if ( ImmValue == <NUM_LIT> ) { emitRI ( <STR_LIT> , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } emitRRI ( <STR_LIT> , TmpReg , ZeroReg , Bits31To16 , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; if ( Bits15To0 ) emitRRI ( <STR_LIT> , TmpReg , TmpReg , Bits15To0 , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } emitRI ( <STR_LIT> , TmpReg , Bits31To16 , IDLoc , Instructions ) ; if ( Bits15To0 ) emitRRI ( <STR_LIT> , TmpReg , TmpReg , Bits15To0 , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } if ( isShiftedUIntAtAnyPosition < <NUM_LIT> > ( ImmValue ) ) { if ( Is32BitImm ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } unsigned FirstSet = findFirstSet ( ( uint64_t ) ImmValue ) ; unsigned LastSet = findLastSet ( ( uint64_t ) ImmValue ) ; unsigned ShiftAmount = FirstSet - ( <NUM_LIT> - ( LastSet - FirstSet ) ) ; uint16_t Bits = ( ImmValue >> ShiftAmount ) & <NUM_LIT> ; emitRRI ( <STR_LIT> , TmpReg , ZeroReg , Bits , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , ShiftAmount , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( AdduOp , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; return false ; } warnIfNoMacro ( IDLoc ) ; if ( loadImmediate ( ImmValue >> <NUM_LIT> , TmpReg , <STR_LIT> , true , false , IDLoc , Instructions ) ) return false ; unsigned ShiftCarriedForwards = <NUM_LIT> ; for ( int BitNum = <NUM_LIT> ; BitNum >= <NUM_LIT> ; BitNum -= <NUM_LIT> ) { uint16_t ImmChunk = ( ImmValue >>


<s> MCSymbol * <ISA_LIT>AsmPrinter :: lookUpOrCreateTOCEntry ( MCSymbol * Sym ) { const DataLayout * DL = TM . getDataLayout ( ) ; MCSymbol * & TOCEntry = TOC [ Sym


<s> return m_MultipartList [ <NUM_LIT> ] . m_LocalNum +


i ] . Reg , Offsets [ i ] * <NUM_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Arg ) ; } CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , VT . getTypeForEVT ( * DAG . getContext ( ) ) , ES , std :: move ( Args ) ) ; return LowerCallTo ( CLI ) .


<s> return ( __m128i ) __builtin_ia32_pmovusqd256_mask ( ( __v4di ) __A , ( __v4si ) _mm_undefined_si128 ( ) , (


<s> bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask


<s> return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && ( rs6000_function_arg_padding ( TYPE_MODE ( valtype )


<s> auto I = Converters . find ( { i , MI -> getOpcode ( ) } ) ; if ( I == Converters . end ( ) || ! I -> second -> isLegal ( MI , TII ) ) C . setIllegal ( ( RegDomain


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAccessReg ( OperandVector & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , nullptr ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: createAccessReg ( Reg . Num , Reg . StartLoc , Reg . EndLoc ) ) ; return MatchOperand_Success


<s> return __builtin_loongson_psubsh ( s


<s> unsigned Rm = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ; bool isAdd = <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ; <STR_LIT> ShOp = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned SBits = getShiftOp


<s> case <STR_LIT> : break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return true ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( VT . getFixedSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits ( ) ) return false ; if ( ! VT . isPow2VectorType ( ) ) return false ; return


<s> if ( LLVM_UNLIKELY ( ! Subtarget . hasPA ( ) ) ) report_fatal_error ( <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator TI = MBB . getFirstTerminator ( ) ; if ( TI != MBB . end ( ) && TI -> getOpcode ( ) == <STR_LIT> && ArgumentStackToRestore == <NUM_LIT> ) { BuildMI ( MBB , TI , DL , TII -> get ( <STR_LIT> ) ) . copyImplicitOps ( * TI ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MBB . erase ( TI ) ; return ; } if ( ArgumentStackToRestore >= <NUM_LIT> ) { int64_t Offset = <NUM_LIT> ; MachineBasicBlock :: iterator FrameI = TI == MBB . end ( ) ? MBB . end ( ) : std :: prev ( TI ) ; if ( FrameI != MBB . end ( ) && canMergeRegUpdate ( FrameI , <STR_LIT> , ArgumentStackToRestore , & Offset ) ) { Offset -= ArgumentStackToRestore ; if ( Offset == <NUM_LIT> ) MBB . erase ( FrameI ) ; else { FrameI -> setDesc ( TII -> get ( Offset >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; FrameI -> getOperand ( <NUM_LIT> ) . setImm ( std :: abs ( Offset


<s> format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( Fragment -> getParent (


<s> static void aarch64_init_libfuncs ( void ) { set_conv_libfunc ( trunc_optab , HFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , SFmode , HFmode , <STR_LIT> ) ; set_optab_libfunc ( add_optab , HFmode , NULL ) ; set_optab_libfunc ( sdiv_optab , HFmode , NULL ) ; set_optab_libfunc ( smul_optab , HFmode , NULL ) ; set_optab_libfunc ( neg_optab , HFmode , NULL ) ; set_optab_libfunc ( sub_optab , HFmode , NULL ) ; set_optab_libfunc ( eq_optab , HFmode , NULL ) ; set_optab_libfunc ( ne_optab , HFmode , NULL ) ; set_optab_libfunc ( lt_optab , HFmode , NULL ) ; set_optab_libfunc ( le_optab , HFmode , NULL ) ; set_optab_libfunc ( ge_optab , HFmode , NULL ) ; set_optab_libfunc ( gt_optab , HFmode , NULL


<s> return <STR_LIT> ( ( <NUM_LIT> << <NUM_LIT> )


<s> MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( MachineBasicBlock :: iterator ( I ) ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loop1MBB , BranchProbability :: getOne ( ) ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; loop1MBB -> addLiveIn ( Ptr ) ; loop1MBB -> addLiveIn ( OldVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( SC ) , NewVal ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop2MBB , DL , TII -> get ( BEQ ) ) . addReg ( NewVal , RegState :: Kill ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; loop2MBB -> addLiveIn ( Ptr ) ; loop2MBB -> addLiveIn ( NewVal ) ; addPostLoopLiveIns ( exitMBB


<s> bool <ISA_LIT>CodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) || DisableCGP ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; bool MadeChange = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; for ( BasicBlock & BB : F ) { auto & Insts = BB . getInstList ( ) ; for ( auto & I : Insts ) { if ( AllVisited . count ( & I ) ) continue ; if ( isa < ICmpInst > ( I ) ) { auto & CI = cast < ICmpInst > ( I ) ; if ( CI . isSigned ( ) || ! isa < IntegerType > ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CI << <STR_LIT> ) ; for ( auto & Op : CI . operands ( ) ) { if ( auto * I = dyn_cast < Instruction > ( Op ) ) MadeChange |= TryToPromote (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc =


<s> } unsigned Type = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_ARM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_ARM_MOVW_PREL_NC ; break ; } return


<s> O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << ImmOffs ; O <<


<s> case <STR_LIT> : return PXLowerSUB ( Op , DAG ) ; case <STR_LIT> : return PXLowerMUL ( Op , DAG ) ; case <STR_LIT> : return PXLowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PXLowerShift ( Op , DAG ) ; case <STR_LIT> : return PXLowerINSERT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return PXLowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return PXLowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return PXLowerSETCC (


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG .

getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> auto Cst = getBuildVectorConstantSplat ( * MI , MRI ) ; if ( ! Cst ) return false ; Cnt = * Cst ; int64_t ElementBits = Ty . getScalarSizeInBits ( ) ; return Cnt >= <NUM_LIT> && Cnt


<s> ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp ,


<s> <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true


<s> return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo


<s> case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_MOFFS8 : case TYPE_REL8 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS16 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS32


<s> PHINode * CurrentPHINode = dyn_cast < PHINode > ( & CurrentPHI ) ; if ( ! CurrentPHINode ) continue ; if ( ! SE -> isSCEVable ( CurrentPHINode -> getType ( ) ) ) continue ; const SCEV * PHISCEV = SE -> getSCEVAtScope ( CurrentPHINode , L ) ; const SCEVAddRecExpr * PHIBasePtrSCEV = dyn_cast < SCEVAddRecExpr > ( PHISCEV ) ; if ( ! PHIBasePtrSCEV ) continue ; const SCEVConstant * PHIBasePtrIncSCEV = dyn_cast < SCEVConstant > ( PHIBasePtrSCEV -> getStepRecurrence ( * SE ) ) ; if ( ! PHIBasePtrIncSCEV ) continue ; if ( CurrentPHINode -> getNumIncomingValues ( ) == <NUM_LIT> ) { if ( ( CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == LatchBB && CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == PredBB ) || ( CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == LatchBB && CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == PredBB ) ) { if ( PHIBasePtrSCEV -> getStart ( ) == BasePtrStartSCEV && PHIBasePtrIncSCEV == BasePtrIncSCEV ) { ++


<s> if ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) ) return true ; if ( mode == BLKmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return true ; return false


<s> if ( ( arm_select_cc_mode ( cond1 = GET_CODE ( x ) , XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) != CCmode ) || ( arm_select_cc_mode ( cond2 = GET_CODE ( y ) , XEXP ( y , <NUM_LIT> ) , XEXP ( y , <NUM_LIT> ) ) != CCmode ) ) return CCmode ; if ( cond_or == DOM_CC_NX_OR_Y ) cond1 = reverse_condition ( cond1 ) ; if ( cond1 != cond2 && ! comparison_dominates_p ( cond1 , cond2 ) && ( swapped = <NUM_LIT> , ! comparison_dominates_p ( cond2 , cond1 ) ) ) return CCmode ; if ( swapped ) std :: swap ( cond1 , cond2 ) ; switch ( cond1 ) { case EQ : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DEQmode ; switch ( cond2 ) { case EQ : return CC_DEQmode ; case LE : return CC_DLEmode ; case LEU : return CC_DLEUmode ; case GE : return CC_DGEmode ; case GEU : return CC_DGEUmode ; default : gcc_unreachable ( ) ; } case LT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTmode ; switch ( cond2 ) { case LT : return CC_DLTmode ; case LE : return CC_DLEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTmode ; switch ( cond2 ) { case GT : return CC_DGTmode ; case GE : return CC_DGEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case LTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTUmode ; switch ( cond2 ) { case LTU : return CC_DLTUmode ; case LEU : return CC_DLEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTUmode ; switch ( cond2


<s> MCOperand ci32 = MCOperand :: createImm ( <NUM_LIT> ) ; emitLEAzzi ( OutStreamer , lo , RD , STI ) ; emitANDrm0 ( OutStreamer , RD , ci32 , RD , STI


<s> for ( auto & MO : MI -> operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return <NUM_LIT> ; RegDomain OpDomain = getDomain ( MRI -> getRegClass ( MO . getReg ( ) ) , MRI -> getTargetRegisterInfo ( ) ) ; if ( OpDomain == DstDomain


<s> if ( ! scanFunction ( ) ) return false ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI


<s> unsigned <ISA_LIT>CodeEmitter :: getSimm19Lsl2Encoding ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable ( <STR_LIT>


<s> if ( ! ARM_DOUBLEWORD_ALIGN ) return PARM_BOUNDARY ; int res = arm_needs_doubleword_align ( mode , type ) ; if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; if ( res > <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; return res > <NUM_LIT> ?


<s> MFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; Context = & funcInfo . Fn -> getContext ( ) ; TargetSupported = ( ( Subtarget -> getRelocationModel ( ) == Reloc :: PIC_ ) && ( Subtarget -> has<ISA_LIT>32r2 ( ) && ( Subtarget -> isABI_O32


<s> else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( KillSrc ) ) ; return ; } } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } assert ( Opc


<s> return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> )

, BoolCarry , DAG . getConstant ( <NUM_LIT> , DL , CarryVT ) ) ;


<s> if ( Mnemonic . getToken ( ) == <STR_LIT> || Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ; Operands . pop_back ( ) ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( IdVal ) ) { int64_t Imm ; if ( IdVal -> evaluateAsAbsolute ( Imm ) ) IdVal = MCConstantExpr :: create ( Imm ,


<s> unsigned ShiftVal = <STR_LIT> ( MO1 . getImm ( ) ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) | ( ShiftVal == <NUM_LIT> ? <NUM_LIT> : ( <NUM_LIT> << <NUM_LIT> ) ) ; assert ( MO . isExpr


<s> assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT>

, LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ;


<s> bool isReg ( ) const { return Kind == k_Register && ! Reg .


<s> if ( ! TARGET_ABI_GNU && regno < crtl -> args . info . regs - <NUM_LIT> ) { regno = crtl -> args . info . regs - <NUM_LIT> ; if ( regno > MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( opcode == <STR_LIT> || opcode == <STR_LIT> ) ; SDValue SrcReg64 = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; SDValue Lo32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; Hi32 = DAG . getNode ( opcode , dl , <STR_LIT> , Hi32 ) ; SDValue DstReg64 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT>


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCCOutOperands ( Inst , <NUM_LIT> ) ; unsigned RegOp = <NUM_LIT> ; if ( Operands . size ( ) == <NUM_LIT> && ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) == ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT>


<s> void <ISA_LIT>BaseInstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { assert ( MI && OpNum < MI -> getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( TRI && <STR_LIT> ) ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg


<s> if ( ! VT . isVector ( ) || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> getConstantSplatNode ( ) )


<s> static DecodeStatus DecodeCallTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm (


<s> unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext


<s> bool <ISA_LIT>FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction ::


<s> static const struct { const char * arg ; const char * name ; HOST_WIDE_INT if_set ; } mapping [ ] = { { <STR_LIT> , <STR_LIT> , MASK_64BIT } , { <STR_LIT> , <STR_LIT> , MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , MASK_ALTIVEC } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { NULL , <STR_LIT> , <NUM_LIT> } } ; const char * cpu_id = <STR_LIT> ; size_t i ; rs6000_file_start ( ) ; darwin_file_start ( ) ; if ( rs6000_default_cpu != <NUM_LIT> && rs6000_default_cpu [ <NUM_LIT> ] != '\0' ) cpu_id = rs6000_default_cpu ; if ( OPTION_SET_P ( rs6000_cpu_index ) ) cpu_id = processor_target_table [ rs6000_cpu_index ] . name ; i = <NUM_LIT> ; while ( mapping [ i ] . arg != NULL && strcmp ( mapping [ i ] . arg , cpu_id ) != <NUM_LIT> && ( mapping [ i ] . if_set & rs6000_isa_flags ) == <NUM_LIT> ) i ++ ; fprintf ( asm_out_file , <STR_LIT> , mapping [


<s> return ( __m128i ) __builtin_ia32_vpcomltuq ( ( __v2di ) __A , ( __v2di )


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = macho :: RIT_Vanilla ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = macho :: RIT_Difference ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( )


<s> assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI


<s> void setReorder ( ) { reorder = true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr >


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> uint64_t ZeroChunk = UImm & ~ ShiftedMask ; uint64_t OneChunk = UImm | ShiftedMask ; uint64_t RotatedImm = ( UImm << <NUM_LIT> ) | ( UImm >> <NUM_LIT> ) ; uint64_t ReplicateChunk = ZeroChunk | ( RotatedImm & ShiftedMask ) ; if ( <STR_LIT> ( ZeroChunk , BitSize , Encoding ) || <STR_LIT> ( OneChunk , BitSize , Encoding ) || <STR_LIT> ( ReplicateChunk , BitSize , Encoding ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( Encoding ) ; const unsigned Imm16 = getChunk ( UImm , Shift / <NUM_LIT> ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , Shift ) ) ; transferImpOps ( MI , MIB


<s> if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) )


<s> return ( __m64 ) __builtin_ia32_phsubw ( ( __v4hi ) __X ,


<s> EVT SrcSVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; if ( <STR_LIT> == Src . getOpcode ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Src . getOperand ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( ! resolveTargetShuffleInputs ( peekThroughBitcasts ( Src ) , Ops , Mask , DAG ) ) return SDValue ( ) ; if ( Mask . size ( ) != NumSrcElts ) { if ( ( NumSrcElts % Mask . size ( ) ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ScaledMask ; int Scale = NumSrcElts / Mask . size ( ) ; scaleShuffleMask < int > ( Scale , Mask , ScaledMask ) ; Mask = std :: move ( ScaledMask ) ; } else if ( ( Mask . size ( ) % NumSrcElts ) == <NUM_LIT> ) { int ExtractIdx = ( int ) N -> getConstantOperandVal ( <NUM_LIT> ) ; int Scale = Mask . size ( ) / NumSrcElts ; int Lo = Scale * ExtractIdx ; int Hi = Scale * ( ExtractIdx + <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = ( int ) Mask . size ( ) ; i != e ; ++ i ) if ( i < Lo || Hi <= i ) Mask [ i ] = SM_SentinelUndef ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue (


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple &


<s> static unsigned CopyToFromAsymmetricReg ( unsigned DestReg , unsigned SrcReg , const <ISA_LIT>Subtarget & Subtarget ) { bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . contains ( SrcReg )


<s> MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII . Imm ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return ; } else MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) .


<s> case <STR_LIT> : Opc = Subtarget -> hasAVX512 ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = Subtarget -> hasAVX512 ( ) ? <STR_LIT> : <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = <STR_LIT> ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { Register CondReg = getRegForValue (


<s> return ( __m256i ) __builtin_ia32_compressdi256_mask ( ( __v4di ) __A , ( __v4di ) _mm256_setzero_si256 ( )


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> static const MCInstrDesc & getInstDesc ( unsigned Opcode ) { return <ISA_LIT>Insts [


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCA . setCPUSubType ( <STR_LIT>


<s> MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; SDNode * Result = CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return std :: make_pair ( true , Result ) ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; std :: pair < SDNode * , SDNode * > LoHi = selectMULT ( Node , MultOpc , DL , NodeTy , true , true ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . first , <NUM_LIT> ) ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . second , <NUM_LIT> ) ) ; return std :: make_pair ( true , nullptr ) ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDNode * Result = selectMULT ( Node , MultOpc , DL , NodeTy , false , true


<s> static bool isThumb ( const MCSubtargetInfo & STI ) { return STI . getFeatureBits (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment

* DF , const MCAsmLayout & Layout ) const override {


<s> RTLIB :: Libcall LC ; if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( ArgVT , VT ) ; else LC = RTLIB :: getFPTOUINT ( ArgVT , VT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDLoc dl ( Op ) ; MakeLibCallOptions CallOptions ; Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , <STR_LIT> , Arg , CallOptions , dl , Chain ) ; Result = DAG . getBitcast ( VT ,


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; LL = <STR_LIT> ; SC = <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; MI -> eraseFromParent


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , MRI , STI ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU


<s> two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ <NUM_LIT> ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ <NUM_LIT> ] , two31r , val , tmp [ <NUM_LIT> ] ) ) ; tmp [ <NUM_LIT> ] = expand_simple_binop ( mode , AND , tmp [ <NUM_LIT> ] , two31r , tmp [ <NUM_LIT> ] , <NUM_LIT> , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ <NUM_LIT> ] ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( HOST_WIDE_INT_1U << <NUM_LIT> ) ; two31 = ix86_build_const_vector ( intmode , <NUM_LIT> , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [


<s> unsigned <ISA_LIT>SEDAGToDAGISel :: getMSACtrlReg ( const SDValue RegIdx ) const { switch ( cast < ConstantSDNode > ( RegIdx ) -> getZExtValue ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return


<s> Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const unsigned Option = MO . getTargetFlags ( ) & <STR_LIT> ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; switch ( Option ) { default : break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) { return MCOperand :: createExpr (


<s> rtx offset_rtx = extract_offset_rtx ( insn ) ; if ( offset_rtx == NULL_RTX ) return false ; if ( REG_P ( offset_rtx


<s> static struct machine_function * mt_init_machine_status ( void ) { struct machine_function *


<s> void setVarArgsRegSaveSize ( unsigned


<s> return Kind == k_Register && Reg . Kind == RegKind :: Scalar &&

<ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CMPOpc ; unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc ( Opc , CMPOpc ) ; BuildMI ( mainMBB , DL , TII -> get ( CMPOpc ) ) . addReg ( SrcReg ) . addReg ( t4 ) ; if ( Subtarget -> hasCMov ( ) ) { if ( VT != <STR_LIT> ) { BuildMI ( mainMBB , DL , TII -> get ( CMOVOpc ) , t2 ) . addReg ( SrcReg ) . addReg ( t4 ) ; } else { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const TargetRegisterClass * RC32 = TRI -> getSubClassWithSubReg ( getRegClassFor ( <STR_LIT> ) , <STR_LIT> ) ; unsigned SrcReg32 = MRI . createVirtualRegister ( RC32 ) ; unsigned AccReg32 = MRI . createVirtualRegister ( RC32 ) ; unsigned Tmp = MRI . createVirtualRegister ( RC32 ) ; unsigned Undef = MRI . createVirtualRegister ( RC32 ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Undef ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , SrcReg32 ) . addReg ( Undef ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , AccReg32 ) . addReg ( Undef ) . addReg ( t4 ) . addImm ( <STR_LIT> ) ; BuildMI ( mainMBB , DL , TII -> get ( CMOVOpc ) , Tmp ) . addReg ( SrcReg32 ) . addReg ( AccReg32 ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: COPY ) , t2 ) . addReg ( Tmp , <NUM_LIT> , <STR_LIT> ) ; } } else { assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned SelOpc = getPseudoCMOVOpc ( VT ) ; <STR_LIT> CC = <STR_LIT> ( CMOVOpc ) ; assert ( CC != <STR_LIT> && <STR_LIT> ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( SelOpc ) , t2 ) . addReg ( SrcReg ) . addReg ( t4 ) . addImm ( CC ) ; mainMBB = EmitLoweredSelect ( MIB , mainMBB ) ; BuildMI ( * origMainMBB , Phi , DL , TII -> get ( <STR_LIT> ) , t4 ) . addReg ( t1 ) . addMBB ( thisMBB ) . addReg ( t3 ) . addMBB ( mainMBB ) ; Phi -> eraseFromParent (


<s> emit_insn ( gen_blockage ( ) ) ; } if ( size < ( <NUM_LIT> << param_stack_clash_protection_guard_size ) ) { pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( NO_PROBE_SMALL_FRAME , true ) ; return ; } HOST_WIDE_INT probe_interval = get_probe_interval ( ) ; if ( size <= <NUM_LIT> * probe_interval ) { HOST_WIDE_INT i ; for ( i = probe_interval ; i <= size ; i += probe_interval ) { rtx insn = pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - probe_interval ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_stack_probe ( stack_pointer_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } HOST_WIDE_INT residual = ( i - probe_interval - size ) ; if ( residual ) pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( residual ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( PROBE_INLINE , residual != <NUM_LIT> ) ; } else { gcc_assert ( int_registers_saved ) ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; if ( sr . saved ) size -= UNITS_PER_WORD ; HOST_WIDE_INT rounded_size = size & - probe_interval ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ; rtx insn ; if ( address_no_seg_operand ( addr , Pmode ) ) insn = emit_insn ( gen_rtx_SET ( sr . reg , addr ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; insn = emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , sr . reg , m -> fs . cfa_offset + rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } rtx size_rtx = GEN_INT ( rounded_size ) ; insn = emit_insn ( gen_adjust_stack_and_probe ( Pmode , sr . reg , sr . reg , size_rtx ) ) ; if ( m -> fs .


<s> return getInvalidInstructionMapping ( ) ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ) OpRegBankIdx [ Idx ] = PMI_FirstFPR ; else OpRegBankIdx [ Idx ] = PMI_FirstGPR ; } unsigned Cost = <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : OpRegBankIdx = { PMI_FirstFPR , PMI_FirstGPR } ; break ; case TargetOpcode :: G_FPTOSI : case TargetOpcode :: G_FPTOUI : OpRegBankIdx = { PMI_FirstGPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_FCMP : OpRegBankIdx = { PMI_FirstGPR , PMI_None , PMI_FirstFPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_BITCAST : if ( OpRegBankIdx [ <NUM_LIT> ] != OpRegBankIdx [ <NUM_LIT> ] ) Cost = copyCost ( * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , OpSize [ <NUM_LIT> ] ) ; break ; case TargetOpcode :: G_LOAD : if ( OpRegBankIdx [ <NUM_LIT> ] != PMI_FirstGPR ) Cost = <NUM_LIT> ; else for ( const MachineInstr & UseMI : MRI . use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( isPreISelGenericFloatingPointOpcode ( UseMI .


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef SymbolName = Tok . getIdentifier ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( SymbolName ) ; if ( ! Sym ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { auto * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EltVT ) return SDValue ( ) ; if ( Elt -> getAPIntValue ( ) . isNullValue ( ) ) return SDValue ( ) ; NewVecC . push_back ( DAG . getConstant ( Elt -> getAPIntValue


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv8qi ( ( int8x8_t


<s> MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; Offset += SPAdj ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . RemoveOperand ( FIOperandNum + <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) { return ; } unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { Offset += ( int32_t ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister (


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , SDLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize


<s> if ( isPrefix ( PrevInst , * MCII ) ) return ; if ( isRightAfterData ( OS . getCurrentFragment ( ) , PrevInstPosition ) ) return ; if ( ! isMacroFused ( PrevInst ,

Inst ) ) PendingBoundaryAlign = nullptr ;


<s> unsigned prfop = MI -> getOperand ( OpNum ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( prfop , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << Name ; else O << '#' <<


<s> X >>= <NUM_LIT> ; val = helper_insert_val_thumb_movw_movt_inst ( val , X ) ; * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) = val >> <NUM_LIT> ; * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) = val & <NUM_LIT> ; return Relocator


<s> unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; bool IsWinEH = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int Offset ; unsigned IgnoredFrameReg ; if ( IsWinEH ) Offset = TFI -> getFrameIndexReferenceFromSP ( MF , FrameIndex , IgnoredFrameReg ) ; else Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; unsigned IgnoredFrameReg ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexReference ( MF ,


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Val ) ) return CreateImm ( CE -> getValue ( ) , S , E , Is<ISA_LIT>64 ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Val ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ) return CreateTLSReg ( SRE , S , E , Is<ISA_LIT>64 ) ; if ( const <ISA_LIT>MCExpr * TE = dyn_cast < <ISA_LIT>MCExpr > ( Val ) ) { int64_t Res


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok (


<s> static bool mips_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { return ( TARGET_OLDABI ? TYPE_MODE ( type ) == BLKmode : ! IN_RANGE ( int_size_in_bytes ( type ) , <NUM_LIT>


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } unsigned LowGPR = ZFI -> getLowSavedGPR ( ) ; unsigned HighGPR = ZFI -> getHighSavedGPR ( ) ; unsigned StartOffset = RegSpillOffsets [ LowGPR ] ; if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( LowGPR , RegState :: Define ) ; MIB . addReg ( HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg


<s> rtx cmp_op0 = operands [ <NUM_LIT> ] ; rtx cmp_op1 = operands [ <NUM_LIT> ] ; rtx tmp_reg ; rtx tmp ; int reverse = <NUM_LIT> ; switch ( code ) { case GT : case GE : tmp = cmp_op0 ; cmp_op0 = cmp_op1 ; cmp_op1 = tmp ; new_code = swap_condition ( new_code ) ; break ; case UNORDERED : case LT : case LE : case EQ : break ; case ORDERED : case


<s> const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , {


<s> materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this ,


<s> auto & MRI = * MIRBuilder . getMRI ( ) ; const RegClassOrRegBank & RegClassOrBank = MRI . getRegClassOrRegBank ( Dst ) ; unsigned Size ; if ( const auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) Size = TRI . getRegSizeInBits ( * RC ) ; else Size = MRI . getType ( Dst ) . getSizeInBits ( ) ; assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; static const unsigned OpcTable [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; unsigned Opc = OpcTable [ Size == <NUM_LIT> ] ; auto CSINC = MIRBuilder . buildInstr ( Opc , { Dst } , { Src1 , Src2 } ) . addImm ( Pred ) ; constrainSelectedInstRegOperands ( * CSINC , TII , TRI , RBI ) ; return & * CSINC


<s> bool MadeChange = false ; if ( isThumb2 && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } if ( ! isThumb1 ) MF -> ensureAlignment ( <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( )


<s> bool <ISA_LIT>MachineFunctionInfo :: globalBaseRegSet ( ) const { return GlobalBaseReg


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; assert ( Align > <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; const bool HasSPE = <ISA_LIT>SubTarget -> hasSPE ( ) ; const TargetRegisterClass * RC ; if ( HasSPE ) RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; else RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc ; if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT>

) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ;


<s> static const <ISA_LIT>MCExpr * CreateGOT ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_AARCH64_GOT , Expr


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( C -> isNullValue ( ) && CC == <STR_LIT> ) { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Zext = Op . getOperand ( <NUM_LIT> ) ; if ( VT . bitsLT ( <STR_LIT> ) ) { VT = <STR_LIT> ; Zext = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned Log2b = Log2_32 ( VT


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > (


<s> return GET_CODE ( x ) == REG && INT_REG_OK_FOR_BASE_P (


<s> bool isDarwinSyntax ( ) const { return


<s> rtx set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set ) =


<s> return std :: make_tuple ( ! A . IsValid , A . ObjectFirst , A . GroupFirst , A . GroupIndex , A . ObjectIndex ) < std :: make_tuple ( ! B . IsValid , B . ObjectFirst , B .

GroupFirst , B . GroupIndex , B . ObjectIndex ) ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val


<s> OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> getContainingCsect ( ) ) ; OutStreamer -> EmitLabel ( CurrentFnDescSym ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( TOCBaseSym , OutContext ) , PointerSize ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , PointerSize


<s> static unsigned int branchTargetOperand ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MBB . size ( ) == <NUM_LIT> ) TS .


<s> auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool UsesWinAAPCS = isTargetWindows ( MF ) ; if ( UsesWinAAPCS && hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) ) { int FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlign ( * RC ) ) ; int FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseMSA128WRegs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseMSARegs ( Operands , ( int ) <STR_LIT>


<s> if ( isUnpredicatedTerminator ( SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastOpc == UncondBrOpc ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( LastOpc != UncondBrOpc ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT>


<s> uint64_t <ISA_LIT>Subtarget :: getAdjustedFrameSize ( uint64_t FrameSize ) const { const <ISA_LIT>FrameLowering * TFL = getFrameLowering ( ) ; FrameSize += getRsaSize ( ) ; FrameSize = alignTo ( FrameSize , TFL -> getStackAlign ( ) ) ; return FrameSize


<s> case BDMem : if ( HaveReg1 ) { if ( parseAddressRegister ( Reg1 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg1 . Num ] ; } if ( Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( HaveReg2 ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDXMem : if ( HaveReg1 ) { if ( parseAddressRegister ( Reg1 ) ) return MatchOperand_ParseFail ; if ( HaveReg2 ) Index = Regs [ Reg1 . Num ] ; else Base = Regs [ Reg1 . Num ] ; } if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDLMem : if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( HaveReg1 && HaveReg2 ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDRMem : if ( ! HaveReg1 || Reg1 . Group != RegGR ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } LengthReg = <STR_LIT> [ Reg1 . Num ] ; if ( HaveReg2 ) { if ( parseAddressRegister ( Reg2 ) ) return MatchOperand_ParseFail ; Base = Regs [ Reg2 . Num ] ; } if ( Length ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; case BDVMem : if ( ! HaveReg1 || Reg1 . Group !=


<s> auto parseOne = [ & ] ( ) -> bool { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue (


<s> if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getVectorElementType ( ) . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { if ( <NUM_LIT> * SrcVT . getSizeInBits ( ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> * VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) ,


<s> rtx sh_movrt_set_dest ( const_rtx pat ) { if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; return GET_CODE ( pat ) == SET && arith_reg_dest ( XEXP ( pat , <NUM_LIT> ) , SImode ) && negt_reg_operand ( XEXP ( pat , <NUM_LIT> ) , VOIDmode )


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> unsigned NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , true , DAG ) ; unsigned OpSrc ; if ( ! NumZeros ) return false ; if ( ! isShuffleMaskConsecutive ( SVOp , NumZeros , NumElems - <NUM_LIT> , <NUM_LIT> , NumElems , OpSrc ) ) return false ; isLeft = true ; ShAmt =


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) :


<s> vmvnq_u32 ( uint32x4_t a ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> bool isImm ( ) const override { return Kind ==


<s> static bool isLdStSafeToCluster ( const MachineInstr & LdSt , const TargetRegisterInfo * TRI ) { if ( LdSt . hasOrderedMemoryRef ( ) || LdSt . getNumExplicitOperands ( ) != <NUM_LIT>


<s> return ( ST == <STR_LIT> || ST == <STR_LIT> || ST == <STR_LIT> || ST ==


<s> SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , DL


<s> void <ISA_LIT>CallFrameOptimization :: collectCallInfo ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , CallContext & Context ) { const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI -> getRegisterInfo ( ) ) ; assert ( I -> getOpcode ( ) == TII -> getCallFrameSetupOpcode ( ) ) ; MachineBasicBlock :: iterator FrameSetup = I ++ ; Context . FrameSetup = FrameSetup ; unsigned int MaxAdjust = TII -> getFrameSize ( * FrameSetup ) >> Log2SlotSize ; if ( ! MaxAdjust ) { Context . NoStackParams = true ; return ; } while ( I -> getOpcode ( ) == <STR_LIT> || I -> isDebugInstr ( ) ) ++ I ; Register StackPtr = RegInfo . getStackRegister ( ) ; auto StackPtrCopyInst = MBB . end ( ) ; for ( auto J = I ; ! J -> isCall ( ) ; ++ J ) if ( J -> isCopy ( ) && J -> getOperand ( <NUM_LIT> ) . isReg ( ) && J -> getOperand ( <NUM_LIT> ) . isReg ( ) && J -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { StackPtrCopyInst = J ; Context . SPCopy = & * J ++ ; StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } if ( MaxAdjust > <NUM_LIT> ) Context . ArgStoreVector . resize ( MaxAdjust , nullptr ) ; DenseSet < unsigned int > UsedRegs ; for ( InstClassification Classification = Skip ; Classification != Exit ; ++ I ) { if ( I == StackPtrCopyInst ) continue ; Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ; if ( Classification != Convert ) continue ; if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT>


<s> enum rtx_code cmp_code = GET_CODE ( operands [ <NUM_LIT> ] ) ; enum machine_mode mode = GET_MODE ( cmp_operands [ <NUM_LIT> ] ) ; switch ( cmp_code ) { case GT : cmp_code = LT ; break ; case LE : cmp_code = GE ; break ; case GTU : cmp_code = LTU ; break ; case LEU : cmp_code = GEU ; break ; default : break ; } if ( cmp_code == GET_CODE ( operands [ <NUM_LIT> ] ) ) { op0 = cmp_operands [ <NUM_LIT> ] ; op1 = cmp_operands [ <NUM_LIT> ] ; } else { op0 = cmp_operands [


<s> Value * <ISA_LIT>IREmitter :: visitPEXTRB ( const SDNode * N


<s> const bool Is64Bit = <STR_LIT> . contains ( Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reg << <STR_LIT> ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> )


<s> const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT>


<s> void \ private_data_section ( ) \ { \ if ( in_section != private_data ) \ { \ fprintf ( asm_out_file , <STR_LIT> , \ xcoff_private_data_section_name ) ; \


<s> if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return false


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c )


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT>

) . getImm ( ) == ImmValue ) return true ;


<s> Value * <ISA_LIT>IREmitter :: visitBSF ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { Opcode = N1 . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return SDValue ( ) ; std :: swap ( N0 , N1 ) ; } if ( N0 == N1 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand (


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB ,

MachineBasicBlock :: iterator I ) const {