<s> Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } } ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getElementType ( ) , BaseAddr , VecTy -> getNumElements ( ) * Factor ) ; CallInst * VldN = createLoadIntrinsic ( BaseAddr ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( VldN ,


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT , Legal ) ; setIndexedStoreAction ( im , VT , Legal ) ; } if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT LongTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : LongTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , <STR_LIT> , Legal ) ; setIndexedStoreAction ( im , <STR_LIT> , Legal ) ; setIndexedLoadAction ( im , <STR_LIT> ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm ( ) ; addExpr ( Inst , Expr


<s> reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . reallowModuleDirective ( ) ; getParser ( ) . Lex ( ) ; return false


<s> return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT>


<s> rtx op [ <NUM_LIT> ] ; machine_mode mode [ <NUM_LIT> ] ; int i ; mode [ <NUM_LIT> ] = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; for ( i = <NUM_LIT> ; i < argcount ; i ++ ) { arg [ i ] = CALL_EXPR_ARG ( exp , i ) ; op [ i ] = expand_normal ( arg [ i ] ) ; mode [ i ] = insn_data [ icode ] . operand [ i ] . mode ; if ( code [ i ] == CONST_INT && GET_CODE ( op [ i ] ) != CONST_INT ) error ( <STR_LIT> , i + <NUM_LIT> ) ; if ( code [ i ] == REG && ! ( * insn_data [ icode ] . operand [ i ] . predicate ) ( op [ i ] , mode [ i ] ) ) op [ i ] = copy_to_mode_reg ( mode [ i ] , op [ i ] ) ; } if ( insn_data [ icode ] . operand [ <NUM_LIT> ] . constraint [ <NUM_LIT> ] == '=' ) { if ( target == <NUM_LIT> || GET_MODE ( target ) != mode [ <NUM_LIT> ] || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , mode [ <NUM_LIT> ] ) ) target = gen_reg_rtx ( mode [ <NUM_LIT> ] ) ; } else target = <NUM_LIT> ; switch ( argcount ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [


<s> static SDValue lowerVectorShuffleWithPSHUFB ( const SDLoc & DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { int Size = Mask . size ( ) ; int LaneSize = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; const int NumBytes = VT . getSizeInBits ( ) / <NUM_LIT> ; const int NumEltBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; assert ( ( Subtarget . hasSSSE3 ( ) && VT . is128BitVector ( ) ) || ( Subtarget . hasAVX2 ( ) && VT . is256BitVector ( ) ) || ( Subtarget . hasBWI ( ) && VT . is512BitVector ( ) ) ) ; SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ( NumBytes ) ; SDValue ZeroMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue V ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) { int M = Mask [ i / NumEltBytes ] ; if ( M < <NUM_LIT> ) { PSHUFBMask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } if ( Zeroable [ i / NumEltBytes ] ) { PSHUFBMask [ i ] = ZeroMask ; continue ; } SDValue SrcV = ( M >= Size ? V2 : V1 ) ; if ( V && V != SrcV ) return SDValue ( ) ; V = SrcV ; M %= Size ; if ( ( M / LaneSize ) != ( ( i / NumEltBytes ) / LaneSize ) ) return SDValue ( ) ; M = M % LaneSize ; M = M * NumEltBytes + ( i % NumEltBytes ) ; PSHUFBMask [ i ] = DAG . getConstant ( M , DL , <STR_LIT> ) ; } assert ( V && <STR_LIT> ) ; MVT I8VT = <STR_LIT> ( <STR_LIT> ,


<s> <STR_LIT> Ty = getRegTy ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MF ) ; unsigned Reg = Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . getReg ( ) == Reg ) { MI . removeOperand ( I ) ; return ; } } llvm_unreachable ( nullptr )


<s> SelectionDAG & DAG = DCI . DAG ; if ( N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return SDValue


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + <NUM_LIT> ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ <NUM_LIT> ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_or_fixed_reg_p ( i ) ) clobs [ nclobs ++ ] = gen_hard_reg_clobber ( V4SImode , i ) ; else { rtx reg = gen_rtx_REG (


<s> bool HasStackObject = false ; for ( unsigned i = <NUM_LIT> , e = MFFrame . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( ! MFFrame . isDeadObjectIndex ( i ) ) { HasStackObject = true ; break ; } if ( HasStackObject || MFFrame . hasCalls ( ) ) StackSize += <STR_LIT> ; StackSize = StackSize > <STR_LIT> ? StackSize - <STR_LIT> : <NUM_LIT> ; MFFrame . setStackSize ( StackSize ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else continue ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned IgnoredFrameReg ; int64_t Offset = getFrameIndexReference ( MF , Save . getFrameIdx (


<s> return ( uint32x2_t ) __builtin_neon_vld1_dupv2si ( ( const __builtin_neon_si


<s> bool <ISA_LIT>TargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { EVT VecVT = VecOp . getValueType ( )


<s> if ( ! Subtarget . hasCMov ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; APInt Lg2Mask = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , Lg2 ) ; SDValue Pow2MinusOne = DAG . getConstant ( Lg2Mask , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , <STR_LIT> , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CMov = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( )


<s> assert ( AddcNode -> getNumValues ( ) == <NUM_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( AddcNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( AddeNode == NULL ) return SDValue ( ) ; if ( AddeNode -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( AddeNode -> getNumOperands ( ) == <NUM_LIT> && AddeNode -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiMul = & MULOp ; SDValue * HiAdd = NULL ; SDValue * LoMul = NULL ; SDValue * LowAdd = NULL ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 -> getOpcode ( ) == Opc ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 -> getOpcode ( )


<s> assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; } if ( TARGET_PROFILE_KERNEL && crtl -> profile ) { gcc_assert ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) ; gcc_assert ( ! TARGET_32BIT ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; if ( DEFAULT_ABI != ABI_ELFv2 && cfun -> static_chain_decl != NULL ) { asm_fprintf ( file , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] , reg_names [ <NUM_LIT> ] ) ; fprintf ( file , <STR_LIT> , RS6000_MCOUNT ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] , reg_names [ <NUM_LIT> ] ) ; } else fprintf ( file , <STR_LIT> , RS6000_MCOUNT ) ; } rs6000_pic_labelno


<s> IntrinsicInst * Pg = dyn_cast < IntrinsicInst > ( II . getArgOperand ( <NUM_LIT> ) ) ; if ( ! Pg ) return None ; if ( Pg -> getIntrinsicID ( ) != <STR_LIT> ) return None ; const auto PTruePattern = cast < ConstantInt > ( Pg -> getOperand ( <NUM_LIT> ) ) ->


<s> static bool areMatchingHiAndLo ( const MCAssembler & Asm , const ELFRelocationEntry & First ,


<s> if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true


<s> case IES_LPAREN : case IES_LBRAC : State = IES_REGISTER ; TmpReg = Reg ; IC . pushOperand ( IC_REGISTER ) ; break ; case IES_MULTIPLY : if ( PrevState == IES_INTEGER ) { if ( IndexReg ) { ErrMsg = <STR_LIT> ; return true ; } State = IES_REGISTER ; IndexReg = Reg ; Scale = IC . popOperand ( ) ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . pushOperand ( IC_IMM


<s> unsigned <ISA_LIT>16InstrInfo :: GetAnalyzableBrOpc ( unsigned Opc


<s> int <ISA_LIT>AsmParser :: matchFPURegisterName ( StringRef Name ) { if ( Name [ <NUM_LIT> ] == 'f' || Name [ <NUM_LIT> ] == 'd' ) { StringRef NumString = Name . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return -


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVT_ABS ; case <STR_LIT> : return ELF


<s> unsigned SizeFactor = OpVT . getSizeInBits ( ) / <NUM_LIT> ; MVT VT128 = <STR_LIT> ( OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / SizeFactor ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG ,


<s> SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back (


<s> case FP_REGS : if ( regno >= <NUM_LIT> && ! ( FR_REGNO_P ( regno ) || GENERAL_REGNO_P ( regno ) ) ) return GR_REGS ; if ( GET_CODE ( x ) == MEM && ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == HImode || GET_MODE ( x ) == QImode ) ) return GR_REGS ; if ( GET_CODE ( x ) == CONST_INT ) return GR_REGS ; if ( GET_CODE ( x ) ==


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( Subtarget -> isTargetELF ( ) ) { TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , getPointerTy ( ) , Subtarget -> is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) , DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain


<s> case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO (


<s> } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = DImode ; gen_func . mov = gen_movdi ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } addr = XEXP ( orig_src , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_src = replace_equiv_address ( orig_src , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; if ( mode != BLKmode ) { rtx tmp_reg = gen_reg_rtx ( mode ) ; emit_insn ( ( * gen_func . mov ) ( tmp_reg , src ) ) ; stores [ num_reg ++ ] = ( * gen_func . mov ) ( dest , tmp_reg ) ; } if ( mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes ) { int i ; for ( i = <NUM_LIT> ; i < num_reg ; i ++ ) emit_insn ( stores [ i ] ) ; num_reg = <NUM_LIT> ; } if ( mode == BLKmode ) { if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) ) { rtx src_reg = copy_addr_to_reg ( XEXP ( src , <NUM_LIT> ) ) ; src = replace_equiv_address ( src , src_reg ) ; } set_mem_size ( src , move_bytes ) ; if ( ! REG_P ( XEXP ( dest , <NUM_LIT> ) ) ) { rtx dest_reg = copy_addr_to_reg ( XEXP ( dest , <NUM_LIT> ) ) ; dest = replace_equiv_address ( dest , dest_reg


<s> bool <ISA_LIT>LegalizerInfo :: legalizeIntrinsic ( LegalizerHelper & Helper , MachineInstr & MI )


<s> return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleHardFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleMT ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option


<s> void rx_split_cbranch ( machine_mode cc_mode , enum rtx_code cmp1 , rtx c1 , rtx c2 , rtx label ) { rtx flags , x ; flags = gen_rtx_REG ( cc_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cc_mode ,


<s> return ( __m128 ) __builtin_ia32_cmpnltss ( ( __v4sf )


<s> EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo


<s> case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { unsigned lsb = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned widthm1 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( widthm1 >= <NUM_LIT> - lsb ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool hasWritebackToken = ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isToken ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) ; bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , Rn , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> + hasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( ! listContainsBase && ! hasWritebackToken && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( listContainsBase && hasWritebackToken ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { if ( listContainsReg ( Inst , <NUM_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , <NUM_LIT> , <STR_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; break ; } case <STR_LIT> : { bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , <NUM_LIT> , <STR_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; break ; } case <STR_LIT> : { bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; break ; } } return


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment * , const


<s> KnownBits Known = DAG . computeKnownBits ( Op0 ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } Src = Op1 ; BitNo = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { Src = AndLHS . getOperand ( <NUM_LIT> ) ; BitNo = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 ( AndRHSVal ) ) { Src = AndLHS ; BitNo = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , dl , Src . getValueType ( ) ) ; } } } if ( ! Src . getNode ( ) ) return SDValue ( ) ; if ( Src . getValueType ( ) == <STR_LIT> || Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) == <STR_LIT> && DAG . MaskedValueIsZero ( BitNo , APInt ( BitNo . getValueSizeInBits ( ) , <NUM_LIT> ) ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , dl , Src . getValueType ( ) , BitNo ) ; <ISA_LIT>CC = DAG . getConstant ( CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src


<s> if ( IntImm . getActiveBits ( ) > <NUM_LIT> ) return false ; bool Success = TII -> isRxSBGMask ( IntImm . getZExtValue ( ) , BitWidth , Start , End ) ; if ( ! Success


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot )


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>elDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64elTarget


<s> if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : <NUM_LIT> ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC ) ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> return __builtin_mve_vcmpltq_v16qi ( __a ,


<s> if ( TT . isOSBinFormatELF ( ) ) return make_unique < TargetLoweringObjectFileELF > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return make_unique < TargetLoweringObjectFileCOFF > ( ) ; llvm_unreachable (


<s> if ( OptLevel != CodeGenOpt :: None && Subtarget . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true


<s> unsigned CallOpc = PrepareCall ( DAG , Callee , InFlag , Chain , dl , SPDiff , isTailCall , RegsToPass , Ops , NodeTys , Subtarget ) ; if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } bool needsTOCRestore = false ; if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { if ( CallOpc == <STR_LIT> ) { needsTOCRestore = true ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { CallOpc = <STR_LIT> ; } } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( needsTOCRestore ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = <ISA_LIT>FrameLowering :: getTOCSaveOffset ( isELFv2ABI ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain


<s> for ( auto * U : CCUser -> uses ( ) ) { if ( CCRegUser == nullptr ) CCRegUser = U ; else if ( CCRegUser != U ) return false ; } } if ( CCRegUser == nullptr ) return false ; if ( CCRegUser -> isMachineOpcode ( ) && CCRegUser -> getMachineOpcode ( ) == <STR_LIT> ) return !

N -> isPredecessorOf ( CCUser -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ;


<s> PM . add ( create<ISA_LIT>ISelDag ( * this , OptLevel


<s> int Thumb1RegisterInfo :: rewriteFrameIndex ( MachineInstr & MI , unsigned FrameRegIdx , unsigned FrameReg , int Offset , unsigned MOVOpc , unsigned


<s> default : llvm_unreachable ( <STR_LIT> ) ; case 'I' : if ( ( short ) Value == ( int ) Value ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'J' : case 'L' : if ( ( short ) Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'K' : if ( ( Value >> <NUM_LIT> ) == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'M' : if ( Value > <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'N'


<s> unsigned int i = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_crc_builtin_data ) ; ++ i ) { aarch64_crc_builtin_datum * d = & aarch64_crc_builtin_data [ i ] ; tree argtype = aarch64_simd_builtin_std_type ( d -> mode , qualifier_unsigned ) ; tree ftype = build_function_type_list ( usi_type , usi_type , argtype ,


<s> else return NULL_RTX ; if ( GET_MODE ( extended_op ) != SImode ) return NULL_RTX ; set_of_reg s = sh_find_set_of_reg ( extended_op , insn , prev_nonnote_nondebug_insn_bb ) ; if ( s . set_src == NULL_RTX ) return NULL_RTX ; if ( t_reg_operand ( s . set_src , VOIDmode ) || negt_reg_operand ( s . set_src , VOIDmode ) ) return extended_op ; else if ( sh_is_logical_t_store_expr ( s . set_src , s . insn ) ) return extended_op ; return NULL_RTX


<s> static tree types [ <NUM_LIT> * ( int ) MAX_MACHINE_MODE ] ; int mode_index ; mode_index = ( int ) mode ; if ( TREE_CODE ( type ) == INTEGER_TYPE && TYPE_UNSIGNED ( type ) ) mode_index += MAX_MACHINE_MODE ; if ( types [ mode_index ] == NULL_TREE ) types [ mode_index ]

= build_vector_type_for_mode ( type , mode ) ;


<s> NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineMemOperand * MMO = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; if ( auto * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { if ( AllowIncDec && ( ! Subtarget . slowIncDec ( ) || DAG . getMachineFunction ( ) . getFunction ( ) -> optForSize ( ) ) ) { if ( ( NewOpc == <STR_LIT> && C -> isOne ( ) ) || ( NewOpc == <STR_LIT> && C -> isAllOnesValue ( ) ) ) return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } , N -> getSimpleValueType ( <NUM_LIT> ) , MMO ) ; if ( ( NewOpc == <STR_LIT> && C -> isOne ( ) ) || ( NewOpc == <STR_LIT> && C -> isAllOnesValue ( ) ) ) return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) }


<s> return ( int32x4_t ) __builtin_neon_vld1_dupv4si ( ( const


<s> if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF && read_only_operand ( x , VOIDmode ) ) output_addr_const ( file , x ) ; else if ( GET_CODE ( x ) == SYMBOL_REF && ! flag_pic ) { output_addr_const ( file , x ) ; fputs ( <STR_LIT> , file ) ; } else if ( GET_CODE ( x ) == CONST ) { const char * sep = <STR_LIT> ; int offset = <NUM_LIT> ; rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file ,


<s> basic_block * body , bb ; body = get_loop_body ( loop ) ; for ( unsigned i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) { bb = body [ i ] ; FOR_BB_INSNS ( bb , insn ) { rtx base = NULL_RTX ; rtx dest = NULL_RTX ; rtx offset = NULL_RTX ; bool writeback = false ; bool ldp = false ; if ( ! INSN_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( get_load_info ( insn , loop , & dest , & base , & offset , & writeback , & ldp ) ) { tag_insn_info * i = new tag_insn_info ( insn , dest , base , offset , writeback , ldp ) ; rtx tag = GEN_INT ( i -> tag ( ) ) ; tag_map . get_or_insert ( tag ) . safe_push ( i ) ; } } } if ( dump_file


<s> * ( __mmask8 * ) __A = __builtin_ia32_kmovb


<s> static <ISA_LIT>Operand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc


<s> void Filler :: insertDefsUses ( MachineBasicBlock :: iterator MI , SmallSet < unsigned , <NUM_LIT> > & RegDefs , SmallSet < unsigned , <NUM_LIT> > & RegUses ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands (


<s> default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : return true ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; default : return false ; } } ; int Op = <NUM_LIT> ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = <NUM_LIT> ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true


<s> IsQRegs = false ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = false ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned BeginIdx = IsQRegs ? <STR_LIT> : <STR_LIT> ; int Spacing = <NUM_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( SubRegs - <NUM_LIT> ) ; Spacing = - <NUM_LIT> ; } unsigned Opc = IsQRegs ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst


<s> gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ; rtx reg = force_reg ( VNx16BImode , CONST0_RTX ( VNx16BImode


<s> VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( Align . value ( ) - <NUM_LIT> , DL , VAList . getValueType ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align . value ( ) , DL , VAList . getValueType ( ) ) ) ; } auto & TD = DAG . getDataLayout ( ) ; unsigned ArgSizeInBytes = TD . getTypeAllocSize ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( alignTo ( ArgSizeInBytes , ArgSlotSizeInBytes ) , DL , VAList . getValueType ( ) ) ) ; Chain = DAG . getStore ( VAListLoad . getValue ( <NUM_LIT> ) , DL , Tmp3 , VAListPtr , MachinePointerInfo ( SV ) ) ; if ( ! Subtarget . isLittle ( ) && ArgSizeInBytes <


<s> static inline __ev64_opaque__ __internal_ev_mwhumiaaw ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNsu ( const SDNode *


<s> return __builtin_mve_vmlaldavq_uv4si ( __a ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DL ( Subtarget . getDataLayoutString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo (

* this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> return RetCC_<ISA_LIT>_APCS_Custom_f64 ( ValNo , ValVT , LocVT , LocInfo


<s> * low_in1 = gen_lowpart ( DImode , op1 ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode ) ; * high_in1 = gen_highpart ( DImode , op1


<s> if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB


<s> O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ; O << <STR_LIT> << getFunctionNumber ( )


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> default : llvm_unreachable ( <STR_LIT> ) ; } unsigned CPI = getCombinedIndex ( CPEMI ) ; assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; return MCP -> getConstants ( ) [ CPI ]


<s> bundle_pos ++ ; } if ( GET_CODE ( insn ) != CODE_LABEL ) b = bundle + INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; else b = <NUM_LIT> ; bundle_pos = <NUM_LIT> ; continue ; } else if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , <NUM_LIT> ) == <NUM_LIT> ) { int t = INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; if ( b ) while ( bundle_pos < t ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( bundle_pos == <NUM_LIT> ) b = <NUM_LIT> ; if ( b && INSN_P ( insn ) ) { t = ia64_safe_type ( insn )


<s> return __builtin_mve_vcaddq_rot90_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a ,


<s> bool hasCMov ( ) const { return HasCMov


<s> static bool hasVirtualRegDefsInBasicBlock ( const MachineInstr & Inst , const MachineBasicBlock * MBB ) { const MachineOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op2 = Inst . getOperand ( <NUM_LIT> ) ; const MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * MI1 = nullptr ; MachineInstr * MI2 = nullptr ; if ( Op1 . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Op1 . getReg ( ) ) ) MI1 = MRI . getUniqueVRegDef ( Op1 . getReg ( ) ) ; if ( Op2 . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Op2 . getReg ( ) ) ) MI2 = MRI . getUniqueVRegDef ( Op2 . getReg ( ) ) ; if ( MI1 && MI2 && MI1 -> getParent ( ) == MBB && MI2 -> getParent ( ) == MBB ) return true ; return


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : PN -> ops ( ) ) { if ( ! ToPromote . count ( V . getNode ( ) ) && V . getValueType ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V ) ) { SDValue ReplOpOps [ ] = { ISR . getOperand ( <NUM_LIT> ) , V , ISR . getOperand ( <NUM_LIT> ) } ; SDNode * ReplOp = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( V ) , ISR . getNode ( ) -> getVTList ( ) , ReplOpOps ) ; Ops . push_back ( SDValue ( ReplOp , <NUM_LIT> ) ) ; } else { Ops . push_back ( V ) ; } } SmallVector < EVT , <NUM_LIT> > NewVTs ; SDVTList VTs = PN -> getVTList ( ) ; for ( unsigned i = <NUM_LIT> , ie = VTs . NumVTs ; i != ie ; ++ i ) if ( VTs . VTs [ i ] == <STR_LIT> ) NewVTs . push_back ( <STR_LIT> ) ; else NewVTs . push_back ( VTs . VTs [ i ] ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; CurDAG -> SelectNodeTo ( PN , NewOpcode , CurDAG -> getVTList ( NewVTs ) , Ops ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs (


<s> } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == <NUM_LIT> && AM . IndexReg . getNode ( ) == <NUM_LIT> && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> bool <ISA_LIT>InstPrinter :: printAlias ( const MCInst * MI ,


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( TheThumbLETarget ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B (


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


<s> bool shouldBuildLookupTables ( ) const { return false


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( C ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * C ; errs ( ) << '\n' ; } ) ; switch ( C -> getValueID ( ) ) { default : { llvm_unreachable ( <STR_LIT> ) ; break ; } case Value :: GlobalVariableVal : { emitGlobalAddress ( static_cast < const GlobalValue * > ( C ) , <STR_LIT> , isa < Function > ( C ) , false ) ; emitWordLE ( <NUM_LIT> ) ; break ; } case Value :: ConstantIntVal : { const ConstantInt * CI = static_cast < const ConstantInt * > ( C ) ; uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val


<s> unsigned getPrefetchDistance ( ) const override { return PrefetchDistance


<s> static bool DisassembleThumb2LdStMul ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( Thumb2SRSOpcode ( Opcode ) ) return DisassembleThumb2SRS ( MI , Opcode , insn , NumOps , NumOpsAdded ) ; if ( Thumb2RFEOpcode ( Opcode ) ) return DisassembleThumb2RFE ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; NumOpsAdded = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++


<s> HOST_WIDE_INT vnum = exact_div ( addr . const_offset , BYTES_PER_SVE_PRED ) . to_constant ( ) ; asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , vnum ) ; } else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , INTVAL ( addr . offset ) ) ; return true ; case ADDRESS_REG_REG : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , reg_names [ REGNO ( addr . offset ) ] ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , reg_names [ REGNO ( addr . offset ) ] , addr . shift ) ; return true ; case ADDRESS_REG_UXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return true ; case ADDRESS_REG_SXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return true ; case ADDRESS_REG_WB : size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; switch ( GET_CODE ( x ) ) { case PRE_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case POST_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case PRE_DEC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case POST_DEC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case PRE_MODIFY : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , INTVAL ( addr . offset ) ) ; return true ; case POST_MODIFY : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , INTVAL ( addr . offset ) ) ; return true ; default : break ; } break ; case ADDRESS_LO_SUM : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] ) ; output_addr_const ( f , addr


<s> if ( Subtarget . hasP9Altivec ( ) ) { Reduced = combineBVOfVecSExt ( N , DAG ) ; if ( Reduced ) return Reduced ; } if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != <STR_LIT> && FirstInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) return SDValue ( ) ; SDValue Ext1 = FirstInput . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT> ) ; auto NodeType = ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT>


<s> return ( Kind == k_Register && Reg . Kind


<s> SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; KnownBits Known ; DAG . computeKnownBits ( SubusLHS , Known ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc


<s> if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Amt ) ) if ( auto * AmtSplat = AmtBV -> getConstantSplatNode ( ) ) { APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; } return SDValue (


<s> int64_t Size ; if ( parseImmExpr ( Size ) ) return


<s> default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> unsigned Op = Win64EH :: UOP_AllocSmall ; if ( ! Wide ) { if ( Size / <NUM_LIT> > <NUM_LIT> ) Op = Win64EH :: UOP_AllocHuge ; else if ( Size / <NUM_LIT> > <NUM_LIT> ) Op = Win64EH :: UOP_AllocLarge ; } else { Op = Win64EH :: UOP_WideAllocMedium ; if ( Size / <NUM_LIT> > <NUM_LIT> ) Op = Win64EH


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : ELF<ISA_LIT>AsmBackend ( T , TT , _OSABI ) { State . SaveCount = <NUM_LIT> ; State . I


<s> } else if ( Subtarget -> isThumb2 ( ) ) { if ( isC && Predicate_t2_so_imm ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( isC && Predicate_imm0_4095 ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { SP , Size , getI32Imm ( <STR_LIT>


<s> return _mm_set_epi32 ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ( *


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) return printS16ImmOperand ( MI , OpNo , O ) ; if ( MI -> getOperand ( OpNo ) . isExpr ( ) && isa < MCBinaryExpr > ( MI

-> getOperand ( OpNo ) . getExpr ( ) ) ) {


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI -> hasVarSizedObjects (


<s> const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( I -> getReg ( ) , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } uint64_t StackSize = <NUM_LIT> * <NUM_LIT> ; MF . getFrameInfo ( ) . setStackSize ( StackSize ) ; unsigned StackReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg (

<STR_LIT> ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , RegSaveReg ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , <NUM_LIT> ) . addOperand ( Segment ) . setMemRefs ( MMOBegin , MMOEnd ) ; unsigned OffsetReg64 = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , OffsetReg64 ) . addImm ( <NUM_LIT> ) . addReg ( OffsetReg ) . addImm ( <STR_LIT> ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , OffsetDestReg ) . addReg ( OffsetReg64 ) . addReg ( RegSaveReg ) ; unsigned NextOffsetReg = MRI . createVirtualRegister ( OffsetRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , NextOffsetReg ) . addReg ( OffsetReg ) . addImm ( UseFPOffset ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , UseFPOffset ? <NUM_LIT> : <NUM_LIT> ) . addOperand ( Segment ) . addReg ( NextOffsetReg ) . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( endMBB ) ; } unsigned OverflowAddrReg = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( overflowMBB , DL , TII -> get ( <STR_LIT> ) , OverflowAddrReg ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , <NUM_LIT> ) . addOperand ( Segment ) . setMemRefs ( MMOBegin , MMOEnd ) ; if ( NeedsAlign ) { assert ( ( Align & ( Align - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( overflowMBB , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( OverflowAddrReg ) . addImm ( Align - <NUM_LIT> ) ; BuildMI ( overflowMBB , DL , TII -> get ( <STR_LIT> ) , OverflowDestReg ) . addReg ( TmpReg ) . addImm ( ~ ( uint64_t ) ( Align - <NUM_LIT> ) ) ; }


<s> m_psdata -> setSectionData ( sd ) ; } sd = m_psdata -> getSectionData ( ) ; moveSectionData ( * pSection . getSectionData ( ) , * sd ) ; } else if ( pSection . type ( ) == llvm :: ELF :: SHT_MIPS_ABIFLAGS ) { } else { ObjectBuilder builder (


<s> int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode


<s> assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> - Val , getContext ( ) ) , S , E , * this ) ) ; return


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT ,

CPU , FS , * this , isLittle ) , isLittle ( isLittle ) {


<s> SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; auto & TD = DAG . getDataLayout ( ) ; EVT PTy = getPointerTy ( TD ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , DL , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const override { return


<s> } return ; } if ( frame_pointer_needed ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> use_eh_return_p ) { Rb = cfun -> machine -> eh_return_data_first_regno ; Re = cfun -> machine ->


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister


<s> bool <ISA_LIT>Subtarget :: enableMachinePipeliner ( )


<s> if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) . addMemOperand ( MMO ) ; else { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } return DestReg


<s> assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT>


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OS . write ( <STR_LIT> , <NUM_LIT> ) ; return true


<s> if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( <NUM_LIT> ) ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( isOSWindows ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT>


<s> if ( MEM_P ( x ) && GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ( SCALAR_FLOAT_MODE_P ( GET_MODE ( x ) ) || targetm . vector_mode_supported_p ( GET_MODE ( x ) ) ) && ! aarch64_pcrelative_literal_loads ) { sri -> icode = aarch64_constant_pool_reload_icode ( mode ) ; return NO_REGS ; } if ( REG_P ( x ) && ( mode == TFmode || mode == TImode ) && mode == GET_MODE ( x ) && FP_REGNUM_P ( REGNO ( x ) ) && ! TARGET_SIMD && reg_class_subset_p ( rclass , FP_REGS ) ) { if ( mode == TFmode ) sri -> icode = CODE_FOR_aarch64_reload_movtf ; else if ( mode == TImode ) sri -> icode = CODE_FOR_aarch64_reload_movti ; return NO_REGS ; } if ( TARGET_FLOAT && rclass == GENERAL_REGS && GET_MODE_SIZE ( mode ) == <NUM_LIT> && MEM_P ( x ) ) return FP_REGS ; if ( rclass == FP_REGS && ( mode == TImode || mode == TFmode ) && CONSTANT_P ( x ) ) return GENERAL_REGS ; return NO_REGS


<s> int nregs = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int total = <NUM_LIT> ; while ( nregs -- > <NUM_LIT> ) { HOST_WIDE_INT low = sext_hwi ( value , BITS_PER_WORD ) ; int insns = num_insns_constant_gpr ( low ) ; if ( insns > <NUM_LIT> && rs6000_is_valid_and_mask ( GEN_INT ( low ) , DImode ) )


<s> return ImplicitItMode == ImplicitItModeTy :: Always || ImplicitItMode


<s> return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; Instruction * I = cast < Instruction > ( U . getUser ( ) ) ; Value * BackToBool = new TruncInst ( IntRetVal , Int1Ty , <STR_LIT> , I ) ; U . set ( BackToBool ) ; return true


<s> return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr (


<s> AI . isValid ( ) ; ++ AI ) if ( RegSet . test ( * AI ) ) return true ; return false


<s> if ( r -> type == ERT_CLEANUP ) flags


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; const StringRef & ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsl ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex (


<s> for ( auto & MBB : MF ) if ( processMachineBasicBlock ( MBB ) ) Changed = true ; return


<s> FrameReg = <STR_LIT> ; return FrameOffset + MF . getFrameInfo ( )


<s> return ( MFI -> hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || MFI -> hasVarSizedObjects ( )

|| MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ;


<s> unsigned SrcRegNum = <ISA_LIT>_MC :: get<ISA_LIT>RegNum ( MI . getOperand ( OpNum ) . getReg ( ) ) ; if ( <STR_LIT> ( SrcReg ) )


<s> node_version_info = node -> function_version ( ) ; gcc_assert ( node -> dispatcher_function && node_version_info != NULL ) ; if ( node_version_info -> dispatcher_resolver ) return node_version_info -> dispatcher_resolver ; default_ver_decl = node_version_info -> next -> this_node -> decl ; node -> definition = false ; resolver_decl = make_resolver_func ( default_ver_decl , node -> decl , & empty_bb ) ; node_version_info -> dispatcher_resolver = resolver_decl ; push_cfun ( DECL_STRUCT_FUNCTION ( resolver_decl ) ) ; auto_vec < tree , <NUM_LIT> > fn_ver_vec ; for ( versn_info = node_version_info -> next ; versn_info ; versn_info = versn_info -> next ) { versn = versn_info -> this_node ; if ( DECL_VINDEX ( versn -> decl ) ) sorry (


<s> static std :: string computeDataLayout


<s> Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitThumbRegPlusImmediate ( MBB , II , dl , DestReg , FrameReg , Offset , TII , * this ) ; MBB . erase ( II ) ; return true ; } else { if ( AddrMode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned ImmIdx = FrameRegIdx + <NUM_LIT> ; int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; unsigned NewOpc = convertToNonSPOpcode


<s> bool <ISA_LIT>DAGToDAGISel :: tryFoldLoad ( SDNode * Root , SDNode * P , SDValue N , SDValue & Base , SDValue & Scale , SDValue &

Index , SDValue & Disp , SDValue & Segment ) {


<s> static SDValue LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op5 = Op . getOperand ( <NUM_LIT> ) ; SDValue Res ; unsigned isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) -> getZExtValue ( ) ; if ( isDeviceBarrier ) { if ( Subtarget -> hasV7Ops ( ) ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ,

DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> static void emit<ISA_LIT>Nops ( MCStreamer & OS , unsigned NumBytes , const <ISA_LIT>Subtarget * Subtarget ) { unsigned NopsToEmit = NumBytes ; ( void ) NopsToEmit ; while ( NumBytes


<s> static rtx aarch64_struct_value_rtx ( tree fndecl ATTRIBUTE_UNUSED , int incoming


<s> if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false


<s> const DataLayout * getDataLayout ( ) const override


<s> static const char * isa_str ( const struct loongarch_isa * isa , char separator ) { APPEND_STRING ( loongarch_isa_base_strings [ isa -> base ] ) APPEND1 ( separator ) if ( isa -> fpu == ISA_EXT_NOFPU ) { APPEND_STRING ( <STR_LIT> OPTSTR_ISA_EXT_FPU ) } else { APPEND_STRING ( OPTSTR_ISA_EXT_FPU ) APPEND_STRING ( loongarch_isa_ext_strings [ isa


<s> } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; UndefElts = UndefElts [ <NUM_LIT> ] ; break ; case <STR_LIT> : case <STR_LIT> : simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; if ( ! UndefElts2 [ <NUM_LIT> ] ) UndefElts . clearBit ( <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { APInt DemandedElts2 = DemandedElts ; DemandedElts2 . clearBit ( <NUM_LIT> ) ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts2 , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; UndefElts . clearBit ( <NUM_LIT> ) ; UndefElts |= UndefElts2 [ <NUM_LIT> ] ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts3 ) ; if ( ! UndefElts2 [ <NUM_LIT> ] || ! UndefElts3 [ <NUM_LIT> ] ) UndefElts . clearBit ( <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto * Ty0 = II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; unsigned InnerVWidth = cast < FixedVectorType > ( Ty0 ) -> getNumElements ( ) ; assert ( VWidth == ( InnerVWidth * <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = Ty0 -> getPrimitiveSizeInBits ( ) /


<s> bool <ISA_LIT>AsmPrinter :: isLongBranchPseudo ( int Opcode )


<s> return false ; } bool IsFP = ScalarRB -> getID ( ) == <STR_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsFP ] [ EltTy . getSizeInBits ( ) == <NUM_LIT> ] ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , & <STR_LIT> , ScalarReg , MIB ) ; if ( ! Widen ) return false ; ScalarReg = Widen -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } auto Dup = MIB . buildInstr ( Opc , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { ScalarReg } ) ; if ( IsFP ) Dup . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Dup , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> drap_ok = drap_ok && drap_align >= align_reqested ; sp_ok = sp_ok && sp_align >= align_reqested ; } if ( m -> use_fast_prologue_epilogue ) { if ( hfp_ok ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = <NUM_LIT> - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = <NUM_LIT> - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len = tlen


<s> TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; RTLIB :: Libcall LC = isF64 ? RTLIB :: SINCOS_STRET_F64 : RTLIB :: SINCOS_STRET_F32 ; const char * LibcallName = TLI . getLibcallName ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy ) : ( Type * ) FixedVectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> == <NUM_LIT> ) ; Reg >>= <NUM_LIT> ; } } else if ( Prefix == <STR_LIT> )


<s> return ( int16x8_t ) __builtin_neon_vrshrs_nv8hi (


<s> char * newsym ; char * p ; tree formal_type ; if ( * asmname == '*' || strchr ( asmname , '@' ) ) return DECL_ASSEMBLER_NAME ( decl ) ; formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return DECL_ASSEMBLER_NAME ( decl ) ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { int parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - <NUM_LIT> ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total +=


<s> if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return true ; return


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( LO32 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT>

) . addReg ( <STR_LIT> ) . addImm ( HI32 ( NumBytes ) ) ;


<s> int AltOpc = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( AltOpc == - <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2


<s> unsigned <STR_LIT> ( SDNode * N ) { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ;


<s> TargetLoweringObjectFile * getObjFileLowering (


<s> __builtin_ia32_incsspq ( ( unsigned long long ) __B ) ; __builtin_ia32_incsspd ( __B )


<s> return DEFAULT_ABI == ABI_DARWIN && ( sel & SAVRES_REG ) == SAVRES_FPR ?


<s> static bool sh_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_SHMEDIA32 && mode == TImode ) return false ; return default_scalar_mode_supported_p (


<s> if ( hasFP ( MF ) ) { int FrameIdx = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> ,


<s> FunctionPass * llvm :: create<ISA_LIT>MemAluCombinerPass ( ) { return new <ISA_LIT>MemAluCombiner (


<s> case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: isJumpTableRelative ( ) const { if ( Subtarget . is<ISA_LIT>64 ( ) ) return true ; return TargetLowering :: isJumpTableRelative (


<s> if ( Imm & ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) ) Imm |= ~ ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue InVec = N -> getOperand ( <NUM_LIT> ) ; SDValue EltNo = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( EltNo ) ) return SDValue ( ) ; EVT OriginalVT = InVec . getValueType ( ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! BCVT . isVector ( ) || BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = DAG . getDataLayout ( ) . getABITypeAlignment ( EltVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( NewAlign > Align || ! TLI . isOperationLegalOrCustom ( <STR_LIT> , EltVT ) ) return SDValue ( ) ; SDLoc dl ( N


<s> void addVectorRegLoOperands ( MCInst & Inst


<s> assert ( <NUM_LIT> ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { assert ( <NUM_LIT> ) ; } else { O << getRegisterName ( Reg ) ; } } else if ( Op . isImm ( ) ) { assert ( ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) || ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ) ; O << '#' << Op . getImm ( ) ; } else { if ( Modifier && Modifier [ <NUM_LIT> ] != <NUM_LIT> && strcmp ( Modifier , <STR_LIT> ) != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; assert ( Op . isExpr ( )


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } } if ( Op . getOpcode ( ) != <STR_LIT> || ! Op . hasOneUse ( ) ) return SDValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; unsigned NewOpc ; switch ( Op . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( needCarryOrOverflowFlag ( SDValue ( N , <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( needCarryOrOverflowFlag ( SDValue ( N , <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; } SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( NewOpc , dl


<s> Inst . addOperand ( MCOperand :: CreateReg ( getPtrReg ( ) )


<s> switch ( Opcode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> MCSymbol * TlsGetAddr = OutContext . getOrCreateSymbol ( Name ) ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( Subtarget -> is32BitELFABI ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; if ( Kind == MCSymbolRefExpr :: VK_PLT && Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC ) TlsRef = MCBinaryExpr :: createAdd ( TlsRef ,

MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ;


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info


<s> case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case FK_Data_8 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets [ SpillOffsetTable

[ I ] . Reg ] = SpillOffsetTable [ I ] . Offset ;


<s> case ldexp_optab : case scalb_optab : case round_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_ROUND ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && TARGET_ROUND ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return


<s> case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_VK1 : case TYPE_VK2 : case TYPE_VK4 : case TYPE_VK8 : case TYPE_VK16 : case TYPE_VK32 : case TYPE_VK64 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : case TYPE_BNDR : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case


<s> static bool ShuffleCrosses128bitLane ( MVT VT , unsigned InputIdx , unsigned OutputIdx


<s> const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isDarwin ( ) ) { return new <ISA_LIT>DarwinAsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , fast ) ; } else { return new <ISA_LIT>LinuxAsmPrinter ( o , tm , tm .


<s> static SDValue LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) { EVT OpVT = Op . getValueType ( ) ; if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op


<s> MCSection * <ISA_LIT>ElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst ,


<s> case <STR_LIT> : return ELF :: R_390_PLT12DBL ; case <STR_LIT> : return ELF :: R_390_PLT16DBL ; case <STR_LIT> : return ELF :: R_390_PLT24DBL ; case <STR_LIT> : return ELF


<s> TD = Target . getDataLayout ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> unsigned Reg = Op . getReg ( ) ; assert ( Op . Reg . Kind == rk_FloatReg ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Op . Reg . RegNum = DoubleRegs [ regIdx / <NUM_LIT>


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( TLI . verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; return RetAddr ; } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG ,


<s> DenseSet < unsigned > KilledRegs ; DenseSet < unsigned > UsedRegs ; for ( const MachineInstr * MI : Cand . Instrs ) { const MachineOperand & MO = getLoadStoreRegOp ( * MI ) ; unsigned Reg = MO . getReg ( ) ; bool IsKill = MO . isKill ( ) ; if ( IsKill ) KilledRegs . insert ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , IsKill ) ) ; UsedRegs . insert ( Reg ) ; if ( IsLoad ) { for ( const MachineOperand & MO : MI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isDead ( ) ) continue ; assert ( MO . isImplicit ( ) ) ; unsigned DefReg = MO . getReg ( ) ; if ( is_contained ( ImpDefs , DefReg ) ) continue ; if ( MI -> readsRegister ( DefReg ) ) continue ; ImpDefs . push_back ( DefReg ) ; } } } typedef MachineBasicBlock :: iterator iterator ; MachineInstr * LatestMI = Cand . Instrs [ Cand . LatestMIIdx ] ; iterator InsertBefore = std :: next ( iterator ( LatestMI ) ) ; MachineBasicBlock & MBB = * LatestMI -> getParent ( ) ; unsigned Offset = getMemoryOpOffset ( * First ) ; unsigned Base = getLoadStoreBaseOp ( * First ) . getReg ( ) ; bool BaseKill = LatestMI -> killsRegister ( Base ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; }


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return Success


<s> MCSymbol * <ISA_LIT>AIXAsmPrinter :: getMCSymbolForTOCPseudoMO ( const MachineOperand & MO ) { const GlobalObject * GO = nullptr ; if ( MO . getType ( ) != MachineOperand :: MO_GlobalAddress || ! ( GO = dyn_cast < const GlobalObject > ( MO . getGlobal ( ) ) ) ) return <ISA_LIT>AsmPrinter :: getMCSymbolForTOCPseudoMO ( MO ) ; const auto * GV = dyn_cast < const GlobalVariable > ( GO ) ; if ( GV ) { ValidateGV ( GV ) ; } MCSymbolXCOFF * XSym = cast < MCSymbolXCOFF > ( getSymbol ( GO ) ) ; if ( GO -> isDeclaration


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk


<s> Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> MachineInstr * <ISA_LIT>CallFrameOptimization :: canFoldIntoRegPush ( MachineBasicBlock :: iterator FrameSetup , unsigned Reg ) { if ( ! Register :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr & DefMI = * MRI -> getVRegDef ( Reg ) ; if ( ( DefMI . getOpcode ( ) != <STR_LIT> && DefMI . getOpcode ( ) != <STR_LIT> ) || DefMI . getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ; for ( MachineBasicBlock :: iterator I = DefMI ; I != FrameSetup ; ++ I ) if ( I -> isLoadFoldBarrier (


<s> static void emitThumb2LoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool