<s> fma_root_node :: fma_root_node ( func_fma_steering * globals , du_chain * chain , int id ) : fma_node ( this , chain ) { this -> m_forest = new fma_forest ( globals , this , id ) ; this -> m_forest -> fma_node_created


<s> if ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_ELF || TARGET_MACHO ) { bool large_toc_ok ; if ( DEFAULT_ABI == ABI_V4 && flag_pic ) return false ; large_toc_ok = ( lra_in_progress && TARGET_CMODEL != CMODEL_SMALL && small_toc_ref ( x , VOIDmode ) ) ; if ( TARGET_TOC && ! large_toc_ok ) return false ; if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ; return CONSTANT_P ( x


<s> unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB


<s> NonceMask . push_back ( <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , NonceMask , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget . hasBMI ( ) && ! Subtarget . hasTBM ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> && N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue (


<s> char cmse_prefix [ ] = <STR_LIT> ; if ( use_cmse && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) { cmse_name_len = sizeof ( cmse_prefix ) + strlen ( name ) ; cmse_name = XALLOCAVEC ( char , cmse_name_len ) ; snprintf ( cmse_name , cmse_name_len , <STR_LIT> , cmse_prefix , name ) ; targetm . asm_out . globalize_label ( file , cmse_name ) ; ARM_DECLARE_FUNCTION_NAME ( file , cmse_name , decl ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , cmse_name , <STR_LIT> ) ; } ARM_DECLARE_FUNCTION_NAME ( file , name , decl ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; ASM_OUTPUT_LABEL ( file , name ) ; if ( cmse_name ) ASM_OUTPUT_LABEL ( file , cmse_name ) ; ARM_OUTPUT_FN_UNWIND ( file , TRUE


<s> return DAG . getAnyExtOrTrunc ( Extract , DL , Op . getValueType ( ) ) ; } if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerFixedLengthExtractVectorElt ( Op , DAG ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSet ( ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Parser . EatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Parser . EatToEndOfStatement ( ) ; return false ; } return true


<s> bool is64BitELFABI ( ) const { return isSVR4ABI ( ) && is<ISA_LIT>64 (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI ,


<s> static SmallPtrSet < Value * , <NUM_LIT> > findAllDefs ( Value * V ) { SmallPtrSet < Value * , <NUM_LIT> > Defs ; SmallVector < Value * , <NUM_LIT> > WorkList ; WorkList . push_back ( V ) ; Defs . insert ( V ) ; while ( ! WorkList . empty ( )


<s> } else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) || TheTriple . isWindowsItaniumEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst2 = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( InstPtr , true ) , stackGrowth ) ; MAI -> addInitialFrameState ( Inst2


<s> return __builtin_mve_vminq_m_sv16qi ( __arm_vuninitializedq_s8 ( ) ,


<s> if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align ,

Subtarget . hasQPX ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT>


<s> if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) ; unsigned int alignment = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; return alignment


<s> static bool Expand2AddrUndef ( MachineInstrBuilder & MIB , const MCInstrDesc & Desc ) { assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Register Reg = MIB -> getOperand (


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p =

strchr ( p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \ RS6000_OUTPUT_BASENAME ( FILE , buffer ) ; \ putc ( '\n' , FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc ,


<s> if ( Opnd0 . getOpcode ( ) != <STR_LIT> || Opnd0 -> use_size ( ) != <NUM_LIT> || ! Subtarget . hasAnyFMA ( ) ) return false ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; bool AllowFusion = ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ; if ( ! AllowFusion ) return false ; Opnd2 =


<s> enum machine_mode mode ; tree type = TREE_TYPE ( field ) ; if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ; mode = TYPE_MODE ( TREE_CODE ( type ) == ARRAY_TYPE ? get_inner_array_type ( type ) :


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) || ( VT . isVector ( ) && TLI . isTypeLegal ( VT ) ) ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( )

. getFunction ( ) . optForMinSize ( ) ) return SDValue ( ) ;


<s> static bool SupportedVectorShiftWithBaseAmnt ( MVT VT , const <ISA_LIT>Subtarget & Subtarget , unsigned Opcode ) { return SupportedVectorShiftWithImm ( VT , Subtarget


<s> } else if ( <STR_LIT> . contains ( Reg ) && Reg != <STR_LIT> ) { HiRegsToRestore . insert ( Reg ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( <STR_LIT> . contains ( Reg ) ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs . insert ( Reg ) ; } auto Terminator = MBB . getFirstTerminator ( ) ; if ( Terminator != MBB . end ( ) && Terminator -> getOpcode ( ) == <STR_LIT> ) { CopyRegs . insert ( <STR_LIT> ) ; CopyRegs . insert ( <STR_LIT> ) ; CopyRegs . insert ( <STR_LIT> ) ; CopyRegs . insert ( <STR_LIT> ) ; for ( auto Op : Terminator -> implicit_operands ( ) ) { if ( Op . isReg ( ) ) CopyRegs . erase ( Op . getReg ( ) ) ; } } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; auto HiRegToRestore = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToRestore , AllHighRegsEnd ) ; while ( HiRegToRestore != AllHighRegsEnd ) { assert ( ! CopyRegs . empty ( ) ) ; auto CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PopMIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; while ( HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { PopMIB . addReg ( * CopyReg , RegState :: Define ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( * HiRegToRestore , RegState :: Define ) . addReg ( * CopyReg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; CopyReg = findNextOrderedReg ( ++ CopyReg , CopyRegs , AllCopyRegsEnd ) ; HiRegToRestore = findNextOrderedReg ( ++ HiRegToRestore , HiRegsToRestore , AllHighRegsEnd ) ; } } MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; bool NeedsPop = false ; for ( unsigned i = CSI . size ( ) ; i


<s> if ( ST -> getMcpu ( ) == <STR_LIT> ) return true ; return


<s> return ( DisableFramePointerElim ( MF ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI


<s> if ( ! CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> && isVarArg ) { return


<s> switch ( c ) { ARM_NAME_ENCODING_LENGTHS default : return <NUM_LIT>


<s> bool <ISA_LIT>LongBranch :: runOnMachineFunction ( MachineFunction & F ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . in<ISA_LIT>16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . inMicro<ISA_LIT>Mode ( ) ? <NUM_LIT> : <NUM_LIT> ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { Offset *=


<s> Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) ) { assert ( MAI . doesSetDirectiveSuppressReloc ( ) ) ; MCSymbol * Label = Ctx . createTempSymbol ( ) ; AsmPrinter . OutStreamer -> EmitAssignment ( Label , Expr ) ; Expr = MCSymbolRefExpr :: create ( Label , Ctx ) ; } break ; } if ( ! Expr ) Expr = MCSymbolRefExpr :: create ( Sym , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr (


<s> SDValue Opnd2 ; if ( isFMAddSub ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; if ( VT . is512BitVector ( ) )


<s> static SDValue lowerVectorShuffleWithPACK ( const SDLoc & DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2

, SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) {


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumbFunction ( ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( AFI -> isThumbFunction ( ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; }


<s> return true ; } if ( isThumbTwo ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! inITBlock ( ) || ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) ) return true ; if ( isThumbTwo ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! inITBlock ( ) ) ) return true ; if ( isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && ( Operands . size ( ) == <NUM_LIT> || Operands . size ( ) == <NUM_LIT> ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <STR_LIT> && static_cast <

<ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) || ( Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) ) ) ) return true ;


<s> void <ISA_LIT>InstPrinterCommon :: printOptionalSegReg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getReg ( ) ) { printOperand ( MI , OpNo , O


<s> bool isTargetFreeBSD ( ) const { return TargetTriple . getOS ( ) ==


<s> unsigned Reg = Op . getReg ( ) ; assert ( Op . Reg . Kind == rk_CoprocReg ) ; unsigned regIdx = <NUM_LIT> ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx


<s> if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; const GlobalObject * GO = GV -> getAliaseeObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN64 ( ) ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( Subtarget . useXGOT ( ) ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> ,

DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; if ( ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) || ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) ) { if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , N0 ) ; SDValue ZeroVec = getZeroVector ( OpVT , Subtarget , DAG , dl ) ; SDValue OpLo = getUnpackl ( DAG , dl , OpVT , N0 , ZeroVec ) ; SDValue OpHi = getUnpackh ( DAG , dl , OpVT , N0 , ZeroVec ) ; EVT HVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType

( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ;


<s> builtin_mode_to_type [ SImode ] [ <NUM_LIT> ] = intSI_type_node ; builtin_mode_to_type [ SImode ] [ <NUM_LIT> ] = unsigned_intSI_type_node ; builtin_mode_to_type [ DImode ] [ <NUM_LIT> ] = intDI_type_node ; builtin_mode_to_type [ DImode ] [ <NUM_LIT> ] = unsigned_intDI_type_node ; builtin_mode_to_type [ TImode ] [ <NUM_LIT> ] = intTI_type_node ; builtin_mode_to_type [ TImode ] [ <NUM_LIT> ] = unsigned_intTI_type_node ; builtin_mode_to_type [ SFmode ] [ <NUM_LIT> ] = float_type_node ; builtin_mode_to_type [ DFmode ] [ <NUM_LIT> ] = double_type_node ; builtin_mode_to_type [ IFmode ] [ <NUM_LIT> ] = ibm128_float_type_node ; builtin_mode_to_type [ KFmode ] [ <NUM_LIT> ] = ieee128_float_type_node ; builtin_mode_to_type [ TFmode ] [ <NUM_LIT> ] = long_double_type_node ; builtin_mode_to_type [ DDmode ] [ <NUM_LIT> ] = dfloat64_type_node ; builtin_mode_to_type [ TDmode ] [ <NUM_LIT> ] = dfloat128_type_node ; builtin_mode_to_type [ V1TImode ] [ <NUM_LIT> ] = V1TI_type_node ; builtin_mode_to_type [ V1TImode ] [ <NUM_LIT> ] = unsigned_V1TI_type_node ; builtin_mode_to_type [ V2DImode ] [ <NUM_LIT> ] = V2DI_type_node ; builtin_mode_to_type [ V2DImode ] [ <NUM_LIT> ] = unsigned_V2DI_type_node ; builtin_mode_to_type [ V2DFmode ] [ <NUM_LIT> ] = V2DF_type_node ; builtin_mode_to_type [ V4SImode ] [ <NUM_LIT> ] = V4SI_type_node ; builtin_mode_to_type [ V4SImode ] [ <NUM_LIT> ] = unsigned_V4SI_type_node ; builtin_mode_to_type [ V4SFmode ] [ <NUM_LIT> ] = V4SF_type_node ; builtin_mode_to_type [ V8HImode ] [ <NUM_LIT> ] = V8HI_type_node ; builtin_mode_to_type [ V8HImode ] [ <NUM_LIT> ] = unsigned_V8HI_type_node ; builtin_mode_to_type [ V16QImode ] [ <NUM_LIT> ] = V16QI_type_node ; builtin_mode_to_type [ V16QImode ] [ <NUM_LIT> ] = unsigned_V16QI_type_node ; tdecl = add_builtin_type ( <STR_LIT> , bool_char_type_node ) ; TYPE_NAME ( bool_char_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , bool_short_type_node ) ; TYPE_NAME ( bool_short_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , bool_int_type_node ) ; TYPE_NAME ( bool_int_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , pixel_type_node ) ; TYPE_NAME ( pixel_type_node ) = tdecl ; bool_V16QI_type_node = rs6000_vector_type ( <STR_LIT> , bool_char_type_node , <NUM_LIT> ) ; bool_V8HI_type_node = rs6000_vector_type ( <STR_LIT> , bool_short_type_node , <NUM_LIT> ) ; bool_V4SI_type_node = rs6000_vector_type ( <STR_LIT> , bool_int_type_node , <NUM_LIT> ) ; bool_V2DI_type_node = rs6000_vector_type ( TARGET_POWERPC64 ? <STR_LIT> : <STR_LIT> , bool_long_long_type_node , <NUM_LIT> ) ; pixel_V8HI_type_node = rs6000_vector_type ( <STR_LIT> , pixel_type_node , <NUM_LIT> ) ; if ( TARGET_EXTRA_BUILTINS ) altivec_init_builtins ( ) ; if ( TARGET_HTM ) htm_init_builtins ( ) ; if ( TARGET_EXTRA_BUILTINS ) rs6000_common_init_builtins ( ) ; ftype = builtin_function_type ( DFmode , DFmode , DFmode , VOIDmode , RS6000_BUILTIN_RECIP , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RECIP ) ; ftype = builtin_function_type ( SFmode , SFmode , SFmode , VOIDmode , RS6000_BUILTIN_RECIPF , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RECIPF ) ; ftype = builtin_function_type ( DFmode , DFmode , VOIDmode ,

VOIDmode , RS6000_BUILTIN_RSQRT , <STR_LIT> ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Res ; SDValue X = ( TyX == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; SDValue Y = ( TyY == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) { SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , Const31 , Const1 , X ) ; } else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; SDValue SrlX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; SDValue SrlY = DAG . getNode ( <STR_LIT> ,


<s> const SDNodeFlags Flags = N -> getFlags ( ) ; if ( Flags . hasVectorReduction ( ) ) { if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; if ( SDValue MAdd = combineLoopMAddPattern ( N , DAG , Subtarget ) ) return MAdd ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( )

&& isHorizontalBinOp ( Op0 , Op1 , true ) && shouldUseHorizontalOp ( Op0 == Op1 , DAG , Subtarget ) ) {


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> bool isImmUnsignedi8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return isImmUnsignedi8Value ( CE ->


<s> unsigned <ISA_LIT>RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> -


<s> if ( ! CONST_INT_P ( x ) ) return false ; HOST_WIDE_INT val = INTVAL ( x ) ; if ( val & <NUM_LIT> ) return IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) ; return IN_RANGE ( val , -


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand ::

createImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: transformToNewImmFormFedByAdd ( MachineInstr & MI , MachineInstr & DefMI , unsigned OpNoForForwarding ) const { MachineRegisterInfo * MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; bool PostRA = ! MRI -> isSSA ( ) ; if ( PostRA ) return false ; if ( ! MI . mayLoadOrStore ( ) ) return false ; unsigned XFormOpcode = RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) ; assert ( ( XFormOpcode != <STR_LIT> ) && <STR_LIT> ) ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! instrHasImmForm ( XFormOpcode , IsVFReg , III , PostRA ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump (


<s> static bool isEAXLiveIn ( MachineFunction & MF ) { for ( MachineRegisterInfo :: livein_iterator II = MF . getRegInfo ( ) . livein_begin ( ) , EE = MF . getRegInfo ( ) . livein_end ( ) ; II != EE ; ++ II ) { unsigned Reg = II -> first ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) return true ; } return


<s> EmitW64Tables ( ) ; MCWinCOFFStreamer :: FinishImpl ( )


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; return


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; assert ( ( NumLaneElts == <NUM_LIT> || NumLaneElts == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Shift = ( NumLaneElts == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= NumLaneElts - <NUM_LIT> ; unsigned ShAmt = ( i << Shift ) % <NUM_LIT> ; Mask |= Elt << ShAmt ; } return


<s> Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState ::


<s> if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; Register LHSReg = getRegForValue ( LHS ) ; Register RHSReg = getRegForValue ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; Register ResultReg = fastEmitInst_rri ( Opc , RC , RHSReg


<s> return SegmentOffset ( IRB , <NUM_LIT> , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; unsigned Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == ( unsigned ) - <NUM_LIT> ) Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; auto GuardReg = getTargetMachine ( ) . Options .


<s> F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; int br_code ; switch ( Opc ) { case <STR_LIT> : br_code = <STR_LIT> ; break ; case <STR_LIT> : br_code = <STR_LIT> ; break ; default : br_code = <NUM_LIT> ; } BuildMI ( BB , dl , TII . get ( br_code ) ) . addMBB


<s> return ( __m256i ) __builtin_ia32_pshuflw256 ( ( __v16hi


<s> static SDValue PerformANDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t TruncMask = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ! isMask_64 ( TruncMask ) ) return SDValue ( ) ; uint64_t Width = CountPopulation_64 ( TruncMask ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift -> getOperand ( <NUM_LIT>


<s> MVT VT ; if ( ! isTypeSupported ( I -> getType ( ) , VT ) || UnsupportedFPMode ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned CondMovOpc ; const TargetRegisterClass * RC ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; Register Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; Register Src2Reg = getRegForValue ( SI -> getFalseValue ( ) ) ; Register CondReg = getRegForValue ( Cond ) ; if ( ! Src1Reg || ! Src2Reg || ! CondReg ) return false ; Register ZExtCondReg = createResultReg ( & <STR_LIT> ) ; if ( ! ZExtCondReg ) return false ; if ( ! emitIntExt ( <STR_LIT> , CondReg , <STR_LIT> , ZExtCondReg , true ) ) return false ; Register ResultReg = createResultReg ( RC ) ; Register TempReg = createResultReg ( RC ) ; if ( ! ResultReg || ! TempReg ) return


<s> if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString


<s> unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / <NUM_LIT> ; EVT ByteVT = EVT :: getVectorVT ( Ctx , <STR_LIT> , { ByteSize , true } ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ElemSize , dl , <STR_LIT> ) ) ; SDValue EXT = DAG . getNode ( <STR_LIT> , dl , ByteVT , Op0


<s> if ( ! Subtarget -> hasAVX ( ) ) return false ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || NumElts != <NUM_LIT> ) return false ; int LaneSize = NumElts / NumLanes ; for ( int l = <NUM_LIT> ; l < NumLanes ; ++ l ) for ( int i = l * LaneSize ; i < LaneSize * ( l + <NUM_LIT> ) ; ++ i ) { int LaneStart = l * LaneSize ; if ( ! isUndefOrInRange ( Mask [ i ] ,

LaneStart , LaneStart + LaneSize ) ) return false ;


<s> const MCConstantExpr * ConstExp = nullptr ; if ( const MCBinaryExpr * BinExpr = dyn_cast < MCBinaryExpr > ( Op . getExpr ( ) ) ) { RefExp = cast < MCSymbolRefExpr > ( BinExpr -> getLHS ( ) ) ; ConstExp = cast < MCConstantExpr > ( BinExpr -> getRHS ( ) ) ; } else RefExp = cast < MCSymbolRefExpr > ( Op


<s> else if ( CM == CodeModel :: JITDefault ) CM = CodeModel :: Large ; else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ; if ( TT . isOSDarwin ( ) ) RM = Reloc :: PIC_ ; else if ( RM == Reloc :: Default || RM == Reloc :: DynamicNoPIC ) RM = Reloc :: Static ; MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue ARMcc ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , dl , DAG ) ; SDValue CCVal = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp3 , FalseVal , CCVal , Cmp ) ; SDValue TrueValLo = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue FalseValLo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , TrueValLo , FalseValLo , CCVal , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl


<s> for ( auto * U : Vec -> uses ( ) ) { if ( U != Op0 . getNode ( ) && U -> hasOneUse ( ) && U -> getOpcode ( ) == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) == Vec && U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue OtherExtend = SDValue ( * U -> use_begin ( ) , <NUM_LIT> ) ; if ( OtherExtend . getOpcode ( ) == N -> getOpcode ( ) && OtherExtend . getOperand ( OpNo ) == SDValue ( U , <NUM_LIT> ) && OtherExtend . getValueType ( ) == <STR_LIT> ) { SDValue VExtend , Chain ; if ( N -> isStrictFPOpcode ( ) ) { Chain = MergeInputChains ( N , OtherExtend . getNode ( ) ) ; if ( ! Chain ) continue ; VExtend = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , { <STR_LIT> , <STR_LIT> } , { Chain , Vec } ) ; Chain = VExtend . getValue ( <NUM_LIT> ) ; } else VExtend = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Vec ) ; DCI . AddToWorklist ( VExtend . getNode ( ) ) ; SDValue Extract1 = DAG . getNode ( <STR_LIT> , SDLoc ( U ) , <STR_LIT> , VExtend , DAG . getConstant ( <NUM_LIT> , SDLoc ( U ) , <STR_LIT> ) ) ; DCI . AddToWorklist ( Extract1 . getNode ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( OtherExtend , Extract1 ) ; if ( Chain ) DAG . ReplaceAllUsesOfValueWith ( OtherExtend . getValue ( <NUM_LIT> ) , Chain ) ; SDValue Extract0 = DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , <STR_LIT> , VExtend , DAG . getConstant ( <NUM_LIT> , SDLoc ( Op0 ) , <STR_LIT> ) ) ; if ( Chain ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , N -> getVTList ( ) , Extract0 , Chain ) ; return Extract0


<s> return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Blend = lowerShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getTargetConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsLowZero ) && ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsHighZero ) && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V2 = DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getTargetConstant


<s> bool IsF128 = ( VT == <STR_LIT> ) ; assert ( VT . isFloatingPoint ( ) && VT != <STR_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && <STR_LIT> ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue SignMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignMask ( EltSizeInBits ) ) , dl , LogicVT ) ; SDValue MagMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignedMaxValue ( EltSizeInBits ) ) , dl , LogicVT ) ; if ( IsFakeVector ) Sign = DAG . getNode ( <STR_LIT> ,


<s> static void build_sv_index ( function_builder & b , const char * signature , const function_group_info


<s> bool IsDouble = Op . getValueType ( ) == <STR_LIT> ; ConstantFPSDNode * CFP = cast < ConstantFPSDNode > ( Op ) ; if ( IsDouble && Subtarget -> isFPOnlySP ( ) ) return SDValue ( ) ; const APFloat & FPVal = CFP -> getValueAPF ( ) ; int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt


<s> Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl (


<s> if ( __GTHR_W32_InterlockedCompareExchange ( & mutex -> counter , <NUM_LIT> , - <NUM_LIT> ) < <NUM_LIT>


<s> StringRef FPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( FPU ) ; std :: vector < const char * > Features ; if ( ! <STR_LIT> ( ID , Features ) ) { Error ( FPUNameLoc , <STR_LIT> ) ; return false


<s> unsigned int fsr ; __asm__ ( <STR_LIT> : <STR_LIT> ( fsr ) ) ; fsr |= FPRS_NS ; __asm__ ( <STR_LIT> : : <STR_LIT> ( fsr


<s> bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , MinSplatBits , HasAnyUndefs ) ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT , N0 , Sz , DAG ) ; SDValue Amt = DAG . getConstant ( EltTy . getSizeInBits ( ) - lg2 , <STR_LIT> ) ; SDValue SRL = getTargetVShiftNode ( <STR_LIT> , dl , VT , SGN , Amt , DAG ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { APInt AllBits = APInt :: getNullValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = canonicalizeBitSelect ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineOrShiftToFunnelShift ( N , DAG


<s> if ( ! getNumWinFrameInfos ( ) ) return ; EHStreamer . Emit (


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: restoreEFLAGS ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt ,


<s> status = DecodeAS ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( cy && ! isImmOnly ) { status = DecodeSX ( MI , sy , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { if ( isUImm ) MI . addOperand ( MCOperand :: createImm ( sy ) ) ; else MI . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( sy ) ) ) ; } status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return


<s> DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred (


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) || isUInt <


<s> OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( )


<s> snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s


<s> if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86 ) addPass (


<s> PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult (


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> ) ; SDVTList Tys ; bool useSSE = isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ; if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( StackSlot )


<s> if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) / <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm )


<s> if ( CC >= LPCC :: UNKNOWN ) OS << <STR_LIT> ; else OS << lanaiCondCodeToString


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI

. getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ;


<s> assert ( VA . getLocVT ( ) == <STR_LIT> ) ; SDValue Part0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Part1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part0 , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part1 , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case


<s> ViaVecTy = <STR_LIT> ; if ( BigEndian ) std :: swap ( LaneA , LaneB ) ; } else LaneB = LaneA ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ; SDValue Result = DAG . getBuildVector ( ViaVecTy , DL , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ; if ( ViaVecTy != ResVecTy ) { SDValue One = DAG . getConstant ( <NUM_LIT> , DL


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { <ISA_LIT>InstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + <NUM_LIT> )

. getImm ( ) , MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) , OS ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { assert ( LHS . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CC1Val , Cmp ) ; } else { SDValue CC1Val = DAG . getConstant ( CC1


<s> insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return true


<s> MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( Align ( <NUM_LIT> ) ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> emitIntValue ( ELF :: ODK_REGINFO , <NUM_LIT> ) ; Streamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> emitIntValue ( ri_gprmask , <NUM_LIT> ) ; Streamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer -> emitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> emitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> emitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> emitIntValue ( ri_cprmask [ <NUM_LIT> ] , <NUM_LIT> ) ; Streamer -> emitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( MTS -> getABI ( ) . IsN32 ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> emitIntValue ( ri_gprmask ,


<s> if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; case 'g' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GE ; break ; case 'l' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LE ; break ; case 'o' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCOmode , code = EQ ; break ; case 'p' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCPmode , code = EQ ; break ; case 's' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCSmode , code = EQ ; break ; case 'z' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; } if ( code == UNKNOWN ) { error ( <STR_LIT> , constraints [ i ] ) ; continue ; } if ( invert ) code = reverse_condition ( code ) ; rtx dest = outputs [ i ] ; if ( ! saw_asm_flag ) { constraints [ i ] = <STR_LIT> ; outputs [ i ] = gen_rtx_REG ( CCmode , FLAGS_REG ) ; saw_asm_flag = true ; } else { constraints [ i ] = <STR_LIT> ; outputs [ i ] = gen_rtx_SCRATCH ( SImode ) ; } rtx x = gen_rtx_REG ( mode , FLAGS_REG ) ; x = gen_rtx_fmt_ee ( code , QImode , x , const0_rtx ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! SCALAR_INT_MODE_P ( dest_mode ) ) { error ( <STR_LIT> ) ; continue ; } if ( dest_mode == QImode ) emit_insn ( gen_rtx_SET ( dest , x ) ) ; else { rtx reg = gen_reg_rtx ( QImode


<s> if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return CSR_Darwin_<ISA_LIT>_AAPCS_SaveList ; return


<s> case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'Y' : case 'l' : case 'k' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'Y' : switch ( Constraint [ <NUM_LIT> ]


<s> case <STR_LIT> : DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; assert ( ( KnownZero & KnownOne ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( KnownZero2 & KnownOne2 ) == <NUM_LIT> && <STR_LIT> ) ; KnownOne &= KnownOne2 ; KnownZero &=


<s> return false ; case <STR_LIT> : return true ; case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , false , VT ) ) return


<s> if ( LN -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || ! isa < ConstantPoolSDNode > ( LN -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return false ; ConstantPoolSDNode * CN = dyn_cast < ConstantPoolSDNode > ( LN -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ; FVal = cast < ConstantFP > ( CN -> getConstVal ( ) ) -> getValueAPF ( ) ; } else return false ; bool IsExact ; APSInt IntVal ( <NUM_LIT> , true ) ; FVal . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ; if ( ! IsExact || ! IntVal . isPowerOf2 ( ) ) return false ; unsigned FBits = IntVal . logBase2 ( ) ; if ( FBits == <NUM_LIT> || FBits > RegWidth ) return false ; FixedPos = CurDAG -> getTargetConstant ( FBits , SDLoc ( N ) , <STR_LIT>


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new <ISA_LIT>ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer (


<s> unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , false ) ) return false ; SrcReg = TmpReg ; break ; } } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetRegs [ i ] ) . addReg ( SrcReg ) ; } } } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get (


<s> bool <ISA_LIT>AdvSIMDScalar :: runOnMachineFunction ( MachineFunction & mf ) { bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( * mf . getFunction ( ) ) )


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; Register FramePointer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const Register ActualNegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; Register NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & CopyInst = TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ; if ( FramePointer == NegSizeReg ) { assert ( KillNegSizeReg && <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , II , dl , CopyInst , ActualNegSizeReg ) . addReg ( NegSizeReg ) . addReg ( NegSizeReg ) ; NegSizeReg = ActualNegSizeReg


<s> return ( long long ) __builtin_ia32_vcvtsd2si64 ( ( __v2df )


<s> inline vector signed short vec_packs ( vector signed int a1 , vector signed int a2 ) { return ( vector signed short ) __builtin_altivec_vpkswss ( ( vector signed int ) a1 , ( vector


<s> MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? <STR_LIT> : <STR_LIT> ) . addDef ( PhysReg + ( STI . isLittle ( ) ? <NUM_LIT> : <NUM_LIT> ) ) . addUse ( ValVReg ) . addImm ( <NUM_LIT> ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? <STR_LIT> : <STR_LIT> ) . addDef ( PhysReg + ( STI . isLittle ( ) ? <NUM_LIT> : <NUM_LIT> ) ) . addUse ( ValVReg ) . addImm ( <NUM_LIT> ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else if ( VT == <STR_LIT> && PhysReg >= <STR_LIT> && PhysReg <= <STR_LIT> ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( PhysReg ) . addUse ( ValVReg ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else { unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg


<s> void addT2SOImmNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , JITCodeEmitter & JCE ) { if ( Subtarget . is<ISA_LIT>64 ( ) ) Options . DisableJumpTables = true ; Subtarget . SetJITMode (


<s> SelectAddrMode2Worker ( N , Base , Offset , Opc ) ; return


<s> Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC ::


<s> bool IsMinSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; if ( IsMinSize ) return SDValue ( ) ; SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ; if ( ReplacedSplat != SDValue ( ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> isVolatile ( ) , S -> isNonTemporal ( ) , S -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG .


<s> } if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( insn -> mode == MODE_16BIT && insn -> opcodeType == ONEBYTE && insn -> opcode == <NUM_LIT> ) attrMask ^= ATTR_ADSIZE ; if ( insn -> mode == MODE_64BIT && isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) { switch ( insn -> opcode ) { case <NUM_LIT> : case <NUM_LIT> : if ( insn -> opcodeType == ONEBYTE ) { attrMask ^= ATTR_OPSIZE ; insn -> immediateSize = <NUM_LIT> ; insn -> displacementSize = <NUM_LIT> ; } break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( insn -> opcodeType == TWOBYTE ) { attrMask ^= ATTR_OPSIZE ; insn -> immediateSize = <NUM_LIT> ; insn -> displacementSize = <NUM_LIT> ; } break ; } } if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT && insn -> vectorExtensionType != TYPE_NO_VEX_XOP ) { if ( ( insn -> vectorExtensionType == TYPE_EVEX && wFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_VEX_3B && wFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_XOP && wFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) { uint16_t instructionIDWithREXW ; if ( getIDWithAttrMask ( & instructionIDWithREXW , insn , attrMask | ATTR_REXW ) ) { insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT> ; } const char * SpecName = GetInstrName ( instructionIDWithREXW , miiArg ) ; if ( ! is64Bit ( SpecName ) ) { insn -> instructionID = instructionIDWithREXW ; insn -> spec = specifierForUID ( instructionIDWithREXW ) ; return <NUM_LIT> ; } } } if ( insn -> opcodeType == ONEBYTE && ( ( insn -> opcode & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_ADSIZE ; if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_OPSIZE ; if ( insn -> mode == MODE_16BIT ) attrMask ^= ATTR_ADSIZE | ATTR_OPSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT> ; } if ( ( insn -> mode == MODE_16BIT || insn -> prefixPresent [ <NUM_LIT> ] ) && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const char * specName , * specWithOpSizeName ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ; insn -> spec


<s> else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Base_FrameIndex << '\n' << <STR_LIT> << Scale << '\n' << <STR_LIT> ; if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n' << <STR_LIT> ; if ( ES ) dbgs ( ) << ES ; else dbgs ( )


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isTerminator ( ) ) return MachineOutlinerInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> , MachineOutlinerTailCall , MachineOutlinerTailCall ) ; return MachineOutlinerInfo ( SequenceSize , <NUM_LIT> ,

<NUM_LIT> , MachineOutlinerDefault , MachineOutlinerDefault ) ;


<s> return __builtin_aarch64_floathihf ( __a )


<s> imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm (


<s> TargetRegistry :: RegisterTarget ( TheARM64Target , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; RegisterTarget < Triple :: aarch64 , true > Z (


<s> CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ; else CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic


<s> static void aarch64_emit_inverted_unspec_cond ( rtx target , rtx_code code , machine_mode pred_mode , rtx ptrue , rtx pred , rtx op0 , rtx op1 , bool can_invert_p ) { if ( can_invert_p ) aarch64_emit_unspec_cond ( target , code , pred_mode , pred , op0 , op1 ) ; else { rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_unspec_cond ( tmp , code , pred_mode , pred , op0 ,


<s> static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse ( MachineRegisterInfo * MRI ) { for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if (

MRI -> isPhysRegUsed ( reg ) ) return false ;


<s> fprintf ( asm_out_file , <STR_LIT> , directive ?


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB ( const Target & T


<s> if ( VT > <STR_LIT> ) return <NUM_LIT> ; if ( ! CI -> isZero ( ) ) return FastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; const TargetRegisterClass * RC = ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned ZeroReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( ZeroReg ,


<s> if ( ! isMem ( ) ) return false ; return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == <NUM_LIT> && ( alignOK ||


<s> const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: BCvt : { llvm_unreachable ( <STR_LIT> ) ; break ; } } unsigned ArgReg ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { ArgReg = NextFPR ++ ; if ( CC != CallingConv :: Fast ) ++ NextGPR ; } else ArgReg = NextGPR ++ ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ArgReg ) . addReg ( Arg ) ; RegArgs . push_back ( ArgReg ) ; } return true


<s> StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol (


<s> case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , true ) ; case <STR_LIT> : case <STR_LIT> : return emitSEL_D ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , false , <STR_LIT> ) ; case <STR_LIT> : case


<s> fma_node :: fma_node ( fma_node * parent , du_chain * chain ) { memset ( this , <NUM_LIT> , sizeof ( * this ) ) ; this -> m_parent = parent ; this -> m_children = new std :: list < fma_node * > ; this -> m_insn =


<s> bool WriteNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TFI -> getStackAlignment (


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; const auto & DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr (


<s> if ( TmpWidth < <NUM_LIT> ) { TmpVT = <STR_LIT> ; TmpWidth = <NUM_LIT> ; } if ( SatWidth == <NUM_LIT> && ! IsSigned && Subtarget . is64Bit ( ) ) { TmpVT = <STR_LIT> ; TmpWidth = <NUM_LIT> ; } if ( SatWidth < TmpWidth ) FpToIntOpcode = <STR_LIT> ; APInt MinInt , MaxInt ; if ( IsSigned ) { MinInt = APInt :: getSignedMinValue ( SatWidth ) . sextOrSelf ( DstWidth ) ; MaxInt = APInt :: getSignedMaxValue ( SatWidth ) . sextOrSelf ( DstWidth ) ; } else { MinInt = APInt :: getMinValue ( SatWidth ) . zextOrSelf ( DstWidth ) ; MaxInt = APInt :: getMaxValue ( SatWidth ) . zextOrSelf ( DstWidth ) ; } APFloat MinFloat ( DAG . EVTToAPFloatSemantics ( SrcVT ) ) ; APFloat MaxFloat ( DAG . EVTToAPFloatSemantics ( SrcVT ) ) ; APFloat :: opStatus MinStatus = MinFloat . convertFromAPInt ( MinInt , IsSigned , APFloat :: rmTowardZero ) ; APFloat :: opStatus MaxStatus = MaxFloat . convertFromAPInt ( MaxInt , IsSigned , APFloat :: rmTowardZero ) ; bool AreExactFloatBounds = ! ( MinStatus & APFloat :: opStatus :: opInexact ) && ! ( MaxStatus & APFloat :: opStatus :: opInexact ) ; SDValue MinFloatNode = DAG . getConstantFP ( MinFloat , dl , SrcVT ) ; SDValue MaxFloatNode = DAG . getConstantFP ( MaxFloat , dl , SrcVT ) ; if ( AreExactFloatBounds ) { if ( DstVT != TmpVT ) { SDValue MinClamped = DAG . getNode ( <STR_LIT> , dl , SrcVT , MinFloatNode , Src ) ; SDValue BothClamped = DAG . getNode ( <STR_LIT> , dl , SrcVT


<s> virtual MVT getShiftAmountTy ( EVT LHSTy )


<s> if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) KnownUndef . setBit ( i ) ; if ( <STR_LIT> ( Op ) ) KnownZero . setBit ( i ) ; else if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { APInt Val = Cst -> getAPIntValue ( ) ; Val = Val . extractBits ( ScalarSizeInBits , ( M % Scale ) * ScalarSizeInBits ) ; if ( Val == <NUM_LIT> ) KnownZero . setBit ( i ) ; } else if ( ConstantFPSDNode * Cst = dyn_cast < ConstantFPSDNode > ( Op ) ) { APInt Val = Cst -> getValueAPF ( ) . bitcastToAPInt ( ) ; Val = Val . extractBits ( ScalarSizeInBits , ( M % Scale ) * ScalarSizeInBits ) ; if ( Val == <NUM_LIT> ) KnownZero . setBit ( i ) ; } continue ; } if ( ( V . getNumOperands ( ) % Size ) == <NUM_LIT> ) { int Scale = V -> getNumOperands


<s> if ( TARGET_THUMB && ! TARGET_FDPIC ) addr = expand_simple_binop ( Pmode , IOR ,

addr , const1_rtx , NULL , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> bool has<ISA_LIT>32r6 ( ) const { return ( <ISA_LIT>ArchVersion >= <ISA_LIT>32r6 && <ISA_LIT>ArchVersion < <ISA_LIT>32Max ) || has<ISA_LIT>64r6


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return true ; return false


<s> enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = <NUM_LIT> , one_var = - <NUM_LIT> ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! CONSTANT_P ( x ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode )


<s> void <ISA_LIT>PromoteConstant :: computeInsertionPoint ( Instruction * User , unsigned OpNo , InsertionPoints & InsertPts ) { DEBUG ( dbgs ( ) << <STR_LIT> << OpNo << <STR_LIT> ) ; DEBUG ( User -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; Instruction * InsertionPoint = findInsertionPoint (


<s> bool isStackIdSafeForLocalArea ( unsigned StackId ) const override { return StackId != TargetStackID ::


<s> unsigned NumLaneElts = NumElts / NumLanes ; if ( NumLaneElts == <NUM_LIT> ) return false ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { unsigned i ; for ( i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { if ( Mask [ i + l ] >= <NUM_LIT> ) break ; } if ( i == NumLaneElts ) continue ; int Start = Mask [ i + l ] ; if ( ! isUndefOrInRange ( Start , l , l + NumLaneElts ) && ! isUndefOrInRange ( Start , l + NumElts , l + NumElts + NumLaneElts ) ) return false ; if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Start , Mask [


<s> unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm . quick_push ( i * <NUM_LIT> ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 ,


<s> return ( int16x4_t ) __builtin_neon_vqnegv4hi


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P (


<s> if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes (


<s> V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> bool <ISA_LIT>TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { return true


<s> if ( ! VT . isFixedLengthVector ( ) ) return false ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT>


<s> if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals


<s> Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( ResultReg ) ) ; ResultReg = MoveReg ; } return true


<s> tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build2 ( COMPLEX_EXPR , eff_type , real , imag ) ; if ( type != eff_type ) result = build1 ( VIEW_CONVERT_EXPR , type , result ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , unshare_expr ( valist ) , pre_p ) ; gimplify_assign ( unshare_expr ( valist ) , unshare_expr ( next_fp_tmp ) , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_build_pointer_plus_hwi ( unshare_expr ( next_o ) , rsize ) ; tmp = build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( next_o_limit ) ) ; tmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_o ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; if ( size > <NUM_LIT> && ! ( TARGET_SH4 || TARGET_SH2A ) ) gimplify_assign ( unshare_expr ( next_o ) , unshare_expr ( next_o_limit ) , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; } if ( ! result ) { tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; } } tmp = std_gimplify_va_arg_expr ( valist , type , pre_p , NULL ) ; if ( result ) { gimplify_assign ( result , tmp , pre_p ) ; result = build1 ( NOP_EXPR , TREE_TYPE ( result ) , result ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p )


<s> getOrCreateFramePointerSaveIndex ( MachineFunction & MF ) const { <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int FI = ZFI -> getFramePointerSaveIndex (


<s> vabdq_u16 ( uint16x8_t a , uint16x8_t b ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> else if ( Op . getOpcode ( ) == <STR_LIT> ) Value = ( dyn_cast < ConstantFPSDNode > ( Op ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else return false ; for ( unsigned J = <NUM_LIT> ; J < BytesPerElement ; ++ J ) { uint64_t Byte = ( Value >> ( J * <NUM_LIT> ) ) & <NUM_LIT> ; if ( Byte == <NUM_LIT> ) Mask |= <NUM_LIT> << ( ( E - I


<s> MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = fastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; Address Addr ; Addr . BaseType = Address ::


<s> case CallingConv :: C : case CallingConv :: CXX_FAST_TLS : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; } case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : if ( ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: GHC : if ( Return ) llvm_unreachable (


<s> MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) , RegState :: Implicit ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) , RegState :: ImplicitDefine ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } else { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> :


<s> S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok (


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getTargetConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } SmallVector < int ,


<s> return __builtin_mve_vqrdmulhq_sv4si ( __a ,


<s> if ( ST -> hasVFP2 ( ) && ! ST -> isThumb1Only ( ) ) { if ( Ty -> isFloatTy ( ) ) { return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo :: TCC_Basic ; } } return TargetTransformInfo ::


<s> HOST_WIDE_INT ud1 , ud2 , ud3 , ud4 ; ud1 = c & <NUM_LIT> ; c = c >> <NUM_LIT> ; ud2 = c & <NUM_LIT> ; c = c >> <NUM_LIT> ; ud3 = c & <NUM_LIT> ; c = c >> <NUM_LIT> ; ud4 = c & <NUM_LIT> ; if ( ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ud2 == <NUM_LIT> && ( ud1 & <NUM_LIT> ) ) || ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ud2 == <NUM_LIT> && ! ( ud1 & <NUM_LIT> ) ) ) emit_move_insn ( dest , GEN_INT ( ( ud1 ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; else if ( ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ( ud2 & <NUM_LIT> ) ) || ( ud4 == <NUM_LIT> && ud3 == <NUM_LIT> && ! ( ud2 & <NUM_LIT> ) ) ) { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( DImode ) ; emit_move_insn ( ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , GEN_INT ( ( ( ud2 << <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud1 ) ) ) ; } else if ( ud3 == <NUM_LIT> && ud4 == <NUM_LIT> ) { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( DImode ) ; gcc_assert ( ud2 & <NUM_LIT>


<s> if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ <NUM_LIT> ] , sel [ <NUM_LIT> ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return


<s> if ( Inst -> getOpcode ( ) == Opcode || isa < PHINode > ( U ) ) { if ( auto * FPOp = dyn_cast < FPMathOperator > ( Inst ) ) if ( ! isa < PHINode > ( FPOp ) && ! FPOp -> getFastMathFlags ( ) . isFast ( ) ) return false ; UsersToVisit . push_back ( U ) ; } else if ( auto * ShufInst = dyn_cast < ShuffleVectorInst > ( U ) ) { unsigned ResultElements = ShufInst -> getType ( ) -> getVectorNumElements ( ) ; if ( ResultElements < ElemNum ) return false ; if ( ElemNumToReduce == <NUM_LIT> ) return false ; if ( ! isa < UndefValue > ( U -> getOperand ( <NUM_LIT> ) ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < ElemNumToReduce / <NUM_LIT> ; ++ i ) if ( ShufInst -> getMaskValue ( i ) != int ( i + ElemNumToReduce / <NUM_LIT> ) ) return false ; for ( unsigned i = ElemNumToReduce / <NUM_LIT> ; i < ElemNum ; ++ i ) if ( ShufInst -> getMaskValue ( i ) != - <NUM_LIT> ) return false ; if ( ! U -> hasOneUse ( ) ) return false ; auto * U2 = dyn_cast < BinaryOperator > ( * U -> user_begin ( ) ) ; if ( ! U2 || U2 -> getOpcode ( ) != Opcode ) return false ; if ( ( U2 -> getOperand ( <NUM_LIT> ) == U -> getOperand ( <NUM_LIT> ) && U2 -> getOperand ( <NUM_LIT> ) == U ) || ( U2 -> getOperand ( <NUM_LIT> ) == U -> getOperand ( <NUM_LIT> ) && U2 -> getOperand ( <NUM_LIT> ) == U ) ) { UsersToVisit . push_back ( U2 ) ; ElemNumToReduce /= <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { if ( Immed < <NUM_LIT> ) Immed *= - <NUM_LIT> ; return isLegalAddImmediate ( Immed )