<s> AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg (

Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) ) ;


<s> return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; if ( getSubTarget ( ) . hasNEON ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> & - <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned Dst = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; unsigned Src = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , Dst ) .


<s> uint64_t SHSrc = MOpSHSrc . getImm ( ) ; uint64_t MBSrc = MOpMBSrc . getImm ( ) ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; uint64_t NewSH = SHSrc + SHMI ; uint64_t NewMB = MBSrc - SHMI ; if ( NewMB > <NUM_LIT> || NewSH > <NUM_LIT> ) return false ; if ( ( <NUM_LIT> - NewSH ) != MEMI ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewSH ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewMB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; NumRotatesCollapsed ++ ; return


<s> void <ISA_LIT>CopyPhysRegs :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> return true ; case Instruction :: UDiv : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectDivRem ( I , <STR_LIT> ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift (


<s> uint64_t Pos = <NUM_LIT> , SMPos , SMSize ; ConstantSDNode * CN ; SDValue NewOperand ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( SecondOperand ) ) ) return SDValue ( ) ; Pos = CN -> getZExtValue ( ) ; if ( Pos >= ValTy . getSizeInBits ( ) ) return SDValue ( ) ; if ( FirstOperandOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( FirstOperand . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; if ( SMPos != <NUM_LIT> || SMSize > <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; NewOperand = FirstOperand . getOperand ( <NUM_LIT>


<s> SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Register , StartLoc , EndLoc ) ) ; } else { Register Reg ; if ( parseRegister ( Reg ) ) return MatchOperand_ParseFail ; RegisterKind Kind ; unsigned RegNo ; if ( Reg . Group == RegGR ) { Kind = GR64Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegFP ) { Kind = FP64Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegV ) { Kind = VR128Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegAR ) { Kind = AR32Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else if ( Reg . Group == RegCR ) { Kind = CR64Reg ; RegNo = <STR_LIT> [ Reg . Num ] ; } else { return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createReg ( Kind , RegNo , Reg


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None ) { int ISD = TLI -> InstructionOpcodeToISD (


<s> } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( )


<s> case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return NULL ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) !=


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , VectorType * Tp , int Index , VectorType * SubTp ) { if ( Kind == TTI :: SK_Broadcast || Kind == TTI :: SK_Transpose || Kind == TTI :: SK_Select || Kind == TTI :: SK_PermuteSingleSrc ) { static const CostTblEntry ShuffleTbl [ ] = { { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( ShuffleTbl , Kind , LT . second ) ) return


<s> Inst . addOperand ( MCOperand :: CreateImm ( Insn << <NUM_LIT> )


<s> return ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release (


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode =


<s> finish_opt_n_resolution ( unsigned int argno , unsigned int first_argno , type_suffix_index first_type , type_class_index expected_tclass , unsigned int expected_bits , type_suffix_index inferred_type ) { if ( inferred_type == NUM_TYPE_SUFFIXES ) inferred_type = first_type ; tree scalar_form = lookup_form ( MODE_n , inferred_type ) ; if ( scalar_argument_p ( argno ) ) { if ( scalar_form ) return scalar_form ; tree res = resolve_to ( mode_suffix_id , inferred_type ) ; if ( res != error_mark_node ) error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , get_vector_type ( first_type ) ) ; return error_mark_node ; } if ( scalar_form && ! require_vector_or_scalar_type ( argno ) ) return error_mark_node ; if ( ! require_derived_vector_type ( argno , first_argno , first_type

, expected_tclass , expected_bits ) ) return error_mark_node ;


<s> if ( exp ) error ( <STR_LIT> , exp , lane , low , high - <NUM_LIT> ) ; else error ( <STR_LIT> , lane , low ,


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return


<s> roundup = build2 ( MODIFY_EXPR , TREE_TYPE ( arg ) , arg , t ) ; } else roundup = NULL ; t = fold_build_pointer_plus_hwi ( arg , size + <NUM_LIT> ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - <NUM_LIT> ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , unshare_expr ( stack ) , t ) ; if ( roundup ) t = build2 ( COMPOUND_EXPR , TREE_TYPE ( t ) , roundup , t ) ; on_stack = build2 ( COMPOUND_EXPR , TREE_TYPE ( arg ) , t , arg ) ; if ( BLOCK_REG_PADDING ( mode , type , <NUM_LIT> ) == PAD_DOWNWARD && size < UNITS_PER_WORD ) { t = build2 ( POINTER_PLUS_EXPR , TREE_TYPE ( arg ) , arg , size_int ( UNITS_PER_WORD - size ) ) ; on_stack = build2 ( COMPOUND_EXPR , TREE_TYPE ( arg ) , on_stack , t ) ; } COND_EXPR_THEN ( cond1 ) = unshare_expr ( on_stack ) ; COND_EXPR_THEN ( cond2 ) = unshare_expr ( on_stack ) ; t = off ; if ( adjust ) t = build2 ( PREINCREMENT_EXPR , TREE_TYPE ( off ) , off , build_int_cst ( TREE_TYPE ( off ) , adjust ) ) ; t = fold_convert ( sizetype , t ) ; t = build2 ( POINTER_PLUS_EXPR , TREE_TYPE ( f_top ) , f_top , t ) ; if ( is_ha ) { int i ; tree tmp_ha , field_t , field_ptr_t ; tmp_ha = create_tmp_var_raw ( type , <STR_LIT> ) ; gimple_add_tmp_var ( tmp_ha ) ; switch ( ag_mode ) { case E_SFmode : field_t = float_type_node ; field_ptr_t = float_ptr_type_node ; break ; case E_DFmode : field_t = double_type_node ; field_ptr_t = double_ptr_type_node ; break ; case E_TFmode : field_t = long_double_type_node ; field_ptr_t = long_double_ptr_type_node ; break ; case E_HFmode : field_t = aarch64_fp16_type_node ; field_ptr_t = aarch64_fp16_ptr_type_node ; break ; case E_BFmode : field_t = aarch64_bf16_type_node ; field_ptr_t = aarch64_bf16_ptr_type_node ; break ; case E_V2SImode : case E_V4SImode : { tree innertype = make_signed_type ( GET_MODE_PRECISION ( SImode ) ) ; field_t = build_vector_type_for_mode ( innertype , ag_mode ) ; field_ptr_t = build_pointer_type ( field_t ) ; } break ; default : gcc_assert ( <NUM_LIT> ) ; } TREE_ADDRESSABLE ( tmp_ha ) = <NUM_LIT> ; tmp_ha = build1 ( ADDR_EXPR , field_ptr_t , tmp_ha ) ; addr = t ; t = fold_convert ( field_ptr_t , addr ) ; t = build2 ( MODIFY_EXPR , field_t , build1 ( INDIRECT_REF , field_t , tmp_ha ) , build1 ( INDIRECT_REF , field_t , t ) ) ; for ( i = <NUM_LIT> ; i < nregs ; ++ i ) { addr = fold_build_pointer_plus_hwi ( addr , UNITS_PER_VREG ) ; u = fold_convert ( field_ptr_t , addr ) ; u = build2 ( MODIFY_EXPR , field_t , build2 ( MEM_REF , field_t , tmp_ha , build_int_cst ( field_ptr_t , ( i * int_size_in_bytes (

field_t ) ) ) ) , build1 ( INDIRECT_REF , field_t , u ) ) ;


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; SmallVector < unsigned , <NUM_LIT> > Regs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , VReg ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret , AssignFn ) ; return handleAssignments ( MIRBuilder , SplitVTs , RetHandler


<s> void addITMaskOperands ( MCInst & Inst , unsigned N


<s> std :: string TT = M . getTargetTriple ( ) ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( M . getEndianness ( ) == Module :: BigEndian && M . getPointerSize ( ) == Module :: Pointer64 ) return <NUM_LIT> ; else if ( M . getEndianness ( ) != Module :: AnyEndianness || M . getPointerSize ( )

!= Module :: AnyPointerSize ) return <NUM_LIT> ;


<s> SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ,


<s> assert ( HasCalleeSavedStackSize && <STR_LIT>


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1


<s> bool <ISA_LIT>TTIImpl :: useReductionIntrinsic ( unsigned Opcode , Type * Ty , TTI :: ReductionFlags Flags ) const { assert ( isa < VectorType > ( Ty ) && <STR_LIT> ) ; unsigned ScalarBits = Ty -> getScalarSizeInBits ( ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; switch ( Opcode ) { case Instruction ::


<s> if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get (


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ; break ; case RegisterSeq : RegSeq = o . RegSeq ; break ; case CPOP : CPool = o . CPool ; break ; case Immediate : Imm = o


<s> EVT ExtVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; if ( ExtVT != <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getValueType ( EVT :: getVectorVT ( * DAG . getContext ( ) , ExtVT . getVectorElementType ( ) , <NUM_LIT> ) ) ) ; Op = DAG . getNode ( <STR_LIT> , dl ,


<s> O << GV << <STR_LIT> << int ( Modifier


<s> for ( const auto & Record : Updates ) InsertionOrder . insert ( std :: make_pair ( Record . C , InsertionOrder . size ( ) ) ) ; std :: stable_sort ( Updates . begin ( ) , Updates . end ( ) , [ & InsertionOrder ] ( const UpdateRecord & L , const UpdateRecord & R ) { return InsertionOrder . lookup ( L . C ) < InsertionOrder


<s> int Offset = getLdStOffsetOp ( MI ) . getImm ( ) ; int OffsetStride = IsUnscaled ? getMemScale ( MI ) : <NUM_LIT> ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , LdStLimit ) ; if ( Paired != E ) { ++ NumPairCreated ; if ( TII -> isUnscaledLdSt (


<s> if ( ! Mask ) Mask = CDAG . getConstantMask ( Packing , true ) ; assert ( LegalVecVT . isSimple ( ) ) ; if ( isVVPUnaryOp ( VVPOpcode ) ) return CDAG . getNode ( VVPOpcode , LegalVecVT , { Op -> getOperand ( <NUM_LIT> ) , Mask , AVL } ) ; if ( isVVPBinaryOp ( VVPOpcode ) ) return CDAG . getNode ( VVPOpcode , LegalVecVT , { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Mask , AVL } ) ; if ( isVVPReductionOp ( VVPOpcode ) ) { auto SrcHasStart = hasReductionStartParam ( Op -> getOpcode ( ) ) ; SDValue StartV = SrcHasStart ? Op -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue VectorV = Op -> getOperand ( SrcHasStart ? <NUM_LIT> : <NUM_LIT> ) ; return CDAG . getLegalReductionOpVVP ( VVPOpcode , Op . getValueType ( ) , StartV , VectorV , Mask , AVL , Op -> getFlags ( ) ) ; } switch ( VVPOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { auto X = Op -> getOperand ( <NUM_LIT> ) ; auto Y = Op -> getOperand ( <NUM_LIT> ) ; auto Z = Op -> getOperand ( <NUM_LIT> ) ; return CDAG . getNode ( VVPOpcode , LegalVecVT , { X


<s> static const IntrinsicData * getIntrinsicWithoutChain ( unsigned IntNo ) { const IntrinsicData * Data = lower_bound ( IntrinsicsWithoutChain , IntNo ) ; if ( Data != std :: end ( IntrinsicsWithoutChain ) && Data -> Id == IntNo ) return Data ; return nullptr


<s> t = a / c ; if ( unlikely ( t == <NUM_LIT> ) || nonfinite ( t ) ) return t ; s = c * t ; w = - ( - b + d * t ) ; asm ( <STR_LIT> : <STR_LIT> ( sigma ) : <STR_LIT> ( c ) , <STR_LIT> ( t ) , <STR_LIT> ( s ) ) ; v = a - s ; tau = ( ( v - sigma ) + w ) / c ; u = t + tau ; if ( nonfinite ( u ) ) return u ; z . dval [ <NUM_LIT> ] = u ; z . dval [ <NUM_LIT> ] = ( t - u ) + tau ; return z . ldval


<s> SDValue Ops [ ] = { DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) , CCReg } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG


<s> const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> usesPICBase ( ) ) { MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel


<s> static DecodeStatus DecodeCPRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> else Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; return DAG . getNode ( <STR_LIT> , dl


<s> O << ( unsigned short ) MI -> getOperand ( OpNo ) . getImm


<s> Inst . addOperand ( MCOperand :: CreateReg (


<s> return __builtin_mve_vqshluq_n_sv16qi ( __a ,


<s> const std :: string & <ISA_LIT>ToTHMStub


<s> static Optional < uint64_t > evaluateMemOpAddrForAddrModeT1_s ( const MCInst & Inst , const MCInstrDesc & Desc , unsigned MemOpIndex , uint64_t


<s> return ( uint64_t ) __builtin_neon_vget_lanev2di ( ( int64x2_t ) __a ,


<s> static SDValue combineZext ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V =

combineExtSetcc ( N , DAG , Subtarget ) ) return V ;


<s> Result = CC_<ISA_LIT>32_SVR4_VarArg ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ; } if ( Result ) { errs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ; llvm_unreachable ( nullptr ) ; } } } else { CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32_SVR4 ) ; } CCInfo . clearWas<ISA_LIT>F128 ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , IsVarArg , MF , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned NumBytes = CCByValInfo . getNextStackOffset ( ) ; int SPDiff = CalculateTailCallSPDiff ( DAG , IsTailCall , NumBytes ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SDValue LROp , FPOp ; Chain = EmitTailCallLoadFPAndRetAddr ( DAG , SPDiff , Chain , LROp , FPOp , dl ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < TailCallArgumentInfo , <NUM_LIT> > TailCallArguments ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; bool seenFloatArg = false ; for ( unsigned i = <NUM_LIT> , RealArgIdx = <NUM_LIT> , j = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ RealArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ RealArgIdx ] ; <STR_LIT> Flags = Outs [ RealArgIdx ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) ->

getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ;


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerCONSTANTPOOL ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP (


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler (


) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return <NUM_LIT> - HasFP ; } case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF )


<s> case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : case <STR_LIT> : { SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TopPart , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue MulLHS = N ->


<s> InConstantPool = false ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return expandTLSLA ( MI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return emitCustomConstantPool


<s> static unsigned sizeExternalSymbolAddress ( bool dword ) { return dword ? <NUM_LIT>


<s> addPass ( new <ISA_LIT>ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } addPass ( create<ISA_LIT>IndirectThunks ( ) )


<s> auto * AndMask = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( AndMask ) { auto AmtVal = AndMask -> getZExtValue ( ) ; if ( ( AmtVal & <NUM_LIT> ) == <NUM_LIT> ) { SDValue AndOp = N1 -> getOperand ( <NUM_LIT> ) ; if ( N1 . hasOneUse ( ) ) { DCI . CombineTo ( N1 . getNode ( ) , AndOp ) ; return SDValue ( N , <NUM_LIT>


<s> uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = macho :: RIT_<ISA_LIT>_HalfDifference ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : MovtBit = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : MovtBit = <NUM_LIT> ; case


<s> BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addLeaRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else { if ( NumBytes ) emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; int MaxTCDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int Offset = <NUM_LIT> ; assert ( MaxTCDelta <= <NUM_LIT> && <STR_LIT> ) ; Offset = StackAdj - MaxTCDelta ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if ( Offset ) { Offset += mergeSPUpdates ( MBB , MBBI , StackPtr , true ) ; emitSPUpdate ( MBB , MBBI , StackPtr , Offset , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) ) ; else if ( RetOpcode == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII .

get ( <STR_LIT> ) , JumpTarget . getReg ( ) ) ;


<s> switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) Known . Zero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( known_lt ( poly_size , min_probe_threshold ) || ! flag_stack_clash_protection ) { aarch64_sub_sp ( temp1 , temp2 , poly_size , frame_related_p ) ; return ; } HOST_WIDE_INT size ; if ( ! poly_size . is_constant ( & size ) ) { if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; print_dec ( poly_size , dump_file ) ; fprintf ( dump_file , <STR_LIT> ) ; } aarch64_add_offset ( Pmode , temp1 , CONST0_RTX ( Pmode ) , poly_size , temp1 , temp2 , false , true ) ; rtx_insn * insn = get_last_insn ( ) ; if ( frame_related_p ) { rtx stack_ptr_copy = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_move_insn ( stack_ptr_copy , stack_pointer_rtx ) ; emit_insn ( gen_stack_tie ( stack_ptr_copy , stack_pointer_rtx ) ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , stack_ptr_copy ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } rtx probe_const = gen_int_mode ( min_probe_threshold , Pmode ) ; rtx guard_const = gen_int_mode ( guard_size , Pmode ) ; insn = emit_insn ( gen_probe_sve_stack_clash ( Pmode , stack_pointer_rtx , stack_pointer_rtx , temp1 , probe_const , guard_const ) ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , gen_int_mode ( poly_size , Pmode ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } return ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , size ) ; HOST_WIDE_INT rounded_size = ROUND_DOWN ( size , guard_size ) ; HOST_WIDE_INT residual = size - rounded_size ; if ( rounded_size <= STACK_CLASH_MAX_UNROLL_PAGES * guard_size ) { for ( HOST_WIDE_INT i = <NUM_LIT> ; i < rounded_size ; i += guard_size ) { aarch64_sub_sp ( NULL , temp2 , guard_size , true ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , guard_used_by_caller ) ) ; emit_insn ( gen_blockage ( ) ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , size != rounded_size ) ; } else { aarch64_add_offset ( Pmode , temp1 , stack_pointer_rtx , - rounded_size , temp1 , NULL , false , true ) ; rtx_insn * insn = get_last_insn ( ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , temp1 , rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> if ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> ) nwords = <NUM_LIT> ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = <NUM_LIT> ; i < nwords ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; } return


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , ( int ) Lo , ( int ) Hi ) ) return false ; return true


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + <NUM_LIT> ) < <NUM_LIT> ) return <NUM_LIT> ; else if ( ( value & <NUM_LIT> ) == <NUM_LIT> && ( value >> <NUM_LIT> == - <NUM_LIT> || value >> <NUM_LIT> == <NUM_LIT> ) ) return <NUM_LIT> ; else if (


<s> __res . as_int [ <NUM_LIT> ] = ( unsigned int ) __res . as_int [ <NUM_LIT> ] >> __count ; __res . as_int [ <NUM_LIT> ] = ( unsigned int ) __res . as_int [ <NUM_LIT> ] >> __count ; return ( __res .


<s> ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) ,

MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool

Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) {


<s> MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( AnonSymbol -> getName ( ) ) ) ; OutStreamer . EmitLabel ( AnonSymbol ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; else OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( )


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( )


<s> MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && isTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) { unsigned TestOpc = <NUM_LIT> ; switch ( SourceVT . SimpleTy ) { default : break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; case <STR_LIT> : TestOpc = <STR_LIT> ; break ; } if ( TestOpc ) { unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TestOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; unsigned JmpOpc = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TrueMBB ) ) { std :: swap ( TrueMBB , FalseMBB ) ; JmpOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( JmpOpc ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; return true ; } } } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , BI , BI -> getCondition ( ) ) ) { unsigned TmpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( TmpReg == <NUM_LIT> ) return false ; unsigned BranchOpc = <STR_LIT> ( CC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BranchOpc ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; return true ; } unsigned OpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT>


<s> memset ( rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; return <NUM_LIT> ; case CALL_INSN : flags . is_branch = <NUM_LIT> ; flags . is_sibcall = SIBLING_CALL_P ( insn ) ; memset ( rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = <NUM_LIT> ; break ; } need_barrier = rtx_needs_barrier ( PATTERN ( insn ) , flags , <NUM_LIT> ) ; break ; case JUMP_INSN : if ( ! ia64_spec_check_p ( insn ) ) flags . is_branch = <NUM_LIT> ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = <NUM_LIT> ; break ; } case INSN : if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) break ; pat = PATTERN ( insn ) ; switch ( recog_memoized ( insn


, masked_fenv , ld_fenv ) , hold_fnclex ) ;


<s> return ; } if ( MO . isImm ( ) ) { O << ( int ) MO . getImm ( ) ; return ; } assert ( MO . isExpr ( ) &&


<s> SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; return selectI64Imm ( CurDAG ,


<s> case E_V2DImode : subparts = <NUM_LIT> ; break ; case E_V4SFmode : case E_V4SImode : subparts = <NUM_LIT> ; break ; case E_V8HImode : subparts = <NUM_LIT> ; break ; case E_V16QImode : subparts = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = <NUM_LIT> ; i < subparts / <NUM_LIT> ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / <NUM_LIT> ) ; for ( i = subparts / <NUM_LIT> ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / <NUM_LIT> ) ; return


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC ||

TARGET_NO_TOC || constant_pool_empty_p ( ) : true ) ;


<s> assert ( ( Cond . size ( ) && Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_<ISA_LIT>_PURECODE ; TextSection = Ctx . getELFSection ( <STR_LIT> , Type , Flags ,


<s> else if ( RC == & <STR_LIT> ) return & <STR_LIT> ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC )


<s> EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ( Ty != <STR_LIT> ) && ( Ty != <STR_LIT> ) ) return SDValue ( ) ; return performDSPShiftCombine ( <STR_LIT> , N , Ty


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target

) Kind = getTargetFixup ( MO . getExpr ( ) ) ;


<s> unsigned int incoming_stack_boundary ; if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ! TARGET_64BIT && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == <NUM_LIT> ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary


<s> unsigned int <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind


<s> if ( ! DstTy . isVector ( ) || ! SrcTy . isVector ( ) ) return false ; assert ( SrcTy . getSizeInBits ( ) > DstTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else return false ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstReg , MRI ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcReg , MRI ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ,

DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubIdx ) ;


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; } else if ( Domain == <STR_LIT> ) { if ( MI -> getDesc ( ) . mayStore ( ) || MI -> getDesc ( ) . mayLoad ( ) ) return false ; } else return false


<s> case IES_LSHIFT : case IES_RSHIFT : case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_LBRAC : case


<s> return ( ST == <STR_LIT> || ST == <STR_LIT> || ST ==

<STR_LIT> ) && getShiftExtendAmount ( ) < width ;


<s> SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , ParmReg , TGA ) ; Chain = DAG . getCopyToReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , TLSAddr ) ; return DAG . getCopyFromReg ( Chain , dl , is64bit ? <STR_LIT> : <STR_LIT> , PtrVT ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> ,


<s> return ( TARGET_USE_MS_BITFIELD_LAYOUT && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) ) ) ||


<s> bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CS . arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: SwiftSelf ) || CS . paramHasAttr ( AttrInd , Attribute :: SwiftError ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register


<s> Type * Ty = V -> getType ( ) ; if ( Ty -> isVoidTy ( ) || Ty -> isPointerTy ( ) ) return true ; if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) Ty = cast < PointerType > ( Ld -> getPointerOperandType ( )


<s> if ( ! TheLoop -> getLoopPreheader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } for ( PHINode & Phi : Header -> phis ( ) ) { const auto * Ty = Phi . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; const bool IsReduction = RecurrenceDescriptor :: AddReductionVar ( & Phi , RecurrenceDescriptor :: RK_IntegerAdd , TheLoop , HasFnNoNaNAttr , RecDesc ) ; if ( ! IsReduction ) continue ; Instruction * Acc = dyn_cast < Instruction > (

Phi . getIncomingValueForBlock ( Latch ) ) ;


<s> } } else if ( CompareOpc == <STR_LIT> || CompareOpc == <STR_LIT> ) { switch ( CRSubReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return ( uint64_t ) Imm1 < ( uint64_t ) Imm2 ? TrueReg : FalseReg ; case <STR_LIT> : return ( uint64_t ) Imm1 > ( uint64_t ) Imm2 ? TrueReg : FalseReg ; case


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple


<s> if ( ! crtl -> is_leaf ) if ( r == LP_REGNO || IVC2_ISAVED_REG ( r ) ) return true ; if ( ! crtl -> is_leaf || cfun -> machine -> doloop_tags > <NUM_LIT> ) if ( r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO ) return true ; if ( crtl -> is_leaf && call_used_regs [ r ] && ! df_regs_ever_live_p ( r ) ) return false ; if ( call_used_regs [ r ] && ! fixed_regs [ r ] )


<s> return new <ISA_LIT>ReduceCRLogicals


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; const Register Reg64 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const Register Reg32 = RI . getSubReg ( Reg64 , <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , Reg32 ) . addReg ( <STR_LIT> ) . addReg ( Reg64 , RegState :: ImplicitDefine ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , Reg64 ) . addReg ( Reg64 ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , Reg32 ) . addReg ( <STR_LIT> ) ; MI -> setDesc ( get (


<s> bool <ISA_LIT>RegisterInfo :: isCallerPreservedPhysReg ( MCRegister PhysReg , const MachineFunction & MF ) const { assert ( Register :: isPhysicalRegister ( PhysReg ) ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! Subtarget . is64BitELFABI ( ) && ! Subtarget . isAIXABI ( ) ) return false ; if ( PhysReg == Subtarget . getTOCPointerRegister ( ) ) return ( getReservedRegs


<s> MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; MIB . addFrameIndex ( FI ) . addImm ( Offset ) ; } else { assert ( Addr . isRegBase ( ) && <STR_LIT> ) ; const MCInstrDesc & II = MIB -> getDesc ( ) ; unsigned Idx = ( Flags & MachineMemOperand :: MOStore ) ? <NUM_LIT> : <NUM_LIT> ; Addr . setReg ( constrainOperandRegClass ( II , Addr . getReg ( ) , II


<s> bool llvm :: CC_<ISA_LIT>32_SVR4_Custom_Dummy ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign

:: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) {


<s> { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true


<s> if ( VT . getSimpleVT ( ) . getScalarType ( ) == <STR_LIT> ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == <NUM_LIT> ) return false ; return isTypeLegal ( VT . getSimpleVT (


<s> explicit <ISA_LIT>MemAluCombiner ( ) : MachineFunctionPass (


<s> vtrnq_p8 ( poly8x16_t a , poly8x16_t b ) { return ( poly8x16x2_t ) { vtrn1q_p8 ( a , b ) , vtrn2q_p8


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL_NORELAX ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr ::


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset


<s> return AM2_BASE ; } if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal =


<s> SWITCH_TO_SECTION_FUNCTION void \ drectve_section ( ) \ { \ if ( in_section != in_drectve ) \ { \ fprintf ( asm_out_file , <STR_LIT>

, <STR_LIT> ) ; \ in_section = in_drectve ; \ } \ }


<s> emit_insn ( gen_aarch64_rsqrte ( mode , xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? <NUM_LIT> : <NUM_LIT> ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( gen_aarch64_rsqrts ( mode , x1 , src , x2 ) ) ; if ( iterations > <NUM_LIT> ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; } if ( ! recp ) { rtx xtmp = gen_reg_rtx ( mmsk ) ; emit_set_insn ( xtmp , gen_rtx_AND ( mmsk , gen_rtx_NOT ( mmsk , xmsk ) , gen_rtx_SUBREG ( mmsk , xdst , <NUM_LIT> ) ) ) ; emit_move_insn ( xdst , gen_rtx_SUBREG ( mode , xtmp , <NUM_LIT> ) ) ; emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , src )


<s> if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; break ; case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI ->


<s> bool <ISA_LIT>FastISel :: selectGetElementPtr ( const Instruction * I ) { unsigned N = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! N ) return false ; bool NIsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; uint64_t TotalOffs = <NUM_LIT> ; Type * Ty = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; MVT VT = TLI . getPointerTy ( ) ; for ( auto OI = std :: next ( I -> op_begin ( ) ) , E = I -> op_end ( ) ; OI != E ; ++ OI ) { const Value * Idx = * OI ; if ( auto * StTy = dyn_cast < StructType > ( Ty ) ) { unsigned Field = cast < ConstantInt > ( Idx ) -> getZExtValue ( ) ; if ( Field ) TotalOffs += DL . getStructLayout ( StTy ) -> getElementOffset ( Field ) ; Ty = StTy -> getElementType ( Field ) ; } else { Ty = cast < SequentialType > ( Ty ) -> getElementType ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( Idx ) ) { if ( CI -> isZero ( ) ) continue ; TotalOffs += DL . getTypeAllocSize ( Ty ) * cast < ConstantInt > ( CI ) -> getSExtValue ( ) ; continue ; } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , NIsKill , TotalOffs ) ; if ( ! N ) return false ; NIsKill = true ; TotalOffs = <NUM_LIT> ; } uint64_t ElementSize = DL . getTypeAllocSize ( Ty ) ; std :: pair < unsigned , bool > Pair = getRegForGEPIndex ( Idx ) ; unsigned IdxN = Pair . first ; bool IdxNIsKill = Pair . second ; if ( ! IdxN ) return false ; if ( ElementSize != <NUM_LIT> ) { unsigned C = fastEmit_i ( VT , VT , <STR_LIT> , ElementSize ) ; if ( ! C ) return false ; IdxN = emitMul_rr ( VT , IdxN , IdxNIsKill , C , true ) ; if ( ! IdxN ) return false ; IdxNIsKill = true ; } N = fastEmit_rr ( VT , VT , <STR_LIT> , N , NIsKill , IdxN , IdxNIsKill ) ; if ( ! N ) return false ; } } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , NIsKill ,


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . Opcode == <STR_LIT> ) abort ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) <<


<s> SDValue C = DAG . getConstant ( InvalidOnQNaN , dl , <STR_LIT> ) ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter (


<s> bool <ISA_LIT>DAGToDAGISel :: canUseBlockOperation ( StoreSDNode * Store , LoadSDNode * Load ) const { if ( Load -> getMemoryVT ( ) != Store -> getMemoryVT ( ) ) return false ; if ( Load -> isVolatile ( ) || Store -> isVolatile ( ) ) return false ; if ( Load -> isInvariant ( ) && Load -> isDereferenceable ( ) ) return true ; const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) +


<s> bool <ISA_LIT>InvISelDAG :: SelectImmShifterOperand ( SDValue N , SDValue & BaseReg , SDValue & Opc , bool CheckProfitability ) { return true


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __asrtle_d ( long int _1 , long int _2 ) { __builtin_loongarch_asrtle_d ( ( long int ) _1 , ( long int )


<s> return ( __m512d ) __builtin_ia32_reducepd512_mask ( ( __v8df ) __A , __B , ( __v8df ) _mm512_setzero_pd ( ) ,


<s> static void aarch64_emit_unspec_cond ( rtx target , rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtx unspec = aarch64_gen_unspec_cond ( code , pred_mode , pred , op0 ,


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter (


<s> default : return Fail ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Rt ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR16RegisterClass ( Inst , Rt ,


<s> bool Thumb2SizeReduce :: ReduceTo2Addr ( MachineBasicBlock & MBB , MachineInstr * MI , const ReduceEntry & Entry , bool LiveCPSR ) { if ( ReduceLimit2Addr != - <NUM_LIT> && ( ( int ) Num2Addrs >= ReduceLimit2Addr ) ) return false ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reg0 != Reg1 ) return false ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewTID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewTID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = TID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TopPart , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue MulLHS = N -> getOperand ( <NUM_LIT>


<s> struct xstormy16_stack_layout xstormy16_compute_stack_layout ( ) { struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( current_function_varargs || current_function_stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = <NUM_LIT> ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( current_function_args_size <= <NUM_LIT> && current_function_args_size != - <NUM_LIT> ) { if ( layout . frame_size + INCOMING_FRAME_SP_OFFSET + current_function_args_size <= <NUM_LIT> ) layout . fp_minus_ap = layout . frame_size


<s> if ( ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst . getOpcode ( ) == <STR_LIT> || SecondLastInst . getOpcode

( ) == <STR_LIT> ) && LastInst . getOpcode ( ) == <STR_LIT> ) {


<s> if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vspltisb || icode == CODE_FOR_altivec_vspltish || icode == CODE_FOR_altivec_vspltisw || icode == CODE_FOR_spe_evsplatfi || icode == CODE_FOR_spe_evsplati ) { if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < - <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShMsk0 ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt0 . getOperand ( <NUM_LIT> ) ) && ShAmt0 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk0 = ShAmt0 ; ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; } SDValue ShMsk1 ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt1 . getOperand ( <NUM_LIT> ) ) && ShAmt1 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk1 = ShAmt1 ; ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; } if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> || ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; std :: swap ( ShMsk0 , ShMsk1 ) ; } if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( auto * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( ( SumC -> getAPIntValue ( ) == Bits || ( SumC -> getAPIntValue ( ) == <NUM_LIT> && ShMsk1 ) ) && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } } else if ( auto * ShAmt1C = dyn_cast < ConstantSDNode > ( ShAmt1 ) ) { auto * ShAmt0C = dyn_cast < ConstantSDNode > ( ShAmt0 ) ; if ( ShAmt0C && ( ShAmt0C -> getSExtValue ( ) + ShAmt1C -> getSExtValue ( ) ) == Bits ) return DAG . getNode ( Opc , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } else if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = ShAmt1 . getOperand ( <NUM_LIT>


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction


<s> Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ; Inst . addOperand ( MCOperand :: createImm ( Shift ) ) ; return Success


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_extract_epi16 ( __m128i const __A , int const __N ) { return ( unsigned short ) ( ( __v8hi )


<s> unsigned RegisterWidth = VT . getSizeInBits ( ) ; unsigned FieldWidth = VT . getScalarSizeInBits ( ) ; unsigned NumElems = RegisterWidth / FieldWidth


<s> enabled_abi_types [ DEFAULT_ABI_BASE ] [ DEFAULT_ABI_EXT ] = <NUM_LIT> ; int abi_base , abi_ext ; for ( unsigned int i = <NUM_LIT> ; i < MULTILIB_LIST_LEN ; i ++ ) { abi_base = tm_multilib_list [ i << <NUM_LIT> ] ; abi_ext = tm_multilib_list [ ( i << <NUM_LIT> ) + <NUM_LIT>


<s> return new Micro<ISA_LIT>SizeReduce ( )


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst .

addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm << <NUM_LIT> ) ) ) ;


<s> if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg

. getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ;


<s> <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! RegInfo || ! FI ) return false ; if ( ! Subtarget . isELFv2ABI ( ) || ! Subtarget . is<ISA_LIT>64 ( ) ) return false ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( ! FrameSize || FrameSize > Subtarget . getRedZoneSize ( ) ) return false ; if ( hasFP ( MF ) || RegInfo -> hasBasePointer ( MF ) || MF . exposesReturnsTwice ( )


<s> TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym ) ; OutStreamer . EmitLabel ( CurrentFnSym


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( softFloat ) FS += FS . empty ( ) ?


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ResValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ResValue ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ResValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ResValue ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ResValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ResValue ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) ,


<s> mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - <NUM_LIT> ; regno = SPARC_FP_ARG_FIRST + slotno * <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - <NUM_LIT> ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != RECORD_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; } else { int intregs_p = <NUM_LIT> , fpregs_p = <NUM_LIT> , packed_p = <NUM_LIT> ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = <NUM_LIT> ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named )


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> unsigned Op = Win64EH :: UOP_AllocSmall ; if ( Size >= <NUM_LIT> ) Op = Win64EH :: UOP_AllocLarge ; else if ( Size >= <NUM_LIT> ) Op = Win64EH :: UOP_AllocMedium ; EmitARM64WinUnwindCode ( Op , -


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << <STR_LIT> ; return false ; } case 'D' : case


<s> return parseIdentifier ( ) ; case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : if ( ! Parser . parseExpression ( ExprVal ) ) return <STR_LIT> ( ExprVal , Start , End ) ; LLVM_FALLTHROUGH ; default : return nullptr


<s> unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } Register ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg )


<s> buildCallOperands ( Ops , CFlags , dl , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget ) ; if ( CFlags . IsTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { { <STR_LIT> , <STR_LIT> } } ; Chain = DAG . getNode ( CallOpc , dl , ReturnTypes , Ops ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; int BytesCalleePops = ( CFlags . CallConv == CallingConv :: Fast && getTargetMachine ( ) .

Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; if ( Lane == <NUM_LIT> ) BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Ws , <NUM_LIT> , <STR_LIT> ) ; else { unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ,

Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ;


<s> if ( S1 && S2 && strcmp ( S1 , S2 ) == <NUM_LIT> ) return true ; return false


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg (


<s> const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> << Log2 ( BBI . PostAlign ) << format ( <STR_LIT> , BBInfo [


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost (


<s> Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , RoundVT , Pg , Val , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( RoundVT ) ) ; Val = getSVESafeBitCast ( ContainerSrcVT . changeTypeToInteger ( ) , Val , DAG ) ; Val = convertFromScalableVector ( DAG , SrcVT . changeTypeToInteger ( ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , VT .


<s> static unsigned sizeGlobalAddress ( bool dword


<s> bool IsFadd = N -> getOpcode ( ) == <STR_LIT> ; auto HorizOpcode = IsFadd ? <STR_LIT> : <STR_LIT> ; assert ( ( IsFadd || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > PostShuffleMask ; if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( HorizOpcode , LHS , RHS , DAG , Subtarget , IsFadd , PostShuffleMask ) ) { SDValue HorizBinOp = DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ; if ( ! PostShuffleMask . empty ( ) ) HorizBinOp = DAG . getVectorShuffle ( VT , SDLoc ( HorizBinOp ) , HorizBinOp , DAG . getUNDEF ( VT ) , PostShuffleMask ) ; return HorizBinOp ; } return SDValue


<s> return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned Base , Index ; const MCExpr * Expr , * Length ; if ( parseAddress ( Base , Expr , Index , Length , <STR_LIT> , ADDR64Reg ) ) return true ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( Base || Index || Length ) Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc


<s> break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>=


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( ( int8x8_t )


<s> SectionKind GVKind ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( GV -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( GV , TM ) : getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) , TM ) ) ; GVSym -> setContainingCsect ( Csect ) ; if ( GV -> isDeclaration ( ) ) return ; if ( ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; OutStreamer -> SwitchSection (


<s> bool isNEONi32splat ( ) const { if ( isNEONByteReplicate ( <NUM_LIT> ) ) return false ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE -> getValue ( ) ; return <STR_LIT> (


<s> Inst . addOperand ( MCOperand :: CreateImm ( getVectorIndex ( ) )


<s> unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) . addImm ( <NUM_LIT> - Size ) .

addImm ( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


<s> Triple TheTriple ( TT ) ; MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> ,


<s> return static_cast < MCELFStreamer & > (


<s> return createMacroFusionDAGMutation (


<s> Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: Address S = pReloc . symValue ( ) ; pReloc . target ( ) = S


<s> <ISA_LIT>LoadStoreOpt ( ) : MachineFunctionPass ( ID


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm


<s> if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; if ( TLI -> allowsMisalignedMemoryAccesses ( LT . second , <NUM_LIT> ) ) return Cost ; Cost += LT . first * ( SrcBytes / Alignment - <NUM_LIT> ) ; if ( Src -> isVectorTy ( ) && Opcode == Instruction :: Store ) for ( int i = <NUM_LIT> , e = Src -> getVectorNumElements ( ) ; i < e ; ++ i ) Cost += getVectorInstrCost

( Instruction :: ExtractElement , Src , i ) ;


<s> if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT>


<s> static void fold_compare_helper ( gimple_stmt_iterator * gsi , tree_code code , gimple * stmt ) { tree arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree cmp = fold_build_vec_cmp ( code , TREE_TYPE ( lhs ) , arg0 , arg1 , gsi ) ; gimple * g = gimple_build_assign ( lhs


<s> if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] .


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op ,


<s> void <ISA_LIT>FrameLowering :: BuildStackAlignAND ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , unsigned Reg , uint64_t MaxAlign ) const { uint64_t Val = - MaxAlign ; unsigned AndOp = getANDriOpcode ( Uses64BitFramePtr , Val ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) , Reg ) . addReg ( Reg ) . addImm (

Val ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == TargetOpcode :: FRAME_ALLOC ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; bool IsWinEH = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int Offset ; if ( IsWinEH ) Offset = static_cast < const <ISA_LIT>FrameLowering * > ( TFI ) -> getFrameIndexOffsetFromSP ( MF , FrameIndex ) ; else Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea (


<s> addr = XEXP ( mem , <NUM_LIT> ) ; struct csky_address caddr ; decompose_csky_address ( addr , & caddr ) ; ops [ <NUM_LIT> ] = reg ; ops [ <NUM_LIT> ] = mem ; sprintf ( buff , templ , isload ? <STR_LIT> : <STR_LIT> , caddr . index ? <STR_LIT> : <STR_LIT> , type ) ; output_asm_insn ( buff , ops ) ; return <STR_LIT>


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT


<s> if ( ! fitsIntoCurrentGroup ( SU ) ) nextGroup ( ) ; DEBUG ( raw_string_ostream cgd ( CurGroupDbg ) ; if ( CurGroupDbg . length ( ) ) cgd << <STR_LIT> ; dumpSU ( SU , cgd ) ; ) ; LastEmittedMI = SU -> getInstr ( ) ; if ( SU -> isCall ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; Reset ( ) ; LastEmittedMI = SU -> getInstr ( ) ; return ; } for ( TargetSchedModel :: ProcResIter PI = SchedModel -> getWriteProcResBegin ( SC ) , PE = SchedModel -> getWriteProcResEnd ( SC ) ; PI != PE ; ++ PI ) { if ( SchedModel -> getProcResource ( PI -> ProcResourceIdx ) -> BufferSize


<s> if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_SPE_WORD - <NUM_LIT> ) / UNITS_PER_SPE_WORD ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_ALTIVEC_WORD - <NUM_LIT> ) / UNITS_PER_ALTIVEC_WORD ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT>


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo ->


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> + getReg ( ) - <STR_LIT>


<s> static unsigned getMatchingLoType ( const MCAssembler & Asm , const ELFRelocationEntry & Reloc ) { unsigned Type = Reloc . Type ; if ( Type == ELF :: R_MIPS_HI16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_HI16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_HI16 ) return ELF :: R_MIPS16_LO16 ; const MCSymbolData & SD = Asm . getSymbolData ( * Reloc . Symbol ) ; if ( MCELF :: GetBinding ( SD ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_GOT16 ) return ELF


<s> case E_V2BFmode : case E_V4HFmode : case E_V4BFmode : case E_V2SFmode : for ( int i = <NUM_LIT> ; i < nunits ; ++ i ) { rtx x = XVECEXP ( op , <NUM_LIT> , i ) ; int v = real_to_target ( NULL , CONST_DOUBLE_REAL_VALUE ( x ) , REAL_MODE_FORMAT ( innermode ) ) ; wide_int wv = wi :: shwi ( v , innermode_bits ) ; val = wi :: insert ( val , wv , innermode_bits * i , innermode_bits ) ; } break ; default : gcc_unreachable ( ) ; } return val . to_shwi


<s> if ( VectorList . ElementKind != ElementKind ) return false ; return VectorList . NumElements


<s> return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl ,