<s> if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( * MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) { int SecondScratchReg = BV . find_next ( * SR1 ) ; if ( SecondScratchReg != - <NUM_LIT> ) * SR2


<s> return <ISA_LIT>ABIInfo ( ABI :: O32


<s> unsigned <ISA_LIT>TargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor (


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( ( ( ! isGP64bit ( ) && isABI_O32 ( ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } if ( hasMSA ( ) && ! MSAWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r5 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; MSAWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r5 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; MSAWarningPrinted = true ; } } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this )


<s> else if ( ( classify & RS6000_BTC_PURE ) != <NUM_LIT> ) { DECL_PURE_P ( t ) = <NUM_LIT> ; TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_FP ) != <NUM_LIT> ) { TREE_NOTHROW ( t ) = <NUM_LIT> ; if ( flag_rounding_math ) { DECL_PURE_P ( t ) = <NUM_LIT> ; DECL_IS_NOVOPS ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else { TREE_READONLY ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } } else if ( ( classify & ( RS6000_BTC_QUAD | RS6000_BTC_PAIR ) ) != <NUM_LIT> ) ; else if ( ( classify & RS6000_BTC_ATTR_MASK


<s> SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch ( access ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createLo ( Expr ,


<s> if ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) { bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch_bti_j_insn_p ( next ) ) continue ; bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = aarch_gen_bti_c (


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand ::


<s> reportParseError ( <STR_LIT> ) ; return false ; } clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMt ( ) ; Parser . Lex ( ) ; return false


<s> switch ( getTargetLowering ( ) -> getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : { unsigned Alignment = getTargetLowering ( ) -> getDataLayout ( ) -> getABITypeAlignment ( CV -> getType ( ) ) ; return CurDAG -> getNode ( <STR_LIT> , DL , PtrVT , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getConstant ( Alignment , <STR_LIT> ) ) ; } case CodeModel :: Large : { SDNode * LitAddr ; LitAddr = CurDAG -> getMachineNode ( <STR_LIT> , DL , PtrVT , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; LitAddr = CurDAG -> getMachineNode ( <STR_LIT> , DL , PtrVT , SDValue ( LitAddr , <NUM_LIT> ) , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; LitAddr = CurDAG -> getMachineNode ( <STR_LIT> , DL , PtrVT , SDValue ( LitAddr , <NUM_LIT> ) , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; LitAddr = CurDAG -> getMachineNode ( <STR_LIT> , DL , PtrVT , SDValue ( LitAddr , <NUM_LIT> ) , CurDAG -> getTargetConstantPool ( CV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return SDValue ( LitAddr , <NUM_LIT> ) ; } default : llvm_unreachable (


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed


<s> const Value * Op = BO ; unsigned Stages = Log2_32 ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != Stages ; ++ i ) { const auto * BO = dyn_cast < BinaryOperator > ( Op ) ; if ( ! BO || BO -> getOpcode ( ) != Instruction :: Add ) return nullptr ; if ( EE . getParent ( ) != BO -> getParent ( ) ) ReduceInOneBB = false ; if ( i != <NUM_LIT> && ! BO -> hasNUses ( <NUM_LIT> ) ) return nullptr ; Value * LHS = BO -> getOperand ( <NUM_LIT> ) ; Value * RHS = BO -> getOperand ( <NUM_LIT> ) ; auto * Shuffle = dyn_cast < ShuffleVectorInst > ( LHS ) ; if ( Shuffle ) { Op = RHS ; } else { Shuffle = dyn_cast < ShuffleVectorInst > ( RHS ) ; Op = LHS ; } if ( ! Shuffle || Shuffle -> getOperand ( <NUM_LIT> ) != Op ) return nullptr ; unsigned MaskEnd = <NUM_LIT> << i


<s> LLVMContext * Context = DAG . getContext ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; if ( VT . isVector ( ) ) EltVT = VT . getVectorElementType ( ) ; Constant * C ; if ( EltVT == <STR_LIT> ) { C = ConstantVector :: getSplat ( <NUM_LIT> , ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; } else { C = ConstantVector :: getSplat ( <NUM_LIT> , ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> <<


<s> inline const MachineInstrBuilder & addRegOffset ( const MachineInstrBuilder & MIB , unsigned Reg , bool isKill


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> static MCOperand createPCXCallOP ( MCSymbol * Label , MCContext & OutContext ) { return create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None


<s> return DecodeVecShiftLImm ( Inst , Imm ,


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetMacro


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII


<s> if ( CPU . empty ( ) ) { CPU = <STR_LIT> ; if ( TT . getArchName ( ) == <STR_LIT> ) CPU = <STR_LIT> ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx


<s> FuncInfo -> setVarArgsFPOffset ( ArgGPRs . size ( ) * <NUM_LIT> + NumXMMRegs * <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateStackObject ( ArgGPRs . size ( ) * <NUM_LIT> + ArgXMMs . size ( ) * <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { TheMachineFunction . getRegInfo ( ) . addLiveIn ( Reg ) ; LiveXMMRegs . push_back ( DAG . getRegister ( Reg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Offset = FuncInfo -> getVarArgsGPOffset ( ) ; for ( SDValue Val : LiveGPRs ) { SDValue FIN = DAG . getNode ( <STR_LIT> , DL , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) , RSFIN , DAG . getIntPtrConstant ( Offset , DL ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FuncInfo -> getRegSaveFrameIndex ( )


<s> if ( IsStackReg ( Op . getMemBaseReg ( ) ) ) Displacement -= OrigSPOffset ; if ( IsStackReg ( Op . getMemIndexReg ( ) ) ) Displacement -= OrigSPOffset * Op . getMemScale ( ) ; assert ( Displacement >= <NUM_LIT> ) ; if ( Displacement == <NUM_LIT> ) { EmitLEA ( Op , Size , Reg , Out ) ; return ; } int64_t Residue


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; bool DoMerge = false ; <STR_LIT> Mode = <STR_LIT> ( Opcode ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = std :: prev ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } else if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase


<s> if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { printPCLabel ( MI , Op + <NUM_LIT> ) ; return ; } const MachineOperand & MO1 = MI


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( )


<s> EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted ,


<s> if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else { auto ext = std :: find_if ( std :: begin ( ExtensionMap ) , std :: end ( ExtensionMap ) , [ & ] ( const Extension & e ) { return ( FBS & e .


<s> unsigned Domain = TID . TSFlags & <STR_LIT> ; if ( TID . mayStore ( ) ) return false ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; if ( ( Domain & <STR_LIT> ) || ( Domain & <STR_LIT> ) ) return MI -> readsRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & TRI ) ; return


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizePICCallPass ( <ISA_LIT>TargetMachine & TM ) { return new OptimizePICCall (


<s> break ; } d = bdesc_paired_preds ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_paired_preds ) ; i ++ , d ++ ) if ( d -> code == fcode ) return paired_expand_predicate_builtin ( d -> icode , exp , target ) ; * expandedp =


<s> LoadInst * WideLd1 = WideLoads . count ( VecLd1 [ <NUM_LIT> ] ) ? WideLoads [ VecLd1 [ <NUM_LIT> ] ] -> getLoad ( ) : CreateWideLoad ( VecLd1 , Ty ) ; Value * Args [ ] = { WideLd0 , WideLd1 , Acc } ; Function * SMLAD = nullptr ; if ( Exchange ) SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; else SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; CallInst * Call = Builder . CreateCall ( SMLAD , Args ) ; NumSMLAD


<s> void <ISA_LIT>InstPrinter :: printVPTPredicateOperand ( const MCInst * MI , unsigned OpNum

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> if ( MI . implicit_operands ( ) . empty ( ) ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >=


<s> SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT , Cond ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( CondVT ) ) return SDValue ( ) ; if ( TValIsAllOnes ) { SDValue CastRHS = DAG . getBitcast ( CondVT , RHS ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastRHS ) ; return DAG . getBitcast ( VT , Or ) ; } if ( FValIsAllZeros ) { SDValue CastLHS = DAG . getBitcast ( CondVT , LHS ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastLHS ) ; return DAG . getBitcast ( VT , And ) ; } return SDValue (


<s> const char * output_ieee_ccmpeq ( rtx insn ,


<s> Op -> Mem . ShiftVal = <NUM_LIT> ; Op -> Mem . ExplicitShift = false ; Op -> Mem . Mode = ImmediateOffset ; Op -> OffsetLoc = OffsetLoc ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> ; bool HasRs = false ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm


<s> SDValue TlsGetAddr = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = PtrTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , PtrTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , TlsGetAddr , Args , DAG , DL ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , DL ,


<s> rtx_insn * insn ; if ( add_operand ( rs , Pmode ) ) insn = emit_insn ( gen_add3_insn ( end_addr , stack_pointer_rtx , rs ) ) ; else { emit_move_insn ( end_addr , GEN_INT ( - rounded_size ) ) ; insn = emit_insn ( gen_add3_insn ( end_addr , end_addr , stack_pointer_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( end_addr , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , rs ) ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( TARGET_64BIT ) retval = emit_insn ( gen_probe_stack_rangedi ( stack_pointer_rtx , stack_pointer_rtx , orig_sp , end_addr ) ) ; else retval = emit_insn ( gen_probe_stack_rangesi ( stack_pointer_rtx , stack_pointer_rtx , orig_sp , end_addr ) ) ; RTX_FRAME_RELATED_P ( retval ) = <NUM_LIT> ; add_reg_note ( retval , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , end_addr ) ) ; emit_insn ( gen_blockage ( )


<s> MVT DstVT ; Type * RetTy = I -> getType ( ) ; if ( ! isTypeLegal ( RetTy , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc = isSigned


<s> MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == <NUM_LIT> ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == <NUM_LIT> || SlotSize == <NUM_LIT> ) ; unsigned RegA = ( SlotSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; case Sub : assert ( Amount > <NUM_LIT> ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; break ; } unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ; MachineInstr * AmountDef = MRI ->


<s> tree t , u ; unsigned int size , ofs ; bool indirect ; indirect = pass_va_arg_by_reference ( type ) ; if ( indirect ) { type = ptr ; ptr = build_pointer_type ( type ) ; } size = int_size_in_bytes ( type ) ; valist_type = TREE_TYPE ( valist ) ; u = fold_convert ( sizetype , size_in_bytes ( type ) ) ; u = fold_build1 ( NEGATE_EXPR , sizetype , u ) ; t = fold_build_pointer_plus ( valist , u ) ; u = build_int_cst ( TREE_TYPE ( t ) , ( HOST_WIDE_INT ) ( size > <NUM_LIT> ? - <NUM_LIT> : - <NUM_LIT> ) ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , u ) ; t = fold_convert ( valist_type , t ) ; t = build2 ( MODIFY_EXPR , valist_type , valist ,


<s> RegisterTarget < Triple :: arm64_be , true > Y ( TheARM64beTarget , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: aarch64 , true > Z ( The<ISA_LIT>leTarget ,


<s> uint64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t UImm = Imm << ( <NUM_LIT> - BitSize ) >> ( <NUM_LIT> - BitSize ) ; uint64_t Encoding ; return <STR_LIT> ( UImm ,


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M , MCContext * C


<s> static bool isCombineInstrCandidateFP ( const MachineInstr & Inst ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; if ( ! isStub ) * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = NewVal ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) { * ( unsigned char * ) ( RetAddr - <NUM_LIT> ) = <NUM_LIT> ; * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = diff & <NUM_LIT> ; } else


<s> const char * <ISA_LIT>Relocator :: getName ( Relocator :: Type pType ) const { return ApplyFunctions [ pType ]


<s> if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; SDValue SelectOp , Phi ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SelectOp = Op0 ; Phi = Op1 ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SelectOp = Op1 ; Phi = Op0 ; } else return SDValue ( ) ; if ( ! detectZextAbsDiff ( SelectOp , Op0 , Op1 ) ) return SDValue ( ) ; SDValue Sad = createPSADBW ( DAG , Op0 , Op1 , DL ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , Sad . getValueSizeInBits ( ) / <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) >= ResVT . getSizeInBits ( ) ) Sad = DAG . getNode ( <STR_LIT> , DL , ResVT , Sad ) ; else Sad = DAG . getNode ( <STR_LIT> , DL , VT , Sad ) ; if ( VT . getSizeInBits ( ) > ResVT . getSizeInBits ( ) ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; Sad = DAG . getNode ( <STR_LIT> , DL , VT , Zero , Sad , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Sad , Phi


<s> if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 )


<s> regno += <NUM_LIT> ; fpu_insn = emit_move_insn ( reg , mem ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , NULL_RTX ) ; RTX_FRAME_RELATED_P ( fpu_insn ) = <NUM_LIT> ; REG_NOTES ( fpu_insn


<s> unsigned OutgoingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) { LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg ,


<s> for ( Instruction & I : * BB ) { CallSite CS ( & I ) ; if ( ! isStateStoreNeeded ( Personality , CS ) ) continue ; int State = getStateForCallSite ( BlockColors , FuncInfo , CS ) ; if ( InitialState == OverdefinedState ) InitialState = State ; FinalState = State ; } if ( InitialState == OverdefinedState ) { Worklist . push_back ( BB ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << InitialState << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << FinalState << '\n' ) ; InitialStates . insert ( { BB , InitialState } ) ; FinalStates . insert ( { BB , FinalState } ) ; } while ( ! Worklist . empty ( ) ) { BasicBlock * BB = Worklist . front ( ) ; Worklist . pop_front ( ) ; if ( InitialStates . count ( BB ) != <NUM_LIT> ) continue ; int PredState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; if ( PredState == OverdefinedState ) continue ; InitialStates . insert ( { BB , PredState } ) ; FinalStates . insert ( { BB , PredState } ) ; for ( BasicBlock * SuccBB : successors ( BB ) ) Worklist . push_back ( SuccBB ) ; } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB ) { CallSite CS ( & I ) ; if ( ! isStateStoreNeeded ( Personality , CS ) ) continue ; int State = getStateForCallSite ( BlockColors , FuncInfo , CS ) ; if ( State != PrevState ) insertStateNumberStore ( & I , State ) ; PrevState = State ; } auto EndState = FinalStates . find ( BB ) ; if ( EndState != FinalStates . end ( ) ) if ( EndState -> second != PrevState ) insertStateNumberStore ( BB -> getTerminator ( ) , EndState -> second ) ; } SmallVector < CallSite ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( result == <NUM_LIT> ) result = <NUM_LIT> ; else if ( result != <NUM_LIT> ) result = - <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( result == <NUM_LIT> ) result = <NUM_LIT> ; else if ( result != <NUM_LIT> ) result = - <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ; } switch ( mode ) { case SFmode : case DFmode : case XFmode : case QImode : case HImode : case SImode : simple : tmp = ix86_expand_compare ( code , op0 , op1 ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; return ; case DImode : if ( TARGET_64BIT ) goto simple ; if ( ! optimize_insn_for_size_p ( ) && TARGET_STV && ( code == EQ || code == NE ) ) { op0 = force_reg ( mode , gen_rtx_XOR ( mode , op0 , op1 ) ) ; op1 = const0_rtx ; } case TImode : { rtx lo [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ; rtx_code_label * label2 ; enum rtx_code code1 , code2 , code3 ; machine_mode submode ; if ( CONSTANT_P ( op0 ) && ! CONSTANT_P ( op1 ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } split_double_mode ( mode , & op0 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; split_double_mode ( mode , & op1 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; submode = mode == DImode ? SImode : DImode ; if ( ( code == EQ || code == NE ) && ( ! optimize_insn_for_size_p ( ) || hi [ <NUM_LIT> ] == const0_rtx || lo [ <NUM_LIT> ] == const0_rtx ) ) { rtx xor0 , xor1 ; xor1 = hi [ <NUM_LIT> ] ; if ( hi [ <NUM_LIT> ] != const0_rtx ) xor1 = expand_binop ( submode , xor_optab , xor1 , hi [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; xor0 = lo [ <NUM_LIT> ] ; if ( lo [ <NUM_LIT> ] != const0_rtx ) xor0 = expand_binop ( submode , xor_optab , xor0 , lo [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp = expand_binop ( submode , ior_optab , xor1 , xor0 , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; ix86_expand_branch ( code , tmp , const0_rtx , label ) ; return ; } if ( CONST_INT_P ( hi [ <NUM_LIT> ] ) ) switch ( code ) { case LT : case LTU : case GE :


<s> unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ABS8

) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ABS16 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_ABS32 ) . Default ( - <NUM_LIT> ) ;


<s> if ( TARGET_FLAT ) return false ; return ! ( crtl -> is_leaf


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend


<s> void EmitARM64WinCFISaveRegPX ( unsigned Reg ,


<s> gcc_assert ( TARGET_SHMEDIA ) ; switch ( code ) { case EQ : case GT : case LT : case UNORDERED : case GTU : case LTU : tmp = gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ; emit_insn ( gen_cstore4_media ( target , tmp , op0 , op1 ) ) ; code = NE ; break ; case NE : case GE : case LE : case ORDERED : case GEU : case LEU : tmp = gen_rtx_fmt_ee ( reverse_condition ( code ) , mode , op0 , op1 ) ; emit_insn ( gen_cstore4_media ( target , tmp , op0 , op1 ) ) ; code = EQ ; break ; case UNEQ : case UNGE : case


<s> for ( i = <NUM_LIT> ; i != NumElts ; ++ i ) { Val = SVOp -> getMaskElt ( i ) ; if ( Val >= <NUM_LIT> ) break ; } if ( Val >= ( int ) NumElts


<s> enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = <NUM_LIT> , one_var = - <NUM_LIT> ; bool all_same = true , all_const_zero = true ; rtx x , mem ; int i ; for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! CONSTANT_P ( x ) ) ++ n_var , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > <NUM_LIT> && ! rtx_equal_p ( x , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) all_same = false ; } if ( n_var == <NUM_LIT> ) { if ( mode != V4SFmode && all_const_zero ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_XOR ( mode , target , target ) ) ) ; return ; } else if ( mode != V4SFmode && easy_vector_constant ( vals , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , vals ) ) ; return ; } else if ( all_same ) ; else { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ) ; return ; } } if ( all_same ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , <NUM_LIT> ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , target , mem ) , x ) ) ) ; x = gen_rtx_VEC_SELECT ( inner_mode , target , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals

, <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ;


<s> RegisterTarget < Triple :: sparc > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcv9 > Y ( The<ISA_LIT>V9Target , <STR_LIT> ,


<s> bool isTargetILP32 ( ) const { return TargetTriple .


<s> if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && Subtarget . hasSSE2 ( ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind


<s> } emitRX ( <STR_LIT> , DstReg , MCOperand :: createExpr ( HighestExpr ) , IDLoc , Instructions ) ; emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , DstReg , DstReg , MCOperand :: createExpr ( HigherExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRR ( <STR_LIT> , DstReg , DstReg , ATReg , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( <STR_LIT> , DstReg , DstReg , SrcReg , IDLoc , Instructions ) ; return false ; } unsigned TmpReg = DstReg ; if ( UseSrcReg && getContext ( ) . getRegisterInfo ( ) -> isSuperOrSubRegisterEq ( DstReg , SrcReg ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } emitRX ( <STR_LIT> , TmpReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , Instructions ) ; emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( <STR_LIT> , DstReg ,

TmpReg , SrcReg , IDLoc , Instructions ) ;


<s> static SDValue getMOVLP ( SDValue & Op , DebugLoc & dl , SelectionDAG & DAG , bool HasSSE2 ) { SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; bool CanFoldLoad = false ; if ( MayFoldVectorLoad ( V2 ) ) CanFoldLoad = true ; else if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op


<s> inline unsigned getPredicateHint ( Predicate Opcode ) { return ( unsigned ) ( Opcode & BR_HINT_MASK


<s> if ( SrcVT . getScalarSizeInBits ( ) == <NUM_LIT> || ! Subtarget . hasAVX2 ( ) ) return false ; if ( is128BitLaneCrossingShuffleMask ( SrcVT . getSimpleVT ( ) , ShuffleMask ) ) return false ; return true


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; auto & STI = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasAES ( ) || ! STI . fixCortexA57AES1742098 ( ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = STI . getRegisterInfo ( ) ; const <ISA_LIT>BaseInstrInfo * TII = STI . getInstrInfo ( ) ; auto & RDA = getAnalysis < ReachingDefAnalysis > ( ) ; SmallVector < AESFixupLocation > FixupLocsForFn


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT>


<s> void <ISA_LIT>MachOTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine


<s> if ( EnableMachineCombinerPass ) addPass ( &


<s> ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( ! mnemonicIsValid ( Name , <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; return Error ( NameLoc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc ,


<s> if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Inst . getOpcode ( ) == <STR_LIT> && Val == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; if ( Val == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success


<s> assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> ) return false ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DemoteRegTo32 ( SrcReg ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( FlagUseZeroBasedSandbox ) return false ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } DEBUG ( DumpInstructionVerbose ( MI )


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else instantiateCondBranch ( MBB , DL , TBB , Cond ) ; return <NUM_LIT> ; } instantiateCondBranch ( MBB , DL , TBB , Cond ) ; BuildMI ( & MBB , DL , get (


<s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ,


<s> void * ptr ; lasterror = GetLastError ( ) ; ptr = TlsGetValue ( key ) ; SetLastError (


<s> if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody (


<s> unsigned J2 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm32 ) ) ; return MCDisassembler ::


<s> return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , vec_sub ( ( ( vec_float4 ) { <NUM_LIT> } )


<s> if ( regno >= V0_REGNUM && regno < V0_REGNUM

+ HA_MAX_NUM_FLDS ) return ! TARGET_GENERAL_REGS_ONLY ;


<s> int Half = NumElems / <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Half ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i

] , NumElems , NumElems * <NUM_LIT> ) ) return false ;


<s> bool hfp = frame_pointer_needed || stack_realign_fp ; unsigned i ; for ( i = <NUM_LIT> ; i < count ; ++ i ) { gcc_assert ( i < MAX_REGS ) ; if ( REG_ORDER [ i ] == BP_REG && hfp ) ++ count ; else if ( REG_ORDER [ i ] == regno ) return true ; } return


<s> SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; AM . Scale = <NUM_LIT> << ShiftAmt ; AM . IndexReg =


<s> bool legitimate_pic_operand_p ( rtx x ) { if ( pic_address_needs_scratch ( x ) ) return false ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ; return true


<s> return decodeRegisterClass ( Inst , RegNo


<s> if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ <NUM_LIT> ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & <NUM_LIT>


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; bool NeedsStackRealignment = RegInfo . needsStackRealignment ( MF ) ; if ( ! NeedsStackRealignment && MFI . getMaxAlignment ( ) > getStackAlignment ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> ,


<s> assert ( Fixup . getOffset ( ) + Size <= Data . size ( ) && <STR_LIT> ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; if ( ( Target . isAbsolute ( ) || IsResolved ) && getFixupKindInfo ( Fixup . getKind ( ) ) . Flags & MCFixupKindInfo :: FKF_IsPCRel ) { if ( Size > <NUM_LIT> && ! isIntN ( Size * <NUM_LIT> , SignedValue ) ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SignedValue ) + <STR_LIT> + Twine ( Size ) + ( ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; }


<s> static SDValue getTargetShuffleNode ( unsigned Opc , DebugLoc dl , EVT VT , SDValue V1 , SDValue V2 , unsigned TargetMask , SelectionDAG & DAG ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo &


<s> ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass


<s> if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ; return


<s> DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue


<s> return ( __mmask16 ) __builtin_ia32_cmpd512_mask ( ( __v16si ) __X , (


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Size = <NUM_LIT> ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits


<s> return ( __m128i ) __builtin_ia32_vpshld_v8hi_mask ( ( __v8hi ) __B , ( __v8hi ) __C , __D , ( __v8hi ) _mm_setzero_si128 ( ) , (


<s> for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) StoreVal |= ByteVal << ( I * <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstant ( StoreVal , DL , <STR_LIT> (

Size * <NUM_LIT> ) ) , Dst , DstPtrInfo , Align ) ;


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op


<s> Op -> MMask . Val = MMask ; Op -> StartLoc = S


<s> set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode


<s> if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true ,

<NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC ) ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( CopyVT . isVector ( ) && ! Subtarget -> isLittleEndian ( ) )


<s> if ( Imm == <NUM_LIT> || Imm == Mask || <STR_LIT> ( Imm & Mask , Size ) ) return false ; unsigned EltSize = Size ; uint64_t DemandedBits = Demanded . getZExtValue ( ) ; Imm &= DemandedBits ; while ( true ) { uint64_t NonDemandedBits = ~ DemandedBits ; uint64_t InvertedImm = ~ Imm & DemandedBits ; uint64_t RotatedImm = ( ( InvertedImm << <NUM_LIT> ) | ( InvertedImm >> ( EltSize - <NUM_LIT> ) & <NUM_LIT> ) ) & NonDemandedBits ; uint64_t Sum = RotatedImm + NonDemandedBits ; bool Carry = NonDemandedBits & ~ Sum & ( <NUM_LIT> << ( EltSize - <NUM_LIT> ) ) ; uint64_t Ones = ( Sum + Carry ) & NonDemandedBits ; NewImm = ( Imm | Ones ) & Mask ; if ( isShiftedMask_64 ( NewImm ) || isShiftedMask_64 ( ~ ( NewImm | ~ Mask ) ) ) break ; if ( EltSize == <NUM_LIT> ) return false ; EltSize /= <NUM_LIT> ; Mask >>= EltSize ; uint64_t Hi = Imm >> EltSize , DemandedBitsHi = DemandedBits >> EltSize ; if ( ( ( Imm ^ Hi ) & ( DemandedBits & DemandedBitsHi ) & Mask ) != <NUM_LIT> ) return false ; Imm |= Hi ; DemandedBits |= DemandedBitsHi ; } ++ NumOptimizedImms ; while ( EltSize < Size ) { NewImm |= NewImm << EltSize ; EltSize *= <NUM_LIT> ; } ( void ) OldImm ; assert ( ( ( OldImm ^ NewImm ) & Demanded . getZExtValue ( ) ) == <NUM_LIT> && <STR_LIT> ) ; assert ( OldImm != NewImm && <STR_LIT> ) ; EVT VT = Op . getValueType (


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup .


<s> if ( ! canEmitConjunction ( Val , DummyCanNegate , DummyMustBeFirst , false , * MIB . getMRI ( ) ) ) return nullptr ; return emitConjunctionRec ( Val , OutCC , false , Register ( ) ,


<s> rtx mask = gen_reg_rtx ( cmp_result_mode ) ; bool inverted = arm_expand_vector_compare ( mask , GET_CODE ( operands [ <NUM_LIT> ] )

, operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , true ) ;


<s> if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass ( create<ISA_LIT>Os16 ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . in<ISA_LIT>16HardFloat ( ) ) addPass ( create<ISA_LIT>16HardFloat (


<s> int single_const_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( big_const_operand ( op , mode ) || GET_CODE ( op ) == CONST || GET_CODE ( op ) ==

LABEL_REF || GET_CODE ( op ) == SYMBOL_REF ) return <NUM_LIT> ;


<s> return ( int16x4_t ) __builtin_neon_vqabsv4hi ( __a )


<s> SDNodeFlags Flags = Op . getNode ( ) -> getFlags ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; if ( ! Flags . hasNoSignedZeros ( ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true


<s> case GPRnopcRegClassID : case tGPR_and_tcGPRRegClassID : case tGPRRegClassID : return getRegBank ( <STR_LIT> ) ; case SPR_8RegClassID : case SPRRegClassID : case DPR_8RegClassID : case DPRRegClassID : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> )


<s> FunctionPass * llvm :: create<ISA_LIT>TOCRegDepsPass ( ) { return new <ISA_LIT>TOCRegDeps


<s> return ! getReservedRegs ( MF ) . test ( PhysReg


<s> return ( __m256i ) __builtin_ia32_psrldi256 ( ( __v8si ) __A ,


<s> if ( <STR_LIT> . contains ( SrcReg ) ) return Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; return <NUM_LIT>


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isSingleInputShuffleMask ( Mask ) ) { SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) { PSHUFBMask [ <NUM_LIT> * i ] = PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } int M = i < <NUM_LIT> ? Mask [ i ] : Mask [ i ] - <NUM_LIT> ; assert ( M >= <NUM_LIT> && M < <NUM_LIT> && <STR_LIT> ) ; PSHUFBMask [ <NUM_LIT> * i ] = DAG . getConstant ( <NUM_LIT> * M , <STR_LIT> ) ; PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> * M + <NUM_LIT> , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode (

<STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ;


<s> return ( __m128 ) __builtin_ia32_cvtsi2ss ( (


<s> static bool isAlwaysCoarse ( StringRef name ) { if ( name . equals ( <STR_LIT>


<s> break ; case <STR_LIT> : case <STR_LIT> : OpCode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( DstReg == SrcReg ) { unsigned ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; ImmReg = ATReg ; } if ( loadImmediate ( ImmValue , ImmReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue

) , false , IDLoc , Out , STI ) ) return true ;


<s> static bool expand_vec_perm_pblendv ( struct expand_vec_perm_d * d ) { unsigned i , which , nelt = d -> nelt ; struct expand_vec_perm_d dcopy , dcopy1 ; machine_mode vmode = d -> vmode ; bool ok ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) ; else if ( TARGET_AVX && ( vmode == V4DFmode || vmode == V8SFmode ) ) ; else if ( TARGET_SSE4_1 && ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> || ( TARGET_MMX_WITH_SSE && GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) || GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) ) ; else return false ; for ( i = <NUM_LIT> , which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e != i ) which |= ( e < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } if ( which != <NUM_LIT> && which != <NUM_LIT> ) return false ; if ( d -> testing_p && GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) return true ; dcopy = * d ; if ( which == <NUM_LIT> ) dcopy . op0 = dcopy . op1 = d -> op1 ; else dcopy . op0 = dcopy . op1 = d -> op0 ; if ( ! d -> testing_p ) dcopy . target = gen_reg_rtx ( vmode ) ; dcopy . one_operand_p = true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) dcopy . perm [ i ] = d -> perm [ i ] & ( nelt - <NUM_LIT> ) ; ok = expand_vec_perm_1 ( & dcopy ) ; if ( GET_MODE_SIZE ( vmode ) != <NUM_LIT> && ! ok ) return false ; else gcc_assert ( ok ) ; if ( d -> testing_p ) return true ; dcopy1 = * d ; if ( which == <NUM_LIT> ) dcopy1 . op1 = dcopy . target ; else dcopy1 . op0 = dcopy . target ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) dcopy1 . perm [ i ] = ( ( d -> perm [


<s> static Relocator :: DWord helper_insert_val_thumb_movw_movt_inst ( Relocator :: DWord pValue , Relocator :: DWord pImm ) { pValue &= <NUM_LIT> ; pValue |= ( pImm &


<s> ( * PI ) -> insert ( J , MI ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugInstr ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB , true ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size ( ) == <NUM_LIT> ) { MachineBasicBlock & PrevMBB = * * ReturnMBB . pred_begin ( ) ; if ( PrevMBB . isLayoutSuccessor ( & ReturnMBB ) && PrevMBB . canFallThrough ( ) ) { PrevMBB . splice ( PrevMBB . end ( ) ,


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16 ( ) ; else TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveEnt (


<s> bool isVirtualSection ( const MCSection & Section ) const { const MCSectionMachO & SMO = static_cast < const MCSectionMachO & > ( Section ) ; return ( SMO . getType ( ) == MCSectionMachO :: S_ZEROFILL || SMO . getType ( ) == MCSectionMachO :: S_GB_ZEROFILL || SMO . getType

( ) == MCSectionMachO :: S_THREAD_LOCAL_ZEROFILL ) ;


<s> void releaseMemory ( ) override { ShapeBBs . clear ( ) ; DefVisited . clear ( ) ; BBVisitedInfo . clear (


<s> unsigned getGPRCalleeSavedArea1Size ( )


<s> unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr ::


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op ,


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const


<s> unsigned int call_properties ( const function_instance & )


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN


<s> std :: swap ( N0 , N1 ) ; } if ( N0 == N1 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; return DAG . getNode ( Opcode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , N00 ,

N1 ) , DAG . getNode ( <STR_LIT> , DL , VT , N01 , N1 ) ) ;


<s> if ( ImpDefIdx != - <NUM_LIT> ) MI . removeOperand ( ImpDefIdx ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI . getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI . addRegisterKilled ( SrcRegS , TRI , true ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; return true


<s> if ( RHS . getNode ( ) ) LHS = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , DAG . getCondCode ( CC ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { LHS , Chain } , dl ) ; return LHS ; } assert ( ! IsStrict && <STR_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue SetCC32 = DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) , CC ) ; int ShuffV [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue Shuff = DAG . getVectorShuffle ( <STR_LIT> , dl , SetCC32 , SetCC32 , ShuffV ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Shuff , SetCC32 ) ) ; } return Op ; } if ( SDValue V = lowerCmpEqZeroToCtlzSrl ( Op , DAG


<s> return __builtin_aarch64_fcvtzssf ( __a ,


<s> void <ISA_LIT>InstrInfo :: copyPhysRegTuple ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc , unsigned Opcode , ArrayRef < unsigned > Indices ) const { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; uint16_t DestEncoding = TRI -> getEncodingValue ( DestReg ) ; uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned NumRegs = Indices . size ( ) ; int SubReg = <NUM_LIT> , End = NumRegs , Incr = <NUM_LIT> ; if ( forwardCopyWillClobberTuple ( DestEncoding , SrcEncoding , NumRegs ) ) { SubReg = NumRegs - <NUM_LIT> ; End = - <NUM_LIT> ; Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder MIB = BuildMI ( MBB , I


<s> if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI


<s> bool <ISA_LIT>TTIImpl :: areFunctionArgsABICompatible ( const Function * Caller , const Function * Callee , SmallPtrSetImpl < Argument * > & Args ) const { if ( ! BaseT :: areFunctionArgsABICompatible ( Caller , Callee ,


<s> if ( cfun -> machine -> frame . laid_out && aarch64_return_address_signing_enabled ( ) && aarch64_ra_sign_key

== AARCH64_KEY_B ) asm_fprintf ( f , <STR_LIT> ) ;


<s> unsigned RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! getConstantVRegVal ( RHS , MRI ) ) std :: swap ( RHS , LHS ) ; const auto RHSImm = getConstantVRegVal ( RHS , MRI ) ; if ( ! RHSImm || * RHSImm != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; const auto Pred = ( CmpInst :: Predicate ) CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ; const unsigned CmpWidth = MRI . getType ( LHS ) .


<s> int mmix_constant_alignment ( tree constant ATTRIBUTE_UNUSED


<s> assert ( ( BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] <


<s> static DecodeStatus DecodeJumpTarget ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( JumpOffset


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( ) const { return true


<s> if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) == Type :: getFloatTy ( CFP -> getContext ( ) ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) == Type :: getDoubleTy ( CFP -> getContext ( ) ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { llvm_unreachable (


<s> bool Lower = ( Subtarget -> isOSWindows ( ) && ! Subtarget -> isTargetMacho ( ) ) || SplitStack ; SDLoc dl ( Op ) ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDNode * Node = Op . getNode ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue Tmp1 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp2 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp3 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Chain = Tmp1 . getOperand ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDLoc ( Node ) ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * DAG . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 ,


<s> unsigned MaxCallFrameSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; while ( MBBI != MBB -> end ( ) ) { MachineInstr & MI = * MBBI ++ ; if ( MI . getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI . getDebugLoc ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitCMOV ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> static rtx neon_vdup_constant ( rtx vals , bool generate ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > <NUM_LIT> ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; if ( ! generate ) return x ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_vec_duplicate ( mode , x


<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { <ISA_LIT>FunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setIsSplitCSR


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Opcode = MI . getOpcode ( ) ; MCNumEmitted ++ ; EmitInstruction ( getBinaryCodeForInstr ( MI )


<s> bool isBDVAddr64Disp12 ( ) const { return isMemDisp12 ( BDVMem , GR64Reg


<s> return ( uint8x8_t ) __builtin_neon_vsrau_nv8qi ( ( int8x8_t ) __a ,


<s> if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( Res , S


<s> const IntegerType * IntTy = dyn_cast < IntegerType > ( Ty ) ; if ( ! IntTy ) return false ; return IntTy -> getBitWidth ( ) ==


<s> static DecodeStatus DecodeRegExtendOperand ( llvm :: MCInst & Inst , unsigned ShiftAmount , uint64_t Address , const void * Decoder ) { if ( ShiftAmount > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( ShiftAmount ) ) ; return MCDisassembler :: Success


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitEHSjLjLongJmp ( MachineInstr * MI , MachineBasicBlock * MBB ) const { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , SPOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { llvm_unreachable ( <STR_LIT> )


<s> unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs ; else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { unsigned RegNo = CTX . getRegisterInfo ( ) . getEncodingValue ( MI . getOperand ( I ) . getReg ( ) ) ; Binary |= <NUM_LIT> << RegNo ; } } return


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT>


<s> if ( TARGET_MCOUNT_RA_ADDRESS ) { if ( cfun -> machine -> frame . ra_fp_offset == <NUM_LIT> ) fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; else fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , Pmode == DImode ? <STR_LIT> : <STR_LIT> , reg_names [ <NUM_LIT> ] , cfun -> machine -> frame . ra_fp_offset , reg_names [ STACK_POINTER_REGNUM ] ) ; } if ( ! TARGET_NEWABI ) fprintf ( file , <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , reg_names [ STACK_POINTER_REGNUM ] , reg_names [ STACK_POINTER_REGNUM ] , Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; if ( TARGET_LONG_CALLS ) fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; else fprintf ( file , <STR_LIT> ) ; mips_pop_asm_switch ( & mips_noat ) ; if ( cfun -> static_chain_decl != NULL ) fprintf ( file , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ,


<s> const SmallVector < int , <NUM_LIT> > & getLiveIn ( ) const { return


<s> fprintf ( file , <STR_LIT> , cfun -> machine -> local_size ) ; fprintf ( file , <STR_LIT> , cfun -> machine -> out_args_size ) ; fprintf ( file , <STR_LIT> ) ; for ( r = <NUM_LIT> ; r < <NUM_LIT> ; r ++ ) { if ( df_regs_ever_live_p ( r ) ) fprintf ( file , <STR_LIT> , reg_names [ r ] ) ; } fputc ( '\n' , file


<s> EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { int32_t Log2 = ImmValue . exactLogBase2 ( ) ; if ( Log2 != - <NUM_LIT> ) { Imm = CurDAG -> getTargetConstant ( Log2 , SDLoc ( N ) , EltTy ) ; return true ; } } return


<s> Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q' : <STR_LIT> Ty = P . getSubtarget ( ) . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , Ty ) ; break ; } O << '%' << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return


<s> case CallingConv :: C : case CallingConv :: PreserveMost : case CallingConv :: Swift : case CallingConv :: SwiftTail : case CallingConv :: Tail : case CallingConv :: Fast : case CallingConv :: GHC : return true ; default : return


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> getDesc ( ) . mayLoad ( )

&& hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ;


<s> <ISA_LIT>FunctionInfo * AFI = I -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII . get ( ADDriOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) .


<s> Type * ArgTy = ( * II ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) ) return false ; unsigned Arg = getRegForValue ( * II ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * II ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) return false ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB . addReg ( RegArgs [ II ] , RegState :: Implicit ) ; MIB . addRegMask ( TRI .


<s> else Offset = <STR_LIT> ( <STR_LIT> , OffImm , <STR_LIT> ) ; if ( isDef ) BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg , getDefRegState ( true ) | getDeadRegState ( RegDeadKill ) ) . addReg (

BaseReg , getKillRegState ( BaseKill ) ) . addReg ( OffReg , getKillRegState ( OffKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) ; else if ( TheTriple . isOSWindows ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoGNU ( ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = <NUM_LIT> ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand ::


<s> getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { { s32 , s32 } } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s32 } , { s32 , p0 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_GEP , G_INTTOPTR } ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalFor ( { { s32 , p0 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( { G_GLOBAL_VALUE , G_JUMP_TABLE } ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FABS , G_FSQRT } ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalFor ( { { s32 , s32 } , { s32 , s64 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_FCEIL , G_FFLOOR } ) . libcallFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 } , { s64 , s32 } ) . libcallForCartesianProduct ( { s64 } , { s64 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_FPTOUI ) . libcallForCartesianProduct ( { s64 } , { s64 , s32 } ) . lowerForCartesianProduct ( { s32 } , { s64 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s64 , s32 } , { s32 } ) . libcallForCartesianProduct ( { s64 , s32 } , { s64 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_UITOFP ) . libcallForCartesianProduct ( { s64 , s32 } , { s64 } ) . customForCartesianProduct ( { s64 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SEXT_INREG ) . lower ( ) ; computeTables ( ) ; verify ( * ST . getInstrInfo ( )


<s> bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue


<s> vld4q_f32 ( const float32_t * __a ) { float32x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t )


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT>


<s> default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI -> getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned DReg = TRI -> getMatchingSuperReg ( Reg , <STR_LIT> , & <STR_LIT> ) ; if ( ! DReg || ! MI -> definesRegister


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; OperandMatchResultTy ResTy = parseAnyRegister ( Operands ) ; if ( ResTy == MatchOperand_Success ) { assert ( Operands . size ( ) == <NUM_LIT> ) ; <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc ( ) ; EndLoc = Operand . getEndLoc ( ) ; if ( Operand . isGPRAsmReg ( ) ) { RegNo = isGP64bit ( ) ? Operand . getGPR64Reg ( ) : Operand .


<s> bool isTargetWin64 ( ) const { return Is64Bit && isOSWindows (


<s> static void printExpr ( const MCExpr * Expr , raw_ostream & OS ) { int Offset = <NUM_LIT> ; const MCSymbolRefExpr * SRE ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT>


<s> const Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getTargetData ( ) -> getIntPtrType ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back (


<s> switch ( RegEnum ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> } if ( TARGET_ISA_V3 ) { } if ( TARGET_ISA_V3M ) { target_flags |= MASK_REDUCED_REGS ; target_flags &= ~ MASK_PERF_EXT ; } if ( TARGET_REDUCED_REGS ) { int r ; for ( r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs

[ r ] = call_used_regs [ r ] = <NUM_LIT> ;


<s> if ( isLdStPairSuppressed ( MI ) ) return false ; if ( Subtarget . avoidQuadLdStPairs ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } return true


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo

& tri , const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) :