<s> unsigned DesiredHi = TRI -> getSubReg ( Desired . getReg ( ) , <STR_LIT> ) ; LivePhysRegs LiveRegs ( & TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor


<s> static DecodeStatus decodeBDLAddr64Disp12Len8Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const MCDisassembler * Decoder ) { return decodeBDLAddr12Len8Operand ( Inst , Field ,


<s> bool <ISA_LIT>Subtarget :: isLegalToCallImmediateAddr ( ) const { if ( In64BitMode || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) == Reloc


<s> void arm_emit_eabi_attribute ( const char * name , int num , int val ) { asm_fprintf ( asm_out_file , <STR_LIT> , num


<s> if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs , Mask ) ; return true


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleOddSPReg ( ) { <ISA_LIT>TargetStreamer :: emitDirectiveModuleOddSPReg ( ) ; OS << <STR_LIT> << ( ABIFlagsSection . OddSPReg ?


<s> void DecodeVPERMILPMask ( unsigned NumElts , unsigned ScalarBits , ArrayRef < uint64_t > RawMask , const APInt & UndefElts , SmallVectorImpl < int > & ShuffleMask ) { unsigned VecSize = NumElts * ScalarBits ; unsigned NumLanes = VecSize / <NUM_LIT> ; unsigned NumEltsPerLane = NumElts / NumLanes ; assert ( ( VecSize == <NUM_LIT> || VecSize == <NUM_LIT> || VecSize == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( ScalarBits == <NUM_LIT> || ScalarBits == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RawMask . size ( ) ; i < e ; ++ i ) { if ( UndefElts [ i


<s> bool <ISA_LIT>RegisterBankInfo :: onlyDefinesFP ( const MachineInstr & MI , const MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : case TargetOpcode :: G_EXTRACT_VECTOR_ELT : case TargetOpcode :: G_INSERT_VECTOR_ELT


<s> void <ISA_LIT>InstPrinter :: printU6ImmOperand ( const MCInst * MI


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; int RegisterFileMoveCost = <NUM_LIT> ; if ( Index == - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { assert ( isa < FixedVectorType > ( Val ) && <STR_LIT> ) ; Align VecAlign = DL . getPrefTypeAlign ( Val ) ; Align SclAlign = DL . getPrefTypeAlign ( ScalarType ) ; if ( Opcode == Instruction :: ExtractElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } if ( Opcode == Instruction :: InsertElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Store , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index % NumElts ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) { assert ( ( LT . second . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubVecs = LT . second . getSizeInBits ( ) / <NUM_LIT> ; SubNumElts = NumElts / NumSubVecs ; if ( SubNumElts <= Index ) { RegisterFileMoveCost += ( Opcode == Instruction :: InsertElement ? <NUM_LIT> : <NUM_LIT> ) ; Index %= SubNumElts ; } } if ( Index == <NUM_LIT> ) { if ( ScalarType -> isFloatingPointTy ( ) ) return RegisterFileMoveCost ; if ( ScalarType -> isIntegerTy ( ) && Opcode == Instruction :: ExtractElement ) return <NUM_LIT> + RegisterFileMoveCost ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; break ; } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; Inst . addOperand ( MCOperand :: createImm ( shift


<s> switch ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) { case ( <STR_LIT> ) : cond = loadZ ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadC ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadN ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadN , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadV ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadV , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> and_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> or_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadN , loadV ) ; break ; case ( <STR_LIT> ) : cond = ctx -> neq ( <NUM_LIT> , loadN , loadV ) ; break ; case ( <STR_LIT> ) : cond = ctx -> and_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadN , loadV ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> or_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> neq ( <NUM_LIT> , loadN , loadV ) ) ; break ; case ( <STR_LIT> )


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const { return getTargetTriple ( ) . isiOS ( ) && ! getTargetTriple ( ) . isOSVersionLT (


<s> const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( MBB , DL , TII . get ( CopyOpc ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this


<s> switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case <STR_LIT> : expandRetRA ( MBB , MI ) ; break ; case <STR_LIT> : expandERet ( MBB , MI ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , true ) ; break ; case <STR_LIT> : case <STR_LIT> : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase (


<s> MVT StoreSVT = StoreVT . getScalarType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; unsigned ScalarSize = StoreSVT . getStoreSize ( ) ; SDLoc DL ( Store ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Offset = i * ScalarSize ; SDValue Ptr = DAG . getMemBasePlusOffset ( Store -> getBasePtr ( ) , Offset , DL ) ; SDValue Scl = DAG . getNode ( <STR_LIT> , DL , StoreSVT , StoredVal , DAG . getIntPtrConstant ( i , DL ) ) ; SDValue Ch = DAG . getStore ( Store -> getChain ( ) , DL , Scl , Ptr , Store -> getPointerInfo ( ) . getWithOffset ( Offset ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; Stores . push_back


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> } ; MachineInstr * LHSDef = getDefIgnoringCopies ( LHS . getReg ( ) , MRI ) ; MachineInstr * RHSDef = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; CmpInst :: Predicate P = ( CmpInst :: Predicate ) Predicate . getPredicate ( ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( P ) ; if ( IsCMN ( LHSDef , CC ) ) return emitCMN ( LHSDef -> getOperand ( <NUM_LIT> ) , RHS , MIRBuilder ) ; if ( IsCMN ( RHSDef , CC ) ) return emitCMN ( LHS , RHSDef -> getOperand ( <NUM_LIT> ) , MIRBuilder ) ; if ( ! isUnsignedICMPPred ( P ) && LHSDef && LHSDef -> getOpcode ( ) == TargetOpcode :: G_AND ) { auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ; if ( ! ValAndVReg || ValAndVReg -> Value != <NUM_LIT> )


<s> ++ It ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( ! isWhileLoopStart ( Terminator ) ) continue ; MachineBasicBlock * WLSTarget = getWhileLoopStartTargetBB ( Terminator ) ; if ( WLSTarget == Predecessor ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> <STR_LIT> ) ; return revertWhileToDo ( WlsInstr , ML ) ; } } } moveBasicBlock ( Predecessor ,


<s> auto IsFalseIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; assert ( ( IsTrueIfZero ( CC , Imm ) || IsFalseIfZero ( CC , Imm ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; unsigned IntOp = cast < ConstantSDNode > ( Int -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; assert ( ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDNode * Br = * N -> use_begin ( ) ; SDValue OtherTarget = Br -> getOperand ( <NUM_LIT> ) ; auto UpdateUncondBr = [ ] ( SDNode * Br , SDValue Dest , SelectionDAG & DAG ) { SDValue NewBrOps [ ] = { Br -> getOperand ( <NUM_LIT> ) , Dest } ; SDValue NewBr = DAG . getNode ( <STR_LIT> , SDLoc ( Br ) , <STR_LIT> , NewBrOps ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Br , <NUM_LIT> ) , NewBr ) ; } ; if ( IntOp == <STR_LIT> ) { SDValue Res ; if ( IsTrueIfZero ( CC , Imm ) ) { SDValue Ops [ ] = { Chain , Elements , Dest } ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { UpdateUncondBr ( Br , Dest , DAG ) ; SDValue Ops [ ] = { Chain , Elements ,


<s> if ( FuncInfo -> getLOHRelated ( ) . count ( & MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Legal ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isTerminator ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; if ( MOP . isReg ( ) && ! MOP . isImplicit ( ) && ( MOP . getReg ( ) == <STR_LIT> || MOP . getReg ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return outliner :: InstrType :: Legal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return


<s> int bits ; val = aarch64_replicate_bitmask_imm ( val_in , mode ) ; tmp = val + ( val & - val ) ; if ( tmp == ( tmp & - tmp ) ) return ( val + <NUM_LIT> ) > <NUM_LIT> ; if ( mode == SImode ) val = ( val << <NUM_LIT> ) | ( val


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> void <ISA_LIT>ATTInstPrinter :: printRoundingControl ( const MCInst * MI , unsigned Op , raw_ostream & O ) { int64_t Imm = MI -> getOperand ( Op ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> void <ISA_LIT>ALFWriter :: extraFrames ( const MachineConstantPool * MCP ) { auto csts = MCP -> getConstants ( ) ; for ( MachineConstantPoolEntry mcpe : csts ) { const Constant * cv = mcpe


<s> if ( parseSymbolicImmVal ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Equal : { SMLoc Loc = getLoc ( ) ; if ( Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; if ( Operands . size ( ) < <NUM_LIT> || ! static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isScalarReg ( ) ) return Error ( Loc , <STR_LIT> ) ; bool IsXReg = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operands [ <NUM_LIT> ] -> getReg ( ) ) ; MCContext & Ctx = getContext ( ) ; E = SMLoc :: getFromPointer ( Loc . getPointer ( ) - <NUM_LIT> ) ; if ( isa < MCConstantExpr > ( SubExprVal ) ) { uint64_t Imm = ( cast < MCConstantExpr > ( SubExprVal ) ) -> getValue ( ) ; uint32_t ShiftAmt = <NUM_LIT> , MaxShiftAmt = IsXReg ? <NUM_LIT> : <NUM_LIT> ; while ( Imm > <NUM_LIT> && countTrailingZeros ( Imm ) >= <NUM_LIT> ) { ShiftAmt += <NUM_LIT> ; Imm >>= <NUM_LIT> ; } if ( ShiftAmt <= MaxShiftAmt && Imm <= <NUM_LIT> ) { Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , Loc , Ctx ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Imm , Ctx ) , S , E , Ctx ) ) ; if ( ShiftAmt ) Operands . push_back ( <ISA_LIT>Operand :: CreateShiftExtend ( <STR_LIT> , ShiftAmt , true ,


<s> if ( op_mode == VOIDmode ) op_mode = GET_MODE ( op1 ) ; switch ( code ) { case NE : case UNLT : case UNLE : case UNGT : case UNGE : code = reverse_condition_maybe_unordered ( code ) ; reverse_p = true ; break ; case EQ : case LT : case LE : case GT : case GE : reverse_p = false ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case EQ : switch ( op_mode ) { case SFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tstsfeq_gpr ( compare_result , op0 , op1 ) : gen_cmpsfeq_gpr ( compare_result , op0 , op1 ) ; break ; case DFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tstdfeq_gpr ( compare_result , op0 , op1 ) : gen_cmpdfeq_gpr ( compare_result , op0 , op1 ) ; break ; case TFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tsttfeq_gpr ( compare_result , op0 , op1 ) : gen_cmptfeq_gpr ( compare_result , op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } break ; case GT : case GE : switch ( op_mode ) { case SFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tstsfgt_gpr ( compare_result , op0 , op1 ) : gen_cmpsfgt_gpr ( compare_result , op0 , op1 ) ; break ; case DFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tstdfgt_gpr ( compare_result , op0 , op1 ) : gen_cmpdfgt_gpr ( compare_result , op0 , op1 ) ; break ; case TFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tsttfgt_gpr ( compare_result , op0 , op1 ) : gen_cmptfgt_gpr ( compare_result , op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } break ; case LT : case LE : switch ( op_mode ) { case SFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tstsflt_gpr ( compare_result , op0 , op1 ) : gen_cmpsflt_gpr ( compare_result , op0 , op1 ) ; break ; case DFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tstdflt_gpr ( compare_result , op0 , op1 ) : gen_cmpdflt_gpr ( compare_result , op0 , op1 ) ; break ; case TFmode : cmp = ( flag_finite_math_only && ! flag_trapping_math ) ? gen_tsttflt_gpr ( compare_result , op0 , op1 ) : gen_cmptflt_gpr ( compare_result , op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } if ( code == LE || code == GE


<s> if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , E , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind (


<s> eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ; unsigned OpReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( OpReg ) ) break ; MachineInstr * Def = MRI -> getVRegDef ( OpReg ) ; if ( ! Def ) break ; if ( Def -> isImplicitDef ( ) ) ++ NumImplicit ; else NonImplicitReg = MI -> getOperand ( I ) . getReg ( ) ; } if ( NumImplicit == NumTotal - <NUM_LIT> ) return optimizeAllLanesPattern ( MI , NonImplicitReg ) ; else return optimizeAllLanesPattern ( MI , MI -> getOperand (


<s> else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetWindows ( ) && ! Subtarget -> isTargetCygMing ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; typedef <ISA_LIT>COFFMachineModuleInfo :: externals_iterator externals_iterator ; for ( externals_iterator I = COFFMMI . externals_begin ( ) , E = COFFMMI . externals_end ( ) ; I != E ; ++ I ) { OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size (


<s> if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( ( to == DDmode && from == SDmode ) || ( to == SDmode && from == DDmode ) ) return true ; if ( from_size < <NUM_LIT> || to_size < <NUM_LIT> ) return false ; if ( from_size == <NUM_LIT> && ( <NUM_LIT> * to_nregs ) != to_size ) return false ; if ( to_size == <NUM_LIT> && ( <NUM_LIT> * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + <NUM_LIT> ) / <NUM_LIT> ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == <NUM_LIT> || from_size == <NUM_LIT>


<s> if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal ==


<s> if ( ! isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , And_mask ) ) return false ; Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; uint64_t Srl_imm = <NUM_LIT> ; if ( ! isIntImmediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) return false ; unsigned BitWide = <NUM_LIT> - countLeadingOnes ( ~ ( And_mask >> Srl_imm ) ) ; if ( BitWide && isMask_64 ( And_mask >> Srl_imm ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; LSB = Srl_imm ; MSB = BitWide + Srl_imm - <NUM_LIT> ; return true ; } return


<s> switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : { if ( ! isSplatVector ( V . getNode ( ) ) ) return SDValue ( ) ; Ld = V . getOperand ( <NUM_LIT> ) ; if ( ! Ld -> hasNUsesOfValue ( VT . getVectorNumElements ( ) , <NUM_LIT> ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Ld = Sc . getOperand ( <NUM_LIT> ) ; if ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) return SDValue ( ) ; break ; } } if ( ! <STR_LIT> ( Ld . getNode ( ) ) ) return SDValue ( ) ; bool Is256 = VT . getSizeInBits ( )


<s> Type * Ty = I -> getType ( ) ; bool isFloat = ( Ty -> isDoubleTy ( ) || Ty -> isFloatTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned Opc ; bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT>


<s> if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst


<s> void addAFGR64AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table


<s> Optional < int > getTaggedBasePointerIndex ( ) const { return


<s> <ISA_LIT>PreLegalizerCombiner :: <ISA_LIT>PreLegalizerCombiner ( ) : MachineFunctionPass


<s> StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * MemBarrierID ; if ( getParser ( ) . parseExpression ( MemBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( MemBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> <ISA_LIT>BranchExpansion ( ) : MachineFunctionPass ( ID ) , ABI ( <ISA_LIT>ABIInfo :: Unknown ( ) ) { initialize<ISA_LIT>BranchExpansionPass ( * PassRegistry :: getPassRegistry (


<s> MachineFunction * MF = TrueMBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MIItBegin -> getDebugLoc ( ) ; <STR_LIT> CC = <STR_LIT> ( MIItBegin -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt !=


<s> halfthree = rs6000_load_constant_and_splat ( mode , dconst3_2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , src ) , UNSPEC_RSQRT ) ) ) ; rs6000_emit_msub ( y , src , halfthree , src ) ; for ( i = <NUM_LIT> ; i < passes ; i ++ ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx u = gen_reg_rtx ( mode ) ; rtx v = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , x0 , x0 ) ) ; rs6000_emit_nmsub ( v , y , u , halfthree ) ; emit_insn ( gen_mul ( x1 ,


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) return getAddrNonPIC ( N


<s> static bool isCandidateStore ( const MachineInstr * Instr ) { switch ( Instr -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return CreateReg ( Index , RegKind_HWRegs , RegInfo , S , E


<s> static unw_word unw_decode_uleb128 ( unsigned char * * dpp ) { unsigned shift = <NUM_LIT> ; unw_word byte , result = <NUM_LIT> ; unsigned char * bp = * dpp ; while ( <NUM_LIT>


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _mm_mfence ( void ) { __builtin_ia32_mfence (


<s> return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK || Memory .


<s> return pParent . getTarget ( ) . getPLT ( ) .


<s> void addCallTargetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) )


<s> MachineBasicBlock & MBB = * MIB -> getParent ( ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; Register Reg = MIB . getReg ( <NUM_LIT> ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MIB -> setDebugLoc ( DL ) ; MIB -> setDesc ( TII . get ( <STR_LIT> )


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op ,


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI


<s> else if ( ISA_HAS_LOAD_DELAY ) return <NUM_LIT> * <NUM_LIT> ; else return <NUM_LIT> * <NUM_LIT>


<s> SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; if ( ArgFlags . isSplit ( ) || ! PendingMembers . empty ( ) ) { PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; } if ( PendingMembers . empty ( ) ) { if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } return false ; } assert ( ArgFlags . isSplitEnd ( ) ) ; unsigned FirstFree = State . getFirstUnallocated ( RegList ) ; bool UseRegs = PendingMembers . size ( ) <= std :: min ( <NUM_LIT> , NumRegs - FirstFree ) ; for ( auto & It : PendingMembers ) { if ( UseRegs ) It . convertToReg ( State . AllocateReg ( RegList [ FirstFree ++ ] ) ) ; else It . convertToMem ( State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ) ; State . addLoc


<s> void addMemoryRegisterOffset64Operands ( MCInst & Inst , unsigned N ) { addMemoryRegisterOffsetOperands ( Inst , N ,


<s> return ( int32x2_t ) __builtin_neon_vqshlsv2si (


<s> static bool DisassembleLdFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short

NumOps , unsigned & NumOpsAdded , BO B ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) || Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue


<s> if ( tls_index != <NUM_LIT> ) { * key = tls_index ; status = __mingwthr_key_dtor ( * key , dtor ) ; } else status = ( int ) GetLastError ( ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) Inst . addOperand (

MCOperand :: createImm ( ConstExpr -> getValue ( ) & <NUM_LIT> ) ) ;


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) .

addReg ( SrcReg ) . addFrameIndex ( FI ) . addReg ( <STR_LIT> ) ;


<s> SmallVector < Value * , <NUM_LIT> > Args { Merge , GP , Scalar } ; <STR_LIT> IntID = <STR_LIT> ; Function * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , { VecTy } ) ; return CallInst :: Create ( Intr -> getFunctionType


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> << Shift , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) ,

<STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveReg ( SMLoc L ) { unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma

( ) || parseImmExpr ( Offset ) ) return true ;


<s> for ( unsigned I = <NUM_LIT> ; I < Num ; I ++ ) if ( isZeroVector ( Ops [ I


<s> Register NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg ( ) , VA ) ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA . getLocReg ( ) , NextVA ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT> ] , NewRegs [ <NUM_LIT> ] ) ; MIRBuilder . buildMerge ( Arg . Regs [ <NUM_LIT> ] ,


<s> SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned ReturnReg = ( PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; SDValue BlockPtr = DAG . getMCSymbol ( DestMBB -> getSymbol


<s> static bool isVEXTRACTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VT = N -> getSimpleValueType (


<s> case <STR_LIT> : assert ( ( Subtarget . systemSupportsUnalignedAccess ( ) || cast < MemSDNode > ( Node ) -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> <= cast < MemSDNode > ( Node ) -> getAlignment ( ) ) && <STR_LIT> ) ; break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == nullptr || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) <<


<s> return CreateReg ( Index , Str , RegKind_FCC , RegInfo , S , E


<s> unsigned OffsetOpc = OffsetInst -> getOpcode ( ) ; if ( OffsetOpc != TargetOpcode :: G_SHL && OffsetOpc != TargetOpcode :: G_MUL ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * OffsetInst , MRI ) ) return None ; Register OffsetReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { Triple TheTriple (


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( SmallVectorImpl < std :: pair < unsigned , unsigned >> :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++ I ) Op -> Registers . push_back ( I -> second ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return Op


<s> ShuffleMask . push_back ( ( ( Imm >> Bit ) & <NUM_LIT> ) ? NumElts + i :


<s> return ( __m256d ) __builtin_ia32_cvtdq2pd256_mask ( ( __v4si ) __A ,


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling ::


<s> APInt Src1DemE = getDemandedSrcElements ( Op , DemandedElts , OpNo + <NUM_LIT> ) ; KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( OpNo ) , Src0DemE , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( OpNo + <NUM_LIT> ) , Src1DemE , Depth + <NUM_LIT> ) ; Known . Zero = LHSKnown .


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT


<s> for ( MachineBasicBlock & MBB : * MF ) { if ( ! BBHasFallthrough ( & MBB ) ) WaterList . push_back ( & MBB ) ; for ( MachineInstr & I : MBB ) { if ( I . isDebugInstr ( ) ) continue ; unsigned Opc = I . getOpcode ( ) ; if ( I . isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; case <STR_LIT> : case <STR_LIT> : T2JumpTables . push_back ( & I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits =


<s> if ( SDValue ShufConcat = combineShuffleOfConcatUndef ( N , DAG , Subtarget ) ) return ShufConcat ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Shuffle = combineTargetShuffle ( Op , DAG , DCI , Subtarget ) ) return Shuffle ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; APInt KnownUndef , KnownZero ; APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( Op , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; } if ( N -> getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . isUndef ( ) && isNullConstant ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue In = N -> getOperand ( <NUM_LIT> ) . getOperand (


<s> if ( ( EltIdx < <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx < <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx < <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return SDValue ( ) ; } MVT BlendVT = VT ; if ( EltVT == <STR_LIT> || ( EltVT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) { BlendVT = <STR_LIT> ( <STR_LIT> ( EltVT . getSizeInBits ( ) ) , NumElems ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VT


<s> const <ISA_LIT>Subtarget & getSubtarget ( )


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u64 ( unsigned long long __X ) { return __builtin_ia32_tzcnt_u64 ( __X


<s> MachineBasicBlock :: iterator FrameSetup = Context . FrameSetup ; MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; FrameSetup -> getOperand ( <NUM_LIT> ) . setImm ( Context . ExpectedDist ) ; DebugLoc DL = FrameSetup -> getDebugLoc ( ) ; for ( int Idx = ( Context . ExpectedDist / <NUM_LIT> ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator MOV = * Context . MovVector [ Idx ] ; MachineOperand PushOp = MOV -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; if ( MOV -> getOpcode ( ) == <STR_LIT> ) { unsigned PushOpcode = <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addOperand ( PushOp ) ; } else { unsigned int Reg = PushOp . getReg ( ) ; bool SlowPUSHrmm = STI -> isAtom ( ) || STI -> isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { Push = BuildMI ( MBB , Context . Call , DL , TII


<s> MachineInstr * ADDMI = getDefMIPostRA ( ToBeDeletedReg , MI , OtherIntermediateUse ) ; if ( OtherIntermediateUse || ! ADDMI ) return false ; if ( ! isADDInstrEligibleForFolding ( * ADDMI ) ) return false ; unsigned ScaleRegIdx = <NUM_LIT> ; int64_t OffsetAddi = <NUM_LIT> ; MachineInstr * ADDIMI = nullptr ; if ( isValidToBeChangedReg ( ADDMI , <NUM_LIT> , ADDIMI , OffsetAddi , OffsetImm ) ) ScaleRegIdx = <NUM_LIT> ; else if ( isValidToBeChangedReg ( ADDMI , <NUM_LIT> , ADDIMI , OffsetAddi , OffsetImm ) ) ScaleRegIdx = <NUM_LIT> ; else return false ; assert ( ADDIMI && <STR_LIT> ) ; unsigned ToBeChangedReg = ADDIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScaleReg = ADDMI -> getOperand ( ScaleRegIdx ) . getReg ( ) ; auto NewDefFor = [ & ] ( unsigned Reg , MachineBasicBlock ::

iterator Start , MachineBasicBlock :: iterator End ) {


<s> if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , <NUM_LIT> , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; tree old_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( old_target == NULL_TREE ) old_target = target_option_default_node ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( old_target ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == <NUM_LIT> ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( new_target ) { if ( DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == NULL_TREE && DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == NULL_TREE ) { target_attribute_cache [ <NUM_LIT> ] = copy_list ( args ) ; target_attribute_cache [ <NUM_LIT> ] = new_target ; target_attribute_cache [ <NUM_LIT> ] = old_optimize != new_optimize ? new_optimize : NULL_TREE ; } DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) =


<s> static bool ShouldXformToMOVHLPS ( ArrayRef < int > Mask , EVT VT ) { if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( VT . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) ) return false ; return true


<s> if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; return Value >= MinValue && Value <=


<s> static MCStreamer * createMCStreamer ( const Triple & TT , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) ,


<s> gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) ; base = ( REGNO ( operands [ <NUM_LIT> ] ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < XVECLEN ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; i ++ ) { p += sprintf ( & pattern [ p ] , <STR_LIT> , base + i ) ; } strcpy ( & pattern [ p ] , <STR_LIT> ) ; output_asm_insn ( pattern


<s> return gen_rtx_REG ( ( ( GET_MODE_CLASS ( mode ) != MODE_INT || GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) ? mode : SImode )


<s> bool <ISA_LIT>LowOverheadLoops :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasLOB ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > (


<s> NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> )


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getImm


<s> if ( Flags . isSExt ( ) ) return CCValAssign :: LocInfo :: SExt ; if ( Flags . isZExt ( ) )


<s> case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsTestAndBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsNegativeBranch = true ; IsTestAndBranch = true ; break ; } if ( IsTestAndBranch && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; assert ( MI -> getParent ( ) && <STR_LIT> ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; if ( ! ( DefMI -> getOpcode ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ! ( DefMI -> getOpcode ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( DefMI -> findRegisterDefOperandIdx ( <STR_LIT> , true ) != - <NUM_LIT> ) return false ; <STR_LIT> CC = ( <STR_LIT> ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool CheckOnlyCCWrites =


<s> static DecodeStatus decodePC32DBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address


<s> if ( regnum -> count == <NUM_LIT> ) return arg ; if ( GET_CODE ( arg ) != CONST_INT || INTVAL ( arg ) < <NUM_LIT> || INTVAL ( arg )


<s> unsigned Opc ; if ( <ISA_LIT>SubTarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; if ( IsSigned ) Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { DestReg = createResultReg ( & <STR_LIT> ) ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc = <STR_LIT> ; else Opc = <ISA_LIT>SubTarget -> hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; unsigned IntReg = <ISA_LIT>SubTarget -> hasSPE ( ) ? DestReg : <ISA_LIT>MoveToIntReg ( I , DstVT , DestReg , IsSigned ) ; if ( IntReg == <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_vpopcountd_v4si (


<s> mark_user_reg ( fpscr_rtx ) ; } if ( ! reload_completed || mdep_reorg_phase !=


<s> static void mips_sim_issue_insn ( struct mips_sim * state , rtx insn ) { state_transition ( state -> dfa_state , insn


<s> remove_insn ( trailing_nott ( ) ) ; return true


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( CSI . size ( ) > <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MIB . addReg ( Reg , getDefRegState ( true ) ) ; } } else { unsigned Reg = CSI [ <NUM_LIT> ] . getReg ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB ,

MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel


<s> assert ( ClassID == GPRRC || ClassID == VSXRC ) ; return ClassID == GPRRC ? <NUM_LIT> : <NUM_LIT> ; } assert ( ClassID == GPRRC || ClassID == FPRRC ||


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void DecodeSubVectorBroadcast ( unsigned DstNumElts , unsigned SrcNumElts , SmallVectorImpl < int > & ShuffleMask ) { unsigned Scale = DstNumElts / SrcNumElts ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) for ( unsigned j = <NUM_LIT> ;

j != SrcNumElts ; ++ j ) ShuffleMask . push_back ( j ) ;


<s> __o = __builtin_aarch64_set_qregoiv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2v4si ( ( __builtin_aarch64_simd_si * ) __a ,


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; unsigned NumLanes = Op . getValueType ( ) .


<s> int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isMachoABI ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc ) ; int NewFPLoc = SPDiff + <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isMachoABI ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc ) ; MVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , PseudoSourceValue :: getFixedStack ( NewRetAddr ) , <NUM_LIT> ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , PseudoSourceValue :: getFixedStack ( NewFPIdx )


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind


<s> cvtStExtTWriteBackImm ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addMemNoOffsetOperands ( Inst , <NUM_LIT> ) ;


<s> static SDValue PerformSubCSINCCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || ! isNullConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue CSINC = N -> getOperand ( <NUM_LIT> ) ; if ( CSINC . getOpcode ( ) != <STR_LIT> || ! CSINC . hasOneUse ( ) ) return SDValue ( ) ; ConstantSDNode * X = dyn_cast < ConstantSDNode > ( CSINC .


<s> bool has<ISA_LIT>32r2 ( ) const { return STI . getFeatureBits ( )


<s> auto * CCValidOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; auto * CCMaskOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! CCValidOp || ! CCMaskOp ) return SDValue ( ) ; int CCValid = CCValidOp -> getZExtValue ( ) ; int CCMask = CCMaskOp -> getZExtValue ( ) ; SDLoc DL ( Node ) ; SDValue Glue = Node -> getOperand ( <NUM_LIT> ) ; IPMConversion IPM = getIPMConversion ( CCValid , CCMask ) ; SDValue Result = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; if ( IPM . XORValue ) Result = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Result , CurDAG -> getConstant ( IPM . XORValue , DL , <STR_LIT> ) ) ; if ( IPM . AddValue ) Result = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Result , CurDAG -> getConstant ( IPM . AddValue , DL , <STR_LIT> ) ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && IPM . Bit == <NUM_LIT> ) { unsigned ShiftOp = TrueOp -> getSExtValue ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Result = CurDAG -> getNode ( ShiftOp , DL , <STR_LIT> , Result , CurDAG -> getConstant ( IPM . Bit , DL , <STR_LIT> ) ) ; } else { if ( VT != <STR_LIT> ) Result = CurDAG -> getNode ( <STR_LIT> , DL , VT , Result ) ; if ( TrueOp -> getSExtValue ( ) == <NUM_LIT> ) { Result = CurDAG -> getNode ( <STR_LIT> , DL , VT , Result , CurDAG -> getConstant ( IPM . Bit , DL , <STR_LIT> ) ) ; Result = CurDAG -> getNode ( <STR_LIT> , DL , VT , Result , CurDAG -> getConstant ( <NUM_LIT> , DL , VT ) ) ; } else


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0


<s> case OP_VMRGHW : ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VMRGLW : ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VSPLTISW0 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [


<s> if ( isDarwin ( ) ) { unsigned RegNo ; int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ) ; return false ; } } LLVM_FALLTHROUGH ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : case AsmToken :: Dollar : case AsmToken :: Exclaim : case AsmToken :: Tilde : if ( ! ParseExpression ( EVal ) ) break ; default : return Error ( S , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( TLSSym , S , E , is<ISA_LIT>64 ( ) ) ) ; } if ( ! TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex (


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return VTBits ; case <STR_LIT> : { unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; if ( Tmp0 == <NUM_LIT> ) return <NUM_LIT> ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; return std :: min ( Tmp0 , Tmp1 ) ; } case <STR_LIT> : { unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp0 == <NUM_LIT> ) return <NUM_LIT> ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: min ( Tmp0 , Tmp1 ) ; } } if ( isTargetShuffle ( Opcode ) ) { SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( getTargetShuffleMask ( Op . getNode ( ) , VT . getSimpleVT ( ) , true , Ops , Mask ) ) { unsigned NumOps = Ops . size ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Mask . size ( ) == NumElts ) { SmallVector < APInt , <NUM_LIT> > DemandedOps ( NumOps , APInt ( NumElts , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( ! DemandedElts [ i ] ) continue ; int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { return <NUM_LIT> ; } else if ( M == SM_SentinelZero ) { continue ; } assert ( <NUM_LIT> <= M && ( unsigned ) M < ( NumOps * NumElts ) && <STR_LIT> ) ; unsigned OpIdx = ( unsigned ) M / NumElts ; unsigned EltIdx = ( unsigned ) M % NumElts ; if ( Ops [ OpIdx ] . getValueType ( ) != VT ) { return <NUM_LIT> ; } DemandedOps [ OpIdx ] . setBit ( EltIdx ) ; } unsigned Tmp0


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO1 = MI . getOperand ( OpIdx ++ ) ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; if ( MO2 . isReg ( ) ) { Binary |= getMachineOpValue ( MI , MO1 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO2 ) ; ++ OpIdx ; } else { Binary |= getMachineOpValue ( MI , MO1 ) ; } if ( MI . getOperand ( OpIdx ) . isImm ( ) && ! TID . OpInfo [ OpIdx ] . isPredicate ( ) && ! TID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) Binary |= ( getMachineOpValue ( MI , OpIdx ) / <NUM_LIT> ) << <STR_LIT> ; emitWordLE ( Binary


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isCPI ( ) ) return true ; if ( MO . isGlobal ( ) ) return isGVStub ( MO . getGlobal ( ) , TM ) ; if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex (


<s> if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && ( CONST_INT_P ( XEXP ( term , <NUM_LIT> ) ) || GET_CODE ( XEXP ( term , <NUM_LIT> ) ) == CONST_DOUBLE ) ) term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT> ) ; } return ix86_delegitimize_address ( x


<s> bool isABI_N64 ( ) const { return <ISA_LIT>ABI


<s> addSavedGPR ( MBB , MIB , SpillGPRs . LowGPR , false ) ; addSavedGPR ( MBB , MIB , SpillGPRs . HighGPR , false ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( SpillGPRs . GPROffset ) ; auto & GRRegClass = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( GRRegClass . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] .


<s> X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( SDValue Res = combineLogicBlendIntoConditionalNegate ( VT , Mask , X , Y , DL , DAG , Subtarget ) ) return Res ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = VT . is256BitVector (


<s> ++ NumLFENCEsInserted ; return ; } unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg )


<s> return isLegalMaskedGatherScatter ( DataType


<s> rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; rtx addr , addr_reg , tramp , eight = GEN_INT ( <NUM_LIT> ) ; if ( ! TARGET_GNU_AS ) { static bool declared_ia64_trampoline = false ; if ( ! declared_ia64_trampoline ) { declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , <STR_LIT> ) ; } } addr = convert_memory_address ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ; addr_reg = copy_to_reg (


<s> bool <ISA_LIT>TargetLowering :: lowerInterleavedStore ( StoreInst * SI , ShuffleVectorInst * SVI , unsigned Factor ) const { assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; VectorType * VecTy = SVI -> getType ( ) ; assert ( VecTy -> getVectorNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubElts = VecTy -> getVectorNumElements ( ) / Factor ; Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , NumSubElts ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; if ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL


<s> bool <ISA_LIT>InstrInfo :: isAsCheapAsAMove ( const


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget ->

hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) {


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( Register :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; if ( DstSize > SrcSize && SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> ) { const TargetRegisterClass * SrcRC = getRegClass ( MRI . getType ( SrcReg ) , SrcRegBank ) ; const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { Register ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! Register :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( Register :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( MRI . getType ( DstReg ) , DstRegBank ) ; if ( SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> && SrcSize > DstSize && Register :: isPhysicalRegister ( SrcReg ) ) { const TargetRegisterClass * SrcRC = getRegClassFromGRPhysReg ( SrcReg ) ; if ( DstRC != SrcRC ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( getSubRegIndex ( DstRC ) ) ; I . getOperand ( <NUM_LIT> ) . substPhysReg ( SrcReg , TRI ) ; } } const TargetRegisterClass * OldRC = MRI . getRegClassOrNull ( DstReg ) ; if ( ! OldRC || ! DstRC -> hasSubClassEq ( OldRC ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } } I . setDesc ( TII . get ( <STR_LIT> ) ) ; return


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! RPI . isPaired ( ) || ! NeedsFrameRecord || RPI . Reg2 != <STR_LIT> || RPI . Reg1 == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( ! RPI . isPaired ( ) || ! NeedsFrameRecord || RPI . Reg1 != <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; int Scale = RPI . getScale ( ) ; if ( RPI . isScalable ( ) ) ScalableByteOffset -= Scale ; else ByteOffset -= RPI . isPaired ( ) ? <NUM_LIT> * Scale : Scale ; if ( NeedsFrameRecord && AFI -> hasSwiftAsyncContext ( ) && RPI . Reg2 == <STR_LIT> ) ByteOffset -= <NUM_LIT> ; assert ( ! ( RPI . isScalable ( ) && RPI . isPaired ( ) ) && <STR_LIT> ) ; if ( AFI -> hasCalleeSaveStackFreeSpace ( ) && ! FixupDone && ! RPI . isScalable ( ) && RPI . Type != RegPairInfo :: FPR128 && ! RPI . isPaired ( ) ) { FixupDone = true ; ByteOffset -= <NUM_LIT> ; assert ( ByteOffset % <NUM_LIT> == <NUM_LIT> ) ; assert ( MFI . getObjectAlign ( RPI . FrameIdx ) <= Align ( <NUM_LIT> ) ) ; MFI . setObjectAlignment ( RPI . FrameIdx , Align ( <NUM_LIT> ) ) ; } int Offset = RPI . isScalable ( ) ? ScalableByteOffset : ByteOffset ; assert ( Offset % Scale == <NUM_LIT> ) ; if ( NeedsFrameRecord && AFI -> hasSwiftAsyncContext ( ) && RPI .


<s> continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( & * I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto NewTBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( OldBranchCode == BranchCode && TBB == NewTBB ) continue ; if ( TBB == NewTBB && ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) ) { BranchCode = <STR_LIT> ; } else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode

== <STR_LIT> && BranchCode == <STR_LIT> ) ) {


<s> Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false ,

true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> SDLoc DL ( N ) ; RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Index , CurDAG


<s> void <ISA_LIT>ConstantIslands :: fixupBTI ( unsigned JTI , MachineBasicBlock & OldBB , MachineBasicBlock & NewBB ) { assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , NewBB . begin ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; const MachineJumpTableInfo & MJTI = * MF -> getJumpTableInfo ( ) ; const MachineJumpTableEntry & JTE = MJTI . getJumpTables ( ) [ JTI ] ; for ( const MachineBasicBlock * MBB : JTE . MBBs ) { if ( MBB != & OldBB ) continue ; -- BlockJumpTableRefCount [


<s> MCContext & Ctx ; Mangler & Mang ; AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) ,


<s> if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ) return new <ISA_LIT>FastISel ( funcInfo


<s> Address ( ) : BaseType ( RegBase ) , Offset ( <NUM_LIT>

) , Scale ( <NUM_LIT> ) , PlusReg ( <NUM_LIT> ) {


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler


<s> MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) DEBUG ( dbgs


<s> code = LE ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; break ; case UNGE : code = GE ; break ; case UNEQ : code = EQ ; break ; default : break ; } switch ( code ) { case GE : break ; case LE : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case ORDERED : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_ABS ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case EQ : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , gen_rtx_ABS ( compare_mode , op0 ) ) ) ) ; op0 = temp ; break ; case UNGE : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; false_cond = true_cond ; true_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case GT : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; true_cond = false_cond ; false_cond = temp


<s> rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT>


<s> int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm ) ) return false ; bool IsFwdFeederRegKilled = false ; if ( ! isRegElgibleForForwarding ( * RegMO , DefMI , MI , KillDefMI , IsFwdFeederRegKilled ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; bool PostRA = ! MRI . isSSA ( ) ; if ( PostRA && MI . getOperand ( OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . ChangeToRegister ( RegMO -> getReg ( ) , false , false , RegMO -> isKill ( ) ) ; if ( ImmMO -> isImm ( ) ) { replaceInstrOperandWithImm ( MI , III . ZeroIsSpecialOrig , Imm ) ; } else { if ( DefMI . getOpcode ( ) == <STR_LIT> ) ImmMO -> setTargetFlags ( <STR_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT> > MOps ; for ( unsigned i = MI . getNumOperands ( ) - <NUM_LIT> ; i >= III . ZeroIsSpecialOrig ; i -- ) { MOps . push_back ( MI . getOperand ( i ) ) ; MI . RemoveOperand ( i ) ; } MOps . pop_back ( ) ; MI . addOperand ( * ImmMO ) ; for ( auto & MO : MOps ) MI . addOperand ( MO ) ; } MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( IsFwdFeederRegKilled || RegMO -> isKill ( ) ) fixupIsDeadOrKill ( & DefMI , & MI , RegMO -> getReg ( ) ) ; if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill ( & DefMI , & MI , ForwardKilledOperandReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; return


<s> return hash_combine ( DenseMapInfo < const MCSymbol * > :: getHashValue ( V . sym ) , DenseMapInfo < int > :: getHashValue (


<s> unsigned <ISA_LIT>InstrInfo :: getCompareAndBranch ( unsigned Opcode , const MachineInstr * MI ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; DeprecatedMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors =


<s> return __arm_vqdmladhq_s32 ( __inactive ,


<s> unsigned Pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Pred == <NUM_LIT> ) return DecodeSETPANInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return res


<s> while ( MI -> getOperand ( RegOps ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( RegOps ) . getReg ( ) ) ; RegOps ++ ; } O << <STR_LIT> ; return false ; } case 'R' : case 'Q' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = ExtraCode [ <NUM_LIT> ] == 'Q' ? OpNum : OpNum + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } case 'e' : case 'f' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) return true ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; unsigned SubReg = TRI -> getSubReg ( Reg , ExtraCode [ <NUM_LIT> ] == 'e' ? <STR_LIT> : <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( SubReg ) ; return false ; } case 'h' : case 'H' : return true ; } } printOperand ( MI ,


<s> gcc_assert ( nreg <= <NUM_LIT> ) ; if ( named && * cum + nreg <= <NUM_LIT> ) return gen_rtx_REG ( mode , * cum +


<s> return DisassembleLdStFrm ( MI , Opcode , insn , NumOps , NumOpsAdded , true ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectShiftedRegister ( SDValue N , bool AllowROR , SDValue & Reg , SDValue & Shift ) { <STR_LIT> ShType = getShiftTypeForNode ( N ) ; if ( ShType == <STR_LIT> ) return false ; if ( ! AllowROR && ShType == <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; unsigned Val = RHS -> getZExtValue ( ) & ( BitSize - <NUM_LIT> ) ; unsigned ShVal = <STR_LIT> ( ShType , Val ) ; Reg = N . getOperand ( <NUM_LIT> ) ; Shift = CurDAG -> getTargetConstant ( ShVal , SDLoc ( N ) , <STR_LIT> ) ; return isWorthFolding (


<s> static Optional < Instruction * > instCombineMaxMinNM ( InstCombiner & IC , IntrinsicInst & II ) { Value * A = II . getArgOperand ( <NUM_LIT> ) ; Value * B = II . getArgOperand ( <NUM_LIT> ) ; if ( A == B ) return IC . replaceInstUsesWith ( II , A ) ; return


<s> bool <ISA_LIT>BranchCoalescing :: validateCandidates ( CoalescingCandidateInfo & SourceRegion , CoalescingCandidateInfo & TargetRegion ) const { if ( TargetRegion . BranchTargetBlock != SourceRegion . BranchBlock ) llvm_unreachable ( <STR_LIT> ) ; else if ( ! MDT -> dominates ( TargetRegion . BranchBlock , SourceRegion . BranchBlock ) ) llvm_unreachable ( <STR_LIT> ) ; else if ( ! MPDT -> dominates ( SourceRegion . BranchBlock , TargetRegion . BranchBlock ) ) llvm_unreachable ( <STR_LIT> ) ; else if ( ! TargetRegion . FallThroughBlock -> empty ( ) || ! SourceRegion . FallThroughBlock -> empty ( ) ) llvm_unreachable ( <STR_LIT> ) ; return


<s> BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , TmpDestReg ) . addReg ( ZeroReg ) . addReg ( PtrReg ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( Incr2Reg ) . addReg ( TmpDestReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp2Reg ) . addReg ( TmpDestReg ) . addReg ( MaskReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp3Reg ) . addReg ( TmpReg ) . addReg ( MaskReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp4Reg ) . addReg ( Tmp3Reg ) . addReg ( Tmp2Reg ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( Tmp4Reg )


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_storeu_pd ( void *


<s> bool isGR32 ( ) const { return isReg ( GR32Reg


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> if ( Subtarget -> isTargetELF ( ) ) { TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , getPointerTy ( ) , Subtarget -> is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) , getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetWindows (


<s> inline bool isImmSExti64i8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value &&


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { llvm_unreachable ( <STR_LIT>


<s> uint64_t Imm = getConstantImm ( ) - Offset ; Imm &= ( <NUM_LIT> << Bits )


<s> VA . convertToReg ( <STR_LIT> ) ; } else if ( ! Subtarget . hasSSE2 ( ) && <STR_LIT> . contains ( VA . getLocReg ( ) ) && ValVT == <STR_LIT> ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; VA . convertToReg ( <STR_LIT> ) ; } if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetVals . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; continue ; } if ( Subtarget . is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget . hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Passv64i1ArgInRegs ( dl , DAG , ValToCopy , RetVals , VA , RVLocs [ ++ I ] , Subtarget ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RVLocs [ I ] . getLocReg ( ) ) ; } else { RetVals . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; } } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , dl , <STR_LIT> ) ) ; for ( auto & RetVal : RetVals ) { if ( RetVal . first == <STR_LIT> || RetVal . first == <STR_LIT> ) { RetOps . push_back ( RetVal . second ) ; continue ; } Chain = DAG . getCopyToReg ( Chain , dl , RetVal . first , RetVal . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetVal . first , RetVal


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF .

hasMSInlineAsm ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> return ( poly64x1_t ) __builtin_neon_vreinterpretdiv4hi ( (


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget >


<s> tree decl ; decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { TREE_ASM_WRITTEN ( decl ) = <NUM_LIT> ; i386_pe_declare_function_type ( asm_out_file , p -> name


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { Opc = Addr [ <NUM_LIT> ] . isFI ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB ) ; return ; } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT>


<s> MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI -> getParent ( ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> ) return true ; } if ( IP ==


<s> __o = __builtin_aarch64_ld4rv8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregxiv8hi