<s> cum -> libcall = libcall ; cum -> nargs_prototype = <NUM_LIT> ; if ( incoming || cum -> prototype ) cum -> nargs_prototype = n_named_args ; if ( ( ! fntype && rs6000_default_long_calls ) || ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4 )


<s> unsigned MaskBits = APInt ( <NUM_LIT> , NumElts * <NUM_LIT> ) . logBase2 ( ) ; APInt ExpectedElt = APInt ( MaskBits , * FirstRealElt + <NUM_LIT> ) ; const int * FirstWrongElt = std :: find_if ( FirstRealElt + <NUM_LIT> , M . end ( ) , [ & ] ( int Elt ) { return Elt != ExpectedElt ++ && Elt != - <NUM_LIT> ; } ) ; if ( FirstWrongElt != M . end ( ) ) return false ; Imm = ExpectedElt . getZExtValue ( ) ; if ( Imm < NumElts ) ReverseEXT = true ; else Imm -= NumElts ; return


<s> else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: Style :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: Style :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( TM , * this , * RBI


<s> BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl


<s> static bool use_vfp_abi ( enum arm_pcs pcs_variant , bool is_double ) { if ( pcs_variant == ARM_PCS_AAPCS_VFP ) { static bool seen_thumb1_vfp = false ; if ( TARGET_THUMB1 &&


<s> NodeSet ( const ImmutableGraph & G , bool ContainsAll = false ) : G { G , V { static_cast < unsigned > ( G . nodes_size ( ) ) , ContainsAll { } bool insert ( const Node & N ) { size_type Idx = G . getNodeIndex ( N ) ; bool AlreadyExists = V . test ( Idx ) ; V . set ( Idx ) ; return ! AlreadyExists ; } void erase ( const Node & N ) { size_type Idx = G . getNodeIndex ( N ) ; V . reset ( Idx ) ; } bool contains ( const Node & N ) const { size_type Idx = G . getNodeIndex ( N ) ; return V . test ( Idx


<s> } if ( ! IsControlFlow && CurState == EXITS_DIRTY ) continue ; if ( hasYmmOrZmmReg ( MI ) ) { CurState = EXITS_DIRTY ; continue ; } if ( ! IsControlFlow ) continue ; if ( IsCall && ! callHasRegMask ( MI ) ) continue ; if ( CurState == EXITS_DIRTY ) { insertVZeroUpper ( MI , MBB ) ; CurState = EXITS_CLEAN ; } else if ( CurState == PASS_THROUGH ) { BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = MI ; CurState =


<s> SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue G = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget <

<ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) {


<s> unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , SPOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( * MBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ; MI -> eraseFromParent


<s> static __inline int __attribute__ ( ( __always_inline__ ) )


<s> } else if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } Inst . setOpcode ( Opcode ) ; if ( Opcode == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createImm (


<s> RegisterTargetMachine < MandarinTargetMachine > X


<s> static std :: unique_ptr < <ISA_LIT>Operand > createFCCReg ( unsigned Index , StringRef Str , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser


<s> return ( __m128h ) __builtin_ia32_vfmulcph128 ( ( __v8hf ) __A , ( __v8hf )


<s> void <ISA_LIT>InterleavedAccessGroup :: interleave8bitStride3 ( ArrayRef < Instruction * > InVec , SmallVectorImpl < Value * > & TransposedMatrix , unsigned VecElems ) { TransposedMatrix . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > GroupSize ; SmallVector < int , <NUM_LIT> > VPShuf ; SmallVector < int , <NUM_LIT> > VPAlign [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > VPAlign2 ; SmallVector < int , <NUM_LIT> > VPAlign3 ; Value * Vec [ <NUM_LIT> ] , * TempVector [ <NUM_LIT> ] ; MVT VT = <STR_LIT> ( <STR_LIT> , VecElems ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ i ] , VPAlign [ i ] ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ]


<s> std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace ) ; if ( ST -> hasVSX ( ) ) { if ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) return Cost ; } bool UnalignedAltivec = Src -> isVectorTy ( ) && Src -> getPrimitiveSizeInBits ( ) >= LT . second . getSizeInBits ( ) && LT . second . getSizeInBits ( ) == <NUM_LIT> && Opcode == Instruction :: Load ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( SrcBytes && Alignment && Alignment < SrcBytes && ! UnalignedAltivec ) { Cost += LT . first * ( SrcBytes / Alignment - <NUM_LIT> ) ; if ( Src -> isVectorTy ( ) && Opcode == Instruction :: Store ) for ( int i = <NUM_LIT> , e = Src -> getVectorNumElements ( ) ; i < e ; ++ i ) Cost += getVectorInstrCost ( Instruction :: ExtractElement , Src , i ) ; } return Cost


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( ) . hasAttribute ( Attributes :: StackAlignment ) ) ; if ( ForceStackAlign ) return canRealignStack ( MF ) ; return requiresRealignment && canRealignStack


<s> assert ( ( Pos < <NUM_LIT> || ( Pos < <NUM_LIT> && TID . Opcode != <STR_LIT> && TID . Opcode != <STR_LIT> ) ) && <STR_LIT> ) ; Binary |= Pos << <NUM_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) { unsigned ShiftOp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Opc = <STR_LIT> ( ShiftOp ) ; if ( Opc == <STR_LIT> ) Binary


<s> void Thumb1InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC == & <STR_LIT> || ( Register :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == & <STR_LIT> || ( Register :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { DebugLoc DL


<s> emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes ,


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregoiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t )


<s> const char * RegName = <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; if ( ! Subtarget -> isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ! GV -> isStrongDefinitionForLinker ( ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage (

) || GV -> hasAvailableExternallyLinkage ( ) ) {


<s> if ( Subtarget -> hasFp256 ( ) ) { if ( ResVT . is128BitVector ( ) && ( InVT . is256BitVector ( ) || InVT . is512BitVector ( ) ) && isa < ConstantSDNode > ( Idx ) ) { return Extract128BitVector ( In , IdxVal , DAG , dl ) ; } if ( ResVT . is256BitVector ( ) && InVT . is512BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { return Extract256BitVector ( In , IdxVal , DAG , dl ) ; } } return SDValue (


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) )

__blsic_u64 ( unsigned long long __X ) {


<s> NOPInsertionPass ( bool is64Bit_ ) : MachineFunctionPass ( ID ) , is64Bit


<s> LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op ,


<s> const MCExpr * getMemOffset ( ) const { assert ( isMem ( ) && <STR_LIT> ) ; return Mem . Offset


<s> return ( __m128i ) __builtin_ia32_pmovwb128_mask ( ( __v8hi ) __A , ( __v16qi )


<s> if ( ! parseRegister ( Operands ) ) return false ; OperandMatchResultTy GotShift = tryParseOptionalShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; const MCExpr * IdVal ; S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Integer : case AsmToken :: Real : case AsmToken :: Hash : { S = getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; if ( Parser . getLexer ( ) . peekTok ( ) . is ( AsmToken :: Real ) ) Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; else if ( IntVal != <NUM_LIT> || isNegative ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; return false ; } const MCExpr * ImmVal ; if ( parseSymbolicImmVal ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Equal : { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( Mnemonic != <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; if ( Operands . size ( ) < <NUM_LIT> || ! static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isReg ( )


<s> assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy =


<s> Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSCst = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( RHSCst && isLegalArithImmed ( RHSCst -> Value . getSExtValue ( ) ) ) return false ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; auto GetRegForProfit = [ & ] ( Register Reg ) { MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; return isCMN ( Def , Pred , MRI ) ? Def -> getOperand ( <NUM_LIT> ) . getReg ( ) : Reg ; } ; Register TheLHS = GetRegForProfit ( LHS ) ; Register TheRHS = GetRegForProfit


<s> static bool isFullyRelaxed ( const MCRelaxableFragment & RF ) { auto & Inst = RF . getInst ( ) ; auto & STI = * RF . getSubtargetInfo ( ) ; bool Is16BitMode = STI . getFeatureBits ( ) [ <STR_LIT> ] ; return getRelaxedOpcode ( Inst , Is16BitMode ) == Inst


<s> static inline unsigned getUnconditionalBrDisp ( int Opc ) { switch ( Opc ) { case <STR_LIT> : return ( ( <NUM_LIT> << <NUM_LIT> ) -


<s> _cvtmask8_u32 ( __mmask8 __A ) { return ( unsigned int ) __builtin_ia32_kmovb ( ( __mmask8 )


<s> int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , NULL , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , NULL , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD ,

DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) )


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> <ISA_LIT>AddressMode ( ) : BaseType ( RegBase ) , Scale ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , Disp ( <NUM_LIT>


<s> return hash_rtx ( p1 , VOIDmode , NULL ,


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getInstrInfo (


<s> unsigned <ISA_LIT>FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF )


<s> void <ISA_LIT>InstPrinter :: printAdrpLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand


<s> default : break ; case Instruction :: BitCast : return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: Alloca : { const AllocaInst * A = cast < AllocaInst > ( V ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm


<s> else { rtx mem , lab ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr , got ) , UNSPEC_TLSGD ) ; tga = rs6000_tls_get_addr ( ) ; rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg ) ) ; global_tlsarg = arg ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , argreg , Pmode ) ; global_tlsarg = NULL_RTX ; rtvec vec = gen_rtvec ( <NUM_LIT> , copy_rtx ( arg ) ) ; rtx uns = gen_rtx_UNSPEC ( Pmode , vec , UNSPEC_TLS_GET_ADDR ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , uns ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , got ) , UNSPEC_TLSLD ) ; tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg ) ) ; global_tlsarg = arg ; emit_library_call_value ( tga , tmp1 , LCT_CONST , Pmode , argreg , Pmode ) ; global_tlsarg = NULL_RTX ; rtvec vec = gen_rtvec ( <NUM_LIT> , copy_rtx ( arg ) ) ; rtx uns = gen_rtx_UNSPEC ( Pmode , vec , UNSPEC_TLS_GET_ADDR ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , uns ) ; if ( rs6000_tls_size == <NUM_LIT> || rs6000_pcrel_p ( ) ) { if ( TARGET_64BIT ) insn = gen_tls_dtprel_64 ( dest , tmp1 , addr ) ; else insn = gen_tls_dtprel_32 ( dest , tmp1 , addr ) ; } else if ( rs6000_tls_size == <NUM_LIT> ) { tmp2 = gen_reg_rtx ( Pmode ) ; if ( TARGET_64BIT ) insn = gen_tls_dtprel_ha_64 ( tmp2 , tmp1 , addr


<s> ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 ,

CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI ) ) return false ;


<s> if ( ! GNULDBackend :: relax ( pModule , pBuilder ) ) { return false ; } rewrite<ISA_LIT>ExIdxSection ( pModule ) ; return true


<s> if ( isSimpleIndexCalc ( * I , EntryReg , BaseReg ) ) { RemovableAdd = & * I ; break ; } for ( unsigned K = <NUM_LIT> , E = I -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = I -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == BaseReg ) return false ; if ( MO . isUse ( ) && MO . getReg ( ) == BaseReg ) { BaseRegKill = BaseRegKill || MO . isKill ( ) ; CanDeleteLEA = false ; } } } if ( ! RemovableAdd ) return true ; for ( ++ I ; & * I != JumpMI ; ++ I ) { for ( unsigned K = <NUM_LIT> , E = I -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = I -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO


<s> return helper_sign_extend ( ( ( ( pTarget >> <NUM_LIT> ) ) & <NUM_LIT> ) |


<s> static const TargetRegisterClass * getRegClassForTypeOnBank ( LLT Ty , const RegisterBank & RB , const RegisterBankInfo & RBI ) { if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return &


<s> imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Q = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Q ) { if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return StackOffset :: getScalable ( ( int64_t ) AFI ->


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT ==


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineBasicBlock :: iterator MBBI = I ; MachineInstr * FirstMI = I ; ++ MBBI ; unsigned Opc = FirstMI -> getOpcode ( ) ; bool MayLoad = FirstMI -> mayLoad ( ) ; bool IsUnscaled = isUnscaledLdst ( Opc ) ; unsigned Reg = FirstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = FirstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = FirstMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( FirstMI -> modifiesRegister ( BaseReg , TRI ) ) return E ; int OffsetStride = IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ? getMemSize ( FirstMI ) : <NUM_LIT> ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return E ; BitVector ModifiedRegs , UsedRegs ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; bool CanMergeOpc = Opc == MI -> getOpcode ( ) ; SExtIdx = - <NUM_LIT> ; if ( ! CanMergeOpc ) { bool IsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( Opc , & IsValidLdStrOpc ) ; if ( ! IsValidLdStrOpc ) continue ; SExtIdx = NonSExtOpc == ( unsigned ) Opc ? <NUM_LIT> : <NUM_LIT> ; CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode ( MI -> getOpcode ( ) ) ; } if ( CanMergeOpc && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned MIBaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int MIOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool MIIsUnscaled = isUnscaledLdst ( MI -> getOpcode ( ) ) ; if ( ! inBoundsForPair ( MIIsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( MI -> mayLoadOrStore ( ) ) MemInsns . push_back ( MI ) ; continue ; } if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( MI -> mayLoadOrStore ( ) ) MemInsns . push_back


<s> static MCPhysReg getPairedGPR ( MCPhysReg Reg , bool Odd , const MCRegisterInfo * RI ) { for ( MCSuperRegIterator Supers ( Reg , RI ) ; Supers . isValid ( ) ; ++ Supers ) if ( <STR_LIT> . contains ( * Supers )

) return RI -> getSubReg ( * Supers , Odd ? <STR_LIT> : <STR_LIT> ) ;


<s> case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++ I ; MI -> removeFromParent ( ) ; LIS -> repairIntervalsInRange ( & MBB , First , Last , OrigRegs ) ; Changed = true ; } return Changed


<s> else { rtx gsym = rs6000_got_sym ( ) ; got = gen_reg_rtx ( Pmode ) ; if ( flag_pic == <NUM_LIT> ) rs6000_emit_move ( got , gsym , Pmode ) ; else { rtx mem , lab ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , const0_rtx , Pmode ) ; r3 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( TARGET_64BIT ) insn = gen_tls_gd_aix64 ( r3 , got , addr , tga , const0_rtx ) ; else insn = gen_tls_gd_aix32 ( r3 , got , addr , tga , const0_rtx ) ; } else if ( DEFAULT_ABI == ABI_V4 ) insn = gen_tls_gd_sysvsi ( r3 , got , addr , tga , const0_rtx ) ; else gcc_unreachable ( ) ; call_insn = last_call_insn ( ) ; PATTERN ( call_insn ) = insn ; if ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx (


<s> void FPS :: handleOneArgFP ( MachineBasicBlock :: iterator & I ) { MachineInstr * MI = I ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) duplicatePendingSTBeforeKill ( Reg , I ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , getScratchReg ( ) , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( StackTop == <NUM_LIT> ) report_fatal_error (


<s> return GlobalBaseReg = MF . getRegInfo ( ) .


<s> MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FP ) . addReg ( Buf ) . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JmpLoc , RegState :: Define ) . addReg ( Buf ) . addImm ( RegSize ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <ISA_LIT> ) . addReg ( Buf ) . addImm ( <NUM_LIT> * RegSize ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( Buf , RegState :: Kill ) . addImm ( <NUM_LIT> * RegSize ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( JmpLoc , RegState :: Kill ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return


<s> const MCExpr * <ISA_LIT>AsmParser :: ApplyPrefixToExpr ( const MCExpr * E , MCSymbolRefExpr :: VariantKind Variant ) { if ( Variant == MCSymbolRefExpr :: VK_None ) return E ; switch ( E -> getKind ( ) ) { case MCExpr :: Target : llvm_unreachable ( <STR_LIT> ) ; case MCExpr :: Constant : llvm_unreachable ( <STR_LIT> ) ; case MCExpr :: SymbolRef


<s> LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , <STR_LIT> , LN0 -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return


<s> return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp ; for ( j = <NUM_LIT> , i = first_reg ; j < num_regs ; i += <NUM_LIT> ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , <NUM_LIT> * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j + <NUM_LIT>


<s> if ( ! Ty . isVector ( ) ) return false ; Optional < int64_t > ImmVal = getVectorSHLImm ( Ty , Src2Reg , MRI ) ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto Shl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg } ) ; if ( ImmVal ) Shl . addImm


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , & MI , DL , TII -> get ( CAPLOAD ) , IntReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( MTC1 ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( IntReg ) ; MI . eraseFromParent (


<s> } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op .


<s> AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > (


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutsVals , const SDLoc & DL , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , Subtarget . abiUsesSoftFloat ( ) , MF . getFunction ( ) . getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutsVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned V0 = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0


<s> if ( TARGET_SHMEDIA ) { if ( satisfies_constraint_I10 ( XEXP ( x , <NUM_LIT> ) ) || satisfies_constraint_J16 ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; else return <NUM_LIT> + rtx_cost ( XEXP ( x , <NUM_LIT> ) , AND , <NUM_LIT> , ! optimize_size ) ; } if ( ( i == <NUM_LIT> || i == <NUM_LIT> ) && code == AND ) return <NUM_LIT> * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return <NUM_LIT> * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return <NUM_LIT> * cost_scale ; return <NUM_LIT> *


<s> bool isDarwin ( ) const { return IsDarwin


<s> Res = DAG . getVectorShuffle ( <STR_LIT> , DL , Res , Res , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( DstVT . is256BitVector ( ) ) return DAG . getBitcast ( DstVT , Res ) ; EVT PackedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PackedSVT , NumElems ) ; Res = DAG . getBitcast ( PackedVT , Res ) ; return truncateVectorCompareWithPACKSS ( DstVT , Res , DL , DAG , Subtarget ) ; } assert ( SrcVT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; EVT PackedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PackedSVT , NumElems / <NUM_LIT> ) ; Lo = truncateVectorCompareWithPACKSS ( PackedVT , Lo , DL , DAG , Subtarget ) ; Hi = truncateVectorCompareWithPACKSS ( PackedVT , Hi , DL , DAG , Subtarget ) ; PackedVT = EVT :: getVectorVT ( * DAG .


<s> FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeSet A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , nullptr ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { const Value * V = CI -> getCalledValue ( ) ; Type * T = nullptr ; if ( V ) T = V -> getType (


<s> void setCalleeSaveStackHasFreeSpace ( bool


<s> return __builtin_mve_sqshl_si ( value ,


<s> bool hasFuseCryptoEOR ( ) const { return HasFuseCryptoEOR


<s> ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) { return CSR_GHC_SaveList


<s> static bool aarch64_macro_fusion_p ( void


<s> ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , dl , MaskVT ) ; else { EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index


<s> bool <ISA_LIT>BaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int64_t CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; Inst . addOperand ( MCOperand :: createReg ( Index == <NUM_LIT> ? <NUM_LIT> : Regs [ Index ] ) ) ; return MCDisassembler ::


<s> return ( uint8_t ) __builtin_aarch64_uqmovnhi


<s> Type * I64Ty = Builder -> getInt64Ty ( ) ; Value * Idx [ ] = { Builder -> getInt32 ( <NUM_LIT> ) , <NUM_LIT> } ; { Builder -> SetInsertPoint ( BasicBlock :: Create ( * Ctx , <STR_LIT> , InitFn ) ) ; Function :: arg_iterator ArgI = InitFn -> getArgumentList ( ) . begin ( ) ; Value * Regset = ArgI ++ ; Value * StackPtr = ArgI ++ ; Value * StackSize = ArgI ++ ; Value * ArgC = ArgI ++ ; Value * ArgV = ArgI ++ ; Value * RSP = Builder -> CreatePtrToInt ( StackPtr , I64Ty ) ; RSP = Builder -> CreateAdd ( RSP , Builder -> CreateZExtOrBitCast ( StackSize ,


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ,


<s> rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 )


<s> SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( MatchAny ? <STR_LIT> : <STR_LIT> ) ; if ( SrcVT . getVectorNumElements ( ) != NumDstElts ) Shuffle = getOpcode_EXTEND_VECTOR_INREG ( Shuffle ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasFP16 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = MaskEltSize == <NUM_LIT> ? <STR_LIT> : ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> __inline__ static unsigned long long sh_media_LDLO_L ( void * p ,


<s> SDValue Ops [ ] = { GA , Reg } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , VT , MachinePointerInfo :: getGOT ( DAG

. getMachineFunction ( ) ) , None , MachineMemOperand :: MOLoad ) ;


<s> tree s = build_string ( strlen ( reg_names [ CA_REGNO ] ) , reg_names [ CA_REGNO ] ) ; return tree_cons ( NULL_TREE ,


<s> if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; return DAG . getBitcast ( ReqVT , DAG . getConstant


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT FullVT = getFullRegisterType ( VT ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . NOT ( A1 ) ; SDValue TmpAns = b . OR ( b . AND ( Tmp , A2 ) , b . AND ( b . SHL < <NUM_LIT> > ( b . AND ( A1 , b .


-> optimize_call_stack ) set_callers_may_not_allocate_frame ( fn ) ;


<s> CopySrcSubreg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) { SwapVector [ VecIdx ] . MentionsPhysVR = <NUM_LIT> ; return CopySrcReg ; } if ( CopySrcSubreg != <NUM_LIT> ) { SwapVector [ VecIdx ] .


<s> bool <ISA_LIT>TargetLowering :: isDesirableToTransformToIntegerOp ( unsigned Opc ,


<s> bool <ISA_LIT>BaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> if ( E ) EVal = <ISA_LIT>MCExpr :: Create ( Variant , E , false , getParser ( ) . getContext ( ) ) ; return false


<s> static bool invalidateWindowsRegisterPairing ( unsigned Reg1 , unsigned Reg2 , bool NeedsWinCFI ) { if ( ! NeedsWinCFI


<s> unsigned Src1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( ( Dest == <STR_LIT> || Src1 == <STR_LIT> ) && ExtType == <STR_LIT> ) || ( ( Dest == <STR_LIT> || Src1 == <STR_LIT> ) && ExtType == <STR_LIT> ) ) { if ( ShiftVal != <NUM_LIT> ) O << <STR_LIT> << ShiftVal ; return ; } } O << <STR_LIT> << <STR_LIT> ( ExtType ) ; if ( ShiftVal != <NUM_LIT> ) O <<


<s> C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT ANDVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , ANDVT , DAG . getNode ( <STR_LIT> , dl , ANDVT , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , ANDVT , Mask ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT ,

Op . getOperand ( <NUM_LIT> ) , Mask ) ;


<s> EmitSled ( MI , SledKind :: FUNCTION_ENTER


<s> int32_t Val = MO . getImm ( ) ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; else if ( Val < <NUM_LIT> ) { Val *= - <NUM_LIT> ; Val |= <NUM_LIT> ; } return Val


_mm512_undefined_si512 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> unsigned int __b = __B ; return ( ( __m64 ) __a


<s> const MCExpr * <ISA_LIT>ELFMCAsmInfo :: getExprForPersonalitySymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MCContext & Ctx = Streamer . getContext


<s> MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true , false ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOpcode ( ) == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; Offset = TFI -> getNonLocalFrameIndexReference ( MF , FrameIndex ) ; FI . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg ,


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( <NUM_LIT> ) . setSubReg (


<s> return __builtin_aarch64_sqadddi ( __a ,


<s> unsigned Emitter < CodeEmitter > :: getShiftOp ( unsigned Imm ) const { switch ( <STR_LIT> ( Imm ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } return <NUM_LIT>


<s> lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return false ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ; } LLVM_DEBUG ( dbgs ( ) <<


<s> if ( ! nds32_check_constant_argument ( icode , <NUM_LIT> , op1 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; op1 = nds32_legitimize_argument ( icode , <NUM_LIT> , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return


<s> if ( GEPPtr -> getType ( ) -> isVectorTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; Type * OffsType = VectorType :: getInteger ( cast < VectorType > ( Ty ) ) ; if ( OffsType != Offsets -> getType ( ) ) { if ( OffsType -> getScalarSizeInBits ( ) > Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Offsets = Builder . CreateZExt ( Offsets , OffsType , <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr


<s> for ( auto * I : Writes ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; assert ( MAC . MemLocs . size ( ) >= <NUM_LIT> && <STR_LIT> ) ; for ( auto & MemLoc : MAC . MemLocs ) { if ( isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( I , MemLoc ) , ModRefInfo :: ModRef


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } if ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { return


<s> static void AnalyzeRetResult ( CCState & State , const SmallVectorImpl < <STR_LIT>


<s> switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case <STR_LIT> : expandRetRA ( MBB , MI ) ; break ; case <STR_LIT> : expandERet ( MBB , MI ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : case <STR_LIT>


<s> if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr & DefMI = * MRI -> getVRegDef ( Reg ) ; if ( ( DefMI . getOpcode ( ) != <STR_LIT> && DefMI . getOpcode ( ) != <STR_LIT> ) || DefMI .

getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ;


<s> bool isCondCode ( ) const { return Kind


<s> union { __ev64_opaque__ v ; uint64_t i ; } u ; u . i =


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> FunctionPass * llvm :: create<ISA_LIT>FixupBWInsts ( ) { return new FixupBWInstPass ( )


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , RM , CM ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo *

) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) :


<s> if ( c == <NUM_LIT> || c == ~ <NUM_LIT> ) return <NUM_LIT> ; shift_mask = ~ <NUM_LIT> ; shift_mask <<= INTVAL ( shiftop ) ; lsb = c & - c ; if ( - lsb != shift_mask ) return <NUM_LIT> ; c = ~ c ; c &= - lsb ; lsb = c & - c ; return c == - lsb ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , high , lsb ; HOST_WIDE_INT shift_mask_low , shift_mask_high ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < <NUM_LIT> ) high = CONST_DOUBLE_HIGH ( andop ) ; if ( ( low == <NUM_LIT> && ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> || high == <NUM_LIT> ) ) || ( low == ~ <NUM_LIT> && ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> || high == ~ <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( HOST_BITS_PER_WIDE_INT < <NUM_LIT> && low == <NUM_LIT> ) { shift_mask_high = ~ <NUM_LIT> ; if ( INTVAL ( shiftop ) > <NUM_LIT> ) shift_mask_high <<= INTVAL ( shiftop ) - <NUM_LIT> ; lsb = high & - high ; if ( - lsb != shift_mask_high || INTVAL ( shiftop ) < <NUM_LIT> ) return <NUM_LIT> ; high = ~ high ; high &= - lsb ; lsb = high & - high ; return high ==


<s> AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG (


<s> tree minus_one_vec = build_minus_one_cst ( type ) ; tree temp = create_tmp_reg_or_ssa_name ( cmp_type ) ; gimple * g = gimple_build_assign ( temp , code , arg0 , arg1 ) ; gsi_insert_before ( gsi , g


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT


<s> return <STR_LIT> ; case FpABIKind :: S32 : return <STR_LIT> ; case FpABIKind :: S64 : if ( Is32BitABI ) return OddSPReg


<s> static bool ix86_profile_before_prologue ( void ) { return flag_fentry


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> case IES_DIVIDE : case IES_MULTIPLY : case IES_LPAREN : State = IES_INTEGER ; if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { assert ( ! IndexReg && <STR_LIT> ) ; IndexReg = TmpReg ; Scale = TmpInt ; if ( Scale != <NUM_LIT> && Scale != <NUM_LIT> && Scale != <NUM_LIT> && Scale != <NUM_LIT> ) { ErrMsg = <STR_LIT> ; return true ; } IC . popOperator ( ) ; } else if ( ( PrevState == IES_PLUS || PrevState == IES_MINUS || PrevState == IES_OR || PrevState == IES_AND || PrevState == IES_LSHIFT || PrevState == IES_RSHIFT || PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE || PrevState == IES_LPAREN || PrevState == IES_LBRAC || PrevState == IES_NOT ) && CurrState == IES_MINUS ) { IC . pushOperand ( IC_IMM , - TmpInt ) ; } else if ( ( PrevState == IES_PLUS || PrevState == IES_MINUS || PrevState == IES_OR || PrevState == IES_AND || PrevState == IES_LSHIFT || PrevState == IES_RSHIFT || PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE || PrevState == IES_LPAREN || PrevState == IES_LBRAC || PrevState == IES_NOT ) && CurrState == IES_NOT ) { IC . pushOperand ( IC_IMM , ~ TmpInt ) ; } else { IC . pushOperand ( IC_IMM , TmpInt ) ; } break ; } PrevState = CurrState


<s> return ( ( vec_double2 ) ( si_eqv ( ( qword ) ( a ) , (


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , Mask , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs


<s> SDValue VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , SVT . getStoreSize ( ) , SVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getMaskedStore ( Chain , dl , DataToTruncate , Addr , VMask , SVT


<s> return new <ISA_LIT>MCInstrAnalysis (


<s> static SDValue LowerBuildVectorv16i8 ( SDValue Op , unsigned NonZeros , unsigned NumNonZero , unsigned NumZero , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget , const TargetLowering & TLI ) { if ( NumNonZero > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue V ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt , LastElt ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) )


<s> if ( calc_live_regs ( & dummy ) >= <NUM_LIT>


<s> if ( auto * Cast = dyn_cast < BitCastInst > ( Op0 ) ) { if ( ! Cast -> getSrcTy ( ) -> isFloatTy ( ) && ! Cast -> getSrcTy ( ) -> isDoubleTy ( ) && ! Cast -> getSrcTy ( ) -> isFP128Ty ( ) ) return ; Value * V = Cast -> getOperand ( <NUM_LIT> ) ; int Mask ; if ( Pred == CmpInst :: ICMP_SLT && Const -> isZero ( ) ) { Mask = <STR_LIT> ; } else if ( Pred == CmpInst :: ICMP_SGT && Const -> isMinusOne ( ) ) { Mask = <STR_LIT> ; } else { return ; } PossibleJunk . insert ( Cast ) ; converted ( & I , V , Mask , true ) ; } else if ( auto * CI = dyn_cast < CallInst > ( Op0 ) ) { Function * F = CI -> getCalledFunction ( ) ; if ( ! F || F -> getIntrinsicID ( ) != <STR_LIT> ) return ; if ( ! Const -> isZero ( ) ) return ; Value * V = CI -> getArgOperand ( <NUM_LIT> ) ; auto * MaskC = dyn_cast < ConstantInt > ( CI -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! MaskC ) return ; int Mask = MaskC -> getZExtValue ( ) ; Mask &= <STR_LIT> ; if ( Pred == CmpInst :: ICMP_NE ) { } else if ( Pred == CmpInst :: ICMP_EQ ) { Mask ^= <STR_LIT>


<s> return __builtin_mve_vornq_m_uv4si ( __arm_vuninitializedq_u32 ( ) ,


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) :

<ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) {


<s> return ( uint32x2_t ) __builtin_neon_vdup_nv2si ( (


<s> static bool resolveTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , SelectionDAG & DAG , unsigned Depth ) { unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue


<s> std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; FuncInfo . EHRegNode = RegNode ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , FuncInfo ) ; break ; case EHPersonality :: MSVC_<ISA_LIT>SEH : addSEHStateStores ( F , FuncInfo


<s> const <ISA_LIT>_64GNULDBackend & getTarget (


<s> SDLoc DL ( Op ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) , DL ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> )


<s> if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = <NUM_LIT> ; } ScoreboardHazardRecognizer :: EmitInstruction (


<s> uint8_t getCPR2SizeValue ( ) { return ( uint8_t )


<s> return ( __m256 ) __builtin_ia32_broadcastf32x2_256_mask ( ( __v4sf ) __A , ( __v8sf ) _mm256_undefined_ps ( ) , ( __mmask8


<s> bool MadeChange = false ; if ( Buckets . empty ( ) ) return MadeChange ; SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( auto & Bucket : Buckets ) if ( prepareBaseForUpdateFormChain ( Bucket ) ) MadeChange |= rewriteLoadStores ( L , Bucket , BBChanged , UpdateForm ) ; if ( MadeChange ) for ( auto & BB : L -> blocks ( ) ) if ( BBChanged . count ( BB ) ) DeleteDeadPHIs ( BB ) ; return MadeChange


<s> if ( ! isPowerOf2_32 ( NumElems ) ) return SDValue ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; assert ( DstVT . getVectorNumElements ( ) == NumElems && <STR_LIT> ) ; assert ( SrcSizeInBits > DstSizeInBits && <STR_LIT> ) ; EVT PackedSVT = EVT :: getIntegerVT ( Ctx , SrcVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; EVT InVT = <STR_LIT> , OutVT = <STR_LIT> ; if ( SrcVT . getScalarSizeInBits ( ) > <NUM_LIT> && ( Opcode == <STR_LIT> || Subtarget . hasSSE41 ( ) ) ) { InVT = <STR_LIT> ; OutVT = <STR_LIT> ; } if ( SrcVT . is128BitVector ( ) ) { InVT = EVT :: getVectorVT ( Ctx , InVT , <NUM_LIT> / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , <NUM_LIT> / OutVT . getSizeInBits ( ) ) ; In = DAG . getBitcast ( InVT , In ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , In , In ) ; Res = extractSubVector ( Res , <NUM_LIT> , DAG , DL , <NUM_LIT> ) ; return DAG . getBitcast ( DstVT , Res ) ; } unsigned NumSubElts = NumElems / <NUM_LIT> ; SDValue Lo = extractSubVector ( In , <NUM_LIT> * NumSubElts , DAG , DL , SrcSizeInBits / <NUM_LIT> ) ; SDValue Hi = extractSubVector ( In , <NUM_LIT> * NumSubElts , DAG , DL , SrcSizeInBits / <NUM_LIT> ) ; unsigned SubSizeInBits = SrcSizeInBits / <NUM_LIT> ; InVT = EVT :: getVectorVT ( Ctx , InVT , SubSizeInBits / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , SubSizeInBits / OutVT . getSizeInBits ( ) ) ; if ( SrcVT . is256BitVector ( ) && DstVT . is128BitVector (


<s> Type * SingleMemOpTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , MaybeAlign ( Alignment ) , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT>


<s> int64_t CNVal = CN -> getSExtValue ( ) ; if ( ( int32_t ) CNVal != CNVal ) return Val ; if ( Op == ADD ) { if ( ( CNVal == <NUM_LIT> ) || ( CNVal == - <NUM_LIT> ) ) { Op = ( CNVal == <NUM_LIT> ) ? INC : DEC ; return SDValue ( ) ; } if ( CNVal < <NUM_LIT> ) { Op = SUB ; CNVal = - CNVal ; } } return CurDAG -> getTargetConstant ( CNVal ,


<s> unsigned Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; return <ISA_LIT>SelectFPExtOrFPTrunc ( I , Opc , & <STR_LIT>


<s> switch ( MI -> getOpcode ( ) ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isFPCmp = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) )


<s> const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return <NUM_LIT> ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> )


<s> extern_symbol * p = VEC_safe_push ( extern_symbol , gc , extern_symbols , NULL ) ; gcc_assert ( file ==


<s> TII = TM -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed =


<s> if ( ! ret ) ++ ( insn -> readerCursor ) ; return


<s> if ( ! maybe_expand_insn ( icode , nops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode )


<s> for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( i != PC_REGNUM ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ) = tmp ; dwarf_par_index ++ ; } break ; } } for ( j = <NUM_LIT> , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( <NUM_LIT> <<


<s> if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility (

) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ;


<s> <ISA_LIT>MCExpr :: VariantKind RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; <ISA_LIT>MCExpr :: VariantKind SymLoc = <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) ; if ( Kind == <STR_LIT> && SymLoc == <ISA_LIT>MCExpr :: VK_GOT ) return true ; return false


<s> unsigned FP = Subtarget . isGP32bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned BP = Subtarget . isGP32bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! Subtarget . hasStandardEncoding ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP


<s> getThumbCBTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup >


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I

) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> static DecodeStatus DecodeCCRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> void <ISA_LIT>ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM .


<s> rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode ,


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMicro<ISA_LIT> ( ) { Micro<ISA_LIT>Enabled =


<s> if ( STI . isTargetDarwin ( ) || STI . isThumb1Only ( ) ) FramePtr = <STR_LIT> ; else FramePtr = <STR_LIT> ; } else if ( STI . isTargetWindows ( ) ) FramePtr = <STR_LIT> ; else FramePtr = STI . isThumb ( )


<s> void WinEHStatePass :: addStateStoresToFunclet ( Value * ParentRegNode , WinEHFuncInfo & FuncInfo , Function & F , int BaseState ) { for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { if ( auto * CI = dyn_cast < CallInst > ( & I ) ) { if ( CI -> doesNotThrow ( ) ) continue ; insertStateNumberStore ( ParentRegNode , CI


<s> bool isWin64 ( ) { return Subtarget . isCallingConvWin64


<s> virtual const Dcpu16RegisterInfo * getRegisterInfo ( )


<s> Op -> PSBHint . Data = Str . data ( ) ; Op -> PSBHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i + NumElems / <NUM_LIT> ) , i + NumElems ) ) return false ; return true


<s> return ( unsigned long long ) __builtin_sh_media_MSHALDS_L ( ( v2si ) mm


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! EmitJalrReloc || Subtarget . in<ISA_LIT>16Mode ( ) || ! isPositionIndependent ( ) || Node -> getNumOperands ( ) < <NUM_LIT> || Node -> getOperand ( <NUM_LIT> ) . getNumOperands ( ) < <NUM_LIT> ) { return ; } const SDValue TargetAddr = Node -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; StringRef Sym ; if ( const GlobalAddressSDNode * G = dyn_cast_or_null < const GlobalAddressSDNode > ( TargetAddr ) ) { if ( ! isa < Function > ( G -> getGlobal ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << G -> getGlobal ( ) -> getName ( ) << <STR_LIT> ) ; return ; } Sym = G -> getGlobal ( ) -> getName ( ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( TargetAddr ) ) { Sym = ES -> getSymbol ( ) ; } if ( Sym . empty ( ) ) return ; MachineFunction * MF = MI . getParent ( ) ->


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) )


<s> RtMI = Paired ; Rt2MI = I ; } else { RtMI = I ; Rt2MI = Paired ; } int OffsetImm = RtMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ) OffsetImm /= OffsetStride ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( RtMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( Rt2MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs (


<s> if ( TARGET_ELF ) addis_str = <STR_LIT> ; else if ( TARGET_XCOFF ) addis_str = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( GET_CODE ( value ) == PLUS ) { rtx op0 = XEXP ( value , <NUM_LIT> ) ; rtx op1 = XEXP ( value , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == UNSPEC && XINT ( op0 , <NUM_LIT> ) == UNSPEC_TOCREL && CONST_INT_P ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( op0 , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( op0 , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = op1 ; if ( TARGET_ELF ) addis_str = <STR_LIT> ; else if ( TARGET_XCOFF ) addis_str = <STR_LIT> ; else gcc_unreachable ( ) ; } } else if ( satisfies_constraint_L ( value ) ) { fuse_ops [ <NUM_LIT> ] = value ; addis_str = <STR_LIT> ; } else if ( TARGET_ELF && ! TARGET_POWERPC64 && CONSTANT_P ( value ) ) { fuse_ops [ <NUM_LIT> ] = value ; addis_str = <STR_LIT> ; } } if ( ! addis_str ) fatal_insn ( <STR_LIT> , addis_value ) ; sprintf ( insn_template , <STR_LIT> , addis_str , comment_str , mode_name ) ; output_asm_insn ( insn_template , fuse_ops ) ; if ( CONST_INT_P ( load_offset ) && satisfies_constraint_I ( load_offset ) ) { sprintf ( insn_template , <STR_LIT> , load_str ) ; fuse_ops [ <NUM_LIT> ] = load_offset ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( GET_CODE ( load_offset ) == UNSPEC && XINT ( load_offset , <NUM_LIT> ) == UNSPEC_TOCREL ) { if ( TARGET_ELF ) sprintf ( insn_template , <STR_LIT> , load_str ) ; else if ( TARGET_XCOFF ) sprintf ( insn_template , <STR_LIT> , load_str ) ; else gcc_unreachable ( ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( load_offset , <NUM_LIT> , <NUM_LIT> ) ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( GET_CODE ( load_offset ) == PLUS && GET_CODE ( XEXP ( load_offset , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( load_offset , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TOCREL && CONST_INT_P ( XEXP ( load_offset , <NUM_LIT> ) ) ) { rtx tocrel_unspec = XEXP ( load_offset , <NUM_LIT> ) ; if ( TARGET_ELF ) sprintf ( insn_template , <STR_LIT> , load_str ) ; else if ( TARGET_XCOFF ) sprintf ( insn_template , <STR_LIT> , load_str ) ; else gcc_unreachable ( ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( tocrel_unspec , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XEXP ( load_offset , <NUM_LIT> ) ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( TARGET_ELF && ! TARGET_POWERPC64 && CONSTANT_P ( load_offset ) ) { sprintf ( insn_template , <STR_LIT> , load_str ) ; fuse_ops [ <NUM_LIT> ] = load_offset ; output_asm_insn ( insn_template , fuse_ops ) ; } else fatal_insn ( <STR_LIT> , load_offset


<s> bool IsLargeFrame = ! isInt < <NUM_LIT> > ( NegFrameSize ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Align MaxAlign = MFI . getMaxAlign ( ) ; bool HasRedZone = Subtarget . is<ISA_LIT>64 ( ) || !


<s> if ( Thumb2PreloadOpcodeNoPCI ( Opcode ) && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Opcode = T2Morph2Preload2PCI ( Opcode ) ; <ISA_LIT>Format Format = <ISA_LIT>Formats [ Opcode ] ; Size = IsThumb2 ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( { errs ( ) << <STR_LIT> << Opcode << <STR_LIT> << <STR_LIT> ( Opcode ) << <STR_LIT> << stringFor<ISA_LIT>Format ( Format ) << '(' << ( int ) Format << <STR_LIT> ; showBitVector ( errs ( ) , insn ) ; } ) ; <ISA_LIT>BasicMCBuilder * Builder = CreateMCBuilder ( Opcode , Format ) ; Builder -> SetSession ( const_cast < Session * > ( & SO ) ) ; if ( ! Builder ) return false ; if ( ! Builder -> Build ( MI , insn ) )


<s> const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { unsigned AlignMinus1 = MRI . createGenericVirtualRegister ( IntPtrTy ) ; MIRBuilder . buildConstant ( AlignMinus1 , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ; unsigned SizeReg = MRI . createGenericVirtualRegister ( IntPtrTy ) ; MIRBuilder . buildConstant ( SizeReg , alignTo ( ValSize , PtrSize ) ) ; unsigned NewList = MRI . createGenericVirtualRegister


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool IsWin64 = Subtarget -> isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumGPRArgRegs = array_lengthof ( GPRArgRegs ) ; unsigned FirstVariadicGPR = CCInfo . getFirstUnallocated ( GPRArgRegs ) ; unsigned GPRSaveSize = <NUM_LIT> * ( NumGPRArgRegs - FirstVariadicGPR ) ; int GPRIdx = <NUM_LIT> ; if ( GPRSaveSize != <NUM_LIT> ) { if ( IsWin64 ) { GPRIdx = MFI . CreateFixedObject ( GPRSaveSize , - ( int ) GPRSaveSize , false ) ; if ( GPRSaveSize & <NUM_LIT> ) MFI . CreateFixedObject ( <NUM_LIT> - ( GPRSaveSize & <NUM_LIT> ) , - ( int ) alignTo ( GPRSaveSize , <NUM_LIT> ) , false ) ; } else GPRIdx = MFI . CreateStackObject ( GPRSaveSize , Align ( <NUM_LIT> ) , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , IsWin64 ? MachinePointerInfo :: getFixedStack ( MF , GPRIdx , ( i - FirstVariadicGPR ) * <NUM_LIT> ) : MachinePointerInfo :: getStack ( MF , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsWin64 ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , Align ( <NUM_LIT> ) , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx


<s> S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } } case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: Create ( RefKind , SubExprVal , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ExprVal , S ,


<s> static int getMemScale ( const MachineInstr &


<s> bool allowMixed16_32 ( ) const { return in<ISA_LIT>16ModeDefault


<s> if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , true ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , {


<s> if ( Flags . isSExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( ValVT ) ) ; else if ( Flags . isZExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG


<s> bool <ISA_LIT>Subtarget :: isPC32DBLSymbol ( const GlobalValue * GV , Reloc

:: Model RM , CodeModel :: Model CM ) const {


<s> void <ISA_LIT>OutgoingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState ::


<s> if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode >


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI


<s> if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( XEXP ( SET_SRC ( curr_set ) , <NUM_LIT> ) ) && REGNO ( XEXP ( SET_SRC ( curr_set ) , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) && rtx_equal_p ( XEXP ( SET_SRC ( prev_set ) , <NUM_LIT> ) , XEXP ( SET_SRC ( curr_set ) , <NUM_LIT> ) ) ) return true ; } } if ( simple_sets_p && aarch64_fusion_enabled_p ( AARCH64_FUSE_MOVK_MOVK ) ) { if ( GET_CODE ( SET_DEST ( prev_set ) ) == ZERO_EXTRACT && GET_CODE ( SET_DEST ( curr_set ) ) == ZERO_EXTRACT && REG_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && REG_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && REGNO ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == REGNO ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && INTVAL ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) == <NUM_LIT> && CONST_INT_P ( SET_SRC ( prev_set ) ) && CONST_INT_P ( SET_SRC ( curr_set ) ) ) return true ; } if ( simple_sets_p && aarch64_fusion_enabled_p


<s> return decodeBDXAddr12Operand ( Inst , Field , <STR_LIT>


<s> if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( SelectAddrMode2Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , Offset , AMOpc , getAL ( CurDAG ) ,

CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ;


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU


<s> return __builtin_mve_vldrbq_sv16qi ( ( __builtin_neon_qi *


<s> if ( ( rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_MFCRF ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POWERPC64 ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; } if ( DEFAULT_ABI == ABI_ELFv2 ) fprintf ( file , <STR_LIT> ) ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || ( TARGET_ELF && flag_pic == <NUM_LIT> ) ) { switch_to_section ( toc_section )


<s> void addRegVRRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( VRegs [ getReg


<s> if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind


<s> DebugLoc dl = Ld -> getDebugLoc ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; if ( RegVT . isVector ( ) && Ext == <STR_LIT> && Subtarget -> hasSSE41 ( ) ) { assert ( MemVT != RegVT && <STR_LIT> ) ; assert ( MemVT . isVector ( ) && <STR_LIT> ) ; unsigned NumElems = RegVT . getVectorNumElements ( ) ; unsigned RegSz = RegVT . getSizeInBits ( ) ; unsigned MemSz = MemVT . getSizeInBits ( ) ; assert ( RegSz > MemSz && <STR_LIT> ) ; if ( ! isPowerOf2_32 ( RegSz * MemSz * NumElems ) ) return SDValue ( ) ; MVT SclrLoadTy = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) == MemSz ) { SclrLoadTy = Tp ; break ; } } if ( SclrLoadTy . getSizeInBits ( ) != MemSz ) return SDValue ( ) ; EVT LoadUnitVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclrLoadTy , RegSz / SclrLoadTy . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , RegSz / MemVT . getScalarType ( ) . getSizeInBits ( ) ) ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; SDValue ScalarInVector = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; SDValue SlicedVec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , ScalarInVector ) ; unsigned SizeRatio = RegSz


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSNaCl ( ) ) return new NaCl<ISA_LIT>AsmBackend ( T , false ) ; return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , true ,


<s> if ( ! mnemonicIsValid ( Name , <NUM_LIT> ) ) { uint64_t FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( Name , FBS ) ; return Error ( NameLoc , <STR_LIT> + Suggestion ) ; } Operands . push_back ( <STR_LIT> ( Name , NameLoc , * this ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer (


<s> emitCalleeSavedRestores ( MBB , MBBI , false


<s> } if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( f , mode ) ) attrs = aarch64_add_attribute ( <STR_LIT> , attrs ) ; return aarch64_add_attribute ( <STR_LIT>


<s> if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ( ! SUBREG_P ( XEXP ( src , <NUM_LIT> ) ) || SUBREG_BYTE ( XEXP ( src , <NUM_LIT> ) ) != <NUM_LIT> || ! REG_P ( SUBREG_REG ( XEXP ( src , <NUM_LIT> ) ) ) ) && ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != QImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) )


<s> InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte && InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> inline bool sh_is_movt_insn ( const rtx_insn * i ) { return sh_movt_set_dest ( i


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> setAttributeItems ( Attribute , IntValue , StringValue ,