<s> int NumLoInputs = count_if ( Mask , [ Size ] ( int M ) { return M >= <NUM_LIT> && M % Size < Size / <NUM_LIT> ; } ) ; int NumHiInputs = count_if ( Mask , [ Size ] ( int M ) { return M % Size >= Size / <NUM_LIT> ; } ) ; bool UnpackLo = NumLoInputs >= NumHiInputs ; auto TryUnpack = [ & ] ( MVT UnpackVT , int Scale ) { SmallVector < int , <NUM_LIT> > V1Mask ( Mask . size ( ) , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > V2Mask ( Mask . size ( ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int UnpackIdx = i / Scale ; if ( ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) != ( Mask [ i ] < Size ) ) return SDValue ( ) ; SmallVectorImpl < int > & VMask = ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) ? V1Mask : V2Mask ; VMask [ ( UnpackIdx / <NUM_LIT> ) * Scale + i % Scale + ( UnpackLo ? <NUM_LIT> : Size / <NUM_LIT> ) ] = Mask [ i ] % Size ; } if ( ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) && ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) return SDValue ( ) ; V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; V1 = DAG . getBitcast ( UnpackVT , V1 ) ; V2 = DAG . getBitcast ( UnpackVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigNumElements = VT . getVectorNumElements ( ) ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) { int Scale = ScalarSize / OrigScalarSize ; int NumElements = OrigNumElements / Scale ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , NumElements ) ; if ( SDValue Unpack = TryUnpack ( UnpackVT , Scale ) ) return Unpack ; } if ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) { assert ( ( NumLoInputs > <NUM_LIT> || NumHiInputs > <NUM_LIT> ) && <STR_LIT> ) ; int HalfOffset = NumLoInputs == <NUM_LIT> ? Size / <NUM_LIT> : <NUM_LIT> ; SmallVector < int , <NUM_LIT> > PermMask ( (


<s> rtx insn ; for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno -- > <NUM_LIT> ; ) if

( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) {


<s> void <ISA_LIT>InstPrinter :: printLogicalImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; O <<


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _get_ssp ( void ) { return __builtin_ia32_rdsspd


<s> } } for ( auto * T : Truncs ) { if ( T -> hasOneUse ( ) && ! isa < StoreInst > ( * T -> user_begin ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * T << <STR_LIT> ) ; return true ; } } for ( auto * E : Exts ) { if ( ! E -> hasOneUse ( ) || cast < Instruction > ( * E -> user_begin ( ) ) -> getOpcode ( ) != Instruction :: Mul ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * E << <STR_LIT> ) ; return


<s> const unsigned DstR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; int addrr_opcode , addri_opcode ; switch ( opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = nullptr ; const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( SrcR1 != <NUM_LIT> && SrcR2 != <NUM_LIT> ) { const MachineOperand & Src1 = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; const MachineOperand & Src2 = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( addrr_opcode ) ) . add ( Dst ) . add ( Src1 ) . add ( Src2 ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MachineOperand & SrcR = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( addri_opcode ) ) . add ( Dst ) . add ( SrcR ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MFI -> insert ( I ,


<s> SDLoc dl ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . is256BitVector ( ) && SubVecVT . is128BitVector ( ) ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , false ) ) return Ld ; } } if ( auto * Ld = dyn_cast < LoadSDNode > ( peekThroughOneUseBitcasts ( SubVec2 ) ) ) { if ( SubVec2 == SubVec && <STR_LIT> ( Ld ) && areOnlyUsersOf ( SubVec2 . getNode ( )

, { Op , Vec } ) && ! Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) {


<s> for ( MVT LegalVecVT : AllVectorVTs ) { setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Custom


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned Base , Index ; const MCExpr * Expr ; if ( parseAddress ( Base , Expr , Index , <STR_LIT> , <ISA_LIT>Operand :: ADDR64Reg , true ) ) return true ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( Base || Index ) Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc


<s> if ( * cum < NUM_ARGUMENT_REGISTERS && ( * cum + XSTORMY16_WORD_SIZE ( arg . type , arg . mode ) > NUM_ARGUMENT_REGISTERS ) ) * cum = NUM_ARGUMENT_REGISTERS ; * cum += XSTORMY16_WORD_SIZE ( arg .


<s> Candidates . clear ( ) ; for ( size_t i = <NUM_LIT> ; i < array_lengthof ( Filters ) ; i ++ ) if ( Filters [ i ] -> check ( * BB , * I ) ) Candidates . push_back ( Filters [ i ] ) ; if ( Candidates . empty ( ) ) { ++ I ; continue ; } unsigned int Roll = RNG -> Random ( <NUM_LIT> ) ; ++ EquivSubstCandidates ; if ( Roll >= multicompiler :: EquivSubstPercentage ) { ++ I ; continue ; } unsigned int Pick = RNG -> Random ( Candidates . size ( ) ) ; MachineBasicBlock :: iterator J = I ; ++ I


<s> in . v = ( vec_double2 ) ( a ) ; d . v = ( vec_float4 ) { <NUM_LIT> } ; d . f [ <NUM_LIT> ] = ( float ) in . d [


<s> void addACC64DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> Parser . Lex ( ) ; MCSymbol * Func = getParser ( ) . getContext ( ) . GetOrCreateSymbol ( Name ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; return


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N ) -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ; if ( ! CR ) return TM .


<s> return __builtin_mve_vbicq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a , __b ,


<s> bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue In = Op . getOperand ( IsStrict


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>BaseTargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> bool <ISA_LIT>RegisterBankInfo :: onlyDefinesFP ( const MachineInstr & MI , const MachineRegisterInfo

& MRI , const TargetRegisterInfo & TRI ) const {


<s> if ( NumElts == <NUM_LIT> ) { Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ; DAG . UpdateNodeOperands ( N , Ops ) ; return Op ; } NumElts = <NUM_LIT> ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , NumElts ) ; Index = ExtendToType ( Index , NewIndexVT , DAG ) ; if ( IndexVT . getScalarType ( ) == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; MVT MaskBitVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; assert ( MaskVT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , NumElts ) ; Mask = ExtendToType ( Mask , ExtMaskVT


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X (


<s> bool isU7ImmX4 ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) && (

getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ; }


<s> static tree ix86_d_handle_target_float_abi ( void ) { const char * abi ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) abi = <STR_LIT> ; else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi ) + <NUM_LIT>


<s> size_t <ISA_LIT>ELFDynamic :: getLocalGotNum ( const ELFFileFormat & pFormat


<s> Streamer . visitUsedExpr ( * getSubExpr


<s> void printMemOffs64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemOffset ( MI , OpNo , O


<s> unsigned OffsetLo = ( unsigned ) ( Offset & <NUM_LIT> ) ; unsigned OffsetHi = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm

( OffsetLo ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> if ( CONST_INT_P ( size ) ) return nds32_expand_movmemsi_loop_known_size ( dstmem , srcmem , size , alignment ) ; else return nds32_expand_movmemsi_loop_unknown_size ( dstmem , srcmem


<s> } const MCSymbolRefExpr * SE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; if ( SE ) { DarwinRefKind = SE -> getKind ( ) ; return true ; } const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; SE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; if ( ! SE ) return false ; DarwinRefKind = SE -> getKind ( ) ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; auto AddendExpr = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; if ( ! AddendExpr ) return false ; Addend = AddendExpr ->


<s> case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - DefaultSafety ; case


<s> if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE

) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ;


<s> sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_BSS : sname = <STR_LIT> ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = <STR_LIT> ; flags = <NUM_LIT> ; break ; case SECCAT_SRODATA : case


<s> Parser . Lex ( ) ; AsmToken Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Equal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; Tok = Parser . getTok ( ) ; if ( ! parseFpABIValue ( FpAbiVal , <STR_LIT> ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> void addImmWithLSLOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , ImmWithLSL


<s> static inline void maybe_add_dllexport ( tree decl ) { if ( i386_pe_type_dllexport_p ( decl ) ) { tree decl_attrs = DECL_ATTRIBUTES ( decl ) ; if ( lookup_attribute ( <STR_LIT> , decl_attrs ) != NULL_TREE ) return ; DECL_ATTRIBUTES ( decl ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE


<s> else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; unsigned ByteSize = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( StackSlot ) ; MachineMemOperand * MMO ; if ( FI ) { int SSFI = FI -> getIndex ( ) ; MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , ByteSize , ByteSize ) ; } else { MMO = cast < LoadSDNode > ( StackSlot ) -> getMemOperand ( ) ; StackSlot = StackSlot . getOperand ( <NUM_LIT> ) ; } SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , Ops , SrcVT , MMO ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( SSFISize , SSFISize , false ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Result , StackSlot , DAG . getValueType ( Op . getValueType ( ) ) , InFlag } ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOStore , SSFISize , SSFISize ) ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , Op . getValueType ( ) , MMO ) ; Result = DAG . getLoad ( Op . getValueType ( ) , DL , Chain , StackSlot , MachinePointerInfo :: getFixedStack

( DAG . getMachineFunction ( ) , SSFI ) ) ;


<s> int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , mode , type , true ) != <NUM_LIT> ) return


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize


<s> else CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ; if ( CC != - <NUM_LIT> ) return CC ; if ( Name [ <NUM_LIT> ] == 'f' ) { StringRef NumString = Name . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; FpFormatTy Format = getFpFormat ( )


<s> void <ISA_LIT>TargetStreamer :: emitFnEnd (


<s> if ( VECTOR_MODE_P ( mode ) ) inner_mode = GET_MODE_INNER ( mode ) ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) return inner_mode == DFmode ? cost -> divsd : cost -> divss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fdiv ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> divsd : cost -> divss ) ; else return cost -> divide [ MODE_INDEX ( mode


<s> if ( Available . size ( ) == <NUM_LIT> ) dbgs ( ) << <STR_LIT> ; Candidate c ( SU , * HazardRec ) ; c . dumpCosts ( ) ; dbgs ( ) << <STR_LIT> ; ) ; Available . erase (


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ; assert ( MO . isImm ( ) &&


<s> unsigned VF = cast < VectorType > ( SrcVTy ) -> getNumElements ( ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( cast < VectorType > ( Ptr -> getType ( ) ) -> getElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ; if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy , VariableMask , Alignment , AddressSpace ) ; return getGSVectorCost ( Opcode , SrcVTy , Ptr ,


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI


<s> void aarch64_asm_output_labelref ( FILE * f , const char * name ) { asm_fprintf ( f , <STR_LIT> ,


<s> virtual void finalizePass ( ) { popTTIStack (


<s> void RecordRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup &

Fixup , MCValue Target , uint64_t & FixedValue ) override {


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef CPU ) : MCAsmBackend ( ) , CPU ( CPU ) , MaxNopLength ( ( CPU == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) { HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal )


<s> unsigned int Roll = RNG -> Random ( <NUM_LIT> ) ; ++ EquivSubstCandidates ; if ( Roll >= multicompiler :: EquivSubstPercentage ) { ++ I ; continue ; } unsigned int Pick = RNG -> Random ( Candidates . size ( ) ) ; MachineBasicBlock :: iterator J = I ; ++ I ; Candidates [ Pick ] -> subst ( * BB , TII , J ) ; Changed = true ; ++ EquivSubstituted ; } return


<s> if ( IsMemAccess || IsSPFirstOperand ) { bool MaskBefore = ( IsMemAccess && baseRegNeedsLoadStoreMask ( Inst . getOperand ( AddrIdx ) . getReg ( ) ) ) ; bool MaskAfter = IsSPFirstOperand && ! IsStore ; if ( MaskBefore || MaskAfter ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; sandboxLoadStoreStackChange ( Inst , AddrIdx , STI , MaskBefore , MaskAfter ) ; return ; } } bool IsIndirectCall ; if ( isCall ( Inst , & IsIndirectCall ) ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; EmitBundleLock ( true ) ; if ( IsIndirectCall ) { unsigned TargetReg = Inst . getOperand ( <NUM_LIT> ) . getReg


<s> int f_target , n_target = <NUM_LIT> ; if ( optimize ) { if ( INSN_ADDRESSES_SIZE ( ) <= ( unsigned ) INSN_UID ( new_mova ) ) return - <NUM_LIT> ; n_addr = INSN_ADDRESSES ( INSN_UID ( new_mova ) ) ; n_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( new_mova ) , <NUM_LIT> ) ) ) ; if ( n_addr > n_target || n_addr + <NUM_LIT> < n_target ) { fixup_mova ( new_mova ) ; return <NUM_LIT> ; } } if ( ! ( * num_mova ) ++ ) { * first_mova = new_mova ; return <NUM_LIT> ; } if ( ! optimize || ( ( f_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( * first_mova ) , <NUM_LIT> ) ) ) ) >= n_target ) ) return - <NUM_LIT> ; ( * num_mova ) -- ; if ( f_target - INSN_ADDRESSES ( INSN_UID ( * first_mova ) ) > n_target - n_addr ) { fixup_mova ( * first_mova ) ; return <NUM_LIT> ; } else { fixup_mova ( new_mova ) ; return <NUM_LIT>


<s> SrcOp = DAG . getBitcast ( ShVT , SrcOp ) ; assert ( NumBits % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; SDValue ShiftVal = DAG . getTargetConstant ( NumBits / <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( Opc , dl , ShVT ,


<s> SDValue Mask = getNodeMask ( Op ) ; SDValue Chain = getNodeChain ( Op ) ; SDValue Scale = getGatherScatterScale ( Op ) ; SDValue PassThru = getNodePassthru ( Op ) ; SDValue StoredValue = getStoredValue ( Op ) ; if ( PassThru && PassThru -> isUndef ( ) ) PassThru = SDValue ( ) ; bool IsScatter = ( bool ) StoredValue ; if ( ! AVL ) AVL = CDAG . getConstant ( DataVT . getVectorNumElements ( ) , <STR_LIT> ) ; if ( ! Mask ) Mask = CDAG . getConstantMask ( Packing , true ) ; SDValue AddressVec = CDAG . getGatherScatterAddress ( BasePtr , Scale ,


<s> rounded = vec_rint ( __A ) ; temp = vec_cts ( rounded , <NUM_LIT> ) ; result = ( __vector unsigned long long ) vec_pack ( temp , temp ) ; return ( __m64 ) ( ( __vector long long


<s> inline SDValue getI32Imm ( unsigned Imm , SDLoc dl ) { return CurDAG -> getTargetConstant ( Imm , dl


<s> switch ( RC -> getSize ( ) / <NUM_LIT> ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; }


<s> } const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT>


<s> if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> <<


<s> if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( cast < VectorType > ( DataTy ) -> getNumElements ( ) == <NUM_LIT> ) return false ; Type * ScalarTy = cast < VectorType > ( DataTy ) ->


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , nullptr ) ; } } if ( ! Constraint . empty ( ) ) { std :: pair < unsigned ,


<s> MCSymbol * <ISA_LIT>ELFStreamer :: EmitCFILabel ( ) { MCSymbol * Label = getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MCELFStreamer :: EmitLabel ( Label ) ; return


<s> if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return Fail ; DecodeZPRRegisterClass ( Inst , Zdn , Addr , Decoder ) ; if ( Inst . getOpcode ( ) != <STR_LIT> ) DecodeZPRRegisterClass ( Inst , Zdn , Addr , Decoder ) ; Inst . addOperand ( MCOperand ::


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return Reserved


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) return <STR_LIT> ; if ( OpFlags == <STR_LIT> || OpFlags == <STR_LIT> ) return


<s> OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( AnonSymbol -> getName ( ) ) ) ; OutStreamer . EmitLabel ( AnonSymbol ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; else OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind ::


<s> static machine_mode counter_mode ( rtx count_exp ) { if ( GET_MODE ( count_exp ) != VOIDmode ) return GET_MODE ( count_exp ) ; if ( ! CONST_INT_P ( count_exp ) ) return Pmode ; if ( TARGET_64BIT && ( INTVAL ( count_exp ) & ~ <NUM_LIT> ) ) return DImode ; return


<s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = CodeModel :: Large ; else if ( CM != CodeModel :: Small && CM !=

CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitMOVLPD (


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL ,


<s> assert ( ( ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] && ! OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ] ] ) && <STR_LIT> ) ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ RegOpcodes [ <NUM_LIT> ] ] = G ; OpcodeToGroup [ MemOpcodes [ <NUM_LIT> ]


<s> static inline std :: array < MachineOperand , <NUM_LIT> > predOps ( <STR_LIT> Pred , unsigned PredReg = <NUM_LIT> ) { return { { MachineOperand :: CreateImm ( static_cast < int64_t > ( Pred ) ) , MachineOperand :: CreateReg ( PredReg , false


<s> return LT . first * <NUM_LIT> ; } if ( ST -> hasMVEFloatOps ( ) && isa < FixedVectorType > ( Src ) && I && ( ( Opcode == Instruction :: Load && I -> hasOneUse ( ) && isa < FPExtInst > ( * I -> user_begin ( ) ) ) || ( Opcode == Instruction :: Store && isa < FPTruncInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) ) { FixedVectorType * SrcVTy = cast < FixedVectorType > ( Src ) ; Type * DstTy = Opcode == Instruction :: Load ? ( * I -> user_begin ( ) ) -> getType ( ) : cast < Instruction > ( I -> getOperand ( <NUM_LIT> )

) -> getOperand ( <NUM_LIT> ) -> getType ( ) ;


<s> MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( OpNo ) . ChangeToRegister (


<s> unsigned <STR_LIT> ( <STR_LIT> CC ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 ,

DAG . getConstant ( <NUM_LIT> , VT ) ) ;


<s> Optional < std :: string > getOutliningStyle ( ) const { return OutliningStyle


<s> static SDValue getAbsolute ( SelectionDAG & DAG , const SDLoc & DL , SDValue Op , bool IsNegative ) { Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op ) ; if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType (


<s> else if ( TARGET_COFF || TARGET_PECOFF ) objfmt = <STR_LIT> ; if ( objfmt == NULL )


<s> unsigned <STR_LIT> ( SDNode * N ) { unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i


<s> LLVM_DEBUG ( LoadedCst -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << '\n' ) ; for ( auto Use : IPI . second ) { assert ( DT . dominates ( LoadedCst , findInsertionPoint ( * Use . first , Use . second ) ) && <STR_LIT> ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << Use . second << <STR_LIT> ; Use . first -> print ( dbgs ( )


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( auto & OrigArg : OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildExtract ( Regs , Offsets , OrigArg . Reg ) ; } ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * CallAssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . addOperand ( Callee ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned ,


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return Error ( L , <STR_LIT> ) ; MCSymbolELF * Sym = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; const MCExpr * Expr ; if ( parseToken ( AsmToken :: Comma ) || check ( getParser ( ) . parseExpression ( Expr ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ) ; TStreamer . emitLocalEntry ( Sym , Expr ) ; return false


<s> const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned DefReg = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( DefReg , RegBank ) ; if ( ! emitInsertSubreg ( DefReg , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I , MRI , MF ) ) return false ; for ( unsigned Idx = <NUM_LIT> ; Idx < I . getNumOperands ( ) ; ++ Idx ) { unsigned Tmp = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( Tmp ,


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 =


<s> if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( BracLoc , <STR_LIT> ) ; Parser . Lex ( ) ; SMLoc StartInBrac = Tok . getLoc ( ) ; IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; const MCExpr * Disp = nullptr ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: Create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: CreateAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM .


<s> const <ISA_LIT>_64GOT & <ISA_LIT>_64GNULDBackend :: getGOT ( ) const { assert ( m_pGOT !=


<s> static SDValue performFpToIntCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isVector ( ) || ! Op . getValueType ( ) . isSimple ( ) || Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; if ( FloatBits != <NUM_LIT> && FloatBits != <NUM_LIT> && ( FloatBits != <NUM_LIT> || ! Subtarget -> hasFullFP16 ( ) ) ) return SDValue ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> ) return SDValue ( ) ; if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue


<s> Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Hint


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , JITCodeEmitter & JCE ) { if ( Subtarget . is<ISA_LIT>64 (


<s> return TargetTriple . getOS ( ) == Triple


<s> return true ; case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) == <STR_LIT> ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return false ; } case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind


<s> else if ( Subtarget -> hasV8MMainlineOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isMClass ( ) && Subtarget -> hasDSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV8MBaselineOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV4TOps ( ) ) return <STR_LIT> ; else return


<s> Index = Index % Width ; if ( ScalarType -> isFloatingPointTy ( ) && Index == <NUM_LIT> ) return <NUM_LIT> ; } int RegisterFileMoveCost = <NUM_LIT> ; if ( Opcode == Instruction :: ExtractElement && ScalarType -> isPointerTy ( ) )


<s> static void mmix_target_asm_function_epilogue ( FILE * stream


<s> CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT VT = VA . getValVT ( ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( )

, VT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> static SDValue skipExtensionForVectorMULL ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return addRequiredExtensionForVectorMULL ( N -> getOperand ( <NUM_LIT> ) , DAG , N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , N -> getOpcode ( ) ) ; assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements


<s> InstructionCost <ISA_LIT>TTIImpl :: getGSScalarCost ( unsigned Opcode , Type * SrcVTy , bool VariableMask , Align Alignment , unsigned AddressSpace ) { unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnes ( VF ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; InstructionCost MaskUnpackCost = <NUM_LIT> ; if ( VariableMask ) { auto * MaskTy = FixedVectorType :: get ( Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , VF ) ; MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false


<s> } else return None ; unsigned ShVal = <STR_LIT> ( <STR_LIT> , ShiftAmt ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Immed ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ShVal )


<s> static rtx or1k_legitimize_address ( rtx x , rtx ,


<s> for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) if ( i != ( unsigned ) ( MemOpNo + <STR_LIT> ) && isIdenticalOp ( MI . getOperand ( i ) , MO ) ) return false ; if ( MI . getOperand ( MemOpNo + <STR_LIT> ) . isImm ( ) && ! isInt < <NUM_LIT> > (

MI . getOperand ( MemOpNo + <STR_LIT> ) . getImm ( ) + AddrDispShift ) ) return false ;


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( The<ISA_LIT>64Target


<s> bool isMemOffs16_32 ( ) const { return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size ||


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo ,


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done =


<s> static SDValue lowerV32I16Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 ,

Mask , Zeroable , Subtarget , DAG ) ) return ZExt ;


<s> assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! Aligned || ( imm & <NUM_LIT> ) == <NUM_LIT> ) ) { APInt LHSKnownZero , LHSKnownOne ; DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( imm , N . getValueType ( ) ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) && ( ! Aligned || ( Imm & <NUM_LIT> ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) && ( ! Aligned || ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short )


<s> flags = default_section_type_flags ( decl , name , reloc ) ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) flags |= SECTION_WRITE | SECTION_RELRO ; return flags


<s> case TYPE_LOAD_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - <NUM_LIT> ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_SRC ( parallel_element ( insn , <NUM_LIT> ) ) ; break ; case TYPE_STORE_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - <NUM_LIT> ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_DEST ( parallel_element ( insn , <NUM_LIT> ) ) ; break ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case


<s> const TargetRegisterInfo * TRI = BB -> getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ; if ( ! MI -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( MI , BB , TRI ) ) { copy0MBB -> addLiveIn ( <STR_LIT> ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; } sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; copy0MBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent (


<s> const char * getPassName ( ) const override { return


<s> } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { InFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetDsp (


<s> if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = <NUM_LIT> ; int ret2 = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) { if ( TREE_CODE ( field ) == FIELD_DECL


<s> Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag , <NUM_LIT> ) ; switch ( item . Type ) { case AttributeItemType ::


<s> CurrentSection = nullptr ; CachedEntries . clear ( )


<s> if ( CI -> getBitWidth ( ) > <NUM_LIT> ) return false ; int64_t ConstVal = CI -> getZExtValue ( ) ; return isUInt < <NUM_LIT> > ( ConstVal ) || ( isUInt < <NUM_LIT> > ( ConstVal >> <NUM_LIT> )


<s> unsigned Offset = <NUM_LIT> + TIdx * <NUM_LIT> ; MI -> getOperand ( <NUM_LIT> )


<s> const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( const BasicBlock * SuccBB : IB -> successors ( ) )

FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ SuccBB ] ) ;


<s> bool isAVX512RC ( ) const { return isImm ( )


<s> case <STR_LIT> :: <ISA_LIT>V5TEJ : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V5 ; case <STR_LIT> :: <ISA_LIT>V6 : case <STR_LIT> :: <ISA_LIT>V6K : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ; case <STR_LIT> :: <ISA_LIT>V7A : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ; case <STR_LIT> :: <ISA_LIT>V7S : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ; case <STR_LIT> :: <ISA_LIT>V7K : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ; case <STR_LIT> :: <ISA_LIT>V6M : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ; case <STR_LIT> :: <ISA_LIT>V7M : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ; case <STR_LIT> :: <ISA_LIT>V7EM : return MachO ::


<s> return ( poly128_t ) __builtin_neon_vreinterprettiv4si ( ( int32x4_t )


<s> unsigned Subo = ( size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Even = MRI . getSubReg ( Reg , Sube ) ; unsigned Odd = MRI . getSubReg ( Reg , Subo ) ; O << getRegisterName ( Even ) <<


<s> bool <ISA_LIT>SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; const MCExpr * TargetExpr = MCSymbolRefExpr :: create ( Target , MCSymbolRefExpr :: VariantKind :: VK_None , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TargetExpr ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> emitLabel ( Target ) ; if ( ! Subtarget -> isGP64bit ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } recordSled ( CurSled , MI


<s> if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , APInt :: getAllOnesValue ( N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( int ) imm & <NUM_LIT> , <STR_LIT> ) ; return


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getSIMDShift32OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> - ( MO . getImm ( ) |


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base . Reg = N ; return


<s> const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize


<s> bool isLegal ( RegDomain RD ) const { return is_contained ( LegalDstDomains , RD


<s> if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; continue ; } if ( MBB -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) return false ; RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , true ) ) ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) MI -> RemoveOperand ( i ) ; MachineInstrBuilder MIB ( MF , & * MI ) ; for ( int i = RegList . size ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) MIB . addOperand ( RegList [


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtps_pi32 ( __m128 __A ) { __v4sf temp , rounded ; __vector unsigned long long result ; temp = ( __v4sf ) vec_splat ( ( __vector long long ) __A , <NUM_LIT> ) ; rounded = vec_rint ( temp ) ; result = ( __vector unsigned long long )


<s> if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue Madd = DAG . getNode ( <STR_LIT> , DL , MAddVT , N0 , N1 ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL ,


<s> DEBUG ( errs ( ) << <STR_LIT> ; AM . dump ( ) ) ; switch ( N . getOpcode ( ) ) { default : break ; case <STR_LIT> : { uint64_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; AM . Disp += Val ; return false ; } case <STR_LIT> : if ( ! MatchWrapper ( N , AM ) ) return false ; break ; case <STR_LIT> : if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . BaseType = <ISA_LIT>ISelAddressMode :: FrameIndexBase ; AM . Base . FrameIndex = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; return false ; } break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; break ; } case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N


<s> break ; case MCK__35_24 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_3 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_32 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_4 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_48 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_6 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_64 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_8 : ExpectedVal = <NUM_LIT> ; break ; } if ( ! Op -> isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i ) ; if ( Idx >= <NUM_LIT> ) { if ( Idx < ( int


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>_32TargetMachine > X ( The<ISA_LIT>_32Target ) ; RegisterTargetMachine < <ISA_LIT>_64TargetMachine > Y ( The<ISA_LIT>_64Target ) ; RegisterAsmInfoFn A ( The<ISA_LIT>_32Target , createTargetAsmInfo ) ; RegisterAsmInfoFn B ( The<ISA_LIT>_64Target , createTargetAsmInfo )


<s> const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [ firstRegToSaveIndex ] , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , OffsetFromOrigArg + <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } AFI -> setArgRegsSaveSize ( ArgRegsSaveSize + AFI -> getArgRegsSaveSize ( ) ) ; if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; return FrameIndex ; } else { if ( ArgSize == <NUM_LIT> )


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , HOST_WIDE_INT offset


<s> Triple T ( MMI -> getModule ( ) -> getTargetTriple ( ) ) ; if ( T . isOSNaCl ( ) ) return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Mang , MMI


<s> static unsigned getPCRelReloc ( unsigned Kind ) { switch ( Kind ) { case FK_Data_2 : return ELF :: R_390_PC16 ; case FK_Data_4 : return ELF :: R_390_PC32 ; case FK_Data_8 : return ELF :: R_390_PC64 ; case <STR_LIT> : return ELF ::


<s> int _U_Qfge ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , <NUM_LIT>


<s> assert ( ! m_MultipartList . empty ( ) && <STR_LIT> ) ; return m_MultipartList [ <NUM_LIT> ] . m_LocalNum


<s> static int sh_pr_n_sets ( void ) { return REG_N_SETS ( TARGET_SHMEDIA ? PR_MEDIA_REG


, ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> } } return false ; } switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrAlign . value ( ) , PtrAlign ) ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; const unsigned Offset = State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , Align ( <NUM_LIT> ) ) ; unsigned FReg = State . AllocateReg ( FPR ) ; if ( FReg ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , FReg , LocVT , LocInfo ) ) ; for ( unsigned I = <NUM_LIT> ; I < StoreSize ; I += PtrAlign


<s> if ( LoImmOp64 == <NUM_LIT> ) { if ( isABI_N32 ( ) || isABI_N64 ( ) ) { if ( loadImmediate ( HiImmOp64 , FirstReg , <STR_LIT> , false , true , IDLoc , Out , STI ) ) return true ; } else { if ( loadImmediate ( HiImmOp64 , FirstReg , <STR_LIT> , true , true , IDLoc , Out , STI ) ) return true ; if ( loadImmediate ( <NUM_LIT> , nextReg ( FirstReg ) , <STR_LIT> , true , true , IDLoc , Out , STI ) ) return true ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitIntValue ( HiImmOp64 , <NUM_LIT> ) ; getStreamer ( ) . EmitIntValue ( LoImmOp64 , <NUM_LIT> ) ; getStreamer ( ) . SwitchSection ( CS ) ; if ( emitPartialAddress ( TOut , IDLoc , Sym ) ) return true ; if ( isABI_N64 ( ) ) TOut . emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; else TOut . emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; if ( isABI_N32 ( ) || isABI_N64 ( ) ) TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> , IDLoc , STI ) ; else { TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg


<s> ExceptionsType = ExceptionHandling :: WinEH


<s> return ( __m512i ) __builtin_ia32_cvttpd2uqq512_mask ( ( __v8df ) __A , ( __v8di ) _mm512_setzero_si512 ( )

, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> uint64_t FrameSize = StackSize - SlotSize ; if ( needsStackRealignment ( MF ) ) FrameSize = ( FrameSize + MaxAlign - <NUM_LIT> ) / MaxAlign * MaxAlign ; NumBytes = FrameSize - CSSize ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , FramePtr ) ; } else { NumBytes = StackSize - CSSize ; } MachineBasicBlock :: iterator LastCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> getDesc ( ) . isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( needsStackRealignment ( MF ) ) { if ( CSSize ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; MBBI = prior ( LastCSPop ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else { if ( NumBytes ) emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end (


<s> int reg_parm_stack_space = REG_PARM_STACK_SPACE ( NULL_TREE ) ; rtx arg_bytes , begin_label_rtx , mcount , sym ; rtx_insn * call_insn ; char begin_label_name [ <NUM_LIT> ] ; bool use_mcount_pcrel_call ; sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pa_encode_label ( sym ) ; mcount = gen_rtx_MEM ( Pmode , sym ) ; if ( ! TARGET_PORTABLE_RUNTIME && ! TARGET_LONG_CALLS && ( TARGET_SOM || flag_function_sections ) ) use_mcount_pcrel_call = TRUE ; else use_mcount_pcrel_call = FALSE ; ASM_GENERATE_INTERNAL_LABEL ( begin_label_name , FUNC_BEGIN_PROLOG_LABEL , label_no ) ; begin_label_rtx = gen_rtx_SYMBOL_REF ( SImode , ggc_strdup ( begin_label_name ) ) ; emit_move_insn ( gen_rtx_REG ( word_mode , <NUM_LIT> ) , gen_rtx_REG ( word_mode , <NUM_LIT> ) ) ; if ( ! use_mcount_pcrel_call ) { if ( TARGET_PA_20 ) emit_insn ( gen_lcla2 ( gen_rtx_REG ( SImode , <NUM_LIT> ) , label_rtx ) ) ; else emit_insn ( gen_lcla1 ( gen_rtx_REG ( SImode , <NUM_LIT> ) , label_rtx ) ) ; } if ( ! NO_DEFERRED_PROFILE_COUNTERS ) { rtx count_label_rtx , addr , r24 ; char count_label_name [ <NUM_LIT> ] ; funcdef_nos . safe_push ( label_no ) ; ASM_GENERATE_INTERNAL_LABEL ( count_label_name , <STR_LIT> , label_no ) ; count_label_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( count_label_name ) ) ; addr = force_reg ( Pmode , count_label_rtx ) ; r24 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r24 , addr ) ; arg_bytes = GEN_INT ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( use_mcount_pcrel_call ) call_insn = emit_call_insn ( gen_call_mcount ( mcount , arg_bytes , begin_label_rtx ) ) ; else call_insn = emit_call_insn ( gen_call ( mcount , arg_bytes ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , r24 ) ; } else { arg_bytes = GEN_INT ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( use_mcount_pcrel_call ) call_insn = emit_call_insn ( gen_call_mcount (


<s> } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [ j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ; } if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Op . getOpcode ( ) ) ) return DAG . getNode ( <ISA_LIT>OpcV , dl , VT , R , Op


<s> StoreSDNode * SD = cast < StoreSDNode > ( Op ) ; EVT MemVT = SD -> getMemoryVT ( ) ; const SDValue Val = SD -> getValue ( ) ; if ( Subtarget . isCheri ( ) && SD -> isTruncatingStore ( ) && Val . getValueType ( ) == <STR_LIT> ) { SDValue Chain = SD -> getChain ( ) ; SDValue BasePtr = SD ->


<s> setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> is<ISA_LIT>32r2 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; OW -> WriteZeros ( Count % <NUM_LIT> ) ; return


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv2di ( (


<s> bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ; return new ELF<ISA_LIT>AsmBackend ( T ,


<s> Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result , DAG . getConstant ( Offset , getPointerTy ( ) ) ) ; return Result


<s> State = IES_ERROR ; break ; case IES_PLUS : case IES_LPAREN : State = IES_REGISTER ; TmpReg = Reg ; IC . pushOperand ( IC_REGISTER ) ; break ; case IES_MULTIPLY : if ( PrevState == IES_INTEGER ) { assert ( ! IndexReg && <STR_LIT> ) ; State = IES_REGISTER ; IndexReg = Reg ; Scale = IC . popOperand ( ) ; IC . pushOperand ( IC_IMM ) ; IC . popOperator ( ) ; } else { State = IES_ERROR


<s> if ( MI . readsRegister ( MisspeculatingTaintReg , TRI ) || MI . modifiesRegister ( MisspeculatingTaintReg , TRI ) ) return true ; } } return


<s> static reg_class_t aarch64_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t rclass , machine_mode mode , secondary_reload_info * sri ) { if ( BYTES_BIG_ENDIAN && reg_class_subset_p ( rclass , FP_REGS ) && ! ( ( REG_P ( x ) && HARD_REGISTER_P ( x ) ) || aarch64_simd_valid_immediate ( x , NULL ) ) && aarch64_sve_data_mode_p ( mode ) ) { sri -> icode = CODE_FOR_aarch64_sve_reload_be ; return NO_REGS ; } if ( MEM_P ( x ) && GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ( SCALAR_FLOAT_MODE_P ( GET_MODE ( x ) ) ||

targetm . vector_mode_supported_p ( GET_MODE ( x ) ) ) && ! aarch64_pcrelative_literal_loads ) {


<s> Register ( ) { <ISA_LIT>TargetMachine :: registerAsmPrinter (


<s> bool <ISA_LIT>DAGToDAGISel :: matchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { SDLoc dl ( N


<s> <ISA_LIT>TLSDynamicCall ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>TLSDynamicCallPass ( * PassRegistry ::


<s> return ( __m128i ) __builtin_ia32_psrav4si_mask ( ( __v4si ) __X , ( __v4si ) __Y , ( __v4si ) _mm_setzero_si128 ( ) ,


<s> return __builtin_mve_vldrwq_sv4si ( ( __builtin_neon_si *


<s> if ( ST -> hasSSE41 ( ) ) { int Idx = CostTableLookup ( SSE41AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE41AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSSE3AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSSE3 ( ) ) { int Idx = CostTableLookup ( SSSE3AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSSE3AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSEAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; int Idx = CostTableLookup ( SSEAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSEAltShuffleTbl [ Idx ] . Cost ; return TargetTransformInfo :: getShuffleCost ( Kind , Tp


<s> static Target The<ISA_LIT>Target ; return


<s> else gcc_assert ( <NUM_LIT> ) ; emit_move_insn ( target , const0_rtx ) ; label1 = gen_label_rtx ( ) ; label2 = gen_label_rtx ( ) ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( GE , CCDSPmode , cmp_result , GEN_INT ( cmp_value ) ) , gen_rtx_LABEL_REF ( VOIDmode , label1 ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , label2 ) ) ) ; emit_barrier ( ) ; emit_label ( label1 ) ; emit_move_insn ( target , const1_rtx ) ; emit_label ( label2 ) ; return


<s> } else { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( Size == <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst ,


<s> Offset = <NUM_LIT> ; MachineBasicBlock & MBB = * MBBI -> getParent ( ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( MBBI == BeginMBBI ) return EndMBBI ; MachineBasicBlock :: iterator PrevMBBI = std ::


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { assert ( <NUM_LIT>


<s> Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg (


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return


<s> int VecSize = VT . getSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; int Len = EltVT . getSizeInBits ( ) ; auto GetShift = [ & ] ( unsigned OpCode , SDValue V , int Shifter ) { MVT VT = V . getSimpleValueType ( ) ; SDValue ShifterV = DAG . getConstant ( Shifter , DL , VT ) ; return DAG . getNode ( OpCode , DL , VT , V , ShifterV ) ; } ; auto GetMask = [ & ] ( SDValue V , APInt Mask ) { MVT VT = V . getSimpleValueType ( ) ; SDValue MaskV = DAG . getConstant ( Mask , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V , MaskV ) ; } ; MVT SrlVT = Len > <NUM_LIT> ? VT : <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; SDValue V = Op ; SDValue Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast ( SrlVT , V ) , <NUM_LIT> ) ) ; SDValue And = GetMask ( Srl , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; V = DAG . getNode ( <STR_LIT> , DL , VT , V , And ) ; SDValue AndLHS = GetMask ( V , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast ( SrlVT , V ) , <NUM_LIT> ) ) ; SDValue AndRHS = GetMask ( Srl , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; V = DAG . getNode ( <STR_LIT> , DL , VT , AndLHS , AndRHS ) ; Srl = DAG . getBitcast ( VT , GetShift ( <STR_LIT> , DAG . getBitcast ( SrlVT , V ) , <NUM_LIT> ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , V , Srl ) ; V = GetMask ( Add , APInt :: getSplat ( Len , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; if ( EltVT == <STR_LIT> ) return


<s> else Index = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Alignment , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . MCSym ) { assert ( ! AM . Disp && <STR_LIT> ) ; assert ( AM . SymbolFlags ==


<s> assert ( AddrOffset != - <NUM_LIT> && <STR_LIT> ) ; AddrOffset += <STR_LIT> ( Descl ) ; return


<s> new_off_3 = off_val_3 - base_off ; if ( new_off_1 > stp_off_upper_limit || new_off_1 < stp_off_lower_limit || new_off_3 > stp_off_upper_limit || new_off_3 < stp_off_lower_limit ) return false ; replace_equiv_address_nv ( mem_1 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_1 ) , true ) ; replace_equiv_address_nv ( mem_2 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_1 + msize ) , true ) ; replace_equiv_address_nv ( mem_3 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_3 ) , true ) ; replace_equiv_address_nv ( mem_4 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_3 + msize ) , true ) ; if ( ! aarch64_mem_pair_operand ( mem_1 , mode ) || ! aarch64_mem_pair_operand ( mem_3 , mode ) ) return false ; if ( code == ZERO_EXTEND ) { mem_1 = gen_rtx_ZERO_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_ZERO_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_ZERO_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_ZERO_EXTEND ( DImode , mem_4 ) ; } else if ( code == SIGN_EXTEND ) { mem_1 = gen_rtx_SIGN_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_SIGN_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_SIGN_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_SIGN_EXTEND ( DImode , mem_4 ) ; } if ( load ) { operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_4 ; } else { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_4 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; } emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , plus_constant ( DImode , base , base_off ) ) ) ; t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; t2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , t1 , t2 ) ) ) ; t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; t2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> ,


<s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( create<ISA_LIT>AtomicExpandPass ( & get<ISA_LIT>TargetMachine ( )


<s> if ( ! new_tree && old_tree ) new_tree = target_option_default_node ; if ( old_tree == new_tree ) return ; aarch64_previous_fndecl = fndecl ; cl_target_option_restore ( & global_options , & global_options_set ,


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Def = MRI -> getUniqueVRegDef ( AmountReg ) ; while ( Def && Def -> isCopy ( ) && Def -> getOperand ( <NUM_LIT> ) . isReg ( ) ) Def = MRI ->

getUniqueVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> << ShImm ; O << <STR_LIT>


<s> if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) && <STR_LIT>


<s> return NO_REGS ; } if ( mode == QImode && ( ( ! TARGET_64BIT && ! in_p && INTEGER_CLASS_P ( rclass ) && MAYBE_NON_Q_CLASS_P ( rclass ) ) || ( ! TARGET_AVX512DQ && MAYBE_MASK_CLASS_P ( rclass ) ) ) ) { int regno = true_regnum ( x ) ; if ( regno == - <NUM_LIT> ) return Q_REGS ; return NO_REGS ; } if ( ( mode == HFmode || mode == HImode || mode == V2QImode || mode == BFmode ) && ! TARGET_SSE4_1 && SSE_CLASS_P ( rclass ) && ! in_p && MEM_P ( x ) ) { sri -> extra_cost = <NUM_LIT> ; return


<s> if ( PR_REGNUM_P ( regno ) ) return <NUM_LIT> ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return true ; if ( FP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_STRUCT ) return end_hard_regno ( mode , regno ) - <NUM_LIT> <= V31_REGNUM ; else return ! VECTOR_MODE_P ( mode


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { const APInt & XorC = Op1 . getConstantOperandAPInt ( <NUM_LIT> ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand (

<NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ;


<s> } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB


<s> if ( ! isExpandISELEnabled ( MF ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; initialize ( MF ) ; if ( ! collectISELInstructions ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DumpISELInstructions ( ) ; expandAndMergeISELs ( ) ; return true


<s> } BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef (

<STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; return Imm .


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister (


<s> Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasInt256 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasBWI ( ) ) ) { if ( matchVectorShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchVectorShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> ==

EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ;


<s> return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ||

MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) ;


<s> AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error (


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( ! printAliasInstr ( MI , STI , OS ) ) printInstruction ( MI ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> : emitMOVi2piecesInstruction ( MI ) ; break ; case <STR_LIT> : emitLEApcrelJTInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT>


uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> return <NUM_LIT> - MI . getOperand (


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta , true ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ; const TargetFrameInfo & TFI = * MF . getTarget


<s> int src_regno = regno_or_subregno ( src ) ; int element_regno = regno_or_subregno ( element ) ; gcc_assert ( REG_P ( tmp_gpr ) ) ; if ( TARGET_P9_VECTOR && ( mode == V16QImode || mode == V8HImode || mode == V4SImode ) && INT_REGNO_P ( dest_regno ) && ALTIVEC_REGNO_P ( src_regno ) && INT_REGNO_P ( element_regno ) ) { rtx dest_si = gen_rtx_REG ( SImode , dest_regno ) ; rtx element_si = gen_rtx_REG ( SImode , element_regno ) ; if ( mode == V16QImode ) emit_insn ( VECTOR_ELT_ORDER_BIG ? gen_vextublx ( dest_si , element_si , src ) : gen_vextubrx ( dest_si , element_si , src ) ) ; else if ( mode == V8HImode ) { rtx tmp_gpr_si = gen_rtx_REG ( SImode , REGNO ( tmp_gpr ) ) ; emit_insn ( gen_ashlsi3 ( tmp_gpr_si , element_si , const1_rtx ) ) ; emit_insn ( VECTOR_ELT_ORDER_BIG ? gen_vextuhlx ( dest_si , tmp_gpr_si , src ) : gen_vextuhrx ( dest_si , tmp_gpr_si , src ) ) ; } else { rtx tmp_gpr_si = gen_rtx_REG ( SImode , REGNO ( tmp_gpr ) ) ; emit_insn ( gen_ashlsi3 ( tmp_gpr_si , element_si , const2_rtx ) ) ; emit_insn ( VECTOR_ELT_ORDER_BIG ? gen_vextuwlx ( dest_si , tmp_gpr_si , src ) : gen_vextuwrx ( dest_si , tmp_gpr_si , src ) ) ; } return ; } gcc_assert ( REG_P ( tmp_altivec ) ) ; if ( scalar_size == <NUM_LIT> ) { if ( ! VECTOR_ELT_ORDER_BIG ) { emit_insn ( gen_xordi3 ( tmp_gpr , element , const1_rtx ) ) ; element2 = tmp_gpr ; } else element2 = element ; emit_insn ( gen_rtx_SET ( tmp_gpr , gen_rtx_AND ( DImode , gen_rtx_ASHIFT ( DImode , element2 , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { if ( ! VECTOR_ELT_ORDER_BIG ) { rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( mode ) - <NUM_LIT> ) ; emit_insn ( gen_anddi3 ( tmp_gpr , element , num_ele_m1 ) ) ; emit_insn ( gen_subdi3 ( tmp_gpr , num_ele_m1 , tmp_gpr ) ) ; element2 = tmp_gpr ; } else element2 = element ; emit_insn ( gen_ashldi3 ( tmp_gpr , element2 , GEN_INT ( bit_shift ) ) ) ; } if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_splat_v2di ( tmp_altivec , tmp_gpr ) ) ; else if ( can_create_pseudo_p ( ) ) emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_gpr , tmp_gpr ) ) ; else { rtx tmp_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; emit_move_insn ( tmp_di , tmp_gpr ) ; emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_di , tmp_di ) ) ; } switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_vslo_v2df ( dest , src , tmp_altivec ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_vslo_v2di ( dest , src , tmp_altivec ) ) ; return ; case E_V4SFmode : { rtx tmp_altivec_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; rtx tmp_altivec_v4sf = gen_rtx_REG ( V4SFmode , REGNO ( tmp_altivec ) ) ; rtx src_v2di = gen_rtx_REG ( V2DImode ,


<s> MIB -> eraseFromParent ( ) ; return true ; } auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! validOpRegPair ( MRI , LHSReg , RHSReg , Helper . OperandSize , Helper . OperandRegBankID ) ) return false ; auto <ISA_LIT>Conds = getComparePreds ( Cond ) ; auto ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; putConstant ( I , ZeroReg , <NUM_LIT> ) ; if ( <ISA_LIT>Conds . second == <STR_LIT> ) { if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; } else { auto IntermediateRes = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! insertComparison ( Helper , I , IntermediateRes , <ISA_LIT>Conds . first , LHSReg , RHSReg , ZeroReg ) ) return false ; if ( ! insertComparison ( Helper , I , ResReg , <ISA_LIT>Conds . second , LHSReg , RHSReg , IntermediateRes ) ) return false ; } MIB -> eraseFromParent (


<s> } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; OpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , OpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return true ; } unsigned CmpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CmpReg == <NUM_LIT> ) return false ; unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CmpReg = constrainOperandRegClass ( TII . get ( TstOpc ) ,


<s> return isInt32Immediate ( N . getNode


<s> if ( RelocM == Reloc :: PIC_ || RelocM == Reloc :: DynamicNoPIC ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getConstTextCoalSection ( ) ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO ::

S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ;


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode (


<s> Ops . push_back ( PredicateMask ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( Inactive


<s> return <STR_LIT> == Reg || Reg == <STR_LIT> ||


<s> AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > (


<s> return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( )


<s> getTargetStreamer ( ) . emitARM64WinCFIEpilogEnd


<s> bool isConstantUImm ( ) const { return isConstantImm ( ) && isUInt < Bits > ( getConstantImm ( ) -


<s> static int loongarch_set_reg_reg_piece_cost ( machine_mode mode


<s> MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid (