<s> if ( CalleeMO . isImm ( ) ) { uint64_t CallTarget = CalleeMO . getImm ( ) ; if ( CallTarget ) { unsigned ScratchIdx = - <NUM_LIT> ; unsigned ScratchReg = <NUM_LIT> ; do { ScratchIdx = Opers . getNextScratchIdx ( ScratchIdx + <NUM_LIT> ) ; ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; } while ( ScratchReg == <STR_LIT> ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; EncodedBytes += <NUM_LIT> ; if ( CallTarget >> <NUM_LIT> ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( CallTarget >> <NUM_LIT> ) ) ; EncodedBytes += <NUM_LIT> ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; EncodedBytes += <NUM_LIT> ; } } else if ( CalleeMO . isGlobal ( ) ) { const MCExpr * Expr = Lower . getExpr ( CalleeMO , MCSymbolRefExpr :: VK_PLT ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( Expr ) ) ; EncodedBytes += <NUM_LIT> ; } unsigned NumBytes = Opers . getNumPatchBytes


<s> return __builtin_ia32_comisdeq ( ( __v2df ) __A , ( __v2df )


<s> if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS ,


<s> return ( uint64x1_t ) __builtin_neon_vcreatedi ( (


<s> __m128 a , b , c ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; b = vec_splat ( __B , <NUM_LIT> ) ; c = a + b ; return ( vec_sel ( __A , c , mask ) ) ; __A [ <NUM_LIT> ] = __A [ <NUM_LIT> ] + __B [ <NUM_LIT>


<s> static bool or1k_frame_pointer_required ( ) { return ( crtl -> accesses_prior_frames


<s> BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> addSuccessor ( DestBB ) ; std :: next ( MBB -> getIterator ( ) ) -> removeSuccessor ( DestBB ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> getInstSizeInBytes ( * MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ; return


<s> if ( Reached . find ( MI ) != Reached . end ( ) ) continue ; Reached . insert ( MI ) ; if ( MI -> isPHI ( ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { unsigned Reg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( Reg


<s> Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = FixedVectorType :: get ( SubVecTy -> getElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { unsigned IdxJ = StoreCount * LaneLen * Factor + j ; if ( Mask [ IdxJ * Factor + IdxI ] >= <NUM_LIT> ) { StartMask = Mask [ IdxJ * Factor + IdxI ] - IdxJ ; break ; } } Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( StartMask , LaneLen ,


<s> bool IsLegal = false ; const APInt ImmInt = Imm . bitcastToAPInt ( ) ; if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; else if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; if ( ! IsLegal && ( VT == <STR_LIT> || VT


<s> unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back (


<s> static DecodeStatus decodeU4ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Target = N -> getOperand ( <NUM_LIT> ) ; EVT CompareTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDVTList CompareVT = CurDAG ->


<s> static void mips_push_asm_switch_1 ( struct mips_asm_switch * asm_switch , const char * prefix , const char *


<s> int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = Ext == <STR_LIT> ; MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg ( ) ) ) ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg (


<s> if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N ,


<s> bool hasSHSTK ( ) const { return HasSHSTK


<s> const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame . getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) { if ( MFFrame . getStackSize ( ) > <NUM_LIT> * sizeof ( long ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( HasFP ) { report_fatal_error ( <STR_LIT> ) ; } MFFrame . setStackSize ( MFFrame . getStackSize ( ) + <STR_LIT> ) ; return ; } DebugLoc DL ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getSpillGPRRegs ( ) . LowGPR ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int FI = Save . getFrameIdx ( ) ; int64_t Offset = MFFrame . getObjectOffset ( FI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = MFFrame . getStackSize ( ) ; bool HasStackObject = false ; for ( unsigned i = <NUM_LIT> , e = MFFrame . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( ! MFFrame . isDeadObjectIndex ( i ) ) { HasStackObject = true ; break ; } if ( HasStackObject || MFFrame . hasCalls ( ) ) StackSize += <STR_LIT> ; StackSize = StackSize > <STR_LIT> ? StackSize - <STR_LIT> : <NUM_LIT> ; MFFrame . setStackSize ( StackSize ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr


<s> emit_insn ( gen_avx2_permv4di_1 ( op , gen_lowpart ( V4DImode , h [ i ] ) , const2_rtx , GEN_INT ( <NUM_LIT> ) , const0_rtx , const1_rtx ) ) ; h [ i ] = gen_lowpart ( V32QImode , op ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! used [ <NUM_LIT> * i ] ) { l [ i ] = NULL_RTX ; continue ; } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> * i ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l [ i ] = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , i ? d -> op1 : d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( l [ i ] , op , vperm ) ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( h [ i ] && l [ i ] ) { op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l [ i ] , h [ i ] ) ) ; l [ i ] = op ; } else if ( h [ i ] ) l [ i ] = h [ i ] ; } gcc_assert ( l [ <NUM_LIT> ] && l [ <NUM_LIT> ] ) ; op = d -> target ; if ( d -> vmode != V32QImode ) op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l [ <NUM_LIT> ] , l [ <NUM_LIT> ] ) ) ; if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options ) , STI ( sti ) , MII ( mii ) , InstInfo ( nullptr ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; Instrumentation . reset ( Create<ISA_LIT>AsmInstrumentation ( Options , Parser .


<s> else * total = <NUM_LIT> ; return true ; case SYMBOL_REF : * total = optimize_size ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : * total = ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ) ; return


<s> if ( TARGET_ABI_OPEN_VMS && arg . end_marker_p ( ) ) { unsigned HOST_WIDE_INT regval = cum -> words ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) regval |= ( ( int ) cum -> atypes [ i ] ) << ( i * <NUM_LIT> + <NUM_LIT> ) ; emit_move_insn ( gen_rtx_REG ( DImode , GR_REG ( <NUM_LIT> ) ) , GEN_INT ( regval ) ) ; } if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return <NUM_LIT> ; if ( TARGET_ABI_OPEN_VMS ) { if ( FLOAT_MODE_P ( arg . mode ) ) return gen_rtx_REG ( arg . mode , FR_ARG_FIRST + cum -> words ) ; else return gen_rtx_REG ( arg . mode , basereg + cum -> words ) ; } if ( arg . type ) hfa_mode = hfa_element_mode ( arg . type , <NUM_LIT> ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || arg . named ) ) { rtx loc [ <NUM_LIT> ] ; int i = <NUM_LIT> ; int fp_regs = cum -> fp_regs ; int int_regs = cum -> words + offset ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = arg . promoted_size_in_bytes ( ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = <NUM_LIT> ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD )


<s> std :: unique_ptr < MCSubtargetInfo > STI ( TM . getTarget ( ) . createMCSubtargetInfo ( TT . str ( ) , <STR_LIT> , <STR_LIT> ) ) ; MCSymbol * HwasanTagMismatchV1Sym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MCSymbol * HwasanTagMismatchV2Sym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; const MCSymbolRefExpr * HwasanTagMismatchV1Ref = MCSymbolRefExpr :: create ( HwasanTagMismatchV1Sym , OutContext ) ; const MCSymbolRefExpr * HwasanTagMismatchV2Ref = MCSymbolRefExpr :: create ( HwasanTagMismatchV2Sym , OutContext ) ; for ( auto & P : HwasanMemaccessSymbols ) { unsigned Reg = std :: get < <NUM_LIT> > ( P . first ) ; bool IsShort = std :: get < <NUM_LIT> > ( P . first ) ; uint32_t AccessInfo = std :: get < <NUM_LIT> > ( P . first ) ; const MCSymbolRefExpr * HwasanTagMismatchRef = IsShort ? HwasanTagMismatchV2Ref : HwasanTagMismatchV1Ref ; MCSymbol * Sym = P . second ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_GROUP , <NUM_LIT> , Sym -> getName ( ) ) ) ; OutStreamer -> emitSymbolAttribute ( Sym , MCSA_ELF_TypeFunction ) ; OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Weak ) ; OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Hidden ) ; OutStreamer -> emitLabel ( Sym ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) , * STI ) ; MCSymbol * HandleMismatchOrPartialSym = OutContext . createTempSymbol ( ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( HandleMismatchOrPartialSym , OutContext ) ) , * STI ) ; MCSymbol * ReturnSym = OutContext


<s> inline vector float vec_floor ( vector


<s> const MCSymbol * <ISA_LIT>ObjectWriter :: ExplicitRelSym ( const MCAssembler & Asm , const MCValue & Target , const MCFragment & F , const MCFixup & Fixup , bool IsPCRel ) const { if ( ! Target . isAbsolute ( ) && Target . getSymA ( ) -> getKind ( ) != MCSymbolRefExpr :: VK_None && IsPCRel ) return & Target . getSymA ( ) -> getSymbol ( ) . AliasedSymbol ( ) ; return


<s> vst4_s16 ( int16_t * __a , int16x4x4_t val ) { __builtin_aarch64_simd_xi __o ; int16x8x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4v4hi ( ( __builtin_aarch64_simd_hi * ) __a


<s> case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true ; case MachineOperand ::


<s> emit_insn ( gen_vsx_sign_extend_qi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrhx ) { temp1 = simplify_gen_subreg ( V8HImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_hi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrwx ) { temp1 = simplify_gen_subreg ( V4SImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_si_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = simplify_gen_subreg ( V2DImode , tiscratch , TImode , <NUM_LIT> ) ; else gcc_unreachable ( ) ; rtx temp2 = simplify_gen_subreg ( TImode , discratch , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_extendditi2_vector ( target


<s> bool isCtlzFast ( ) const override { return


<s> void addImm0_127Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Tok = Parser . getTok ( ) . getIdentifier ( ) ; if ( Tok [ <NUM_LIT> ] != 'c' && Tok [ <NUM_LIT> ] != 'C' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return


<s> format = end ; if ( bits == <NUM_LIT> || bits == <NUM_LIT> ) bits = instance . type_suffix ( bits ) . element_bits ; return find_type_suffix ( tclass , bits ) ; } if ( ch == 'w' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; if ( type_suffixes [ suffix ] . integer_p ) return find_type_suffix ( type_suffixes [ suffix ] . tclass , <NUM_LIT> ) ; return suffix ; } if ( ch == 'p' ) return TYPE_SUFFIX_b ; if ( ch == 'B' ) return TYPE_SUFFIX_bf16 ; if ( ch == 'q' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix


<s> static tree rs6000_builtin_mask_for_load ( void


<s> <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return TargetAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( )


<s> if ( ! CONST_INT_P ( op ) ) return false ; val = INTVAL ( op ) ; return ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT>


<s> void <ISA_LIT>SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs ,


<s> if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false ,


<s> static MachineInstr :: const_mop_iterator getStackMapEndMOP ( MachineInstr :: const_mop_iterator MOI , MachineInstr :: const_mop_iterator MOE ) { for ( ; MOI != MOE ; ++ MOI ) if ( MOI -> isRegMask ( ) || ( MOI -> isReg ( ) && MOI -> isImplicit ( ) ) ) break ; return MOI


<s> static SDValue lowerVECTOR_SHUFFLE_PCKOD ( SDValue Op , EVT ResTy , SmallVector < int , <NUM_LIT> > Indices , SelectionDAG & DAG ) { assert ( ( Indices . size ( ) % <NUM_LIT> ) == <NUM_LIT> ) ; int Idx


<s> LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( LdarOp ) , Dest . getReg ( ) ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CmpOp ) , ZeroReg ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addOperand ( Desired ) . addImm ( ExtendImm ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; BuildMI ( StoreBB , DL , TII -> get ( StlrOp ) , StatusReg ) . addOperand ( New ) . addOperand ( Addr ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , RegState :: Kill ) . addMBB ( LoadCmpBB ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end (


<s> state -> insns_left = state -> issue_rate ; memset ( & state -> last_set , <NUM_LIT> , sizeof ( state -> last_set ) ) ; state_reset ( state -> dfa_state


<s> TargetRegistry :: RegisterMCAsmInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) ,


<s> if ( GET_CODE ( pat ) == SET && REG_P ( XEXP ( pat , <NUM_LIT> ) ) && REGNO ( XEXP ( pat , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && CONST_INT_P ( XEXP ( pat , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( pat , <NUM_LIT> ) ) == <NUM_LIT> || INTVAL ( XEXP

( pat , <NUM_LIT> ) ) == STORE_FLAG_VALUE ) ) return XEXP ( pat , <NUM_LIT> ) ;


<s> unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ScrReg ) . addReg ( SrcReg ) . addImm ( ShiftImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( ScrReg


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> AM . Scale = <NUM_LIT> ; } } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == <NUM_LIT> && AM . IndexReg . getNode ( ) == <NUM_LIT> && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> return ( __m256i ) __builtin_ia32_pmovwb512_mask ( ( __v32hi ) __A ,


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X =


<s> if ( DeadNZCVIdx != - <NUM_LIT> ) { if ( CmpInstr . definesRegister ( <STR_LIT> ) || CmpInstr . definesRegister ( <STR_LIT> ) ) { CmpInstr . eraseFromParent ( ) ; return true ; } unsigned Opc = CmpInstr . getOpcode ( ) ; unsigned NewOpc = convertFlagSettingOpcode ( CmpInstr ) ; if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr . setDesc ( MCID ) ; CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr


<s> } save_restore_insns ( <NUM_LIT> ) ; if ( crtl -> calls_eh_return ) { rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != <NUM_LIT> || crtl -> calls_eh_return ) { emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } } if ( crtl -> calls_eh_return ) { emit_move_insn ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) , stack_pointer_rtx ) ; emit_use ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ) ; emit_jump_insn ( gen_eh_return_internal


<s> Inst . addOperand ( MCOperand :: CreateImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemIndexReg ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateMCValue


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( getMemDisp ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( getMemSegReg ( ) )


<s> __v2df result = ( __v2df ) __A ; result [ <NUM_LIT> ] = * __B ; return ( __m128d


<s> static bool isIncomingOfPHI ( Instruction * I ) { for ( Use & U : I ->


<s> unsigned Opc = is64Bit ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( Opc ) , Reg ) ; } return


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) )


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitBPOSGE32 ( MachineInstr * MI , MachineBasicBlock *


<s> int mask = <NUM_LIT> ; if ( ( mflag_sched_br_data_spec && ! reload_completed && optimize > <NUM_LIT> ) || ( mflag_sched_ar_data_spec && reload_completed ) ) { mask |= BEGIN_DATA ; if ( ! sel_sched_p ( ) && ( ( mflag_sched_br_in_data_spec && ! reload_completed ) || ( mflag_sched_ar_in_data_spec && reload_completed ) ) ) mask |= BE_IN_DATA ; } if ( mflag_sched_control_spec && ( ! sel_sched_p ( ) || reload_completed ) ) { mask |= BEGIN_CONTROL ; if ( ! sel_sched_p ( ) &&

mflag_sched_in_control_spec ) mask |= BE_IN_CONTROL ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; bool IsMinSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; if ( IsMinSize ) return SDValue ( ) ; SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ; if ( ReplacedSplat != SDValue ( ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S ->


<s> if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> ( llvm


<s> uint64_t <ISA_LIT>FrameLowering :: getFramePointerSaveOffset (


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI -> getOperand (


<s> int nreg = CEIL ( GET_MODE_SIZE ( arg . mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= <NUM_LIT> ) ; if ( arg . named ) * cum


<s> if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return


<s> unsigned ElemBytes = VT . getVectorElementType ( ) . getStoreSize ( ) ; if ( ElemBytes <= <NUM_LIT> ) { Opcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EVT InVT = VT . changeVectorElementTypeToInteger ( ) ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( ElemBytes * <NUM_LIT> ) , <STR_LIT> / ElemBytes / <NUM_LIT> ) ; if ( VT != InVT ) { Op1 = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , InVT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; } SDValue Op = DAG . getNode ( Opcode , SDLoc ( N ) , OutVT , Op1 ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT ,


<s> Inst . addOperand ( MCOperand :: CreateReg ( FRegs [ getReg ( ) ]


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) , DAG . getBitcast ( <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ) ) ; } if ( SDValue Cmp = foldVectorXorShiftIntoCmp ( N , DAG , Subtarget ) ) return Cmp ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue SetCC = foldXor1SetCC ( N , DAG ) ) return SetCC ; if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG )


<s> const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: Fast , RetTy , Callee ,


<s> isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB


<s> MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else


<s> if ( ! RLL || ! isShift ( RLL , <STR_LIT> , <NUM_LIT> ) ) return false ; MachineInstr * SRL = getDef ( RLL -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! SRL || ! isShift ( SRL , <STR_LIT> , <STR_LIT> ) ) return false ; MachineInstr * IPM = getDef ( SRL -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! IPM || IPM -> getOpcode ( ) != <STR_LIT> ) return false ; if ( IPM -> getParent ( ) != Compare . getParent ( ) ) return false ; MachineBasicBlock :: iterator MBBI = IPM , MBBE = Compare . getIterator ( ) ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return false ; } Compare . eraseFromParent ( ) ; if ( LGFR ) eraseIfDead ( LGFR , MRI ) ; eraseIfDead ( RLL , MRI ) ; eraseIfDead ( SRL


<s> lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc (


<s> static void mmix_target_asm_function_prologue ( FILE * ) { cfun -> machine -> in_prologue =


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue TEB = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; Chain = TLSArray . getValue ( <NUM_LIT> ) ; SDValue TLSIndexHi = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue TLSIndexLo = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndexHi ) ; SDValue TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , TLSIndexLo


<s> getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( LoadOpcode


<s> } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( isFP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Size = <NUM_LIT> ; if ( hasCOP3 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( hasCHERI ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCHERI32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isGP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_GP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isPTR64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_PTR6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>2 ( ) && isPTR64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32_64_PTR6432 , Instr ,


<s> static HOST_WIDE_INT rounded_frame_size ( int pushed ) { HOST_WIDE_INT size = get_frame_size ( ) ; HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT ; if ( ACCUMULATE_OUTGOING_ARGS ) size += crtl -> outgoing_args_size ; return ( ( size + pushed + align - <NUM_LIT> ) &


<s> SDLoc dl ( Op ) ; SDValue SatValue ; uint64_t SatConstant ; bool SatUSat ; if ( ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) && isSaturatingConditional ( Op , SatValue , SatConstant , SatUSat ) ) { if ( SatUSat ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; else return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; } SDValue LowerSatConstant ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FalseVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( Subtarget -> hasV8_1MMainlineOps ( ) && CFVal && CTVal && LHS . getValueType ( ) == <STR_LIT> && RHS . getValueType ( ) == <STR_LIT> ) { unsigned TVal = CTVal -> getZExtValue ( ) ; unsigned FVal = CFVal -> getZExtValue ( ) ; unsigned Opcode = <NUM_LIT> ; if ( TVal == ~ FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == ~ FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( TVal + <NUM_LIT> == FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; std :: swap ( TrueVal , FalseVal ) ; std :: swap ( TVal , FVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( Opcode ) { if ( Opcode != <STR_LIT> && HasLowerConstantMaterializationCost ( FVal , TVal , Subtarget ) ) { std :: swap (


<s> unsigned R = getRelaxedOpcodeArith ( Inst ) ; if ( R != Inst . getOpcode ( ) ) return R ; return getRelaxedOpcodeBranch ( Inst , is16BitMode


<s> rtx mips_expand_thread_pointer ( rtx tp ) { rtx fn ; if ( TARGET_MIPS16 ) { if ( ! mips16_rdhwr_stub ) mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ( ) ; fn = mips16_stub_call_address ( mips16_rdhwr_stub ) ; emit_insn ( PMODE_INSN ( gen_tls_get_tp_mips16 , ( tp , fn ) ) ) ; } else emit_insn ( PMODE_INSN ( gen_tls_get_tp ,


<s> void printS22ImmOperand ( const MachineInstr * MI , unsigned OpNo ) { int val = ( unsigned int ) MI -> getOperand ( OpNo ) . getImm ( ) ; if ( val >= <NUM_LIT> )


<s> if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg1 , MRI , TRI ) ; auto ValAndVReg = getConstantVRegValWithLookThrough (


<s> rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = <NUM_LIT> ; data -> cost [ vect_body ] = <NUM_LIT> ; data -> cost [ vect_epilogue ] = <NUM_LIT> ; rs6000_vect_nonmem = false ; return


<s> static inline bool isSVECpyImmByte ( int64_t


<s> SDValue LenMinus1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getZExtOrTrunc ( Size , DL , <STR_LIT> ) , DAG .

getConstant ( - <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> static bool isCMOVWithZeroOrAllOnesLHS ( SDValue N , bool AllOnes ) { if ( N . getOpcode ( ) != <STR_LIT> || ! N . getNode ( ) -> hasOneUse ( ) ) return false ; SDValue FalseVal = N . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( FalseVal ) ; if ( ! C ) return


<s> RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return true


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true


<s> if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( <STR_LIT> , attributes ) !=


<s> MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is256BitVector ( ) && NumElts == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt <


<s> emit_move_insn ( adjust_address ( tramp_mem , SImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; emit_move_insn ( adjust_address ( tramp_mem , SImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; return ; } tramp_templ = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; fixed_len = TRAMPOLINE_SIZE - <NUM_LIT> * GET_MODE_SIZE ( Pmode ) ; tramp_templ = gen_datalabel_ref ( tramp_templ ) ; dst = tramp_mem ; src = gen_const_mem ( BLKmode , tramp_templ ) ; set_mem_align ( dst , <NUM_LIT> ) ; set_mem_align ( src , <NUM_LIT> ) ; emit_block_move ( dst , src , GEN_INT ( fixed_len ) , BLOCK_OP_NORMAL ) ; emit_move_insn ( adjust_address ( tramp_mem , Pmode , fixed_len ) , fnaddr ) ; emit_move_insn ( adjust_address ( tramp_mem , Pmode , fixed_len + GET_MODE_SIZE ( Pmode ) ) , cxt ) ; emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; return ; } else if ( TARGET_SHMEDIA ) { rtx quad0 = gen_reg_rtx ( DImode ) , cxtload = gen_reg_rtx ( DImode ) ; rtx quad1 = gen_reg_rtx ( DImode ) , quad2 = gen_reg_rtx ( DImode ) ; rtx movishori = force_reg ( V2HImode , ( simplify_gen_subreg ( V2HImode , GEN_INT ( <NUM_LIT> ) , SImode , <NUM_LIT> ) ) ) ; rtx ptabs = force_reg ( DImode , GEN_INT ( <NUM_LIT> ) ) ; rtx blink = force_reg ( DImode , GEN_INT ( <NUM_LIT> ) ) ; tramp = force_reg ( Pmode , tramp ) ; fnaddr = force_reg ( SImode , fnaddr ) ; cxt = force_reg ( SImode , cxt ) ; emit_insn ( gen_mshflo_w_x ( gen_rtx_SUBREG ( V4HImode , quad0 , <NUM_LIT> ) , gen_rtx_SUBREG ( V2HImode , fnaddr , <NUM_LIT> ) , movishori ) ) ; emit_insn ( gen_rotrdi3_mextr ( quad0 , quad0 , GEN_INT ( TARGET_LITTLE_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ) ) ; emit_insn ( gen_ashldi3_media ( quad0 , quad0 , const2_rtx ) ) ; emit_move_insn ( change_address ( tramp_mem , DImode , NULL_RTX ) , quad0 ) ; emit_insn ( gen_mshflo_w_x ( gen_rtx_SUBREG ( V4HImode , cxtload , <NUM_LIT> ) , gen_rtx_SUBREG ( V2HImode , cxt ,


<s> static SDValue LowerMUL_LOHI ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) , Op1 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op0 . getValueType ( ) ; SDLoc dl ( Op ) ; assert ( ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) || ( VT == <STR_LIT> && Subtarget -> hasInt256 ( ) ) ) ; const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue Hi0 = DAG . getVectorShuffle ( VT , dl , Op0 , Op0 , Mask ) ; SDValue Hi1 = DAG . getVectorShuffle ( VT , dl , Op1 , Op1 , Mask ) ; MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget -> hasSSE41 ( )


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( MF . getFunction ( ) . hasOptSize ( ) ) return false ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> || windowsRequiresStackProbe ( MF , StackBumpBytes


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? <STR_LIT> :


<s> MachineConstantPool & MCP = * MF . getConstantPool ( ) ; TII = ( const <ISA_LIT>InstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; isThumb1 = AFI -> isThumb1OnlyFunction ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; HasFarJump = false ; HasInlineAsm = false ; MF . RenumberBlocks ( ) ; bool MadeChange = false ; if ( isThumb2 && AdjustJumpTableBlocks ) { JumpTableFunctionScan ( MF ) ; MadeChange |= ReorderThumb2JumpTables ( MF ) ; T2JumpTables . clear ( ) ; MF . RenumberBlocks ( ) ; } if ( ! isThumb1 ) MF . EnsureAlignment ( <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP . isEmpty ( ) ) { DoInitialPlacement ( MF , CPEMIs ) ; if ( isThumb1 ) MF . EnsureAlignment ( <NUM_LIT> ) ; } AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; InitialFunctionScan ( MF , CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= RemoveUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= HandleConstantPoolUser ( MF , i ) ; if ( CPChange && ++ NoCPIters >


<s> if ( ARM_FUNC_TYPE ( cfun -> machine -> func_type ) == ARM_FT_UNKNOWN ) cfun -> machine ->


<s> Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; const MCExpr * Expr = getMemOffset ( ) ; addExpr ( Inst , Expr ) ; Inst . addOperand ( MCOperand :: createImm ( getMemOp ( )


<s> int64_t ImmVal = ValAndVReg -> Value . getSExtValue ( ) ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { if ( ! LookedThroughZExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = isSignExtendShiftType ( Ext ) ? <NUM_LIT> : <NUM_LIT> ; if ( SignExtend && Ext != <STR_LIT> ) return None ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg ( ) ) ) ; OffsetReg = moveScalarRegClass ( OffsetReg ,


<s> case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp ) ; break ; } return Tmp


<s> case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy ,


<s> static unsigned int rest_of_handle_insert_vzeroupper ( void ) { if ( TARGET_VZEROUPPER && flag_expensive_optimizations && ! optimize_size ) { for ( int i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ; g -> get_passes ( ) -> execute_pass_mode_switching ( ) ; } ix86_add_reg_usage_to_vzerouppers (


<s> if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return <NUM_LIT> ; } return PartialRegUpdateClearance


<s> return x ; } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == HIGH ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } * win = <NUM_LIT>


<s> * op = gen_rtx_SUBREG ( vmode , * op , <NUM_LIT> ) ; } else if ( CONST_INT_P ( * op ) ) { rtx vec_cst ; rtx tmp = gen_rtx_SUBREG ( vmode , gen_reg_rtx ( smode ) , <NUM_LIT> ) ; if ( constm1_operand ( * op , GET_MODE ( * op ) ) ) vec_cst = CONSTM1_RTX ( vmode ) ; else { unsigned n = GET_MODE_NUNITS ( vmode ) ; rtx * v = XALLOCAVEC ( rtx , n ) ; v [ <NUM_LIT> ] = * op ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) v [ i ] = const0_rtx ; vec_cst = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( n , v ) ) ; } if ( ! standard_sse_constant_p ( vec_cst , vmode ) ) { start_sequence ( ) ; vec_cst = validize_mem ( force_const_mem ( vmode , vec_cst ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; } emit_insn_before ( gen_move_insn ( copy_rtx ( tmp )


<s> unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; bool SignedConv = Opc == <STR_LIT> ; if ( SignedConv && ! Subtarget . hasP9Altivec ( ) ) return SDValue ( ) ; SDValue Wide = widenVec ( DAG , Op . getOperand ( <NUM_LIT> ) , dl ) ; EVT WideVT = Wide . getValueType ( ) ; unsigned WideNumElts = WideVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffV ; for ( unsigned i = <NUM_LIT> ; i < WideNumElts ; ++ i ) ShuffV . push_back ( i + WideNumElts ) ; if ( Subtarget . isLittleEndian ( ) ) { ShuffV [ <NUM_LIT> ] = <NUM_LIT> ; ShuffV [ WideNumElts / <NUM_LIT> ] = <NUM_LIT> ; } else { ShuffV [ WideNumElts / <NUM_LIT> - <NUM_LIT> ] = <NUM_LIT> ; ShuffV [ WideNumElts - <NUM_LIT> ] = <NUM_LIT> ; } SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) : DAG . getConstant ( <NUM_LIT> , dl , WideVT


<s> SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi


<s> if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op


<s> std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; std :: string Key = CPU + FS ; if ( F . hasMinSize ( ) ) Key


<s> unsigned getShiftRight32Imm ( const MachineInstr & MI , unsigned Op ) const { return


<s> return __builtin_aarch64_ld1v16qi ( ( const __builtin_aarch64_simd_qi *


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isOperationLegalOrCustom ( <STR_LIT> , VT ) ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( VT . is128BitVector ( ) && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; auto OnlyUsedAsSelectCond = [ ] ( SDValue Cond ) { for ( SDNode :: use_iterator UI = Cond -> use_begin ( ) , UE = Cond -> use_end ( ) ; UI != UE ; ++ UI ) if ( ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) || UI . getOperandNo ( ) != <NUM_LIT> ) return false ; return true ; } ; if ( OnlyUsedAsSelectCond ( Cond ) ) { APInt DemandedMask ( APInt :: getSignMask ( BitWidth ) ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; if ( ! TLI . SimplifyDemandedBits ( Cond , DemandedMask , Known , TLO , <NUM_LIT> , true ) ) return SDValue ( ) ; for ( SDNode * U : Cond


<s> if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( ( Op0 . getValueType ( ) == <STR_LIT> && ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 )

) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget . isAtom ( ) ) {


<s> static void mips_end_function_definition ( const char * name ) { if ( ! flag_inhibit_size_directive )


<s> const int64_t CalleeSaveSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; const bool HasFP = hasFP ( MF ) ; const bool IsRCXLiveIn = MBB . isLiveIn ( <STR_LIT> ) ; const bool IsRDXLiveIn = MBB . isLiveIn ( <STR_LIT> ) ; int64_t InitSlot = <NUM_LIT> + CalleeSaveSize + ( HasFP ? <NUM_LIT> : <NUM_LIT> ) ; if ( IsRCXLiveIn ) RCXShadowSlot = InitSlot ; if ( IsRDXLiveIn ) RDXShadowSlot = InitSlot ; if ( IsRDXLiveIn && IsRCXLiveIn ) RDXShadowSlot += <NUM_LIT> ; if ( IsRCXLiveIn ) addRegOffset ( BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) , <STR_LIT> , false , RCXShadowSlot ) . addReg ( <STR_LIT> ) ; if ( IsRDXLiveIn ) addRegOffset ( BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) , <STR_LIT> , false , RDXShadowSlot ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , SizeReg ) . addReg ( <STR_LIT> ) ; } BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , ZeroReg ) . addReg ( ZeroReg , RegState :: Undef ) . addReg ( ZeroReg , RegState :: Undef ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , CopyReg ) . addReg ( <STR_LIT> ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , TestReg ) . addReg ( CopyReg ) . addReg ( SizeReg ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , FinalReg ) . addReg ( TestReg ) . addReg ( ZeroReg ) . addImm ( <STR_LIT> ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , LimitReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( ThreadEnvironmentStackLimit ) . addReg ( <STR_LIT> ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( FinalReg ) . addReg ( LimitReg ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( ContinueMBB ) . addImm ( <STR_LIT> ) ; RoundMBB -> addLiveIn ( FinalReg ) ; BuildMI ( RoundMBB , DL , TII . get ( <STR_LIT> ) , RoundedReg ) . addReg ( FinalReg ) . addImm ( PageMask ) ; BuildMI ( RoundMBB , DL , TII . get ( <STR_LIT>


<s> fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; mips_start_function_definition ( fnname , TARGET_MIPS16 ) ; if ( ! flag_inhibit_size_directive ) { const struct mips_frame_info * frame ; frame = & cfun -> machine -> frame ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , reg_names [ frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ] , ( frame_pointer_needed ? frame -> total_size - frame -> hard_frame_pointer_offset : frame -> total_size ) , reg_names [ RETURN_ADDR_REGNUM ] , frame -> var_size , frame -> num_gp , frame -> num_fp , frame -> args_size , frame -> cprestore_size ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , frame -> mask , frame -> gp_save_offset ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , frame -> fmask , frame -> fp_save_offset ) ; } if ( mips_must_initialize_gp_p ( ) && mips_current_loadgp_style ( ) == LOADGP_OLDABI ) { if ( TARGET_MIPS16 ) { output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { mips_push_asm_switch ( & mips_noreorder ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; if ( ! cfun -> machine -> all_noreorder_p ) mips_pop_asm_switch ( & mips_noreorder ) ; else mips_push_asm_switch ( & mips_nomacro ) ; } } else if ( cfun -> machine -> all_noreorder_p ) { mips_push_asm_switch ( & mips_noreorder ) ; mips_push_asm_switch ( & mips_nomacro


<s> if ( ! Subtarget -> inMicro<ISA_LIT>Mode ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) || Subtarget -> has<ISA_LIT>32r6 ( ) ) return false ; <ISA_LIT>II = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF


<s> case LibFunc :: truncf : case LibFunc :: truncl : Opcode = <STR_LIT> ; break ; } MVT VTy = TLI -> getSimpleValueType ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( VTy == <STR_LIT> ) return true ; if ( TLI -> isOperationLegalOrCustom ( Opcode , VTy ) ) continue ; else if ( VTy . isVector ( ) && TLI -> isOperationLegalOrCustom ( Opcode , VTy . getScalarType ( ) ) ) continue ; return true ; } } return true ; } else if ( isa < BinaryOperator > ( J ) && J -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) { return true ; } else if ( isa < UIToFPInst > ( J ) || isa < SIToFPInst > ( J ) || isa < FPToUIInst > ( J ) || isa < FPToSIInst > ( J ) ) { CastInst * CI = cast < CastInst > ( J ) ; if ( CI -> getSrcTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || CI -> getDestTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || isLargeIntegerTy ( TT . isArch32Bit ( ) , CI -> getSrcTy ( ) -> getScalarType ( ) ) || isLargeIntegerTy ( TT . isArch32Bit ( ) , CI -> getDestTy ( ) -> getScalarType ( ) ) ) return true ; } else if ( isLargeIntegerTy ( TT . isArch32Bit ( ) , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: UDiv || J -> getOpcode ( ) == Instruction :: SDiv || J -> getOpcode ( ) == Instruction :: URem || J -> getOpcode ( ) == Instruction :: SRem ) ) { return true ; } else if ( TT . isArch32Bit ( ) && isLargeIntegerTy ( false , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: Shl || J -> getOpcode ( ) == Instruction :: AShr || J -> getOpcode ( ) == Instruction :: LShr ) ) { return true ; } else if ( isa < IndirectBrInst > ( J ) || isa < InvokeInst > ( J ) ) { return true ; } else if ( SwitchInst * SI = dyn_cast < SwitchInst > ( J ) ) { if ( ! TM


<s> if ( ( ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) ) || ( ( ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) ) ) ) sc = context -> cfa ; else if ( ( ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) ) || ( ( ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) && ( * ( unsigned short * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) ) ) ) { struct rt_sigframe { struct siginfo info ; struct ucontext uc ; } * rt_ = context -> cfa ; sc = ( struct sigcontext * ) ( void * ) & rt_ -> uc . uc_mcontext ; } else return


<s> } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode


<s> assert ( ( ( ! Subtarget -> hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( ( Op0 . getValueType ( ) == <STR_LIT> ) && isOneConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , NewCC ) ; } bool isFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , bool _is64Bit ) : <ISA_LIT>AsmBackend ( T ,


<s> } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : case Match_AlignedMemoryRequires64 : case Match_DupAlignedMemoryRequires64 : case Match_AlignedMemoryRequires64or128 : case Match_DupAlignedMemoryRequires64or128 : case Match_AlignedMemoryRequires64or128or256 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getAlignmentLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; switch ( MatchResult ) { default : llvm_unreachable ( <STR_LIT> ) ; case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires32


<s> if ( Subtarget -> isABI_EABI ( ) ) O << <STR_LIT> << ( Subtarget -> isGP32bit ( ) ? <STR_LIT> : <STR_LIT> ) << '\n' ; O << <STR_LIT> <<


<s> unsigned UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . addOperand ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> isAtom ( ) || STI -> isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; DefMov -> eraseFromParent ( ) ; } else { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addReg ( Reg ) . getInstr ( ) ; } break ; } if ( ! TFL -> hasFP ( MF ) ) TFL -> BuildCFI ( MBB , std :: next ( Push ) ,

DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , SlotSize ) ) ;


<s> for ( reg = <NUM_LIT> ; reg < CSKY_NGPR_REGS ; reg ++ ) { bool save = false ; if ( CSKY_TARGET_ARCH ( CK801 ) && reg > <NUM_LIT> && reg < <NUM_LIT> ) continue ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > <NUM_LIT> ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_really_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == FRAME_POINTER_REGNUM ) save = true ; else if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && reg == CSKY_LR_REGNUM && ( ! crtl -> is_leaf || csky_far_jump_used_p ( ) ) ) save = true ; else if ( crtl -> calls_eh_return && reg >= CSKY_FIRST_EH_RETDATA_REGNUM && reg <= CSKY_LAST_EH_RETDATA_REGNUM ) save = true ; if ( reg == CSKY_STACKADJUST_REGNUM && cfun -> machine -> reg_offset > CSKY_MAX_SP_ADJUST


<s> Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) ,


<s> uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ,


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && !


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned isRead = ~ cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) & <NUM_LIT> ; if ( ! isRead && ( ! Subtarget -> hasV7Ops ( ) || ! Subtarget -> hasMPExtension ( ) ) ) return Op . getOperand ( <NUM_LIT> ) ; unsigned isData = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Subtarget -> isThumb ( ) ) { isRead = ~ isRead & <NUM_LIT> ; isData = ~ isData


<s> for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = <STR_LIT> + MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) || ! TargetRegisterInfo :: isVirtualRegister


<s> case <STR_LIT> : isPre = true ; break ; case <STR_LIT> : break ; } unsigned MemOpc = getUnindexedOpcode ( MI -> getOpcode ( ) ) ; if ( MemOpc == <NUM_LIT> ) return NULL ; MachineInstr * UpdateMI = NULL ; MachineInstr * MemMI = NULL ; unsigned AddrMode = ( TSFlags & <STR_LIT> ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned NumOps = MCID . getNumOperands ( ) ; bool isLoad = ! MI -> mayStore ( ) ; const MachineOperand & WB = isLoad ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Base = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Offset = MI -> getOperand ( NumOps - <NUM_LIT> ) ; unsigned WBReg = WB . getReg ( ) ; unsigned BaseReg = Base . getReg ( ) ; unsigned OffReg = Offset . getReg ( ) ; unsigned OffImm = MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; switch ( AddrMode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { bool isSub = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; if ( OffReg == <NUM_LIT> ) { if ( <STR_LIT> ( Amt ) == - <NUM_LIT> ) return NULL ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addImm ( Amt ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( Amt != <NUM_LIT> ) { <STR_LIT> ShOpc = <STR_LIT> ( OffImm ) ; unsigned SOOpc = <STR_LIT> ( ShOpc , Amt ) ; UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addReg ( <NUM_LIT> ) . addImm ( SOOpc ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } else UpdateMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isSub ? <STR_LIT> : <STR_LIT> ) , WBReg ) . addReg ( BaseReg ) . addReg ( OffReg ) . addImm ( Pred ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { bool isSub = <STR_LIT> (


<s> if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; unsigned ByteSize = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( StackSlot ) ; MachineMemOperand * MMO ; if ( FI ) { int SSFI = FI -> getIndex ( ) ; MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , ByteSize , ByteSize ) ; } else { MMO = cast < LoadSDNode > ( StackSlot ) -> getMemOperand ( ) ; StackSlot = StackSlot . getOperand ( <NUM_LIT> ) ; } SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , Ops , SrcVT , MMO ) ; if (


<s> const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> } if ( N -> getMemoryVT ( ) == <STR_LIT> ) { SDValue Flag ; SDValue Bits ; SDValue NewVal = prepareTS1AM ( Op , DAG , Flag , Bits ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; SDValue Aligned = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , { Ptr , DAG . getConstant ( - <NUM_LIT> , DL , <STR_LIT> ) } ) ; SDValue TS1AM = DAG . getAtomic ( <STR_LIT> , DL , N -> getMemoryVT ( ) , DAG . getVTList ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) , Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ) , { N -> getChain ( ) , Aligned , Flag , NewVal } , N -> getMemOperand ( ) ) ; SDValue Result = finalizeTS1AM ( Op , DAG , TS1AM , Bits ) ; SDValue Chain = TS1AM . getValue (


<s> if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT>


<s> if ( ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; EVT WideVecVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue WideVec = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Subtarget . hasAVX ( ) && ! Subtarget . hasAVX2 ( ) && TLI . isTypeLegal ( WideVecVT ) && WideVecVT . getSizeInBits ( ) == <NUM_LIT> && WideVec . getOpcode ( ) == <STR_LIT> ) { auto isConcatenatedNot = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; if ( ! isBitwiseNot ( V ) ) return false ; SDValue NotOp = V -> getOperand ( <NUM_LIT> ) ; return peekThroughBitcasts ( NotOp ) . getOpcode ( ) == <STR_LIT> ; } ; if ( isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) || isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) ) { SDValue Concat = split256IntArith ( WideVec , DAG ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getBitcast ( WideVecVT , Concat ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue InVec = N -> getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( VT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; return getOnesVector ( VT , DAG , SDLoc ( N ) ) ; } if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( VT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , VT . getVectorNumElements ( ) ) ) ; if ( InVec . getOpcode ( ) == <STR_LIT> && InVec . hasOneUse ( ) && InVec . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; if ( IdxVal == <NUM_LIT> && InVec . hasOneUse ( ) ) { unsigned InOpcode = InVec . getOpcode ( ) ; if ( VT == <STR_LIT> && InVec . getValueType (


<s> llvm :: StringRef fde_region = createFDERegionForPLT ( ) ; EhFrame :: CIE * cie = new EhFrame :: GeneratedCIE ( cie_region ) ; EhFrame :: FDE * fde = new EhFrame :: GeneratedFDE ( fde_region , * cie ) ; uint8_t aug_data = ( uint8_t ) ( llvm :: dwarf :: DW_EH_PE_pcrel | llvm :: dwarf :: DW_EH_PE_sdata4 ) ; cie -> setFDEEncode ( aug_data ) ; cie -> setAugmentationData ( std :: string ( <NUM_LIT> , aug_data ) ) ; EhFrame :: cie_iterator i = eh_frame -> cie_begin ( ) ; for ( EhFrame :: cie_iterator e = eh_frame -> cie_end ( ) ; i != e ; ++ i ) { EhFrame :: CIE & exist_cie = * * i ; if ( exist_cie == * cie ) { SectionData :: iterator cur_iter ( exist_cie ) ; frag_list . insertAfter ( cur_iter , fde ) ; fde -> setCIE ( exist_cie


<s> unsigned <ISA_LIT>InstrInfo :: getLoadOpcodeForSpill ( const TargetRegisterClass * RC ) const { const unsigned * OpcodesForSpill =


<s> Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl ) ) ; return ; case <STR_LIT> : { EVT TrgVT = N -> getValueType ( <NUM_LIT> ) ; EVT OpVT = N -> getOperand ( <NUM_LIT> ) .


<s> SDValue <ISA_LIT>TargetLowering :: LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc = Cond . getOpcode ( ) ; if ( Cond . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Cond -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Cond , DAG , <ISA_LIT>cc ) ; <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc


<s> const TargetRegisterClass * ThumbRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return & <STR_LIT> ; return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass (


<s> SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , <NUM_LIT> , UndefElts , RawMask ) ) return ; unsigned NumElts = Width / <NUM_LIT> ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Element = RawMask [ i


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; return visibility_types [ vis


<s> static unsigned decodeVCVTFractionBits (


<s> return __builtin_mve_vmladavaq_uv8hi ( __a ,


<s> int imm = Val & <NUM_LIT> ; if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( imm << <NUM_LIT> ) ) ; return MCDisassembler


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 ) && <STR_LIT> ) ; else assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 ) && <STR_LIT> ) ; } bool CloseParen = <ISA_LIT>MCExpr :: printVariantKind ( O , TF ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) ->


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) &


<s> if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts , opts_set ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , false ) ; arm_option_check_internal ( opts ) ; arm_option_reconfigure_globals ( )


<s> else return <NUM_LIT> ; const unsigned Form132Index = <NUM_LIT> ; const unsigned Form213Index = <NUM_LIT> ; const unsigned Form231Index = <NUM_LIT> ; static const unsigned FormMapping [ ] [ <NUM_LIT> ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [ <NUM_LIT> ] ; if ( FMA3Group . isRegOpcodeFromGroup ( Opc ) ) { FMAForms [ <NUM_LIT> ] = FMA3Group . getReg132Opcode ( ) ; FMAForms [ <NUM_LIT> ] = FMA3Group . getReg213Opcode ( ) ; FMAForms [ <NUM_LIT> ] = FMA3Group . getReg231Opcode ( ) ; } else { FMAForms [ <NUM_LIT> ] = FMA3Group . getMem132Opcode ( ) ; FMAForms [ <NUM_LIT> ] = FMA3Group . getMem213Opcode ( ) ; FMAForms [ <NUM_LIT> ] = FMA3Group . getMem231Opcode ( ) ; } unsigned FormIndex ; for ( FormIndex = <NUM_LIT> ; FormIndex < <NUM_LIT> ; FormIndex ++ ) if ( Opc == FMAForms [ FormIndex ] ) break ; FormIndex = FormMapping [ Case ] [ FormIndex ] ; return FMAForms [


<s> return ( __m64 ) __builtin_ia32_paddsw ( ( __v4hi ) __m1 , (


<s> bool isMovWSymbol ( ArrayRef < <ISA_LIT>MCExpr :: VariantKind > AllowedModifiers ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , ELFRefKind , DarwinRefKind , Addend ) ) { return false ; } if ( DarwinRefKind != MCSymbolRefExpr :: VK_None ) return false ; for ( unsigned i = <NUM_LIT> ; i != AllowedModifiers . size ( ) ; ++ i ) { if ( ELFRefKind == AllowedModifiers [ i ]


<s> bool isTypedVectorList ( ) const { if ( Kind != k_VectorList ) return false ; if ( VectorList . Count != NumRegs


<s> SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; AM . Scale = <NUM_LIT> << ShiftAmt ; AM . IndexReg = NewAnd ; return false


<s> static bool isUndefOrInRange ( ArrayRef < int > Mask , int Low , int Hi ) { return llvm :: all_of ( Mask , [ Low , Hi ] ( int M

) { return isUndefOrInRange ( M , Low , Hi ) ; } ) ;


<s> const class MachineLegalizer * getMachineLegalizer ( )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getJumpTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr & MI = * -- MBBI ; if ( CompleteCCUsers && ( MI . isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI . eraseFromParent ( ) ; Changed = true ; CCUsers . clear (


<s> printOperand ( MI , i ) ; if ( i != e - <NUM_LIT> ) O << <STR_LIT> ; } O <<


<s> static ScheduleDAGInstrs * create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , ST . use<ISA_LIT>PreRASchedStrategy ( ) ? std :: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) : std :: make_unique < GenericScheduler > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI


<s> if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N ,


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { HasV4TOps = false ; HasV5TOps = false ; HasV5TEOps = false ; HasV6Ops = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide =


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ) ; return false ; } } if ( ! ParseExpression ( EVal ) ) break ; LLVM_FALLTHROUGH ; default : return Error ( S , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex (


<s> O << <STR_LIT> << utohexstr ( MI -> getOperand (


<s> if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugInstr ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; llvm :: sort ( Candidates . begin ( ) , Candidates . end ( ) , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates ) { if ( Candidate -> CanMergeToLSMulti || Candidate -> CanMergeToLSDouble ) { MachineInstr * Merged = MergeOpsUpdate ( * Candidate ) ; if ( Merged ) { Changed = true ; unsigned Opcode = Merged -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MergeBaseUpdateLSDouble ( * Merged ) ; else MergeBaseUpdateLSMultiple ( Merged ) ; } else { for ( MachineInstr * MI : Candidate -> Instrs ) { if ( MergeBaseUpdateLoadStore ( MI ) ) Changed = true ; } } } else { assert ( Candidate -> Instrs . size ( ) == <NUM_LIT> ) ; if ( MergeBaseUpdateLoadStore ( Candidate -> Instrs . front ( ) ) ) Changed = true ; } } Candidates . clear ( )


<s> static bool DisassembleN2RegFrm ( MCInst & MI , unsigned Opc , uint32_t insn , unsigned short NumOps


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> && ! zeroPermitted ) S = MCDisassembler :: Fail ; uint64_t DecVal ; if ( isSigned ) DecVal = SignExtend32 < size + <NUM_LIT> > ( Val << <NUM_LIT> ) ; else DecVal = (


<s> MachineOperand MOpSHSrc = SrcMI -> getOperand ( <NUM_LIT> ) ; MachineOperand MOpMBSrc = SrcMI -> getOperand ( <NUM_LIT> ) ; MachineOperand MOpSHMI = MI . getOperand ( <NUM_LIT> ) ; MachineOperand MOpMEMI = MI . getOperand ( <NUM_LIT> ) ; if ( ! ( MOpSHSrc . isImm ( ) && MOpMBSrc . isImm ( ) && MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHSrc = MOpSHSrc . getImm ( ) ; uint64_t MBSrc = MOpMBSrc . getImm ( ) ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; uint64_t NewSH = SHSrc + SHMI ; uint64_t NewMB = MBSrc - SHMI ; if ( NewMB > <NUM_LIT> || NewSH > <NUM_LIT> ) return false ; if ( ( <NUM_LIT> - NewSH ) != MEMI ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewSH ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewMB ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( SrcMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; SrcMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; NumRotatesCollapsed ++ ; if ( MRI -> use_nodbg_empty ( SrcReg ) ) { assert ( ! SrcMI -> hasImplicitDef ( ) && <STR_LIT> ) ; SrcMI -> eraseFromParent (


<s> void <ISA_LIT>DAGToDAGISel :: SelectPostStoreLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) transform ( Regs , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > (