<s> } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType


<s> if ( j == <NUM_LIT> ) break ; if ( ! BucketChain . Elements [ j ] . Offset || cast < SCEVConstant > ( BucketChain . Elements [ j ] . Offset ) -> isZero ( ) ) break ; const SCEV * Offset = BucketChain . Elements [ j ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Offset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; default : Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; break ; } if ( DecodeRegListOperand16 ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> std :: unique_ptr < ScheduleDAGMutation

> create<ISA_LIT>MacroFusionDAGMutation ( ) {


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTruncatedShiftCount ( MI , <NUM_LIT> ) != <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( Register R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC


<s> virtual const TargetFrameLowering * getFrameLowering


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> static bool compareMbbNumbers ( const MachineBasicBlock * LHS , const MachineBasicBlock * RHS ) { return LHS -> getNumber ( ) < RHS


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> } if ( ins >> <NUM_LIT> == <NUM_LIT> ) { reg_unit src = ( ins >> <NUM_LIT> & <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : gprs [ ins >> <NUM_LIT> & <NUM_LIT> ] ; uint32_t * p = ( uint32_t * ) ( src + ( int16_t ) ins ) ; if ( p == NULL || invalid_address != NULL ) return false ; invalid_address = p ; continue ; } if ( ins >> <NUM_LIT> == <NUM_LIT> ) { reg_unit src = ( ins >> <NUM_LIT> & <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : gprs [ ins >> <NUM_LIT> & <NUM_LIT> ] ; uint32_t * p = ( uint32_t * ) ( src + ( int16_t ) ins ) ; int i ; for ( i = ( ins >> <NUM_LIT> & <NUM_LIT> ) ; i < <NUM_LIT> ; i ++ ) { if ( p == invalid_address ) return false ; gprs [ i ] = * p ++ ; } continue ; } if ( ( ins & <NUM_LIT> ) == <NUM_LIT> ) { lr = gprs [ ins >> <NUM_LIT> & <NUM_LIT> ] ; continue ; } if ( ( ins & <NUM_LIT> ) == <NUM_LIT> ) { gprs [ ins >> <NUM_LIT> & <NUM_LIT> ] = lr ; continue ; } if ( ( ins & <NUM_LIT> ) == <NUM_LIT> ) { ctr = gprs [ ins >> <NUM_LIT> & <NUM_LIT> ] ; continue ; } if ( ( ins & <NUM_LIT> ) == <NUM_LIT> ) { int i ; uint32_t mask = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask |= ( ( - ( ins >> ( <NUM_LIT> + i ) & <NUM_LIT> ) ) & <NUM_LIT> ) << <NUM_LIT> * i ; cr = ( cr & ~ mask ) | ( gprs [ ins >> <NUM_LIT> & <NUM_LIT> ] & mask ) ; continue ; } if ( ins == <NUM_LIT> ) { lr = ( reg_unit ) pc ; continue ; } if ( ins == <NUM_LIT> ) { pc = ( uint32_t * ) ctr ; continue ; } if ( ins ==


<s> if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( SubVecTy , DL ) ) return Factor * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor

, Indices , Alignment , AddressSpace ) ;


<s> shmask . ll [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) >> <NUM_LIT>


<s> case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; } return


<s> SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V ) return SDValue (


<s> static SDValue PromoteMVEPredVector ( SDLoc dl , SDValue Pred , EVT VT , SelectionDAG & DAG ) { SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue AllZeroes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllZeroes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllZeroes ) ; EVT NewVT = getVectorTyFromPredicateVector ( VT ) ; SDValue RecastV1 ; if ( VT != <STR_LIT> ) RecastV1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Pred ) ; else RecastV1 = Pred ; SDValue PredAsVector = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RecastV1 , AllOnes , AllZeroes ) ; return DAG . getNode ( <STR_LIT> , dl , NewVT


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMovePRegSingleOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( ( ( OpNo == <NUM_LIT> ) || ( OpNo == <NUM_LIT> ) ) && <STR_LIT> ) ; MCOperand Op = MI . getOperand ( OpNo ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; switch ( Op . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> return ( ( vec_double2 ) ( si_selb ( ( qword ) ( a ) , ( qword ) ( b ) ,


<s> DAG . computeKnownBits ( Op0 , Known ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 (


<s> a = ( __vector unsigned short ) vec_splats ( __A ) ; b = ( __vector unsigned short ) vec_splats ( __B ) ; w0 = vec_vmuleuh ( a , b ) ; w1 = vec_vmulouh ( a , b ) ; c = ( __vector unsigned short ) vec_perm ( w0 ,


<s> r1 = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_load_split_stack_limit ( r0 ) ) ; alloc_hi = ( - allocate + <NUM_LIT> ) & ~ <NUM_LIT> ; alloc_lo = - allocate - alloc_hi ; if ( alloc_hi != <NUM_LIT> ) { emit_insn ( gen_add3_const ( r12 , r1 , alloc_hi ) ) ; if ( alloc_lo != <NUM_LIT> ) emit_insn ( gen_add3_const ( r12 , r12 , alloc_lo ) ) ; else emit_insn ( gen_nop ( ) ) ; } else { emit_insn ( gen_add3_const ( r12 , r1 , alloc_lo ) ) ; emit_insn ( gen_nop ( ) ) ; } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 , r0 ) ) ) ; ok_label = gen_label_rtx ( ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , compare , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , ok_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( insn ) = ok_label ; add_reg_br_prob_note ( insn , profile_probability :: very_likely ( ) ) ; lr = gen_rtx_REG ( Pmode , LR_REGNO


<s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( Idx . getSimpleValueType ( ) == <STR_LIT> ) Idx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Idx ) ; if ( Val . getSimpleValueType ( ) == <STR_LIT> ) Val = DAG . getBitcast ( <STR_LIT> , Val ) ; assert ( Val . getSimpleValueType ( ) == <STR_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue Result = Op ; if ( <NUM_LIT> ) { } else { SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue PackedElt = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { Vec , HalfIdx } ) , <NUM_LIT> ) ; SDValue AndIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { AndIdx , Const1 } ) ; SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL ,


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian , bool IsILP32 ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , IsLittleEndian , IsILP32 ) ; return createELFObjectWriter ( MOTW , OS ,


<s> bool <ISA_LIT>AsmParser :: validatetSTMRegList ( const MCInst & Inst , const OperandVector & Operands , unsigned ListNo ) { const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ; bool ListContainsSP = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsPC = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; if ( ListContainsSP && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; return


<s> if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI . getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true


<s> function_arg_info arg ( type , true ) ; apply_pass_by_reference_rules ( get_cumulative_args ( args_so_far ) , arg ) ; unsignedp = TYPE_UNSIGNED ( type ) ; arg . mode = promote_mode ( arg . type , arg . mode , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( arg ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , arg ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , <NUM_LIT> , <NUM_LIT> )

, <NUM_LIT> ) == NULL_RTX ) return true ;


<s> unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx ; unsigned IncorrectIdx = CorrectIdx ? - <NUM_LIT> : FirstNonZeroIdx ; unsigned IncorrectDst = CorrectIdx ? - <NUM_LIT> : FirstNonZeroDst ; for ( unsigned Idx = FirstNonZeroIdx + <NUM_LIT> ; Idx < NumElems ; ++ Idx ) { SDValue Elem = Op . getOperand ( Idx ) ; if ( Elem . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Elem ) ) continue ; if ( Elem . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Elem . getOperand ( <NUM_LIT> ) != V ) return SDValue ( ) ; unsigned Dst = cast < ConstantSDNode > ( Elem . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Dst == Idx ) ++ CorrectIdx ; else if ( IncorrectIdx == - <NUM_LIT> ) { IncorrectIdx = Idx ; IncorrectDst = Dst ; } else return SDValue (


<s> void Emitter < CodeEmitter > :: emitPseudoInstruction ( const MachineInstr & MI ) { unsigned Opcode = MI . getDesc ( ) . Opcode ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetInstrInfo :: INLINEASM : { if ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) [ <NUM_LIT> ] ) { llvm_report_error ( <STR_LIT> ) ; } break ; } case TargetInstrInfo :: DBG_LABEL : case TargetInstrInfo :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case TargetInstrInfo :: IMPLICIT_DEF : case TargetInstrInfo :: DECLARE : case <STR_LIT> : break ; case <STR_LIT> : emitConstPoolInstruction (


<s> unsigned Opc = I -> second . first ; unsigned Index = I -> second . second & TB_INDEX_MASK ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; const MCInstrDesc & MCID = get ( Opc ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = getRegClass ( MCID , Index , & RI , MF ) ; unsigned NumDefs = MCID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUnalignedMemAccessFast ( ) ) return false ; unsigned Alignment = RC -> getSize ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = ( * MMOs . first ) && (

* MMOs . first ) -> getAlignment ( ) >= Alignment ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler ::


<s> } fprintf ( stderr , <STR_LIT> , ( ( current_function_decl && DECL_NAME ( current_function_decl ) ) ? IDENTIFIER_POINTER ( DECL_NAME ( current_function_decl ) ) : <STR_LIT> ) ) ; fprintf ( stderr , <STR_LIT> , info -> total_size ) ; fprintf ( stderr , <STR_LIT> , info -> pretend_size ) ; fprintf ( stderr , <STR_LIT> , info -> args_size ) ; fprintf ( stderr , <STR_LIT> , info -> extra_size ) ; fprintf ( stderr , <STR_LIT> , info -> reg_size ) ; fprintf ( stderr , <STR_LIT> , info -> var_size ) ; fprintf ( stderr , <STR_LIT> , info -> frame_size ) ; fprintf ( stderr , <STR_LIT> , info -> reg_mask ) ; fprintf ( stderr , <STR_LIT> , info -> save_fp ) ; fprintf ( stderr , <STR_LIT> , info -> save_lr ) ; fprintf ( stderr , <STR_LIT> , info -> initialized ) ; fprintf ( stderr , <STR_LIT> ) ; for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) if ( ( <NUM_LIT> << regno ) & info -> reg_mask

) fprintf ( stderr , <STR_LIT> , reg_names [ regno ] ) ;


<s> return __builtin_mve_vmulq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) ,


<s> if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = loongarch_first_stack_step ( frame ) ; step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { loongarch_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! IMM12_OPERAND ( step1 ) ) { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = LARCH_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } loongarch_for_each_saved_reg ( frame -> total_size -


<s> return new <ISA_LIT>TargetStreamer ( S


<s> } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; Register UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; Register DefReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << DefIdx << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( DefReg ) ) { int UseIdx = SwapMap [ & UseMI ] ; if ( SwapVector [ UseIdx ] . VSEMI -> getOpcode ( ) != MI -> getOpcode ( ) ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; LLVM_DEBUG ( dbgs ( )


<s> SMLoc Loc = Parser . getTok ( ) . getLoc ( ) , EndLoc ; const MCExpr * Expr = nullptr ; unsigned Reg = <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( Parser . parseExpression ( Expr , EndLoc ) ) return true ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Expr = nullptr ; Reg = RE -> getRegNo ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) return Error ( Loc , <STR_LIT> , SMRange ( Loc , EndLoc ) ) ; if ( Reg == <STR_LIT> ) return Error ( Loc , <STR_LIT> , SMRange ( Loc , EndLoc ) ) ; if ( ! Parser . parseOptionalToken ( AsmToken :: Colon ) ) { Operands . push_back ( <STR_LIT> ( Reg , Loc , EndLoc ) ) ; return false ; } if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) return Error ( Loc , <STR_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: Star ) ) Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; } } return ParseMemOperand ( Reg , Expr , Loc , EndLoc ,


<s> assert ( InstMaskEnd >= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskStart - <NUM_LIT> ) , getI32Imm ( InstMaskEnd - <NUM_LIT> ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskStart ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskStart == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskEnd ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskStart ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2


<s> AM . Scale = Mgs -> getValue ( ) . getScalarValueSizeInBits ( ) / <NUM_LIT> ; unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( isa < ConstantSDNode > ( N ) ) { assert ( cast < ConstantSDNode > ( N


<s> assert ( ( Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind ==

k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR ) && <STR_LIT> ) ;


<s> } if ( opts -> x_nopcrelative_literal_loads == <NUM_LIT> ) aarch64_nopcrelative_literal_loads = false ; if ( opts -> x_nopcrelative_literal_loads == <NUM_LIT> && ! TARGET_FIX_ERR_A53_843419 ) aarch64_nopcrelative_literal_loads = true ; if ( opts -> x_nopcrelative_literal_loads && ( aarch64_cmodel == AARCH64_CMODEL_TINY || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC ) ) aarch64_nopcrelative_literal_loads


<s> static inline bool getAM6WBFlag ( unsigned Mode ) { return Mode &


<s> unsigned OpcA = FirstMI . getOpcode ( ) ; unsigned OpcB = MI . getOpcode ( ) ; if ( OpcA == OpcB ) return ! <ISA_LIT>InstrInfo :: isPreLdSt ( FirstMI ) ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) { Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) OpcA


<s> } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { emitWordLE ( Binary | getMachineSoRegOpValue ( MI , MCID , MO , OpIdx ) ) ; return ; } if ( MO . isReg ( ) ) { emitWordLE ( Binary | get<ISA_LIT>RegisterNumbering ( MO . getReg ( )


<s> <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ; <ISA_LIT>StackPtr = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; TD = getDataLayout ( ) ; resetOperationActions (


<s> return Reg == <STR_LIT> || Reg == <STR_LIT> || Reg ==


<s> int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject (


<s> int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasDSP ( ) ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ; if ( SYSmvalue < <NUM_LIT> ) return SYSmvalue | Mask


<s> else progname ++ ; sprintf ( buf , <STR_LIT> , profdir , ( long ) getpid ( ) , progname ) ; proffile = buf ; } else { proffile = <STR_LIT> ; } fd = creat ( proffile , <NUM_LIT> ) ; if ( fd < <NUM_LIT> ) { perror ( proffile ) ; return ; } fprintf ( stderr , <STR_LIT> , sbuf , ssiz ) ; write ( fd , sbuf , ssiz ) ; endfrom = s_textsize / ( HASHFRACTION * sizeof ( * froms ) ) ; for ( fromindex = <NUM_LIT> ; fromindex < endfrom ; fromindex ++ ) { if ( froms [ fromindex ] == <NUM_LIT> ) { continue ; } frompc = s_lowpc + ( fromindex * HASHFRACTION * sizeof (


<s> return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PRE_DEC && XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == stack_pointer_rtx ) ; case 'S' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && xstormy16_legitimate_address_p ( VOIDmode , XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; case 'T' : return <NUM_LIT> ; case 'U' : return ( GET_CODE ( x ) == CONST_INT && ( INTVAL ( x ) < <NUM_LIT> || INTVAL ( x ) > <NUM_LIT> ) ) ; case 'Z' : return ( GET_CODE ( x ) == CONST_INT && ( INTVAL ( x ) == <NUM_LIT> ) ) ; case 'W'


<s> bool hasCustomCheapAsMoveHandling ( )


<s> return ( __m256i ) __builtin_ia32_pmovqd512_mask ( ( __v8di ) __A , ( __v8si )

_mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc DL ; bool isTailCall = false ; bool isInterrupt = false ; bool isTrap = false ; if ( MBB . end ( ) != MI ) { DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; isTrap = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isTrap && STI . hasV5TOps ( ) ) { if ( MBB . succ_empty ( ) ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc


<s> Register InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { updateValueMap ( I , InputReg ) ; return true ; } Register ResultReg = fastEmitInst_extractsubreg ( <STR_LIT>


<s> } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getScalarType ( ) == <STR_LIT> ) { assert ( VT . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> const Function * F = CurDAG -> getMachineFunction ( ) . getFunction ( ) ; OptForSize = F -> hasFnAttr ( Attribute :: OptimizeForSize ) ; DEBUG ( BB -> dump ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) PreprocessForRMW ( ) ; PreprocessForFPConvert ( ) ; DOUT << <STR_LIT> ; Indent = <NUM_LIT> ; SelectRoot ( * CurDAG ) ; DOUT << <STR_LIT> ; CurDAG -> RemoveDeadNodes


<s> bool isToken ( ) const override { return Kind == k_Token


<s> vmovl_high_u16 ( uint16x8_t a ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) :


<s> SDValue NEVec , TransA , TransB , Res , NotOp1 , NotOp0 ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerWithCastAndOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : NEVec = lowerWithCastAndOp ( Op , DAG , <STR_LIT> ) ; return DAG . getNOT ( dl , NEVec , VT ) ; case <STR_LIT> : case <STR_LIT> : NotOp1 = DAG . getNOT ( dl , Op1 , VT ) ; TransA = DAG . getNode ( <STR_LIT> , dl , FullVT , Op0 ) ; TransB = DAG . getNode ( <STR_LIT> , dl , FullVT , NotOp1 ) ; Res = DAG . getNode ( <STR_LIT> , dl , FullVT , TransA , TransB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; case <STR_LIT> : case <STR_LIT> : NotOp0 = DAG . getNOT ( dl , getFullRegister ( Op0 , DAG ) , FullVT ) ; Res = DAG . getNode ( <STR_LIT> , dl , FullVT , NotOp0 , getFullRegister ( Op1 , DAG ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; case <STR_LIT> : case <STR_LIT> : Res = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getCondCode ( <STR_LIT> ) ) ; return DAG . getNOT ( dl , Res , VT ) ; case <STR_LIT> : case <STR_LIT> : Res = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getCondCode ( <STR_LIT> ) ) ; return DAG . getNOT ( dl , Res , VT ) ; } } else if ( VT == <STR_LIT> ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return GENLowerICMP_EQ ( Op , DAG ) ; case <STR_LIT> : return GENLowerICMP_SLT ( Op , DAG ) ; case <STR_LIT> : return GENLowerICMP_SGT ( Op , DAG ) ; case <STR_LIT> : return GENLowerICMP_ULT ( Op , DAG ) ; case <STR_LIT> : return GENLowerICMP_UGT ( Op , DAG ) ; case <STR_LIT> : Res = GENLowerICMP_EQ ( Op , DAG ) ; return b . NOT ( Res ) ; case <STR_LIT> : Res = GENLowerICMP_SLT ( Op , DAG ) ; return b . NOT ( Res ) ; case


<s> static bool ShouldXformToMOVLP ( SDNode * V1 , SDNode * V2 , ShuffleVectorSDNode * Op ) { if ( ! <STR_LIT> ( V1 ) && ! isScalarLoadToVector ( V1 ) ) return false ; if ( <STR_LIT> ( V2 ) ) return false ; unsigned NumElems = Op -> getValueType ( <NUM_LIT>


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue (


<s> static DecodeStatus DecodeDDRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = DDDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return Success


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII . get ( ADDriOpc ) ,

BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; assert ( Subtarget . hasPartwordAtomics ( ) && <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; unsigned dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { if ( const MCSymbolRefExpr * SRE = dyn_cast_or_null < MCSymbolRefExpr > ( Value ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr

:: VK_<ISA_LIT>_SBREL && ! ( Size == <NUM_LIT> ) ) getContext ( ) . reportFatalError ( Loc , <STR_LIT> ) ;


<s> Zeroable [ i ] = ( Elt . isUndef ( ) || <STR_LIT> ( Elt ) ) ; } assert ( Zeroable . size ( ) - Zeroable . count ( ) > <NUM_LIT> && <STR_LIT> ) ; SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op -> getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ]


<s> switch ( Type ) { default : return true ; case ELF ::


<s> len = strlen ( templ ) ; return ( strncmp ( section , templ , len ) == <NUM_LIT> && ( section [ len ]


<s> pmuluw ( uint32x2_t s , uint32x2_t t ) { return __builtin_loongson_pmuluw ( s , t


<s> else after = expand_simple_binop ( mode , code , before , val , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_store_conditional ( mode , mem , after ) ; emit_unlikely_jump ( EQ , label ) ; if ( orig_before ) emit_move_insn ( orig_before , before ) ; if ( orig_after ) emit_move_insn ( orig_after ,


<s> static inline unsigned getCCValues ( unsigned int Flags ) { return ( Flags & CCValuesMask ) >>


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> if ( mips_macc_chains_last_hilo != <NUM_LIT> ) for ( i = nready - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( mips_linked_madd_p ( mips_macc_chains_last_hilo , ready [ i ] ) ) { for ( j = nready - <NUM_LIT> ; j > i ; j -- ) if ( recog_memoized ( ready [ j ]

) >= <NUM_LIT> && get_attr_may_clobber_hilo ( ready [ j ] ) ) {


<s> static SDValue performORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Enable<ISA_LIT>ExtrGeneration ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue Res = tryCombineToEXTR (


<s> virtual const char * getPassName ( ) const { return


<s> V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = Mask . size ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { V2 =


<s> MCSymbol * & TOCEntry = TOC [ Sym ] ; while ( ! TOCEntry ) { if ( OutContext . LookupSymbol ( Twine ( DL -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( TOCLabelID ++ ) ) == nullptr ) { TOCEntry = GetTempSymbol ( <STR_LIT> , TOCLabelID


<s> DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM12 . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM12 . BaseType == <STR_LIT> ) { if ( ! AM12 . Base . Reg . getNode ( ) ) AM12 . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } assert ( AM12 . IndexReg . getNode ( ) == <NUM_LIT> && <STR_LIT> ) ; getAddressOperandsRI ( AM12 , Base , Disp


<s> bool <ISA_LIT>AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { if ( ! parseAuthExpr ( Res , EndLoc ) ) return false ; return getParser ( ) . parsePrimaryExpr ( Res ,


<s> void Initialize ( MCContext & Ctx , const TargetMachine & TM ) override { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects (


<s> static inline bool isGVStub ( GlobalValue * GV , <ISA_LIT>TargetMachine & TM ) { return TM . getSubtarget < <ISA_LIT>Subtarget > ( ) .

GVRequiresExtraLoad ( GV , TM , false ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < <STR_LIT> > SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX512 ( ) ) { int Idx = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX512CostTbl [ Idx ] . Cost ; } if ( ST -> hasAVX2 ( ) ) { int Idx = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX2CostTbl [ Idx ] . Cost ; } if ( ST -> hasAVX ( ) ) { int Idx = CostTableLookup ( AVX1CostTbl , ISD ,


<s> return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT>


<s> MCTargetStreamer & TS = * getParser ( ) . getStreamer ( )


<s> void <ISA_LIT>TargetAsmStreamer :: emit<ISA_LIT>WinCFISaveSP ( unsigned Reg


<s> static __inline unsigned long long sh_media_MSHALDS_W ( unsigned long long mm , unsigned int mn ) { typedef float v4hi __attribute__ ( ( mode


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand (

MCOperand :: createReg ( Regs [ i ] ) ) ;


<s> fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'y' && STACK_TOP_P ( x ) ) { fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'w' ) msize = <NUM_LIT> ; else if ( code == 'b' ) msize = <NUM_LIT> ; else if ( code == 'k' ) msize = <NUM_LIT> ; else if ( code == 'q' ) msize = <NUM_LIT> ; else if ( code == 'h' ) msize = <NUM_LIT> ; else if ( code == 'x' ) msize = <NUM_LIT> ; else if ( code == 't' ) msize = <NUM_LIT> ; else if ( code == 'g' ) msize = <NUM_LIT> ; else msize = GET_MODE_SIZE ( GET_MODE ( x ) ) ; regno = REGNO ( x ) ; if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM || regno == FPSR_REG ) { output_operand_lossage ( <STR_LIT> , reg_names [ regno ] ) ; return ; } else if ( regno == FLAGS_REG ) { output_operand_lossage ( <STR_LIT> ) ; return ; } if ( code == 'V' ) { if ( GENERAL_REGNO_P ( regno ) ) msize = GET_MODE_SIZE ( word_mode ) ; else error ( <STR_LIT> ) ; } duplicated = code == 'd' && TARGET_AVX ; switch ( msize ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( GENERAL_REGNO_P ( regno ) && msize > GET_MODE_SIZE ( word_mode ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; case <NUM_LIT> : if ( LEGACY_INT_REGNO_P ( regno ) ) putc ( msize > <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : normal : reg = hi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; if ( ! ANY_QI_REGNO_P ( regno ) ) error ( <STR_LIT> ) ; reg = qi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; reg = qi_high_reg_name [ regno ] ; break ; case <NUM_LIT> : case <NUM_LIT> : if ( SSE_REGNO_P ( regno ) ) { gcc_assert ( ! duplicated ) ; putc ( msize == <NUM_LIT> ? 'y' : 'z' , file ) ; reg = hi_reg_name [ regno ] + <NUM_LIT> ; break ; } goto normal ; default : gcc_unreachable ( ) ; } fputs ( reg ,


<s> MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , NewMBB ) ; return NewMBB


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Index << <STR_LIT> ) ; return CreateReg ( Index , Str , RegKind_Numeric ,


<s> PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( )


<s> virtual const TargetFrameLowering * getFrameLowering (


<s> DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; UseSoftFloat = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false


<s> void addCOP2AsmRegOperands ( MCInst & Inst , unsigned N )


<s> MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr


<s> return create<ISA_LIT>MachObjectWriter ( OS , true , MachO


<s> SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false ,


<s> std :: vector < Constant * > CV ; if ( EltVT == <STR_LIT> ) { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Op .


<s> static bool selectCCOpsAreFMaxCompatible ( SDValue Cmp , SDValue Result ) { if ( Cmp == Result ) return true ; ConstantFPSDNode * CCmp = dyn_cast < ConstantFPSDNode > ( Cmp ) ; ConstantFPSDNode * CResult = dyn_cast < ConstantFPSDNode > ( Result ) ; if ( CCmp && CResult && Cmp . getValueType ( ) == <STR_LIT> && Result . getValueType ( ) == <STR_LIT> ) { bool Lossy ; APFloat CmpVal = CCmp -> getValueAPF ( ) ; CmpVal . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Lossy ) ; return CResult -> getValueAPF ( ) . bitwiseIsEqual ( CmpVal ) ; } return Result -> getOpcode ( ) == <STR_LIT> && Result -> getOperand ( <NUM_LIT> )


<s> MCELFStreamer :: emitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) )


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr


<s> static char buffer [ sizeof ( <STR_LIT> ) + <NUM_LIT> * sizeof ( int ) ] ; poly_int64 offset_value = rtx_to_poly_int64 ( offset ) ; gcc_assert ( aarch64_sve_addvl_addpl_immediate_p ( offset_value ) ) ; int factor = offset_value . coeffs [ <NUM_LIT> ] ; if ( ( factor & <NUM_LIT> ) == <NUM_LIT> ) snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> , factor / <NUM_LIT> ) ; else snprintf ( buffer , sizeof ( buffer ) , <STR_LIT> ,


<s> bool isLittleEndian ( ) const { return isLittle


<s> const char * fmt ; int used = <NUM_LIT> ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( x ) + is_dest ) ) ; return <NUM_LIT> ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( y

) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ;


<s> enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; if ( ! TARGET_ALTIVEC ) return <NUM_LIT> ; mask = rs6000_emit_vector_compare ( rcode , cc_op0 ,


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm12Operand ( const MachineInstr * MI , int OpNum ) { const MachineOperand & MO1 = MI


<s> if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned CondReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; int Imm = <NUM_LIT> ; bool UseImm = false ; bool isNegativeImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; Imm = ( int ) ConstInt -> getValue ( ) . getZExtValue ( ) ; if ( Imm < <NUM_LIT> ) { isNegativeImm = true ; Imm = ~ Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm ) { Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; } unsigned CmpOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CondReg = constrainOperandRegClass ( TII . get ( CmpOpc ) , CondReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> :


<s> for ( tree list = SH_ATTRIBUTES ( func ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( <STR_LIT> , get_attribute_name ( list ) ) ) return true ; return false


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { if ( ! Subtarget -> useConstIslands ( ) ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs (


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) return <STR_LIT> ; return


<s> Defs . set ( <STR_LIT> ) ; } BitVector CallerSavedRegs ( TRI . getNumRegs ( ) , true ) ; CallerSavedRegs . reset ( <STR_LIT> ) ; CallerSavedRegs . reset ( <STR_LIT> ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( MI . getParent ( ) -> getParent ( ) ) ; * R ; ++ R ) for ( MCRegAliasIterator AI ( * R , & TRI , true ) ; AI . isValid

( ) ; ++ AI ) CallerSavedRegs . reset ( * AI ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory


<s> <ISA_LIT>PostLegalizerLoweringInfo ( bool OptSize , bool MinSize ) : CombinerInfo ( true , false , nullptr , true , OptSize , MinSize ) { if ( ! GeneratedRuleCfg . parseCommandLineOption ( ) )


<s> MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressDarwin ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) ++ NumMovwMovt ; unsigned Wrapper = isPositionIndependent ( ) ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo ::

getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> static bool isSequentialOrUndefOrZeroInRange ( ArrayRef < int > Mask , unsigned Pos , unsigned Size , int Low ) { for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i , ++ Low ) if ( ! isUndefOrZero ( Mask [ i ] ) && Mask [ i ] != Low ) return false ; return true


<s> static void checkNeonReplicateArgs ( unsigned FromW , unsigned ToW ) { assert ( ( FromW == <NUM_LIT> || FromW == <NUM_LIT> || FromW == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( ToW == <NUM_LIT> || ToW == <NUM_LIT> || ToW == <NUM_LIT> ) &&


<s> SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode >


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> rval = gen_reg_rtx ( r_mode ) ; } if ( TARGET_LSE ) { if ( reg_overlap_mentioned_p ( rval , oldval ) ) rval = copy_to_mode_reg ( r_mode , oldval ) ; else emit_move_insn ( rval , gen_lowpart ( r_mode , oldval ) ) ; emit_insn ( gen_aarch64_compare_and_swap_lse ( mode , rval , mem , newval , mod_s ) ) ; cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; } else { insn_code code = code_for_aarch64_compare_and_swap ( mode ) ; if ( ! insn_data [ code ] . operand [ <NUM_LIT> ] . predicate ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; emit_insn ( GEN_FCN ( code ) ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; cc_reg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; } if ( r_mode != mode ) rval = gen_lowpart ( mode


<s> } if ( ! ConstantsMatch ) continue ; SDValue Inp = ( i == <NUM_LIT> ) ? Node -> getOperand ( <NUM_LIT> ) : Node -> getOperand ( <NUM_LIT> ) ; SDValue SizeC = DAG . getConstant ( VT . getSizeInBits ( ) , dl , <STR_LIT> ) ; SDValue Index = getIndexFromUnindexedLoad ( Ld ) ; if ( ! Index ) return SDValue ( ) ; Index = DAG . getZExtOrTrunc ( Index , dl , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SizeC , Index ) ; Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ) ; SDValue AllOnes = DAG . getAllOnesConstant ( dl , VT ) ; SDValue LShr = DAG . getNode ( <STR_LIT> , dl , VT , AllOnes , Sub ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Inp , LShr ) ; } } } } return SDValue (


<s> MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , InsertPt -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Count ) ; if ( ! IsDo ) MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) { SmallVector < MachineInstr * , <NUM_LIT> > Killed ; SmallVector < MachineInstr * , <NUM_LIT> > Dead ; if ( auto * Def = RDA -> getReachingMIDef ( Start , Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Killed . push_back ( Def ) ; while ( ! Killed . empty ( ) ) { MachineInstr * Def = Killed . back ( ) ; Killed . pop_back ( ) ; Dead . push_back ( Def ) ; for ( auto & MO : Def -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isKill ( ) ) continue ; MachineInstr * Kill = RDA -> getReachingMIDef ( Def , MO . getReg ( ) ) ; if ( Kill && RDA -> getNumUses ( Kill , MO . getReg ( ) ) == <NUM_LIT> ) Killed . push_back ( Kill ) ; } } for ( auto * MI : Dead


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val


<s> return ( ( vec_int4 ) ( si_rotmi ( ( qword ) ( a )


<s> if ( DEBUG_INSN_P ( insn ) ) return AVX_U128_ANY ; if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { if ( GET_CODE ( XEXP ( link , <NUM_LIT> ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ix86_check_avx_upper_register ( arg ) ) return AVX_U128_DIRTY ; } } bool avx_upper_reg_found = false ; note_stores ( insn , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; if ( avx_upper_reg_found ) return AVX_U128_DIRTY ; const function_abi & abi = insn_callee_abi ( insn ) ; if ( ! hard_reg_set_subset_p ( reg_class_contents [ SSE_REGS ] , abi . mode_clobbers ( V4DImode ) ) ) return AVX_U128_ANY ; return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; if ( ix86_check_avx_upper_register ( dest ) ) { if ( standard_sse_constant_p ( src , GET_MODE ( dest ) ) != <NUM_LIT> ) return AVX_U128_DIRTY ; else return AVX_U128_ANY ; } else { FOR_EACH_SUBRTX ( iter , array , src , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; } return AVX_U128_ANY ; } FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex (

Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ;


<s> void <ISA_LIT>HazardRecognizer :: nextGroup ( ) { if ( CurrGroupSize == <NUM_LIT> ) return ; DEBUG ( dumpCurrGroup ( <STR_LIT> ) ) ; DEBUG ( CurGroupDbg = <STR_LIT> ; ) ; GrpCount ++ ; CurrGroupSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ; if ( CriticalResourceIdx != UINT_MAX && ( ProcResourceCounters [ CriticalResourceIdx

] <= ProcResCostLim ) ) CriticalResourceIdx = UINT_MAX ;


<s> tag_map . traverse < tag_map_t * , avoid_collisions_1 > ( & tag_map ) ; } while ( map_changed


<s> void printlea64mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> static inline unsigned getAM3Opc ( AddrOpc Opc , unsigned char Offset ) { bool isSub = Opc


<s> if ( Reg . Group == RegV ) { Error ( Reg . StartLoc , <STR_LIT> ) ; return true ; } else if ( Reg


<s> static rtx ix86_erase_embedded_rounding ( rtx pat ) { if ( GET_CODE ( pat ) == INSN ) pat = PATTERN ( pat ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; if ( XVECLEN ( pat , <NUM_LIT> ) == <NUM_LIT> ) { rtx p0 = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; rtx p1 = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( p0 ) == SET && GET_CODE ( p1 ) == UNSPEC && XINT ( p1 , <NUM_LIT> ) == UNSPEC_EMBEDDED_ROUNDING ) ; return p0 ; } else { rtx * res = XALLOCAVEC ( rtx , XVECLEN ( pat , <NUM_LIT> ) ) ; int i = <NUM_LIT> ; int j = <NUM_LIT> ; for ( ; i < XVECLEN ( pat , <NUM_LIT> ) ; ++ i ) { rtx elem = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( elem ) != UNSPEC || XINT ( elem , <NUM_LIT> ) != UNSPEC_EMBEDDED_ROUNDING


<s> case MODIFIER_OPCODE : insn -> opcodeModifier = insn -> opcode - insn -> spec -> modifierBase ; return <NUM_LIT> ; case MODIFIER_MODRM : insn -> opcodeModifier = insn -> modRM


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( ! HasNopl ) { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) <NUM_LIT> ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count !=


<s> int <ISA_LIT>ConstantPoolJT :: getExistingMachineCPValue ( MachineConstantPool *


<s> return ( __m128i ) __builtin_ia32_extracti64x2_256_mask ( ( __v4di ) __A , __imm , ( __v2di ) _mm_setzero_di ( ) ,


<s> static inline void desc_mem_stack_f ( unw_word t , unw_word size


<s> __arm_mcrr2 ( const unsigned int __coproc , const unsigned int __opc1 , uint64_t __value , const unsigned int __CRm ) { __builtin_arm_mcrr2 ( __coproc , __opc1 ,


<s> int <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { if ( isa < ScalableVectorType > ( ValTy ) ) return getArithmeticReductionCostSVE ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; if ( IsPairwiseForm ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT .


<s> for ( auto DefMI : List ) { int64_t AddrDispShiftTemp = getAddrDispShift ( MI , MemOpNo , * DefMI , <NUM_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) ) continue ; if ( TII -> getRegClass ( Desc , MemOpNo + <STR_LIT> , TRI , * MF ) != MRI -> getRegClass ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; int DistTemp = calcInstrDist ( * DefMI , MI ) ; assert ( DistTemp != <NUM_LIT> && <STR_LIT> ) ; if ( DistTemp > <NUM_LIT> || BestLEA == nullptr ) { if ( BestLEA != nullptr && ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) && isInt < <NUM_LIT> > ( AddrDispShift ) ) continue ; BestLEA = DefMI ; AddrDispShift = AddrDispShiftTemp ; Dist = DistTemp ; } if ( DistTemp < <NUM_LIT> ) break ; } return BestLEA !=


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> Value * <ISA_LIT>IREmitter :: visitPRELOAD ( const SDNode *


<s> static int getCompactUnwindRegNum ( const unsigned * CURegs , unsigned Reg ) { int Idx = <NUM_LIT> ; for ( ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs


<s> void <ISA_LIT>TargetStreamer :: emitFPU (


<s> static DecodeStatus DecodeVecShiftR32ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm


<s> int getGlobalRegFI ( ) const { return GlobalRegFI


<s> static __inline qword si_shlh ( qword a , qword b ) { vec_ushort8 mask ; mask = ( vec_ushort8 ) vec_sra ( vec_sl ( ( vec_ushort8 ) ( b ) , vec_splat_u16 (

<NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ;


<s> addPass ( create<ISA_LIT>LowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass


<s> break ; case <NUM_LIT> : index = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( in ) return MAX ( ix86_cost -> mmx_load [ index ] , ix86_cost -> mmx_store [ index ] ) ; return in ? ix86_cost -> mmx_load [ index ] : ix86_cost -> mmx_store [ index ] ; } switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : if ( Q_CLASS_P ( regclass ) || TARGET_64BIT ) { if ( ! in ) return ix86_cost -> int_store [ <NUM_LIT> ] ; if ( TARGET_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p ( cfun ) ) cost = ix86_cost -> movzbl_load ; else cost = ix86_cost -> int_load [ <NUM_LIT> ] ; if ( in == <NUM_LIT> ) return MAX ( cost , ix86_cost -> int_store [ <NUM_LIT> ] ) ; return cost ; } else { if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> movzbl_load , ix86_cost -> int_store [ <NUM_LIT> ] + <NUM_LIT> ) ; if ( in ) return ix86_cost -> movzbl_load ; else return ix86_cost -> int_store [ <NUM_LIT> ] + <NUM_LIT> ; } break ; case <NUM_LIT> : if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> int_load [ <NUM_LIT> ] , ix86_cost -> int_store [ <NUM_LIT> ] ) ; return in ? ix86_cost -> int_load [ <NUM_LIT> ] : ix86_cost -> int_store [ <NUM_LIT> ] ; default : if ( mode == TFmode ) mode = XFmode ; if ( in == <NUM_LIT> ) cost = MAX ( ix86_cost -> int_load [ <NUM_LIT> ]


<s> static enum calling_abi ix86_function_abi (


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( The<ISA_LIT>beTarget ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( TheARM64Target


<s> for ( int i = <NUM_LIT> , Size = Mask . size


<s> _Unwind_VRS_Result _Unwind_VRS_Set ( _Unwind_Context * context , _Unwind_VRS_RegClass regclass , _uw regno , _Unwind_VRS_DataRepresentation representation , void * valuep ) { phase1_vrs * vrs = ( phase1_vrs * ) context ; switch ( regclass ) { case _UVRSC_CORE : if ( representation != _UVRSD_UINT32 || regno > <NUM_LIT> ) return _UVRSR_FAILED ; vrs -> core . r [ regno ] = * ( _uw * ) valuep ; return _UVRSR_OK ; case _UVRSC_VFP : case


<s> valist_type = TREE_TYPE ( valist ) ; u = fold_convert ( valist_type , size_in_bytes ( type ) ) ; t = build ( MINUS_EXPR , valist_type , valist , u ) ; u = build_int_cst ( valist_type , ( size > <NUM_LIT> ? - <NUM_LIT> : - <NUM_LIT> ) ) ; t = build ( BIT_AND_EXPR , valist_type , t , u ) ; t = build ( MODIFY_EXPR , valist_type , valist , t ) ; ofs = ( <NUM_LIT> - size ) % <NUM_LIT> ; if ( ofs != <NUM_LIT> ) { u = fold_convert ( valist_type , size_int ( ofs ) ) ; t = build ( PLUS_EXPR , valist_type , t , u ) ; } t = fold_convert ( ptr , t ) ; t = build_va_arg_indirect_ref ( t ) ; if ( indirect ) t =


<s> Reserved . set ( <STR_LIT> ) ; if ( hasStackRealignment ( MF ) && MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( MCPhysReg Reg : <STR_LIT> ) Reserved . set ( Reg ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved


<s> if ( ( byte1 & <NUM_LIT> ) == <NUM_LIT> && ytreg == <NUM_LIT> ) UNW_DEC_RESTORE ( X2 , t , abreg , arg ) ; else UNW_DEC_SPILL_REG ( X2 , t , abreg , x , ytreg , arg ) ; return


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addFrameIndex ( FI ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addMemOperand


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( )

) return M . getFunction ( <STR_LIT> ) ;


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset =


<s> fprintf ( stream , <STR_LIT> , align / BITS_PER_UNIT ) ; fprintf ( stream , <STR_LIT> , LOCAL_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT>


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( )


<s> return ( __mmask16 ) __builtin_ia32_cmpb128_mask ( ( __v16qi ) __X , (


<s> machine_mode mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode


<s> return rotr32 ( <NUM_LIT> , getSOImmValRotate ( V


<s> assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExtendInVecOpc = getOpcode_EXTEND_VECTOR_INREG ( Opc ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( ExtendInVecOpc , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( ExtendInVecOpc


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo


<s> return SupportedVectorShiftWithImm ( VT ,


<s> OperandMatchResultTy parseBDVAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands ,


<s> void <ISA_LIT>AsmPrinter :: printThumbS4ImmOperand ( const MachineInstr *


<s> case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm !=


<s> int LROffset = <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , true ) ; FI -> setReturnAddrSaveIndex ( RASI ) ; } return DAG . getFrameIndex ( RASI , PtrVT


<s> SDValue X = SetCC -> getOperand ( <NUM_LIT> ) ; SDValue Y = SetCC -> getOperand ( <NUM_LIT> ) ; EVT OpVT = X . getValueType ( ) ; unsigned OpSize = OpVT . getSizeInBits ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpSize < <NUM_LIT> ) return SDValue ( ) ; bool IsOrXorXorCCZero = isNullConstant ( Y ) && X . getOpcode ( ) == <STR_LIT> && X . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && X . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ; if ( isNullConstant ( Y ) && ! IsOrXorXorCCZero ) return SDValue ( ) ; auto IsVectorBitCastCheap = [ ] ( SDValue X ) { X = peekThroughBitcasts ( X ) ; return isa < ConstantSDNode > ( X ) || X . getValueType ( ) . isVector ( ) || X . getOpcode ( ) == <STR_LIT> ; } ; if ( ( ! IsVectorBitCastCheap ( X ) || ! IsVectorBitCastCheap ( Y ) ) && ! IsOrXorXorCCZero ) return SDValue ( ) ; EVT VT = SetCC -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( SetCC ) ; bool HasAVX = Subtarget . hasAVX ( ) ; if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && HasAVX ) || ( OpSize == <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) ) { bool HasPT = Subtarget . hasSSE41 ( ) ; EVT VecVT = <STR_LIT> ; EVT CmpVT = <STR_LIT> ; if ( OpSize == <NUM_LIT> ) VecVT = CmpVT = <STR_LIT> ; if ( OpSize == <NUM_LIT> ) { if ( Subtarget . hasBWI ( ) ) { VecVT = <STR_LIT> ; CmpVT = <STR_LIT> ; } else


<s> if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOpcode ( ) == <STR_LIT> ? AddrOp . getOperand ( <NUM_LIT> ) : AddrOp ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlign ( FI -> getIndex ( ) ) . value ( ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ; if ( AddrOp . getOpcode ( ) != <STR_LIT> ) return true ; } if ( AddrOp . getOpcode ( ) == <STR_LIT> ) return isIntS16Immediate ( AddrOp . getOperand ( <NUM_LIT> ) , Imm ) && ! ( Imm % Val ) ; return AddrOp . getOpcode (


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DebugLoc = MIB -> getDebugLoc ( ) ; auto Mov0I = BuildMI ( MBB , InsertBefore , DebugLoc , TII . get ( <STR_LIT> ) ) . addDef ( MRI . createVirtualRegister ( & <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov0I , TII , TRI , RBI ) ) return false ; auto LHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RHSReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( LHSReg ) == MRI . getType ( RHSReg ) && MRI . getType ( LHSReg ) . getSizeInBits

( ) == <NUM_LIT> && MRI . getType ( RHSReg ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; } Inst . addOperand ( MCOperand :: CreateReg (


<s> explicit <ISA_LIT>ScalarTargetTransformImpl ( const TargetLowering * TL ) : ScalarTargetTransformImpl ( TL ) , Subtarget ( & TL -> getTargetMachine ( ) .

getSubtarget < <ISA_LIT>Subtarget > ( ) ) { }


<s> if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; if ( ! EnableBasePointer ) return


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = getFrameRegister ( MF ) ; int64_t Offset = ( TFI -> getFrameIndexOffset ( MF , FrameIndex ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII . getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; else { int64_t OldOffset = Offset


<s> unsigned getMemOffsetRegShifted ( ) const { assert ( Mem . OffsetIsReg && <STR_LIT> ) ; return Mem


<s> if ( RegWidth == <NUM_LIT> && Shift > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; case TargetOpcode ::


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target (


<s> virtual const TargetData * getTargetData


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> )


<s> tryParseRegisterOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , bool is64BitReg ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int RegNo =


<s> while ( GET_CODE ( x ) == SUBREG ) x = XEXP ( x , <NUM_LIT> ) ; return GET_CODE ( x ) == REG && GR_REGNO_P (


<s> StringRef <ISA_LIT> = ! <ISA_LIT>Attr . hasAttribute ( Attribute :: None ) ? <ISA_LIT>Attr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( <ISA_LIT> . size ( ) + FS . size ( ) ) ; Key += <ISA_LIT> ; Key += FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , getDataLayoutString ( Triple ( TT ) ) , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , RM , CM , OL ) , TLOF (

createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , TargetABI ( computeTargetABI ( Triple ( TT ) , Options ) ) {


<s> rtx old_reg , new_reg , cmp_reg , ar_ccv , label ; enum insn_code icode ; if ( ( mode == SImode || mode == DImode ) && ( code == PLUS || code == MINUS ) && fetchadd_operand ( val , mode ) ) { if ( code == MINUS ) val = GEN_INT ( - INTVAL ( val ) ) ; if ( ! old_dst ) old_dst = gen_reg_rtx ( mode ) ; switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : emit_insn ( gen_memory_barrier ( ) ) ; case MEMMODEL_RELAXED : case MEMMODEL_ACQUIRE : case MEMMODEL_SYNC_ACQUIRE : case MEMMODEL_CONSUME : if ( mode == SImode ) icode = CODE_FOR_fetchadd_acq_si ; else icode = CODE_FOR_fetchadd_acq_di ; break ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : if ( mode == SImode ) icode = CODE_FOR_fetchadd_rel_si ; else icode = CODE_FOR_fetchadd_rel_di ; break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( is_mm_relaxed ( model ) || is_mm_release ( model ) || MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_binop ( DImode , AND , new_reg , val , NULL_RTX , true , OPTAB_DIRECT ) ; new_reg = expand_simple_unop ( DImode , code , new_reg


<s> machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_ld1rq ( mode , dest , src , ptrue ) ) ; return true


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> } if ( CC == CallingConv :: <ISA_LIT>_FastCall ) return CC_<ISA_LIT>_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_<ISA_LIT>_32_FastCC ; else if ( CC == CallingConv :: GHC )


<s> diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ <NUM_LIT> ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; output_asm_insn ( <STR_LIT> , operands ) ; mode = GET_MODE (


<s> unsigned R12 = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) { int SecondScratchReg = BV . find_next ( * SR1 ) ; if ( SecondScratchReg != - <NUM_LIT> ) *


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( ) , TLInfo ( TM ) , TSInfo ( ) , FrameLowering ( ) { InstrItins = getInstrItineraryForCPU ( CPU


<s> assert ( Op2 . getReg ( ) != <STR_LIT> ) ; Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( Coef ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; } if ( ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) || Op1 . isFI ( ) ) && Op2 . getReg ( ) != <STR_LIT> ) { Ops . push_back ( dwarf :: DW_OP_plus ) ; } } DIExpression :: appendOffset ( Ops , Offset ) ; Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , Ops ) ; return ParamLoadedValue ( * Op , Expr ) ; ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! TRI -> isSuperRegisterEq ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Reg ) ) return None ; return ParamLoadedValue ( MI . getOperand ( <NUM_LIT> ) , Expr ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return describeMOVrrLoadedValue ( MI , Reg , TRI ) ; case <STR_LIT> : { if ( ! TRI -> isSuperRegisterEq ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Reg ) ) return None ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return ParamLoadedValue ( MachineOperand :: CreateImm ( <NUM_LIT> ) , Expr ) ; return None ; } case <STR_LIT> : { if ( ! TRI -> isSubRegisterEq ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Reg ) ) return None ; Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction


<s> return __builtin_loongson_pcmpgtb_s ( s , t


<s> N -> getMask ( M ) ; return :: isMOVLMask ( M , N


<s> if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , MaskConst ) ; SDValue Res = DAG . getBitcast


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU ,

FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW


<s> static __inline int __attribute__ ( ( __always_inline__ ) ) cmse_nonsecure_caller ( void ) { return __builtin_arm_cmse_nonsecure_caller (


<s> if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; assert ( Ret != <NUM_LIT> && <STR_LIT> ) ; return Ret


<s> return LowerToBSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && AsmPieces . size ( ) == <NUM_LIT> && ( AsmPieces [ <NUM_LIT> ] == <STR_LIT> || AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { AsmPieces . clear ( ) ; SplitString ( IA -> getConstraintString ( ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; std :: sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) { return LowerToBSwap ( CI ) ; } } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { SmallVector < StringRef , <NUM_LIT> > Words ; SplitString ( AsmPieces [ <NUM_LIT> ] ,


<s> A = N0 ; } else if ( ( FoldableOp = getFoldableLogicOp ( N0 ) ) ) { A = N1 ; } else return false ; SDValue B = FoldableOp . getOperand ( <NUM_LIT> ) ; SDValue C = FoldableOp . getOperand ( <NUM_LIT> ) ; SDNode * ParentA = N ; SDNode * ParentB = FoldableOp . getNode ( ) ; SDNode * ParentC = FoldableOp . getNode ( ) ; uint8_t TernlogMagicA = <NUM_LIT> ; uint8_t TernlogMagicB = <NUM_LIT> ; uint8_t TernlogMagicC = <NUM_LIT> ; auto PeekThroughNot = [ ] ( SDValue & Op , SDNode * & Parent , uint8_t & Magic ) { if ( Op . getOpcode ( ) == <STR_LIT> && Op . hasOneUse ( ) && <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { Magic = ~ Magic ; Parent = Op . getNode ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } } ; PeekThroughNot ( A , ParentA , TernlogMagicA ) ; PeekThroughNot ( B , ParentB , TernlogMagicB ) ; PeekThroughNot ( C , ParentC , TernlogMagicC ) ; uint8_t Imm ; switch ( FoldableOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Imm = TernlogMagicB & TernlogMagicC ; break ; case <STR_LIT> : Imm = TernlogMagicB | TernlogMagicC ; break ; case <STR_LIT> : Imm = TernlogMagicB ^ TernlogMagicC


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) )