<s> RelocOut . outword ( BR24 . getPackedFields ( ) ) ; ++ NumRelocs ; } Addr -= MR . getMachineCodeOffset ( ) ; Addr >>= <NUM_LIT> ; Addr &= <NUM_LIT> ; Addr <<= <NUM_LIT> ; Addr |= ( SecOut [ MR . getMachineCodeOffset ( ) ] << <NUM_LIT> ) ; Addr |= ( SecOut [ MR . getMachineCodeOffset ( ) + <NUM_LIT> ] & <NUM_LIT> ) ; SecOut . fixword ( Addr , MR . getMachineCodeOffset ( ) ) ; break ; } case <STR_LIT> : { Addr -= MR . getMachineCodeOffset ( ) ; Addr &= <NUM_LIT> ; SecOut . fixhalf ( Addr , MR . getMachineCodeOffset ( ) + <NUM_LIT> ) ; break ; } case <STR_LIT> : { MachORelocation HA16 ( MR . getMachineCodeOffset ( ) , ToIdx , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_HA16 ) ; MachORelocation PAIR ( Addr & <NUM_LIT> , <NUM_LIT> , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_PAIR ) ; NumRelocs = <NUM_LIT> ; RelocOut . outword ( HA16 . getRawAddress ( ) ) ; RelocOut . outword ( HA16 . getPackedFields ( ) ) ; RelocOut . outword ( PAIR . getRawAddress ( ) ) ; RelocOut . outword ( PAIR . getPackedFields ( ) ) ; Addr += <NUM_LIT> ; SecOut . fixhalf ( Addr >> <NUM_LIT> , MR . getMachineCodeOffset ( ) + <NUM_LIT> ) ; break ; } case <STR_LIT> : { MachORelocation LO16 ( MR . getMachineCodeOffset ( ) , ToIdx , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_LO16 ) ; MachORelocation PAIR ( Addr >> <NUM_LIT> , <NUM_LIT> , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_PAIR ) ; NumRelocs = <NUM_LIT> ; RelocOut . outword ( LO16 . getRawAddress ( ) ) ; RelocOut . outword ( LO16 . getPackedFields ( ) ) ; RelocOut . outword ( PAIR . getRawAddress ( ) ) ; RelocOut . outword ( PAIR . getPackedFields ( )


<s> static __inline int __get_cpuid ( unsigned int __leaf , unsigned int * __eax , unsigned int * __ebx , unsigned int * __ecx , unsigned int * __edx ) { unsigned int __ext =


<s> if ( ! isRunOfOnes64 ( Imm64 , MB , ME ) ) return false ; unsigned OnesOnLeft = ME + <NUM_LIT> ; unsigned ZerosInBetween = ( MB - ME + <NUM_LIT> ) & <NUM_LIT> ; Val = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , Loc , <STR_LIT> , Val , getI64Imm ( OnesOnLeft , Loc ) , getI64Imm ( ZerosInBetween , Loc


<s> int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( CONSTANT_P ( recog_data . operand [ i ] ) ) { enum attr_mode mode = get_attr_mode ( insn ) ; gcc_assert ( ! len ) ; if ( shortform && CONST_INT_P ( recog_data . operand [ i ] ) ) { HOST_WIDE_INT ival = INTVAL ( recog_data . operand [ i ] ) ; switch ( mode ) { case MODE_QI : len = <NUM_LIT> ; continue ; case MODE_HI : ival = trunc_int_for_mode ( ival , HImode ) ; break ; case MODE_SI : ival = trunc_int_for_mode ( ival , SImode ) ; break ; default : break ; } if ( IN_RANGE ( ival , - <NUM_LIT> , <NUM_LIT> ) ) { len =


<s> if ( DoDump ) { DEBUG ( errs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << UserOffset << <STR_LIT> << CPEOffset <<

<STR_LIT> << int ( CPEOffset - UserOffset ) << <STR_LIT> << * MI ) ;


<s> if ( CacheLineSize . getNumOccurrences ( ) > <NUM_LIT> ) return CacheLineSize ; unsigned Directive = ST


<s> void <ISA_LIT>InstPrinter :: printFCCOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { llvm_unreachable (


<s> return __builtin_mve_vminvq_sv16qi ( __a ,


<s> return __builtin_ia32_vcvtph2qq512_mask_round ( __A , _mm512_setzero_si512 ( ) , ( __mmask8 ) -


<s> return ( __m64 ) __builtin_arm_wunpckehuh ( (


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false ,


<s> CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( ) , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy (


<s> return __builtin_ia32_aesencwide256kl_u8 ( ( __v2di * ) __A , ( __v2di * ) __B


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; unsigned tmp0 , tmp1 ; if ( Op . getResNo ( ) == <NUM_LIT> && isIntrinsicWithCC ( Op , tmp0 , tmp1 ) ) { Known . Zero . setBitsFrom ( <NUM_LIT> ) ; return ; } EVT VT = Op . getValueType ( ) ; if ( Op . getResNo ( ) != <NUM_LIT> || VT == <STR_LIT> ) return ; assert ( Known . getBitWidth ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; assert ( ( ! VT . isVector ( ) || ( DemandedElts . getBitWidth ( ) == VT . getVectorNumElements ( ) ) ) && <STR_LIT> ) ; unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { bool IsLogical = false ; unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id


<s> return ( int16x8_t ) __builtin_aarch64_saddl2v16qi (


<s> typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MSHALDS_L (


<s> StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = ParseRegisterOperand ( nullptr , <STR_LIT> ) ; EndLoc = Parser . getTok ( ) . getLoc (


<s> if ( operands [ <NUM_LIT> ] == const0_rtx ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) INTVAL ( operands [ <NUM_LIT> ] ) >= <NUM_LIT> ) { int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( unsigned ) ( ~ i ) < <NUM_LIT> ) return <STR_LIT> ; if ( ( unsigned ) i < <NUM_LIT> ) return <STR_LIT> ; if ( i >= - <NUM_LIT> && i < <NUM_LIT> ) return <STR_LIT> ; if ( ( unsigned ) i < <NUM_LIT> ) return <STR_LIT> ; if ( i >= - <NUM_LIT> && i < <NUM_LIT> ) return <STR_LIT> ; } if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; case HImode : if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( i == <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) i < <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) ~ i < <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) i < <NUM_LIT> ) return <STR_LIT> ; } return <STR_LIT> ; case QImode : if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( i == <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) ~ i < <NUM_LIT> ) return <STR_LIT> ; } return <STR_LIT> ; default : gcc_unreachable (


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value


<s> else if ( ( rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 || rs6000_cpu == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; else ret = <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs [ FIRST_FPR_REGNO ] [ mode ] ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost (


<s> static DecodeStatus DecodeCPSInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned imod = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; S = MCDisassembler :: SoftFail ; } return S


<s> if ( x == const0_rtx ) return <NUM_LIT> ; return ( x == CONST0_RTX ( GET_MODE (


<s> U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; BBOffsets [ NewIsland -> getNumber ( ) ] = BBOffsets [ NewMBB -> getNumber ( ) ] ; if ( isThumb && ( BBOffsets [ NewIsland -> getNumber ( ) ] % <NUM_LIT> != <NUM_LIT> || HasInlineAsm ) ) Size += <NUM_LIT> ; BBSizes [ NewIsland -> getNumber ( ) ] += Size ; AdjustBBOffsetsAfter ( NewIsland , Size ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex ( ID ) ; break ; } DEBUG ( errs ( ) << <STR_LIT> << ID << <STR_LIT> << CPI << '\t' << * UserMI ) ; return


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int64_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; int SoImmVal ; if ( offset == INT32_MIN ) { Val = <NUM_LIT> ; SoImmVal = <NUM_LIT> ; } else if ( offset < <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; if ( SoImmVal == - <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; } } else { SoImmVal = <STR_LIT> ( offset ) ; if ( SoImmVal == - <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; } } assert ( SoImmVal != - <NUM_LIT>


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixMulHigh ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { EncodedValue |= <NUM_LIT> <<


<s> if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) IsResolved = false ; if ( IsResolved ) ( void ) adjustFixupValue ( Fixup


<s> LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT> ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( unsigned i = <NUM_LIT> ; i < SplitEVTs . size ( ) ; ++ i ) { ArgInfo CurArgInfo = ArgInfo { VRegs [ i ] , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) } ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; if ( ! splitToValueTypes ( CurArgInfo , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildUnmerge ( Regs , VRegs [ i ] ) ; } ) ) return false ; } <ISA_LIT>OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , RetCC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder ,


<s> assert ( v . size ( ) >= <NUM_LIT> ) ; assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v


<s> CPUser ( MachineInstr * mi , MachineInstr * cpemi , unsigned maxdisp , bool neg , bool soimm ) : MI ( mi ) , CPEMI ( cpemi ) , MaxDisp ( maxdisp ) , NegOk ( neg ) , IsSoImm ( soimm ) { HighWaterMark = CPEMI -> getParent (


<s> lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Instruction * Load = tryCreateIncrementingGatScat ( I , Ptr , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( )


) _MM_SET_ROUNDING_MODE ( unsigned int __mode ) {


<s> MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool ExtendedInMem = VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> && VA . getValVT ( ) . getSizeInBits ( ) != VA . getLocVT ( ) . getSizeInBits ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable , true ) ; return DAG . getFrameIndex ( FI , PtrVT ) ; } EVT ArgVT = Ins [ i ] . ArgVT ; bool ScalarizedAndExtendedVector = ArgVT . isVector ( ) && ! VA . getLocVT ( ) . isVector ( ) && VA . getLocVT ( ) . getSizeInBits ( ) != ArgVT . getScalarSizeInBits ( ) ; if ( Flags . isCopyElisionCandidate ( ) && VA . getLocInfo ( ) != CCValAssign :: Indirect && ! ExtendedInMem && ! ScalarizedAndExtendedVector ) { SDValue PartAddr ; if ( Ins [ i ] . PartOffset == <NUM_LIT> ) { int FI = MFI . CreateFixedObject ( ArgVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , false ) ; PartAddr = DAG . getFrameIndex ( FI , PtrVT ) ; return DAG . getLoad ( ValVT , dl , Chain , PartAddr , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_ASHR || MI . getOpcode ( ) == TargetOpcode :: G_LSHR || MI . getOpcode ( ) == TargetOpcode :: G_SHL ) ; Register AmtReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getIConstantVRegValWithLookThrough ( AmtReg , MRI ) ; if ( ! VRegAndVal ) return true ; int64_t Amount = VRegAndVal -> Value . getSExtValue ( ) ; if ( Amount > <NUM_LIT> ) return


<s> return ( __m64 ) __builtin_ia32_cvtps2pi ( ( __v4sf


<s> O << <STR_LIT> << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> << OffImm ; O << markup (


<s> const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> bool isDarwin ( ) const { return TargetTriple . isMacOSX (


<s> return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op . getOperand (

<NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectArithImmed ( MachineOperand & Root ) const { auto MaybeImmed = getImmedFromMO (


<s> return __builtin_mve_vsubq_n_uv16qi ( __a ,


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType


<s> if ( ! isGPRMem ( ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK ||


<s> assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC || ClassID == VSXRC ) ; if ( ST ->


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB64 ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { return new <ISA_LIT>AsmBackend ( T , TT . getOS (


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const


<s> int first_fp_reg_to_save ( ) { int first_reg ; for ( first_reg = <NUM_LIT> + <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; return first_reg


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode (

) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> return static_cast < MCELFStreamer & > ( Streamer


<s> if ( GET_CODE ( op0 ) == AND && XEXP ( op0 , <NUM_LIT> ) == const1_rtx && ( GET_CODE ( op1 ) == PLUS || ( GET_CODE ( op1 ) == MULT && XEXP ( op1 , <NUM_LIT> ) == const2_rtx ) ) ) return <NUM_LIT> ; if ( GET_CODE ( op0 ) == MULT && XEXP ( op0 , <NUM_LIT> ) == const2_rtx && GET_CODE ( op1 ) == LSHIFTRT && CONST_INT_P ( XEXP ( op1 , <NUM_LIT> ) ) && INTVAL ( XEXP ( op1 , <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; } if ( treg_set_expr ( op1 , SImode ) ) return <NUM_LIT> ; if ( treg_set_expr ( op0 , SImode ) ) return <NUM_LIT> ; } const int cost_scale = GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? <NUM_LIT> : <NUM_LIT> ; if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ==

SUBREG ) return <NUM_LIT> * cost_scale ;


<s> switch ( this -> Subtarget . getDarwinDirective ( ) ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL ,


<s> unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) { unsigned Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost ( CmpOpTy , Dst ) ; if ( Opcode == Instruction :: ZExt ) Cost += NumDstVectors ; return Cost ; } } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) return NumDstVectors ; unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) ) ; unsigned TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) )


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return <NUM_LIT>


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( )


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII .

getCallFrameDestroyOpcode ( ) && InternalAmt ) {


<s> if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return MachineOutlinerInstrType :: Legal ; if ( MI . isCall ( ) ) { const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( M && <STR_LIT> ) ; Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isSymbol ( ) ) { Callee = M -> getFunction ( MOP . getSymbolName ( ) ) ; break ; } else if ( MOP . isGlobal ( ) ) { Callee = M -> getFunction ( MOP . getGlobal ( ) -> getGlobalIdentifier ( ) ) ; break ; } } if ( ! Callee ) return MachineOutlinerInstrType :: Illegal ; if ( Callee -> isVarArg ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( Argument & Arg : Callee -> args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . getType ( ) -> getPointerElementType ( ) -> isAggregateType ( ) ) return MachineOutlinerInstrType :: Illegal ; } if ( Callee -> doesNotAccessMemory ( ) ) return MachineOutlinerInstrType :: Legal ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return MachineOutlinerInstrType :: Illegal ; if ( CalleeMF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getBytesInStackArgArea ( ) != <NUM_LIT> ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } if ( MI . isPosition ( ) )


<s> static uint16_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK2 : \ case TYPE_VK4 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ case TYPE_VK32 : \ case TYPE_VK64 : \ if ( index > <NUM_LIT> ) \ *

valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_BNDR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _BND0 + index ; \ } \ }


<s> assert ( GISel && <STR_LIT> ) ; return GISel -> getCallLowering (


<s> } if ( ! TM ) return true ; const TargetLowering * TLI = TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ; if ( Function * F = CI -> getCalledFunction ( ) ) { unsigned Opcode ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc :: Func Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc :: copysign : case LibFunc :: copysignf : continue ; case LibFunc :: copysignl : return true ; case LibFunc :: fabs : case LibFunc :: fabsf : case LibFunc :: fabsl : continue ; case LibFunc :: sqrt : case LibFunc :: sqrtf : case LibFunc :: sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc :: floor : case LibFunc :: floorf : case LibFunc :: floorl : Opcode = <STR_LIT> ; break ; case LibFunc :: nearbyint : case LibFunc :: nearbyintf : case LibFunc :: nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc


<s> int opcode = MI -> getOpcode ( ) ; const MCInstrDesc & Desc = MI -> getDesc ( ) ; int AddrOffset = <STR_LIT> ( Desc . TSFlags , opcode ) ; if ( AddrOffset >= <NUM_LIT> ) { AddrOffset += <STR_LIT> ( Desc ) ; MachineOperand & p = MI -> getOperand (


<s> if ( ! EHInfo ) report_fatal_error ( <STR_LIT> ) ; auto * FINode = dyn_cast < FrameIndexSDNode > ( RegNode ) ; if ( ! FINode ) report_fatal_error ( <STR_LIT> ) ; EHInfo -> EHRegNodeFrameIndex = FINode


<s> bool isMemUImm12Offset ( ) const { if ( Kind == k_Immediate && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val <


<s> SmallVector < MCInst , <NUM_LIT> > Instructions ; expandInstruction ( Inst , IDLoc , Instructions ) ; for ( unsigned i = <NUM_LIT> ; i < Instructions . size ( ) ; i ++ ) { Out . EmitInstruction ( Instructions [ i ] , getSTI ( ) ) ; } } else { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo !=


<s> static void packCmovGroup ( MachineInstr * First , MachineInstr * Last ) { assert ( <STR_LIT> ( Last -> getOpcode ( ) ) != <STR_LIT> && <STR_LIT> ) ; SmallVector < MachineInstr * , <NUM_LIT> > DBGInstructions ; for ( auto I = First -> getIterator ( ) , E = Last -> getIterator ( ) ; I != E ; I ++ ) { if ( I -> isDebugValue ( ) ) DBGInstructions . push_back


<s> vmul_n_u32 ( uint32x2_t a , uint32_t b ) { uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> bool hasZeroCycleZeroingFPWorkaround (


<s> void <ISA_LIT>HazardRecognizer :: Reset ( ) { LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ITBlockSize =


<s> void addMem512Operands ( MCInst & Inst , unsigned N )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS


<s> const MCSymbolRefExpr * SRE ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; assert ( Kind == MCSymbolRefExpr :: VK_None || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_LO || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_HI ) ; OS << SRE -> getSymbol ( ) ; if ( Offset )


<s> Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( IndxTy -> isVectorTy ( ) ) IndxTy = IndxTy -> getVectorElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int SplitFactor = std :: max ( IdxsLT . first , SrcLT . first ) ; if ( SplitFactor > <NUM_LIT> ) { Type * SplitSrcTy = VectorType :: get ( SrcVTy -> getScalarType ( ) , VF / SplitFactor ) ; return SplitFactor * getGSVectorCost ( Opcode , SplitSrcTy , Ptr


<s> static DecodeStatus DecodeJumpTarget ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( JumpOffset


<s> case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Value ) ; AddValueSymbolsImpl ( BE -> getLHS ( ) , Asm ) ; AddValueSymbolsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr ::


<s> void WinEHStatePass :: insertStateNumberStore ( Value * ParentRegNode , Instruction * IP , int State ) { IRBuilder < > Builder ( IP


<s> if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; bool isDef = GV -> isStrongDefinitionForLinker ( ) ; if ( isPICStyleRIPRel ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return <STR_LIT> ; if ( isTargetDarwin ( ) ) { if ( GV -> hasDefaultVisibility ( ) && ! isDef ) return <STR_LIT> ; } else if ( ! isTargetWin64 ( ) ) { assert ( isTargetELF ( ) && <STR_LIT> ) ; if ( ! GV -> hasLocalLinkage ( ) && GV -> hasDefaultVisibility ( ) ) return <STR_LIT> ; } return <STR_LIT> ; } if ( isPICStyleGOT ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( isPICStyleStubPIC ( ) ) { if ( isDef ) return <STR_LIT> ; if ( ! GV -> hasHiddenVisibility ( ) ) return <STR_LIT> ; if ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) { return <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI ->


<s> return ! getStackProbeSymbolName ( MF ) .


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { assert ( Tp -> isVectorTy ( ) ) ; assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned NumVectors = getNumberOfParts ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT>


<s> static SDValue peekThroughEXTRACT_SUBVECTORs ( SDValue V ) { while ( V . getOpcode ( ) == <STR_LIT> ) V =


<s> static char * rs6000_offload_options ( void )


<s> bool isTargetFTOL ( ) const { return Subtarget -> isTargetKnownWindowsMSVC ( ) && ! Subtarget -> is64Bit


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc (


<s> static bool isFrameLoadOpcode ( int Opcode ) { switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ; } return


<s> void markPhysRegUsed ( unsigned PhysReg ) override { MIB . addDef ( PhysReg , RegState ::


<s> addr = XEXP ( addr , <NUM_LIT> ) ; if ( ! mep_call_address_operand ( addr , VOIDmode ) ) addr = force_reg ( SImode , addr ) ; if ( ! operands [ returns_value + <NUM_LIT> ] ) operands [ returns_value


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand


<s> SMLoc getEndLoc ( ) const { return EndLoc


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm (


<s> MCInstPrinter ( MAI , MII , MRI ) { setAvailableFeatures ( STI .


<s> bool <ISA_LIT>InstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != <STR_LIT> && DefOpc != <STR_LIT> && DefOpc != <STR_LIT> ) return false ; if ( DefMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ) return false ; int32_t ImmVal = ( int32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - <NUM_LIT> ; bool TieOps = false ; switch ( UseOpc ) { case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; default : return


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT>


<s> __builtin_ia32_aor64 ( ( long long * )


<s> return ( ( vec_double2 ) ( si_rotqmbybi ( ( qword ) (


<s> if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return <NUM_LIT> ; return - ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM


<s> static void emitBinary ( MCStreamer & OutStreamer , unsigned Opcode , MCOperand & RS1 , MCOperand & Src2 , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst Inst ; Inst . setOpcode ( Opcode ) ; Inst . addOperand ( RD ) ; Inst . addOperand ( RS1 ) ; Inst . addOperand ( Src2


<s> return ( __m128 ) __builtin_ia32_getexpps128_mask ( ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8


<s> Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Alias , * Mang ) ; OS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOF . getDrectveSection


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |=


<s> return __builtin_mve_vld1q_uv4si ( ( __builtin_neon_si * )


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx ,


<s> if ( F . hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) )


<s> setISALevelAndRevisionFromPredicates ( P ) ; setGPRSizeFromPredicates ( P ) ; setCPR1SizeFromPredicates ( P ) ; setISAExtensionFromPredicates ( P


<s> ix86_tls_symbol = gen_rtx_SYMBOL_REF ( Pmode , ( TARGET_GNU_TLS && ! TARGET_64BIT ) ? <STR_LIT> : <STR_LIT> ) ; } return ix86_tls_symbol


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) { object :: mach :: CPUSubtype<ISA_LIT> CS = StringSwitch < object :: mach :: CPUSubtype<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7F ) . Cases ( <STR_LIT>

, <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7S ) . Default ( object :: mach :: CS<ISA_LIT>_V7 ) ;


<s> MVT ReturnMVT ; if ( Subtarget -> is64Bit ( ) && VT == <STR_LIT> && ExtendKind == <STR_LIT> ) ReturnMVT = <STR_LIT> ; else ReturnMVT = <STR_LIT> ; EVT MinVT = getRegisterType ( Context , ReturnMVT ) ; return VT . bitsLT ( MinVT )


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const <ISA_LIT>TargetLowering & TLI = * static_cast < const <ISA_LIT>TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; unsigned AS = DstPtrInfo . getAddrSpace ( ) ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) , AS ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT>


<s> const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock :: iterator II ( MI ) ; unsigned Fc = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const auto & FGR64RegClass = TRI ->


<s> unsigned getBaseReg ( ) const { return BaseReg


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false


<s> if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant (

RHSC , <STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC , <STR_LIT> ) ;


<s> unsigned CondBit0 = Mask >> <NUM_LIT> & <NUM_LIT> ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O << 't' ; else O


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_Q : OutOps . push_back ( Op ) ; return false ; } return


<s> unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasDSP ( ) && ( FlagsVal & <NUM_LIT> ) ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! has8MSecExt ( ) && ( FlagsVal == <NUM_LIT> || FlagsVal == <NUM_LIT> || ( FlagsVal > <NUM_LIT> && FlagsVal < <NUM_LIT> ) ) ) return MatchOperand_NoMatch ; if ( ! hasV8MMainline ( ) && ( FlagsVal == <NUM_LIT> || FlagsVal == <NUM_LIT> || ( FlagsVal > <NUM_LIT> && FlagsVal <= <NUM_LIT> ) ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCA . setELFHeaderEFlags (


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return &


<s> else if ( It -> killsRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) IsFwdFeederRegKilled = true ; if ( ( & * It ) == & DefMI ) break ; } assert ( ( & * It ) == & DefMI && <STR_LIT> ) ; if ( DefMI . modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) return KillDefMI ; return true


<s> void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; void EmitBasicBlockEnd ( const MachineBasicBlock & MBB ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = nullptr ) ; void printRegisterList ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void EmitStartOfAsmFile ( Module & M ) override ; void EmitEndOfAsmFile ( Module & M ) override ; void PrintDebugValueComment ( const MachineInstr *


<s> default : gcc_unreachable ( ) ; } } else if ( GET_CODE ( src ) == CONST_INT ) { if ( REGNO ( dst ) > <NUM_LIT> ) return <STR_LIT> ; else if ( CSKY_CONST_OK_FOR_N ( INTVAL ( src ) + <NUM_LIT> ) ) return <STR_LIT> ; else if ( CSKY_CONST_OK_FOR_T ( INTVAL ( src ) ) ) return <STR_LIT> ; else if ( csky_shifted_imm8_constant ( INTVAL ( src ) , NULL , NULL ) ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( GET_CODE ( src ) == CONST_DOUBLE && GET_MODE ( src ) == SFmode ) { const REAL_VALUE_TYPE * d ; long l ; d = CONST_DOUBLE_REAL_VALUE ( src ) ; REAL_VALUE_TO_TARGET_SINGLE ( * d , l ) ; operands [ <NUM_LIT> ] = GEN_INT ( l ) ; src = operands [ <NUM_LIT> ] ; if ( CSKY_CONST_OK_FOR_N ( INTVAL ( src ) + <NUM_LIT> ) ) return <STR_LIT> ; else return


<s> NewMBB -> splice ( NewMBB -> end ( ) , ThisMBB , InsertPoint , ThisMBB -> end ( ) ) ; NewMBB -> transferSuccessors ( ThisMBB ) ; if ( ! ProbOrigTarget . isUnknown ( ) ) { auto MBBI = find ( NewMBB -> successors ( ) , OrigTarget ) ; NewMBB -> setSuccProbability ( MBBI , ProbOrigTarget ) ; MBBI = find ( NewMBB -> successors ( ) , OrigFallThrough ) ; NewMBB -> setSuccProbability ( MBBI , ProbOrigFallThrough ) ; } ThisMBB -> addSuccessor ( NewBRTarget , ProbToNewTarget ) ; ThisMBB -> addSuccessor ( NewMBB , ProbFallThrough ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( NewBROpcode ) ) . addReg ( BSI . SplitCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewBRTarget ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewMBB ) ; if ( BSI . MIToDelete ) BSI . MIToDelete -> eraseFromParent ( ) ; auto FirstTerminator = NewMBB -> getFirstTerminator ( ) ; if ( BSI . NewCond ) { assert ( FirstTerminator -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; FirstTerminator -> getOperand ( <NUM_LIT> ) . setReg ( BSI . NewCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( BSI . InvertOrigBranch ) FirstTerminator -> setDesc ( TII -> get ( InvertedOpcode ) ) ; for ( auto * Succ : NewMBB -> successors ( ) ) { updatePHIs ( Succ , ThisMBB , NewMBB , MRI ) ; } addIncomingValuesToPHIs ( NewBRTarget , ThisMBB , NewMBB , MRI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ThisMBB -> dump (


<s> int Offset = getLdStOffsetOp ( MI ) . getImm ( ) ; int OffsetStride = IsUnscaled ? TII -> getMemScale ( MI ) : <NUM_LIT> ; if ( Offset > <NUM_LIT> ) Offset -= OffsetStride ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , LdStLimit , false ) ; if ( Paired != E


<s> char * orig = curr_feature_string ; int i ; do { bool clear = false ; next_feature_string = strchr ( curr_feature_string , ',' ) ; if ( next_feature_string ) * next_feature_string ++ = '\0' ; if ( * curr_feature_string == '^' ) { curr_feature_string ++ ; clear = true ; } for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; i ++ ) { if ( ! strcmp ( curr_feature_string , ix86_tune_feature_names [ i


<s> if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - <NUM_LIT> ; sign = REAL_VALUE_NEGATIVE ( r ) ? <NUM_LIT> : <NUM_LIT> ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT> ) ; if ( mantissa != <NUM_LIT> ) return - <NUM_LIT> ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) )


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> )


<s> return ( int16_t ) __builtin_aarch64_sqrdmulhhi (


<s> static bool isAllActivePredicate ( SelectionDAG & DAG , SDValue N ) { unsigned NumElts = N . getValueType ( ) . getVectorMinNumElements ( ) ; while ( N . getOpcode ( ) == <STR_LIT> ) { N = N . getOperand ( <NUM_LIT> ) ; if ( N . getValueType ( ) . getVectorMinNumElements ( ) < NumElts ) return false ; } if ( <STR_LIT> ( N . getNode ( )


<s> ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o


<s> return ( __m512i ) __builtin_ia32_vpshld_v32hi ( ( __v32hi )


<s> if ( ! Subtarget -> isThumb1Only ( ) ) return true ; if ( Level == BeforeLegalizeTypes )


<s> unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false ,


<s> return PR_REGNUM_P ( regno ) || regno


<s> unsigned OptimizePICCall :: getCount ( const Value


<s> if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createReg ( Memory


<s> return matchVectorAddressRecursively ( N , AM ,


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_allocate += <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate


<s> switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>InstPrinter :: printVectorListTwo ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O <<


<s> auto InsPt = MachineFunction :: iterator ( MBB ) ; ++ InsPt ; std :: vector < std :: pair < MachineBasicBlock * , unsigned >> TargetMBBs ; const DebugLoc & DL = JTInst -> getDebugLoc ( ) ; MachineOperand Selector = JTInst -> getOperand ( <NUM_LIT> ) ; const GlobalValue * CombinedGlobal = JTInst -> getOperand ( <NUM_LIT> ) . getGlobal ( ) ; auto CmpTarget = [ & ] ( unsigned Target ) { if ( Selector . isReg ( ) ) MBB -> addLiveIn ( Selector . getReg ( ) ) ; BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( CombinedGlobal , JTInst -> getOperand ( <NUM_LIT> + <NUM_LIT> * Target ) . getImm ( ) ) . addReg ( <NUM_LIT> ) ; BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( Selector ) . addReg ( <STR_LIT> ) ; } ; auto CreateMBB = [ & ] ( ) { auto * NewMBB = MF -> CreateMachineBasicBlock ( BB ) ; MBB -> addSuccessor ( NewMBB ) ; if ( ! MBB -> isLiveIn ( <STR_LIT> ) ) MBB -> addLiveIn ( <STR_LIT> ) ; return NewMBB ; } ; auto EmitCondJump = [ & ] ( unsigned CC , MachineBasicBlock * ThenMBB ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ThenMBB ) . addImm ( CC ) ; auto * ElseMBB = CreateMBB ( ) ; MF -> insert ( InsPt , ElseMBB ) ; MBB = ElseMBB ; MBBI = MBB -> end ( ) ; } ; auto EmitCondJumpTarget = [ & ] ( unsigned CC , unsigned Target ) { auto * ThenMBB = CreateMBB ( ) ; TargetMBBs . push_back ( { ThenMBB , Target } ) ; EmitCondJump ( CC , ThenMBB ) ; } ; auto EmitTailCall = [ & ] ( unsigned Target ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( JTInst -> getOperand ( <NUM_LIT> + <NUM_LIT> * Target ) ) ; } ; std :: function < void ( unsigned , unsigned ) > EmitBranchFunnel = [ & ] ( unsigned FirstTarget , unsigned NumTargets ) { if ( NumTargets == <NUM_LIT> ) { EmitTailCall ( FirstTarget ) ; return ; } if ( NumTargets == <NUM_LIT> ) { CmpTarget ( FirstTarget + <NUM_LIT>


<s> const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op .


<s> Inst . Op = FPOInstruction :: StackAlloc ; Inst . RegOrOffset = StackAlloc ; CurFPOData -> Instructions . push_back (


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( )


<s> assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset == <NUM_LIT> ) return ; } BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( Offset ) . addImm ( <STR_LIT> ( <STR_LIT> ,


<s> static rtx loongarch_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno , argno ; opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) loongarch_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return loongarch_expand_builtin_insn ( icode , opno


<s> Observer . changingInstr ( MI ) ; auto & GlobalOp = MI . getOperand ( <NUM_LIT> ) ; auto * GV = GlobalOp . getGlobal ( ) ; GlobalOp . ChangeToGA ( GV , Offset , GlobalOp . getTargetFlags ( ) ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewGVDst = MRI . cloneVirtualRegister ( Dst ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( NewGVDst ) ; Observer . changedInstr ( MI ) ; B . buildPtrAdd ( Dst , NewGVDst , B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , - static_cast < int64_t > ( MinOffset ) ) ) ; return true


<s> if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) || <STR_LIT> ( Op ) ) Zeroable [ i ] = true ; else if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { APInt Val = Cst -> getAPIntValue ( ) ; Val = Val . lshr ( ( M % Scale ) * ScalarSizeInBits ) ; Val = Val . getLoBits ( ScalarSizeInBits ) ; Zeroable [ i ] = ( Val == <NUM_LIT> ) ; } else if ( ConstantFPSDNode * Cst = dyn_cast < ConstantFPSDNode > ( Op ) ) { APInt Val = Cst -> getValueAPF ( ) . bitcastToAPInt ( ) ; Val = Val . lshr ( ( M % Scale ) * ScalarSizeInBits ) ; Val = Val . getLoBits ( ScalarSizeInBits ) ; Zeroable [ i ] =


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT>


<s> } if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC =


<s> unsigned V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( Imm ) ) & Imm ; if ( getT2SOImmVal ( V ) != - <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState ArgCCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; ArgCCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; unsigned NumBytes = ArgCCInfo . getNextStackOffset ( ) ; for ( auto & Arg : Outs ) { if ( ! Arg . Flags . isByVal ( ) ) continue ; report_fatal_error ( <STR_LIT> ) ; } Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } } SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } if ( isa < GlobalAddressSDNode > ( Callee )


<s> case <STR_LIT> : Inst . erase ( std :: next ( Inst . begin ( ) ) ) ; Inst . erase ( std :: prev ( Inst . end ( ) ) ) ; Inst . insert ( std :: next ( Inst . begin ( ) ) , MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . insert ( Inst . end ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . erase ( Inst . begin ( ) ) ; Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : Inst . erase ( std :: next ( Inst . begin ( ) ) ) ; Inst . insert ( Inst . end ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : return processLRW ( Inst , IDLoc , Out ) ; case <STR_LIT> : return processJSRI ( Inst , IDLoc , Out ) ; case <STR_LIT> : return processJMPI ( Inst , IDLoc ,


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom


<s> ADefined = true ; AOffs = Target . getConstant ( ) + Layout . getFragmentOffset ( Fragment ) ; } if ( ! Target . getSymB ( ) && ( ! ADefined || Target . getConstant ( ) == <NUM_LIT> || AOffs > <NUM_LIT>

) ) recordRegularRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue , FK ) ;


<s> assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; assert ( Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; switch ( TM . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Default : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ,

Reg ) . addExternalSymbol ( <STR_LIT> ) ;


<s> } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; I -> dropAllReferences ( ) ; Dead . insert ( I ) ; } for ( auto * I : Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; I -> eraseFromParent ( ) ; } for ( auto I : L -> blocks ( ) ) DeleteDeadPHIs ( I ) ; return


<s> shmask . c [ si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b )


<s> return makeArrayRef ( std :: begin ( GPR64ArgRegsWin64 ) , std :: end ( GPR64ArgRegsWin64 ) ) ; } static const MCPhysReg GPR64ArgRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> static inline void helper_clear_thumb_bit ( Relocator :: DWord &


<s> case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return


<s> assert ( Arg . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) ,


<s> default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Reg , T


<s> bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; SmallVector < unsigned , <NUM_LIT> > SrcOperandIds ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT ( ) ) ; Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) ,


<s> if ( VT != SrcOp . getSimpleValueType ( ) ) SrcOp = DAG . getBitcast ( VT , SrcOp ) ; if ( ShiftAmt == <NUM_LIT> ) return SrcOp ; if ( ShiftAmt >= ElementType . getSizeInBits ( ) ) { if ( Opc == <STR_LIT> ) ShiftAmt = ElementType . getSizeInBits ( ) - <NUM_LIT> ; else return DAG . getConstant ( <NUM_LIT> , dl , VT ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; if ( <STR_LIT> ( SrcOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Elts ; unsigned NumElts = SrcOp -> getNumOperands ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg )


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveLocalEntry (


<s> emit_insn ( gen_unspec_volatile_isb ( ) ) ; return target ; case NDS32_BUILTIN_MFSR : return nds32_expand_builtin_reg_ftype_imm ( CODE_FOR_unspec_volatile_mfsr , exp , target ) ; case NDS32_BUILTIN_MFUSR : return nds32_expand_builtin_reg_ftype_imm ( CODE_FOR_unspec_volatile_mfusr , exp , target ) ; case NDS32_BUILTIN_MTSR : return nds32_expand_builtin_null_ftype_reg_imm ( CODE_FOR_unspec_volatile_mtsr , exp , target ) ; case NDS32_BUILTIN_MTUSR : return nds32_expand_builtin_null_ftype_reg_imm ( CODE_FOR_unspec_volatile_mtusr , exp , target ) ; case NDS32_BUILTIN_SETGIE_EN : emit_insn ( gen_unspec_volatile_setgie_en ( ) ) ; return target ; case NDS32_BUILTIN_SETGIE_DIS : emit_insn ( gen_unspec_volatile_setgie_dis ( ) ) ; return target ; default : gcc_unreachable (


<s> static bool SupportedVectorShiftWithImm ( MVT VT , const <ISA_LIT>Subtarget * Subtarget , unsigned Opcode ) { if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . is512BitVector ( ) && ( VT . getScalarSizeInBits ( ) > <NUM_LIT> || Subtarget -> hasBWI ( )


<s> return ( __m128i ) __builtin_ia32_pmullw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; static const unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs - <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( FirstReg + getVectorListStart ( )


<s> InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( <ISA_LIT>Operand * Err = ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return Err ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ) ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT>


<s> unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; shift_mask >>= INTVAL ( shiftop


<s> SDValue Lo = extract128BitVector ( Src , <NUM_LIT> , DAG , dl ) ; SDValue Hi = extract128BitVector ( Src , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT>


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags (


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; const Align PtrAlign = Align ( PtrSize ) ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrAlign ) ) ; MachineInstrBuilder DstPtr ; if ( Alignment > PtrAlign ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Alignment . value ( ) - <NUM_LIT> ) ; auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MIRBuilder . buildPtrMask ( PtrTy , ListTmp , Log2 ( Alignment ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , PtrSize , PtrAlign ) ) ; MI . eraseFromParent ( )


<s> return lowerV4I32VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I8VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; default : llvm_unreachable ( <STR_LIT> )


<s> if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> if ( CI ) return isTypeLegal ( VT ) ? Op : SDValue ( ) ; SDValue InVec = Op . getOperand ( <NUM_LIT> ) ; SDValue InIdx = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned EltBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( NumElts * EltBits < <STR_LIT> ) return SDValue ( ) ; if ( getIntrinsicID ( InIdx . getNode ( ) ) == <STR_LIT> ) { SDValue PopOpnd = InIdx . getOperand ( <NUM_LIT> ) ; if ( PopOpnd . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , PopOpnd , InVec ) ; } if ( isTypeLegal ( VT ) ) return Op ; EVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue SplatIdx = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getZExtOrTrunc ( InIdx , DL , <STR_LIT> ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Seq = DAG . getNode ( <STR_LIT> ,


<s> obstack_grow ( & m_string_obstack , name ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > (


<s> x . q = q ; return ( x . f [ <NUM_LIT>


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; switch ( Feature ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetDsp ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetDspr2 ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetMicro<ISA_LIT> ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>1 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>4 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec . push_back ( DAG . getConstant ( i == DestElt ? <NUM_LIT> : i , BaseVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , MaskVT , & MaskVec [


<s> void <ISA_LIT>InstPrinter :: printCPSIFlag ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; unsigned IFlags = Op . getImm ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) O << <STR_LIT> ( <NUM_LIT> << i ) ; if ( IFlags == <NUM_LIT> ) O


<s> SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Ld ) , { MemOp } ) ; CurDAG -> RemoveDeadNode ( N


<s> FrameReg = getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = BasePtr ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( MFI -> hasVarSizedObjects ( ) && ! hasBasePointer ( MF ) ) ) { FrameReg = getFrameRegister ( MF ) ; return FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = BasePtr ; } else if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = getFrameRegister (


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) : TargetLowering ( TM ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> auto Ty = MRI . getType ( LHS . getReg ( ) ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; bool Is32Bit = Size == <NUM_LIT> ; if ( auto Fns = selectArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectShiftedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS }


<s> to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx new_reg = <NUM_LIT> ; rtx and_mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < and_insns . length ( ) ; i ++ ) { rtx_insn * and_insn = and_insns [ i ] ; rtx and_op = and_ops [ i ] ; rtx and_base = XEXP ( and_op , <NUM_LIT> ) ; if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; } XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( new_reg ) , new_reg , and_mask ) ; SET_SRC ( body ) = mem ; INSN_CODE ( insn )


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; MCSymbol * Sym = Context . getOrCreateSymbol ( Name ) ; const MCSymbolRefExpr * ExprRef = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Context ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( <NUM_LIT> ) ; OS . PushSection ( ) ; OS . SwitchSection ( Sec ) ; OS . EmitValueImpl ( ExprRef , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet = false ; OS . PopSection ( ) ; MCSymbol * CurPCSym = Context . createTempSymbol ( ) ; OS . EmitLabel


<s> if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4 ) && cum -> escapes ) { if ( SCALAR_FLOAT_MODE_P ( mode ) ) { rs6000_passes_float = true ; if ( ( HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT ) && ( FLOAT128_IBM_P ( mode ) || FLOAT128_IEEE_P ( mode ) || ( type != NULL && TYPE_MAIN_VARIANT ( type ) == long_double_type_node ) ) ) rs6000_passes_long_double = true ; } if ( named && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) rs6000_passes_vector = true ; } if ( TARGET_ALTIVEC_ABI && ( ALTIVEC_OR_VSX_VECTOR_MODE ( elt_mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) == <NUM_LIT> ) ) ) { bool stack = false ; if ( USE_ALTIVEC_FOR_ARG_P ( cum , elt_mode , named ) ) { cum -> vregno += n_elts ; if ( ! targetm . calls . split_complex_arg && type && TREE_CODE ( type ) == COMPLEX_TYPE && elt_mode == KCmode ) cum -> vregno ++ ; if ( ! TARGET_ALTIVEC ) error ( <STR_LIT> <STR_LIT> <STR_LIT> , <STR_LIT> ) ; if ( ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_64BIT ) || ( cum -> stdarg && DEFAULT_ABI != ABI_V4 ) ) stack = true ; } else stack = true ; if ( stack ) { int align ; if ( TARGET_32BIT ) align = - ( rs6000_parm_offset ( ) + cum -> words ) & <NUM_LIT> ; else align = cum -> words & <NUM_LIT> ; cum -> words += align + rs6000_arg_size ( mode , type ) ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cum -> words , align ) ; fprintf ( stderr , <STR_LIT> , cum -> nargs_prototype , cum -> prototype , GET_MODE_NAME ( mode ) ) ; } } } else if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( mode , type


<s> bool isFGRAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_FGR && RegIdx


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; bool Unsigned = false ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + <STR_LIT> + Twine ( stackSize ) + <STR_LIT>

+ StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ;


<s> setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , s1 } , WidenScalar ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; } for ( auto Ty : { s1 , s8 , s16 } ) { setAction ( { G_ZEXT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_SEXT , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_ICMP , s1 } ,


<s> MOVType = DestType ; MOVOpcode = DestWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( A64Imms :: isMOVNImm ( DestWidth , BitPat , UImm16 , Shift ) ) { MOVType = DestType ; MOVOpcode = DestWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( DestWidth == <NUM_LIT> && A64Imms :: isMOVNImm ( <NUM_LIT> , BitPat , UImm16 , Shift ) ) { MOVType = <STR_LIT> ; MOVOpcode = <STR_LIT> ; } else if ( A64Imms :: isLogicalImm ( DestWidth , BitPat , LogicalBits ) ) { MOVOpcode = DestWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; uint16_t ZR = DestWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> getMachineNode ( MOVOpcode , dl , DestType , CurDAG -> getRegister ( ZR , DestType ) , CurDAG -> getTargetConstant ( LogicalBits , <STR_LIT> ) ) ; } else { return NULL ; } ResNode = CurDAG -> getMachineNode ( MOVOpcode , dl , MOVType , CurDAG -> getTargetConstant ( UImm16 , <STR_LIT> ) , CurDAG -> getTargetConstant ( Shift , <STR_LIT> ) ) ; if ( MOVType != DestType ) { ResNode = CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) ; } return ResNode


<s> bool isTokenEqual ( StringRef Str ) const { return Kind == k_Token && getToken ( )


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) { initialize<ISA_LIT>DAGToDAGISelPass ( * PassRegistry :: getPassRegistry (


<s> return getSubExpr ( ) -> EvaluateAsRelocatable ( Res ,


<s> const int ZeroMask = <NUM_LIT> ; int V1Idx = M < Size ? M * Scale + i % Scale : ZeroMask ; int V2Idx = M < Size ? ZeroMask : ( M - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } MVT ShufVT = <STR_LIT> ( <STR_LIT> , NumBytes ) ; if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , ShufVT , DAG . getBitcast ( ShufVT , V1 ) , DAG . getBuildVector ( ShufVT , DL , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , ShufVT , DAG . getBitcast ( ShufVT , V2 ) , DAG . getBuildVector ( ShufVT , DL , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode ( <STR_LIT> , DL , ShufVT , V1 ,


<s> return new <ISA_LIT>AsmBackend ( T , TT . getOS ( )


<s> return __builtin_mve_vorrq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) ,


<s> const auto * IVTy = cast < VectorType > ( II . getType ( ) ) ; while ( Cursor ) { const auto * CursorVTy = cast < VectorType > ( Cursor -> getType ( ) ) ; if ( CursorVTy -> getElementCount ( ) . getKnownMinValue ( ) < IVTy -> getElementCount ( ) . getKnownMinValue ( ) ) break ; if ( Cursor -> getType ( ) == IVTy ) EarliestReplacement =


<s> while ( I1 != List . end ( ) ) { MachineInstr & First = * * I1 ; auto I2 = std :: next ( I1 ) ; while ( I2 != List . end ( ) ) { MachineInstr & Last = * * I2 ; int64_t AddrDispShift ; assert ( calcInstrDist ( First , Last ) > <NUM_LIT> && <STR_LIT> ) ; if ( ! isReplaceable ( First , Last , AddrDispShift ) ) { ++ I2 ; continue ; } Register FirstVReg = First . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LastVReg = Last . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto UI = MRI -> use_begin ( LastVReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; if ( MI . isDebugValue ( ) ) { replaceDebugValue ( MI , FirstVReg , AddrDispShift ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; MO . setReg ( FirstVReg ) ; MachineOperand & Op = MI . getOperand ( MemOpNo + <STR_LIT> ) ; if ( Op . isImm ( ) ) Op . setImm ( Op . getImm ( ) + AddrDispShift ) ; else if ( ! Op . isJTI ( ) ) Op . setOffset ( Op . getOffset ( )


<s> auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeSet :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildExtract ( Regs , Offsets , VReg ) ; } ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; Success = handleAssignments ( MIRBuilder , AssignFn , SplitArgs , Handler ) ; } MIRBuilder . insertInstr ( MIB ) ; return Success


<s> void <ISA_LIT>MCCodeEmitter :: EmitByte ( unsigned char C , raw_ostream &


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : CheckCPSRDef = true ; case <STR_LIT> : break ; } if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ; return CheckCPSRDef ? ! definesCPSR ( MI


<s> ComplexRendererFns selectAddrModeUnscaled64 ( MachineOperand & Root ) const { return selectAddrModeUnscaled ( Root ,


<s> while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . getOpcode ( ) == TargetInstrInfo :: INLINEASM ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( EnableRegisterScavenging ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , false , false , true ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetInstrInfo :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get


<s> ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; if ( const char * bzeroEntry = V && V -> isNullValue ( ) ? Subtarget . getBZeroEntry ( ) : nullptr ) { EVT IntPtr = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = DAG . getTargetLoweringInfo ( ) . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT>


<s> rtx arm_gen_load_multiple ( int * regs , int count , rtx basereg , int write_back

, rtx basemem , HOST_WIDE_INT * offsetp ) {