<s> Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue (


<s> return new <ISA_LIT>PassConfig ( this


<s> static bool arm_block_set_unaligned_non_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { unsigned int i ; rtx dst , addr , mem ; rtx val_exp , val_reg , reg ; machine_mode mode ; HOST_WIDE_INT v = value ; gcc_assert ( align == <NUM_LIT> || align == <NUM_LIT> ) ; if ( align == <NUM_LIT> ) v |= ( value << BITS_PER_UNIT ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; val_exp = GEN_INT ( v ) ; if ( ! arm_block_set_non_vect_profit_p ( val_exp , length , align , true , false ) )


<s> auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm


<s> if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( )

|| In64BitMode ) stackAlignment = <NUM_LIT> ;


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return


<s> const char * mips16_set_fcsr_one_only_stub :: get_name ( ) { return


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU ,


<s> unsigned EAX = <NUM_LIT> , EBX = <NUM_LIT> , ECX = <NUM_LIT> , EDX = <NUM_LIT> ; union { unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( <STR_LIT> ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; <STR_LIT> ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT>


<s> case <NUM_LIT> : break ; } unsigned NumOps = Desc -> getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc -> getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; break ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MachineOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , <STR_LIT> + <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return ( uint64x1_t ) { __builtin_aarch64_ashldi ( ( int64_t ) __a


<s> return ( ( vec_uint4 ) ( si_mpyhhau ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c )


<s> return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { bool Writeback = true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) Writeback = false ; } O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT>


<s> int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedCmpVal ) . addReg ( CmpVal ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftedCmpVal ) . addReg ( MaskedCmpVal ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedNewVal ) . addReg ( NewVal ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftedNewVal ) . addReg ( MaskedNewVal ) . addReg ( ShiftAmt ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedOldVal0 ) . addReg ( OldVal )


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( )


<s> bool <ISA_LIT>Subtarget :: useStride4VFPs ( const MachineFunction & MF ) const { return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction ( )


<s> if ( nregs == <NUM_LIT> ) return ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tem = adjust_address_nv ( x , reg_mode , i * GET_MODE_SIZE ( reg_mode ) ) ; if (


<s> int _U_Qfeq ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , <NUM_LIT> )


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> } EVT SignExtSrcVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT SrcMemVT = cast < VTSDNode > ( Src -> getOperand ( MemVTOpNum ) ) -> getVT ( ) ; if ( ( SignExtSrcVT != SrcMemVT ) || ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( DstVT , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < Src -> getNumOperands ( ) ; ++ I ) Ops . push_back ( Src -> getOperand ( I ) ) ; SDValue ExtLoad = DAG . getNode ( NewOpc , SDLoc ( N ) , VTs , Ops ) ; DCI . CombineTo ( N , ExtLoad ) ; DCI . CombineTo ( Src . getNode ( ) , ExtLoad , ExtLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N


<s> const BlockAddress * BA = BASDN -> getBlockAddress ( ) ; if ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ; return getTOCEntry ( DAG , SDLoc ( BASDN ) , true , GA ) ; } unsigned MOHiFlag ,


<s> bool <ISA_LIT>16RegisterInfo :: requiresRegisterScavenging ( const


<s> unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; if ( SrcRegBank != DstRegBank && ( DstSize == <NUM_LIT> && SrcSize == <NUM_LIT> ) ) SrcSize = DstSize = <NUM_LIT> ; return { getMinClassForRegBank ( SrcRegBank , SrcSize , true ) , getMinClassForRegBank


<s> bool isMMX = VT . getSizeInBits ( ) == <NUM_LIT> ; EVT ShVT = isMMX ? <STR_LIT> : <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG .

getConstant ( NumBits , TLI . getShiftAmountTy ( ) ) ) ) ;


<s> if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; if ( MO . getReg ( ) != <STR_LIT> ) continue ; assert ( LiveCPSR && <STR_LIT>


<s> LoadChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( Stride , dl , BasePtr . getValueType ( ) ) ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadChains ) ; SDValue Value = DAG . getBuildVector ( Op . getValueType ( ) , dl , Vals ) ; if ( LN -> isIndexed ( ) ) { SDValue RetOps [ ] = { Value , Vals [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , TF } ; return DAG . getMergeValues ( RetOps , dl ) ; } SDValue RetOps [ ] = { Value , TF } ; return DAG . getMergeValues ( RetOps , dl ) ; } assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LN -> isUnindexed ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > VectElmts , VectElmtChains ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Idx = DAG . getConstant ( i , dl , BasePtr . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType (


<s> Iter Filler :: replaceWithCompactJump ( MachineBasicBlock & MBB , Iter Jump , DebugLoc DL ) { const <ISA_LIT>InstrInfo * TII = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & NewDesc = TII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Jump


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveReg ( unsigned Reg , int Offset ) { assert ( Offset >= <NUM_LIT> && Offset <= <NUM_LIT> && <STR_LIT> ) ; EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveReg ,


<s> return ( int16x8_t ) __builtin_aarch64_sqaddv8hi (


<s> rtx op0 , op1 ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ <NUM_LIT> ] ) , gen_rtx_fmt_ee ( code , GET_MODE ( op0 )

, op0 , op1 ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm8 ( const MCInst & MI , unsigned

Op , SmallVectorImpl < MCFixup > & Fixups ) const {


<s> void EmitARM64WinCFINop ( ) override { OS << <STR_LIT>


<s> if ( ! Match ) continue ; if ( Match . getScalarValueSizeInBits ( ) != BitWidth ) continue ; unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && ( ( Subtarget . hasAVX ( ) && BitWidth >= <NUM_LIT> ) || Subtarget . hasAVX2 ( ) ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( Op == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; APInt ResOnes = APInt :: getAllOnesValue ( ResWidth ) ; APInt ResZero = APInt :: getNullValue ( ResWidth ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , ResWidth ) ; SDLoc DL ( Extract ) ; SDValue Res = DAG . getBitcast ( MaskVT


<s> if ( Subtarget -> hasNEON ( ) && <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && ! cast < LoadSDNode > ( N0 ) -> isVolatile ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> getAlignment ( ) , LN0

-> getMemOperand ( ) -> getFlags ( ) ) ;


<s> <STR_LIT> ExtType = LD -> getExtensionType ( ) ; SDValue Chain = LD -> getChain ( ) , Undef = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) ; if ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) { SDValue LDL = CreateLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return CreateLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = CreateLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = CreateLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT> ) || ( ExtType == <STR_LIT> ) ) return LWR ; assert ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) ; DebugLoc DL = LD -> getDebugLoc ( ) ; SDValue Const32 = DAG . getConstant ( <NUM_LIT> ,


<s> static SDValue PerformAddCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSSE3orAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX2 ( ) && ( VT == <STR_LIT> || <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N , DAG )


<s> if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) && ! Subtarget -> isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs ,


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap


<s> if ( Subtarget -> has<ISA_LIT>32II ( ) ) Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; else { SDNode * StatusWord = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; SDValue Constant1 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , VT ) ; Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( StatusWord , <NUM_LIT> ) , Constant1 ) ; } SDNode * AddCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS


<s> int64_t Disp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register OrigCmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OrigSwapVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register BitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NegBitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned LOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; unsigned CSOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigOldVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register CmpVal = MRI . createVirtualRegister ( RC ) ; Register SwapVal = MRI . createVirtualRegister ( RC ) ; Register StoreVal = MRI . createVirtualRegister ( RC ) ; Register RetryOldVal = MRI . createVirtualRegister ( RC ) ; Register RetryCmpVal = MRI . createVirtualRegister ( RC ) ; Register RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * SetMBB = emitBlockAfter ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB )

. addReg ( RetryOldVal ) . addMBB ( SetMBB ) ;


<s> if ( ! TII -> isStridedAccess ( MI ) ) continue ; Optional < LoadInfo > OptLdI = getLoadInfo ( MI ) ; if ( ! OptLdI ) continue ; LoadInfo LdI = * OptLdI ; Optional < unsigned > OptOldTag = getTag ( TRI , MI , LdI ) ; if ( ! OptOldTag ) continue ; auto & OldCollisions = TagMap [ * OptOldTag ] ; if ( OldCollisions . size ( ) <= <NUM_LIT> ) continue ; bool Fixed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; if ( ! DebugCounter :: shouldExecute ( FixCounter ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; continue ; } for ( unsigned OpI = <NUM_LIT> , OpE = MI . getNumOperands ( ) ; OpI < OpE ; ++ OpI ) { if ( OpI == static_cast < unsigned > ( LdI . BaseRegIdx ) ) continue ; MachineOperand & MO = MI . getOperand ( OpI ) ; if ( MO . isReg ( ) && MO . readsReg ( ) ) LR . addReg ( MO . getReg ( ) ) ; } for ( unsigned ScratchReg : <STR_LIT> ) { if ( ! LR . available ( ScratchReg ) || MRI . isReserved ( ScratchReg ) ) continue ; LoadInfo NewLdI ( LdI ) ; NewLdI . BaseReg = ScratchReg ; unsigned NewTag = * getTag ( TRI , MI , NewLdI ) ; if ( TagMap . count ( NewTag ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( ScratchReg , TRI ) << '\n' ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg


<s> if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_IBT ; if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_SHSTK ; if ( FeatureFlagsAnd ) { if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; emitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> emitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> emitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; emitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT>


<s> Chains . clear ( ) ; for ( const auto & MI : MBB ) { for ( auto r : Chains ) { SmallVector < unsigned , <NUM_LIT> > toDel ; if ( regJustKilledBefore ( LIs , r , MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( r , TRI ) << <STR_LIT> ; MI . print ( dbgs ( ) ) ; ) ; toDel . push_back ( r ) ; } while ( ! toDel . empty ( ) ) { Chains . remove ( toDel . back ( ) ) ; toDel . pop_back ( ) ; } } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case


<s> return ( __m512d ) __builtin_ia32_rcp14pd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_undefined_pd ( )


<s> MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; ArgInfo ArgRetInfo ( VRegs , * Val , <NUM_LIT> ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , RetInfos , DL , F . getCallingConv ( ) ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; std :: string FuncName = F . getName ( ) . str ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( TLI . CCAssignFnForReturn ( ) , FuncName . c_str ( ) ,


<s> if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ( ToEltVT == <STR_LIT> || ToEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> ) return SDValue ( ) ; auto isVMOVNOriginalMask = [ & ] ( ArrayRef < int > M , bool rev ) { unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) || ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ]

!= ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ;


<s> void <ISA_LIT>InstPrinter :: printLabelOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! MO . isImm ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } uint64_t UImm = MO . getImm ( ) ; uint64_t Sign = UImm & ( <NUM_LIT> << ( field_width - <NUM_LIT> ) ) ; int64_t SImm = scale * ( ( UImm & ~ Sign )


<s> do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align


<s> MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( std :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; computeBlockSize ( OrigBB ) ; computeBlockSize ( NewBB ) ; adjustBBOffsetsAfter (


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) )


<s> int64_t maxBwdBranchOffset ( ) const { return MAX_BWD_BRANCH_OFFSET


<s> if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) .


<s> AFI -> setReturnRegsCount ( RVLocs . size ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { const Function & F = MF . getFunction ( ) ; if ( Subtarget . hasQPX ( ) && Size >= <NUM_LIT> && ( ! IsMemset || Size >= <NUM_LIT> ) && ( ! SrcAlign || SrcAlign >= <NUM_LIT> ) && ( ! DstAlign || DstAlign >= <NUM_LIT> ) && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return <STR_LIT> ; } if ( Subtarget . hasAltivec ( ) && Size >= <NUM_LIT> && ( ( ( ! SrcAlign || SrcAlign >= <NUM_LIT> ) && ( ! DstAlign || DstAlign >= <NUM_LIT> ) ) || ( ( IsMemset &&

Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return <STR_LIT> ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && ( FeatureBits [ <STR_LIT> ] ) != <NUM_LIT> ) S = SoftFail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ITBlock . instrInITBlock ( ) && ! ITBlock . instrLastInITBlock ( ) ) S = SoftFail ; break ; default : break ; } if ( ( ! isVectorPredicable ( MI . getOpcode ( ) ) && VPTBlock . instrInVPTBlock ( ) ) || ( isVectorPredicable ( MI . getOpcode ( ) ) && ITBlock . instrInITBlock ( ) ) ) S = SoftFail ; unsigned CC = <STR_LIT> ; unsigned VCC = <STR_LIT> ; if ( ITBlock . instrInITBlock ( ) ) { CC = ITBlock . getITCC ( ) ; ITBlock . advanceITState ( ) ; } else if ( VPTBlock . instrInVPTBlock ( ) ) { VCC = VPTBlock . getVPTPred ( ) ; VPTBlock . advanceVPTState ( ) ; } const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator CCI = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ CCI ) { if ( OpInfo [ i ] . isPredicate ( ) || CCI == MI . end ( ) ) break ; } if ( <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) { CCI = MI . insert ( CCI , MCOperand :: createImm ( CC ) ) ; ++ CCI ; if ( CC == <STR_LIT> ) MI . insert (

CCI , MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> } } else if ( code == IOR || code == XOR ) { if ( value == <NUM_LIT> ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std :: swap ( op1 , op2


<s> virtual void getAnalysisUsage ( AnalysisUsage & Info ) { Info . setPreservesAll (


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; return


<s> std :: pair < StackMaps :: Location , MachineInstr :: const_mop_iterator > <ISA_LIT>AsmPrinter :: stackmapOperandParser ( MachineInstr :: const_mop_iterator MOI , MachineInstr :: const_mop_iterator MOE , const TargetMachine & TM ) { typedef StackMaps :: Location Location ; const MachineOperand & MOP = * MOI ; assert ( ! MOP . isRegMask ( ) && ( ! MOP . isReg ( ) || ! MOP . isImplicit ( ) ) && <STR_LIT> ) ; if ( MOP . isImm ( ) ) { switch ( MOP . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case StackMaps :: DirectMemRefOp : { unsigned Size = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) ; assert ( ( Size % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Size /= <NUM_LIT> ; return parseMemoryOperand ( StackMaps :: Location :: Direct , Size , llvm :: next ( MOI ) , MOE ) ; } case StackMaps :: IndirectMemRefOp : { ++ MOI ; int64_t Size = MOI -> getImm (


<s> } unsigned Align = <NUM_LIT> ; if ( Subtarget -> hasXMM ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> unsigned getMinPrefetchStride ( ) const { return MinPrefetchStride


<s> unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; UpdateValueMap ( I ,


<s> switch ( Subtarget -> getTargetABI ( ) ) { case <ISA_LIT>Subtarget :: O32 : return


<s> break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : Hash = hash_combine ( Hash , Val . Disp -> getIndex ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Hash = hash_combine ( Hash , Val . Disp -> getSymbolName ( ) ) ; break ; case MachineOperand :: MO_GlobalAddress : Hash = hash_combine ( Hash , Val . Disp -> getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : Hash = hash_combine ( Hash , Val . Disp -> getBlockAddress ( ) ) ; break ; case MachineOperand :: MO_MCSymbol : Hash = hash_combine ( Hash , Val . Disp ->


<s> Inst . addOperand ( MCOperand :: createImm ( getCoproc


<s> } else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isIntImmediate ( Add0 , Add0Imm ) && Add0Imm != <NUM_LIT> && ( Add0Imm % Size == <NUM_LIT> ) ) { unsigned NegOpc ; unsigned ZeroReg ; EVT SubVT = ShiftAmt -> getValueType ( <NUM_LIT> ) ; if ( SubVT == <STR_LIT> ) { NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( SubVT == <STR_LIT> ) ; NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , ZeroReg , SubVT ) ; MachineSDNode * Neg = CurDAG -> getMachineNode ( NegOpc , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = SDValue ( Neg , <NUM_LIT> ) ; } else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isIntImmediate ( Add0 , Add0Imm ) && ( Add0Imm % Size == Size - <NUM_LIT> ) ) { unsigned NotOpc ; unsigned ZeroReg ; EVT SubVT = ShiftAmt -> getValueType ( <NUM_LIT> ) ; if ( SubVT == <STR_LIT> ) { NotOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( SubVT == <STR_LIT> ) ; NotOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , ZeroReg , SubVT ) ; MachineSDNode * Not = CurDAG -> getMachineNode ( NotOpc , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = SDValue ( Not , <NUM_LIT> ) ; } else return false ; } else { uint64_t MaskImm ; if ( ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) && ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) ) return false ; if ( countTrailingOnes ( MaskImm ) < Bits ) return false ; NewShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) NewShiftAmt = narrowIfNeeded ( CurDAG , NewShiftAmt ) ; else if ( VT == <STR_LIT> && NewShiftAmt -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; MachineSDNode * Ext = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewShiftAmt , SubReg ) ; NewShiftAmt = SDValue ( Ext , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , NewShiftAmt } ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return


<s> bool <ISA_LIT>AsmParser :: reportParseError ( SMLoc Loc , StringRef ErrorMsg


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd =


<s> aarch64_simd_switcher simd ; for ( unsigned int i = <NUM_LIT> ; i < ARM_NEON_H_TYPES_LAST ; i ++ ) for ( unsigned int count = <NUM_LIT> ; count <= <NUM_LIT> ; ++ count ) if ( ! aarch64_scalar_builtin_type_p ( aarch64_simd_types [ i ] . type ) ) register_tuple_type ( count , i ) ; aarch64_init_simd_builtin_functions ( true


<s> else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MBB != MI . getOperand ( <NUM_LIT> ) .


<s> rtx pat , addr ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = Pmode ; machine_mode mode1 = Pmode ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( icode == CODE_FOR_altivec_lvx_v2df_2op || icode == CODE_FOR_altivec_lvx_v2di_2op || icode == CODE_FOR_altivec_lvx_v4sf_2op || icode == CODE_FOR_altivec_lvx_v4si_2op || icode == CODE_FOR_altivec_lvx_v8hi_2op || icode == CODE_FOR_altivec_lvx_v16qi_2op ) { rtx rawaddr ; if ( op0 == const0_rtx ) rawaddr = op1 ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; rawaddr = gen_rtx_PLUS ( Pmode , op1 , op0 ) ; } addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - <NUM_LIT> ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode :


<s> int width , is_valid ; static char templ [ <NUM_LIT> ] ; is_valid = neon_immediate_valid_for_logic ( * op2 , mode , inverse , op2 , & width ) ; gcc_assert ( is_valid != <NUM_LIT> ) ; if ( quad ) sprintf ( templ , <STR_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ArgsBaseOffset = <NUM_LIT> ; unsigned ArgsPreserved = <NUM_LIT> ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( ArgsPreserved , <NUM_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! IsVarArg )


<s> return __builtin_ia32_comilt ( ( __v4sf ) __A , ( __v4sf )


<s> return ( __m256i ) __builtin_ia32_vplzcntq_256_mask ( ( __v4di ) __A , ( __v4di ) _mm256_setzero_si256 ( ) , ( __mmask8 )


<s> assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg (


<s> bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG .

getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: addTypeForFixedLengthSVE ( MVT VT ) { assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; for ( unsigned Op = <NUM_LIT> ; Op < <STR_LIT> ; ++ Op ) setOperationAction ( Op , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT


<s> static DecodeStatus DecodeF32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> assert ( OpVT == <STR_LIT> || OpVT == <STR_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || ( hasHardQuad && TLI . isTypeLegal ( OpVT ) )

) return SDValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> MVT OpEltVT = OpVT . getVectorElementType ( ) ; unsigned InputBits = OpEltVT . getSizeInBits ( ) * VT . getVectorNumElements ( ) ; SDValue V = Op ; while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V != Op && V . getOpcode ( ) == <STR_LIT> ) { MVT InnerVT = V . getSimpleValueType ( ) ; MVT InnerEltVT = InnerVT . getVectorElementType ( ) ; if ( OpEltVT == InnerEltVT ) { assert ( OpVT == InnerVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V . getOperand ( <NUM_LIT> ) ) ; } if ( InnerEltVT . getSizeInBits ( ) < InputBits ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( OpVT , V ) ) ; } if ( V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) == InputBits ) { SDValue ExtractedV = V . getOperand ( <NUM_LIT> ) ; SDValue OrigV = ExtractedV . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( ExtractedV . getOperand ( <NUM_LIT> ) ) ) { MVT OrigVT = OrigV . getSimpleValueType ( ) ; if ( OrigVT . getSizeInBits ( ) > OpVT


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { StackAlignment = <NUM_LIT> ; DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasAltivec = false ; HasQPX = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX =


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode4 ( SDValue Op , SDValue N , SDValue & Addr , SDValue & Mode ) { Addr = N ; Mode = CurDAG -> getTargetConstant


<s> const FeatureBitset & Features = STI -> getFeatureBits ( ) ; if ( Features [ <STR_LIT> ] ) emitRR ( <STR_LIT> , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; else emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT>


<s> AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID (


<s> NewI . cloneMemRefs ( I ) ; constrainSelectedInstRegOperands ( * NewI , TII , TRI , RBI ) ; break ; } case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) | ( 'U' << <NUM_LIT> ) ) ; break ; case <STR_LIT> : { Register Src1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Src1 ) ; const LLT S8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT P0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; unsigned Opc ; if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , getDataLayoutString ( TT ) , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , getEffectiveRelocModel ( TT , RM ) , getEffective<ISA_LIT>CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , TargetABI ( computeTargetABI ( TT , Options ) ) { initAsmInfo ( )


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations ; }


<s> return ( ( int ) isSub << <NUM_LIT> )


<s> OtherMO = & Use . getOperand ( <NUM_LIT> ) ; } else continue ; auto tryAddHint = [ & ] ( const MachineOperand * MO ) -> void { Register Reg = MO -> getReg ( ) ; Register PhysReg = Register :: isPhysicalRegister ( Reg ) ? Reg : Register ( VRM -> getPhys ( Reg ) ) ; if ( PhysReg ) { if ( MO -> getSubReg ( ) ) PhysReg = getSubReg ( PhysReg , MO -> getSubReg ( ) ) ; if ( VRRegMO -> getSubReg ( ) ) PhysReg = getMatchingSuperReg ( PhysReg , VRRegMO -> getSubReg ( ) , MRI -> getRegClass ( VirtReg ) ) ; if ( ! MRI -> isReserved ( PhysReg ) && ! is_contained ( Hints , PhysReg ) ) TwoAddrHints . insert ( PhysReg ) ; } } ; tryAddHint ( OtherMO ) ; if ( CommuMO ) tryAddHint ( CommuMO ) ; } for ( MCPhysReg OrderReg : Order ) if ( TwoAddrHints . count ( OrderReg ) ) Hints . push_back ( OrderReg ) ; } if ( MRI -> getRegClass ( VirtReg ) == & <STR_LIT> ) { SmallVector < Register , <NUM_LIT> > Worklist ; SmallSet < Register , <NUM_LIT> > DoneRegs ; Worklist . push_back ( VirtReg ) ; while ( Worklist . size ( ) ) { Register Reg = Worklist . pop_back_val ( ) ; if ( ! DoneRegs . insert ( Reg ) . second ) continue ; for ( auto & Use : MRI -> reg_instructions ( Reg ) ) { if ( Use . getOpcode ( ) == <STR_LIT> || Use . getOpcode ( ) == <STR_LIT> ) { MachineOperand & TrueMO = Use . getOperand ( <NUM_LIT> ) ; MachineOperand & FalseMO = Use . getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = TRI -> getCommonSubClass ( getRC32 ( FalseMO , VRM , MRI ) , getRC32 ( TrueMO , VRM , MRI ) ) ; if ( Use . getOpcode ( ) == <STR_LIT> ) RC = TRI -> getCommonSubClass ( RC , getRC32 ( Use . getOperand ( <NUM_LIT> ) , VRM , MRI ) ) ; if ( RC && RC != & <STR_LIT> ) { addHints ( Order , Hints , RC , MRI ) ; return true ; } Register OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg


<s> for ( SDNode * N : GN -> uses ( ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; MinOffset = std :: min ( MinOffset , C -> getZExtValue ( ) ) ; } uint64_t Offset = MinOffset + GN


<s> static int iq2000_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - <NUM_LIT> ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT>


<s> if ( MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT || MI . getOpcode ( ) == TargetOpcode :: STATEPOINT ) { StackOffset Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true , false ) ; Offset += StackOffset :: getFixed ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; return ; } if ( MI . getOpcode ( ) == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; StackOffset Offset = TFI -> getNonLocalFrameIndexReference ( MF , FrameIndex ) ; assert ( ! Offset . getScalable ( ) && <STR_LIT> ) ; FI . ChangeToImmediate ( Offset . getFixed ( ) ) ; return ; } StackOffset Offset ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) ) ; } else if ( Tagged ) { StackOffset SPOffset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) ) ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) ) ; } else { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; } if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; Register ScratchReg = createScratchRegisterForInstruction ( MI , FIOperandNum , TII ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg


<s> LLT ValTy = MRI . getType ( Dst ) ; uint64_t ValSize = ValTy . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValTy , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , PtrTy , PtrAlign ) ) ; MI . eraseFromParent (


<s> SDValue CompareOps [ ] = { LHS , RHS , Chain } ; SDNode * Compare = CurDAG -> getMachineNode ( <STR_LIT> , N , CompareVT , CompareOps ) ; CondCodeSDNode * CC = cast < CondCodeSDNode > ( Cond . getNode ( ) ) ; SDValue CCVal = CurDAG -> getTargetConstant ( CC ->


<s> bool is64Bit = T . getArch ( ) == Triple :: ppc64 || T . getArch ( ) == Triple :: ppc64le ; std :: string Ret ; if ( isLittleEndianTriple ( T ) ) Ret = <STR_LIT> ; else Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( T ) ; if ( ! is64Bit || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( is64Bit && ( T . isOSAIX ( ) || T . isOSLinux ( ) ) ) Ret += <STR_LIT> ; return


<s> unsigned int alignment = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; return


<s> AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( getPointerWidth ( ) , SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo ,


<s> emit_insn ( gen_load_toc_v4_PIC_1 ( lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_3b ( tmp2 , tmp1 , got , lab ) ) ; emit_insn ( gen_load_toc_v4_PIC_3c ( dest , tmp2 , got , lab ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { emit_insn ( gen_load_toc_v4_pic_si ( ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_insn ( gen_load_toc_v4_PIC_1 ( symF ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest , symL , symF ) ) ; } else { rtx tocsym , lab ; tocsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( toc_label_name ) ) ; need_toc_init = <NUM_LIT> ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( tocsym , lab ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( dest , dest , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , dest ) ) ; } emit_insn ( gen_addsi3 ( dest , temp0 , dest )


<s> inline vector signed short vec_madds ( vector signed short a1 , vector signed short a2


<s> MCSection * <ISA_LIT>MCAsmInfo :: getNonexecutableStackSection ( MCContext &


<s> if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == TargetOpcode :: COPY_TO_REGCLASS ) return ; printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> )

. isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {


<s> SDValue Ops [ ] = { Opd0 , Opd1 , CurDAG -> getTargetConstant ( LSB , dl , VT ) , CurDAG -> getTargetConstant ( MSB , dl , VT ) } ; return CurDAG -> SelectNodeTo ( N , Opc , VT ,


<s> else { unsigned pair_idx = <NUM_LIT> , lone_idx = <NUM_LIT> , shift ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ( d -> perm [ i ] > <NUM_LIT> && count == <NUM_LIT> ) || ( d -> perm [ i ] < <NUM_LIT> && count == <NUM_LIT> ) ) lone_idx = i ; gcc_assert ( count == ( lone_idx ? <NUM_LIT> : <NUM_LIT> ) ) ; shift = lone_idx & <NUM_LIT> ; pair_idx = <NUM_LIT> - lone_idx + <NUM_LIT> * shift ; perm1 [ <NUM_LIT> ] = perm1 [ <NUM_LIT> ] = ( count == <NUM_LIT> ) ? d -> perm [ lone_idx ] : d -> perm [ lone_idx ] - <NUM_LIT> ; perm1 [ <NUM_LIT> ] = perm1 [ <NUM_LIT> ] = ( count == <NUM_LIT> ) ? d -> perm [ pair_idx ] : d -> perm [ pair_idx ] + <NUM_LIT> ; if ( count == <NUM_LIT> ) std :: swap ( d -> op0 , d -> op1 ) ; ok = expand_vselect_vconcat ( tmp , d -> op0 , d -> op1 , perm1 , d -> nelt , false ) ; gcc_assert ( ok


<s> Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; if ( VT == <STR_LIT> ) Addr


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FeatureDummy ( false ) { ParseSubtargetFeatures ( CPU , CPU


<s> return ( uint16x4_t ) ( vabs_f16 ( __a ) < vabs_f16 ( __b ) ) ; return ( uint16x4_t ) __builtin_neon_vcaltv4hf


<s> Uses . insert ( V ) ; return Defs . count (


<s> return new <ISA_LIT>CodeEmitter ( TM ,


<s> if ( MFI . adjustsStack ( ) && TFL . hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( NumBytes ) ; MI . eraseFromParent ( ) ; return


<s> EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = <STR_LIT> ( EltTy ,


<s> else if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNum ) && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNum ) ) IsVector = false ; else if ( Layout . size ( ) == <NUM_LIT> ) IsVector = false ; if ( ! IsVector ) Error ( Parser . getTok ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = <STR_LIT> ; break ; default : return false ; } unsigned UnallocatedRegisterIndex = State . getFirstUnallocated ( RegList ) ; if ( UnallocatedRegisterIndex < RegList . size ( ) ) State . AllocateStack ( LocVT . getSizeInBits ( ) / <NUM_LIT> , Align ( <NUM_LIT> ) ) ; return false


<s> return ( __m256i ) __builtin_ia32_loaddqudi256_mask ( ( __v4di * ) __P ,


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT>


<s> assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( VT ) ; if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , Ext } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size ,


<s> MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHT_REL ) ; const MCSymbolRefExpr * ExprRef = MCSymbolRefExpr :: create ( Name , MCSymbolRefExpr :: VK_None , Context ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( <NUM_LIT> ) ; OS . PushSection ( ) ; OS . SwitchSection ( Sec ) ; OS . EmitValueImpl ( ExprRef , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet = false ; OS . PopSection


<s> SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getResNo ( ) == <NUM_LIT> && N0 . getValueType ( ) == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) { SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , VT ) ; SDValue R = DAG . getNode ( <STR_LIT> , dl , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , R . getValue ( <NUM_LIT> ) ) ; return R . getValue ( <NUM_LIT> ) ; } return SDValue ( )


<s> if ( ! TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT ( decl ) ) DECL_VISIBILITY ( decl )


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CalleeVReg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToES ( Symbol ) ; MI . setDesc ( TII -> get ( Opc ) ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , AvailableReg ) . addReg ( CalleeVReg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToES ( Symbol ) ; MI . setDesc ( TII -> get ( Opc ) ) ; MachineInstrBuilder ( * BB -> getParent ( ) , & MI ) . addReg ( AvailableReg , RegState ::


<s> SDValue AVL = getNodeAVL ( Op ) ; SDValue Data = getStoredValue ( Op ) ; SDValue PassThru = getNodePassthru ( Op ) ; SDValue StrideV = getLoadStoreStride ( Op , CDAG ) ; auto DataVT = * getIdiomaticVectorType ( Op . getNode ( ) ) ; auto Packing = getTypePacking ( DataVT ) ; if ( ! AVL ) AVL = CDAG . getConstant ( DataVT . getVectorNumElements ( ) , <STR_LIT> ) ; if ( ! Mask ) Mask = CDAG . getConstantMask ( Packing , true ) ; if ( IsLoad ) { MVT LegalDataVT = getLegalVectorType ( Packing , DataVT . getVectorElementType ( ) . getSimpleVT ( ) ) ; auto NewLoadV = CDAG . getNode ( <STR_LIT> , { LegalDataVT , <STR_LIT> } , { Chain , BasePtr , StrideV , Mask , AVL } ) ; if ( ! PassThru || PassThru -> isUndef ( ) ) return NewLoadV ; SDValue DataV = CDAG . getNode ( <STR_LIT> , DataVT , { NewLoadV , PassThru , Mask , AVL } ) ; SDValue NewLoadChainV = SDValue ( NewLoadV . getNode ( ) , <NUM_LIT> ) ; return CDAG . getMergeValues ( { DataV , NewLoadChainV } ) ; } assert ( VVPOpc == <STR_LIT> ) ; return CDAG . getNode ( <STR_LIT> , Op . getNode ( ) -> getVTList ( ) , { Chain , Data , BasePtr , StrideV


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCCE ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger


<s> return __builtin_mve_vcaddq_rot90_uv4si ( __a ,


<s> } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || ( code == LE && TARGET_IEEE && TARGET_SH2E ) || ( code == GE && ! ( TARGET_IEEE && TARGET_SH2E ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { gcc_assert ( TARGET_IEEE && TARGET_SH2E ) ; need_ccmpeq = true ; code = GT ; } gcc_assert ( code == EQ || code == GT || code == NE || code == LE ) ; } switch ( code ) { case EQ : case GT : case GE : case GTU : case GEU : branch_code = code ; break ; case NE : case LT : case


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { if ( AddSub == <STR_LIT> ) Val *= - <NUM_LIT> ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( Val , SDLoc ( Op ) , <STR_LIT> ) ; return true


<s> O << formatImm ( MI -> getOperand ( Op ) . getImm


<s> if ( ! isThumb1 ) llvm_unreachable ( <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; NumUBrFixed ++


<s> BuildMI ( MBB , & * MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , & * MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; MFI . setObjectAlignment ( CSI [ i ] . getFrameIdx ( ) , STI . getCapAlignment ( ) ) ; } bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken && KillRAOnSpill


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) != <STR_LIT> ) return false ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t MinOffset = - <NUM_LIT> ; for ( auto & UseInstr : MRI . use_nodbg_instructions ( Dst ) ) { if ( UseInstr . getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return false ; auto Cst = getIConstantVRegValWithLookThrough ( UseInstr . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Cst ) return false ; MinOffset = std :: min ( MinOffset , Cst -> Value . getZExtValue ( ) ) ; } uint64_t CurrOffset = GlobalOp . getOffset ( ) ; uint64_t NewOffset = MinOffset + CurrOffset ; if ( NewOffset <= CurrOffset ) return false ; if ( NewOffset >= ( <NUM_LIT> << <NUM_LIT> ) ) return false ; Type * T = GV ->


<s> EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF


<s> case <STR_LIT> : AtomicOp = <STR_LIT> ; NeedsAdditionalReg = true ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; NeedsAdditionalReg = true ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; NeedsAdditionalReg = true ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; NeedsAdditionalReg = true ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; NeedsAdditionalReg = true ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; NeedsAdditionalReg = true ; break ; default : AtomicOp = getCheriPostRAAtomicOp ( MI , & IsCapabilityArg , & NeedsAdditionalReg ) ; break ; } Register OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto RC = RegInfo . getRegClass ( OldVal ) ; if ( IsCapabilityArg ) RC = & <STR_LIT> ; Register Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch = RegInfo . createVirtualRegister ( RC ) ; MachineBasicBlock :: iterator II ( MI ) ; Register PtrCopy = RegInfo . createVirtualRegister ( RegInfo . getRegClass ( Ptr ) ) ; unsigned IncrCopy = Incr ; if ( Register :: isVirtualRegister ( Incr ) ) { IncrCopy = RegInfo . createVirtualRegister ( RegInfo . getRegClass ( Incr ) ) ; BuildMI ( * BB , II , DL , TII -> get (

<STR_LIT> ) , IncrCopy ) . addReg ( Incr ) ;


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI


<s> assert ( CapSize == <NUM_LIT> && <STR_LIT> ) ; assert ( ! getContext ( ) . getAsmInfo ( ) -> isLittleEndian


<s> unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; TII . loadRegFromStack ( MBB , I , VR , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , Dst ) .


<s> case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op


<s> O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; }


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( N0 ) && IsFoldableRMW ( N0 , Op ) ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Commute = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( N1 ) && ( ! Commute || ! isa < ConstantSDNode > ( N0 ) || ( Op . getOpcode ( ) != <STR_LIT> && IsFoldableRMW ( N1 , Op ) ) ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ( Commute && ! isa < ConstantSDNode > ( N1 ) ) || ( Op .

getOpcode ( ) != <STR_LIT> && IsFoldableRMW ( N0 , Op ) ) ) ) return false ;


<s> return ( __mmask8 ) __builtin_ia32_fpclassss ( ( __v4sf )


<s> return ( int32x2_t ) __builtin_neon_vraddhnv2di ( __a ,


<s> if ( isa < FCmpInst > ( & I ) ) return false ; if ( isa < FPExtInst > ( & I ) || isa < FPTruncInst > ( & I ) ) return false ; if ( isa < SExtInst > ( & I ) || isa < ZExtInst > ( & I ) ) if ( ! I . getOperand ( <NUM_LIT> ) -> hasOneUse ( ) || ! isa < LoadInst > ( I . getOperand ( <NUM_LIT> ) ) ) return false ; if ( isa < TruncInst > ( & I ) ) if ( ! I . hasOneUse ( ) || ! isa < StoreInst > ( * I . user_begin ( ) ) ) return false ; return


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { switch ( Subtarget . TargetType


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const { return TM . isPositionIndependent ( )


<s> if ( Parity == <NUM_LIT> ) C = G -> getPreferredColor ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Parity << <STR_LIT> << ColorNames [ ( int ) C ] << <STR_LIT> ) ; if ( G -> requiresFixup ( ) && C != G -> getPreferredColor ( ) ) { C = G -> getPreferredColor ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << G -> str ( ) << <STR_LIT> <STR_LIT> << ColorNames [ ( int ) C ] << <STR_LIT> ) ; } Changed |= colorChain ( G , C , MBB ) ; Parity += ( C == Color :: Even ) ? G -> size ( ) : - G -> size


<s> const <ISA_LIT>InstrInfo * TII = getInstrInfo ( ) ; if ( RxSBG . Rotate != <NUM_LIT> ) Mask = ( Mask << RxSBG . Rotate ) | ( Mask >> ( <NUM_LIT> - RxSBG . Rotate ) ) ; Mask &= RxSBG . Mask ; if ( TII -> isRxSBGMask ( Mask , RxSBG . BitSize , RxSBG . Start , RxSBG . End ) ) { RxSBG . Mask = Mask ; return true ; } return false


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , int val ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( val ) ; return gen_rtx_CONST_VECTOR ( mode


<s> case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N , DCI


<s> } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MPI , <NUM_LIT> , MachineMemOperand :: MOLoad ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF ) , PtrVT ) ; unsigned CPAlignment = cast < ConstantPoolSDNode > ( FudgePtr ) -> getAlignment ( ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Four , Zero ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , CPAlignment ) ; Chain = Fudge . getValue ( <NUM_LIT> ) ; if ( IsStrict ) { SDValue Add = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , Fild , Fudge } ) ; if ( DstVT == <STR_LIT> ) return Add ; return DAG . getNode ( <STR_LIT> , dl , { DstVT , <STR_LIT> } , { Add . getValue ( <NUM_LIT> ) , Add , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) } ) ; } SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Add , DAG

. getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> Function * Stxr = <STR_LIT> ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = <STR_LIT> ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout (


<s> sprintf ( instr , <STR_LIT> , conditional ) ; } } else if ( IS_INTERRUPT ( func_type ) ) sprintf ( instr , <STR_LIT> , conditional ) ; else sprintf ( instr , <STR_LIT> , conditional ) ; p = instr + strlen ( instr ) ; for ( reg = <NUM_LIT> ; reg <= SP_REGNUM ; reg ++ ) if ( live_regs_mask & ( <NUM_LIT> << reg ) ) { int l = strlen ( reg_names [ reg ] ) ; if ( first ) first = <NUM_LIT> ; else { memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; p += <NUM_LIT> ; } memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; memcpy ( p + <NUM_LIT> , reg_names [ reg ] , l ) ; p += l + <NUM_LIT> ; } if ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) { sprintf ( p , <STR_LIT> , first ? <STR_LIT> : <STR_LIT> , return_reg ) ; if ( IS_INTERRUPT ( func_type ) ) strcat ( p , <STR_LIT> ) ; } else strcpy ( p , <STR_LIT> ) ; } output_asm_insn ( instr , & operand ) ; if ( really_return && func_type != ARM_FT_INTERWORKED && ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ) { return <STR_LIT> ; } } if ( really_return ) { switch ( ( int ) ARM_FUNC_TYPE ( func_type ) ) { case ARM_FT_ISR : case ARM_FT_FIQ : sprintf ( instr , <STR_LIT> , conditional ) ; break ; case ARM_FT_INTERWORKED : gcc_assert ( arm_arch5t || arm_arch4t ) ; sprintf ( instr , <STR_LIT> , conditional ) ; break ; case ARM_FT_EXCEPTION : sprintf ( instr , <STR_LIT> , conditional ) ; break ; default : if ( IS_CMSE_ENTRY (


<s> if ( Kind == MCK_FPR64 && ( Op . Reg . RegNum < <STR_LIT> || Op . Reg . RegNum > <STR_LIT> ) ) return Match_InvalidRegOutOfRange ; return Match_Success ; } } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { if ( Kind == MCK_GPRPair ) { Op . Reg . RegNum = MRI -> getEncodingValue ( Reg ) + <STR_LIT> ; return Match_Success ; } } return Match_InvalidOperand


<s> int count = XVECLEN ( op , <NUM_LIT> ) ; int first_set = vfp ? <NUM_LIT> : <NUM_LIT> ; machine_mode expected_mode = vfp ? E_SFmode : E_SImode ; for ( int i = first_set ; i < count ; i ++ ) { elt = XVECEXP ( op , <NUM_LIT> , i ) ; if ( ! vfp && GET_CODE ( elt ) == UNSPEC_VOLATILE ) { if ( XINT ( elt , <NUM_LIT> ) != VUNSPEC_CLRM_APSR || XVECLEN ( elt , <NUM_LIT> ) != <NUM_LIT> || XVECEXP ( elt , <NUM_LIT> , <NUM_LIT> ) != CONST0_RTX ( SImode ) || i != count - <NUM_LIT> ) return false ; continue ; } if ( GET_CODE ( elt ) == CLOBBER ) continue ; if ( GET_CODE ( elt ) != SET ) return false ; reg = SET_DEST ( elt ) ; zero = SET_SRC ( elt ) ; if ( ! REG_P ( reg ) || GET_MODE ( reg ) != expected_mode || zero != CONST0_RTX ( SImode ) ) return false ; regno = REGNO ( reg ) ; if ( vfp ) { if ( i != first_set && regno != last_regno + <NUM_LIT> ) return false ; } else { if ( regno == SP_REGNUM || regno == PC_REGNUM ) return false ; if ( i != first_set && regno <= last_regno )


<s> if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode )


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI ->

getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_SaveList ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_SaveList ; else if ( isSVEFunction ( * MF ) ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo


<s> assert ( SrcScalarBits < DstScalarBits && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumDstElts ; i ++ ) { Mask . push_back ( i ) ; for ( unsigned j = <NUM_LIT> ; j != Scale ; j ++ ) Mask . push_back (


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Val

) , DAG . getValueType ( Val . getValueType ( ) ) ) ;


<s> static bool insn_can_be_in_speculative_p ( rtx insn ATTRIBUTE_UNUSED


<s> VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( getGlobalContext ( ) ) , NumElem ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedLoad ( SrcVTy , <NUM_LIT> ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedStore ( SrcVTy , <NUM_LIT> ) ) || ! isPowerOf2_32 ( NumElem ) ) { unsigned MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; unsigned ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( getGlobalContext ( ) ) , NULL ) ; unsigned BranchCost = getCFInstrCost ( Instruction :: Br ) ; unsigned MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; unsigned ValueSplitCost = getScalarizationOverhead ( SrcVTy , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; unsigned MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( SrcVTy ) ; unsigned Cost = <NUM_LIT> ; if ( LT . second != TLI -> getValueType ( SrcVTy ) . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_Alternate , SrcVTy , <NUM_LIT> , <NUM_LIT> ) + getShuffleCost ( TTI :: SK_Alternate , MaskTy , <NUM_LIT> , <NUM_LIT> ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { VectorType * NewMaskTy = VectorType :: get ( MaskTy -> getVectorElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy , <NUM_LIT> , MaskTy ) ; } if ( ! ST -> hasAVX512 ( ) ) return Cost + LT


<s> Triple TheTriple ( TT ) ; const uint8_t ABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT


<s> const MCExpr * Register ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( Register ) ) return MatchOperand_ParseFail ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Register ) ) { int64_t Value = CE -> getValue ( ) ; if ( Value < <NUM_LIT> || Value > <NUM_LIT> ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Register , StartLoc , EndLoc ) ) ; } else { Register Reg ; if ( parseRegister ( Reg ) ) return MatchOperand_ParseFail ; RegisterKind Kind ; unsigned RegNo ; if ( Reg . Group == RegGR ) { Kind =


<s> if ( VT == <STR_LIT> ) return buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( VT == <STR_LIT> ) { SDValue Op01 = buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; SDValue Op23 = buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( Op01 . isUndef ( ) ) Op01 = Op23 ; else if ( Op23 . isUndef ( ) ) Op23 = Op01 ; if ( Op01 . getOpcode ( ) == <STR_LIT> && Op01 == Op23 ) return Op01 ; Op01 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op01 ) ; Op23 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op23 ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op01 , Op23 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } SmallVector < SDValue , <STR_LIT> > Constants ( NumElements , SDValue ( ) ) ; SmallVector < bool , <STR_LIT> > Done ( NumElements , false ) ; unsigned NumConstants = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { SDValue Elem = Elems [ I ] ; if ( Elem . getOpcode ( ) == <STR_LIT> || Elem . getOpcode ( ) == <STR_LIT> ) { NumConstants += <NUM_LIT> ; Constants [ I ] = Elem ; Done [ I ] = true ; } } SDValue Result ; if ( NumConstants > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) if ( ! Constants [ I ] . getNode ( ) ) Constants [ I ] = DAG .

getUNDEF ( Elems [ I ] . getValueType ( ) ) ;


<s> static CodeModel :: Model getEffectiveCodeModel ( const Triple & TT , Optional < CodeModel :: Model > CM , bool JIT ) { if ( CM ) { if ( * CM != CodeModel :: Small && * CM != CodeModel :: Tiny && * CM != CodeModel :: Large ) { if ( ! TT . isOSFuchsia ( ) ) report_fatal_error ( <STR_LIT> ) ; else if ( * CM != CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else if ( * CM == CodeModel :: Tiny && ! TT . isOSBinFormatELF ( ) )


<s> bool <ISA_LIT>TargetLowering :: canTreatAsByteVector ( EVT VT ) const { if ( ! Subtarget . hasVector (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CmpInst :: FCMP_OEQ : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_OGT : NeedSwap = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_OLT : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_OGE : NeedSwap = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_OLE : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_UNO : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_UNE : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_ULE : NeedSwap = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_UGE : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_ULT :


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG ,


<s> if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; In = DAG . getBitcast ( InVT , In ) ; } return DAG . getSetCC ( DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , <STR_LIT> ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT ,


<s> if ( cfun -> machine -> func_type == TYPE_UNKNOWN ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( fndecl ) ) ) ) { int nargs = <NUM_LIT> ; for ( tree arg = DECL_ARGUMENTS ( fndecl ) ; arg ; arg = TREE_CHAIN ( arg ) ) nargs ++ ; cfun -> machine -> no_caller_saved_registers = true ; cfun -> machine -> func_type = nargs == <NUM_LIT> ? TYPE_EXCEPTION : TYPE_INTERRUPT ; ix86_optimize_mode_switching [ X86_DIRFLAG ] = <NUM_LIT> ; if ( write_symbols != NO_DEBUG && write_symbols != DWARF2_DEBUG ) sorry ( <STR_LIT> <STR_LIT> ) ; } else { cfun -> machine ->


<s> void <ISA_LIT>CodeEmitter :: emitVFPLoadStoreMultipleInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx + <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; ++ NumRegs ; } if ( Binary & <NUM_LIT> ) Binary |= NumRegs * <NUM_LIT> ; else Binary


<s> uint32_t j1 = ( pOffset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t lo = ( pOffset & <NUM_LIT>


<s> void <ISA_LIT>IncomingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign


<s> static SDValue getMOVL ( SelectionDAG & DAG , SDLoc dl , EVT VT , SDValue V1 , SDValue V2 ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ; Mask . push_back ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++


<s> return __builtin_mve_vcvttq_f32_f16v4sf (


<s> OperandMatchResultTy parseBDAddr64 ( OperandVector & Operands


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) std :: swap ( LHS , RHS ) ; if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDLoc DL ( N ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT OpVT = LHS . getValueType ( ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } } return DAGCombineTruncBoolExt ( N


<s> return ( uint8x16_t ) __builtin_neon_vld1_lanev16qi ( ( const __builtin_neon_qi * ) __a , ( int8x16_t )


<s> const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1


<s> unsigned Opc ; SDValue Offset , Base ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore ( N , Opc_rr , Opc_ri , N -> getOperand ( NumVecs + <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Scale ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , Base , Offset , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printVFPf32ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << '#' << MI -> getOperand (