<s> static void aarch64_emit_sve_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { rtx flag = gen_int_mode (


<s> const char * <ISA_LIT>GNUInfo :: entry (


<s> bool isMovKSymbolG1 ( ) const { return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G1_NC , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ,

<ISA_LIT>MCExpr :: VK_DTPREL_G1_NC } ) ;


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> ignoreZeroFlag ( ) ) { addPass ( new IgnoreZeroFlag ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> performSDIVReplace ( ) ) { addPass ( new ReplaceSDIV ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> fixCallImmediates ( ) ) { addPass ( new FixCALL ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> preventRoundChange ( ) ) { addPass ( new PreventRoundChange ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPsLoadStore ( ) ) { addPass ( new InsertNOPsLoadStore ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl


<s> return createELFObjectWriter ( createELFObjectTargetWriter ( )


<s> static bool IsInSmallSection ( uint64_t Size


<s> unsigned Out = MRI -> createVirtualRegister ( QPR ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( QPR ? <STR_LIT> : <STR_LIT> ) , Out ) . addReg ( Reg ) . addImm (

Lane ) . add ( predOps ( <STR_LIT> ) ) ;


<s> unsigned <ISA_LIT>SEInstrInfo :: getAnalyzableBrOpc ( unsigned Opc ) const { return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ||

Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return SDValue ( ) ; SDValue And0 = N -> getOperand ( <NUM_LIT> ) , And1 = N -> getOperand ( <NUM_LIT> ) ; uint64_t SMPos0 , SMSize0 , SMPos1 , SMSize1 ; ConstantSDNode * CN ; if ( And0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And0 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( ~ CN -> getSExtValue ( ) , SMPos0 , SMSize0 ) ) return SDValue ( ) ; if ( And1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 )


<s> case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( dyn_cast < ConstantFP > ( CallOperandVal ) ) { weight = CW_Constant ; } break ; case 'e' : if ( ConstantInt * C = dyn_cast <


<s> return ( __m128 ) __builtin_ia32_cmpltss ( ( __v4sf ) __A ,


<s> return __builtin_loongson_pandn_sb ( s


<s> TerminatorInfo <ISA_LIT>LongBranch :: describeTerminator ( MachineInstr * MI ) { TerminatorInfo Terminator ; Terminator . Size = TII -> getInstSizeInBytes ( MI ) ; if ( MI -> isConditionalBranch ( ) || MI -> isUnconditionalBranch ( ) ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Terminator . Branch = MI ; Terminator . TargetBlock = TII -> getBranchInfo ( MI ) . Target -> getMBB ( )


<s> Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned )


<s> int Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; int ThisVal = ( Imm > Chunk ) ? Chunk : Imm ; Imm -= ThisVal ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> )


<s> case RegPairInfo :: FPR128 : if ( <STR_LIT> . contains ( NextReg ) ) RPI . Reg2 = NextReg ; break ; } } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; int Scale = RPI . Type == RegPairInfo :: FPR128 ? <NUM_LIT> : <NUM_LIT> ; Offset -= RPI . isPaired ( ) ? <NUM_LIT>


<s> return <ISA_LIT>Lowering -> SelectAddressRegImm34 ( N , Disp


<s> unsigned Shift = <STR_LIT> ( Val ) ; return <STR_LIT> ( Val ) == <STR_LIT> && ( Shift == <NUM_LIT> || Shift ==


<s> static SDValue lowerV4I64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isHalfCrossingShuffleMask ( Mask ) ) return splitAndLower256BitVectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , lowerV4F64VectorShuffle ( Op


<s> case FP_LO_REGS : case FP_LO8_REGS : vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( ( vec_flags & VEC_SVE_DATA ) && constant_multiple_p ( GET_MODE_SIZE ( mode ) , aarch64_vl_bytes ( mode , vec_flags ) , & nregs ) ) return nregs ; return ( vec_flags & VEC_ADVSIMD ? CEIL ( lowest_size , UNITS_PER_VREG ) : CEIL ( lowest_size , UNITS_PER_WORD ) ) ; case


<s> unsigned Opc = cast < Instruction > ( V ) -> getOpcode ( ) ; return Opc == Instruction :: AShr || Opc == Instruction :: SDiv ||

Opc == Instruction :: SRem || Opc == Instruction :: SExt ;


<s> static __inline vec_int4 spu_xor ( vec_int4 a , signed int b ) { return ( ( vec_int4 ) ( si_xori ( ( qword ) ( a )


<s> UP . MaxCount = <NUM_LIT> ; UP . FullUnrollMaxCount = <NUM_LIT> ; UP . Partial = false ; UP . Runtime = false ; UP . AllowRemainder =


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasAVX ( ) || ST . hasFastPartialYMMorZMMWrite ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; EverMadeChange = false ; Is<ISA_LIT>INTR = MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ; bool FnHasLiveInYmmOrZmm = checkFnHasLiveInYmmOrZmm ( MRI ) ; bool YmmOrZmmUsed = FnHasLiveInYmmOrZmm ; const TargetRegisterClass * RCs [ <NUM_LIT> ] = { & <STR_LIT> , & <STR_LIT> } ; for ( auto * RC : RCs ) { if ( ! YmmOrZmmUsed


<s> static inline bool mips_constant_elt_p


<s> bool <ISA_LIT>AsmParser :: parseSetNoAtDirective ( ) { MCAsmParser & Parser = getParser ( ) ; AssemblerOptions . back ( ) -> setATReg ( <NUM_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError (


<s> bool isU32Imm ( ) const { return isImm ( <NUM_LIT> , ( <NUM_LIT>


<s> unsigned FP = <STR_LIT> ; unsigned ZERO = <STR_LIT> ; unsigned ADDu = <STR_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } if ( <ISA_LIT>FI -> callsEhReturn


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) return <STR_LIT> ; if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? <STR_LIT> : <STR_LIT> ; else return GV -> hasLocalLinkage ( ) ?


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y


<s> PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM == Reloc :: Static ) ; if ( in<ISA_LIT>16Mode ( ) ) HasBitCount


<s> unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ; RHSReg = constrainOperandRegClass ( II , RHSReg , II . getNumDefs ( ) + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( LHSReg , getKillRegState ( LHSIsKill ) ) . addReg ( RHSReg , getKillRegState ( RHSIsKill ) ) ; return


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { if ( BytesRemoved ) * BytesRemoved = <NUM_LIT> ; return <NUM_LIT> ; } -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( BytesRemoved ) * BytesRemoved =


<s> Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( int ) imm & <NUM_LIT> , <STR_LIT> ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } Disp = DAG . getTargetConstant ( <NUM_LIT> , getPointerTy ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base =


<s> unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return true


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } int64_t Imm = CI -> getZExtValue ( ) ; if ( VT == <STR_LIT> ) return <ISA_LIT>Materialize64BitInt ( Imm , RC ) ; else if ( VT == <STR_LIT> ) return <ISA_LIT>Materialize32BitInt ( Imm , RC ) ; return <NUM_LIT>


<s> if ( EltVT . isFloatingPoint ( ) ) { Zero = DAG . getBitcast ( EltVT , Zero ) ; AllOnes = DAG . getBitcast ( EltVT , AllOnes ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i


<s> if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; initialize (


<s> unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ( maxCallFrameSize & ( MaxAlign - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { if ( LP64 ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; Register NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister


) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( <NUM_LIT> ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( <NUM_LIT> ) ) ; \ }


<s> return ( poly8x8_t ) __builtin_neon_vget_highv16qi ( ( int8x16_t


<s> if ( INSN_CODE ( insn ) == CODE_FOR_divmodsi4 || INSN_CODE ( insn ) == CODE_FOR_udivmodsi4 ) return true ; return false


<s> bool isMachO = MAI . hasSubsectionsViaSymbols ( ) ; StringRef Name ; bool needFuncName = true ; if ( isMachO ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: EndOfStatement ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken ::

String ) ) return Error ( L , <STR_LIT> ) ;


<s> unsigned stackAlignment ( ) const { return has<ISA_LIT>64 ( ) ?


<s> return Kind == k_Register && ! Reg . isVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { static const TypeConversionCostTblEntry NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first


<s> } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_H44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_M44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_L44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HH ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HM ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT10 ) . Case ( <STR_LIT> , VK_Sparc_R_DI<ISA_LIT>32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_HI22

) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_LOX10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LDX ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_LOX10 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case


<s> case MachineOperand :: MO_Register : if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ; OutStreamer -> emitInstruction ( CallInst , getSubtargetInfo ( ) ) ; } auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel


<s> OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( POPCNT ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM32 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC


<s> void printbytemem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> return ( uint16x4_t ) __builtin_neon_vceqzv4hf (


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> unsigned FrameReg ; return getFrameIndexReference ( MF , FI , FrameReg


<s> printInstruction ( MI , O ) ; printAnnotation ( O ,


<s> unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( Ret , getSubtargetInfo ( ) ) ; emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; recordSled ( CurSled , MI , SledKind ::


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI ->


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed


<s> return new <ISA_LIT>BranchCoalescing


<s> unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr ,

MachinePointerInfo ( FuncArg , I * <NUM_LIT> ) , false , false , <NUM_LIT> ) ;


<s> if ( ! canCoalesceBranch ( Cand2 ) ) break ; assert ( MPDT -> dominates ( Cand2 . BranchTargetBlock , Cand1 . BranchBlock ) && <STR_LIT> ) ; if ( ! identicalOperands ( Cand1 . Cond , Cand2 . Cond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cand1 . BranchBlock -> getNumber ( ) << <STR_LIT> << Cand2 . BranchBlock -> getNumber ( ) << <STR_LIT> ) ; break ; } if ( ! canMerge ( Cand2 , Cand1 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cand1 . BranchBlock -> getNumber ( ) << <STR_LIT> << Cand2 . BranchBlock -> getNumber ( ) << <STR_LIT> ) ; NumBlocksNotCoalesced ++


<s> inline bool isImmPCRel ( uint64_t TSFlags ) { switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result


<s> const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , Offset , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset ) . addMemOperand


<s> return __builtin_mve_vaddq_m_n_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __b ,


<s> SDValue GA = DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ; return getTOCEntry ( DAG , SDLoc ( BASDN ) , GA ) ; } if ( Subtarget . is32BitELFABI ( ) && isPositionIndependent ( ) ) return getTOCEntry ( DAG , SDLoc ( BASDN ) , DAG . getTargetBlockAddress ( BA , PtrVT , BASDN -> getOffset ( ) ) ) ; unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( TgtBAHi , TgtBALo , IsPIC


<s> TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; IsRelocPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this


<s> if ( signature_args [ signature ] [ <NUM_LIT> ] ) { if ( ignore ) return NULL_RTX ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ nop ++ ] = target ; } else target = NULL_RTX ; for ( int i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ , nop ++ ) { tree arg ; machine_mode opmode , argmode ; tree optype ; if ( ! signature_args [ signature ] [ i ] ) break ; arg = CALL_EXPR_ARG ( exp , i - <NUM_LIT> ) ; if ( arg == error_mark_node ) return const0_rtx ; if ( signature_args [ signature ] [ i ]


<s> CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , <NUM_LIT> ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; bool isPIC = MF . getTarget ( )

. getRelocationModel ( ) == Reloc :: PIC_ ;


<s> auto EC = cast < VectorType > ( A -> getType ( ) ) -> getElementCount ( ) ; auto EvenIdx = Builder . CreateSeriesVector ( EC , Zero , Two ) ; auto OddIdx = Builder . CreateSeriesVector ( EC , One , Two ) ; auto UnzipEven = Builder . CreateShuffleVector ( A , B , EvenIdx ) ; auto UnzipOdd = Builder . CreateShuffleVector ( A , B , OddIdx ) ; return std :: make_tuple ( UnzipEven ,


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = <STR_LIT> ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand (


<s> if ( Offset != <NUM_LIT> && ( AM . ES || AM . MCSym ) ) return true ; int64_t Val = AM . Disp + Offset ; CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) ) { if ( ! <STR_LIT> ( Val , M , AM . hasSymbolicDisplacement ( ) ) ) return true ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && ! isDispSafeForFrameIndex ( Val ) ) return true ; } AM . Disp = Val


<s> } for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getVectorElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getVectorNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , VectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case


<s> CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize


<s> for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo (


<s> aarch64_print_operand_address ( STREAM , X ) { \ rtx fun , lr ; \ lr = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; \ fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_NAME ) ; \

emit_library_call ( fun , LCT_NORMAL , VOIDmode , <NUM_LIT> , lr , Pmode ) ; \ }


<s> bool <ISA_LIT>BaseRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF


<s> N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl


<s> bool <ISA_LIT>RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |=


<s> static bool isUpperSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal ,

const <STR_LIT> CC , const SDValue K ) {


<s> return val_in | ~ aarch64_and_split_imm1


<s> static tree rs6000_handle_longcall_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool


<s> static unsigned int aarch64_sve_in_loop_reduction_latency ( vec_info * vinfo , stmt_vec_info stmt_info , tree vectype , const sve_vec_cost * sve_costs ) { switch ( aarch64_reduc_type ( vinfo , stmt_info ) ) { case EXTRACT_LAST_REDUCTION : return sve_costs -> clast_cost ; case FOLD_LEFT_REDUCTION : switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_HFmode


<s> bool isCCRegNumber ( ) const { return ( Kind == Expression && isUInt < <NUM_LIT> > ( getExprCRVal ( ) ) ) || ( Kind == Immediate

&& isUInt < <NUM_LIT> > ( getImm ( ) ) ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_CMP_SWAP ( SDValue Op , SelectionDAG & DAG ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; EVT NarrowVT = Node -> getMemoryVT ( ) ; EVT WideVT = <STR_LIT> ; if ( NarrowVT == WideVT ) return Op ; int64_t BitSize = NarrowVT . getSizeInBits ( ) ; SDValue ChainIn = Node -> getOperand ( <NUM_LIT> ) ; SDValue Addr = Node -> getOperand ( <NUM_LIT> ) ; SDValue CmpVal = Node -> getOperand ( <NUM_LIT> ) ; SDValue SwapVal = Node -> getOperand ( <NUM_LIT> ) ; MachineMemOperand * MMO = Node -> getMemOperand ( ) ; SDLoc DL (


<s> return ( __m512d ) __builtin_ia32_expanddf512_maskz ( ( __v8df ) __A , ( __v8df ) _mm512_setzero_pd ( ) ,


<s> if ( ! GV -> hasAttribute ( <STR_LIT> ) ) return false ; assert ( PointerSize == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( PointerSize >= GV -> getAlign ( ) . valueOrOne ( ) . value ( ) && <STR_LIT> <STR_LIT> ) ; Type * GVType = GV -> getValueType ( ) ; assert ( GVType -> isSized (


<s> float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> bool <ISA_LIT>TargetLowering :: isLegalStoreImmediate ( int64_t Imm


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU


<s> IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_FloatAdd : IntID = <STR_LIT> ; break ; } if ( IntID == <STR_LIT> ) return nullptr ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * Intrinsic = <STR_LIT> ( M , IntID , Src


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn ) ) ) ; return MCDisassembler ::


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT>


<s> CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask2 = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Mask2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val


<s> for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> switch ( Opc ) { case <STR_LIT> : if ( ! Op . hasOneUse ( ) || ! isTypeLegal ( VT ) || Subtarget . hasQPX ( ) ) break ; const TargetOptions & Options = getTargetMachine ( ) . Options ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; SDLoc Loc ( Op ) ; NegatibleCost N2Cost = NegatibleCost :: Expensive ; SDValue NegN2 = getNegatedExpression ( N2 , DAG , LegalOps , OptForSize , N2Cost , Depth + <NUM_LIT> ) ; if ( ! NegN2 ) return SDValue ( ) ; if ( Flags . hasNoSignedZeros ( ) || Options . NoSignedZerosFPMath ) { NegatibleCost N0Cost = NegatibleCost :: Expensive ; SDValue NegN0 = getNegatedExpression ( N0 , DAG , LegalOps , OptForSize ,


<s> bool <ISA_LIT>TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , bool Fast ) { PM . add (


<s> return ( int16x4_t ) __builtin_neon_vqshl_s_nv4hi (


) _writefsbase_u32 ( unsigned int __B ) {


<s> } if ( loongarch_valid_base_register_p ( XEXP ( x , <NUM_LIT> ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , <NUM_LIT> ) , mode , strict_p ) ) { info -> reg = XEXP ( x , <NUM_LIT> ) ; return true ; } info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP (


<s> unsigned min , max , minswap , maxswap ; bool in_order , ok , swap = false ; rtx shift , target ; struct expand_vec_perm_d dcopy ; if ( ( ! TARGET_SSSE3 || GET_MODE_SIZE ( d -> vmode ) != <NUM_LIT> ) && ( ! TARGET_AVX2 || GET_MODE_SIZE ( d -> vmode ) != <NUM_LIT> ) ) return false ; min = <NUM_LIT> * nelt ; max = <NUM_LIT> ; minswap = <NUM_LIT> * nelt ; maxswap = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; unsigned eswap = d -> perm [ i ] ^ nelt ; if ( GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ) { e = ( e & ( ( nelt / <NUM_LIT> ) - <NUM_LIT> ) ) | ( ( e & nelt ) >> <NUM_LIT> ) ; eswap = e ^ ( nelt / <NUM_LIT> ) ; } if ( e < min ) min = e ; if ( e > max ) max = e ; if ( eswap < minswap ) minswap = eswap ; if ( eswap > maxswap ) maxswap = eswap ; } if ( min == <NUM_LIT> || max - min >= ( GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ? nelt / <NUM_LIT> : nelt ) ) { if ( d -> one_operand_p || minswap == <NUM_LIT> || maxswap - minswap >= ( GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ? nelt / <NUM_LIT> : nelt ) ) return false ; swap = true ; min = minswap ; max = maxswap ; } if ( d -> testing_p && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> && ! single_insn_only_p ) return true ; dcopy = * d ; if ( swap ) { dcopy . op0 =


<s> unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ScrReg ) . addReg ( SrcReg ) . addImm ( ShiftImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( ScrReg ) . addImm ( ShiftImm ) ; return BB


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } } else if ( DestRC == <STR_LIT> ) { if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } else if ( SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } } return


<s> default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX512 ( ) ) { const TargetRegisterClass * VR128X = & <STR_LIT> ; const TargetRegisterClass * VK1 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , VK1 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned ImplicitDefReg = createResultReg ( VR128X ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned MovOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned MovReg = fastEmitInst_rrrr ( MovOpcode , VR128X , RHSReg , RHSIsKill , CmpReg , true , ImplicitDefReg , true , LHSReg , LHSIsKill ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( MovReg ) ; } else if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill ,


<s> if ( flag_stack_clash_protection && maybe_ne ( cfun -> machine -> frame . below_hard_fp_saved_regs_size , <NUM_LIT> ) && known_eq ( offset , <NUM_LIT> ) ) continue ; if ( frame_pointer_needed ) offset -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset += crtl -> outgoing_args_size ; if ( aarch64_sve_mode_p ( mode ) ? offset_9bit_signed_scaled_p ( mode , offset ) : offset_12bit_unsigned_scaled_p ( mode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( cfun -> machine -> frame . spare_pred_reg != INVALID_REGNUM ) bitmap_clear_bit ( components

, cfun -> machine -> frame . spare_pred_reg ) ;


<s> bool <ISA_LIT>FrameLowering :: needsDwarfCFI ( const MachineFunction


<s> case <STR_LIT> : case <STR_LIT> : return tryCombineFixedPointConvert ( N , DCI , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : case


<s> assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( )


<s> unsigned Out = MRI -> createVirtualRegister ( QPR ? & <STR_LIT> : & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( QPR ? <STR_LIT> : <STR_LIT> ) , Out ) . addReg ( Reg ) . addImm ( Lane ) ) ; return


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasAVX ( ) ) { int Idx = CostTableLookup ( AVXAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVXAltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSE41AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSE41 ( ) ) { int Idx = CostTableLookup ( SSE41AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE41AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSSE3AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSSE3 ( ) ) { int Idx = CostTableLookup ( SSSE3AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSSE3AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSEAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; int Idx = CostTableLookup ( SSEAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSEAltShuffleTbl [ Idx ] . Cost ; return BaseT :: getShuffleCost ( Kind , Tp ,


<s> if ( Inputs [ i ] . isUndef ( ) ) for ( int & M : Mask ) if ( ( lo <= M ) && ( M < hi ) ) M = SM_SentinelUndef ; if ( any_of ( Mask , [ lo , hi ] ( int i ) { return ( lo <= i ) && ( i < hi ) ; } ) ) { UsedInputs . push_back ( Inputs [ i ] ) ; continue ; } for ( int & M : Mask ) if ( lo <= M


<s> void setLocalStackSize ( uint64_t Size ) { LocalStackSize =


<s> const MCSymbolData & SymData = Asm . getSymbolData ( Sym ) ; IsResolved = ( SymData . getFragment ( ) == DF ) ; } if ( A && ( ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) ) IsResolved = false ; ( void ) adjustFixupValue ( Fixup , Value , false , & Asm . getContext (


<s> rtx tmp ; model = SYMBOL_REF_TLS_MODEL ( symbol ) ; if ( model ) tmp = legitimize_tls_address ( symbol , model , true ) ; else tmp = legitimize_pe_coff_symbol ( symbol , true ) ; if ( tmp ) { tmp = force_operand ( tmp , NULL ) ; tmp = expand_simple_binop ( Pmode , PLUS , tmp , addend , op0 , <NUM_LIT> , OPTAB_DIRECT ) ; if ( tmp == op0 ) return ; op1 = convert_to_mode ( mode , tmp , <NUM_LIT> ) ; } } if ( ( flag_pic || MACHOPIC_INDIRECT ) && symbolic_operand ( op1 , mode ) ) { if ( TARGET_MACHO && ! TARGET_64BIT ) { if ( MACHOPIC_INDIRECT ) { rtx temp = ( op0 && REG_P ( op0 ) && mode == Pmode ) ? op0 : gen_reg_rtx ( Pmode ) ; op1 = machopic_indirect_data_reference ( op1 , temp ) ; if ( MACHOPIC_PURE ) op1 = machopic_legitimize_pic_address ( op1 , mode , temp == op1 ? <NUM_LIT> : temp ) ; } if ( op0 != op1 && GET_CODE ( op0 ) != MEM ) { rtx insn = gen_rtx_SET ( op0 , op1 ) ; emit_insn ( insn ) ; return ; } if ( GET_CODE ( op0 ) == MEM ) op1 = force_reg ( Pmode , op1 ) ; else { rtx temp = op0 ; if ( GET_CODE ( temp ) != REG ) temp = gen_reg_rtx ( Pmode ) ; temp = legitimize_pic_address ( op1 , temp ) ; if ( temp == op0 ) return ; op1 = temp ; } } else { if ( MEM_P ( op0 ) ) op1 = force_reg ( mode , op1 ) ; else if ( ! ( TARGET_64BIT && x86_64_movabs_operand ( op1 , DImode ) ) ) { rtx reg = can_create_pseudo_p ( ) ? NULL_RTX : op0 ; op1 = legitimize_pic_address ( op1 , reg ) ; if ( op0 == op1 ) return ; op1 = convert_to_mode ( mode , op1 , <NUM_LIT> ) ; } } } else { if ( MEM_P ( op0 ) && ( PUSH_ROUNDING ( GET_MODE_SIZE ( mode ) ) != GET_MODE_SIZE ( mode ) || ! push_operand ( op0

, mode ) ) && MEM_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ;


<s> } else { unsigned OffHi = ( unsigned ) NumBytes >> <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> )

. addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) addPass ( create<ISA_LIT>PostLegalizeCombiner (


<s> static __inline qword si_from_double ( double d ) { union { qword q ; double d [ <NUM_LIT> ] ; } x ; x . d [ <NUM_LIT> ] = d ; return ( x .


<s> } } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = FUNCTION_ARG ( args_so_far , VOIDmode , void_type_node , <NUM_LIT> ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx insn , pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; insn = emit_insn ( pattern ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , NULL_RTX , REG_NOTES ( insn ) ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG ( gpr_mode ,


<s> case RT64_NONE : if ( Modifier == MCSymbolRefExpr :: VK_None ) return ELF :: R_<ISA_LIT>_64_NONE ; llvm_unreachable ( <STR_LIT> ) ; case RT64_64 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC64 : ELF :: R_<ISA_LIT>_64_64 ; case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC32 : ELF :: R_<ISA_LIT>_64_32 ; case RT64_32S : return ELF :: R_<ISA_LIT>_64_32S ; case RT64_16 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC16 : ELF :: R_<ISA_LIT>_64_16 ; case RT64_8 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_PC8 : ELF :: R_<ISA_LIT>_64_8 ; } llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_GOT : switch ( Type ) { case RT64_64 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC64 : ELF :: R_<ISA_LIT>_64_GOT64 ; case RT64_32 : return IsPCRel ? ELF :: R_<ISA_LIT>_64_GOTPC32 : ELF :: R_<ISA_LIT>_64_GOT32 ; case RT64_32S : case RT64_16 : case RT64_8 : case RT64_NONE : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT64_64 ) ; assert ( ! IsPCRel ) ; return ELF :: R_<ISA_LIT>_64_GOTOFF64 ; case MCSymbolRefExpr :: VK_TPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_TPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_TPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : case RT64_NONE : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_DTPOFF64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_DTPOFF32 ; case RT64_32S : case RT64_16 : case RT64_8 : case RT64_NONE : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_SIZE : assert ( ! IsPCRel ) ; switch ( Type ) { case RT64_64 : return ELF :: R_<ISA_LIT>_64_SIZE64 ; case RT64_32 : return ELF :: R_<ISA_LIT>_64_SIZE32 ; case RT64_32S : case RT64_16 : case RT64_8 : case RT64_NONE : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_64_TLSDESC_CALL ; case MCSymbolRefExpr :: VK_TLSDESC : return ELF :: R_<ISA_LIT>_64_GOTPC32_TLSDESC ; case MCSymbolRefExpr :: VK_TLSGD : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_TLSGD ; case MCSymbolRefExpr :: VK_GOTTPOFF : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_GOTTPOFF ; case MCSymbolRefExpr :: VK_TLSLD : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_TLSLD ; case MCSymbolRefExpr :: VK_PLT : checkIs32 ( Ctx , Loc , Type ) ; return ELF :: R_<ISA_LIT>_64_PLT32 ; case MCSymbolRefExpr :: VK_GOTPCREL : checkIs32 ( Ctx , Loc , Type ) ; if ( ! Ctx . getAsmInfo ( ) -> canRelaxRelocations ( ) ) return ELF :: R_<ISA_LIT>_64_GOTPCREL ; switch ( Kind ) { default : return ELF :: R_<ISA_LIT>_64_GOTPCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_64_GOTPCRELX


<s> if ( ! speed_p || predictable_p ) return branch_costs -> predictable ; else return branch_costs


<s> inline vector signed int vec_vmsumshm ( vector signed short a1 , vector signed short a2 , vector signed int a3 ) { return ( vector signed int ) __builtin_altivec_vmsumshm ( ( vector signed short ) a1 , ( vector signed short )


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> || strncmp ( name , <STR_LIT> ,

<NUM_LIT> ) == <NUM_LIT> ) flags |= SECTION_BSS ;


<s> TargetRegistry :: RegisterDCInstrSema ( The<ISA_LIT>_64Target , create<ISA_LIT>DCInstrSema ) ; TargetRegistry :: RegisterDCRegisterSema ( The<ISA_LIT>_64Target ,


<s> ConstantSDNode * CN ; if ( And0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And0 . getOperand ( <NUM_LIT> ) ) ) || ! IsShiftedMask ( ~ CN -> getSExtValue ( ) , SMPos0 , SMSize0 ) ) return SDValue ( ) ; if ( And1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! IsShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand (


<s> InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC


<s> static SDValue combineMaskedLoad ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { MaskedLoadSDNode * Mld = cast < MaskedLoadSDNode > ( N ) ; if ( Mld -> isExpandingLoad ( ) ) return SDValue ( ) ; if ( Mld -> getExtensionType ( ) == <STR_LIT> ) { if ( SDValue ScalarLoad = reduceMaskedLoadToScalarLoad ( Mld , DAG , DCI ) ) return ScalarLoad ; if ( ! Subtarget . hasAVX512 ( ) ) if ( SDValue Blend

= combineMaskedLoadConstantMask ( Mld , DAG , DCI ) ) return Blend ;


<s> rtx mmix_dynamic_chain_address ( rtx


<s> static void nds32_emit_mem_move ( rtx src , rtx dst , enum machine_mode mode , int addr_offset ) { gcc_assert ( MEM_P ( src ) && MEM_P ( dst ) ) ; rtx tmp_reg = gen_reg_rtx ( mode ) ; nds32_emit_load_store ( tmp_reg , src , mode , addr_offset , true ) ; nds32_emit_load_store ( tmp_reg , dst , mode , addr_offset


<s> static __inline__ float __fabsf ( float x ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r )


<s> if ( TheTriple . isOSDarwin ( ) ) return new <ISA_LIT>MCAsmInfoDarwin ( ) ; return new <ISA_LIT>ELFMCAsmInfo (


<s> SDValue rd = DAG . getNode ( <STR_LIT> , dl , Tys , & TheChain , <NUM_LIT> ) ; SDValue rax = DAG . getCopyFromReg ( rd , dl , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; SDValue rdx = DAG . getCopyFromReg ( rax . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , rax . getValue ( <NUM_LIT> ) ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rax ,

Tmp ) , rdx . getValue ( <NUM_LIT> ) } ;


<s> rtx ix86_tls_module_base ( void ) { if ( ! ix86_tls_module_base_symbol ) { ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( ix86_tls_module_base_symbol ) |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT ; } return ix86_tls_module_base_symbol


<s> MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } NumBytes = - MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI ,


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand (


<s> case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static bool loongarch_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS args ; cumulative_args_t cum = pack_cumulative_args ( & args ) ; memset ( & args , <NUM_LIT> , sizeof ( args ) ) ; function_arg_info arg ( const_cast < tree > ( type ) , true ) ; return loongarch_pass_by_reference ( cum


<s> uint8_t Type = Symbol -> getType ( ) ; if ( Type != ELF :: STT_FUNC ) return ; if ( isMicro<ISA_LIT>Enabled ( ) ) Symbol -> setOther (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemOffset ( ) ) ; ( void ) CE ; assert ( ( CE || CE -> getValue ( ) == <NUM_LIT> ) &&


<s> SDValue EXTRACT_VECTOR_ELT ( SDValue Vec , unsigned


<s> rtx freg = gen_reg_rtx ( V4SFmode ) ; rtx sreg = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx cvt = ( ( TARGET_XSCVDPSPN ) ? gen_vsx_xscvdpspn_scalar ( freg , sreg ) : gen_vsx_xscvdpsp_scalar ( freg , sreg ) ) ; emit_insn ( cvt ) ; emit_insn ( gen_vsx_xxspltw_v4sf_direct ( target , freg , const0_rtx ) ) ; } else { rtx dbl_even = gen_reg_rtx ( V2DFmode ) ; rtx dbl_odd = gen_reg_rtx ( V2DFmode ) ; rtx flt_even = gen_reg_rtx ( V4SFmode ) ; rtx flt_odd = gen_reg_rtx ( V4SFmode ) ; rtx op0 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op1 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op2 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op3 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; emit_insn ( gen_vsx_concat_v2sf ( dbl_even , op0 , op1 ) ) ; emit_insn ( gen_vsx_concat_v2sf ( dbl_odd , op2 , op3 ) ) ; emit_insn ( gen_vsx_xvcvdpsp ( flt_even , dbl_even ) ) ; emit_insn ( gen_vsx_xvcvdpsp ( flt_odd , dbl_odd ) ) ; rs6000_expand_extract_even ( target , flt_even , flt_odd ) ; } return ; } if ( all_same && GET_MODE_SIZE ( inner_mode ) <= <NUM_LIT> ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( target , mem


<s> unsigned int startbit , endbit ; int intregs , intoffset ; machine_mode mode ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , <NUM_LIT> ) ; if ( mode == BLKmode ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; } } startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; cum -> words += intregs ; if ( ( unsigned ) cum -> words < ( endbit / BITS_PER_WORD ) ) { int pad = ( endbit / BITS_PER_WORD ) - cum -> words ; cum -> words +=


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; std :: map < unsigned , Chain * > ActiveChains ; std :: vector < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( std :: move ( Cs ) ) ; } llvm :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front ( ) ) ; }


<s> } MCValue Res ; bool Relocatable = Expr -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ; if ( ! Relocatable || Res . getSymB ( ) ) return false ; if ( ! Res . getSymA ( ) && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) return false ; if ( Res . getSymA ( ) ) DarwinRefKind = Res . getSymA ( ) -> getKind ( ) ; Addend = Res .


<s> bool MadeChange = false ; if ( ! L -> empty ( ) ) return MadeChange ; SmallPtrSet < const Value * , <NUM_LIT> > EphValues ; CodeMetrics :: collectEphemeralValues ( L , AC , EphValues ) ; CodeMetrics Metrics ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) if ( CallInst * CI = dyn_cast < CallInst > ( J ) ) if ( Function * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return MadeChange ; Metrics . analyzeBasicBlock ( * I , * TTI , EphValues ) ; } unsigned LoopSize = Metrics . NumInsts ; if ( ! LoopSize ) LoopSize = <NUM_LIT> ; unsigned ItersAhead = PrefDist / LoopSize ; if ( ! ItersAhead ) ItersAhead = <NUM_LIT> ; SmallVector < std :: pair < Instruction * , const SCEVAddRecExpr * > , <NUM_LIT> > PrefLoads ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { Value * PtrValue ; Instruction *


<s> return ( uint32x2_t ) ( __a >= <NUM_LIT>


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr


<s> unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ; unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) MIB

. addOperand ( MI -> getOperand ( i ) ) ;


<s> bool Thumb1FrameLowering :: needPopSpecialFixUp ( const MachineFunction & MF ) const { <ISA_LIT>FunctionInfo * AFI = const_cast < MachineFunction * > ( & MF ) -> getInfo <


<s> PM . add ( createBasicTargetTransformInfoPass ( this ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; int LRIdx = <NUM_LIT> ; Optional < int > FpOffset ; for ( auto & MO : MI . operands ( ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) == <STR_LIT> ) LRIdx = Regs . size ( ) ; Regs . push_back ( MO . getReg ( ) ) ; } else if ( MO . isImm ( ) ) { FpOffset = MO . getImm ( ) ; } } int Size = ( int ) Regs . size ( ) ; if ( Size == <NUM_LIT> ) return false ; assert ( Size % <NUM_LIT> == <NUM_LIT> ) ; assert ( MI . getOpcode ( ) == <STR_LIT> ) ; if ( FpOffset && shouldUseFrameHelper ( MBB , NextMBBI , Regs , FrameHelperType :: PrologFrame ) ) { emitStore ( MF , MBB , MBBI , * TII , <STR_LIT> , <STR_LIT> , - LRIdx - <NUM_LIT> , true ) ; auto * PrologFrameHelper = getOrCreateFrameHelper ( M , MMI , Regs , FrameHelperType :: PrologFrame , * FpOffset ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( PrologFrameHelper ) . setMIFlag ( MachineInstr :: FrameSetup ) . copyImplicitOps (

MI ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> return DecodeMemAS ( Inst , insn , Address , Decoder


<s> if ( ! SCALAR_FLOAT_TYPE_P ( fromtype ) || ! SCALAR_FLOAT_TYPE_P ( type ) ) return NULL_TREE ; if ( ( TYPE_PRECISION ( fromtype ) == <NUM_LIT> && TYPE_PRECISION ( type ) > <NUM_LIT> ) || ( TYPE_PRECISION ( type ) == <NUM_LIT> && TYPE_PRECISION ( fromtype ) > <NUM_LIT>

) ) return convert ( type , convert ( float_type_node , expr ) ) ;


<s> switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand ::


<s> Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf = false ; return


<s> if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM )


<s> MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , Get<ISA_LIT>GVSymbol ( MO . getGlobal ( ) , MO . getTargetFlags ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO


<s> unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; std :: pair < unsigned , unsigned > Opcodes = getMFHiLoOpc ( Src ) ; if ( ! Opcodes . first ) return false ; return expandCopyACC ( MBB , I , Opcodes . first ,


<s> return ( __m128d ) __builtin_ia32_cmpltpd ( ( __v2df ) __A , ( __v2df )


<s> case OPT_m4_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_SINGLE_ONLY ; return true ; case OPT_m4a : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A ; return true ; case OPT_m4a_nofpu : case OPT_m4al : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_NOFPU ; return true ; case OPT_m4a_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_SINGLE ; return true ; case OPT_m4a_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_SINGLE_ONLY ; return true ; case OPT_m5_32media : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_32MEDIA ; return true ; case OPT_m5_32media_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_32MEDIA_NOFPU ; return true ; case OPT_m5_64media : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_64MEDIA ; return true ; case OPT_m5_64media_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_64MEDIA_NOFPU ; return true


<s> int <ISA_LIT>CodeEmitter :: emitUSH ( const MachineInstr & MI ) { unsigned src = getMachineOpValue ( MI , MI . getOperand ( <NUM_LIT> ) ) ; unsigned base = getMachineOpValue ( MI , MI . getOperand ( <NUM_LIT> ) ) ; unsigned offset = getMachineOpValue ( MI , MI . getOperand


<s> if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i !=

e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ;


<s> int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << formatHex ( ( uint64_t ) Address ) ; } else { O << * Op .


<s> return ( __m256i ) __builtin_ia32_broadcastmb256 (


<s> unsigned <STR_LIT> ( unsigned Opcode , Type * Ty , OperandValueKind Op1Info , OperandValueKind Op2Info , OperandValueProperties Opd1PropInfo , OperandValueProperties Opd2PropInfo ) const { int ISDOpcode = TLI -> InstructionOpcodeToISD ( Opcode ) ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry < <STR_LIT> > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx =


<s> static SDValue lowerShuffleAsZeroOrAnyExtend ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { int Bits = VT . getSizeInBits ( ) ; int NumLanes = Bits / <NUM_LIT> ; int NumElements = VT . getVectorNumElements ( ) ; int NumEltsPerLane = NumElements / NumLanes ; assert ( VT . getScalarSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ( int ) Mask . size ( ) == NumElements && <STR_LIT> ) ; auto Lower = [ & ] ( int Scale ) -> SDValue { SDValue InputV ; bool AnyExt = true ; int Offset = <NUM_LIT> ; int Matches = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < NumElements ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( i % Scale != <NUM_LIT> ) { if ( ! Zeroable [ i ] ) return SDValue ( ) ; AnyExt = false ; continue ; } SDValue V = M < NumElements ? V1 : V2 ; M = M % NumElements ; if ( ! InputV ) { InputV = V ; Offset = M - ( i / Scale ) ; } else if ( InputV != V ) return SDValue ( ) ; if ( ! ( ( <NUM_LIT> <= Offset && Offset < NumEltsPerLane ) || ( Offset % NumEltsPerLane ) == <NUM_LIT> ) ) return SDValue ( ) ; if ( Offset && ( Offset / NumEltsPerLane ) != ( M /


<s> MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else { ReplaceVCMPWithVPT ( VCMP , VCMP ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert ( VPST ) ; } else if ( Block . containsVCTP ( ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( Block . size ( ) == <NUM_LIT> ) { assert ( VPST -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; LoLoop . ToRemove . insert ( VPST ) ; } else LoLoop . BlockMasksToRecompute . insert ( VPST ) ; } else if ( Insts . front ( ) -> getOpcode ( ) == <STR_LIT> ) { MachineInstr * VPST = Insts . front ( ) ; auto Next = ++ MachineBasicBlock :: iterator ( VPST ) ; assert ( getVPTInstrPredicate ( * Next ) != <STR_LIT> && <STR_LIT> ) ; ( void ) Next ; MachineInstr * VprDef = RDA -> getUniqueReachingMIDef ( VPST , <STR_LIT> ) ; if ( VprDef && VCMPOpcodeToVPT ( VprDef -> getOpcode ( ) ) && ! LoLoop . ToRemove . contains ( VprDef ) ) { MachineInstr * VCMP = VprDef ; if ( std :: none_of ( ++ MachineBasicBlock :: iterator ( VCMP ) , MachineBasicBlock :: iterator ( VPST ) , hasVPRUse ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReplaceVCMPWithVPT ( VCMP , VPST ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert


<s> OffsetStride = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OffsetStride = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OffsetStride = <NUM_LIT> ; break ; } if ( Offset % OffsetStride != <NUM_LIT> ) return false ; Offset /= OffsetStride ; return


<s> static int mips_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { struct mips_arg_info info


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success


<s> if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) { lo = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; hi = gen_rtx_HIGH (


<s> llvm :: MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & InstrInfo , const MCRegisterInfo & , MCContext & context ) { return new <ISA_LIT>MCCodeEmitter ( InstrInfo , context


<s> Index = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: RBrac ) ) { LaneKind = AllLanes ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; const MCExpr * LaneIndex ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( LaneIndex ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LaneIndex ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; int64_t Val = CE -> getValue


<s> if ( satisfies_constraint_Is15 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> , this_regno , this_regno , delta ) ; } else if ( satisfies_constraint_Is20 ( GEN_INT ( delta ) ) ) { fprintf ( file , <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } else { fprintf ( file , <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , delta ) ; fprintf ( file , <STR_LIT> , this_regno , this_regno ) ; } } fprintf ( file


<s> return ( ( int_size_in_bytes ( type ) > ( <NUM_LIT> * UNITS_PER_WORD ) ) ||

( int_size_in_bytes ( type ) == - <NUM_LIT> ) ) ;


<s> bool isRegExtendLSL ( ) const { if ( ! isShiftOrExtend ( ) ) return false ; if ( ShiftExtend . ShiftType != <STR_LIT> )


<s> MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; assert ( MBBI != Entry -> end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ; MBBI -> eraseFromParent ( ) ; bool RemovedAllMTVRSAVEs = true ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } } RemovedAllMTVRSAVEs &= FoundIt ; } } if ( RemovedAllMTVRSAVEs ) { MBBI = MI ; assert ( MBBI != Entry -> begin ( ) && <STR_LIT> ) ; -- MBBI ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MBBI -> eraseFromParent (


<s> emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ <NUM_LIT> ) != <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( VOIDmode , temp3 , gen_safe_OR64 ( temp2 , ( low_bits & <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( <NUM_LIT> - <NUM_LIT> ) ) & <NUM_LIT> ) ; rtx low2 = GEN_INT ( ( low_bits >> ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ) & <NUM_LIT> ) ; rtx low3 = GEN_INT ( ( low_bits >> ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ) & <NUM_LIT> ) ; int to_shift = <NUM_LIT> ; if ( low1 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low1 ) ) ) ; sub_temp = op0 ; to_shift = <NUM_LIT> ; } else { to_shift += <NUM_LIT> ; } if ( low2 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low2 ) ) ) ; sub_temp = op0 ; to_shift = <NUM_LIT> ; } else { to_shift += <NUM_LIT> ; } emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode ,


<s> vmvnq_s32 ( int32x4_t a ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) :


<s> } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = SI


<s> FOR_EACH_SUBRTX ( i , array , SET_SRC ( s ) , ALL ) if ( * i != NULL && ( ( REG_P ( * i ) || SUBREG_P ( * i ) ) &&

reg_set_between_p ( * i , from , to ) ) ) return true ;


<s> EVT RetVT = N -> getValueType ( <NUM_LIT> ) ; assert ( RetVT . isScalableVector ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; MVT RetElVT = RetVT . getVectorElementType ( ) . getSimpleVT ( ) ; unsigned NumElements = <STR_LIT> / RetElVT . getSizeInBits ( ) ; EVT MaxVT = llvm :: <STR_LIT> ( RetElVT , NumElements ) ; if ( RetVT . getSizeInBits ( ) . getKnownMinSize ( ) > MaxVT . getSizeInBits ( ) . getKnownMinSize ( ) ) return SDValue ( ) ; const SDValue Base = N -> getOperand ( <NUM_LIT> ) ; const SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Base . getValueType ( ) ) || ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Offset . getValueType ( ) ) ) return SDValue ( ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType ( HwRetVt ) ; SDVTList VTs = DAG . getVTList ( HwRetVt


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return SelectIndexedLoad ( N ) ; case <STR_LIT> : return SelectIndexedStore ( N ) ; case <STR_LIT> : return SelectFrameIndex ( N ) ; case <STR_LIT> : return ConstantToRegisterExpand ( N , SDValue ( N , <NUM_LIT> ) ) . getNode ( ) ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SelectTargetGlobalAddressforADD ( N , N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; break ; case <STR_LIT> : return SelectCompare ( N ) ; case <STR_LIT> : return SelectConditionalBranch ( N ) ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; unsigned char TargetFlags =


<s> static inline int is_multilib_enabled ( struct loongarch_abi abi ) { return enabled_abi_types [ abi . base ] [ abi . ext


<s> SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasInt256 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasBWI ( ) ) ) { if ( matchShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> == EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ; return true ; } } if ( ( EltSizeInBits % V1 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> && ( EltSizeInBits % V2 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> ) { bool IsBlend = true ; unsigned NumV1Elts = V1 . getValueType ( ) . getVectorNumElements ( ) ; unsigned NumV2Elts = V2 . getValueType ( ) . getVectorNumElements ( ) ; unsigned Scale1 = NumV1Elts / NumMaskElts ; unsigned Scale2 = NumV2Elts / NumMaskElts ; APInt DemandedZeroV1 = APInt :: getNullValue ( NumV1Elts ) ; APInt DemandedZeroV2 = APInt :: getNullValue ( NumV2Elts ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; if ( M == SM_SentinelZero ) { DemandedZeroV1 . setBits ( i * Scale1 , ( i + <NUM_LIT> ) * Scale1 ) ; DemandedZeroV2 . setBits ( i * Scale2 , ( i + <NUM_LIT> ) * Scale2 ) ; continue ; } if ( M == ( int ) i ) { DemandedZeroV2 . setBits ( i * Scale2 , ( i + <NUM_LIT> ) * Scale2 ) ; continue ; } if ( M == ( int ) ( i + NumMaskElts ) ) { DemandedZeroV1 . setBits ( i * Scale1 , ( i + <NUM_LIT> ) * Scale1 ) ; continue ; } IsBlend =


<s> bool <ISA_LIT>BaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) ) ) return false ; if ( STI . isGPRegisterReserved ( BasePtr - <STR_LIT> ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg