<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg


<s> } case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <ISA_LIT>ScalarSSEf32 ? ( Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; case <STR_LIT> : Opc = <ISA_LIT>ScalarSSEf64 ? ( Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT>


<s> void <ISA_LIT>Operand :: print ( raw_ostream & OS ) const { llvm_unreachable ( <STR_LIT>


<s> case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT>


<s> Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps ,


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS ,

bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) {


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeGPRRegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Ry + Imm5 ] ) ) ; return MCDisassembler ::


<s> static bool isSHUFPMask ( const SmallVectorImpl < int > & Mask , MVT VT ) { int NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; int Half = NumElems / <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Half ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , NumElems ) ) return false ; for ( int i = Half ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [

i ] , NumElems , NumElems * <NUM_LIT> ) ) return false ;


<s> Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = FixedVectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT>


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_UADDE ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar


<s> HABaseType Base = HA_UNKNOWN ; uint64_t Members = <NUM_LIT> ; bool result = isHomogeneousAggregate ( Ty , Base , Members ) ; DEBUG ( dbgs ( ) << <STR_LIT> << result << <STR_LIT> ; Ty -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; return


<s> return ( uint8x8_t ) __builtin_neon_vqshluv8qi ( ( int8x8_t )


<s> setKillFlags ( BB ) ; setupBlockStack ( ) ; for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ++ I ) { MachineInstr & MI = * I ; uint64_t Flags = MI . getDesc ( ) . TSFlags ; unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI . isInlineAsm ( ) ) FPInstClass = <STR_LIT> ; if ( MI . isCopy ( ) && isFPCopy ( MI ) ) FPInstClass = <STR_LIT> ; if ( MI . isImplicitDef ( ) && <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) FPInstClass = <STR_LIT> ; if ( MI . isCall ( ) ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = nullptr ; if ( I != BB . begin ( ) ) PrevMI = & * std :: prev ( I ) ; ++ NumFP ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs


<s> RetRegs . push_back ( RetReg ) ; } else { Register Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register TmpReg = createResultReg ( RC


<s> unsigned Hi4 = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; unsigned Lo12 = Value & <NUM_LIT> ; Value = ( Hi4 << <NUM_LIT> ) | ( Lo12 ) ; } return


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> <STR_LIT> getExtendForAtomicOps ( ) const override { return


<s> Ld = NarrowVectorLoadToElement ( cast < LoadSDNode > ( Ld ) , DestIndex , DAG ) ; SDValue LoadScalarToVector = DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand

( <NUM_LIT> ) , LoadScalarToVector , N -> getOperand ( <NUM_LIT> ) ) ;


<s> Register BitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NegBitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned LOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; unsigned CSOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigOldVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register CmpVal = MRI . createVirtualRegister ( RC ) ; Register SwapVal = MRI . createVirtualRegister ( RC ) ; Register StoreVal = MRI . createVirtualRegister ( RC ) ; Register RetryOldVal = MRI . createVirtualRegister ( RC ) ; Register RetryCmpVal = MRI . createVirtualRegister ( RC ) ; Register RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = <STR_LIT> ( MI , MBB ) ; MachineBasicBlock * LoopMBB = <STR_LIT> ( StartMBB ) ; MachineBasicBlock * SetMBB = <STR_LIT> ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor (


<s> if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS

( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS ) ) return <NUM_LIT> ;


<s> bool IdxRegKill = true ; if ( isThumb2 ) { IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool PreservedBaseReg = preserveBaseRegister ( MI , User . MI , DeadSize , CanDeleteLEA , BaseRegKill ) ; if ( ! jumpTableFollowsTB ( MI , User . CPEMI ) && ! PreservedBaseReg ) continue ; } else { unsigned BaseReg = User . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( User . MI -> getIterator ( ) == User . MI -> getParent ( ) -> begin ( ) ) continue ; MachineInstr * Shift = User . MI -> getPrevNode ( ) ; if ( Shift -> getOpcode ( ) != <STR_LIT> || Shift -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || ! Shift -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; IdxReg = Shift -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShiftedIdxReg = Shift -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == IdxReg && ! jumpTableFollowsTB ( MI , User . CPEMI ) ) continue ; MachineInstr * Load = User . MI -> getNextNode ( ) ; if ( Load -> getOpcode ( ) != <STR_LIT> ) continue ; if ( Load -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || Load -> getOperand ( <NUM_LIT> ) . getReg ( ) != ShiftedIdxReg || ! Load -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; auto * TRI = STI -> getRegisterInfo ( ) ; if ( registerDefinedBetween ( BaseReg , Load -> getNextNode ( ) , MBB -> end ( ) , TRI ) ) continue ; if ( isPositionIndependent_ROPI_PIP ) { MachineInstr * Add = Load -> getNextNode ( ) ; if ( Add -> getOpcode ( ) != <STR_LIT> || Add -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || Add -> getOperand ( <NUM_LIT> ) . getReg ( ) != Load -> getOperand ( <NUM_LIT> ) . getReg ( ) || ! Add -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) continue ; if ( registerDefinedBetween ( IdxReg , Add -> getNextNode ( ) , MI , TRI ) ) continue ; Add -> eraseFromParent ( ) ; DeadSize += <NUM_LIT> ; } else { if ( Load -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT>


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI , bool IsLittleEndian , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI ,

( Is64Bit ) ? true : false , IsLittleEndian ) ;


<s> std :: string FS ; if ( TT . isArch64Bit ( ) ) FS = <STR_LIT> ; else if ( TT . getEnvironment ( ) != Triple :: CODE16 ) FS = <STR_LIT> ; else FS = <STR_LIT>


<s> const unsigned RemainingPrefixSize = [ & ] ( ) -> unsigned { SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ; Emitter . emitPrefix ( RF . getInst ( ) , VecOS , STI ) ; assert ( Code . size ( ) < <NUM_LIT> && <STR_LIT> ) ; unsigned ExistingPrefixSize = Code . size ( ) ; if ( TargetPrefixMax <= ExistingPrefixSize ) return <NUM_LIT> ; return TargetPrefixMax - ExistingPrefixSize ; } ( ) ; const unsigned PrefixBytesToAdd = std :: min ( MaxPossiblePad , RemainingPrefixSize ) ; if ( PrefixBytesToAdd == <NUM_LIT> ) return false ; const uint8_t Prefix = determinePaddingPrefix ( RF . getInst ( ) ) ; SmallString < <NUM_LIT> > Code ; Code . append (


<s> return ( __mmask64 ) __builtin_ia32_cmpb512_mask ( ( __v64qi ) __X , ( __v64qi )


<s> SMLoc RegEndLoc2 , LayoutLoc2 ; SMLoc RegLoc2 = Parser . getTok ( ) . getLoc ( ) ; if ( ! TryParseVector ( Reg2 , RegEndLoc2 , LayoutStr2 , LayoutLoc2 ) ) return MatchOperand_ParseFail ; unsigned Space = ( Reg < Reg2 ) ? ( Reg2 - Reg ) : ( Reg2 + <NUM_LIT> - Reg ) ; if ( LayoutStr != LayoutStr2 ) { Error ( LayoutLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { Error ( RegLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += Space ; } else { unsigned LastReg = Reg ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; unsigned Reg2 ; StringRef LayoutStr2 ; SMLoc RegEndLoc2 , LayoutLoc2 ; SMLoc RegLoc2 = Parser . getTok ( ) . getLoc ( ) ; if ( ! TryParseVector ( Reg2 , RegEndLoc2 , LayoutStr2 , LayoutLoc2 ) ) return MatchOperand_ParseFail ; unsigned Space = ( LastReg < Reg2 ) ? ( Reg2 - LastReg ) : ( Reg2 + <NUM_LIT> - LastReg ) ; Count ++ ; if ( Space != <NUM_LIT> ) { Error ( RegLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( LayoutStr != LayoutStr2 ) { Error ( LayoutLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Count > <NUM_LIT> ) { Error ( RegLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } LastReg =


<s> PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] .

getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ;


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ? nelt : <NUM_LIT> ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * <NUM_LIT> + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != <NUM_LIT> ) std :: swap ( in0 ,


<s> BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addReg ( Mask2 ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addReg ( ShiftNewVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( SC ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop2MBB , DL , TII -> get ( BEQ ) ) . addReg ( Dest , RegState :: Kill ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; loop2MBB -> addLiveIn ( Ptr ) ; loop2MBB -> addLiveIn ( Mask2 ) ; loop2MBB -> addLiveIn ( Dest ) ; loop2MBB -> addLiveIn ( ShiftNewVal ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Mask ) . addReg ( ShiftAmnt ) ; if ( STI -> has<ISA_LIT>32r2 ( ) ) { BuildMI ( sinkMBB , DL , TII -> get ( SEOp ) , Dest ) . addReg ( Dest ) ; } else { const unsigned ShiftImm = I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; } sinkMBB -> addLiveIn ( Mask ) ; sinkMBB -> addLiveIn ( ShiftAmnt ) ; addPostLoopLiveIns ( exitMBB , LiveRegs ) ; exitMBB -> addLiveIn ( Dest ) ; NMBBI = BB .


<s> if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode )


<s> int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( TIP . first

) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ;


<s> switch ( Kind ) { case VK_<ISA_LIT>_LO : return Value & <NUM_LIT> ; case VK_<ISA_LIT>_HI : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHER : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHERA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHEST : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHESTA


<s> if ( VTy -> getElementType ( ) == Type :: getBFloatTy ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getHalfTy ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt64Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt32Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt16Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType (


<s> return __builtin_neon_usdotv16qi_ssus ( __r ,


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm =


<s> PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> if ( hint ) inform ( input_location , <STR_LIT> <STR_LIT> , s , hint ) ; else inform ( input_location , <STR_LIT> , s ) ; XDELETEVEC (


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N0 ) , DAG . getBitcast ( <STR_LIT> , N1 ) ) ) ; } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N


<s> float64x2x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v2df ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregxiv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregxiv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregxiv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregxiv2df ( __o , <NUM_LIT>


<s> static int nds32_address_cost ( rtx address , machine_mode mode , addr_space_t as , bool speed ) { return nds32_address_cost_impl ( address , mode ,


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( hasFP ( MF ) ) MRI .


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr


<s> unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI

, MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( <NUM_LIT> ) .


<s> for ( unsigned i = <NUM_LIT> ; i < e ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < e ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( e + i ) , i ) ) return false ; return


<s> switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T


<s> } } SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; SmallVector < unsigned , <NUM_LIT> > ImpDefs ; SmallVector < MachineOperand * , <NUM_LIT> > UsesOfImpDefs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; for ( MIOperands MO ( memOps [ i ] . MBBI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) || ! MO -> isImplicit ( ) || MO -> isDead ( ) ) continue ; unsigned DefReg = MO -> getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) == ImpDefs . end ( ) ) ImpDefs . push_back ( DefReg ) ; findUsesOfImpDef ( UsesOfImpDefs , memOps , DefReg , memOps [ i ] .


<s> if ( __N < <NUM_LIT> ) if ( __builtin_constant_p ( __N ) ) result = vec_sld ( zeros , ( __v16qu ) __A , ( <NUM_LIT> - __N ) ) ; else { __v16qu shift = vec_splats ( ( unsigned char ) ( __N * <NUM_LIT> ) ) ; result = vec_sro ( ( __v16qu ) __A , shift ) ; } else result = zeros ; return ( __m128i


<s> FunctionPass * llvm :: create<ISA_LIT>AtomicExpandPass ( const <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>AtomicExpandPass (


<s> rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( <NUM_LIT> , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( op0


<s> if ( ! isMul4 ) { Bytes &= ~ <NUM_LIT> ; ExtraOpc = <STR_LIT> ; } NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = <STR_LIT> ; } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; if ( DestReg == <STR_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedPred = NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , DestReg , BaseReg , NumBytes , true , TII , MRI , dl ) ; return ; } if ( DstNotEqBase ) { if ( is<ISA_LIT>LowRegister ( DestReg ) && is<ISA_LIT>LowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; const TargetInstrDesc & TID = TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TID , DestReg ) ) ; AddDefaultPred ( MIB . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; } BaseReg = DestReg


<s> uint64_t getPC32DBLEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const


<s> bool <ISA_LIT>SelectionDAGInfo :: isBaseRegConflictPossible ( SelectionDAG & DAG , ArrayRef < unsigned > ClobberSet ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasInlineAsmWithSPAdjust ( ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned BaseReg = TRI -> getBaseRegister ( ) ; for ( unsigned R : ClobberSet ) if ( BaseReg == R )


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success ; } if ( RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo , Address ,


<s> Reg = mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return nullptr


<s> bool isInteger_32 ( InstType InstTy , unsigned OpSize ) const { if ( InstTy == InstType :: Integer &&


<s> static unsigned aarch64_next_callee_save ( unsigned regno ,


<s> case <NUM_LIT> : AliasReg = Subtarget -> getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ; } case <STR_LIT> : { StoreSDNode * SD = dyn_cast < StoreSDNode > ( Parent ) ; switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = Subtarget -> getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg


<s> const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool isZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = EmitIntExt ( RVVT , SrcReg , DestVT , isZExt


<s> return ( __mmask64 ) __builtin_ia32_kmovq ( *


<s> return ( __m512i ) __builtin_ia32_pmovzxbw512_mask ( ( __v32qi ) __A , ( __v32hi ) _mm512_setzero_hi ( ) , (


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue (


<s> return __builtin_loongson_psllh_s ( s


<s> NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NeedsWinCFI ) { auto SEH = std :: next ( MBBI ) ; if ( <ISA_LIT>InstrInfo :: isSEHInstruction ( * SEH ) ) SEH -> eraseFromParent ( ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( CSStackSizeInc % Scale == <NUM_LIT> ) ; MIB . addImm ( CSStackSizeInc / Scale ) ; MIB . setMIFlags ( MBBI -> getFlags ( ) ) ; MIB . setMemRefs ( MBBI -> memoperands ( ) ) ; if ( NeedsWinCFI ) InsertSEH ( * MIB , * TII , InProlog ? MachineInstr :: FrameSetup : MachineInstr :: FrameDestroy ) ; return std :: prev ( MBB . erase ( MBBI


<s> if ( RegInfo -> hasBasePointer ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) %


<s> static bool isCommutedMOVL ( ShuffleVectorSDNode * N , bool V2IsSplat = false , bool V2IsUndef = false ) { return isCommutedMOVLMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> ) , V2IsSplat


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> rtx body = PATTERN ( insn ) ; int elt = GET_CODE ( body ) == ADDR_DIFF_VEC ? <NUM_LIT> : <NUM_LIT> ; return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , elt ) ; } return <NUM_LIT>


<s> if ( ! MI -> isFullCopy ( ) ) return MI ; if ( ! TRI -> isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MachineInstr * Def = MRI -> getVRegDef ( MI ->

getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> switch ( rs6000_cpu_attr ) { case CPU_PPC8540 : case CPU_PPC8548 : return <NUM_LIT> ; case


<s> if ( Subtarget . hasVector ( ) ) VerifyVectorTypes ( Outs ) ; for ( auto & Out : Outs ) if ( Out . ArgVT == <STR_LIT> ) return false ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , isVarArg , MF ,


<s> static bool isSource ( Value * V ) { if ( ! isa < IntegerType > ( V -> getType ( ) ) ) return false ; if ( isa < Argument > ( V ) ) return true ; else if ( isa < LoadInst > ( V ) ) return true ; else if ( isa < BitCastInst > (


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; else { MRI . setPhysRegUnused ( <STR_LIT>


<s> bool <ISA_LIT>FastISel :: SelectIndirectBr ( const Instruction * I ) { unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; assert ( isThumb2 || Subtarget -> hasV4TOps ( ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst


<s> if ( GET_CODE ( set ) != SET ) return false ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { mem = & SET_DEST ( set ) ; reg = & SET_SRC ( set ) ; } else { reg = & SET_DEST ( set ) ; mem = & SET_SRC ( set ) ; if ( GET_CODE ( * mem ) == SIGN_EXTEND ) mem = & XEXP ( * mem , <NUM_LIT> ) ; } if ( GET_CODE ( * reg ) != REG || ! LOADABLE_CR_REGNO_P ( REGNO ( * reg ) ) ) return false ; if ( GET_CODE ( * mem ) != MEM || ! rtx_equal_p ( XEXP ( * mem , <NUM_LIT> ) , gpr ) ) return false ; mem_bytes = GET_MODE_SIZE ( GET_MODE ( * mem


<s> void <ISA_LIT>PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt ::


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ; return false


<s> machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( <NUM_LIT> , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixLoadStoreExclusive ( const MCInst & MI , unsigned EncodedValue ) const { if ( ! hasRs ) EncodedValue |= <NUM_LIT> ; if ( ! hasRt2


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI -> readsRegister ( Reg , TRI ) ) return <NUM_LIT> ; } return


<s> for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == <STR_LIT> ) { MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer


<s> x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( <NUM_LIT> , x )


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { if ( hasFP ( MF ) ) { int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject (


<s> if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % <NUM_LIT> == <NUM_LIT> ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % <NUM_LIT> == <NUM_LIT> ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode ) return ( ( regno - GP_REG_FIRST ) & <NUM_LIT> ) == <NUM_LIT> || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == <NUM_LIT> || ( MIN_FPRS_PER_FMT == <NUM_LIT> && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= <NUM_LIT> && ( regno & <NUM_LIT> ) != <NUM_LIT> ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & <NUM_LIT> ) != <NUM_LIT> ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * <NUM_LIT> ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * <NUM_LIT> && ( ( regno - DSP_ACC_REG_FIRST ) & <NUM_LIT> ) == <NUM_LIT> ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return

mclass == MODE_INT && size <= UNITS_PER_WORD ;


<s> & <STR_LIT> ) ; int64_t Imm = UseSExt ? CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ; return ImmReg


<s> StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & CTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , CPU , FS , CTM ) ; CTS . emitTargetAttributes ( STI


<s> return ( __m512i ) __builtin_ia32_vcvttph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( )

, ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> return ( int32x2_t ) __builtin_neon_vreinterpretv2siv8qi ( ( int8x8_t


<s> void <ISA_LIT>AnalyzeImmediate :: ReplaceADDiuSLLWithLUi ( InstSeq & Seq ) { if ( ( Seq . size ( ) < <NUM_LIT> ) || ( Seq [ <NUM_LIT> ] . Opc != ADDiu ) || ( Seq [ <NUM_LIT> ] . Opc != SLL ) || ( Seq [ <NUM_LIT> ] . ImmOpnd < <NUM_LIT> ) ) return ; int64_t Imm = ( ( ( int64_t ) Seq [ <NUM_LIT> ] . ImmOpnd ) << <NUM_LIT> ) >> <NUM_LIT> ; int64_t ShiftedImm = Imm << ( Seq [ <NUM_LIT> ] . ImmOpnd - <NUM_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( ShiftedImm ) ) return ; Seq [ <NUM_LIT> ] . Opc = LUi ; Seq [ <NUM_LIT> ] . ImmOpnd = ( unsigned ) ( ShiftedImm & <NUM_LIT> ) ; Seq . erase ( Seq . begin ( ) +


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createMicro<ISA_LIT>SizeReductionPass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( create<ISA_LIT>HazardSchedule ( ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( )


<s> int8x16_t result = vcombine_s8 ( a , vcreate_s8 ( __AARCH64_UINT64_C (


<s> return V4SFmode ; case TImode : return V1TImode ; case DImode : return V2DImode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; default : ; } if ( TARGET_SPE ) switch ( mode ) { case SFmode : return V2SFmode ; case SImode : return V2SImode ; default


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>Target , create<ISA_LIT>AsmStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target


<s> if ( mt_nops_required ) fprintf ( f , <STR_LIT> , mt_nops_required , mt_nop_reasons ) ; while ( mt_nops_required ) { fprintf ( f ,


<s> return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; case llvm :: <STR_LIT> : return <STR_LIT> ; default : return <STR_LIT>


<s> int priority1 = rs6000_clone_priority ( decl1 ) ; int priority2 = rs6000_clone_priority ( decl2 ) ; int ret =


<s> getJumpTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects (


<s> encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst = MI ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerCompactBranch ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode =


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( ! Subtarget . hasDQI ( ) || SrcVT != <STR_LIT> || Subtarget . is64Bit ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) return SDValue ( ) ; unsigned NumElts = Subtarget . hasVLX ( ) ? <NUM_LIT> : <NUM_LIT> ; MVT VecInVT = <STR_LIT> ( <STR_LIT> , NumElts


<s> LongBrMBB -> addSuccessor ( BalTgtMBB ) ; BalTgtMBB -> addSuccessor ( TgtMBB ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned BalOp = <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else { BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; TgtMBB -> setAlignment ( MIPS_NACL_BUNDLE_ALIGN ) ; } } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( ) ; LongBrMBB -> addSuccessor ( TgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) )


<s> SmallVector < int , <NUM_LIT> > MaskVec ; SVOp -> getMask ( MaskVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( MaskVec [ i ] > ( int ) NumElems ) { MaskVec [ i ] = NumElems ; Changed = true ; } } if ( Changed ) return DAG . getVectorShuffle ( VT , SVOp -> getDebugLoc ( ) , SVOp -> getOperand ( <NUM_LIT> ) , SVOp -> getOperand ( <NUM_LIT> )


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> unsigned StackAlign = DL . getStackAlignment ( ) ; unsigned Align = std :: min ( PendingMembers [ <NUM_LIT> ] . getExtraInfo ( ) , StackAlign ) ; ArrayRef < MCPhysReg > RegList ; switch ( LocVT . SimpleTy ) { case <STR_LIT> : { RegList = RRegList ; unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; unsigned RegAlign = alignTo ( Align , <NUM_LIT> ) / <NUM_LIT> ; while ( RegIdx % RegAlign != <NUM_LIT> && RegIdx < RegList . size ( ) ) State . AllocateReg ( RegList [ RegIdx ++ ] ) ; break ; } case <STR_LIT> : case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) /


<s> static tree ix86_vector_shift_count ( tree arg1 ) { if ( tree_fits_uhwi_p ( arg1 ) ) return arg1 ; else if ( TREE_CODE ( arg1 ) == VECTOR_CST && CHAR_BIT == <NUM_LIT> ) { unsigned char buf [ <NUM_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; if ( ! Ld0 -> hasOneUse ( ) ||


<s> unsigned End = KillInst ? KillInstIdx : LastInstIdx ; unsigned OtherEnd = Other . KillInst ? Other . KillInstIdx : Other . LastInstIdx ; return StartInstIdx <= OtherEnd && Other .


<s> case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; } return


<s> for ( auto & MI : MBB ) { InstrPos [ & MI ] = Pos += <NUM_LIT> ; if ( isLEA ( MI ) ) LEAs [ getMemOpKey ( MI , <NUM_LIT> ) ] . push_back ( const_cast < MachineInstr * > ( &


<s> EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = CC . intArgRegs ( ) [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy ,

FIN , DAG . getConstant ( Offset , PtrTy ) ) ;


<s> const <ISA_LIT>TargetMachine & getTargetMachine (


<s> while ( V . getNode ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; return V


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand ::


<s> unsigned int uid = INSN_UID ( insn ) ; if ( NONDEBUG_INSN_P ( insn ) ) { insn_entry [ uid ] . insn = insn ; if ( GET_CODE ( insn ) == CALL_INSN ) insn_entry [ uid ] . is_call = <NUM_LIT> ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref mention ; FOR_EACH_INSN_INFO_USE ( mention , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REAL_REG ( mention ) ) ; if ( mode == DImode && DF_REF_INSN_INFO ( mention ) ) { rtx feeder = DF_REF_INSN ( mention ) ; if ( GET_CODE ( feeder ) == CALL_INSN ) mode = V4SImode ; } if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode || FLOAT128_VECTOR_P ( mode ) ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; union_defs ( insn_entry , insn , mention ) ; } } FOR_EACH_INSN_INFO_DEF ( mention , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REAL_REG ( mention ) ) ; if ( mode == DImode && GET_CODE ( insn ) == SET && ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( SET_DEST ( insn ) ) ) ) mode = GET_MODE ( SET_DEST ( insn ) ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode || FLOAT128_VECTOR_P ( mode ) ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; else if ( REG_FUNCTION_VALUE_P ( DF_REF_REG ( mention ) ) ) insn_entry [ uid ] . is_live_out = <NUM_LIT> ; union_uses ( insn_entry , insn , mention ) ; } } if ( insn_entry [ uid ] . is_relevant ) { insn_entry [ uid ] . is_load = insn_is_load_p ( insn ) ; insn_entry [ uid ] . is_store = insn_is_store_p ( insn ) ; if ( insn_is_swap_p ( insn ) ) insn_entry [ uid ] . is_swap = <NUM_LIT> ; else { unsigned int special =


<s> bool selectBDXAddr20Only128 ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p = strchr ( p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \

RS6000_OUTPUT_BASENAME ( FILE , buffer ) ; \ putc ( '\n' , FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ; return true


<s> int dimode_p = GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( <STR_LIT> , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) ; if ( fisttp ) output_asm_insn


<s> } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( isInt < <NUM_LIT> > ( Offset ) ) BuildMI ( MBB , II , dl , TII . get

( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( isN64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return NULL


<s> return ( __m512i ) __builtin_ia32_pbroadcastd512 ( ( __v4si ) __A , ( __v16si ) _mm512_undefined_si512 ( )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT>


<s> Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back ( Val ) ; } return Chain


<s> bool ProtectJTSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectJT ( ) ) return false ; bool modified = false ; for ( MachineFunction :: iterator MBB = Func . begin ( ) ; MBB != Func . end ( ) ; MBB ++ ) { MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != MBB -> end ( ) ) { MachineBasicBlock :: iterator NMI = std


<s> SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT>


<s> } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; if ( ConstSplatVal && ( Subtarget -> hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget -> hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment


<s> unsigned <ISA_LIT>CodeEmitter :: encodeNEONRm ( const MachineInstr & MI , unsigned OpIdx ) const { unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT>


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB


<s> bool useSoftFloat ( ) const { return STI . getFeatureBits (


<s> void <ISA_LIT>TargetStreamer :: AnnotateTLSDescriptorSequence ( const MCSymbolRefExpr * SRE ) { llvm_unreachable ( <STR_LIT>


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> ,


<s> if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; if ( Subtarget . hasVLX ( ) ) return SDValue ( ) ; MVT BlendVT = VT . is256BitVector ( ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT , Y ) ; Mask = DAG . getBitcast ( BlendVT , Mask ) ; Mask = DAG . getSelect ( DL , BlendVT , Mask , Y , X ) ; return DAG . getBitcast ( VT


<s> return ( int8x16_t ) __builtin_neon_vreinterpretv16qiv8hi (


<s> return false ; case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( <ISA_LIT>InstrInfo :: isVRRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; else if ( <ISA_LIT>InstrInfo :: isVFRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; const char * RegName ; RegName = <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; RegName = <ISA_LIT>RegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI ,


<s> } if ( GET_CODE ( src1 ) == MEM && GET_CODE ( src2 ) == MEM ) { if ( matching_memory != <NUM_LIT> ) src2 = force_reg ( mode , src2 ) ; else src1 = force_reg ( mode , src1 ) ; } if ( ( CONSTANT_P ( src1 ) || ( ! matching_memory && GET_CODE ( src1 ) == MEM ) ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) src1


<s> break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ExternalSymbol : if ( TF == <STR_LIT> ) O << <STR_LIT> << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) << <STR_LIT> ; else O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' <<


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MRI


<s> bool <ISA_LIT>AsmParser :: parseNeonVectorList ( OperandVector & Operands ) { auto ParseRes = tryParseVectorList < RegKind :: NeonVector > ( Operands , true ) ; if ( ParseRes != MatchOperand_Success


<s> CallInst * SetLength = B . CreateCall ( SetLengthFn , { BitCast , Size } ) ; if ( cheri :: ShouldCollectCSetBoundsStats ) { Value * AlignmentSource = BitCast ; Instruction * DebugInst = dyn_cast < Instruction > ( AlignmentSource ) ; if ( ! DebugInst ) DebugInst = InsertPt ; cheri :: addSetBoundsStats ( Align ( getKnownAlignment ( AlignmentSource , * TD ) ) , Size , getPassName ( ) , AO . Src , <STR_LIT> , cheri :: inferSourceLocation ( DebugInst ) ) ; } if ( BitCast == AO . ValueSrc . Base ) BitCast = SetLength ; Value * Result = SetLength ; if ( AO . ValueSrc . Offset != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << AO . ValueSrc


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM ,

DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( )


<s> int __gthr_win32_mutex_unlock ( __gthread_mutex_t * mutex ) { if ( InterlockedDecrement ( & mutex -> counter ) >= <NUM_LIT> ) return ReleaseSemaphore ( mutex -> sema , <NUM_LIT> , NULL ) ? <NUM_LIT> : <NUM_LIT> ; else return


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <


<s> const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: createSub ( PCRelExpr , DotExpr


<s> uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Disp


<s> std :: string tripleString ( <STR_LIT> ) ; std :: string featureString ; OwningPtr < const TargetMachine > targetMachine ( T . createTargetMachine ( tripleString , featureString ) ) ; InitRegisterMap ( targetMachine -> getRegisterInfo ( )


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . shadowReg ( <STR_LIT> ) ) ) ; EmitAdjustRSP ( Ctx , Out , <NUM_LIT> ) ; if ( Ctx . getRegisterInfo ( ) && FrameReg != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> )


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> return ( __m256i ) __builtin_ia32_movdquhi256_mask ( ( __v16hi ) __A , ( __v16hi )


<s> const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , ++ MachineBasicBlock :: iterator ( I ) , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ; return Copy


<s> if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true


<s> return ( unsigned long long ) __builtin_ia32_vcvttss2usi64 (


<s> int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , false , BaseReg , false , BaseUndef , false , OffUndef , Pred , PredReg , TII , isT2 ) ; NewBBI = llvm :: prior ( MBBI ) ; if ( isT2 && NewOpc == <STR_LIT> && OffImm + <NUM_LIT> >= <NUM_LIT>


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( Index == <NUM_LIT>


<s> if ( Offset == ( unsigned ) - <NUM_LIT> ) Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; auto GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; else if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; return SegmentOffset ( IRB ,


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case


<s> break ; } } else if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { Modifier = <STR_LIT> ; } } break ; case MachineOperand :: MO_BlockAddress : Name = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Name = MO . getSymbolName ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Name = GetCPISymbol ( MO . getIndex ( ) ) -> getName ( ) ; break ; } if ( PrintImmediatePrefix ) O << '#' ; if ( Modifier == <STR_LIT> && Suffix == <STR_LIT> ) O << Name ; else if ( Modifier == <STR_LIT> && Suffix != <STR_LIT> ) O << <STR_LIT> << Suffix << ':' << Name ; else if ( Modifier != <STR_LIT> && Suffix == <STR_LIT> ) O << <STR_LIT> << Modifier << ':' << Name ; else O << <STR_LIT> << Modifier << '_' << Suffix << ':' << Name ; return false


<s> bool i386_pe_type_dllexport_p ( tree decl ) { gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) ; if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE && DECL_ARTIFICIAL ( decl ) && ! DECL_THUNK_P


<s> unsigned char Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int


<s> <ISA_LIT>3DNowLevel = NoThreeDNow ; HasX87 = false ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY

) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> if ( isThumb && UserOffset % <NUM_LIT> != <NUM_LIT> ) UserOffset -= <NUM_LIT> ; if ( isThumb && TrialOffset % <NUM_LIT> != <NUM_LIT> ) TrialOffset += <NUM_LIT> ; if ( UserOffset <= TrialOffset ) { if ( TrialOffset - UserOffset <= MaxDisp ) return true ; } else if ( NegativeOK


<s> assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = F -> getTarget ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) .


<s> return ( __m512i ) __builtin_ia32_pmovsxwq512_mask ( ( __v8hi ) __A , ( __v8di )

_mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo


<s> const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = FrameInfo -> CreateStackObject ( ByteSize , StackAlign , false ) ; SDValue SRet = DAG . getFrameIndex ( FrameIdx , getPointerTy ( DL ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT .


<s> return ; } else { pcum -> aapcs_nextnvrn = NUM_FP_ARG_REGS ; goto on_stack ; } } ncrn = pcum -> aapcs_ncrn ; nregs = size / UNITS_PER_WORD ; if ( allocate_ncrn && ( ncrn + nregs <= NUM_ARG_REGS ) ) { gcc_assert ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || nregs == <NUM_LIT> ) ; if ( nregs == <NUM_LIT> && ncrn % <NUM_LIT> && ( aarch64_function_arg_alignment ( mode , type , & abi_break ) == <NUM_LIT> * BITS_PER_UNIT ) ) { if ( abi_break && warn_psabi && currently_expanding_gimple_stmt ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; ++ ncrn ; gcc_assert ( ncrn + nregs <= NUM_ARG_REGS ) ; } if ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || GET_MODE_CLASS ( mode ) == MODE_INT ) pcum -> aapcs_reg = gen_rtx_REG ( mode , R0_REGNUM + ncrn ) ; else { rtx par ; int i ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tmp = gen_rtx_REG ( word_mode , R0_REGNUM + ncrn +


<s> const SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( And . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftOpc = Shift . getOpcode ( ) ; if ( ( ShiftOpc != <STR_LIT> && ShiftOpc != <STR_LIT> ) ) return SDValue ( ) ; bool IsShiftRight = ShiftOpc == <STR_LIT> ; ConstantSDNode * C2node = dyn_cast < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ; if ( ! C2node ) return SDValue ( ) ; uint64_t C1 ; if ( ! isAllConstantBuildVector ( And . getOperand ( <NUM_LIT> ) , C1 ) ) return SDValue ( ) ; uint64_t C2 = C2node -> getZExtValue ( ) ; unsigned ElemSizeInBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( C2 > ElemSizeInBits ) return SDValue ( ) ; unsigned ElemMask = ( <NUM_LIT> << ElemSizeInBits ) - <NUM_LIT> ; if ( ( C1 & ElemMask ) != ( ~ C2 & ElemMask ) ) return SDValue ( ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; SDValue Y = Shift . getOperand ( <NUM_LIT> ) ; unsigned Intrin = IsShiftRight ? <STR_LIT> : <STR_LIT> ; SDValue ResultSLI = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Intrin , <STR_LIT> ) , X , Y , Shift . getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF18 ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS8 ; } case FK_Data_2 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS16 ; } case FK_Data_4 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_GOT : return ELF :: R_<ISA_LIT>_GOT_BREL ; case MCSymbolRefExpr :: VK_TLSGD : return ELF :: R_<ISA_LIT>_TLS_GD32 ; case MCSymbolRefExpr :: VK_TPOFF : return ELF :: R_<ISA_LIT>_TLS_LE32 ; case MCSymbolRefExpr :: VK_GOTTPOFF : return ELF :: R_<ISA_LIT>_TLS_IE32 ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS32 ; case MCSymbolRefExpr :: VK_GOTOFF : return ELF :: R_<ISA_LIT>_GOTOFF32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : return ELF :: R_<ISA_LIT>_TARGET1 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : return ELF :: R_<ISA_LIT>_TARGET2 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : return ELF :: R_<ISA_LIT>_SBREL32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : return ELF :: R_<ISA_LIT>_TLS_LDO32 ; case MCSymbolRefExpr :: VK_TLSCALL


<s> int i ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( ( HOST_WIDE_INT_1 << i ) - <NUM_LIT> == INTVAL ( x ) || ( HOST_WIDE_INT_1 << i ) - <NUM_LIT> == ~ INTVAL ( x ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case CONST : case CONST_DOUBLE : case LABEL_REF : case SYMBOL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; case UDIV : case UMOD : case DIV : case MOD : return <NUM_LIT> ; case TRUNCATE : return <NUM_LIT> ; case AND : case XOR : case IOR : return <NUM_LIT> ; case MEM : return ( <NUM_LIT> + <NUM_LIT> * ( ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) / UNITS_PER_WORD ) + ( ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) ? <NUM_LIT> : <NUM_LIT> ) ) ; case IF_THEN_ELSE : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC ) return <NUM_LIT> ; return <NUM_LIT> ; case SIGN_EXTEND : case ZERO_EXTEND : total = mode == DImode ? COSTS_N_INSNS ( <NUM_LIT> ) : <NUM_LIT> ; total += thumb1_rtx_costs ( XEXP ( x , <NUM_LIT> ) , GET_CODE ( XEXP ( x , <NUM_LIT> ) ) , code ) ; if ( mode == SImode )


<s> SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT ,


<s> case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; Alternative = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; Alternative = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case


<s> <ISA_LIT>MIPeepholeOpt ( ) : MachineFunctionPass (


<s> if ( fntype == NULL ) return false ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) != NULL ) return true ; return false


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . LRU . available ( <STR_LIT> ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { FrameID = MachineOutlinerRegSave ; NumBytesNoStackCalls += Costs . CallRegSave ; C . setCallInfo ( MachineOutlinerRegSave , Costs . CallRegSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( C . UsedInSequence . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += Costs . CallDefault ; C . setCallInfo ( MachineOutlinerDefault , Costs . CallDefault ) ; SetCandidateCallInfo ( MachineOutlinerDefault , Costs . CallDefault ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else return outliner :: OutlinedFunction


<s> switch ( I . getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT


<s> return ( __m256d ) __builtin_ia32_vfmaddsubpd256_mask ( ( __v4df ) __A , ( __v4df ) __B , - (


<s> default : return false ; case <NUM_LIT> : if ( matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> } ) ) { return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && ( matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) || matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) ) { AsmPieces . clear ( ) ; StringRef ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ) { AsmPieces . clear ( ) ; StringRef ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; array_pod_sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( clobbersFlagRegisters ( AsmPieces ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { InlineAsm :: ConstraintInfoVector Constraints =


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; } return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg ,


<s> unsigned <ISA_LIT>TargetLowering :: getMaximalGlobalOffset ( ) const { return ( Subtarget -> isThumb1Only ( ) ? <NUM_LIT>


<s> bool isBDAddr32Disp20 ( ) const { return isMemDisp20 ( ADDR32Reg ,


<s> if ( RegBits != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; const MCOperand & MO = MI . getOperand ( OpNo ) ; return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) )


<s> assert ( isMem ( MI , Op ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg ( )


<s> unsigned Flavour = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; unsigned RA = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X = new MCRegisterInfo (


<s> static void ia64_emit_insn_before ( rtx insn , rtx before ) { emit_insn_before ( insn , before


<s> void <ISA_LIT>InstPrinter :: printSysCROperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; assert ( Op . isImm ( )


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; return vectorCostAdjustment ( Cost , Opcode , Ty


<s> static const char * const CPUDirectives [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; if ( Subtarget . isGigaProcessor ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> &&


<s> if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = std :: next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> GetInstSizeInBytes ( UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT>


<s> if ( TARGET_64BIT ) if ( flag_pic ) { fprintf ( file , <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , MCOUNT_NAME ) ; } else { fprintf ( file , <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , MCOUNT_NAME ) ; } else if ( flag_pic ) { fprintf ( file , <STR_LIT> , LPREFIX , labelno , PROFILE_COUNT_REGISTER ) ; fprintf ( file , <STR_LIT> ,


<s> tree_code subcode = gimple_assign_rhs_code ( stmt_info -> stmt ) ; switch ( subcode ) { case PLUS_EXPR : case POINTER_PLUS_EXPR : case MINUS_EXPR : if ( kind == scalar_stmt ) { if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> addss ; else if ( X87_FLOAT_MODE_P ( mode ) ) stmt_cost = ix86_cost -> fadd ; else stmt_cost = ix86_cost -> add ; } else stmt_cost = ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op ) ; break ; case MULT_EXPR : case WIDEN_MULT_EXPR : case MULT_HIGHPART_EXPR : stmt_cost = ix86_multiplication_cost ( ix86_cost , mode ) ; break ; case NEGATE_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( X87_FLOAT_MODE_P ( mode ) ) stmt_cost = ix86_cost -> fchs ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; else stmt_cost = ix86_cost -> add ; break ; case TRUNC_DIV_EXPR : case CEIL_DIV_EXPR : case FLOOR_DIV_EXPR : case ROUND_DIV_EXPR : case TRUNC_MOD_EXPR : case CEIL_MOD_EXPR : case FLOOR_MOD_EXPR : case RDIV_EXPR : case ROUND_MOD_EXPR : case EXACT_DIV_EXPR : stmt_cost = ix86_division_cost ( ix86_cost , mode ) ; break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR


<s> EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment


<s> right -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = right ; else if ( node == node -> par -> left )


<s> static uint32_t swapHalfWords ( uint32_t Value , bool IsLittleEndian ) { if ( IsLittleEndian ) { uint32_t Swapped = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; Swapped |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; return Swapped ; } else return


<s> return __builtin_aarch64_sminpv4hi ( a ,


<s> static unsigned decodeNEONRd ( uint32_t insn ) { return ( ( insn >> <STR_LIT> ) & <NUM_LIT> ) << <NUM_LIT> | ( ( insn >> <STR_LIT>


<s> if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ) return false ; Idx ++


<s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand ::


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Op , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue (


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> vmlsq_n_s16 ( int16x8_t a , int16x8_t b , int16_t c ) { int16x8_t result


<s>
break
;
case
LT
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
LE
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
GT
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
p
=
strchr
(
string
,
'\0'
)
;
if
(
annul
&&
!
far
)
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
XINT
(
note
,
<NUM_LIT>
)
>=
REG_BR_PROB_BASE
/
<NUM_LIT>
)
^
far
)
<STR_LIT>
:
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
*
p
=
p
<
string
+
<NUM_LIT>
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
<NUM_LIT>
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
<NUM_LIT>
&&
delta
<
<NUM_LIT>
)
veryfar
=
<NUM_LIT>
;
}
strcpy
(
p
,
<STR_LIT>
)
;
if
(
annul
||
!
final_sequence
)
p
[
<NUM_LIT>
]
=
'6'
;
p
+=


<s> BasicBlock * BB = PHI -> getParent ( ) ; SmallVector < Instruction * , <NUM_LIT> > Incomings ; for ( unsigned I = <NUM_LIT> , E = PHI -> getNumIncomingValues ( ) ; I != E ; ++ I ) { Value * Op = PHI -> getIncomingValue ( I ) ; Instruction * Inst = dyn_cast < Instruction


<s> if ( Cost != - <NUM_LIT> ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ICA ,