<s> emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI ,


<s> return ( ( qword ) ( vec_sub ( ( vec_uint4 ) ( b ) , ( vec_uint4 )


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg ,


<s> assert ( N == <NUM_LIT> && isMemMode7 ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBaseRegNum ( ) ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemOffset ( ) ) ; ( void )


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; SDValue Vec ; if ( VT . is256BitVector ( ) ) { if ( HasInt256 ) { SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( VT . is128BitVector ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> return _inet_makeaddr ( net , lna ) >>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode4 ( SDNode * Op , SDValue N , SDValue & Addr , SDValue & Mode ) { Addr = N ; Mode = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) =


<s> for ( auto & I : EXRLTargets2Sym ) { OutStreamer -> emitLabel ( I . second ) ; const MCInstSTIPair & MCI_STI =


<s> static DecodeStatus decodeU6ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodeUImmOperand < <NUM_LIT> >


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; } else { MIB . add ( MO ) ; } } updateOperandRegConstraints ( MF , * NewMI , TII ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) NewMI -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MBB -> insert ( InsertPt , NewMI


<s> return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_3 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_4 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_5 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32 : case llvm :: ELF :: EF_MIPS_ARCH_32R2 : case llvm :: ELF :: EF_MIPS_ARCH_32R6 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_64 : case llvm :: ELF :: EF_MIPS_ARCH_64R2 : case llvm :: ELF


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) -


<s> for ( ; B != E ; ++ B ) if ( ! B -> isDebugInstr ( ) ) return B ; return E


<s> OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; const MCExpr * TargetExpr = MCSymbolRefExpr :: create ( Target , MCSymbolRefExpr :: VariantKind :: VK_None , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr (


<s> LiveRegs . addLiveIns ( * MBB ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( LiveRegs . available ( MRI , <STR_LIT> ) ) return <STR_LIT> ; for ( unsigned Reg : <STR_LIT> ) { if ( LiveRegs . available ( MRI , Reg ) ) return Reg ; } return <STR_LIT>


<s> static DecodeStatus DecodeStoreCP ( MCInst & Inst , unsigned insn

, uint64_t Address , const void * Decoder ) {


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { SupportsDebugInformation = true ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString =


) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> if ( ! tryParseRegisterOperand ( Operands , Mnemonic ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , Mnemonic ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . ParseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Identifier . end ( ) ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken


<s> AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( QPR ? <STR_LIT> : <STR_LIT> ) , Out ) . addReg ( Reg ) . addImm ( Lane ) ) ; return Out


<s> Value * <ISA_LIT>IREmitter :: visitATOMAND64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> return ( __mmask8 ) __builtin_ia32_ucmpq128_mask ( ( __v2di ) __X , ( __v2di )


<s> case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerCMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG


<s> ConstantSDNode * FalseC = dyn_cast < ConstantSDNode > ( False ) ; if ( ! FalseC ) return SDValue ( ) ; const SDLoc DL ( N ) ; if ( ! FalseC -> getZExtValue ( ) ) { <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( DL , SetCC . getValueType ( ) , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , <STR_LIT> ( CC , true ) ) ; return DAG . getNode ( <STR_LIT> , DL , FalseTy , SetCC , False , True ) ; } SDValue True = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * TrueC = dyn_cast < ConstantSDNode > ( True ) ; if ( ! TrueC || ! True . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; if ( True . getValueType ( ) == <STR_LIT> )


<s> std :: swap ( LHS , RHS ) ; if ( ! isSetCCOrZExtSetCC ( LHS , InfoAndKind ) ) return SDValue ( ) ; } EVT CmpVT = InfoAndKind . Is<ISA_LIT> ? InfoAndKind . Info . <ISA_LIT> . Cmp -> getOperand ( <NUM_LIT> ) . getValueType ( ) : InfoAndKind . Info . Generic . Opnd0 -> getValueType ( ) ; if ( CmpVT != <STR_LIT> && CmpVT != <STR_LIT> ) return SDValue ( ) ; SDValue CCVal ; SDValue Cmp ; SDLoc dl ( Op ) ; if ( InfoAndKind . Is<ISA_LIT>


<s> const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size ,


<s> bool Emitter < CodeEmitter > :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { MovePCtoLROffset = <NUM_LIT> ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF .

end ( ) ; BB != E ; ++ BB ) emitBasicBlock ( * BB ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << FrameSize << <STR_LIT> ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> } auto BTI = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! BTI ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBTIHint ( BTI -> Encoding , Tok . getString ( ) , S , getContext ( ) ) ) ; Parser . Lex


<s> static tree rs6000_init_stack_protect_guard (


<s> if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ; return ; } O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> (

<STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> } assert ( SN -> isUnindexed ( ) && <STR_LIT> ) ; assert ( Value . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Ops [ ] = { StoreChain , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value , FIdx } ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; StoreChain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , <STR_LIT> , PtrInfo ) ; SDValue Loads [ <NUM_LIT> ] , LoadChains [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned Offset = <NUM_LIT> * i ; SDValue Idx = DAG . getConstant ( Offset , dl , FIdx . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , FIdx . getValueType ( ) , FIdx , Idx ) ; Loads [ i ] = DAG . getLoad ( <STR_LIT> , dl , StoreChain , Idx , PtrInfo . getWithOffset ( Offset ) ) ; LoadChains [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; } StoreChain = DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue ShiftRightLogicInByte ( SDValue A , int immInByte ) { MVT VT = A . getSimpleValueType ( ) ; assert ( ( VT . getSizeInBits ( ) == <NUM_LIT> || VT . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && VT != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue B = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A , Constant ( immInByte * <NUM_LIT> , <STR_LIT> ) ) ; return


<s> bool hasSymbolicDisplacement ( ) const { return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT> || JT !=


<s> return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( isSingleInputShuffleMask ( Mask ) ) { if ( Subtarget -> hasSSE3 ( ) ) if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) +

( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) {


<s> unsigned getDPRCalleeSavedAreaSize ( ) const { return DPRCSSize


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> static unsigned getOffsetONFromFION ( const MachineInstr & MI , unsigned FIOperandNum ) { unsigned OffsetOperandNo = ( FIOperandNum == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNum -


<s> void <ISA_LIT>PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( )


<s> if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; bool IsNaCl = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn )


<s> RegD = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegD , isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ; else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> )


<s> bool NEONPreAllocPass :: PreAllocNEONRegisters ( MachineBasicBlock & MBB ) { bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; for ( ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = & * MBBI ; unsigned FirstOpnd , NumRegs ; if ( ! isNEONMultiRegOp ( MI -> getOpcode ( ) , FirstOpnd , NumRegs ) ) continue ; MachineBasicBlock :: iterator NextI = llvm :: next ( MBBI ) ; for ( unsigned R = <NUM_LIT> ; R < NumRegs ; ++ R ) { MachineOperand & MO = MI -> getOperand ( FirstOpnd + R ) ; assert ( MO . isReg ( ) && MO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned VirtReg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( VirtReg ) && <STR_LIT> ) ; static const unsigned NEONDRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; MO . setReg ( NEONDRegs [ R ] ) ; if ( MO . isUse ( ) ) { AddDefaultPred ( BuildMI ( MBB , MBBI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , MO . getReg ( ) ) . addReg ( VirtReg ) ) ; if ( MO . isKill ( ) ) { MachineInstr * CopyMI = prior ( MBBI ) ; CopyMI -> findRegisterUseOperand ( VirtReg ) -> setIsKill ( ) ; } MO . setIsKill


<s> for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; MIB . addMBB ( TBB


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + <NUM_LIT> ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ <NUM_LIT> ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = <NUM_LIT> ; i < nclobs ; ++ i ) XVECEXP (


<s> if ( REG_P ( dest ) || SUBREG_P ( dest ) ) { int d_regno = regno_or_subregno ( dest ) ; rtx scalar1 = operands [ <NUM_LIT> ] ; rtx scalar2 = operands [ <NUM_LIT> ] ; rtx scalar3 = operands [ <NUM_LIT> ] ; rtx scalar4 = operands [ <NUM_LIT> ] ; rtx tmp1 = operands [ <NUM_LIT>


<s> getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , false , GA ) ; } SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo , IsPIC


<s> <ISA_LIT>ElfTargetObjectFile ( ) : TargetLoweringObjectFileELF (


<s> void printi256mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI ,


<s> static bool get<ISA_LIT>LoadDeprecationInfo ( MCInst & MI , MCSubtargetInfo & STI , std :: string & Info ) { assert ( ! STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; bool ListContainsPC = false , ListContainsLR = false ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI )


<s> SDLoc DL ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) , DAG .

getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) ) ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false ,

false , NULL , <NUM_LIT> , NULL , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>FastISel :: emitLogicalOp ( unsigned ISDOpc , MVT RetVT , const Value * LHS , const Value * RHS ) { if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; unsigned Opc ; switch ( ISDOpc ) { case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; unsigned RHSReg ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS )

) RHSReg = materializeInt ( C , <STR_LIT> ) ;


<s> if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_BITSIZE ( mode ) > <NUM_LIT> || ( GET_MODE_BITSIZE ( mode ) > <NUM_LIT> && ! TARGET_POWERPC64 && ! ( TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode ) ) ) return false ; return CONSTANT_P ( x ) ; } return false


<s> if ( TARGET_ISEL ) return rs6000_emit_int_cmove ( dest , op , true_cond , false_cond ) ; return false ; } is_against_zero = op1 == CONST0_RTX ( compare_mode ) ; if ( SCALAR_FLOAT_MODE_P ( compare_mode ) && flag_trapping_math && ! is_against_zero ) return false ; if ( code == UNLT || code == UNGT || code == UNORDERED || code == NE || code == LTGT || code == LT || code == UNLE ) { code = reverse_condition_maybe_unordered ( code ) ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; } if ( code == UNEQ && HONOR_NANS ( compare_mode ) ) return false ; if ( HONOR_INFINITIES ( compare_mode ) && code != GT && code != UNGE && ( ! CONST_DOUBLE_P ( op1 ) || real_isinf ( CONST_DOUBLE_REAL_VALUE ( op1 ) ) ) && ( ( ! rtx_equal_p ( op0 , false_cond ) && ! rtx_equal_p ( op1 , false_cond ) ) || ( ! rtx_equal_p ( op0 , true_cond ) && ! rtx_equal_p ( op1 , true_cond ) ) ) ) return false ; if ( compare_mode != SFmode && compare_mode != DFmode ) return false ; if ( ! is_against_zero ) { temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_MINUS ( compare_mode , op0 , op1 ) ) ) ; op0 = temp ; op1 = CONST0_RTX ( compare_mode ) ; } if ( ! HONOR_NANS ( compare_mode ) ) switch ( code ) { case GT : code = LE ; temp = true_cond ; true_cond = false_cond ; false_cond =


<s> if ( ( ExtVT != <STR_LIT> || Subtarget -> is64Bit ( ) ) && SrcOp . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == ExtVT ) { OpVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ) ; } } } return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , OpVT

, DAG . getNode ( <STR_LIT> , dl , OpVT , SrcOp ) ) ) ;


<s> * xloc = mips_split_symbol ( <NUM_LIT> , * xloc ) ; return true ; } if ( GET_CODE ( * xloc ) == PLUS && GET_CODE ( XEXP ( * xloc , <NUM_LIT> ) ) == CONST_INT ) { rtx reg ; reg = XEXP ( * xloc


<s> static SDValue getBuildVectorSplat ( EVT VecTy , SDValue SplatValue , bool BigEndian , SelectionDAG & DAG ) { EVT ViaVecTy = VecTy ; SDValue SplatValueA = SplatValue ; SDValue SplatValueB = SplatValue ; SDLoc DL ( SplatValue ) ; if ( VecTy == <STR_LIT> ) { ViaVecTy = <STR_LIT> ; SplatValueA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValueB ) ; } if ( BigEndian ) std :: swap ( SplatValueA , SplatValueB ) ; SDValue Ops [ <NUM_LIT> ] = { SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_S , <STR_LIT>

} , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ;


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , const Triple & TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend (


<s> temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4sf ( __o , ( float32x4_t ) temp


<s> return __builtin_mve_vhsubq_n_sv8hi ( __a ,


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask


<s> bool system_reg_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG : case MACH_REG : return true


<s> static bool getMRCDeprecationInfo ( MCInst & MI , const MCSubtargetInfo & STI , std :: string & Info ) { if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && ( ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) ) { Info = <STR_LIT> <STR_LIT> ; return true ; } return


<s> if ( FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset = <NUM_LIT> ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words ) return <NUM_LIT> ; else if ( cum -> words + offset >= max_arg_words ) return <NUM_LIT> ; else return ( max_arg_words - cum -> words - offset


<s> MVT FullVT = getFullRegisterType ( VecVT ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; assert ( EltVT . isInteger ( ) && Val . getValueType ( ) . bitsGE ( EltVT ) && <STR_LIT> ) ; if ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , FullVT , Trunc ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , Ext ) ; } else { assert ( Val . getSimpleValueType ( ) . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; MVT I32VecType = <STR_LIT> ( <STR_LIT> , VecVT . getSizeInBits ( ) / <NUM_LIT> ) ; int mask = ( <NUM_LIT> << EltVT . getSizeInBits


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return res


<s> unsigned BitNum = findFirstSet ( x ) ; return ( x == x >> BitNum << BitNum ) && isUInt < N


<s> break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , Mask ) ; IsUnary = IsFakeUnary = N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePALIGNRMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : { IsUnary = true ; SDValue MaskNode = N -> getOperand ( <NUM_LIT> ) ; while ( MaskNode -> getOpcode ( ) == <STR_LIT> ) MaskNode = MaskNode -> getOperand ( <NUM_LIT> ) ; if ( MaskNode -> getOpcode ( ) == <STR_LIT> ) { EVT VT = MaskNode . getValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; if ( ! VT . isInteger ( ) ) return false ; int NumBytesPerElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; for ( int i = <NUM_LIT> , e = MaskNode -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue Op = MaskNode -> getOperand ( i ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { RawMask . push_back ( ( uint64_t ) SM_SentinelUndef ) ; continue ; } auto * CN = dyn_cast < ConstantSDNode > ( Op . getNode ( ) ) ; if ( ! CN ) return false ; APInt MaskElement = CN -> getAPIntValue ( ) ; for ( int j = <NUM_LIT> ; j < NumBytesPerElement ; ++ j ) { RawMask . push_back ( MaskElement . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) ; MaskElement = MaskElement . lshr ( <NUM_LIT> ) ; } } DecodePSHUFBMask ( RawMask , Mask ) ; break ; } auto * MaskLoad = dyn_cast < LoadSDNode > (


<s> Res . Mem . OffsetIsReg = OffsetIsReg ; Res . Mem . Offset = Offset ; Res . Mem . OffsetRegNum = OffsetRegNum ; Res . Mem . OffsetRegShifted = OffsetRegShifted ; Res . Mem . ShiftType = ShiftType ; Res . Mem . ShiftAmount = ShiftAmount ; Res . Mem . Preindexed


<s> if ( I -> mayStore ( ) ) { DebugLoc DL3 = MBB -> findDebugLoc ( I ) ; int storeOpcode = I -> getOpcode ( ) ; int loadOpcode = <NUM_LIT> ; int cmpOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } default : { errs ( ) << <STR_LIT> ; check = false ; } } if ( check ) { assert ( loadOpcode != <NUM_LIT> ) ; assert ( cmpOpcode != <NUM_LIT> ) ; MachineInstr * MIload = BuildMI ( MF , DL3 , TII -> get ( loadOpcode ) ) ; MIload -> setFlags (


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op


<s> EVT SrcVT = Src . getValueType ( ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( ) <= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) . isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc (


<s> static void arm_add_cfa_adjust_cfa_note ( rtx insn , int size , rtx dest , rtx src ) { rtx dwarf ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SET ( dest , plus_constant ( Pmode , src , size


<s> if ( isa < MCSymbolRefExpr > ( Imm . Val ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ; if ( ! CE ) return false ; Val = CE -> getValue ( ) ; } else if ( isGPRMem ( ) ) { if ( ! Memory . OffsetImm || Memory . OffsetRegNum )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( DAG . getConstant ( <NUM_LIT> , dl , ElementType ) ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( DAG . getConstant ( <NUM_LIT> , dl , ElementType ) ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl


<s> MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; } else { OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg (

) ) . addReg ( <STR_LIT> ) . addImm ( LPCC :: ICC_T ) , STI ) ;


<s> if ( generateSignBits ( V ) ) return false ; auto * I = cast < Instruction > ( V ) ; if ( I -> hasOneUse ( ) && isSink ( * I -> use_begin ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return true ; } if ( isa < OverflowingBinaryOperator > ( I


<s> bool <ISA_LIT>AsmParser :: parseDirectiveUnreq ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( L , <STR_LIT> ) ; RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Parser . Lex (


<s> if ( ( val >> <NUM_LIT> ) == <NUM_LIT> || mode == SImode ) { if ( generate ) { emit_insn ( gen_rtx_SET ( dest , GEN_INT ( val & <NUM_LIT> ) ) ) ; if ( mode == SImode ) emit_insn ( gen_insv_immsi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; else emit_insn ( gen_insv_immdi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } mask = <NUM_LIT> ; zero_match = ( ( val & mask ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; one_match = ( ( ~ val & mask ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; if ( zero_match != <NUM_LIT> && one_match != <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> , mask <<= <NUM_LIT> ) { val2 = val & ~ mask ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; val2 = val | mask ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; val2 = val2 & ~ mask ; val2 = val2 | ( ( ( val2 >> <NUM_LIT> ) | ( val2 << <NUM_LIT> ) ) & mask ) ; if ( val2 != val && aarch64_bitmask_imm ( val2 , mode ) ) break ; } if ( i != <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_vplzcntd_128_mask ( ( __v4si ) __A , ( __v4si )


<s> if ( NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm


<s> gen_lvsl = gen_altivec_lvsl_reg_si ; } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , <NUM_LIT> ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_add ( tmp , tmp , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_sub ( tmp , GEN_INT ( <NUM_LIT> - width ) , tmp ) ) ; rtx mask = gen_reg_rtx ( V16QImode ) ; rtx mask_v2di = gen_reg_rtx ( V2DImode ) ; rtvec v = rtvec_alloc ( <NUM_LIT> ) ; if ( ! BYTES_BIG_ENDIAN ) { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; } else { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; } emit_insn ( gen_vec_initv2didi ( mask_v2di , gen_rtx_PARALLEL ( V2DImode , v ) ) ) ; rtx sub_mask = simplify_gen_subreg ( V16QImode , mask_v2di , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( mask , sub_mask ) ) ; rtx tmp_val = gen_reg_rtx ( SImode ) ; if ( inner_mode == E_SFmode ) if ( TARGET_DIRECT_MOVE_64BIT ) emit_insn ( gen_movsi_from_sf ( tmp_val , val ) ) ; else { rtx stack = rs6000_allocate_stack_temp ( SFmode , false , true ) ; emit_insn ( gen_movsf_hardfloat ( stack , val


<s> getPowerTwoOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return countTrailingZeros ( ( uint64_t ) MO


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { assert ( SrcAS != DestAS && <STR_LIT> ) ; if ( getPointerSize ( SrcAS ) != getPointerSize


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue (


, V2 , Mask , Subtarget , DAG ) ) return V ;


<s> bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasInt256 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero && ! V2IsAllZero ) { CommuteVectorShuffleMask ( MaskVals , <NUM_LIT> ) ; V1 = V2 ; } SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i ++ ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> || EltIdx >= <NUM_LIT> ) EltIdx = <NUM_LIT> ; else { if ( ( EltIdx >= <NUM_LIT> && i < <NUM_LIT> ) || ( EltIdx < <NUM_LIT> && i >= <NUM_LIT>


<s> DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( dispatch_decl ) = <NUM_LIT> ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl


<s> static <ISA_LIT>Operand * CreateMemBarrierOpt ( <STR_LIT> Opt , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand


<s> if ( TrueMaskElt < <NUM_LIT> ) return false ; EVT EltVT = MaskedOp -> getMemoryVT ( ) . getVectorElementType ( ) ; Offset = <NUM_LIT> ; Addr = MaskedOp -> getBasePtr ( ) ; if ( TrueMaskElt != <NUM_LIT> ) { Offset = TrueMaskElt * EltVT . getStoreSize ( ) ; Addr = DAG . getMemBasePlusOffset ( Addr , TypeSize :: Fixed ( Offset )


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrOffsetNone ( SDValue


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget <


<s> if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC )


<s> if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , offset_adj ) = tmp ; } for ( j = <NUM_LIT> , i = <NUM_LIT> ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; if ( ( num_regs == <NUM_LIT> ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) =


<s> const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ) ; return ; } O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << TM . getRegisterInfo ( ) -> get ( MO2 . getReg (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> ShouldPrint = true ; } if ( get<ISA_LIT>Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM -> add ( create<ISA_LIT>IssueVZeroUpperPass (


<s> static int match_bracketed_pair ( typeinfo * typedata , char open , char close , restriction restr ) { if ( linebuf [ pos ] == open ) { safe_inc_pos ( ) ; int oldpos = pos ; char * x = match_integer ( ) ; if ( x == NULL ) { diag ( oldpos , <STR_LIT> ) ; return <NUM_LIT> ; } consume_whitespace ( ) ; if ( linebuf [ pos ] != ',' ) { diag ( pos , <STR_LIT> ) ; return <NUM_LIT> ; } safe_inc_pos ( ) ; consume_whitespace ( ) ; oldpos = pos ; char * y = match_integer ( ) ; if ( y == NULL ) { diag ( oldpos , <STR_LIT> ) ; return <NUM_LIT> ; } typedata -> restr = restr ; typedata -> val1 = x ; typedata -> val2 = y ; consume_whitespace ( ) ; if ( linebuf [ pos ] != close ) { diag ( pos , <STR_LIT> ) ; return <NUM_LIT> ; } safe_inc_pos ( ) ; return <NUM_LIT>


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : if ( ! Check ( S , MCDisassembler :: Fail ) ) return MCDisassembler :: Fail ; } if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: CreateImm ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT>


<s> unsigned CarryInReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; MachineInstr * Def = MRI . getVRegDef ( CarryInReg ) ; while ( Def -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CarryInReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Def = MRI . getVRegDef ( CarryInReg ) ; } unsigned Opcode ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_UADDE ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CarryInReg ) ; if ( ! RBI . constrainGenericRegister ( CarryInReg ,


<s> if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs


<s> if ( ! EnableHomogeneousPrologEpilog ) return false ; if ( ReverseCSRRestoreSeq ) return false ; if ( EnableRedZone ) return false ; if ( needsWinCFI ( MF ) ) return false ; if ( getSVEStackSize ( MF ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo


<s> static bool isVMerge ( ShuffleVectorSDNode * N , unsigned UnitSize , unsigned LHSStart , unsigned RHSStart ) { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; assert ( ( UnitSize == <NUM_LIT> || UnitSize == <NUM_LIT> || UnitSize == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> / UnitSize ; ++ i ) for ( unsigned j = <NUM_LIT> ; j != UnitSize ; ++ j ) { if ( ! isConstantOrUndef ( N -> getMaskElt ( i * UnitSize * <NUM_LIT> + j ) , LHSStart + j + i * UnitSize ) || ! isConstantOrUndef ( N -> getMaskElt ( i * UnitSize * <NUM_LIT> + UnitSize + j ) , RHSStart + j + i * UnitSize ) ) return false ; } return true


<s> static bool checkFnHasLiveInYmmOrZmm ( MachineRegisterInfo & MRI ) { for ( MachineRegisterInfo :: livein_iterator I = MRI . livein_begin ( ) , E = MRI . livein_end ( ) ; I != E ; ++ I ) if ( isYmmOrZmmReg ( I -> first ) ) return true ; return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; PrevReg = Reg ; ++ Count ; } } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( Count > <NUM_LIT> ) return Error ( S , <STR_LIT> ) ; unsigned NumElements = <NUM_LIT> ; char ElementKind = <NUM_LIT> ; if ( ! Kind . empty ( ) ) parseValidVectorKind ( Kind , NumElements , ElementKind ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , NumElements , ElementKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is


<s> if ( BYTES_BIG_ENDIAN ) { bool from_sve_p = aarch64_sve_data_mode_p ( from ) ; bool to_sve_p = aarch64_sve_data_mode_p ( to ) ; if ( from_sve_p != to_sve_p )


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None

) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT VecVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue MaskCasted = DAG . getNode ( <STR_LIT> , dl , VecVT , Mask ) ; SDValue Operand = IsFNABS ? DAG . getNode ( <STR_LIT> , dl , VecVT , Op0 . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , dl , VecVT , Op0 ) ; unsigned BitOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( BitOp , dl , VecVT , Operand , MaskCasted ) ) ; } unsigned BitOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> :


<s> static int forward_branch_p ( rtx insn ) { rtx label = JUMP_LABEL ( insn ) ; while ( insn ) { if ( insn == label


<s> if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed ( CSRegs [ i ] ) ) { ExtraReg = CSRegs [ i ] ; break ; } } if ( ExtraReg != <NUM_LIT> ) { MF . getRegInfo ( ) . setPhysRegUsed ( ExtraReg ) ; } else { assert ( RS && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; RS -> addScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment (


<s> AssemblerDialect = <NUM_LIT> ; if ( T . getOS ( ) == llvm :: Triple :: FreeBSD || ( T . getOS ( ) == llvm :: Triple :: NetBSD && ! is64Bit ) || ( T . getOS ( ) == llvm

:: Triple :: OpenBSD && ! is64Bit ) ) UseIntegratedAssembler = true ;


<s> if ( Offset . isExpr ( ) ) { Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) { if ( inMicro<ISA_LIT>Mode ( ) ) Inst . setOpcode ( has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( ! isInt < <NUM_LIT> > ( Offset . getImm (

) ) ) return Error ( IDLoc , <STR_LIT> ) ;


<s> MatrixKind getMatrixKind ( ) const { assert ( Kind == k_MatrixRegister && <STR_LIT> ) ; return MatrixReg .


<s> static section * pa_som_tm_clone_table_section ( void


<s> PM . add ( create<ISA_LIT>ISelDag ( * this , OptLevel ) ) ; PM . add ( createX87FPRegKillInserterPass ( ) ) ; return false


<s> return loongarch_function_value_1 ( valtype , fn_decl_or_type ,


<s> return ( uint32x2_t ) __builtin_neon_vqshluv2si ( ( int32x2_t ) __a ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - DefaultSafety ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - DefaultSafety ; case <STR_LIT> : return <NUM_LIT>


<s> if ( ! fgets ( lines [ lastline ] , LINELEN , file ) ) fatal ( <STR_LIT> ) ; strcpy ( & linebuf [ len - <NUM_LIT> ] , lines [ lastline ] ) ; len += strlen ( lines [ lastline ] ) - <NUM_LIT> ; } } if ( linebuf [ len - <NUM_LIT> ] != '\n' ) fatal ( <STR_LIT> ) ; pos = <NUM_LIT> ; consume_whitespace ( )


<s> rtx set ; set = gen_rtx_SET ( VOIDmode , mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; return set


<s> if ( isNEONByteReplicate ( <NUM_LIT> ) ) return false ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI -> definesRegister (


<s> return ( uint64x1_t ) { __a [ <NUM_LIT> ] > <NUM_LIT>


<s> case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned Binary = <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; emitWordLE ( Binary ) ; emitMiscBranchInstruction ( MI ) ; break ; } case TargetOpcode :: INLINEASM : { if ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) [ <NUM_LIT> ] ) { report_fatal_error ( <STR_LIT> ) ; } break ; } case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ) ; break ; case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : break ; case <STR_LIT> : emitConstPoolInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT>


<s> return __builtin_mve_vbicq_n_uv4si ( __a ,


<s> return ( uint8x8_t ) __builtin_neon_vbslv8qi ( ( int8x8_t ) __a , (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! hasShiftedReg ( Second ) ; } } } if ( Subtarget . hasArithmeticCbzFusion ( ) ) { unsigned SecondOpcode = Second . getOpcode ( ) ; if ( SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> ) { switch ( First . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , GetCPISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; bool ignored ; Val . convert ( APFloat :: IEEEdouble , APFloat :: rmTowardZero , & ignored ) ; MCOp = MCOperand :: CreateFPImm ( Val . convertToDouble ( ) ) ; break ; } case MachineOperand :: MO_RegisterMask


<s> Vec [ <NUM_LIT> ] = InVec [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) TempVector [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , Vec [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , VPAlign [ <NUM_LIT> ] ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( TempVector [ i ] , TempVector [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , VPAlign [ <NUM_LIT> ] ) ; unsigned NumOfElm = VT .


<s> void <ISA_LIT>TargetELFStreamer :: emitFrame ( unsigned StackReg , unsigned StackSize , unsigned ReturnReg_ ) { MCContext & Context = getStreamer ( ) . getAssembler ( ) .


<s> case TargetOpcode :: COPY : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ; } case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrModePCOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups


<s> MCAsmParser & getParser ( ) const { return Parser


<s> void printi512mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O


<s> if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == <NUM_LIT> && Alignment >= <NUM_LIT> ) || ( EltWidth

== <NUM_LIT> && Alignment >= <NUM_LIT> ) || EltWidth == <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel , bool IsRelocWithSymbol , int64_t Addend ) const { return GetRelocTypeInner ( Target , Fixup , IsPCRel


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> __o = __builtin_aarch64_ld4di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t


<s> val = force_operand ( plus_constant ( Pmode , xop0 , n ) , NULL_RTX ) ; emit_move_insn ( base_reg , val ) ; x = plus_constant ( Pmode , base_reg , low_n ) ; } else if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ; if ( CONSTANT_P ( xop1 ) && ! symbol_mentioned_p ( xop1 ) ) xop1 = force_reg ( SImode , xop1 ) ; if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_MINUS ( SImode , xop0 , xop1 ) ; } else if ( CONST_INT_P ( x ) && optimize > <NUM_LIT> ) { unsigned int bits ; HOST_WIDE_INT mask , base , index ; rtx base_reg ; bits = ( mode == SImode ) ? <NUM_LIT> : <NUM_LIT> ; mask = ( <NUM_LIT> << bits ) - <NUM_LIT> ; base = INTVAL ( x ) & ~ mask ; index = INTVAL ( x ) & mask ; if ( bit_count ( base & <NUM_LIT> ) > ( <NUM_LIT> - bits ) / <NUM_LIT> ) { base |= mask ; index -= mask ; } base_reg = force_reg ( SImode , GEN_INT ( base


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT VT8Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N1 ) ; SDValue N3 = DAG . getNode ( <STR_LIT> , DL , VT8Bit


<s> static DecodeStatus DecodeVRRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> :


<s> MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , <NUM_LIT> > WorkList ( <NUM_LIT> , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node =


<s> } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lanai > X ( The<ISA_LIT>Target ,


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t Val = MO . getImm ( ) ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; else if ( Val < <NUM_LIT> ) { Val *= -


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass


<s> return ( __m128i ) __builtin_ia32_vpshrdv_v8hi ( ( __v8hi ) __A , ( __v8hi )


<s> if ( isSpecialLLVMGlobalArrayForStaticInit ( GV ) ) return ; MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; SectionKind GVKind ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( GV -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( GV , TM ) : getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) , TM ) ) ; if ( GV -> isDeclaration ( ) ) return ; if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> emitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; OutStreamer -> emitLabel ( EmittedInitSym ) ; emitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer


<s> return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 : case


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , Op . getDebugLoc ( ) , getPointerTy (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this , PM


<s> void <ISA_LIT>InstPrinter :: printPImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI ,


<s> return __builtin_ia32_vcvtdq2ph128_mask ( ( __v4si ) __C ,


<s> break ; } if ( NeedsWinCFI ) { auto SEH = std :: next ( MBBI ) ; if ( <ISA_LIT>InstrInfo :: isSEHInstruction ( * SEH ) ) SEH -> eraseFromParent ( ) ; } TypeSize Scale = TypeSize :: Fixed ( <NUM_LIT> ) ; unsigned Width ; int64_t MinOffset , MaxOffset ; bool Success = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) -> getMemOpInfo ( NewOpc , Scale , Width , MinOffset , MaxOffset ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; if ( MBBI -> getOperand ( MBBI -> getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || CSStackSizeInc < MinOffset || CSStackSizeInc > MaxOffset ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , StackOffset :: getFixed ( CSStackSizeInc ) , TII , FrameFlag , false , false , nullptr , EmitCFI , StackOffset :: getFixed ( CFAOffset ) ) ; return std :: prev ( MBBI ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx


<s> DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpAddLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToLDR ; break ; case MCLOH_AdrpAddStr : if ( Info . MI1 != nullptr ) { DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpAddStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToSTR ; } break ; case MCLOH_AdrpLdrGotLdr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToLDR ; break ; case MCLOH_AdrpLdrGotStr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToSTR ; break ; case MCLOH_AdrpLdrGot : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGot , { & MI , Info . MI0 } ) ; break ; case MCLOH_AdrpAdrp : llvm_unreachable ( <STR_LIT>


<s> static bool loongarch_valid_lo_sum_p ( enum loongarch_symbol_type symbol_type , machine_mode mode , rtx x ) { int align , size ; if ( loongarch_symbol_insns ( symbol_type , mode ) == <NUM_LIT> ) return false ; if ( ! loongarch_split_symbol_type ( symbol_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , &


<s> if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride )


<s> AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective =


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; APInt DemandedMask ( APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; KnownBits LHSKnown ; if ( TLI . SimplifyDemandedBits ( LHS , DemandedMask , LHSKnown , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; return SDValue ( N , <NUM_LIT> ) ; } KnownBits RHSKnown ; if ( TLI . SimplifyDemandedBits ( RHS , DemandedMask , RHSKnown , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; return SDValue ( N


<s> static __inline vec_int4 spu_gencx ( vec_int4 a , vec_int4 b , vec_int4 c ) { return ( ( vec_int4 ) ( si_cgx ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c )


<s> return <NUM_LIT> - FPDiff ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; case


<s> unsigned IsToVec = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( IsToVec ) { DecodeFPR128RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; } else { DecodeGPR64RegisterClass ( Inst , Rd , Address , Decoder


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> )

, DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> case EQ : msw_skip = NE ; lsw_taken = EQ ; if ( prob . initialized_p ( ) ) { msw_skip_prob = rev_prob ; lsw_taken_prob = prob > profile_probability :: never ( ) ? profile_probability :: guessed_always ( ) : profile_probability :: guessed_never ( ) ; } break ; case NE : msw_taken = NE ; msw_taken_prob = prob ; lsw_taken = NE ; lsw_taken_prob = profile_probability :: guessed_never ( ) ; break ; case GTU : case GT : msw_taken = comparison ; if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) break ; if ( comparison != GTU || op2h != CONST0_RTX ( SImode ) ) msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GTU ; break ; case GEU : case GE : if ( op2l == CONST0_RTX ( SImode ) ) msw_taken = comparison ; else { msw_taken = comparison == GE ? GT : GTU ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GEU ; } break ; case LTU : case LT : msw_taken = comparison ; if ( op2l == CONST0_RTX ( SImode ) ) break ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = LTU ; break ; case LEU : case LE : if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) msw_taken = comparison ; else { lsw_taken = LEU ; if ( comparison == LE ) msw_taken = LT ; else if ( op2h != CONST0_RTX ( SImode ) ) msw_taken = LTU ; else { msw_skip = swap_condition ( LTU ) ; break ; } msw_skip = swap_condition ( msw_taken ) ; } break ; default : return false ; } num_branches = ( ( msw_taken != LAST_AND_UNUSED_RTX_CODE ) + ( msw_skip != LAST_AND_UNUSED_RTX_CODE ) + ( lsw_taken != LAST_AND_UNUSED_RTX_CODE ) ) ; if ( comparison != EQ && comparison != NE && num_branches > <NUM_LIT> ) { if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) && prob . initialized_p ( ) && prob . to_reg_br_prob_base ( ) >= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) && prob . to_reg_br_prob_base ( ) <= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ) { msw_taken_prob = prob . apply_scale ( <NUM_LIT> , <NUM_LIT> ) ; msw_skip_prob = rev_prob . apply_scale ( REG_BR_PROB_BASE , rev_prob . to_reg_br_prob_base ( ) + REG_BR_PROB_BASE ) ; lsw_taken_prob = prob ; } else { msw_taken_prob = prob ; msw_skip_prob = profile_probability :: guessed_always ( ) ; lsw_taken_prob = prob ; } } operands [ <NUM_LIT> ] = op1h ; operands [ <NUM_LIT>


<s> if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; if ( ! BoolArgs . empty ( ) ) { for ( auto & KV : BoolArgs ) { Register OrigReg = KV . first ; Register WideReg = KV . second ; LLT WideTy = MRI . getType ( WideReg ) ; assert ( MRI . getType ( OrigReg ) . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildTrunc ( OrigReg , MIRBuilder . buildAssertZExt ( WideTy , WideReg , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ) ; } } <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , <NUM_LIT> )


<s> const ConstantSDNode * CN = cast < ConstantSDNode > ( N ) ; Pred = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( N ) , <STR_LIT> ) ; Reg = CurDAG -> getRegister ( <STR_LIT> ,


<s> VectorType * VecTy = SVI -> getType ( ) ; assert ( VecTy -> getVectorNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubElts = VecTy -> getVectorNumElements ( ) / Factor ; Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , NumSubElts ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT>


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } if ( Subtarget . hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; } if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask


<s> unsigned long p = <NUM_LIT> ; return __builtin_bpermd ( p


<s> static const MCSymbol * GetAnonSym ( const MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName ( ) . end ( ) ) ; TmpStr += <STR_LIT> ; return Ctx . GetOrCreateSymbol ( TmpStr . str


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs ; Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF ( ) ) { SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; } if ( InstrumentSandboxingCFI ) { const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; OutStreamer -> SwitchSection ( TLOF -> getMagicStringTableSection ( ) ) ; for ( int i = <NUM_LIT> ; i < FunctionMagicLabelCount ; i ++ ) { std :: string magic_label ; magic_label = <STR_LIT> + std :: to_string ( i ) ; SmallString < <NUM_LIT> > NameStr ( magic_label ) ; MCSymbol * magic_symbol = TLOF -> getContext ( ) . getOrCreateSymbol ( NameStr ) ; OutStreamer -> EmitSymbolValue ( magic_symbol , <NUM_LIT>


<s> int64_t maxBwdBranchOffset ( ) const { return MAX_BWD_BRANCH_OFFSET


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI , MII , MRI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( MAI


<s> case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; unsigned RestAlign = std :: min


<s> case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , true ) ; break ; case <STR_LIT>


<s> if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) )


<s> SDValue Ops [ ] = { DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) , Glue } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> OutStreamer -> EmitLabel ( JTISymbol ) ; OutStreamer -> EmitDataRegion ( MCDR_DataRegionJT32 ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB ->


<s> ctors_section ( ) ; assemble_align ( POINTER_SIZE ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file ,


<s> nargs = nops + <NUM_LIT> ; if ( ! check_num_arguments ( nargs ) || ! require_vector_type ( i , VECTOR_TYPE_svbool_t ) ) return false ; i += <NUM_LIT> ; } else { nargs =


<s> if ( get<ISA_LIT>Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM -> add ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return


<s> unsigned getPrefLoopAlignment ( ) const


<s> getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpIdx ) . isExpr (


<s> return DecodeMem ( Inst , insn , Address , Decoder

, false , DecodeQFPRegsRegisterClass ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT> ) { Register Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister


<s> lo = gen_rtx_REG ( SImode , LO_REGNO ) ; if ( dest ) pattern = gen_mulsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) ) ; else pattern = gen_mulsi3_lo ( lo , src1 , src2


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredWinAlloca ( MachineInstr * MI , MachineBasicBlock * BB ) const { assert ( ! Subtarget . isTargetMachO ( ) ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstr * ResumeMI = Subtarget . getFrameLowering ( ) -> emitStackProbe ( * BB -> getParent ( ) , * BB , MI , DL , false ) ; MachineBasicBlock * ResumeBB = ResumeMI -> getParent (


<s> scope_counter ( int & counter ) : m_counter ( counter ) { ++


<s> EmitFunctionStubs ( const MachineModuleInfoMachO :: SymbolListTy & Stubs ) { bool is<ISA_LIT>64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( <NUM_LIT> ) == <NUM_LIT> ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; const MCSection * LSPSection = TLOFMacho . getLazySymbolPointerSection ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( AnonSymbol -> getName ( ) ) ) ; OutStreamer . EmitLabel ( AnonSymbol ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; else OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> + AnonSymbol -> getName ( ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym


<s> static MCStreamer * createMCStreamer ( const Triple & TT , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return createELFStreamer ( Context , MAB , OS ,


<s> const TargetInstrDesc & TID = MI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = TID . getNumOperands ( ) ; i != e ; ++ i ) { if ( TID . OpInfo [ i ] . isPredicate ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ! Reg || Reg == <STR_LIT> ) continue ; if ( Entry . WideOpc == <STR_LIT> && Reg == <STR_LIT> ) continue ; if ( Entry . LowRegs1 && ! is<ISA_LIT>LowRegister ( Reg ) ) return false ; } else if ( MO . isImm ( ) && ! TID . OpInfo [ i ] . isPredicate ( ) ) { if ( MO . getImm ( ) > Limit || ( MO . getImm ( ) & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; } } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewTID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewTID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB ,


<s> InConstantPool = false ; OutStreamer . EmitDataRegion


<s> for ( regno2 = regno + <NUM_LIT> ; ( saved_regs_mask & ( <NUM_LIT> << regno2 ) ) == <NUM_LIT> ; regno2 ++ ) ; reg1 = gen_rtx_REG ( SImode , regno ) ; reg2 = gen_rtx_REG ( SImode , regno2 ) ; if ( first ) { rtx insn ; first = false ; mem1 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ; mem2 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * ( num_regs - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * ( num_regs ) ) ) ; tmp1 = gen_rtx_SET ( mem1 , reg1 ) ; tmp2 = gen_rtx_SET ( mem2 , reg2 ) ; RTX_FRAME_RELATED_P ( tmp0 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) = <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp0 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp1 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp2 ; insn = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } else { mem1 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) ; mem2 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * ( i + <NUM_LIT> ) ) ) ; tmp1 = gen_rtx_SET ( mem1 , reg1 ) ; tmp2 = gen_rtx_SET ( mem2 , reg2 ) ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) = <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp1 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp2 ; emit_insn ( par ) ; } tmp1 = gen_rtx_SET ( gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) , reg1 ) ; tmp2 = gen_rtx_SET ( gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * ( i + <NUM_LIT> ) ) ) , reg2 ) ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) =


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>ExpandPseudoPass ( get<ISA_LIT>TargetMachine ( ) )


<s> void printf64mem ( const MCInst * MI , unsigned


<s> unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI ,


<s> int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx , SPReg , true ) ; assert ( Offset >= <NUM_LIT> && SPReg == TRI ->


<s> AU . addRequired < MachineModuleInfo > ( ) ; } AU . addRequired < DwarfWriter >


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) )

&& REGNO ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TOC_REGISTER ) ;


<s> insn -> regBase = MODRM_REG_AX ; insn -> eaRegBase = EA_REG_AX ; break ; case <NUM_LIT> : insn -> regBase = MODRM_REG_EAX ; insn -> eaRegBase = EA_REG_EAX ; break ; case <NUM_LIT> : insn -> regBase = MODRM_REG_RAX ; insn -> eaRegBase = EA_REG_RAX ; break ; } reg |= rFromREX ( insn -> rexPrefix ) << <NUM_LIT> ; rm |= bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ; evexrm = <NUM_LIT> ; if ( insn -> vectorExtensionType == TYPE_EVEX && insn -> mode == MODE_64BIT ) { reg |= r2FromEVEX2of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; evexrm = xFromEVEX2of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; } insn -> reg = ( Reg ) ( insn -> regBase + reg ) ; switch ( insn -> addressSize ) { case <NUM_LIT> : { EABase eaBaseBase = EA_BASE_BX_SI ; switch ( mod ) { case <NUM_LIT> : if ( rm == <NUM_LIT> ) { insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; } else { insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_NONE ; } break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_8 ; insn -> displacementSize = <NUM_LIT> ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaRegBase + rm ) ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { EABase eaBaseBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_EAX : EA_BASE_RAX ) ; switch ( mod ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; switch ( rm & <NUM_LIT> ) { case <NUM_LIT> : insn -> eaBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_sib : EA_BASE_sib64 ) ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_32 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; break ; } break ; case <NUM_LIT> : insn -> displacementSize =


<s> case <STR_LIT> : if ( VT . isScalableVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( VT . isScalableVector ( ) ) { unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opc ) ; } if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( )