<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > <NUM_LIT> ) ) { const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue (


<s> bool KillsOp0 = MI -> killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( KillsOp0 ) freeStackSlotAfter


<s> const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( DstRB . getID ( ) != SrcRB . getID ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRB . getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( DstTy , DstRB ) ; if ( ! DstRC ) return false ; const TargetRegisterClass * SrcRC = getRegClassForTypeOnBank ( SrcTy , SrcRB ) ; if ( ! SrcRC ) return false ; unsigned SubIdx ; if ( DstRC == SrcRC ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else { return false ; } SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } I . getOperand ( <NUM_LIT> ) . setSubReg


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , CostKind ) ; if ( ! ValTy -> isVectorTy ( ) ) { switch ( Opcode ) { case Instruction :: ICmp : { unsigned ScalarBits = ValTy -> getScalarSizeInBits ( ) ; if ( I != nullptr && ScalarBits >= <NUM_LIT> ) if ( LoadInst * Ld = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( const ConstantInt * C = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( ! Ld -> hasOneUse ( ) && Ld -> getParent ( ) == I -> getParent ( ) && C -> getZExtValue ( ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += ( I != nullptr ? getOperandsExtensionCost ( I ) : <NUM_LIT> ) ; return Cost ; } case Instruction :: Select : if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } else if ( ST -> hasVector ( ) ) { unsigned VF = cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst ::


<s> return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( TAB ) ,

OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> const RegisterBank & DstRB = * RBI . getRegBank ( Dst , MRI , TRI ) ; if ( EltRB != DstRB ) return false ; if ( any_of ( make_range ( I . operands_begin ( ) + <NUM_LIT> , I . operands_end ( ) ) , [ & MRI ] ( const MachineOperand & Op ) { return ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , Op . getReg ( ) , MRI ) ; } ) ) return false ; unsigned SubReg ; const TargetRegisterClass * EltRC = getMinClassForRegBank ( EltRB , EltTy . getSizeInBits ( ) ) ; if ( ! EltRC ) return false ; const TargetRegisterClass * DstRC = getMinClassForRegBank ( DstRB , MRI . getType ( Dst ) . getSizeInBits ( ) ) ; if ( ! DstRC ) return false ; if ( ! getSubRegForClass ( EltRC , TRI , SubReg ) ) return false ; auto SubregToReg = MIB . buildInstr ( <STR_LIT> , { Dst } , { } ) . addImm ( <NUM_LIT> ) . addUse ( EltReg ) . addImm ( SubReg ) ; I . eraseFromParent


<s> emit_move_insn ( offset == <NUM_LIT> ? change_address ( addr , SImode , NULL_RTX ) : adjust_address ( addr , SImode , offset )


<s> } else { assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; uint64_t Intval = Opcodes [ <NUM_LIT> ] | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> ; emitIntValue ( Intval , Opcodes . size ( ) ) ; } SwitchSection ( & FnStart -> getSection ( ) ) ; EHReset (


<s> } else { Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } } int LoMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int * MaskPtr = LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; MaskPtr [ LoIdx ] = Idx ; LoIdx ++ ; } else { Locs [ i ] = std :: make_pair ( MaskIdx , HiIdx ) ; MaskPtr [ HiIdx ] = Idx ; HiIdx ++ ; } } SDValue LoShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & LoMask [ <NUM_LIT> ] ) ; SDValue HiShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & HiMask [ <NUM_LIT> ] ) ; int MaskOps [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Locs [ i ] . first != - <NUM_LIT> ) MaskOps [ i ] = Locs [ i ] . first * <NUM_LIT> + Locs [ i ] . second ; return DAG . getVectorShuffle ( VT , dl , LoShuffle , HiShuffle , & MaskOps [


<s> return __arm_vshllbq_x_n_u16 ( __a ,


<s> } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addLeaAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; } unsigned MCPOffset = MCP . getConstantPoolIndex ( C , Align ) ; unsigned ResultReg = createResultReg (


<s> if ( simplejump_p ( insn ) ) { emit_insn_before ( gen_erepeat_end ( ) , insn ) ; delete_insn ( insn ) ; } else { mep_invert_branch ( insn , newlast ) ; emit_insn_after ( gen_erepeat_end ( ) , newlast ) ; } break ; } if ( LABEL_P ( prev ) ) { rtx_insn * user = <NUM_LIT> ; int safe = <NUM_LIT> ; if ( LABEL_NUSES ( prev ) == <NUM_LIT> ) { for ( user = PREV_INSN ( prev ) ; user && ( INSN_P ( user ) || NOTE_P ( user ) ) ; user = PREV_INSN ( user ) ) if ( JUMP_P ( user ) && JUMP_LABEL ( user ) == prev ) { safe = INSN_UID ( user ) ; break ; } } if ( ! safe ) break ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , safe , INSN_UID ( prev ) ) ; } if ( INSN_P ( prev ) ) { count ++ ; } } } if ( dump_file ) fprintf (


<s> } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , <NUM_LIT> ) ; accum_rtx_p = & XEXP ( fma_rtx , <NUM_LIT> ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , <NUM_LIT> ) ; if ( accum_rtx_p != chain


<s> I = std :: find_if ( B , E , isdigit ) ; Prefix . assign ( B , I - B ) ; if ( I == E ) return std :: make_pair ( true , false ) ; return std :: make_pair ( ! getAsUnsignedInteger ( StringRef ( I , E - I ) ,


<s> unsigned NumElems = N -> getNumOperands ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i ) ) return false ; return true


<s> bool isImm1_64 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return


<s> static inline int getFP64Imm ( const APFloat &


<s> DebugLoc dl = I == MBB -> end ( ) ? DebugLoc ( ) : I -> getDebugLoc ( ) ; unsigned STReg = getSTReg ( RegNo ) ; pushReg ( AsReg


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftLeft ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftRightArithmetic ( N ,


<s> void <ISA_LIT>AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out , getParser ( ) . shouldPrintSchedInfo


<s> if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F


<s> if ( code == LT || code == GE ) { code = swap_condition ( code ) ; std :: swap ( cop0 , cop1 ) ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( <NUM_LIT> , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ,


<s> bool <ISA_LIT>PromoteConstant :: isDominated ( Instruction * NewPt , Instruction * User , unsigned OpNo , InsertionPoints & InsertPts ) { DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( * NewPt -> getParent ( ) -> getParent ( ) ) . getDomTree ( ) ; for ( auto & IPI : InsertPts ) { if ( NewPt == IPI . first || DT . dominates ( IPI . first , NewPt ) || ( IPI . first -> getParent ( ) != NewPt -> getParent ( ) && DT . dominates ( IPI . first -> getParent ( ) , NewPt -> getParent ( ) ) ) ) { DEBUG ( dbgs (


<s> exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg


<s> if ( ST -> hasAVX ( ) && PreferVectorWidth >= <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> hasSSE1 ( ) && PreferVectorWidth >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( ST -> is64Bit ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> Relocator :: DWord P = pReloc . place ( ) ; Relocator :: DWord X = helper_get_page_address ( S + A ) - helper_get_page_address ( P ) ; pReloc . target ( ) = helper_reencode_adr_imm ( pReloc . target ( ) , ( X >> <NUM_LIT> ) ) ; return Relocator


<s> return __builtin_mve_vmaxaq_sv4si ( __a ,


<s> } } if ( TARGET_V9 && TARGET_ARCH64 && GET_MODE ( x ) == DImode && ! ( TARGET_VIS3 && ( code == GTU || code == LTU ) ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; if ( code == GTU || code == LEU ) { if ( ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) && ( GET_CODE ( y ) == REG || GET_CODE ( y ) == SUBREG ) ) { tem = x ; x = y ; y = tem ; code = swap_condition ( code ) ; } } if ( code == LTU || ( ! TARGET_VIS3 && code == GEU ) ) { emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , gen_compare_reg_1 ( code , x , y ) , const0_rtx ) ) ) ; return true


<s> int pa_adjust_insn_length ( rtx_insn * insn , int length ) { rtx pat = PATTERN ( insn ) ; if ( ( unsigned int ) length >= INT_MAX ) { if ( GET_CODE ( pat ) == SEQUENCE ) insn = as_a < rtx_insn * > ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MILLI : length = pa_attr_length_millicode_call ( insn ) ; break ; case TYPE_CALL : length = pa_attr_length_call ( insn , <NUM_LIT> ) ; break ; case TYPE_SIBCALL : length = pa_attr_length_call ( insn , <NUM_LIT> ) ; break ; case TYPE_DYNCALL : length = pa_attr_length_indirect_call ( insn ) ; break ; case TYPE_SH_FUNC_ADRS : length = pa_attr_length_millicode_call ( insn ) + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) length += compute_cpymem_length ( insn ) - <NUM_LIT> ; else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) length += compute_clrmem_length ( insn ) - <NUM_LIT> ; else if ( JUMP_P ( insn ) && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length == <NUM_LIT> && JUMP_LABEL ( insn ) != NULL_RTX && ! forward_branch_p ( insn ) ) length += <NUM_LIT> ; else if ( GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_PARALLEL_BRANCH && length == <NUM_LIT> ) length += <NUM_LIT> ; else if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && ! FP_REG_P ( XEXP ( XVECEXP ( pat , <NUM_LIT>

, <NUM_LIT> ) , <NUM_LIT> ) ) && length == <NUM_LIT> && ! forward_branch_p ( insn ) ) length += <NUM_LIT> ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffective<ISA_LIT>CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( getOptLevel ( ) <= EnableGlobalISelAtO ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner (


<s> rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; if ( rounded_size <= ( HOST_WIDE_INT_1 << <NUM_LIT> ) ) emit_insn ( gen_rtx_SET ( sr . reg , plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size - size ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } last = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; release_scratch_register_on_entry ( & sr ) ; } if ( size > <NUM_LIT> ) { rtx expr = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( expr , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode


<s> t_naked = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ; t_no_prologue = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ; return ( ( t_naked != NULL_TREE ) || ( t_no_prologue != NULL_TREE


<s> case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success


<s> SDValue SrcOp = SrcBC . getOperand ( <NUM_LIT> ) ; if ( SrcOp . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , SrcOp ) ; EVT SrcOpVT = SrcOp . getValueType ( ) ; if ( SrcOpVT . isScalarInteger ( ) && VT . isInteger ( ) && ( SrcOpVT . getSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> ) { unsigned Scale = SrcOpVT . getSizeInBits ( ) / SrcEltBits ; unsigned Offset = IdxC . urem ( Scale ) * SrcEltBits ; if ( Offset == <NUM_LIT> ) { SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , SrcVT . getScalarType ( ) ) ; SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , VT ) ; return SrcOp ; } } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && SrcBC . hasOneUse ( ) ) { auto * MemIntr = cast < MemIntrinsicSDNode > ( SrcBC ) ; unsigned SrcBCWidth = SrcBC . getScalarValueSizeInBits ( ) ; if ( MemIntr -> getMemoryVT ( ) . getSizeInBits ( ) == SrcBCWidth && VT . getSizeInBits ( ) == SrcBCWidth ) { SDValue Load = DAG . getLoad ( VT , dl , MemIntr -> getChain ( ) , MemIntr -> getBasePtr ( ) , MemIntr -> getPointerInfo ( ) , MemIntr -> getAlignment ( ) , MemIntr -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( MemIntr , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) && SrcBC . getValueType ( ) . isInteger ( ) && ( SrcBC . getScalarValueSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> && SrcBC . getScalarValueSizeInBits ( ) == SrcBC . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) { unsigned Scale = SrcBC . getScalarValueSizeInBits ( ) / SrcEltBits ; if ( IdxC . ult ( Scale ) ) { unsigned Offset = IdxC . getZExtValue ( ) * SrcVT . getScalarSizeInBits ( ) ; SDValue Scl = SrcBC . getOperand ( <NUM_LIT> ) ; EVT SclVT = Scl . getValueType ( ) ; if ( Offset ) { Scl = DAG . getNode ( <STR_LIT> , dl , SclVT , Scl , DAG . getShiftAmountConstant ( Offset , SclVT , dl ) ) ; } Scl = DAG . getZExtOrTrunc ( Scl , dl , SrcVT . getScalarType ( ) ) ; Scl = DAG . getZExtOrTrunc ( Scl , dl , VT ) ; return Scl ; } } if ( <STR_LIT> == Src . getOpcode ( ) && SrcVT . is128BitVector ( ) && IdxC ==


<s> assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( VecTy -> getScalarType ( ) ) == <NUM_LIT> ; if ( Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) && ! EltIs64Bits ) { unsigned NumElts = VecTy -> getVectorNumElements ( ) ; Type * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts


<s> return GuaranteedTailCallOpt && canGuaranteeTCO (


<s> switch ( getLexer ( ) . getKind ( ) ) { default : break ; case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; unsigned RegKind ; if ( matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) { StringRef name = Parser . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( RegNo ) { default : Op = <STR_LIT> ( RegNo , RegKind , S , E ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Plus : case AsmToken :: Minus


<s> emitCalleeSavedRestores ( MBB , MBBI


<s> return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall ,


<s> if ( ! decompose_csky_address ( XEXP ( op , <NUM_LIT> ) , & addr ) ) return false ; if ( ! is_csky_address_register_rtx_p ( addr . base , <NUM_LIT> ) ) return false ; if ( addr . index && ( constraint [ <NUM_LIT> ] == 'Q' || constraint [ <NUM_LIT> ] == 'W' ) ) { if ( ! is_csky_address_register_rtx_p ( addr . index , <NUM_LIT> ) ) return false ; if ( addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT> || addr .

scale == <NUM_LIT> || addr . scale == <NUM_LIT> ) return true ;


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( The<ISA_LIT>64Target ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B (


<s> static bool isORCopyInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; break ; case <STR_LIT>


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; return IntVal


<s> vec_uint4 v ; unsigned char c [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchVersion = V6T2 ; } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } if ( <ISA_LIT>ArchVersion >= V6T2 ) ThumbMode = Thumb2 ; } } if ( <ISA_LIT>ArchVersion < V6T2 && ThumbMode >= Thumb2 ) <ISA_LIT>ArchVersion = V6T2 ; if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( <ISA_LIT>ArchVersion <


<s> return static_cast < CondCode > ( static_cast < unsigned


<s> assert ( ! Subtarget -> isTargetEnvMacho ( ) && <STR_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT>


<s> unsigned NextBlockOffset , NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = Water ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockAlignment = NextBlock -> getAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand


<s> return ( __m128i ) __builtin_ia32_pmovdb512_mask ( ( __v16si ) __A , (


<s> bool has_trailing_nott ( void ) const { return m_trailing_nott_insn !=


<s> bool HasAnyUndefs ; if ( ! BVN || ! BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElementBits ) || SplatBitSize > ElementBits ) return false ; Cnt = SplatBits . getSExtValue ( ) ; return true


<s> int64_t FirstByte = MFI . getObjectOffset ( ClobberedFI ) ; int64_t LastByte = FirstByte + MFI . getObjectSize ( ClobberedFI ) - <NUM_LIT> ; ArgChains . push_back ( Chain ) ; for ( SDNode :: use_iterator U = DAG . getEntryNode ( ) . getNode ( ) -> use_begin ( ) , UE = DAG . getEntryNode ( ) . getNode ( ) -> use_end ( ) ; U != UE ; ++ U ) if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( * U ) ) if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ; InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte &&

InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ;


<s> auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( AMXCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Builder . CreateSExt ( Col , Builder . getInt64Ty ( ) ) } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; AMXCast -> replaceAllUsesWith ( NewInst ) ; AMXCast -> eraseFromParent ( ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II ) return false ; Prepare ( AMXCast -> getType ( ) ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand ( <NUM_LIT> ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Builder . CreateSExt ( Col , Builder . getInt64Ty ( ) ) , Src } ; Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Value * NewInst = Builder . CreateLoad ( AMXCast -> getType (


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) )


<s> Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . align = <NUM_LIT> ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . align = <NUM_LIT> ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16


<s> lastCheck = CI -> getParent ( ) ; DebugLoc DL3 = CI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32LETarget ( ) , create<ISA_LIT>LEDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler


<s> return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Subtarget . hasSSE2 ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( SDValue NotSrc = IsNOT ( Src , DAG ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; NotSrc = DAG . getBitcast ( SrcVT , NotSrc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , NotSrc ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) ) ,


<s> void printLSROperand ( const MCInst * MI , unsigned


<s> <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM )


<s> MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( Op ) ; unsigned ResultReg ; if ( SrcVT == <STR_LIT> ) { uint64_t Mask = <NUM_LIT> ; switch ( DestVT . SimpleTy ) { default : return false ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; case <STR_LIT> : Mask = <NUM_LIT>


<s> Hi = DAG . getVectorShuffle ( InVT , DL , In , In , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; } else { assert ( InVT == <STR_LIT> && <STR_LIT> ) ; Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; } Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; } if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { In = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getConstant ( ShiftInx , DL , InVT ) ) ; } if ( Subtarget . hasDQI ( ) ) return DAG . getSetCC ( DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , <STR_LIT> ) ; return DAG . getSetCC ( DL , VT , In , DAG . getConstant

( <NUM_LIT> , DL , InVT ) , <STR_LIT> ) ;


<s> return rs6000_hash_constant ( thc -> key )


<s> while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( CondDefReg ) ) { for ( const MachineInstr & UI : MRI . use_nodbg_instructions ( CondDefReg ) ) { if ( CondDef == & UI ) continue ; if ( UI . getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP )


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; Register Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; Register Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .

get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ;


<s> if ( DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > <NUM_LIT> ) { int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + <NUM_LIT> ) >> <NUM_LIT> : <NUM_LIT> ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode =


<s> branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return


<s> unsigned <ISA_LIT>SEFrameLowering :: ehDataReg ( unsigned I ) const { static const unsigned EhDataReg [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned EhDataReg64 [ ]


<s> default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } default : return false


<s> if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . getDarwinDirective ( ) == <STR_LIT> ) { UP . Partial = UP . Runtime = true ; } TargetTransformInfo :: getUnrollingPreferences ( F , L


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ; char regIdx = '0' + ( intVal % <NUM_LIT> ) ; char tmp [ ] = { '{' , regType , regIdx


<s> if ( getMemBaseReg ( ) ) Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; else Inst . addOperand ( MCOperand :: createReg ( getMemDefaultBaseReg ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemDisp ( )


<s> bool <ISA_LIT>AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand (


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( )


<s> linkExceptionRegistration ( Builder , Trampoline ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { bool UseStackGuard = ( PersonalityName == <STR_LIT> ) ; RegNodeTy = getSEHRegistrationType ( ) ; RegNode = Builder . CreateAlloca ( RegNodeTy ) ; Value * SP = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , { } ) ; Builder . CreateStore ( SP , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; StateFieldIndex = <NUM_LIT> ; insertStateNumberStore ( RegNode , & * Builder . GetInsertPoint ( ) , UseStackGuard ? - <NUM_LIT> : - <NUM_LIT> ) ; Value * FI8 = Builder . CreateBitCast ( F , Int8PtrType ) ; Value * LSDA = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , FI8 ) ; Type * Int32Ty = Type :: getInt32Ty ( TheModule -> getContext ( ) ) ; LSDA = Builder . CreatePtrToInt ( LSDA , Int32Ty ) ; if ( UseStackGuard ) { Value * Cookie = TheModule -> getOrInsertGlobal ( <STR_LIT> , Int32Ty ) ; Value * Val = Builder . CreateLoad ( Int32Ty ,


<s> static bool sh_legitimize_address_displacement ( rtx * offset1 , rtx * offset2 , poly_int64 orig_offset , machine_mode mode ) { if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , orig_offset ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * offset1 = adj . offset_adjust ; * offset2 = adj . mov_disp ; return


<s> void addMemoryIndexed8Operands ( MCInst & Inst , unsigned


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( Imm . isZero ( ) || Imm . isNegZero ( ) ) return true ; return <ISA_LIT>VectorConstantInfo ( Imm ) . isVectorConstantLegal (


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F )


<s> assert ( ! ( ShOpc == <STR_LIT> && ! ShImm ) && <STR_LIT> ) ; O << getShiftOpcStr ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) { O <<


<s> if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= <NUM_LIT> << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~


<s> unsigned Opcode = Inst . getOpcode ( ) ; bool NeedsDisjointWritebackTransfer = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; } switch ( Opcode ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr


<s> void EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int


<s> Name += <STR_LIT> ; } MCSymbol * Sym = OutContext . GetOrCreateSymbol ( Name ) ; return MCOperand :: CreateMCValue ( MCValue :: get ( Sym , <NUM_LIT> , MO . getOffset (


<s> return ( __m128i ) __builtin_ia32_vaesdeclast_v16qi ( ( __v16qi ) __A , ( __v16qi )


<s> return ( __m256i ) __builtin_ia32_pmovwb512_mask ( ( __v32hi ) __A , ( __v32qi )

_mm256_undefined_si256 ( ) , ( __mmask32 ) - <NUM_LIT> ) ;


<s> SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo (


<s> static DecodeStatus DecodeLogicalImmInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm ; if ( Datasize ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) ; imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( imm ,


<s> return new <ISA_LIT>TargetStreamer ( S


<s> SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <STR_LIT> ) ; return <STR_LIT> ; } if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && MaskRegClassContains ( SrcReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister ( DestReg , <STR_LIT> ) ; return <STR_LIT> ; } return


<s> bool hasFastVariableShuffle ( ) const { return


<s> case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return Helper . tryCombineExtendingLoads ( MI ) ; } return false


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . has<ISA_LIT>64 ( ) ) return Subtarget . has<ISA_LIT>64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . has<ISA_LIT>32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( )


<s> if ( Val . getOpcode ( ) == <STR_LIT> ) return { Val . getOperand ( <NUM_LIT> ) , Val . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . getFixedSizeInBits ( ) - <NUM_LIT> } ; return { Val , Val . getValueSizeInBits (


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return <STR_LIT>


<s> bool isMemThumbRIs4 ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm ->


<s> unsigned & CondReg = CondRegs [ Cond ] ; unsigned & InvCondReg = CondRegs [ <STR_LIT> ( Cond ) ] ; if ( ! CondReg && ! InvCondReg ) CondReg = promoteCondToReg (


<s> MCDisassembler :: DecodeStatus <ISA_LIT>GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = <NUM_LIT> ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor -


<s> unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc

= ( Subtarget . hasP9Vector ( ) ) ? <STR_LIT> : <STR_LIT> ;


<s> return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem .


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: restoreWin32EHStackPointers ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool RestoreSP ) const { assert ( STI . isTargetWindowsMSVC ( ) && <STR_LIT> ) ; assert ( STI . isTargetWin32 ( ) && <STR_LIT> ) ; assert ( STI . is32Bit ( ) && ! Uses64BitFramePtr && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; Register FramePtr = TRI -> getFrameRegister ( MF ) ; Register BasePtr = TRI -> getBaseRegister ( ) ; WinEHFuncInfo & FuncInfo = * MF . getWinEHFuncInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo (


&& flag_expensive_optimizations && ! optimize_size ;


<s> unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; assert ( RI -> regsOverlap ( RegToPrint , Reg ) ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint , isVector ? <STR_LIT> : <STR_LIT> ) ; return false


<s> ++ it ) { reserveHeader ( ) ; it -> m_pLastLocal = & m_SectionData -> back ( ) ; reserve ( it -> m_LocalNum ) ; it -> m_pLastGlobal = & m_SectionData -> back ( ) ; reserve ( it -> m_GlobalNum ) ; it -> m_pLastTLS = & m_SectionData -> back ( ) ; reserve ( it -> m_TLSNum ) ; if ( it == m_MultipartList . begin ( ) ) { reserve ( getGlobalNum ( ) - it -> m_GlobalNum ) ; } else { size_t count = it -> m_GlobalNum + it -> m_LocalNum ; for ( size_t i = <NUM_LIT> ; i < count ; ++ i ) pRelDyn . reserveEntry ( ) ; } for ( size_t i = <NUM_LIT> ; i < it ->

m_TLSDynNum ; ++ i ) pRelDyn . reserveEntry ( ) ;


<s> if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M ,


<s> void <ISA_LIT>FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL

, const MCCFIInstruction & CFIInst ) const {


<s> RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg


<s> IsILP32 = STI . getTargetTriple ( ) . getEnvironment ( ) == Triple :: GNUILP32 ; MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits (


<s> return __builtin_mve_vmladavq_uv4si ( __a ,


<s> static void report_missing_extension ( location_t location , tree fndecl , const char * extension ) { if ( reported_missing_extension_p ) return ; error_at ( location , <STR_LIT> , fndecl , extension ) ; inform ( location , <STR_LIT> <STR_LIT> <STR_LIT> , extension ) ; reported_missing_extension_p =


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) ) { <ISA_LIT>MachineFunctionInfo * MFI = CurDAG -> getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Base = CurDAG -> getRegister ( MFI -> getGlobalBaseReg ( ) , <STR_LIT> ) ; Offset = Addr ; return true ; } } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true


<s> MachineOperand & OldOp1 = OldMI1 . getOperand ( <NUM_LIT> ) ; MachineOperand & OldOp2 = OldMI2 . getOperand ( <NUM_LIT> ) ; MachineOperand & NewOp1 = NewMI1 . getOperand ( <NUM_LIT> ) ; MachineOperand & NewOp2 = NewMI2 . getOperand ( <NUM_LIT> ) ; assert ( OldOp1 . isReg ( ) && OldOp1 . getReg ( ) == <STR_LIT> && OldOp1 . isDead ( ) && <STR_LIT> ) ; assert ( OldOp2 . isReg ( ) && OldOp2 . getReg ( ) == <STR_LIT> && OldOp2 . isDead ( ) && <STR_LIT> ) ; ( void ) OldOp1


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegSet (


<s> bool isABI_EABI ( ) const { return ABI . IsEABI (


<s> MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo

& MRI , const MCTargetOptions & Options ) {


<s> for ( SDValue V : { V1 , V2 } ) { unsigned Opcode ; int ShiftAmt = match1BitShuffleAsKSHIFT ( Opcode , Mask , Offset , Zeroable ) ; if ( ShiftAmt >= <NUM_LIT> ) { MVT WideVT = VT ; if ( ( ! Subtarget . hasDQI ( ) && NumElts == <NUM_LIT> ) || NumElts < <NUM_LIT> ) WideVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getUNDEF ( WideVT ) , V , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( Opcode == <STR_LIT> && WideVT != VT ) { int WideElts = WideVT . getVectorNumElements ( ) ; Res = DAG . getNode ( <STR_LIT> , DL , WideVT , Res , DAG . getTargetConstant ( WideElts - NumElts , DL , <STR_LIT> ) ) ; ShiftAmt += WideElts - NumElts ; } Res = DAG . getNode ( Opcode , DL , WideVT , Res , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } Offset += NumElts ; } MVT ExtVT ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = Subtarget . canExtendTo512DQ ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; ExtVT = Subtarget . canExtendTo512BW ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget . useBWIRegs ( ) ) return SDValue


<s> static MachineOperand & getBaseOperand ( MachineInstr *


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return new <ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std ::

move ( OW ) , std :: move ( Emitter ) ) ;


<s> int <ISA_LIT>ELFFrameLowering :: getOrCreateFramePointerSaveIndex ( MachineFunction & MF ) const { <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int FI = ZFI -> getFramePointerSaveIndex ( ) ; if ( ! FI ) { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; int Offset = getBackchainOffset (


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( FoldedLoad ) { MVT VT = * RC -> vt_begin ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; Load = DAG . getTargetNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , TM ) , dl , VT , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back ( Load ) ; } std :: vector < MVT > VTs ; const TargetRegisterClass * DstRC = <NUM_LIT> ; if ( TID . getNumDefs ( ) > <NUM_LIT> ) { const TargetOperandInfo & DstTOI = TID . OpInfo [ <NUM_LIT> ] ; DstRC = DstTOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( DstTOI . RegClass ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { MVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) TID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; std :: copy ( AfterOps . begin ( ) , AfterOps . end ( ) , std :: back_inserter ( BeforeOps ) ) ; SDNode * NewNode = DAG . getTargetNode ( Opc , dl , VTs , & BeforeOps [ <NUM_LIT> ] , BeforeOps . size ( ) ) ; NewNodes . push_back ( NewNode ) ; if ( FoldedStore ) { AddrOps . pop_back ( ) ; AddrOps . push_back ( SDValue ( NewNode , <NUM_LIT> ) ) ; AddrOps . push_back ( Chain ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; SDNode * Store = DAG . getTargetNode ( getStoreRegOpcode ( <NUM_LIT> , DstRC , isAligned , TM ) , dl , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back


<s> int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT>


<s> if ( ! SRASrc1 || SRASrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Op0 = SignExt . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue SHL = Op0 ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SHLSrc1 || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; * Opc = Accumulate ? <STR_LIT> :


<s> if ( isLogicOp ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) WideRes = computeLogicOpInGPR ( N -> getOperand ( <NUM_LIT> ) ) ; else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return nullptr ; else WideRes = getSETCCInGPR ( N -> getOperand ( <NUM_LIT> ) , N -> getOpcode ( ) == <STR_LIT> ? SetccInGPROpts :: SExtOrig : SetccInGPROpts :: ZExtOrig ) ; if ( ! WideRes ) return nullptr ; SDLoc dl ( N ) ; bool Input32Bit = WideRes . getValueType ( ) == <STR_LIT> ; bool Output32Bit = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ; NumSextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; NumZextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue ConvOp = WideRes ; if ( Input32Bit != Output32Bit ) ConvOp = addExtOrTrunc ( WideRes , Input32Bit ? ExtOrTruncConversion :: Ext : ExtOrTruncConversion :: Trunc


<s> if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; <STR_LIT> P1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> P2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( P1 == P2 ) return true ; if ( P1 == <STR_LIT> && ( P2 == <STR_LIT> || P2 == <STR_LIT> ) ) return true ; if ( P1 == <STR_LIT> && ( P2 == <STR_LIT> || P2 == <STR_LIT> ) ) return true ; return false


<s> LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB )


<s> if ( const auto * C = dyn_cast < ConstantInt > ( MI -> getOperand ( <NUM_LIT> )

) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) return true ;


<s> return __builtin_aarch64_lfrintnusfsi_us ( __a )


<s> OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT_LO32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOTOFF_HI32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOTOFF_LO32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PLT_HI32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_HI32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_LO32 : OS << <STR_LIT> ; break ; case


<s> unsigned Opc = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { if ( Opc == <STR_LIT> ) { AtomicSDNode * AN = cast < AtomicSDNode > ( N . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) , AN -> getOrdering ( ) , AN -> getSynchScope ( ) ) ; } assert ( Opc == <STR_LIT> && <STR_LIT>


<s> for ( i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Index = ZerosFromLeft ? i : NumElems - i - <NUM_LIT> ; SDValue Elt = getShuffleScalarElt ( SVOp , Index , DAG , <NUM_LIT> ) ; if ( ! ( Elt . getNode ( ) && ( Elt . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Elt ) ) ) ) break ; } return i


<s> tree na , ti_decl = CLASSTYPE_TYPEINFO_VAR ( tmv ) ; na = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , NULL_TREE ) ; decl_attributes ( & ti_decl , na , <NUM_LIT> ) ; } for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; else if ( TREE_CODE ( member ) == FUNCTION_DECL ) { tree thunk ; maybe_add_dllexport ( member ) ; for ( thunk = DECL_THUNKS ( member ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) maybe_add_dllexport ( thunk ) ; } for ( member = CLASSTYPE_VTABLES ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; } else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t )


<s> if ( ! Vector ) return <NUM_LIT> ; if ( ST -> hasVector ( )


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS )


<s> OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , TII -> get ( Opc ) ) ; if ( ! isLdStMul ) { MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) { MIB . addImm ( OffsetImm / Scale ) ; } assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; ( * MIB ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase ( MI ) ; ++ NumLdSts


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; return vectorCostAdjustment ( Cost , Opcode , Ty ,


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; unsigned Opt ; if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( ! hasV8Ops ( ) && ( Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> ) ) Opt = ~ <NUM_LIT> ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * MemBarrierID ; if ( getParser ( ) . parseExpression ( MemBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( MemBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc


<s> return ( vcall_offset >= - <NUM_LIT> || ! fixed_regs [


<s> int64_t Offset1 , Offset2 ; if ( ! GetImm ( MI1 , <NUM_LIT> , Offset1 ) ) return false ; if ( ! GetImm ( MI2 , <NUM_LIT> , Offset2 ) ) return false ; unsigned Reg1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg


<s> aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_index ) args [ k ] = SIMD_ARG_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_pair_index ) args [ k ] = SIMD_ARG_LANE_PAIR_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_quadtup_index ) args [ k ] = SIMD_ARG_LANE_QUADTUP_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_struct_load_store_lane_index ) args [ k ] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = SIMD_ARG_CONSTANT ; else if ( d -> qualifiers

[ qualifiers_k ] & qualifier_maybe_immediate ) {


<s> const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) ) return false ; unsigned GPRCnt = <NUM_LIT> ; unsigned FPRCnt = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftAsync ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : ++ GPRCnt


<s> Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else { Shift = <NUM_LIT> ; Expr = getImm ( ) ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr


<s> if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION (

t ) == <NUM_LIT> ) return float_type_node ;


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else return true


<s> OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , Subtarget . is<ISA_LIT>64 ( ) ? <NUM_LIT>


<s> static SDValue combineSetCCEFLAGS ( SDValue EFLAGS , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC , DAG ,


<s> insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else { dbgprintf ( insn , <STR_LIT>


<s> if ( V -> getType ( ) -> isDoubleTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg


<s> uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getOperand (


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOperand ( ) { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; StringRef AsmTokStr = Parser . getTok ( ) . getString ( ) ; if ( ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) && isParsingInlineAsm ( ) ) return ParseIntelOffsetOfOperator ( Start ) ; if ( ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) && isParsingInlineAsm ( ) ) return ParseIntelTypeOperator ( Start ) ; if ( isParsingIntelSyntax ( ) && ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Real ) || getLexer ( ) . is ( AsmToken :: Minus ) ) { const MCExpr * Val ; if ( ! getParser ( ) . ParseExpression ( Val , End ) ) { return <STR_LIT> ( Val , Start , End ) ; } } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; getParser ( ) . Lex


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM .


<s> return aarch64_classify_address ( & addr , x ,


<s> return new <ISA_LIT>PassConfig ( * this ,


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass

* RC , const TargetRegisterInfo * TRI ) const override {


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] (


<s> if ( ! Check ( S , DecodeAddrMode7Operand ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePostIdxReg ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , Cond , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return <NUM_LIT> ; if ( frame_pointer_needed ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ; save_reg_mask |= arm_compute_save_reg0_reg12_mask


<s> return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL

( x ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ;


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>GVSymbol ( const GlobalValue * GV , unsigned char TargetFlags ) { if ( Subtarget -> isTargetMachO ( ) ) { bool IsIndirect = ( TargetFlags & <STR_LIT> ) && Subtarget -> GVIsIndirectSymbol ( GV , TM . getRelocationModel ( ) ) ; if ( ! IsIndirect ) return getSymbol ( GV ) ; MCSymbol * MCSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; return MCSym ; } else if ( Subtarget -> isTargetCOFF ( )


<s> return ( __m128i ) __builtin_ia32_vpcomneqd ( ( __v4si ) __A ,


<s> bool InConstantPool = false ; std :: map < const char * , const <STR_LIT> * > StubsNeeded ; void EmitSled ( const MachineInstr & MI , SledKind Kind ) ; bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; void emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; void emitInlineAsmStart ( ) const override ; void emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const override ; void EmitJal ( const MCSubtargetInfo & STI , MCSymbol * Symbol ) ; void EmitInstrReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( const MCSubtargetInfo & STI , unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction


<s> return __builtin_ia32_ucomisdge ( ( __v2df ) __A , ( __v2df )


<s> return ( __builtin_sh_media_LDLO_Q ( ( char * ) p + <NUM_LIT> ) | __builtin_sh_media_LDHI_Q ( p


<s> return ( ( qword ) ( vec_ld ( <NUM_LIT> , ( vector unsigned char * ) ( imm ) )


<s> Value * <ISA_LIT>IREmitter :: visitVMULLu ( const SDNode * N


<s> if ( CB ) if ( CB -> arg_empty ( ) || ! CB -> paramHasAttr ( <NUM_LIT> , Attribute :: StructRet ) || CB -> paramHasAttr ( <NUM_LIT> , Attribute :: InReg ) || Subtarget -> isTargetMCU


<s> initialize<ISA_LIT>CTRLoopsPass ( PR ) ; initialize<ISA_LIT>CTRLoopsVerifyPass ( PR ) ; initialize<ISA_LIT>LoopPreIncPrepPass ( PR ) ; initialize<ISA_LIT>TOCRegDepsPass ( PR ) ; initialize<ISA_LIT>EarlyReturnPass ( PR ) ; initialize<ISA_LIT>VSXCopyPass ( PR ) ; initialize<ISA_LIT>VSXFMAMutatePass ( PR ) ; initialize<ISA_LIT>VSXSwapRemovalPass ( PR ) ; initialize<ISA_LIT>ReduceCRLogicalsPass ( PR ) ; initialize<ISA_LIT>BSelPass ( PR


<s> if ( ! GlobalBaseReg ) { getGlobalBaseReg ( ) ; initGlobalBaseReg ( )


<s> return ( ( qword ) ( vec_ld ( si_to_uint ( a ) & ~ <NUM_LIT> , ( vector unsigned char * ) ( imm ) )


<s> if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB


<s> static const MCPhysReg * GetFPR ( ) { static const MCPhysReg FPR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> rtx x ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = gen_rtx_VEC_CONCAT ( v2mode , op0


<s> static uint64_t allOnes ( unsigned int Count ) { return Count == <NUM_LIT> ? <NUM_LIT> : ( uint64_t ( <NUM_LIT> )

<< ( Count - <NUM_LIT> ) << <NUM_LIT> ) - <NUM_LIT> ;


<s> int StackSize = ( int ) ( MFI -> getStackSize ( ) ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) - StackSize ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( MI . getOperand ( i + <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) ; MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( i + <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( const GlobalValue * GV , DebugLoc dl , int64_t Offset , SelectionDAG & DAG ) const { unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , getTargetMachine ( ) ) ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy


<s> EVT InScalarVT = InVT . getVectorElementType ( ) ; if ( InScalarVT . getSizeInBits ( ) <= ScalarVT . getSizeInBits ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto IsConstVectorInRange = [ ] ( SDValue V , unsigned Min , unsigned Max ) { BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( V ) ; if ( ! BV || ! BV -> isConstant ( ) ) return false ; for ( SDValue Op : V -> ops ( ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return false ; const APInt & Val = C -> getAPIntValue ( ) ; if ( Val . ult ( Min ) || Val . ugt ( Max ) ) return false ; } return true ; } ; auto LHS = In . getOperand ( <NUM_LIT> ) ; auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; auto AVGBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT>

] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) {


<s> AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> return ( ( TARGET_MS_BITFIELD_LAYOUT && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) ) ) || lookup_attribute ( <STR_LIT> ,


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> static void load_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest = gen_rtx_REG ( word_mode , reg ) ; rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx src ; if ( VAL_14_BITS_P ( disp ) ) src = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , basereg , disp ) ) ; else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , delta


<s> Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; MaxInstLength = <NUM_LIT> ; switch ( TheTriple . getOS ( ) ) { case Triple :: NetBSD : ExceptionsType = ExceptionHandling ::


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool IsThumb , bool IsAndroid ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , IsThumb ( IsThumb ) , IsAndroid ( IsAndroid ) { EHReset ( )


<s> if ( isGPR ( reg ) && ! ( I -> mayLoad ( ) && ! opcount ) ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg ( reg ) ) ; MBB -> insert ( I , cmpInst ) ; MachineInstr * MItest = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( ErrorBB ) ; MBB -> insert ( I


<s> static unsigned offsetMinAlignForOpcode ( unsigned OpC ) { switch ( OpC ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case