<s> if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ; return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine (


<s> unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } DEBUG ( BB -> dump ( )


<s> rtx label = operands [ <NUM_LIT> ] ; emit_insn ( gen_rtx_SET ( gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , gen_rtx_fmt_ee ( code , CCFPmode , operand0 , operand1 ) ) ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( NE , VOIDmode , gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , const0_rtx ) ,

gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ;


<s> rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = const_double_from_real_value ( r_pow , DFmode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec )


<s> Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord P = pReloc . place ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; uint16_t upper_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) ; uint16_t lower_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) ; Relocator :: DWord val = ( ( upper_inst ) << <NUM_LIT> ) | ( lower_inst ) ; Relocator :: DWord A = helper_extract_thumb_movw_movt_addend ( val ) + pReloc . addend ( ) ; Relocator :: DWord X = ( ( S + A ) | T ) - P ; val = helper_insert_val_thumb_movw_movt_inst ( val , X )


<s> bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) ITStates . push_back ( CCBits ) ; else ITStates . push_back ( CCBits ^ <NUM_LIT>


<s> return ( ! SHIFT_COUNT_TRUNCATED || aarch64_vector_mode_supported_p ( mode ) || aarch64_vect_struct_mode_p ( mode ) ) ? <NUM_LIT> : ( GET_MODE_BITSIZE ( mode


<s> inline vector unsigned short vec_vadduhs ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned short ) __builtin_altivec_vadduhs ( ( vector signed short ) a1 , ( vector


<s> case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex


<s> if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI


<s> ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this

) ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , JITInfo ( ) {


<s> if ( MI . getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> ) . isTied ( ) ) MI .


<s> bool sh_symbian_dllexport_name_p ( const char * symbol ) { return strncmp ( DLL_EXPORT_PREFIX , symbol , strlen (


<s> static SDValue lowerV8F64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG )


<s> bool hasV9_1aOps ( ) const { return HasV9_1aOps


<s> bool <ISA_LIT>FastISel :: IsMemcpySmall (


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; if (


<s> static DecodeStatus DecodeSPR_8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler


<s> assert ( VT == N0 . getValueType ( ) && ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( N1 ) -> getAPIntValue ( ) ; if ( ShiftVal . zextOrTrunc ( <NUM_LIT> ) . uge ( NumBitsPerElt ) ) { if ( LogicalShift ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; else ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( Opcode == <STR_LIT> && ( ShiftVal + <NUM_LIT> ) == NumBitsPerElt && N0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( LogicalShift && ( ShiftVal . getZExtValue ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back ( <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , NonceMask , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned ShiftImm = ShiftVal . getZExtValue ( )


<s> MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; <ISA_LIT>TargetELFStreamer * ELFTargetStreamer = static_cast < <ISA_LIT>TargetELFStreamer * > ( getTargetStreamer ( ) ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg


<s> SWAP_INT ( call_used_regs [ i ] , call_used_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_really_used_regs [ i ] , call_really_used_regs [ i + <NUM_LIT> ] ) ; SWAP_STRING ( reg_names [ i ] , reg_names [ i + <NUM_LIT> ]


<s> case <STR_LIT> : ResultPtr = ResultPtr >> <NUM_LIT> ; if ( ( ( ( intptr_t ) ( MR -> getResultPointer ( ) ) & <NUM_LIT> ) >> <NUM_LIT> ) == <NUM_LIT> ) { ResultPtr += <NUM_LIT> ; } * ( ( unsigned * ) RelocPos ) |= ( unsigned ) ResultPtr ; break ; case <STR_LIT> : { int Addend = * ( ( unsigned * ) RelocPos ) & <NUM_LIT> ; ResultPtr = ( ResultPtr + Addend ) & <NUM_LIT> ; * ( ( unsigned * ) RelocPos )


<s> } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { int16_t SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( SImm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> hasSPE (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string SP = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT> , I * <NUM_LIT> * <NUM_LIT> ) ; SExpr * Reg_times_8 = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , SP ) , ctx -> dec_unsigned ( <NUM_LIT>


<s> } MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( ! isTailCall && ! isPatchPoint && ( ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) || Subtarget . isAIXABI ( ) ) ) { if ( CallOpc == <STR_LIT> ) { if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ; CallOpc = <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( CallOpc == <STR_LIT> && ! callsShareTOCBase ( & MF . getFunction ( ) , Callee , DAG . getTarget ( ) ) ) { CallOpc = <STR_LIT> ; } } if ( Subtarget . isAIXABI ( ) && isFunctionGlobalAddress ( Callee ) ) { GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Callee ) ; auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSymbol * S = Context . getOrCreateSymbol ( Twine ( <STR_LIT> ) + Twine ( G -> getGlobal ( ) -> getName ( ) ) ) ; Callee = DAG . getMCSymbol ( S


<s> const <ISA_LIT>Subtarget * STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> has<ISA_LIT>32r6 ( ) || STI -> inMicro<ISA_LIT>Mode ( ) ) return false ; bool Changed = false ; const <ISA_LIT>InstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; bool InsertNop = false ; if ( std :: next ( I ) != FI -> end ( ) && ! TII -> SafeInForbiddenSlot ( * getNextMachineInstr (


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( * this ) { Subtarget = static_cast < <ISA_LIT>TargetMachine & > ( TM ) .


<s> static rtx mips_expand_builtin_compare_1 ( enum insn_code icode , enum mips_fp_condition cond , tree exp , int nargs ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; rtx output ; int opno , argno ; gcc_assert ( nargs + <NUM_LIT> == insn_data [ ( int ) icode ] . n_generator_args ) ; output = mips_allocate_fcc ( insn_data [ ( int ) icode ] . operand [ <NUM_LIT> ] . mode ) ; opno = <NUM_LIT>


<s> if ( isMicro<ISA_LIT> ) { LL = <STR_LIT> ; SC = <STR_LIT> ; } else { LL = Subtarget -> has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget -> has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; } AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; } BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( StoreVal ) . addReg ( Ptr


<s> ForCodeSize = MF . getFunction ( ) -> optForSize ( ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val

== std :: numeric_limits < int32_t > :: min ( ) ) ;


<s> CCState CCRetInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full :


<s> return ( __m128 ) __builtin_ia32_vpermilps ( ( __v4sf ) __X ,


<s> AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch = RegInfo . createVirtualRegister ( RegInfo . getRegClass ( OldVal ) ) ; MachineBasicBlock :: iterator II (


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; return ret


C ( U ) ] \ = add_builtin_function ( N ( L ) , FT1 ( R , A ) , \ C ( U ) , BUILT_IN_MD , NULL , NULL_TREE ) ;


<s> const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeItem :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue ) ; break ; case AttributeItem :: TextAttribute : Streamer . EmitBytes ( item . StringValue ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT>


<s> if ( HARD_REGNO_MODE_OK ( FP_REG_FIRST , mode ) ) size = MIN ( size , UNITS_PER_FPREG ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) FP_REGS ] ) ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size -


<s> void <ISA_LIT>BaseTargetMachine :: addAnalysisPasses (


<s> unsigned Opcode = <NUM_LIT> ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : return true ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc_copysign : case LibFunc_copysignf : continue ; case LibFunc_copysignl : return true ; case LibFunc_fabs : case LibFunc_fabsf : case LibFunc_fabsl : continue ; case LibFunc_sqrt : case LibFunc_sqrtf : case LibFunc_sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc_floor : case LibFunc_floorf : case LibFunc_floorl : Opcode = <STR_LIT> ; break ; case LibFunc_nearbyint : case LibFunc_nearbyintf : case LibFunc_nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc_ceil : case LibFunc_ceilf : case LibFunc_ceill : Opcode = <STR_LIT> ; break ; case LibFunc_rint : case LibFunc_rintf : case LibFunc_rintl : Opcode = <STR_LIT> ; break ; case LibFunc_round : case LibFunc_roundf : case LibFunc_roundl : Opcode = <STR_LIT> ; break ; case LibFunc_trunc : case LibFunc_truncf : case LibFunc_truncl : Opcode = <STR_LIT> ; break ; case LibFunc_fmin : case LibFunc_fminf : case LibFunc_fminl : Opcode = <STR_LIT> ; break ; case LibFunc_fmax : case


<s> else errs ( ) << <STR_LIT> << LazyPtr << <STR_LIT> << Fn << <STR_LIT> ) ; } JCE . emitAlignment ( <NUM_LIT> ) ; Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( LazyPtr - ( intptr_t ( Addr ) + <NUM_LIT> + <NUM_LIT> ) ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } else { JCE . emitAlignment ( <NUM_LIT> ) ; Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } } } else { JCE . emitAlignment ( <NUM_LIT> ) ; Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( ! sys :: Memory :: setRangeWritable ( Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } JCE . emitWordLE ( <NUM_LIT>


<s> static MachineInstr * insertCopy ( const TargetInstrInfo * TII , MachineInstr & MI , unsigned Dst , unsigned Src , bool IsKill ) { MachineInstrBuilder MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << *


<s> BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI . eraseFromParent ( )


<s> if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == HIGH ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return


<s> if ( Printer . TM . getTargetTriple ( ) . isOSDarwin ( ) ) return lowerSymbolOperandDarwin ( MO , Sym ) ; if ( Printer . TM . getTargetTriple ( ) . isOSBinFormatCOFF ( ) ) return lowerSymbolOperandCOFF ( MO , Sym ) ; assert ( Printer . TM . getTargetTriple ( ) . isOSBinFormatELF ( ) && <STR_LIT> ) ; return lowerSymbolOperandELF ( MO , Sym


<s> const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op


<s> if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == PLUS ) { rtx unspec = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( unspec ) == UNSPEC && ( XINT ( unspec , <NUM_LIT> ) == UNSPEC_TLSGD ||

XINT ( unspec , <NUM_LIT> ) == UNSPEC_TLSLDM ) ) return <NUM_LIT> ;


<s> BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; Warning ( IDLoc , <STR_LIT> ) ; return false ; } return false ; } if ( IsSrcRegZero || IsTrgRegZero ) { if ( ( IsSrcRegZero && PseudoOpcode == <STR_LIT> ) || ( IsTrgRegZero && PseudoOpcode == <STR_LIT> ) ) { return false ; } if ( ( IsSrcRegZero && PseudoOpcode == <STR_LIT> ) || ( IsTrgRegZero && PseudoOpcode == <STR_LIT> ) ) { BranchInst . setOpcode ( <STR_LIT> ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; Warning ( IDLoc , <STR_LIT> ) ; return false ; } if ( IsUnsigned ) { BranchInst . setOpcode ( AcceptsEquality ? <STR_LIT> : <STR_LIT> ) ; BranchInst . addOperand ( MCOperand :: createReg ( IsSrcRegZero ? TrgReg : SrcReg ) ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; return false ; } BranchInst . setOpcode ( IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode ) ; BranchInst . addOperand ( MCOperand :: createReg ( IsSrcRegZero ? TrgReg : SrcReg ) ) ; BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; return false ; } unsigned ATRegNum = getATReg ( IDLoc ) ; if ( ! ATRegNum ) return true ; warnIfNoMacro ( IDLoc ) ; MCInst SetInst ; SetInst . setOpcode ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) ; SetInst . addOperand ( MCOperand :: createReg ( ATRegNum ) ) ; SetInst . addOperand ( MCOperand :: createReg ( ReverseOrderSLT ? TrgReg : SrcReg ) ) ; SetInst . addOperand ( MCOperand :: createReg ( ReverseOrderSLT ? SrcReg : TrgReg ) ) ; Instructions . push_back ( SetInst ) ; if ( ! IsLikely ) BranchInst . setOpcode ( AcceptsEquality ? <STR_LIT> : <STR_LIT> ) ; else BranchInst . setOpcode ( AcceptsEquality ? <STR_LIT> : <STR_LIT> ) ; BranchInst . addOperand ( MCOperand :: createReg ( ATRegNum ) ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createExpr (


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocReg ( Reg , S ) ) ; return


<s> gcc_assert ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == MEM ) ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; rtx_insn * and_insn ; rtx and_operation = find_alignment_op ( insn , base_reg , & and_insn ) ; if ( and_operation != <NUM_LIT> ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx and_base = XEXP ( and_operation , <NUM_LIT> ) ; rtx new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; rtx copy = gen_rtx_SET ( new_reg ,


<s> static const IntrinsicData * getIntrinsicWithoutChain ( unsigned IntNo ) { const IntrinsicData * Data = lower_bound ( IntrinsicsWithoutChain , IntNo ) ; if ( Data != std :: end ( IntrinsicsWithoutChain ) && Data -> Id == IntNo ) return Data ; return nullptr


<s> break ; case LT : libfunc = op_mode == DFmode ? ltdf_libfunc : ltsf_libfunc ; break ; case LE : libfunc = op_mode == DFmode ? ledf_libfunc : lesf_libfunc ; break ; default : gcc_unreachable ( ) ; } start_sequence ( ) ; cmp = emit_library_call_value ( libfunc , <NUM_LIT> , LCT_CONST , SImode , op0 , op_mode , op1 , op_mode ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) ; return gen_rtx_fmt_ee ( jump_code , mode ,


<s> while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear (


<s> <STR_LIT> <STR_LIT> ( <STR_LIT> Opcode ) { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> PrintRegName ( O , getRegisterName ( Op . getReg ( ) ) ) ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Shift .


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; SDValue Mask = N -> getMask ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; if ( MaskVT . getVectorElementType ( ) != <STR_LIT> ) { if ( PassThru . isUndef ( ) || <STR_LIT> ( PassThru . getNode ( ) ) ) return Op ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getOffset ( ) , Mask , getZeroVector ( VT , Subtarget , DAG , dl ) , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getAddressingMode ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Select = DAG . getNode ( <STR_LIT> , dl , VT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Select , NewLoad . getValue ( <NUM_LIT> ) } , dl ) ; } assert ( ( ! N -> isExpandingLoad ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isExpandingLoad ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> /


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const MachineOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg (


<s> bool src_vliw = mep_vliw_function_p ( cfun -> decl ) ; bool tgt_vliw = INTVAL ( tgt ) ; return src_vliw ==


<s> SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( DAG . SignBitIsZero ( Op0 ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT ,


<s> unsigned getMemOp ( ) const { assert ( isMem ( ) && <STR_LIT> ) ; return Mem . AluOp


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp , ArrayRef < const Value * > Args ) { InstructionCost CostFactor = vectorCostAdjustmentFactor ( Instruction :: ShuffleVector , Tp , nullptr ) ; if ( ! CostFactor . isValid ( )

) return InstructionCost :: getMax ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T ,

TT , FS , false ) , InstrInfo ( Subtarget ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) :


<s> OperandMatchResultTy parseGR64 ( OperandVector & Operands ) { return parseRegister ( Operands , GR64Reg


<s> TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) { MF . getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; } LoweringMap Lowerings ; computeLowerings ( MF , Lowerings


<s> case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 : return <NUM_LIT> ; case FK_PCRel_8


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; unsigned Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto UShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Src2Reg } ) ; constrainSelectedInstRegOperands ( * UShl , TII , TRI , RBI ) ; I . eraseFromParent (


<s> case CmpInst :: Predicate :: ICMP_NE : ExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : ExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: ICMP_ULT : case CmpInst :: Predicate :: ICMP_UGT : ExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_UGE : if ( ( ST -> hasSSE41 ( ) && MTy . getScalarSizeInBits ( ) == <NUM_LIT> ) || ( ST -> hasSSE2 ( ) && MTy . getScalarSizeInBits ( ) < <NUM_LIT> ) ) { ExtraCost = <NUM_LIT> ; } else { ExtraCost = <NUM_LIT> ; } break ; case CmpInst :: Predicate :: BAD_ICMP_PREDICATE : case CmpInst :: Predicate :: BAD_FCMP_PREDICATE : ExtraCost = <NUM_LIT> ; break ; default : break ; } } } static const CostTblEntry SLMCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ]


<s> case PLUS : case MINUS : break ; default : gcc_unreachable ( ) ; } before = gen_reg_rtx ( SImode ) ; if ( after ) after = gen_reg_rtx ( SImode ) ; store_mode = mode = SImode ; } } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = expand_simple_binop ( mode , AND , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_simple_unop ( mode , NOT , x , after , <NUM_LIT> ) ; } else { after = expand_simple_binop ( mode , code , before , val , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = after ; if ( mask ) { x = expand_simple_binop ( SImode , AND , after , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = rs6000_mask_atomic_subword ( before , x , mask ) ; } else if ( store_mode != mode ) x = convert_modes ( store_mode , mode , x , <NUM_LIT> ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( store_mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift


<s> return ( frame_pointer_needed || ! crtl -> is_leaf || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( regno ) ) ; case HW_TO_GCC_REGNO ( <NUM_LIT> ) : case HW_TO_GCC_REGNO ( <NUM_LIT> ) : case HW_TO_GCC_REGNO (


<s> static void DecodePUNPCKLMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( i )


<s> SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; bool isST0 = VA . getLocReg ( ) == <STR_LIT> ; unsigned Opc = <NUM_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( Opc , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } Val = DAG . getNode ( <STR_LIT> , dl , CopyVT , Val ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) ,

CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> SDValue CCReg ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; CCReg = emitMemMemImm ( DAG , DL , <STR_LIT>


<s> O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo + <NUM_LIT>


<s> const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT>


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_prefetch_i64gather_ps ( __m512i index , __mmask8 mask , void * addr , int scale , int hint ) { __builtin_ia32_gatherpfqps ( mask , ( __v8di ) index , ( int


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( isThumb && <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; NumUBrFixed ++ ; DOUT << <STR_LIT> <<


<s> if ( Count == <NUM_LIT> ) { return true


<s> bool hasArithmeticCbzFusion ( ) const { return


<s> } case MULT : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case PLUS : { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; machine_mode op1_mode = GET_MODE ( op1 ) ; if ( op1_mode == VOIDmode && CONST_INT_P ( op1 ) && outer_code == MEM ) op1_mode = Pmode ; if ( outer_code == MEM && ( ( REG_P ( op0 ) && reg_or_ubyte_operand ( op1 , op1_mode ) ) || ctable_addr_operand ( op0 , VOIDmode ) || ctable_addr_operand ( op1 , VOIDmode ) || ( ctable_base_operand ( op0 , VOIDmode ) && REG_P ( op1 ) ) || ( ctable_base_operand ( op1 , VOIDmode ) && REG_P ( op0 ) ) ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } } case SIGN_EXTEND : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ASHIFTRT : { rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( const_1_operand ( op1 , VOIDmode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ZERO_EXTRACT : { rtx op2 = XEXP ( x , <NUM_LIT> ) ; if ( ( outer_code == EQ || outer_code == NE ) && CONST_INT_P ( op2 ) && INTVAL ( op2 ) == <NUM_LIT> ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS (


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int Off = Offset ; unsigned i = <NUM_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; else { assert ( AFI ->


<s> StringRef getPassName ( ) const override


<s> SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( GV -> isDeclaration ( ) ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , dl , PtrVT , GetGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> ,


<s> return isMemDisp12 ( ADDR64Reg , BDMem


<s> SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits (


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module &


<s> if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT> : { ++ CurOp ; break ; } case <STR_LIT> : { emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; break ; } } uint64_t Encoding = TSFlags & <STR_LIT> ; bool HasREX = false ; if ( Encoding ) emitVEXOpcodePrefix ( MemoryOperand , MI , OS ) ; else HasREX = emitOpcodePrefix ( MemoryOperand ,


<s> static int supersparc_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( ! recog_memoized ( insn ) ) return <NUM_LIT> ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == <NUM_LIT> ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD )


<s> return ( __m512i ) __builtin_ia32_compressdi512_mask ( ( __v8di ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , (


<s> uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * <NUM_LIT>


<s> static DecodeStatus DecodeAddrMode7Operand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { return DecodeGPRRegisterClass ( Inst , Val , Address


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . has<ISA_LIT>64 ( ) ) return Subtarget . has<ISA_LIT>64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . has<ISA_LIT>32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( )


<s> static __inline qword si_fms ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , vec_sub ( ( (

vec_float4 ) { <NUM_LIT> } ) , ( vec_float4 ) ( c ) ) ) ) ) ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return Kind - FirstLiteralRelocationKind ; if ( const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) ) { if ( SExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 ) return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; } if ( IsPCRel ) { switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>8 ; case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_NONE : return ELF ::


<s> void <ISA_LIT>ConstantIslands :: dumpBBs ( ) { for ( unsigned J = <NUM_LIT> , E = BBOffsets . size ( ) ; J != E ; ++ J ) { DOUT ( llvm :: dbgs ( ) << <STR_LIT> << J << <STR_LIT> << BBOffsets [ J

] << <STR_LIT> << BBSizes [ J ] << <STR_LIT> ) ;


<s> static <ISA_LIT>Operand * CreateReg ( unsigned RegNum , bool isVector , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Register , Ctx


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSimm23Lsl2Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) &&


<s> unsigned getMinPrefetchStride ( ) { return <NUM_LIT>


<s> static void MoveBelowTokenFactor ( SelectionDAG * CurDAG , SDValue Load , SDValue Store , SDValue TF ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = TF . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) if ( Load . getNode ( ) == TF . getOperand ( i ) . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( TF . getOperand ( i ) ) ; SDValue NewTF = CurDAG -> UpdateNodeOperands ( TF , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; SDValue NewLoad = CurDAG -> UpdateNodeOperands ( Load , NewTF , Load . getOperand ( <NUM_LIT>


<s> __attribute__ ( ( vector_size ( <NUM_LIT> * sizeof ( float ) ) ) ) ; static __inline unsigned long long sh_media_MABS_L ( unsigned long long mm ) { typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_absv2si2 ( ( v2si


<s> if ( TARGET_CBCOND && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && ( GET_MODE ( operands [ <NUM_LIT> ] ) == SImode || ( TARGET_ARCH64 && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) ) && ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT || SPARC_SIMM5_P ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) ) { emit_cbcond_insn ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } if ( TARGET_ARCH64 && operands [ <NUM_LIT> ] == const0_rtx && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) { emit_v9_brxx_insn ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands


<s> vector unsigned int v ; unsigned int i [ <NUM_LIT> ] ; } aa ; aa . v = ( vector unsigned int ) ( a ) ; if ( aa . i [ <NUM_LIT> ] > b


<s> vpaddq_f64 ( float64x2_t a , float64x2_t b ) { float64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> unsigned Alignment = IntrAlign -> getLimitedValue ( ) < MemAlign ? MemAlign : IntrAlign -> getLimitedValue ( ) ; if ( ! isPowerOf2_32 ( Alignment ) ) return nullptr ; auto * BCastInst = Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , PointerType :: get ( II . getType ( ) , <NUM_LIT> ) ) ; return Builder . CreateAlignedLoad ( II . getType ( ) , BCastInst , Align ( Alignment )


<s> static SDValue foldADCToCINC ( SDNode * N , SelectionDAG & DAG ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( ! isNullConstant ( RHS ) )


<s> return Result . first ; } } int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; } Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> - ( <NUM_LIT> - BitNo ) , dl , <STR_LIT> ) ) ; Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags ,

DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> for ( const MachineOperand & MO : MI . implicit_operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) ) if ( TRI -> regsOverlap ( Reg , MO . getReg (


<s> getBranchTarget21OpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr (


<s> } case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( MI . getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI . getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI . getOperand


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG


<s> static rtx function_value_ms_32 ( machine_mode orig_mode , machine_mode mode , const_tree fntype , const_tree fn , const_tree valtype ) { unsigned int regno ; if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 && ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || valtype == NULL_TREE


<s> SExpr * output_pos = ctx -> s_ge ( <NUM_LIT> , output , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * arg1_neg = ctx -> s_lt ( <NUM_LIT> , ctx -> load ( <NUM_LIT> , Rn ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * arg2_neg = ctx -> s_lt ( <NUM_LIT> , arg2_sexpr , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * output_neg = ctx -> s_lt ( <NUM_LIT> , output , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * V = ctx -> or_ ( <NUM_LIT> , ctx -> and_ ( <NUM_LIT> , ctx -> and_ ( <NUM_LIT> , arg1_pos , arg2_neg ) , output_neg ) , ctx -> and_ ( <NUM_LIT> , ctx -> and_ ( <NUM_LIT> , arg1_neg , arg2_pos ) , output_pos ) ) ; SExpr * expr_nzcv = ctx -> conc ( <NUM_LIT> , <NUM_LIT> , ctx -> conc ( <NUM_LIT> , <NUM_LIT> , ctx -> conc ( <NUM_LIT> , <NUM_LIT> , ctx -> s_lt ( <NUM_LIT> , output , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , output , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) , ctx -> conc ( <NUM_LIT> , <NUM_LIT> , csub , V ) ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; SExpr * stor_nzcv = ctx -> store ( ctx -> address


<s> static <ISA_LIT>Operand * CreateMSACtrlReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc

S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegList ( SmallVectorImpl < unsigned > & Regs , SMLoc StartLoc , SMLoc EndLoc , <ISA_LIT>AsmParser & Parser ) { assert ( Regs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; auto Op = std :: make_unique < <ISA_LIT>Operand >


<s> assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isUndefOrZeroOrInRange ( Mask , <NUM_LIT> , <NUM_LIT> * NumElts ) && <STR_LIT> ) ; bool ZeroLane [ <NUM_LIT> ] = { true , true } ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) ZeroLane [ i & <NUM_LIT> ] &= Zeroable [ i ] ; ShuffleImm = <NUM_LIT> ; bool ShufpdMask = true ; bool CommutableMask = true ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( Mask [ i ] == SM_SentinelUndef || ZeroLane [ i & <NUM_LIT> ] ) continue ; if ( Mask [ i ] < <NUM_LIT> ) return false ; int Val = ( i & <NUM_LIT> ) + NumElts * ( i & <NUM_LIT> ) ; int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i ] > Val + <NUM_LIT> ) ShufpdMask


<s> static bool CalculateStackSlotUsed ( EVT ArgVT , EVT OrigVT , <STR_LIT> Flags , unsigned PtrByteSize , unsigned LinkageSize , unsigned ParamAreaSize , unsigned & ArgOffset , unsigned & AvailableFPRs , unsigned & AvailableVRs , bool HasQPX ) { bool UseMemory = false ; Align Alignment = CalculateStackSlotAlignment ( ArgVT , OrigVT , Flags , PtrByteSize ) ; ArgOffset = alignTo ( ArgOffset , Alignment ) ; if ( ArgOffset >= LinkageSize + ParamAreaSize ) UseMemory = true ; ArgOffset += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; if ( Flags . isInConsecutiveRegsLast ( ) ) ArgOffset = ( ( ArgOffset + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; if ( ArgOffset > LinkageSize + ParamAreaSize ) UseMemory = true ; if ( ! Flags . isByVal (


<s> if ( ! isImm ( ) ) return false ; if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return isUInt < <NUM_LIT>


<s> bool <ISA_LIT>InstructionSelector :: selectJumpTable ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_JUMP_TABLE && <STR_LIT> ) ; assert ( I . getOperand ( <NUM_LIT> ) . isJTI ( ) && <STR_LIT> ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned JTI = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; auto MovMI = MIB . buildInstr ( <STR_LIT> , { DstReg } , { } ) . addJumpTableIndex ( JTI , <STR_LIT> ) . addJumpTableIndex ( JTI , <STR_LIT> | <STR_LIT> ) ; I . eraseFromParent (


<s> assert ( MI && <STR_LIT> ) ; StackOffset SaveOffset ( Offset ,


<s> id = TREE_VALUE ( TREE_VALUE ( model_attr ) ) ; if ( id == small_ident1 || id == small_ident2 ) return


<s> void Thumb1InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I ->


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , true


<s> MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val !=


<s> return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> && ( regno == STACK_POINTER_REGNUM || regno >= FIRST_PSEUDO_REGISTER || x ==

hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ;


<s> const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned storesuccess = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; if ( isThumb2 ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( destlo , RegState :: Define ) . addReg ( desthi , RegState :: Define ) . addReg ( ptr ) ) ; } else { unsigned GPRPair0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( GPRPair0 , RegState :: Define ) . addReg ( ptr ) ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; } unsigned StoreLo , StoreHi ; if ( IsCmpxchg ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( i == <NUM_LIT> ? destlo : desthi ) . addReg ( i == <NUM_LIT> ? vallo : valhi ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( exitMBB ) ; BB -> addSuccessor ( i == <NUM_LIT> ? contBB : cont2BB ) ; BB = ( i == <NUM_LIT> ? contBB : cont2BB ) ; } StoreLo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; StoreHi = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( Op1 ) { unsigned tmpRegLo = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op1 ) , tmpRegLo ) . addReg ( destlo ) . addReg ( vallo ) ) . addReg ( NeedsCarry ? <STR_LIT> : <NUM_LIT> , getDefRegState ( NeedsCarry ) ) ; unsigned tmpRegHi = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op2 ) , tmpRegHi ) . addReg ( desthi ) . addReg ( valhi ) ) . addReg ( IsMinMax ? <STR_LIT> : <NUM_LIT> , getDefRegState ( IsMinMax ) ) ; StoreLo =


<s> case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : case Match_AlignedMemoryRequires64 : case Match_DupAlignedMemoryRequires64 : case Match_AlignedMemoryRequires64or128 : case Match_DupAlignedMemoryRequires64or128 : case Match_AlignedMemoryRequires64or128or256 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getAlignmentLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; switch ( MatchResult ) { default : llvm_unreachable ( <STR_LIT> ) ; case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires64 : case Match_DupAlignedMemoryRequires64


<s> if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case FK_Data_1 : case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static unsigned SelectInt64CountDirect ( int64_t Imm ) { unsigned Remainder = <NUM_LIT> ; unsigned Shift = <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if


<s> DOUT ( llvm :: dbgs ( ) << <STR_LIT> << LabelID << <STR_LIT> << ( void * ) MCE . getCurrentPCValue


<s> return ( unsigned long long ) __builtin_sh_media_MSHFHI_B ( ( v8qi ) mm ,


<s> } MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) return Error ( ExtLoc , <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension . Features ) ; FeatureBitset Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; return


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) break ; I -> eraseFromParent (


<s> if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares (


<s> bool isTarget64BitLP64 ( ) const { return Is64Bit && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < NUM_ARGUMENT_REGISTERS && * cum + XSTORMY16_WORD_SIZE ( type , mode

) > NUM_ARGUMENT_REGISTERS ) * cum = NUM_ARGUMENT_REGISTERS ;


<s> const MCSymbol * <ISA_LIT>ELFObjectWriter :: ExplicitRelSym ( const MCAssembler & Asm , const MCValue & Target , const MCFragment & F , const MCFixup & Fixup , bool IsPCRel ) const { if ( ! Target . getSymA ( ) ) return NULL ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break


<s> case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( <STR_LIT> [ I ] ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset + Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy


<s> } const Align Align = MF -> getAlignment ( ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << Log2 ( Align ) << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= Align . value ( ) ; EndInsertOffset -= Align .


<s> std :: string <ISA_LIT>LowerMASSVEntries :: createMASSVFuncName ( Function & Func , const <ISA_LIT>Subtarget * Subtarget ) { StringRef Suffix = getCPUSuffix ( Subtarget ) ; auto GenericName = Func . getName ( ) . drop_back ( MASSVSuffixLength ) . str ( ) ; std :: string MASSVEntryName = GenericName + Suffix


<s> if ( ! Load || ! Load -> isSimple ( ) ) return false ; if ( Load -> getType ( ) != FixedPredType ) return false ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( Load ) ; auto * PtrBitCast = Builder . CreateBitCast ( Load -> getPointerOperand ( ) , PredType -> getPointerTo ( Load -> getPointerAddressSpace ( ) ) ) ; auto * LoadPred = Builder . CreateLoad ( PredType , PtrBitCast ) ; BitCast -> replaceAllUsesWith ( LoadPred ) ; BitCast -> eraseFromParent ( ) ; if ( IntrI -> getNumUses ( ) == <NUM_LIT> ) IntrI -> eraseFromParent ( ) ; if ( Load -> getNumUses ( ) == <NUM_LIT> ) Load ->


<s> bool isUpperSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal , const <STR_LIT>


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; PM . add ( createNoTargetTransformInfoPass ( ) ) ; } else LLVMTargetMachine :: addAnalysisPasses


<s> static int FindInConvertTable ( const <ISA_LIT>TypeConversionCostTblEntry * Tbl , unsigned len , int ISD , MVT Dst , MVT Src ) { for ( unsigned int i = <NUM_LIT> ; i < len ; ++ i ) if ( Tbl [ i ] . ISD == ISD && Tbl [ i ] . Src == Src && Tbl [ i


<s> GetJumpTableSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable (


<s> return new <ISA_LIT>PassConfig ( * this


<s> return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && ( signed_p ? IN_RANGE ( INTVAL ( elt ) , - <NUM_LIT> , <NUM_LIT>

) : IN_RANGE ( INTVAL ( elt ) , <NUM_LIT> , <NUM_LIT> ) ) ) ;


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo +


<s> SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOStore ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; Chain = CWD . getValue ( <NUM_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; SDValue LUT = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LUT , Shift ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; RetVal = DAG . getZExtOrTrunc ( RetVal , DL , VT ) ; return DAG . getMergeValues ( { RetVal ,


<s> printThumbAddrModeRI5Operand ( MI , Op , O


<s> SDValue <ISA_LIT>TargetLowering :: LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = DAG . getTargetLoweringInfo


<s> CCValAssign & VA = ArgLocs [ I ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> || ArgVT == <STR_LIT> || ! VA . isRegLoc ( ) || VA . needsCustom ( ) ) return false ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) return false ; } NumBytes = CCInfo . getNextStackOffset ( ) ; NumBytes = std :: max ( NumBytes , LinkageSize + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TII . getCallFrameSetupOpcode ( ) ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; unsigned NextGPR = <STR_LIT> ; unsigned NextFPR = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: BCvt


<s> static SDValue lowerShuffleAsInsertPS ( const SDLoc & DL , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT>


<s> return ( int16x4_t ) __builtin_neon_vld1v4hi ( ( const __builtin_neon_hi *


<s> fma_slot = this -> m_insn_fma_head_map -> get ( insn ) ; if ( fma_slot ) return * fma_slot ; return


<s> return MI . modifiesRegister ( <STR_LIT> , TRI


<s> unsigned Reg ; SMLoc DummyLoc ; if ( ParseRegister ( Reg , DummyLoc , DummyLoc ) || Parser . parseEOL ( <STR_LIT> ) ) return addErrorSuffix ( <STR_LIT> ) ; return getTargetStreamer ( ) . emitFPOSetFrame ( Reg , L


<s> CallingConv :: ID CC = CLI . CallConv ; emitInst ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT> ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor (


<s> unsigned VBI = Bits [ i ] . getValueBitIndex ( ) ; if ( i >= VBI ) RLAmt [ i ] = i - VBI ; else RLAmt [ i ] = Bits . size ( ) - ( VBI - i ) ; } else if ( Bits [ i ] . isZero ( ) ) { NeedMask = true ; RLAmt [ i ] =


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ; AFI -> setVarArgsFrameIndex (


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ( maxCallFrameSize & ( MaxAlign - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill )

. addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ;


<s> assert ( hasValue ( ) && <STR_LIT> ) ; return Idx


<s> __v4si result ; __v4si temp ; const __v4si vzero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __asm__ ( <STR_LIT> : <STR_LIT> ( temp ) : <STR_LIT> ( __A ) : ) ; temp = vec_mergeo ( temp , temp ) ; result = ( __v4si ) vec_vpkudum ( ( __vector long ) temp , ( __vector long


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ShifterImmediate ) ; Op -> ShifterImm . isASR = isASR ; Op -> ShifterImm . Imm = Imm ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return


<s> if ( TREE_CODE ( exp ) == VAR_DECL && ! is_global_var ( exp ) ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ; return


<s> case <STR_LIT> : return & * I ; } ++ NumCmpTermRejs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; return nullptr ; } for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isDeadDef ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return & * I ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumLiveDstRejs ; return nullptr ; case <STR_LIT> : case <STR_LIT> : case


<s> return ( __m128i ) __builtin_ia32_pmovsqw256_mask ( ( __v4di ) __A , ( __v8hi )

_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> APSInt IntVal ( <NUM_LIT> , true ) ; FVal . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ; if ( ! IsExact || ! IntVal . isPowerOf2 ( ) ) return false ; unsigned FBits = IntVal . logBase2 ( ) ; if ( FBits == <NUM_LIT> || FBits > RegWidth ) return false ; FixedPos = CurDAG -> getTargetConstant ( FBits , SDLoc ( N ) ,


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return

<STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ;


<s> unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; unsigned Alignment = std :: min ( Flags . getByValAlign ( ) , RegSizeInBytes ) ; EVT PtrTy = getPointerTy ( ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; unsigned NumRegs = LastReg - FirstReg ; if ( NumRegs ) { const ArrayRef < MCPhysReg > ArgRegs = Subtarget . getABI ( ) . GetByValArgRegs ( ) ; bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy

, LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ;


<s> void getForFrameOffset ( int64_t & ByteSized )


<s> if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) add_to_hard_reg_set ( & set

-> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ;


<s> unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT

) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask

, Zeroable , Subtarget , DAG ) ) return Shift ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case rk_FloatReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return <NUM_LIT> ; Reg = QuadFPRegs [ regIdx


<s> float64x2x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * F


<s> return ( get_attr_got ( insn ) != GOT_UNSET || mips_small_data_pattern_p ( PATTERN ( insn )

) || reg_overlap_mentioned_p ( pic_offset_table_rtx , PATTERN ( insn ) ) ) ;


<s> VariantKind getKind ( ) const { return


<s> return isCommutedMOVLMask ( M , N -> getValueType ( <NUM_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex


<s> unsigned NumOps = MCID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber ( ) ; if ( DTNumber < JTNumber ) { MachineBasicBlock * NewBB = adjustJTTargetBlockForward ( MBB


<s> static void logger ( void * arg , const char * log ) { if ( ! arg ) return ; raw_ostream & vStream = * ( static_cast < raw_ostream * > ( arg ) ) ; vStream << log <<


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I


<s> int getReturnAddrSaveIndex ( ) const { return ReturnAddrSaveIndex


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! <ISA_LIT>FI -> getLOHRelated ( ) .


<s> MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; MachineBasicBlock :: iterator InsertPoint = MI -> getNextNode ( ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VSRCTmp1 ) . addReg ( NewVReg ) ; DEBUG ( MI -> getNextNode ( ) -> dump ( ) ) ; insertSwap ( MI , InsertPoint , VSRCTmp2 , VSRCTmp1 ) ; DEBUG ( MI -> getNextNode ( ) -> getNextNode ( ) -> dump ( ) ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( VSRCTmp2 ) ; DEBUG ( MI -> getNextNode ( ) -> getNextNode ( ) -> getNextNode ( ) -> dump ( ) ) ; } else { insertSwap ( MI , InsertPoint , DstReg , NewVReg ) ; DEBUG ( MI -> getNextNode ( ) -> dump (


<s> MachineBasicBlock :: iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = llvm :: next ( MII ) ; MachineInstr * MI = & * MII ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( SIGNED_INTEGER_16BIT_P ( value ) ) return <NUM_LIT> ; else if ( ( value & <NUM_LIT> ) == <NUM_LIT> && ( value >> <NUM_LIT> == - <NUM_LIT> || value >> <NUM_LIT> == <NUM_LIT> ) ) return <NUM_LIT> ; else if ( TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P ( value ) ) return <NUM_LIT> ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = sext_hwi ( value , <NUM_LIT> ) ; HOST_WIDE_INT high = value


<s> if ( HAS_VLINDEX ( MCID . TSFlags ) ) return GET_VLINDEX ( MCID . TSFlags ) ; return - <NUM_LIT>


<s> EmitRawState ( <ISA_LIT>MCNaClSFIState & S ) : State (


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true )


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectIntAddr11MM ( SDValue Addr , SDValue & Base , SDValue &