<s> case <STR_LIT> : return expandDiv ( Inst , IDLoc , Out , STI , true , false ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandTrunc ( Inst , false , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandTrunc ( Inst , true , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandTrunc ( Inst , true , true , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlh ( Inst , true , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlh ( Inst , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlw ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( ImmValue ) ) return MER_NotAMacro ; return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; } return MER_NotAMacro ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUInt < <NUM_LIT> > ( ImmValue ) ) return MER_NotAMacro ; return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; } return MER_NotAMacro ; case <STR_LIT> : case <STR_LIT> : return expandRotation ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case


<s> } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Scale , Index , Disp ) ; return


<s> const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame -> getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_vpcomgtuw ( ( __v8hi )


<s> assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; return get<ISA_LIT>RegisterNumbering ( MO . getReg (


<s> if ( Fn . hasFnAttribute ( <STR_LIT> ) ) Fn . getFnAttribute ( <STR_LIT>

) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; MVT SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; const unsigned Reg = ( Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned SPReg = RegInfo ->


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } } bool isFP = Op1 . getValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return


<s> return ; } SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) && ! GVKind . isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( isVerbose ( ) ) { if ( GV -> hasInitializer ( ) ) { GV -> printAsOperand ( OutStreamer -> GetCommentOS ( ) , false , GV -> getParent ( ) ) ; OutStreamer -> GetCommentOS ( ) << '\n' ; } } MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> hasCommonLinkage ( ) || GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; if ( ! TM . getDataSections ( ) || GV -> hasSection ( ) ) { OutStreamer -> emitLabel ( EmittedInitSym ) ; } llvm :: for_each ( GOAliasMap [ GV ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getSymbol ( Alias )


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler *


<s> static void assign_csky_minipool_offsets ( Mfix * barrier ) { HOST_WIDE_INT offset = <NUM_LIT> ; Mnode * mp ; minipool_barrier = barrier ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { mp -> offset = offset


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performLDNT1Combine ( N , DAG ) ; case <STR_LIT> : return performLDNF1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLDNF1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performSTNT1Combine ( N , DAG ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG ,


<s> const unsigned PtrByteSize = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; static const MCPhysReg GPR_32 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : State . AllocateStack ( PtrByteSize , PtrByteSize ) ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { MVT RegVT = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; } else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , <NUM_LIT> ) ; if ( unsigned Reg = State . AllocateReg ( FPR ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < StoreSize ; i += PtrByteSize ) State . AllocateReg ( Is<ISA_LIT>64 ?


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool Upper = IdxVal >= NumElems / <NUM_LIT> ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( Upper ? IdxVal - NumElems / <NUM_LIT> : IdxVal , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } return SDValue (


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrAddiuOp ( )


<s> newsrc = gen_rtx_LABEL_REF ( VOIDmode , lab ) ; emit_insn ( gen_sp_switch_1 ( newsrc ) ) ; } HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( target_flags != save_flags && ! current_function_interrupt ) emit_insn ( gen_toggle_sz ( ) ) ; push_regs ( & live_regs_mask , current_function_interrupt ) ; stack_usage += d ; if ( flag_pic && ! TARGET_FDPIC && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) emit_insn ( gen_GOTaddr2picreg ( const0_rtx ) ) ; if ( target_flags != save_flags && ! current_function_interrupt ) emit_insn ( gen_toggle_sz ( ) ) ; target_flags = save_flags ; output_stack_adjust ( - rounded_frame_size ( d ) , stack_pointer_rtx , <NUM_LIT> , NULL , true ) ; stack_usage += rounded_frame_size ( d ) ; if ( frame_pointer_needed ) emit_frame_insn ( GEN_MOV ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( crtl -> profile || flag_exceptions || flag_unwind_tables ) emit_insn ( gen_blockage


<s> else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = arm_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args


<s> return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) , Node -> getValueType (


<s> static __inline long long sh_media_ADDZ_L ( unsigned int


<s> mips_pop_asm_switch ( & mips_noreorder ) ; } fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl


<s> emit_insn ( gen_rtx_SET ( new_base , gen_rtx_PLUS ( Pmode , base , new_base ) ) ) ; return new_base


<s> return ( __m64 ) __builtin_ia32_pavgb ( ( __v8qi ) __A , ( __v8qi )


<s> bool <ISA_LIT>TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) ->


<s> if ( ( V_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) ) return <NUM_LIT> ; if ( ( HILO_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return <NUM_LIT> ; if ( HILO_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) return <NUM_LIT> ; if ( ( HILO_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) || ( V_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return <NUM_LIT> ; return


<s> return ( __mmask8 ) __builtin_ia32_cmpss_mask ( ( __v4sf ) __X , ( __v4sf )


<s> virtual StringRef getPassName ( ) const override { return


<s> } else { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ,


<s> MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . OffsetBits ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( CondBrMBBOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; splitBlockBeforeInstr ( MBBI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) ) ; MI -> getOperand ( CondBrMBBOperand ) . setMBB ( NextBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; unsigned OffsetBits = <NUM_LIT>


<s> auto Ty = MRI . getType ( CompareReg ) ; unsigned Width = Ty . getSizeInBits ( ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; assert ( Width <= <NUM_LIT> && <STR_LIT> ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = {

{ <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;


<s> static __inline__ float __fsels ( float x , float y , float z ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) ,


<s> case <STR_LIT> : case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> NTOperator = is64BitFP ? <STR_LIT> : <STR_LIT> ; unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue OnesOrZeroesF = DAG . getNode ( NTOperator , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , <STR_LIT> ) ) ; SDValue OnesOrZeroesI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ANDed ) ; return OneBitOfTruth ; } } } } return SDValue (


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> if ( ! Subtarget -> hasSVE ( ) || DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT OpVT = N0 . getValueType ( ) ; if ( ! OpVT . isScalableVector ( ) || OpVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; if ( Idx . getOpcode ( ) != <STR_LIT> || ! isAllOnesConstant ( Idx . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue VS = Idx . getOperand ( <NUM_LIT> ) ; if ( VS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumEls = OpVT . getVectorElementCount ( ) . getKnownMinValue ( ) ; if ( VS . getConstantOperandVal ( <NUM_LIT> ) != NumEls ) return SDValue ( ) ; SelectionDAG & DAG = DCI .


<s> rtx op3 = expand_normal ( arg3 ) ; enum insn_code icode = d -> icode ; const struct insn_data_d * insn_p = & insn_data [ icode ] ; machine_mode mode0 = insn_p -> operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_p -> operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = UNEQ ; bool need_ucomi = false ; enum rtx_code comi_comparisons [ <NUM_LIT> ] = { UNEQ , GT , GE , UNORDERED , LTGT , UNLE , UNLT , ORDERED , UNEQ , UNLT , UNLE , LT , LTGT , GE , GT , LT , UNEQ , GT , GE , UNORDERED , LTGT , UNLE , UNLT , ORDERED , UNEQ , UNLT , UNLE , LT , LTGT , GE , GT , LT } ; bool need_ucomi_values [ <NUM_LIT> ] = { true , false , false , true , true , false , false , true , true , false , false , true , true , false , false , true , false , true , true , false , false , true , true , false , false , true , true , false , false , true , true , false } ; if ( ! CONST_INT_P ( op2 ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( INTVAL ( op2 ) < <NUM_LIT> || INTVAL ( op2 ) >= <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op3 , SImode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } comparison = comi_comparisons [ INTVAL ( op2 ) ] ; need_ucomi = need_ucomi_values [ INTVAL ( op2 ) ] ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( need_ucomi ) icode = icode == CODE_FOR_sse_comi_round ? CODE_FOR_sse_ucomi_round : CODE_FOR_sse2_ucomi_round ; pat = GEN_FCN ( icode ) ( op0 , op1 , op3 ) ; if ( ! pat ) return <NUM_LIT> ; if ( INTVAL ( op3 ) == NO_ROUND ) { pat = ix86_erase_embedded_rounding ( pat


<s> MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB


<s> unsigned <ISA_LIT>MachOTargetObjectFile :: getTTypeEncoding ( )


<s> rtx rperm [ MAX_VECT_LEN ] , x ; rtx_insn * insn ; unsigned i ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; insn = emit_insn ( x


<s> bool isCortexM7 ( ) const { return <ISA_LIT>ProcFamily == CortexM7


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ; int NumOp = MI . getNumExplicitOperands ( )


<s> Value * <ISA_LIT>IREmitter :: visitWrapperRIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue NOOP ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , VTs , Ops ) , <NUM_LIT> ) ; return NOOP


<s> unsigned Cmode = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Imm3 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Imm4 = Imm & <NUM_LIT> ; Binary |= ( I << <NUM_LIT> ) | ( Imm3 << <NUM_LIT> ) | ( Cmode << <NUM_LIT> ) | ( Op << <NUM_LIT> ) | Imm4 ; if ( IsThumb ) Binary = convertNEONDataProcToThumb ( Binary


<s> } unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; } else


<s> MachineInstr * LoadMI = nullptr ; switch ( MIRBuilder . getDataLayout ( ) . getTypeStoreSize ( CPVal -> getType ( ) ) ) { case <NUM_LIT> : LoadMI = & * MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Adrp } ) . addConstantPoolIndex ( CPIdx , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMI = & * MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Adrp } ) . addConstantPoolIndex ( CPIdx , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; break ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * CPVal -> getType ( ) ) ; return nullptr ; } constrainSelectedInstRegOperands ( * Adrp , TII


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , <STR_LIT> ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ; if ( Subtarget -> isTargetILP32 ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FrameAddr , DAG


<s> return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size ,

Alignment . value ( ) , RTLIB :: MEMMOVE ) ;


<s> MemRefBegin += <STR_LIT> ( Desc ) ; MachineOperand & BaseMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseMO . isReg ( ) ) return false ; BaseReg = BaseMO . getReg ( ) ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm (


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg

( SrcReg ) . addFrameIndex ( FI ) . addReg ( <STR_LIT> ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_store1_pd ( double *


<s> initReachingDef ( MF , ColorOpToReachedUses , Gen , Kill , ReachableUses , RegToId , DummyOp , ADRPMode ) ; if ( ! DummyOp ) reachingDefAlgorithm ( MF , ColorOpToReachedUses , In , Out , Gen , Kill ,


<s> getBDAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) ) ; return ( Base << <NUM_LIT>


<s> const MCOperand & RegMO = MI . getOperand ( OpIdx ) ; const MCOperand & ImmMO = MI . getOperand ( OpIdx + <NUM_LIT> ) ; assert ( ImmMO . getImm ( ) >= <NUM_LIT> ) ; Bits |= ( getMachineOpValue ( MI , RegMO , Fixups , STI ) << <NUM_LIT> ) ; Bits |= ( unsigned ) ImmMO . getImm ( ) & <NUM_LIT> ; return Bits


<s> if ( requiresRegisterScavenging ( MF ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } if ( LP64 ) { if ( requiresRegisterScavenging ( MF ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg


<s> static DecodeStatus DecodeRestrictedUPredicateOperand ( MCInst & Inst , unsigned Val , uint64_t


<s> SMLoc TypeLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * Val = nullptr ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return nullptr ; if ( ! Info . OpDecl ) return ErrorOperand ( Start , <STR_LIT> ) ; unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Length ; break ; case IOK_SIZE : CVal = Info . Size ; break ; case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> inline vector unsigned char vec_vmrghb ( vector unsigned char a1 , vector unsigned char a2 ) { return ( vector unsigned char ) __builtin_altivec_vmrghb ( ( vector signed char


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return MaterializeGV ( GV ,


<s> void function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ) { struct mips_arg_info info ; mips_arg_info ( cum , mode , type , named , & info ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < <NUM_LIT> && info . fpr_p ) cum -> fp_code += ( mode == SFmode ? <NUM_LIT> : <NUM_LIT> ) << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset +


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( AddressRegI64 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; switch ( AccessSize ) { case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction ::


<s> if ( isN64 ( ) ) return MachineJumpTableInfo ::


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) || isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; APInt C2Int = C2 -> getAPIntValue ( ) ; APInt C1Int = C1ShlC2 -> getAPIntValue ( ) ; APInt Mask = APInt :: getHighBitsSet ( C2Int . getBitWidth ( ) , C2Int . getBitWidth


<s> SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( )


<s> if ( ! ConstSplatVal && ! Ld -> hasNUsesOfValue ( VT . getVectorNumElements ( ) , <NUM_LIT> ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( VT . is256BitVector ( ) ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; if ( ! ConstSplatVal && ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) ) return SDValue ( ) ; break ; } } bool Is256 = VT . is256BitVector ( ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits ( ) ; if ( ScalarSize == <NUM_LIT> || ( Is256 &&


<s> return ( int16x4_t ) __builtin_neon_vqdmulh_lanev4hi (


<s> static void csky_output_constpool_label ( FILE * stream , rtx x ) { char buf [ <NUM_LIT> ] ; gcc_assert ( GET_CODE ( x


<s> rtx regs [ <NUM_LIT> ] ; i = <NUM_LIT> ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= <NUM_LIT> ) { rtx mem = gen_frame_mem ( BLKmode , regs [ i ]


<s> bool <ISA_LIT>AdvSIMDScalar :: isProfitableToTransform ( const MachineInstr & MI ) const { if ( ! isTransformable ( MI ) ) return false ; unsigned NumNewCopies = <NUM_LIT> ; unsigned NumRemovableCopies = <NUM_LIT> ; Register OrigSrc0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OrigSrc1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubReg0 ; unsigned SubReg1 ; if ( ! MRI -> def_empty ( OrigSrc0 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc0 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( MOSrc0 ) -- NumNewCopies ; if ( MOSrc0 && MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) ++ NumRemovableCopies ; } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( MOSrc1 ) -- NumNewCopies ; if ( MOSrc1 && MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) ++ NumRemovableCopies ; } Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool AllUsesAreCopies = true ; for ( MachineRegisterInfo :: use_instr_nodbg_iterator Use = MRI -> use_instr_nodbg_begin ( Dst ) , E = MRI -> use_instr_nodbg_end ( ) ; Use != E ; ++ Use ) { unsigned SubReg ; if ( getSrcFromCopy ( & * Use , MRI , SubReg ) || isTransformable


<s> case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case


<s> MVT ResVT = Op . getSimpleValueType ( ) ; assert ( ( In . getSimpleValueType ( ) . is256BitVector ( ) || In . getSimpleValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ; if ( ResVT . is128BitVector ( ) ) return extract128BitVector ( In , IdxVal , DAG


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup , Value , IsPCRel , Ctx , IsLittleEndian , true ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize &&


<s> FOR_EACH_INSN_USE ( use , insn ) { rtx x = DF_REF_REG ( use


<s> RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return false


<s> switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; I -> getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; I -> getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ; break ; } } if ( ! I -> isBundledWithSucc ( ) )


<s> bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , <NUM_LIT> , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return


<s> if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; return isTypeLegal ( VT . getSimpleVT (


<s> return ( __m128i ) __builtin_ia32_psignd128 ( ( __v4si ) __X ,


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return getDirectBrEncoding ( MI , OpNo , Fixups , STI


<s> else emit_insn ( gen_rtx_SET ( reg , vrsave ) ) ; int offset = info -> vrsave_save_offset + frame_off ; emit_insn ( gen_frame_store ( reg , frame_reg_rtx , offset ) ) ; emit_insn ( gen_iorsi3 ( reg , reg , GEN_INT ( info -> vrsave_mask ) ) ) ; emit_insn ( generate_set_vrsave ( reg , info ,


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { return Subtarget . hasVector ( ) ? <STR_LIT> :


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult .


<s> case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) . getSizeInBits ( ) ; ( void ) SrcSz ; assert ( SrcSz == Known . getBitWidth ( ) ) ; assert ( DstSz > SrcSz ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Known


<s> alias_set_type set ; next_cum = * get_cumulative_args ( cum ) ; rs6000_function_arg_advance_1 ( & next_cum , arg . mode , arg . type , arg . named , <NUM_LIT> ) ; if ( DEFAULT_ABI == ABI_V4 ) { first_reg_offset = next_cum . sysv_gregno - GP_ARG_MIN_REG ; if ( ! no_rtl ) { int gpr_reg_num = <NUM_LIT> , gpr_size = <NUM_LIT> , fpr_size = <NUM_LIT> ; HOST_WIDE_INT offset = <NUM_LIT> ; if ( cfun -> va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG ) gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset ; if ( TARGET_HARD_FLOAT && next_cum . fregno <= FP_ARG_V4_MAX_REG && cfun -> va_list_fpr_size ) { if ( gpr_reg_num ) fpr_size = ( next_cum . fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD ; if ( cfun -> va_list_fpr_size < FP_ARG_V4_MAX_REG + <NUM_LIT> - next_cum . fregno ) fpr_size += cfun -> va_list_fpr_size * UNITS_PER_FP_WORD ; else fpr_size += ( FP_ARG_V4_MAX_REG + <NUM_LIT> - next_cum . fregno ) * UNITS_PER_FP_WORD ; } if ( gpr_reg_num ) { offset = - ( ( first_reg_offset * reg_size ) & ~ <NUM_LIT> ) ; if ( ! fpr_size && gpr_reg_num > cfun -> va_list_gpr_size ) { gpr_reg_num = cfun -> va_list_gpr_size ; if ( reg_size == <NUM_LIT> && ( first_reg_offset & <NUM_LIT> ) ) gpr_reg_num ++ ; } gpr_size = ( gpr_reg_num * reg_size + <NUM_LIT> ) & ~ <NUM_LIT> ; } else if ( fpr_size ) offset = - ( int ) ( next_cum . fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD - ( int ) ( GP_ARG_NUM_REG * reg_size ) ; if ( gpr_size + fpr_size ) { rtx reg_save_area = assign_stack_local ( BLKmode , gpr_size + fpr_size , <NUM_LIT> ) ; gcc_assert ( MEM_P ( reg_save_area ) ) ; reg_save_area = XEXP ( reg_save_area , <NUM_LIT> ) ; if ( GET_CODE ( reg_save_area ) == PLUS ) { gcc_assert ( XEXP ( reg_save_area , <NUM_LIT> ) == virtual_stack_vars_rtx ) ; gcc_assert ( CONST_INT_P ( XEXP ( reg_save_area , <NUM_LIT> ) ) ) ; offset += INTVAL ( XEXP ( reg_save_area , <NUM_LIT> ) ) ; } else gcc_assert ( reg_save_area == virtual_stack_vars_rtx ) ; } cfun -> machine -> varargs_save_offset


<s> case Triple :: COFF : return LowerGlobalAddressWindows ( Op , DAG ) ; case Triple :: ELF : return LowerGlobalAddressELF ( Op , DAG ) ; case Triple :: MachO : return LowerGlobalAddressDarwin ( Op , DAG ) ; } case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const llvm :: MCInstrInfo & MCII ,

const llvm :: MCRegisterInfo & MRI , llvm :: MCContext & Ctx ) {


<s> if ( cum -> nregs < NUM_ARG_REGS ) * pretend_size = ( NUM_ARG_REGS - cum


<s> void addHI32DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getHI32DSPReg ( ) )


<s> else if ( MO . isCPI ( ) ) emitConstPoolAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , getRelocation ( MI , MO ) ) ; else llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> __vector unsigned int c , d ; static const __vector unsigned int float_exp_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf )


<s> if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( DEFAULT_ABI == ABI_V4 ) { cum -> escapes = call_ABI_of_interest ( fndecl ) ; if ( cum -> escapes ) { tree return_type ; if ( fntype ) { return_type = TREE_TYPE ( fntype ) ; return_mode = TYPE_MODE ( return_type ) ; } else return_type = lang_hooks . types . type_for_mode ( return_mode , <NUM_LIT> ) ; if ( return_type != NULL ) { if ( TREE_CODE ( return_type ) == RECORD_TYPE && TYPE_TRANSPARENT_AGGR ( return_type ) ) { return_type = TREE_TYPE ( first_field ( return_type ) ) ; return_mode = TYPE_MODE ( return_type ) ; } if ( AGGREGATE_TYPE_P ( return_type ) && ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( return_type

) <= <NUM_LIT> ) ) rs6000_returns_struct = true ;


<s> Register regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent (


<s> BuildMI ( headMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackProbed ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( headMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( footMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; headMBB -> addSuccessor ( bodyMBB ) ; headMBB -> addSuccessor ( footMBB ) ; } { addRegOffset ( BuildMI ( bodyMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; const unsigned SUBOpc = getSUBriOpcode ( Uses64BitFramePtr , StackProbeSize ) ; BuildMI ( bodyMBB , DL , TII . get ( SUBOpc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( bodyMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackProbed ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( bodyMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( bodyMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; bodyMBB -> addSuccessor ( bodyMBB ) ; bodyMBB -> addSuccessor ( footMBB ) ; } { BuildMI ( footMBB , DL , TII . get ( TargetOpcode :: COPY ) , StackPtr ) . addReg ( FinalStackProbed ) . setMIFlag ( MachineInstr :: FrameSetup ) ; addRegOffset ( BuildMI ( footMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; footMBB -> addSuccessor ( & MBB ) ; } recomputeLiveIns ( * headMBB ) ; recomputeLiveIns ( * bodyMBB ) ; recomputeLiveIns ( * footMBB


<s> Inst . addOperand ( MCOperand :: CreateReg ( VectorList . RegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , <NUM_LIT> ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op

) , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ;


<s> for ( auto & MI : BB ) { TrapInfo TI = MI . getTrapInfo ( ) ; if ( ! TI . isUnknown ( ) ) { uint64_t MaxNumVFuncs = TI . getMaxNumVFuncs ( ) ; assert ( MaxNumVFuncs <= ( <NUM_LIT> << <NUM_LIT> ) / TrampSize && <STR_LIT> ) ; if ( MaxNumVFuncs > ( <NUM_LIT> << <NUM_LIT> ) / TrampSize ) { DEBUG ( dbgs ( ) << MaxNumVFuncs


<s> bool <ISA_LIT>ShortenInst :: shortenOn001AddCC ( MachineInstr & MI , unsigned Opcode , bool CCLive ) { if ( ! CCLive && shortenOn001 ( MI , Opcode ) ) { MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return


<s> MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; MachineBasicBlock :: instr_iterator LI = LastITMI ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , std :: next ( LI ) ) ; Modified = true ; ++ NumITs ; } return


<s> return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <NUM_LIT> , false , false

, MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , const TargetOptions & Options ) { return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm < TrueImm ) ; if ( HeadCmp == <STR_LIT> ) { adjustHeadCond = ! adjustHeadCond ; } if ( adjustHeadCond ) { Changed |= adjustTo ( HeadCmpMI , HeadCmp , TrueCmpMI , TrueImm ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; if ( VT . isVector ( ) ) return LowerVSETCC ( Op , Subtarget , DAG ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode


<s> return ( long long ) __builtin_ia32_vcvttss2si64 ( ( __v4sf )


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , ResTy ) ; SDValue Bit = DAG . getNode ( <STR_LIT> , DL , ResTy , One , Op -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , Op -> getOperand ( <NUM_LIT> ) ,


<s> if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , VT , Ext ) ; } return


<s> void <ISA_LIT>InstPrinter :: printPImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand (


<s> if ( SetFlags ) RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; else RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ; RHSReg = constrainOperandRegClass ( II , RHSReg , II . getNumDefs ( ) + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( LHSReg ) . addReg ( RHSReg ) . addImm ( getArithExtendImm ( ExtType , ShiftImm ) ) ; return


<s> SDLoc dl ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue MLAOp1 ; SDValue MLAOp2 ; int LaneIdx = - <NUM_LIT> ; if ( Op1 . getOpcode ( ) != <STR_LIT> || ! checkV64LaneV128 ( Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) , MLAOp1 , MLAOp2 , LaneIdx ) ) { std :: swap ( Op0 , Op1 ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || ! checkV64LaneV128 ( Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) , MLAOp1 , MLAOp2 , LaneIdx ) ) return nullptr ; } SDValue LaneIdxVal = CurDAG -> getTargetConstant ( LaneIdx , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Op0 , MLAOp1 , MLAOp2 , LaneIdxVal } ; unsigned MLAOpc = ~ <NUM_LIT> ; switch ( N -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : MLAOpc = <STR_LIT> ; break ; case <STR_LIT> : MLAOpc = <STR_LIT> ; break ; case <STR_LIT>


<s> return TargetABI == <ISA_LIT>_ABI_ELFv2


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL


<s> bool <ISA_LIT>AsmBackend :: canPadBranches ( MCObjectStreamer & OS ) const { if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; if ( ! OS . getCurrentSectionOnly ( ) -> getKind ( ) . isText ( ) ) return false ; if ( OS . getAssembler ( ) . isBundlingEnabled


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const TargetMachine & TM = FuncInfo . MF -> getTarget (


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy


<s> if ( SV == <NUM_LIT> ) { SV = extractBitsFromValue ( SF , <NUM_LIT> , getReg ( <STR_LIT>


short __q4 , short __q5 , short __q6 , short __q7 ) {


<s> if ( GET_CODE ( src ) == CONST || GET_CODE ( src ) == MEM ) src = XEXP ( src , <NUM_LIT> ) ; else if ( GET_CODE ( src ) == SYMBOL_REF || GET_CODE ( src ) == LABEL_REF || GET_CODE ( src ) == PLUS ) break ; else return false


<s> static const __vector unsigned int __float_exp_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; __b = ( __vector unsigned int ) vec_abs ( (


<s> bool NeedsWinCFI = IsWin64Prologue && MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t MaxAlign = calculateMaxStackAlign ( MF ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( isFuncletReturnInstr ( MBBI ) ) { NumBytes = MFI -> getMaxCallFrameSize ( ) ; if ( Is64Bit ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) ; } } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) { if ( TRI -> needsStackRealignment ( MF )


<s> bool mergeStoresAfterLegalization ( )


<s> rtx x = * iter ; if ( MEM_P ( x ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( x


<s> unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , true , false , false , Reg0IsDead ) . addReg ( Reg2 , false , false , Reg2IsKill ) . addReg ( Reg1 , false , false , Reg1IsKill ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) .


Mask , Subtarget , DAG ) ) return Result ;


<s> if ( ! KillsSrc && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , ScratchFPReg


<s> if ( Opcode == TargetOpcode :: COPY_TO_REGCLASS ) return ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<= <NUM_LIT> ; } ++ MCNumEmitted


<s> for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * Anon = MCSymbolRefExpr :: Create ( AnonSymbol , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: Create ( LazyPtr , OutContext ) ; const MCExpr * Sub = MCBinaryExpr :: CreateSub ( LazyPtrExpr , Anon , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( Anon ) ) ; OutStreamer . EmitLabel ( AnonSymbol ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubHa16 = <ISA_LIT>MCExpr :: CreateHa ( Sub , isDarwin , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubHa16 ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubLo16 = <ISA_LIT>MCExpr :: CreateLo ( Sub , isDarwin , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubLo16 ) . addExpr ( SubLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; MCSymbol * DyldStubBindingHelper = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) { ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; DebugLoc dl = CP -> getDebugLoc ( ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , getPointerTy ( ) , CP -> getAlignment ( ) ) ; Result = DAG . getNode ( <STR_LIT> , dl ,


<s> static MachineInstr * getDef ( unsigned Reg


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; Register Reg = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( DstOpcode ) , <NUM_LIT> , MRI -> getTargetRegisterInfo ( ) , * MBB -> getParent ( ) ) ) ; MachineInstrBuilder Bld = BuildMI ( * MBB , MI , DL , TII -> get ( DstOpcode ) , Reg ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) ) ) Bld . add ( MO ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) ) . add ( MI -> getOperand


<s> Parser . Lex ( ) ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Real ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } APFloat RealVal ( APFloat :: IEEEdouble , Parser . getTok ( ) . getString ( ) ) ; if ( Negative ) RealVal . changeSign ( ) ; double DblVal = RealVal . convertToDouble ( ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( DblVal , S


<s> return isImm ( ) && dyn_cast < MCConstantExpr > ( getImm (


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>32 ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT>


( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> __builtin_ia32_storedquhi128_mask ( ( __v8hi * ) __P , ( __v8hi )


<s> if ( ! TARGET_SSE2 ) { gcc_checking_assert ( ! float16_type_node && ! bfloat16_type_node ) ; float16_type_node = ix86_float16_type_node ; bfloat16_type_node = ix86_bf16_type_node ; callback ( float16_type_node


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return <ISA_LIT>BaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugInstr ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( )


<s> static bool isFixupKindRIPRel ( unsigned Kind ) { return Kind == <STR_LIT> || Kind ==


<s> if ( useSVEForFixedLengthVectorVT ( OpVT ) ) return LowerFixedLengthBitcastToSVE ( Op , DAG ) ; if ( OpVT . isScalableVector ( ) ) { if ( isTypeLegal ( OpVT ) && ! isTypeLegal ( ArgVT ) ) { assert ( OpVT . isFloatingPoint ( ) && ! ArgVT . isFloatingPoint ( ) && <STR_LIT> ) ; SDValue ExtResult = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getSVEContainerType ( ArgVT ) , Op . getOperand ( <NUM_LIT> ) ) ; return getSVESafeBitCast ( OpVT , ExtResult , DAG ) ; } return getSVESafeBitCast ( OpVT , Op . getOperand ( <NUM_LIT> ) , DAG ) ; } if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) return Op ; assert ( ArgVT == <STR_LIT> ) ; SDLoc DL ( Op )


<s> int regno ; regno = true_regnum ( x ) ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < <NUM_LIT> || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) ) return NO_REGS ; if ( FP_REG_P ( regno ) && loongarch_mode_ok_for_mov_fmt_p ( mode ) ) return NO_REGS ; return GR_REGS


<s> vmvn_p8 ( poly8x8_t a ) { poly8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> const struct machine_function * m = cfun -> machine ; unsigned last_reg = m -> call_ms2sysv_extra_regs + MIN_REGS - <NUM_LIT> ; gcc_assert ( m -> call_ms2sysv_extra_regs <= MAX_EXTRA_REGS ) ; return m_regs [ last_reg ] .


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( *


<s> return ( float64x1_t ) { __builtin_aarch64_ucvtfdi_sus ( vget_lane_u64 ( __a , <NUM_LIT> ) ,


<s> for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) { store_reg ( i , offset , HARD_FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } gr_saved ++ ; } else { offset = local_fsize - actual_fsize ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , regno , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( regno , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) { if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , i , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } if ( merge_sp_adjust_with_store ) set_reg_plus_d ( STACK_POINTER_REGNUM , STACK_POINTER_REGNUM , actual_fsize , <NUM_LIT> ) ; } if ( flag_pic && actual_fsize != <NUM_LIT> && ! TARGET_64BIT ) { rtx addr = gen_rtx_PLUS ( word_mode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( word_mode , addr ) , pic_offset_table_rtx ) ; } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { rtx base ; if ( frame_pointer_needed ) { set_reg_plus_d ( <NUM_LIT> , HARD_FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; base =


<s> if ( Opcode == <STR_LIT> ) { if ( Val -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; CanNegate = true ; MustBeFirst = false ; return true ; } if ( Depth > <NUM_LIT> ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { bool IsOR = Opcode == <STR_LIT> ; SDValue O0 = Val -> getOperand ( <NUM_LIT> ) ; SDValue O1 = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateL ; bool MustBeFirstL ; if ( ! canEmitConjunction ( O0 , CanNegateL , MustBeFirstL , IsOR , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; bool MustBeFirstR ; if ( ! canEmitConjunction ( O1 , CanNegateR , MustBeFirstR , IsOR , Depth + <NUM_LIT> ) ) return false ; if ( MustBeFirstL && MustBeFirstR


<s> bool <ISA_LIT>GOT :: isGOTFull ( ) const { uint64_t gotCount = <ISA_LIT>GOT0Num + m_MultipartList . back ( ) . m_LocalNum + m_MultipartList .


<s> if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str


<s> x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4HFmode : gen = gen_aarch64_trn2v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn2v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn2v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn1v16qi ; break ; case V8QImode : gen = gen_aarch64_trn1v8qi ; break ; case V8HImode : gen = gen_aarch64_trn1v8hi ; break ; case V4HImode : gen = gen_aarch64_trn1v4hi ; break ; case V4SImode : gen = gen_aarch64_trn1v4si ; break ; case V2SImode : gen = gen_aarch64_trn1v2si ; break ; case V2DImode : gen = gen_aarch64_trn1v2di ; break ; case V4HFmode : gen = gen_aarch64_trn1v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn1v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn1v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn1v2sf ;


<s> break ; } ; if ( SetCC0 . getOpcode ( ) != <STR_LIT> || SetCC1 . getOpcode ( ) != <STR_LIT> || SetCC0 -> getOperand ( <NUM_LIT> ) != SetCC1 -> getOperand ( <NUM_LIT> ) ) return false ; CC0 = ( <STR_LIT> ) SetCC0 -> getConstantOperandVal ( <NUM_LIT> ) ; CC1 = ( <STR_LIT> ) SetCC1 -> getConstantOperandVal ( <NUM_LIT> ) ; Flags = SetCC0 -> getOperand ( <NUM_LIT> ) ; return true


<s> const isr_attribute_entry * ptr ; const char * arg ; if ( argument == NULL_TREE ) return CSKY_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return CSKY_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_map ; ptr -> arg != NULL ; ptr ++ ) if ( strcmp

( arg , ptr -> arg ) == <NUM_LIT> ) return ptr -> return_value ;


<s> if ( ! DestIsHigh && ! SrcIsHigh ) MI . setDesc ( get ( LowOpcode ) ) ; else if ( DestIsHigh && SrcIsHigh ) MI . setDesc ( get ( HighOpcode ) ) ; else LOCRMuxJumps ++


<s> insn -> writemask = aaaFromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimmInvPow2 ( SDValue N , SDValue


<s> if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( )

) ) UseNEONForSinglePrecisionFP = true ;


<s> return ( TT . getArch ( ) == Triple :: ppc64 || TT


<s> __vector unsigned int t ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_10 ] ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_32 ] ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_54 ] + <NUM_LIT> ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_76 ] + <NUM_LIT> ; return vec_perm ( ( __v4sf ) __A , ( __v4sf ) __B ,


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getLoad ( ResTy , DL , ChainIn

, Address , MachinePointerInfo ( ) , <NUM_LIT> ) ;


<s> size_type edges_size ( ) const { return EdgesSize


<s> if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) emit_window_save ( size_int_rtx ) ; else if ( size <= <NUM_LIT> ) { emit_window_save ( GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS


<s> void <ISA_LIT>InstPrinter :: printAddrModeTBB ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand (


<s> } ; auto extractHalf = [ ] ( Value * FullV , Value * HalfV ) { auto * FullVT = cast < VectorType > ( FullV -> getType ( ) ) ; auto * HalfVT = cast < VectorType > ( HalfV -> getType ( ) ) ; return FullVT -> getNumElements ( ) == <NUM_LIT> * HalfVT -> getNumElements ( ) ; } ; ArrayRef < int > M1 , M2 ; Value * S1Op1 , * S2Op1 ; if ( ! match ( Op1 , m_Shuffle ( m_Value ( S1Op1 ) , m_Undef ( ) , m_Mask ( M1 ) ) ) || ! match ( Op2 , m_Shuffle ( m_Value ( S2Op1 ) , m_Undef ( ) , m_Mask ( M2 ) ) ) ) return false ; if ( ! areTypesHalfed ( S1Op1 , Op1 ) || ! areTypesHalfed ( S2Op1 , Op2 ) || ! extractHalf ( S1Op1 , Op1 ) || ! extractHalf ( S2Op1 , Op2 ) ) return false ; int M1Start = - <NUM_LIT> ; int M2Start = - <NUM_LIT> ; int NumElements = cast < VectorType > ( Op1 -> getType ( ) ) -> getNumElements ( ) * <NUM_LIT> ; if ( ! ShuffleVectorInst :: isExtractSubvectorMask ( M1 , NumElements , M1Start ) || ! ShuffleVectorInst :: isExtractSubvectorMask ( M2 , NumElements , M2Start ) || M1Start != M2Start || ( M1Start != <NUM_LIT> && M2Start != ( NumElements / <NUM_LIT> ) ) ) return false ; return true


<s> static bool hasPairwiseAdd ( unsigned Opcode , EVT VT , bool FullFP16 ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( FullFP16 && VT == <STR_LIT> ) || VT ==


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzmsk_u64 ( unsigned long long __X ) { return ~ __X & ( __X -


<s> void <ISA_LIT>BaseInstrInfo :: saveLROnStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; int Align = - Subtarget . getStackAlignment ( ) . value ( ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill )

. addReg ( <STR_LIT> ) . addImm ( Align ) . add ( predOps ( <STR_LIT> ) ) ;


<s> __builtin_sh_media_STHI_L ( ( char * ) p + s


<s> auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( & MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint (


<s> return ( __m256i ) __builtin_ia32_permti256 ( ( __v4di ) __X , (


<s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; } return


<s> if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , Opcode ) ) return false ; MachineInstr * BuiltMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( Opcode ) ) ; for ( const auto & MO : MI . operands ( ) ) BuiltMI -> addOperand ( MO ) ; BuiltMI -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; MI . eraseFromParent


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false


, Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> static bool isHorizontalBinOp ( SDValue & LHS , SDValue & RHS , bool IsCommutative ) { if ( LHS . getOpcode ( ) != <STR_LIT> && RHS . getOpcode ( ) != <STR_LIT> ) return false ; MVT VT = LHS . getSimpleValueType ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; assert ( ( NumLaneElts % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned HalfLaneElts = NumLaneElts / <NUM_LIT> ; SDValue A , B ; SmallVector < int , <NUM_LIT> > LMask ( NumElts ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { if ( LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) A = LHS . getOperand ( <NUM_LIT> ) ; if ( LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) B = LHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( LHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , LMask . begin ( ) ) ; } else { if ( LHS . getOpcode ( ) != <STR_LIT> ) A = LHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) LMask [ i ] = i ; } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( )


<s> Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> RegIdx . Tok . Data = Str . data ( ) ; Op -> RegIdx . Tok . Length = Str . size (


<s> NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT>


<s> break ; } case CONST_DOUBLE : { if ( GET_MODE ( op ) != mode ) return false ; if ( mode == SFmode ) { mode = DFmode ; size = GET_MODE_SIZE ( DFmode ) ; } constant_fp_to_128bit_vector ( op , mode , <NUM_LIT> , info ) ; splat_p = true ; break ; } case CONST_VECTOR : { if ( GET_MODE ( op ) != mode || GET_MODE_SIZE ( mode ) != VECTOR_128BIT_BYTES ) return false ; machine_mode ele_mode = GET_MODE_INNER ( mode ) ; size_t ele_size = GET_MODE_SIZE ( ele_mode ) ; size_t nunits = GET_MODE_NUNITS ( mode ) ; for ( size_t num = <NUM_LIT> ; num < nunits ; num ++ ) { rtx ele = CONST_VECTOR_ELT ( op , num ) ; size_t byte_num = ( BYTES_BIG_ENDIAN ? num : nunits - <NUM_LIT> - num ) * ele_size ; if ( CONST_INT_P ( ele ) ) constant_int_to_128bit_vector ( ele , ele_mode , byte_num , info ) ; else if ( CONST_DOUBLE_P ( ele ) ) constant_fp_to_128bit_vector ( ele , ele_mode , byte_num , info ) ; else return false ; } break ; } case VEC_DUPLICATE : { if ( GET_MODE ( op ) != mode || GET_MODE_SIZE ( mode ) != VECTOR_128BIT_BYTES ) return false ; machine_mode ele_mode = GET_MODE_INNER ( mode ) ; size_t ele_size = GET_MODE_SIZE ( ele_mode ) ; rtx ele = XEXP ( op , <NUM_LIT> ) ; size_t nunits = GET_MODE_NUNITS ( mode ) ; if ( ! CONST_INT_P ( ele ) && ! CONST_DOUBLE_P ( ele ) ) return false ; for ( size_t num = <NUM_LIT> ; num < nunits ; num ++ ) { size_t byte_num = num * ele_size ; if ( CONST_INT_P ( ele ) ) constant_int_to_128bit_vector ( ele , ele_mode , byte_num , info ) ; else constant_fp_to_128bit_vector ( ele , ele_mode , byte_num , info ) ; } break ; } default : return false ; } if ( splat_p && size < VECTOR_128BIT_BYTES ) { if ( ( VECTOR_128BIT_BYTES % size ) != <NUM_LIT> ) return false ; for ( size_t offset = size ; offset < VECTOR_128BIT_BYTES ; offset += size ) memcpy ( ( void * ) & info -> bytes [ offset ] , ( void * ) & info -> bytes [ <NUM_LIT> ] , size ) ; } info -> original_size = size ; unsigned char first_byte = info -> bytes [ <NUM_LIT> ] ; info -> all_bytes_same = true ; for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_BYTES ; i ++ ) if ( first_byte != info -> bytes [ i ] ) { info -> all_bytes_same = false ; break ; } for ( size_t i = <NUM_LIT> ; i < VECTOR_128BIT_HALF_WORDS ; i ++ ) info -> half_words [ i ] = ( ( info -> bytes [ i * <NUM_LIT> ] << <NUM_LIT> ) | info -> bytes [ (


<s> bool FourReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; NumOpsAdded = FourReg ? <NUM_LIT> : <NUM_LIT> ; return true


<s> PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment =


<s> if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg


<s> MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain , NegSize ,


<s> void initPICLabelUId ( unsigned UId ) { PICLabelUId =


<s> static void vax_init_libfuncs ( void ) { set_optab_libfunc ( udiv_optab , SImode , TARGET_ELF


<s> SDValue LowOp = Ops [ Low ] ; SDValue HighOp = Ops [ High ] ; if ( HighOp . getOpcode ( ) == <STR_LIT> ) return Op ; if ( LowOp . getOpcode ( ) == <STR_LIT> ) { int64_t Value = int32_t ( cast < ConstantSDNode > ( LowOp ) -> getZExtValue ( ) ) ; if ( ! isInt < <NUM_LIT> > ( Value ) ) return Op ; } if ( HighOp . getOpcode ( ) == <STR_LIT> && HighOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue HighOp0 = HighOp . getOperand ( <NUM_LIT> ) ; uint64_t Mask = cast < ConstantSDNode > ( HighOp . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( DAG . MaskedValueIsZero ( HighOp0 , APInt ( <NUM_LIT> , ~ ( Mask | <NUM_LIT> ) )


<s> if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return SDValue ( ) ; SDValue ShiftRight = N -> getOperand ( <NUM_LIT> ) , Mask = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftRightOpc = ShiftRight . getOpcode ( ) ; if ( ShiftRightOpc != <STR_LIT> && ShiftRightOpc != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * CN ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( ShiftRight . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( )


<s> return parseAddress ( Operands , BDMem , <STR_LIT> ,


<s> setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; setAction ( { G_ICMP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s8 } , { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 , s8 ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR , G_SDIV } ) . legalFor ( { s8 , s16 , s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 , s64 ) ; setAction ( { G_MERGE_VALUES , s128 } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , s128


<s> assert ( HaveMask ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N .


<s> bool <ISA_LIT>ShortenInst :: shortenSelect ( MachineInstr & MI , unsigned Opcode ) { if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MI . setDesc ( TII -> get ( Opcode ) ) ; MI . tieOperands ( <NUM_LIT> ,


<s> if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> && V . getNumOperands ( ) == <NUM_LIT> && V . getOperand ( <NUM_LIT> ) .

getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ;


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) )


<s> SDLoc DL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; MVT VT = LHS . getSimpleValueType ( ) ; unsigned GenericOpc = <STR_LIT> == N -> getOpcode ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = DAG . getNode ( GenericOpc , DL , VT , LHS , RHS ) ; return DAG . getMergeValues ( { Res , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } , DL ) ; } auto MatchGeneric = [ & ] ( SDValue N0 , SDValue N1 , bool Negate ) { SDValue Ops [ ] = { N0 , N1 } ; SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) ) ; if ( SDNode * GenericAddSub = DAG . getNodeIfExists ( GenericOpc , VTs , Ops ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( Negate ) Op = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op ) ; DCI . CombineTo (


<s> void pa_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { <STR_LIT> , pa_d_handle_target_float_abi } , { <STR_LIT> , pa_d_handle_target_object_format }


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_cvtepi64_storeu_epi16 ( void *


<s> BlockISELList thisBlockISELs ; for ( MachineInstr & MI : MBB ) if ( isISEL ( MI ) ) thisBlockISELs . push_back ( & MI ) ; if ( ! thisBlockISELs . empty ( ) ) ISELInstructions . insert ( std :: make_pair ( MBB . getNumber (


<s> bool PadShortFunc :: cyclesUntilReturn ( MachineBasicBlock * MBB , unsigned int & Cycles ) { DenseMap < MachineBasicBlock * , VisitedBBInfo > :: iterator it = VisitedBBs . find ( MBB ) ; if ( it != VisitedBBs . end ( ) ) { VisitedBBInfo BBInfo = it -> second ; Cycles += BBInfo . Cycles ; return BBInfo . HasReturn ; } unsigned int CyclesToEnd = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MBBI != MBB -> end ( ) ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isReturn ( ) && ! MI -> isCall ( ) ) { VisitedBBs [ MBB ] = VisitedBBInfo ( true , CyclesToEnd ) ; Cycles +=


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO

. getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( GA ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , TF ) ; if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol

( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ;