<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( SmallVectorImpl < std :: pair < unsigned , SMLoc > > :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++ I ) Op -> Registers . push_back ( I -> first ) ; array_pod_sort ( Op -> Registers . begin ( ) , Op -> Registers . end ( ) ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2v8qi ( ( __builtin_aarch64_simd_qi *


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; WinEHEncodingType = WinEH :: EncodingType :: Itanium


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL


<s> if ( <STR_LIT> . contains ( SrcReg ) ) { assert ( Subtarget . hasBWI ( ) ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( SrcReg ) ) return Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> .


<s> static bool ia64_legitimate_address_reg ( const_rtx reg , bool strict ) { if ( ( REG_P ( reg ) && ia64_reg_ok_for_base_p ( reg , strict ) ) || ( GET_CODE ( reg ) == SUBREG && REG_P ( XEXP ( reg , <NUM_LIT> ) ) && ia64_reg_ok_for_base_p ( XEXP ( reg , <NUM_LIT> ) ,


<s> } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { MachineInstr * Cmp ; CmpInst :: Predicate Pred ; std :: tie ( Cmp , Pred ) = emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; if ( ! Cmp ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; unsigned CmpOpc = selectFCMPOpc ( * CondDef , MRI ) ; if ( ! CmpOpc ) return false ; auto Cmp = MIB . buildInstr ( CmpOpc , { } , { CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) Cmp . addUse ( CondDef -> getOperand ( <NUM_LIT> ) . getReg


<s> static inline bool hasLEAOffset ( const MachineOperand & Offset ) { return ( Offset . isImm ( ) && Offset . getImm (

) != <NUM_LIT> ) || Offset . isGlobal ( ) ;


<s> EVT NarrowVT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> || NarrowVT != <STR_LIT> ) return false ; uint64_t ShiftImm ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShiftImm ) ) return false ; SDLoc dl ( N


<s> static bool useVPTERNLOG ( const <ISA_LIT>Subtarget & Subtarget , MVT VT


] || profile_flag || interrupt_handler ) ;


<s> int direct_return ( void ) { return ( reload_completed && xstormy16_compute_stack_layout ( ) . frame_size == <NUM_LIT> && !


<s> static bool arm_memory_load_p ( rtx insn ) { rtx body , lhs , rhs ; ; if ( insn == NULL_RTX || GET_CODE ( insn ) != INSN ) return false ; body = PATTERN ( insn


<s> std :: unique_ptr < CSEConfigBase > <ISA_LIT>PassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM ->


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixLoadStoreExclusive ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI


<s> if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , PtrVT , true ) , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { SDValue SpillSlot = DAG . CreateStackTemporary ( VA . getValVT ( ) ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; ArgValue = SpillSlot ; } else ArgValue = convertValVTToLocVT ( DAG , DL , VA , ArgValue ) ; if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; unsigned Offset = <STR_LIT> + VA . getLocMemOffset ( ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( Offset ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue Glue ; if ( auto * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , PtrVT ) ; Callee = DAG . getNode ( <STR_LIT> , DL , PtrVT , Callee ) ; } else if ( auto * E = dyn_cast < ExternalSymbolSDNode > (


<s> if ( file_format -> hasGOT ( ) && ( & pSectHdr == & file_format -> getGOT ( ) ) ) return SHO_DATA ; if ( file_format -> hasGOTPLT ( ) && ( & pSectHdr == & file_format -> getGOTPLT ( ) ) ) return SHO_DATA ; if ( file_format -> hasPLT ( ) && ( & pSectHdr == & file_format


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , bool little , const <ISA_LIT>TargetMachine & _TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , IsLittle ( little ) , TM ( _TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies ( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( *

this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) {


<s> case CONST_INT : return INTVAL ( op ) == <NUM_LIT> ; case REG : case


<s> void setArgumentStackSize ( unsigned size ) { ArgumentStackSize =


<s> unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> ) { assert ( TM . getInstrInfo ( ) && <STR_LIT> ) ; return new <ISA_LIT>HazardRecognizer970 ( TM


<s> } else if ( Subtarget -> isThumb2 ( ) ) { if ( <STR_LIT> ( CVal ) != - <NUM_LIT> ) break ; } else { if ( <STR_LIT> ( CVal ) != - <NUM_LIT> ) break ; } return ; case 'J' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= - <NUM_LIT> && CVal <= - <NUM_LIT> ) break ; } else { if ( CVal >= - <NUM_LIT> && CVal <= <NUM_LIT> ) break ; } return ; case 'K' : if ( Subtarget -> isThumb1Only ( ) ) { if ( CVal != <NUM_LIT> && <STR_LIT> ( CVal ) ) break ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( <STR_LIT> ( ~ CVal ) != - <NUM_LIT> ) break ; } else { if ( <STR_LIT> ( ~ CVal ) != - <NUM_LIT> ) break ; } return ; case 'L' : if ( Subtarget -> isThumb1Only ( ) ) { if ( CVal >= - <NUM_LIT> && CVal < <NUM_LIT> ) break ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( <STR_LIT> ( - CVal ) != - <NUM_LIT> ) break ; } else { if ( <STR_LIT> ( - CVal ) != - <NUM_LIT> ) break ; } return ; case 'M' : if ( Subtarget -> isThumb ( ) ) { if ( ( CVal >= <NUM_LIT> && CVal <= <NUM_LIT> ) && ( ( CVal & <NUM_LIT> ) == <NUM_LIT> ) ) break ; } else { if ( ( CVal >= <NUM_LIT> && CVal <= <NUM_LIT> ) || ( ( CVal & ( CVal - <NUM_LIT> ) ) == <NUM_LIT> ) ) break ; } return ; case 'N' : if ( Subtarget -> isThumb ( ) ) { if ( CVal >= <NUM_LIT> && CVal <= <NUM_LIT> ) break ; } return ; case 'O' : if ( Subtarget -> isThumb ( ) ) { if ( ( CVal >= - <NUM_LIT> && CVal <= <NUM_LIT> ) && ( ( CVal & <NUM_LIT> ) == <NUM_LIT> ) ) break ; } return ; } Result = DAG . getTargetConstant ( CVal , Op . getValueType ( ) ) ; break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result )


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( auto & OrigArg : OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , CallConv , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , OrigArg . Reg , Offset ) ; } ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) SplitArgs . back ( ) . Flags . setZExt ( ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv

( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ;


<s> FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset (


<s> for ( i = half_elts , j = <NUM_LIT> ; j < half_elts ; ++ i , ++ j ) XVECEXP ( par , <NUM_LIT> , i ) = GEN_INT ( j ) ; rtx sel = gen_rtx_VEC_SELECT ( mode , src_reg , par ) ; SET_SRC ( body ) = sel ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan (


<s> if ( ! isITCondCode ( ) ) return false ; <STR_LIT> CC = getCondCode ( ) ; return CC == <STR_LIT> || CC


<s> bool <ISA_LIT>ExpandISEL :: isExpandISELEnabled ( const MachineFunction & MF ) { return ! GenerateISEL || ! MF . getSubtarget <

<ISA_LIT>Subtarget > ( ) . hasISEL ( ) ;


<s> void <ISA_LIT>AddressSanitizer :: InstrumentMOVSBase ( unsigned DstReg , unsigned SrcReg , unsigned CntReg , unsigned AccessSize , MCContext & Ctx , MCStreamer & Out ) { RegisterContext RegCtx ( <STR_LIT> , <STR_LIT> , IsSmallMemAccess ( AccessSize ) ? <STR_LIT> : <STR_LIT> ) ; InstrumentMemOperandPrologue ( RegCtx , Ctx , Out ) ; { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , SrcReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , SrcReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr ::


<s> finish_opt_n_resolution ( unsigned int argno , unsigned int first_argno , type_suffix_index first_type , type_class_index expected_tclass , unsigned int expected_bits , type_suffix_index inferred_type ) { if ( inferred_type == NUM_TYPE_SUFFIXES ) inferred_type = first_type ; tree scalar_form = lookup_form ( MODE_n , inferred_type ) ; if ( scalar_argument_p ( argno ) ) { if ( scalar_form ) return scalar_form ; tree res = resolve_to ( mode_suffix_id , inferred_type ) ; if ( res != error_mark_node ) error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , get_vector_type ( first_type ) ) ; return error_mark_node


<s> ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget . hasMSA ( ) && type -> isVectorTy ( ) && type -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) == <NUM_LIT> ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case


<s> void nds32_split_sms ( rtx out , rtx in0 , rtx in1 , rtx in0_idx0 , rtx in1_idx0 , rtx in0_idx1 , rtx in1_idx1 ) { rtx result0 = gen_reg_rtx ( SImode ) ; rtx result1 = gen_reg_rtx ( SImode


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; Chain = DAG . getStore ( Chain , DL , Lo , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . getAlignment ( ) , Nd . getTBAAInfo ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr ,

DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ;


<s> imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return


<s> CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = <STR_LIT> ; } else if ( el_mode == SFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = <STR_LIT> ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( )


<s> if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( & N , N0 , N1


<s> AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> assert ( Subtarget . isTargetDarwin ( ) && Subtarget . is64Bit ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; RTLIB :: Libcall LC = isF64 ? RTLIB :: SINCOS_STRET_F64 : RTLIB :: SINCOS_STRET_F32 ; const char * LibcallName = TLI . getLibcallName ( LC ) ; SDValue Callee = DAG . getExternalFunctionSymbol ( LibcallName ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy ) : ( Type * ) FixedVectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo


<s> break ; } std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred )


<s> if ( MatchAddressRecursively ( N , AM , <NUM_LIT> ) ) return true ; if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == <NUM_LIT> ) { AM . Base_Reg =


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg


<s> count += get_attr_length ( from ) ; tmp = is_jump_table ( from ) ; if ( tmp != NULL ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next


<s> unsigned int regno ; rtx_insn * insn ; for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno -- > <NUM_LIT> ; ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg (


<s> unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) .


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveFReg ( unsigned Reg , int Offset ) { assert ( Offset >= <NUM_LIT> && Offset


<s> assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcSubIdx = MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; DstSubIdx = MI . getOperand ( <NUM_LIT>


<s> static StringRef computeDataLayout ( const Triple & TT ) { assert ( TT . isArch16Bit ( ) && <STR_LIT> ) ; return


<s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand


<s> return ( __m128i ) __builtin_ia32_cvttps2uqq128_mask ( ( __v4sf ) __A , (


<s> if ( ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GV -> getType (


<s> for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ; else MIB . addMBB ( restoreMBB ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MIB . addRegMask ( RegInfo -> getNoPreservedMask ( ) ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , mainDstReg ) ; mainMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( mainDstReg ) . addMBB ( mainMBB ) . addReg ( restoreDstReg ) . addMBB ( restoreMBB ) ; if ( RegInfo -> hasBasePointer ( * MF ) ) { const bool Uses64BitFramePtr = Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FI -> setRestoreBasePointer ( MF ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * MF ) ; unsigned BasePtr = RegInfo -> getBaseRegister ( ) ; unsigned Opm = Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( restoreMBB , DL , TII -> get ( Opm ) , BasePtr ) , FramePtr , true , <ISA_LIT>FI -> getRestoreBasePointerOffset ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } BuildMI ( restoreMBB , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( restoreMBB , DL , TII -> get ( <STR_LIT> )


<s> enum aarch64_parse_opt_result parse_res = aarch64_parse_tune ( str , res ) ; if ( parse_res == AARCH64_PARSE_OK ) return true ; switch ( parse_res )


<s> bool <ISA_LIT>FrameLowering :: hasGOT ( const MachineFunction


<s> if ( insn -> vectorExtensionType != TYPE_EVEX ) return - <NUM_LIT> ; insn -> writemask = static_cast < Reg > ( aaaFromEVEX4of4 ( insn -> vectorExtensionPrefix


<s> Address ( ) : Kind ( RegBase ) , ExtType ( <STR_LIT> ) , OffsetReg ( <NUM_LIT> ) , Shift ( <NUM_LIT> ) , Offset ( <NUM_LIT> ) , GV ( nullptr ) { Base . Reg


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler


<s> bool <ISA_LIT>TargetLowering :: useStackGuardXorFP ( ) const { return Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) && ! Subtarget


<s> getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; return false


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return &


<s> assert ( ( ! table || Domain < <NUM_LIT> ) && <STR_LIT> ) ; } if ( ! table ) { assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; table = lookup ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX2InsertExtract ) ; } if ( ! table ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512 ) ; if ( table && Domain == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQ ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT>


<s> <STR_LIT> CC = <STR_LIT> ( <STR_LIT> ( MI . getOpcode ( ) ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction :: iterator It = ++ MBB -> getIterator ( ) ; MachineFunction * F = MBB -> getParent ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( BB ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; if ( checkEFLAGSLive ( LastCMOV ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB -> addSuccessor ( SinkMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ( CC ) ) ) . addMBB ( SinkMBB ) ; FalseMBB -> addSuccessor ( SinkMBB ) ; MachineInstrBuilder MIB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> ( MIIt -> getOpcode ( ) ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; auto Op1Itr = RegRewriteTable . find ( Op1Reg ) ; if ( Op1Itr != RegRewriteTable . end ( ) ) Op1Reg = Op1Itr -> second . first ; auto Op2Itr = RegRewriteTable . find ( Op2Reg ) ; if ( Op2Itr != RegRewriteTable . end ( ) ) Op2Reg = Op2Itr -> second . second ; MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( FalseMBB ) . addReg ( Op2Reg ) . addMBB ( MBB ) ; ( void )


<s> switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign


<s> const MCSectionMachO & SMO = static_cast < const MCSectionMachO & > ( Section ) ; return SMO . getType ( ) ==


<s> void addImm0_15Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> bool ret = rs6000_legitimate_address_p ( mode , x , reg_ok_strict ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( mode ) , reg_ok_strict , ( reload_completed ? <STR_LIT> : ( reload_in_progress ? <STR_LIT> : <STR_LIT> ) ) , GET_RTX_NAME


<s> const MCExpr * Expr = getSubExpr ( ) ; if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) OS << '(' ; Expr -> print (


<s> EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt


<s> if ( rx_small_data_limit > <NUM_LIT> && GET_MODE_SIZE ( mode ) <= rx_small_data_limit && align <=


<s> } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal , <NUM_LIT> , false , SDLoc ( Op )


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { MCStreamer * S = createELFStreamer ( Context , MAB , OS , Emitter , RelaxAll , NoExecStack ) ; new <ISA_LIT>TargetELFStreamer (


<s> unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType (


<s> if ( Kind == MCExpr :: Binary ) { unsigned Res = getExprOpValue ( cast < MCBinaryExpr > ( Expr ) -> getLHS ( ) , Fixups , STI ) ; Res += getExprOpValue ( cast < MCBinaryExpr > ( Expr ) -> getRHS ( ) , Fixups , STI ) ; return Res ; } if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: CEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_CALL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_ABS_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_ABS_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TLSGD : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TLSLDM : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_DTP_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_DTP_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOTTPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TP_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TP_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT> ; } return


<s> if ( Index && MemKind != BDXMem && MemKind != BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Length && MemKind != BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length && MemKind == BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) .

getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;


<s> rtx mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; set_mem_align ( mem , <NUM_LIT> ) ; emit_move_insn ( reg , mem ) ; ix86_add_cfa_restore_note ( NULL_RTX , reg , cfa_offset ) ; cfa_offset -= <NUM_LIT>


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( )


<s> int <STR_LIT> ( SDNode * N , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return - <NUM_LIT> ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; unsigned i ; for ( i = <NUM_LIT> ; i != <NUM_LIT> && SVOp -> getMaskElt ( i ) < <NUM_LIT> ; ++ i ) ; if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; bool isLE = DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ; if ( ( ShuffleKind == <NUM_LIT> && ! isLE ) || ( ShuffleKind == <NUM_LIT> && isLE ) ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else if ( ShuffleKind == <NUM_LIT> ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ( ShiftAmt + i ) & <NUM_LIT> )


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const <ISA_LIT>TargetMachine & >


<s> strcpy ( target_str , original_str ) ; vectors_str = strstr ( target_str , <STR_LIT> ) ; if ( vectors_str != NULL ) { vectors_str = strtok ( vectors_str , <STR_LIT> ) ; value_str = strtok ( NULL , <STR_LIT> ) ; nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors = atoi ( value_str ) + <NUM_LIT> + <NUM_LIT> ; } else nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors = <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ; strcpy ( nds32_isr_vectors [ <NUM_LIT> ] . func_name , func_name ) ; strcpy ( target_str , original_str ) ; nmi_str = strstr ( target_str , <STR_LIT> ) ; if ( nmi_str != NULL ) { nmi_str = strtok ( nmi_str , <STR_LIT> ) ; value_str = strtok ( NULL , <STR_LIT> ) ; strcpy ( nds32_isr_vectors [ <NUM_LIT> ] . nmi_name , value_str


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSetFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHAddFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHNop ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveNext ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogStart ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogEnd ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHTrapFrame ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHMachineFrame ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHContext ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHClearUnwoundToCall ( Loc ) ; else return true ; } else return true ; return


<s> unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI . CreateFixedObject ( FrameObjSize , FrameObjOffset , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs ) return ; MVT RegTy = <STR_LIT> ( GPRSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ FirstReg + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg ,


<s> unsigned basereg = Is64Bit ? <STR_LIT> : <STR_LIT> ; return ( Op . isMem ( ) && ( Op . Mem . SegReg == <NUM_LIT> || Op . Mem . SegReg == <STR_LIT> ) && isa < MCConstantExpr > ( Op . Mem . Disp ) && cast < MCConstantExpr > ( Op . Mem

. Disp ) -> getValue ( ) == <NUM_LIT> && Op . Mem . BaseReg == basereg && Op . Mem . IndexReg == <NUM_LIT> ) ;


<s> if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; unsigned MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( *


<s> if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && x != CONST0_RTX ( mode ) ) return false ; if ( ! NEW_HP_ASSEMBLER && ! TARGET_GAS && GET_CODE ( x ) == LABEL_REF ) return false ; if ( tls_referenced_p ( x ) ) return false ; if ( TARGET_64BIT && GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( TARGET_64BIT && HOST_BITS_PER_WIDE_INT > <NUM_LIT> && GET_CODE ( x ) == CONST_INT && ! reload_in_progress && ! reload_completed && ! LEGITIMATE_64BIT_CONST_INT_P ( INTVAL ( x ) ) && ! pa_cint_ok_for_move ( UINTVAL ( x ) ) ) return false ; if ( function_label_operand ( x , mode ) ) return false ; return true


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( - OffImm ) << markup ( <STR_LIT> ) ; } else { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( OffImm ) << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> return arg == error_mark_node ? arg : TREE_TYPE (


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( TM -> getOptLevel (


<s> IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this


<s> for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; bool decrement = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; if ( ! increment && ! decrement ) continue ; new_rhs = rhs + ( increment ? <NUM_LIT> : - <NUM_LIT> ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) && ( rhs < <NUM_LIT> ) == ( new_rhs < <NUM_LIT> ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode , * op1


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = TM . getTargetData ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = ( TM . getFrameInfo ( ) -> getStackGrowthDirection ( ) == TargetFrameInfo :: StackGrowsUp ? TD -> getPointerSize ( ) : - TD -> getPointerSize ( ) ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; Offset = MaxOffset - Offset + saveAreaOffset ; if ( HasFP && FramePtr == Reg ) continue ; MachineLocation CSDst ( MachineLocation :: VirtualFP ,


<s> return ( _U_Qfcmp ( a , b , <NUM_LIT> )


<s> return ( __m256i ) __builtin_ia32_vcvttph2dq256_mask ( __C , ( __v8si )


<s> return PICStyle == PICStyles :: Style ::


<s> return ( ( qword ) ( vec_add ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT>


<s> return ( uint64x1_t ) { __builtin_aarch64_ushldi_uus ( __a [


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ; if ( UnpckNode ) return UnpckNode ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2


<s> unsigned Opc = Inst . getOpcode ( ) ; const signed Msb = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Inst . getOperand ( <NUM_LIT> ) . getImm ( ) : Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Lsb = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Inst . getOperand ( <NUM_LIT> ) . getImm ( ) : Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Msb < Lsb ) return Match_RequiresMsbNotLessThanLsb ; return Match_Success ; } } return


<s> Src = & MI . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; return true


<s> case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) ) ) ; SDValue MemOp ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; MemOp = DAG . getMemcpy ( Chain , dl , PtrOff , Arg , SizeNode , Flags . getByValAlign ( ) , false , true , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; } else { MemOp = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal (


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { llvm_report_error ( <STR_LIT> ) ; } if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; } SDValue Val ; if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag


<s> bool <ISA_LIT>LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; DefinedInBB . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign


<s> static MCSymbol * GetLazyPtr ( MCSymbol * Sym , MCContext & Ctx ) { StringRef NoStub = Sym -> getName ( ) . substr ( <NUM_LIT> , Sym -> getName ( ) . size ( ) - <NUM_LIT> ) ; return Ctx . GetOrCreateSymbol (


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Val ; Entry . Ty = Val . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsZExt = true ; Args . push_back ( Entry ) ; Entry . Node = Exponent ; Entry . Ty = Exponent . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsZExt = true ; Args . push_back ( Entry ) ; Type * LCRTy = Val . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; const auto * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool IsTC = TLI . isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) && F -> getReturnType ( ) == LCRTy ; if ( IsTC ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , LCRTy , Callee , std :: move ( Args ) ) . setTailCall ( IsTC ) ; std :: pair < SDValue , SDValue > CI = TLI . LowerCallTo ( CLI ) ; return ! CI . second . getNode ( ) ? DAG . getRoot (


<s> LLVM_EXPLICIT operator bool ( ) const { return RegSize


<s> unsigned getCalleeSavedFrameSize ( )


<s> void <ISA_LIT>AsmPrinter :: printPCLabel ( const MachineInstr *


<s> CCState CCRetInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs


<s> rtx xfoo0 ; if ( REG_P ( x ) ) { if ( ! reload_in_progress || reg_equiv_mem ( REGNO ( x ) ) == <NUM_LIT> || indirectable_address_p ( reg_equiv_mem ( REGNO ( x ) ) , strict , false ) ) return true ; } if ( indirectable_constant_address_p ( x , false ) ) return true ; if ( indirectable_address_p ( x , strict , false ) ) return true ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; if ( MEM_P ( x ) && indirectable_address_p ( xfoo0 , strict , true ) ) return true ; if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC ) && BASE_REGISTER_P ( xfoo0 , strict ) ) return true ; return false


<s> SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ; const bool ToSP = DefMI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; const unsigned t2ADD = ToSP ? <STR_LIT> : <STR_LIT> ; const unsigned t2SUB = ToSP ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? t2ADD : t2SUB ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? t2SUB : t2ADD ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; } case <STR_LIT> : case <STR_LIT> : if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } } } unsigned OpIdx = Commute ? <NUM_LIT> : <NUM_LIT> ; Register Reg1 = UseMI . getOperand ( OpIdx ) . getReg ( ) ; bool isKill = UseMI . getOperand ( OpIdx ) . isKill ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( Reg ) ; Register NewReg = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( NewUseOpc ) , NewReg ) . addReg ( Reg1 , getKillRegState ( isKill ) ) . addImm ( SOImmValV1 ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . setReg ( NewReg


) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> Name . insert ( Name . begin ( ) , Prefix , Prefix + strlen ( Prefix ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl


<s> return SelectAddrModeIndexed ( N , <NUM_LIT> , Base ,


<s> unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( <STR_LIT> ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; <STR_LIT> ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; DetectFamilyModel ( EAX , Family , Model ) ; IsBTMemSlow = IsAMD || ( Family ==


<s> if ( & vStream == & nulls ( ) ) loggerFn = <NUM_LIT> ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , ( void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return


<s> return __builtin_mve_vqaddq_uv4si ( __a ,


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( )


<s> inline SDValue getSmallIPtrImm ( unsigned Imm


<s> bool hasAbsoluteCall ( ) const { return HasAbsoluteCall


<s> if ( ACPV -> LabelId == LabelId ) return true ; if ( Kind == <STR_LIT> || Kind == <STR_LIT> ) return true ; } return false


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF


<s> std :: unique_ptr < ScheduleDAGMutation >

create<ISA_LIT>MacroFusionDAGMutation ( ) {


<s> return __builtin_mve_vrndxq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) ,


<s> std :: vector < <ISA_LIT>FrameSortingObject > SortingObjects ( MFI -> getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI -> getObjectAlignment ( Obj ) ; int ObjectSize = MFI -> getObjectSize ( Obj ) ; if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , <ISA_LIT>FrameSortingComparator ( ) ) ; int i = <NUM_LIT> ; for ( auto & Obj : SortingObjects


<s> const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II


<s> int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc .


<s> for ( const auto & LI : Succ -> liveins ( ) ) { int RegIdx = mapRegToGPRIndex ( LI . PhysReg ) ; if ( RegIdx >= <NUM_LIT> ) LOHInfos [ RegIdx ] . OneUser = true ; } } for ( const MachineInstr & MI : make_range ( MBB . rbegin ( ) , MBB . rend ( ) ) ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : if ( canDefBePartOfLOH ( MI ) ) { const MachineOperand & Def = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Def . isReg ( ) && Def . isDef ( ) && <STR_LIT> ) ; assert ( Op . isReg ( ) && Op . isUse ( ) && <STR_LIT> ) ; int DefIdx = mapRegToGPRIndex ( Def . getReg (


<s> return ( __m128i ) __builtin_ia32_pabsq128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 )


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , ScalarEvolution * SE , const SCEV * Ptr ) { unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; int MaxMergeDistance = <NUM_LIT> ; if ( ST -> hasNEON ( ) ) { if ( Ty -> isVectorTy ( ) && SE && ! BaseT :: isConstantStridedAccessLessThan ( SE , Ptr , MaxMergeDistance + <NUM_LIT> ) ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue Madd = DAG . getNode ( <STR_LIT> , DL , MAddVT , N0 , N1 ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , Madd , Zero ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Concat


<s> if ( flag_mkernel ) { rs6000_default_long_calls = <NUM_LIT> ; rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT ; } if ( ! flag_mkernel && ! flag_apple_kext && TARGET_64BIT && ! ( rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC ) ) rs6000_isa_flags |= OPTION_MASK_ALTIVEC ; if ( ! flag_mkernel && ! flag_apple_kext && strverscmp ( darwin_macosx_version_min , <STR_LIT> ) >= <NUM_LIT> && ! ( rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC ) && ! global_options_set . x_rs6000_cpu_index ) { rs6000_isa_flags |=


<s> static rtx sparc_builtin_setjmp_frame_value ( void ) { return hard_frame_pointer_rtx


<s> format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } macho :: RelocationEntry MRE ; MRE . Word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( macho :: RIT_Pair << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | macho :: RF_Scattered ) ; MRE . Word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) return false ; } macho :: RelocationEntry MRE ; MRE . Word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | macho :: RF_Scattered ) ; MRE . Word1 = Value ; Writer -> addRelocation ( Fragment -> getParent (


<s> case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f16_OP1 : case MachineCombinerPattern :: FMLSv4f16_OP2 : case MachineCombinerPattern :: FMLSv8f16_OP1 : case MachineCombinerPattern :: FMLSv8f16_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : case MachineCombinerPattern :: FMULv2i32_indexed_OP1 : case MachineCombinerPattern :: FMULv2i32_indexed_OP2 : case MachineCombinerPattern :: FMULv2i64_indexed_OP1 : case MachineCombinerPattern :: FMULv2i64_indexed_OP2 : case MachineCombinerPattern :: FMULv4i16_indexed_OP1 : case MachineCombinerPattern :: FMULv4i16_indexed_OP2 : case MachineCombinerPattern :: FMULv4i32_indexed_OP1 : case MachineCombinerPattern :: FMULv4i32_indexed_OP2 : case MachineCombinerPattern :: FMULv8i16_indexed_OP1 : case MachineCombinerPattern :: FMULv8i16_indexed_OP2 : case MachineCombinerPattern :: MULADDv8i8_OP1 : case MachineCombinerPattern :: MULADDv8i8_OP2 : case MachineCombinerPattern :: MULADDv16i8_OP1 : case MachineCombinerPattern :: MULADDv16i8_OP2 : case MachineCombinerPattern :: MULADDv4i16_OP1 : case MachineCombinerPattern :: MULADDv4i16_OP2 : case MachineCombinerPattern :: MULADDv8i16_OP1 : case MachineCombinerPattern :: MULADDv8i16_OP2 : case MachineCombinerPattern :: MULADDv2i32_OP1 : case MachineCombinerPattern :: MULADDv2i32_OP2 : case MachineCombinerPattern :: MULADDv4i32_OP1 : case MachineCombinerPattern :: MULADDv4i32_OP2 : case MachineCombinerPattern :: MULSUBv8i8_OP1 : case MachineCombinerPattern :: MULSUBv8i8_OP2 : case MachineCombinerPattern


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { EVT VT ; if ( N -> getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; VT = LD -> getMemoryVT ( ) ; } else if ( N -> getOpcode ( ) == <STR_LIT> ) { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { uint64_t RHSC = RHS


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder ,


<s> const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; { auto Op = MI . getOpcode ( ) ; if ( Op == <STR_LIT> || Op == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; } if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; const MCInstrDesc & Desc = MI . getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { default : NumBytes = <NUM_LIT> ; break ; case TargetOpcode :: STACKMAP : NumBytes = StackMapOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: PATCHPOINT : NumBytes = PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case


<s> if ( Stress ) return true ; if ( Cst -> getType ( ) -> isVectorTy (


<s> return __aarch64_vget_lane_any ( __a ,


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses (


<s> auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( k_RegList , Parser ) ; Op -> RegList . List = new SmallVector < unsigned , <NUM_LIT> > ( Regs . begin ( ) , Regs . end ( ) ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return Op


<s> rtx insn ; bool return_in_pc = false ; if ( ARM_FUNC_TYPE ( func_type ) != ARM_FT_INTERWORKED && ( TARGET_ARM || ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL ) && ! IS_STACKALIGN ( func_type ) && really_return && crtl -> args . pretend_args_size == <NUM_LIT> && saved_regs_mask & ( <NUM_LIT> << LR_REGNUM ) && ! crtl -> calls_eh_return ) { saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << PC_REGNUM ) ; return_in_pc = true ; } if ( num_regs == <NUM_LIT> && ( ! IS_INTERRUPT ( func_type ) || ! return_in_pc ) ) { for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; if ( i == PC_REGNUM ) { insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , i ) , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; insn = emit_jump_insn ( insn ) ; } else { insn = emit_insn ( gen_movsi ( gen_rtx_REG ( SImode , i ) , addr ) ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , i ) , NULL_RTX ) ; arm_add_cfa_adjust_cfa_note ( insn , UNITS_PER_WORD , stack_pointer_rtx , stack_pointer_rtx ) ; } } } else { if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) { if ( TARGET_THUMB2 ) thumb2_emit_ldrd_pop ( saved_regs_mask ) ; else if ( TARGET_ARM && ! IS_INTERRUPT ( func_type ) ) arm_emit_ldrd_pop ( saved_regs_mask ) ; else arm_emit_multi_reg_pop ( saved_regs_mask ) ; } else arm_emit_multi_reg_pop ( saved_regs_mask ) ; } if ( return_in_pc ) return ; } if ( crtl -> args . pretend_args_size ) { int i , j ; rtx dwarf = NULL_RTX ; rtx_insn * tmp = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( crtl -> args . pretend_args_size ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; if ( cfun -> machine -> uses_anonymous_args ) { int num_regs = crtl -> args . pretend_args_size / <NUM_LIT> ; saved_regs_mask = ( <NUM_LIT> >> num_regs ) & <NUM_LIT> ; for ( j = <NUM_LIT> , i = <NUM_LIT> ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { rtx reg = gen_rtx_REG ( SImode , i ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } REG_NOTES ( tmp ) = dwarf ; } arm_add_cfa_adjust_cfa_note ( tmp , crtl -> args . pretend_args_size , stack_pointer_rtx ,


<s> assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( getMemDisp ( ) )


<s> SDValue Input ; auto isSExtOfVecExtract = [ & ] ( SDValue Op ) -> bool { if ( ! Op ) return false ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Extract = Op . getOperand ( <NUM_LIT> ) ; if ( Extract . getOpcode ( ) == <STR_LIT> ) Extract = Extract . getOperand ( <NUM_LIT> ) ; if ( Extract . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * ExtOp = dyn_cast < ConstantSDNode > ( Extract . getOperand ( <NUM_LIT> ) ) ; if ( ! ExtOp ) return false ; Index = ExtOp -> getZExtValue ( ) ; if ( Input && Input != Extract . getOperand ( <NUM_LIT> ) ) return false ; if ( ! Input ) Input = Extract . getOperand ( <NUM_LIT> ) ; Elems = Elems << <NUM_LIT> ; Index = DAG . getDataLayout ( ) . isLittleEndian ( ) ? Index : Index << <NUM_LIT> ; Elems |= Index ; return true ; } ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; i ++ ) { if ( ! isSExtOfVecExtract ( N -> getOperand ( i ) ) ) { return SDValue ( ) ; } } int TgtElemArrayIdx ; int InputSize = Input . getValueType ( ) . getScalarSizeInBits ( ) ; int OutputSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; if ( InputSize + OutputSize == <NUM_LIT> ) TgtElemArrayIdx = <NUM_LIT> ; else if ( InputSize + OutputSize == <NUM_LIT> ) TgtElemArrayIdx = <NUM_LIT> ; else if ( InputSize + OutputSize == <NUM_LIT> ) TgtElemArrayIdx = <NUM_LIT> ; else if ( InputSize + OutputSize == <NUM_LIT> ) TgtElemArrayIdx = <NUM_LIT> ; else if ( InputSize + OutputSize == <NUM_LIT> ) TgtElemArrayIdx = <NUM_LIT> ; else return SDValue ( ) ; uint64_t CorrectElems = TargetElems [ TgtElemArrayIdx ] ; CorrectElems = DAG . getDataLayout ( ) . isLittleEndian ( ) ? CorrectElems & <NUM_LIT> : CorrectElems & <NUM_LIT> ; if ( Elems != CorrectElems ) { return addShuffleForVecExtend ( N , DAG , Input , Elems , CorrectElems ) ; } return SDValue (


<s> if ( TheTriple . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , TAB , OS , Emitter , RelaxAll , true ) ; return create<ISA_LIT>ELFStreamer ( Ctx , TAB ,


<s> bool <ISA_LIT>RegisterInfo :: isReservedReg ( const MachineFunction & MF , unsigned Reg ) const { return getReservedRegs ( MF )


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ; return false


<s> getGlobalBaseReg ( ) ; initGlobalBaseReg ( ) ; } return


<s> <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( IsStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } llvm_unreachable (


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return


<s> static void addOperands ( MachineInstrBuilder & MIB , ArrayRef < MachineOperand > MOs , int PtrOffset = <NUM_LIT> ) { unsigned NumAddrOps = MOs . size ( ) ; if ( NumAddrOps < <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand


<s> MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } else { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) ; } if ( setLR ) MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegState :: Implicit ) . addReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegState :: ImplicitDefine ) ; if ( OpC == <STR_LIT> || OpC == <STR_LIT> ) MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return true ; } return false


<s> if ( Mapping . isValid ( ) ) return Mapping ; LLT Ty = MI . getType ( ) ; unsigned BankID ; if ( Ty . isVector ( ) ) BankID = <STR_LIT> ; else BankID = <STR_LIT> ; Mapping = InstructionMapping { <NUM_LIT> , <NUM_LIT> , MI . getNumOperands ( ) } ; int Size = Ty . isSized ( ) ? Ty . getSizeInBits ( )


<s> SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformShuffleCombine ( N , DAG , * this ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG ,


<s> rtx pat = PATTERN ( insn ) ; rtx unspec_relax_group = XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; int group_id = nds32_alloc_relax_group_id (


<s> bool <ISA_LIT>SETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( VT . isFatPointer ( ) ) return false ; <STR_LIT> SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( AS ) ) { if ( Fast ) { if ( Subtarget . isCheri ( ) ) * Fast = false ; else * Fast =


<s> AM . SymbolFlags = GA -> getTargetFlags ( ) ; if ( N . getValueType ( ) == <STR_LIT> ) { AM . Scale = <NUM_LIT> ; AM . IndexReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } else { AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } getAddressOperands ( AM , SDLoc ( N ) , Base , Scale , Index , Disp , Segment ) ; return true


<s> } Opcode = <STR_LIT> ; } else if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = RHS . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( SubOp0 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } } if ( Opcode == <NUM_LIT> ) Opcode = <STR_LIT> ; SDValue Condition = DAG . getConstant ( Predicate , DL , MVT_CC ) ; <STR_LIT> InvOutCC = <STR_LIT> ( OutCC )


<s> static SDValue lowerVectorShuffleAsBitBlend ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG ) { assert ( VT . isInteger ( ) && <STR_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; int NumEltBits = EltVT . getSizeInBits ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask

[ i ] != i + Size ) return SDValue ( ) ;


<s> if ( TrialOffset - UserOffset <= MaxDisp ) return true ; } else if ( NegativeOK ) { if ( UserOffset - TrialOffset <= MaxDisp ) return true ; } return


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF

:: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ;


<s> static bool matchDupFromInsertVectorElt ( int Lane , MachineInstr & MI , MachineRegisterInfo & MRI , ShuffleVectorPseudo & MatchInfo ) { if ( Lane != <NUM_LIT> ) return false ; auto * InsMI = getOpcodeDef ( TargetOpcode :: G_INSERT_VECTOR_ELT , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! InsMI ) return false ; if ( ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return false ; int64_t Index = <NUM_LIT> ; if ( ! mi_match ( InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Index ) ) || Index ) return false ; MatchInfo = ShuffleVectorPseudo ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , { InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; return


<s> static bool alg_usable_p ( enum stringop_alg alg , bool memset , bool have_as ) { if ( alg == no_stringop ) return false ; if ( alg == vector_loop ) return TARGET_SSE || TARGET_AVX ; if ( alg == rep_prefix_1_byte || alg == rep_prefix_4_byte ||


<s> unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; SDValue Ld = DAG . getLoad ( Cst . getValueType ( ) , DL , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; SDValue Brcst = DAG . getNode ( <STR_LIT> , DL , ExtVT , In , Ld ) ; if ( VT . is512BitVector ( ) ) return Brcst ; return DAG . getNode ( <STR_LIT> , DL


<s> if ( immediate_operand ( src2 , mode ) ) return false ; if ( immediate_operand ( src1 , mode ) ) return true ; if ( MEM_P ( src2 ) ) return false ; if ( MEM_P ( src1 ) ) return true ; return false


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> uint16_t DestEncoding = TRI -> getEncodingValue ( DestReg ) ; uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned NumRegs = Indices . size ( ) ; int SubReg = <NUM_LIT> , End = NumRegs , Incr = <NUM_LIT> ; if ( forwardCopyWillClobberTuple ( DestEncoding , SrcEncoding , NumRegs ) ) { SubReg = NumRegs - <NUM_LIT> ; End = - <NUM_LIT> ; Incr =


<s> name = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM ) ; fprintf ( f , <STR_LIT> ) ; if ( arm_dllexport_name_p ( name ) ) name = arm_strip_name_encoding ( name ) ; asm_fprintf ( f , <STR_LIT> ,


<s> for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) for ( unsigned j = <NUM_LIT> ; j != SrcNumElts ; ++


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOpt :: findMatchingUpdateInsnForward ( MachineBasicBlock :: iterator I , int UnscaledOffset , unsigned Limit ) { MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineInstr * MemMI = I ; MachineBasicBlock :: iterator MBBI = I ; unsigned BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI =


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText ( <STR_LIT>

+ Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> unsigned SrcReg = <NUM_LIT> ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; SrcReg = getRegForValue ( Op0 ) ; if ( SrcReg == <NUM_LIT> ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT>


<s> if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) >= <NUM_LIT> ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP

, MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ;


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; assert ( rsym != NULL && <STR_LIT> ) ; assert ( pSection . getLink ( ) != NULL ) ; if ( ( pSection . getLink ( ) -> flag ( ) & llvm :: ELF :: SHF_ALLOC ) == <NUM_LIT> ) return ; if ( rsym -> isLocal ( ) ) scanLocalReloc ( pReloc , pSection ) ; else scanGlobalReloc ( pReloc , pBuilder , pSection ) ; if ( rsym -> isUndef ( ) && ! rsym -> isDyn ( ) && ! rsym -> isWeak ( ) && ! rsym ->

isNull ( ) ) issueUndefRef ( pReloc , pSection , pInput ) ;


<s> bool has<ISA_LIT>32r2 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>32r2 || <ISA_LIT>ArchVersion == <ISA_LIT>32r6 || <ISA_LIT>ArchVersion ==


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target ,


<s> static int stackSlotSize ( ) { return <NUM_LIT>


<s> else { if ( ! anchor_reg ) { anchor_reg = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_insn ( gen_add3_insn ( anchor_reg , base_rtx , gen_int_mode ( fp_offset , Pmode ) ) ) ; } base_rtx = anchor_reg ; } offset -= fp_offset ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; bool need_cfa_note_p = ( base_rtx != stack_pointer_rtx ) ; if ( ! aarch64_sve_mode_p ( mode ) && ( regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset += GET_MODE_SIZE ( mode ) ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; if ( aarch64_emit_cfi_for_reg_p ( regno2 ) ) { if ( need_cfa_note_p ) aarch64_add_cfa_expression ( insn , reg2 , stack_pointer_rtx , sp_offset + GET_MODE_SIZE ( mode ) ) ; else RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } regno = regno2 ; } else if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) { insn = emit_insn ( gen_aarch64_pred_mov ( mode , mem , ptrue , reg ) ) ; need_cfa_note_p = true ; } else if ( aarch64_sve_mode_p ( mode ) ) insn = emit_insn ( gen_rtx_SET


<s> if ( DataVT == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue SrcNew ; if ( Data . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode


<s> if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) { if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( )

) PM -> add ( createThumb2SizeReductionPass ( ) ) ;


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RTB = DAG . getNode ( <STR_LIT> , dl , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RTB , RTB . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( N -> isStrictFPOpcode ( ) ? <NUM_LIT> : <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl ) ) ; return ; case <STR_LIT> : { if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return ; SDValue Lowered = LowerTRUNCATEVector ( SDValue ( N , <NUM_LIT> ) , DAG ) ; if ( Lowered ) Results . push_back ( Lowered ) ; return ; } case <STR_LIT> : return ; case <STR_LIT> : SDValue Lowered = LowerFP_EXTEND ( SDValue (


<s> size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; j != e ; ++ j ) { Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; if ( MergedSize > MaxOffset ) { break ; } Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { Constant * Idx [ <NUM_LIT> ] = { ConstantInt :: get ( Int32Ty , <NUM_LIT> ) , ConstantInt :: get ( Int32Ty , k - i ) } ; Constant * GEP = ConstantExpr :: getInBoundsGetElementPtr ( MergedGV , Idx ) ; Globals [ k ] -> replaceAllUsesWith


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = <STR_LIT> ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! TM . Options

. UseSoftFloat ) In<ISA_LIT>16HardFloat = true ;


<s> if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) == <STR_LIT> ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , <NUM_LIT> > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > <NUM_LIT> ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( <NUM_LIT> ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain = UseChain ; } } else if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != <STR_LIT> || ! Copy -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else { return false ; } bool HasRet =


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm (


<s> unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) <<


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> EmitImmediate ( const MCOperand & DispOp , unsigned Size , MCFixupKind FixupKind , unsigned & CurByte , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , int ImmOffset ) const { if ( DispOp . isImm ( ) ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } const MCExpr * Expr = DispOp . getExpr ( ) ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create (


<s> Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_YB ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_YB ) ; } else { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_BY ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_BY ) ; } return