<s> auto FProb = FuncInfo -> BPI -> getEdgeProbability ( BB , FBB ) ; const uint32_t Threshold = <NUM_LIT> ; if ( std :: max ( TProb , FProb ) / Threshold < std :: min ( TProb , FProb ) ) return <STR_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FuncInfo -> Fn -> getName ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << <STR_LIT> << TBB -> getName ( ) << <STR_LIT> << TProb << <STR_LIT> <<

<STR_LIT> << FBB -> getName ( ) << <STR_LIT> << FProb << <STR_LIT> ) ;


<s> int cur_pos ; cur_pos = <NUM_LIT> ; fprintf ( stream , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < len ; i ++ ) { int c ; c = ( unsigned char ) string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream )


<s> rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn )


<s> static bool shouldPreventUndefRegUpdateMemFold ( MachineFunction & MF , MachineInstr & MI ) { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) , true ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isUndef ( )


<s> PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; SuccPrepCount = <NUM_LIT> ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I

) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> bool pru_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { bool in_memory = ( ! pru_arg_in_reg_bysize ( int_size_in_bytes ( type ) ) || int_size_in_bytes ( type ) == - <NUM_LIT> ) ; return


<s> unsigned <ISA_LIT>InstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>ConditionOptimizer :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree


<s> if ( Kind == k_Immediate && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMemory ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm ->


<s> static SDValue materializeSBB ( SDNode * N , SDValue EFLAGS , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue CF = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue SBB = DAG . getNode ( <STR_LIT> , DL


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> hasAVX ( ) ) { DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> ) { return Insert128BitVector ( Vec , SubVec , Idx , DAG ,


<s> if ( d -> perm [ i ] != i + nelt ) ident2 = false ; } else { dsecond . perm [ i ] = <NUM_LIT> ; dfirst . perm [ i ] = d -> perm [ i ] ; if ( d -> perm [ i ] != i ) ident1 = false ; } if ( two_insn && ! ident1 && ! ident2 ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( dfirst . perm [ i ] == <NUM_LIT> ) { if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> && dfirst . perm [ i ^ ( nelt / <NUM_LIT> ) ] != <NUM_LIT> ) dfirst . perm [ i ] = dfirst . perm [ i ^ ( nelt / <NUM_LIT> ) ] ^ ( nelt / <NUM_LIT> ) ; else dfirst . perm [ i ] = i ; } else { if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> && dsecond . perm [ i ^ ( nelt / <NUM_LIT> ) ] != <NUM_LIT> ) dsecond . perm [ i ] = dsecond . perm [ i ^ ( nelt / <NUM_LIT> ) ] ^ ( nelt / <NUM_LIT> ) ; else dsecond . perm [ i ] = i ; } if ( ! d -> testing_p ) { if ( ! ident1 ) dfinal . op0 = dfirst . target = gen_reg_rtx ( d -> vmode ) ; if ( ! ident2 ) dfinal . op1 = dsecond . target = gen_reg_rtx ( d -> vmode ) ; } bool ok ; rtx_insn * seq1 = NULL , * seq2 = NULL ; if ( ! ident1 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dfirst ) ; seq1 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( ! ident2 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dsecond ) ; seq2 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( d -> testing_p ) return true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) dfinal . perm [ i ] = ( d -> perm [ i ] >= nelt ? i + nelt : i ) ; emit_insn ( seq1


<s> SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getUNDEF ( SVT ) ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , DL , { VT , <STR_LIT> } , { Op -> getOperand ( <NUM_LIT> ) , Res } ) ; return DAG . getNode ( <STR_LIT> , DL


<s> const <ISA_LIT>Reginfo & getMReginfo (


<s> static DecodeStatus DecodeGPR32spRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler


<s> static unsigned getDUPLANEOp ( EVT EltType ) { if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> )


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR32DecoderTable [ RegNo ] ; if ( Register == <STR_LIT> )


<s> unsigned getModImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & ST ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind ,


<s> BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setAlignment ( Align ( <NUM_LIT> ) ) ; } else { CPEBB -> setAlignment ( getCPEAlign ( * CPEBB -> begin (


<s> unsigned getRegisterListOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; MBB . erase ( MI


<s> if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue V = lowerVectorShuffleAsByteShiftMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue Unpack = lowerShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Unpack ; if ( ! IsBlendSupported && Subtarget


<s> SplatValueA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValueB ) ; } if ( BigEndian ) std :: swap ( SplatValueA , SplatValueB ) ; SDValue Ops [ <NUM_LIT> ] = { SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy ,

makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ;


<s> virtual bool gate ( function * ) { if ( aarch_bti_enabled


<s> const unsigned globalRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; globalRegs [ i ] != <NUM_LIT> ; ++ i ) { unsigned reg = globalRegs [


<s> uint64_t Top = ( Mask >> First ) + <NUM_LIT> ; if ( ( Top & - Top ) == Top ) { LSB = First ; Length = findFirstSet ( Top ) ; return true ; } return


<s> MachineBasicBlock * MBB = & * I ; if ( ! MDT -> isReachableFromEntry ( MBB ) ) continue ; for ( MachineBasicBlock :: iterator MII = MBB -> getFirstTerminator ( ) , MIIE =

MBB -> end ( ) ; MII != MIIE ; ++ MII ) {


<s> virtual const MandarinSubtarget * getSubtargetImpl ( ) const { return &


<s> assert ( MBBI -> isCompare ( ) && MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ! MBBI -> mayLoad ( ) && <STR_LIT> ) ; MachineBasicBlock * MBB = MBBI -> getParent ( ) ; bool CCLive = true ; SmallVector < MachineInstr * , <NUM_LIT> > CCUsers ; for ( MachineBasicBlock :: iterator Itr = std :: next ( MBBI ) ; Itr != MBB -> end ( ) ; ++ Itr ) { if ( Itr -> readsRegister ( <STR_LIT> ) ) { unsigned Flags = Itr -> getDesc ( ) .


<s> <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction


<s> EmitBundleLock ( false ) ; if ( MaskBefore ) { unsigned BaseReg = MI . getOperand ( AddrIdx ) . getReg ( ) ; emitMask ( BaseReg , LoadStoreStackMaskReg , STI ) ; } MCELFStreamer :: EmitInstruction ( MI , STI ) ; if ( MaskAfter ) { unsigned SPReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( <STR_LIT> == SPReg


<s> case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FSQRT : case TargetOpcode ::


<s> EVT NewIndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , Index . getValueType ( ) . getVectorElementType ( ) , <NUM_LIT> ) ; Index = DAG . getNode ( <STR_LIT> , dl , NewIndexVT , Index , DAG . getUNDEF ( Index . getValueType ( ) ) ) ; Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index , Scale } ; return DAG . getMaskedScatter ( DAG . getVTList ( <STR_LIT> ) , N -> getMemoryVT ( ) , dl , Ops , N -> getMemOperand ( ) ) ; } MVT IndexVT = Index . getSimpleValueType ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; if ( IndexVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; Src = ExtendToType ( Src , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDVTList VTs = DAG . getVTList ( MaskVT


<s> } LDM . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; STM . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; std :: sort ( ScratchRegs . begin ( ) , ScratchRegs . end ( ) , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue


<s> static inline bool isSVEMaskOfIdenticalElements ( int64_t Imm ) { auto Parts = bit_cast < std :: array < T , sizeof ( int64_t ) / sizeof ( T ) >> ( Imm ) ; return all_of ( Parts , [ & ] ( T Elem ) {

return Elem == Parts [ <NUM_LIT> ] ; } ) ;


<s> void addMSACtrlAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> return isDisp8 ( Value ) ; } unsigned Mask = CD8_Scale - <NUM_LIT> ; assert ( ( CD8_Scale & Mask ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value & Mask ) return false ; Value /= ( int ) CD8_Scale ; bool Ret = ( Value ==


<s> aarch64_init_simd_builtin_types ( ) ; aarch64_init_simd_builtin_scalar_types ( ) ; aarch64_init_simd_builtin_functions (


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo (


<s> return ( __m256 ) __builtin_ia32_loadaps256_mask ( ( __v8sf * ) __P , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8


<s> bool <ISA_LIT>BaseRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { const MCInstrDesc & Desc = MI -> getDesc ( ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; unsigned i = <NUM_LIT> ; while ( ! MI -> getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT>


<s> auto CheckValueSize = [ TargetElemMaxSize ] ( Value * OffsetElem ) { ConstantInt * OConst = dyn_cast < ConstantInt > ( OffsetElem ) ; if ( ! OConst ) return false ; int SExtValue = OConst -> getSExtValue ( ) ; if ( SExtValue >= TargetElemMaxSize || SExtValue < <NUM_LIT> ) return false ; return true ; } ; if ( isa < FixedVectorType > ( ConstOff -> getType ( ) ) ) { for ( unsigned i = <NUM_LIT> ; i < TargetElemCount ; i ++ ) { if ( ! CheckValueSize ( ConstOff -> getAggregateElement ( i ) ) ) return


<s> static <ISA_LIT>Operand * CreateShifter ( <STR_LIT> ShOp , unsigned Val , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Shifter , Ctx ) ; Op -> Shifter . Val = <STR_LIT> ( ShOp , Val ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> } if ( isVCTP ( MI ) && ! AddVCTP ( MI ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; bool IsUse = false ; unsigned LastOpIdx = MI -> getNumOperands ( ) - <NUM_LIT> ; for ( auto & Op : enumerate ( reverse ( MCID . operands ( ) ) ) ) { const MachineOperand & MO = MI -> getOperand ( LastOpIdx - Op . index ( ) ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( <STR_LIT> ( Op . value ( ) . OperandType ) ) { VPTState :: addInst ( MI ) ; IsUse = true ; } else if ( MI -> getOpcode ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } bool RequiresExplicitPredication = ( MCID . TSFlags &


<s> assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int Offset = AFI -> getCalleeSavedStackSize ( ) ; unsigned GPRSaveSize = AFI -> getVarArgsGPRSize ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetWindows ( ) ) Offset -= alignTo ( GPRSaveSize , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] .


<s> Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult


<s> return ( __m128i ) __builtin_ia32_pmovqb256_mask ( ( __v4di ) __A , ( __v16qi )


<s> InsertionPointsPerFunc InsertPtsPerFunc ; computeInsertionPoints ( Val ,


<s> else if ( code == 'R' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , <NUM_LIT> - INTVAL ( x ) ) ; else if ( code == 'H' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( int ) ( <NUM_LIT> & ~ INTVAL ( x ) ) ) ; else if ( code == 'h' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( short ) - INTVAL ( x ) ) ; else if ( code == 'B' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( int ) ( <NUM_LIT> & ~ INTVAL ( x ) ) ) ; else if ( code == 'b' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( int ) ( <NUM_LIT> & - INTVAL ( x ) ) ) ; else if ( code == 'M' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ~ ( ( <NUM_LIT> << INTVAL ( x ) ) - <NUM_LIT> ) ) ; else if ( code == 'x' && CONST_INT_P ( x ) ) fprintf ( file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; else if ( REG_P ( x ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x )


<s> return getLoadStoreRegOpcode ( SrcReg , RC , isStackAligned


<s> static rtx moxie_static_chain ( const_tree ARG_UNUSED ( fndecl_or_type ) , bool incoming_p ) { rtx addr , mem ; if ( incoming_p ) addr = plus_constant ( Pmode , arg_pointer_rtx , <NUM_LIT> * UNITS_PER_WORD ) ; else addr = plus_constant ( Pmode , stack_pointer_rtx , - UNITS_PER_WORD ) ; mem = gen_rtx_MEM ( Pmode , addr ) ; MEM_NOTRAP_P ( mem


<s> if ( GlobalBaseReg ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * PtrRC = Subtarget . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; GlobalBaseReg = RegInfo . createVirtualRegister ( PtrRC ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) , GlobalBaseReg ) ; <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { const GlobalValue * GV = MO . getGlobal ( ) ; if ( const GlobalVariable * GVB = dyn_cast < GlobalVariable > ( GV ) ) if ( GV -> getSection ( ) == <STR_LIT> ) return getAuthGVStub ( GVB , Printer ) ; unsigned TargetFlags = MO . getTargetFlags ( ) ; const Triple & TheTriple = Printer . TM . getTargetTriple ( ) ; if ( ! TheTriple . isOSBinFormatCOFF ( ) ) return Printer . getSymbolPreferLocal ( * GV ) ; assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & ( <STR_LIT> | <STR_LIT> ) ) ; if ( ! IsIndirect ) return Printer . getSymbol ( GV ) ; SmallString < <NUM_LIT> > Name ; if ( TargetFlags & <STR_LIT> ) Name = <STR_LIT> ; else if ( TargetFlags & <STR_LIT> ) Name = <STR_LIT> ; Printer . TM . getNameWithPrefix ( Name , GV , Printer . getObjFileLowering ( ) . getMangler ( ) ) ; MCSymbol * MCSym = Ctx .


<s> return isConstantImm ( ) && isUInt < Bits > ( getConstantImm ( ) - Offset


<s> void eraseMatchingBitGroups ( function_ref < bool ( const BitGroup & ) > F ) { BitGroups . erase ( std :: remove_if ( BitGroups . begin ( ) , BitGroups . end ( ) , F ) , BitGroups . end


<s> void <ISA_LIT>DAGToDAGISel :: InstructionSelect ( ) { DEBUG ( BB -> dump ( ) ) ; DOUT << <STR_LIT> ; Indent = <NUM_LIT> ; SelectRoot ( *


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> printInstruction ( MI ) ; OutStreamer . AddBlankLine (


<s> assert ( Subtarget -> hasFP64 ( ) || RHS . getValueType ( ) != <STR_LIT> ) ; SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> return <STR_LIT> ( ( Imm >> <NUM_LIT> )


<s> vec_char16 av ; av = ( vec_char16 ) ( a ) ; return ( ( qword ) ( vec_unpackh ( vec_perm ( av , av , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>

, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ) ;


<s> IRBuilder < > Builder ( & * II ) ; Ptr = Builder . CreateBitCast ( Ptr , STy -> getElementType ( <NUM_LIT> ) -> getPointerTo ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < STy -> getNumElements ( ) ; ++ i ) { auto * Idx = ConstantInt :: get ( Builder . getInt64Ty ( ) , i ) ; auto * Addr = Builder . CreateGEP ( Ptr , Idx ) ; auto * Data = Builder . CreateExtractValue ( Val , i ) ; auto NewStore = Builder . CreateStore ( Data , Addr ) ; NewStore -> setDebugLoc ( II -> getDebugLoc ( ) ) ; } II -> eraseFromParent (


<s> Parser . Lex ( ) ; Code16GCC = true ; if ( ! is16BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal ==


<s> SMLoc getEndLoc ( ) const override { return EndLoc


<s> inline SDValue getI32Imm ( unsigned Imm , SDLoc DL ) { return CurDAG -> getTargetConstant ( Imm , DL ,


<s> return ( ( qword ) ( vec_and ( ( vec_char16 ) ( a ) , vec_splat ( ( vec_char16 ) ( si_from_char


<s> bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo


<s> unsigned MaskEltSize = MaskVT . getScalarSizeInBits ( ) ; if ( AllowIntDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE41 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) ) { unsigned MaxScale = <NUM_LIT> / MaskEltSize ; for ( unsigned Scale = <NUM_LIT> ; Scale <= MaxScale ; Scale *= <NUM_LIT> ) { bool Match = true ; unsigned NumDstElts = NumMaskElts / Scale ; for ( unsigned i = <NUM_LIT> ; i != NumDstElts && Match ; ++ i ) { Match &= isUndefOrEqual ( Mask [ i * Scale ] , ( int ) i ) ; Match &= isUndefOrZeroInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; } if ( Match ) { unsigned SrcSize = std :: max ( <NUM_LIT> , NumDstElts * MaskEltSize ) ; MVT ScalarTy = MaskVT . isInteger ( ) ? MaskVT . getScalarType ( ) : <STR_LIT> ( MaskEltSize ) ; SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) { V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( <STR_LIT> ) ; } else Shuffle = unsigned ( <STR_LIT> ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( ! Subtarget . hasAVX2 ( ) && isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> ,


<s> void optimization_options ( int level ATTRIBUTE_UNUSED , int size ATTRIBUTE_UNUSED


<s> if ( AssignFn ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ) return true ; StackSize = std :: max ( StackSize , static_cast < uint64_t > ( State . getNextStackOffset ( ) ) ) ; return


<s> __inline__ static unsigned long long sh_media_MSHFLO_W ( unsigned long


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarSizeInBits ( ) %

<NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ;


<s> llvm :: sort ( Relocs . begin ( ) , Relocs . end ( ) , [ ] ( const ELFRelocationEntry & A , const ELFRelocationEntry & B ) { return A . Offset < B . Offset ; } ) ; std :: list < <ISA_LIT>RelocationEntry > Sorted ; std :: list < ELFRelocationEntry > Remainder ; LLVM_DEBUG ( dumpRelocs ( <STR_LIT> , Relocs ) ) ; copy_if_else ( Relocs . begin ( ) , Relocs . end ( ) , std :: back_inserter ( Remainder ) , std :: back_inserter ( Sorted ) , [ ] ( const ELFRelocationEntry & Reloc ) { return getMatchingLoType ( Reloc ) != ELF :: R_MIPS_NONE ; } ) ; for ( auto & R : Remainder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << R << <STR_LIT> ) ; unsigned MatchingType = getMatchingLoType ( R ) ; assert ( MatchingType != ELF


<s> return hasReservedCallFrame ( MF ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI ->


<s> static machine_mode aarch64_simd_container_mode ( machine_mode mode , unsigned width ) { gcc_assert ( width == <NUM_LIT> || width == <NUM_LIT> ) ; if ( TARGET_SIMD ) { if ( width == <NUM_LIT> ) switch ( mode ) { case


<s> unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; if ( ! MI . hasOneMemOperand ( ) ) return false ; const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; if ( MMO . isVolatile ( ) || MMO . isAtomic ( ) ) return false ; if ( MMO . getAlign ( ) < Align ( <NUM_LIT> ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT>


<s> void i386_pe_adjust_class_at_definition ( tree t ) { tree member ; gcc_assert ( CLASS_TYPE_P ( t ) ) ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t ) ) != NULL_TREE ) { tree tmv = TYPE_MAIN_VARIANT ( t ) ; if ( tmv != NULL_TREE && CLASSTYPE_TYPEINFO_VAR ( tmv ) != NULL_TREE ) { tree na , ti_decl = CLASSTYPE_TYPEINFO_VAR ( tmv ) ; na = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , NULL_TREE ) ; decl_attributes ( & ti_decl , na , <NUM_LIT> ) ; } for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = DECL_CHAIN ( member )

) if ( TREE_CODE ( member ) == FUNCTION_DECL ) {


<s> unsigned A15SDOptimizer :: createImplicitDef ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL ) { Register Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Out ) ; return Out


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; uint64_t Imm64 ; if ( ! isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) ) return false ; if ( isUInt < <NUM_LIT> > ( Imm64 ) ) return false ; SDLoc Loc ( N ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; unsigned NumOfLeadingZeros = countLeadingZeros ( Imm64 ) ; if ( NumOfLeadingZeros != <NUM_LIT> ) Imm64 |= maskLeadingOnes < uint64_t > ( NumOfLeadingZeros ) ; unsigned MB , ME ; if ( ! isRunOfOnes64 ( Imm64 , MB , ME ) ) return false ; unsigned OnesOnLeft = ME +


<s> Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) , MI . getOperand ( OpNo - <NUM_LIT> ) ) ; const Align OffsetAlign ( getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || ! isAligned ( OffsetAlign , Offset ) ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II

, DL , OffsetBitSize == <NUM_LIT> ? & NewImm : nullptr ) ;


<s> SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , SrcVT ) ) , DAG . getConstant ( BytesLeft , SizeVT ) , Align , isVolatile , AlwaysInline , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Results [ <NUM_LIT> ] , Results . size


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false ,


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget -> isTarget64BitLP64 ( ) ?


<s> Value * <ISA_LIT>IREmitter :: visitVLD3LN_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> if ( REGNO ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) != SP_REGNO ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; return INTVAL ( XEXP ( SET_SRC ( pat


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getABI ( ) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI . IsN64 ( ) ? <NUM_LIT> : ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ? <NUM_LIT>


<s> inline static <STR_LIT> A64InvertCondCode ( <STR_LIT> CC ) { return static_cast < <STR_LIT> > ( static_cast < unsigned >


<s> return ( __m128d ) __builtin_ia32_cmpneqpd ( ( __v2df ) __A ,


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo


<s> SLL = <STR_LIT> ; LUi = <STR_LIT> ; } InstSeqLs SeqLs ; if ( LastInstrIsADDiu | ! Imm ) GetInstSeqLsADDiu ( Imm , Size , SeqLs ) ; else GetInstSeqLs ( Imm , Size , SeqLs


<s> static SDValue LowerCTTZ ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) ) { assert ( ST -> hasNEON ( ) ) ; SDValue X = N -> getOperand ( <NUM_LIT> ) ; SDValue NX = DAG . getNode ( <STR_LIT> , dl , VT , getZeroVector ( VT , DAG , dl ) , X ) ; SDValue LSB = DAG . getNode ( <STR_LIT> , dl , VT , X , NX ) ; EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; SDValue Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Bits ) ; } if ( ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) && ( N -> getOpcode ( ) == <STR_LIT> ) ) { unsigned NumBits = ElemTy . getSizeInBits ( ) ; SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinus1 , CTLZ ) ; } SDValue Bits ; if ( ElemTy == <STR_LIT> ) { SDValue FF = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , FF ) ; } else { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo (


<s> return Ctx . getXCOFFSection ( <STR_LIT> , SectionKind :: getText ( ) , XCOFF :: CsectProperties ( XCOFF ::

XMC_PR , XCOFF :: XTY_ER ) ) -> getQualNameSymbol ( ) ;


<s> if ( ( e . flag & FUNC_DISINTERRUPT ) && ! ( e . used & FUNC_DISINTERRUPT ) ) warning ( <NUM_LIT> , <STR_LIT> , s ) ; return


<s> static void mep_insn_dependent_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_mentioned_p ( x , * pinsn ) ) * pinsn


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP , PtrVT ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SaveSP = Op . getOperand ( <NUM_LIT>


<s> tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < <NUM_LIT> || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < <NUM_LIT> && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < <NUM_LIT> && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true ) ) regno = BX_REG ; else if ( ! ( regparm == <NUM_LIT> && static_chain_p ) && ix86_save_reg ( SI_REG , true ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx insn = emit_insn ( gen_push ( sr ->


<s> static unsigned getFixupKindNumBytes ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case


<s> else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass


<s> return __builtin_aarch64_nearbyintv2sf ( __a )


<s> Relocation :: Type getCopyRelType ( ) const { return


<s> int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( unsigned ) ( ~ i ) < <NUM_LIT> ) return <STR_LIT> ; if ( ( unsigned ) i < <NUM_LIT> ) return <STR_LIT> ; if ( i >= - <NUM_LIT> && i < <NUM_LIT> ) return <STR_LIT> ; if ( ( unsigned ) i < <NUM_LIT> ) return <STR_LIT> ; if ( i >= - <NUM_LIT> && i < <NUM_LIT> ) return <STR_LIT> ; } if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; case HImode : if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( i == <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) i < <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) ~ i < <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) i < <NUM_LIT> ) return <STR_LIT> ; } return <STR_LIT> ; case QImode : if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { int i = INTVAL ( operands [ <NUM_LIT>


<s> int RegNodeEscapeIndex = escapeRegNode ( F ) ; FuncInfo . EHRegNodeEscapeIndex = RegNodeEscapeIndex ; int CurState = <NUM_LIT> ; SmallPtrSet < BasicBlock * , <NUM_LIT> > ExceptBlocks ; for ( BasicBlock & BB : F ) { for ( auto I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ++ I ) { if ( auto * CI = dyn_cast < CallInst > ( I ) ) { auto * Intrin = dyn_cast < IntrinsicInst > ( CI ) ; if ( Intrin ) { continue ; } insertStateNumberStore ( RegNode , CI , - <NUM_LIT> ) ; } else if ( auto * II = dyn_cast < InvokeInst > ( I ) ) { LandingPadInst * LPI = II -> getUnwindDest ( ) -> getLandingPadInst ( ) ; auto InsertionPair = FuncInfo . LandingPadStateMap . insert ( std :: make_pair ( LPI , CurState ) ) ; auto Iter = InsertionPair . first ; int & State = Iter -> second ; bool Inserted = InsertionPair . second ; if ( Inserted ) { auto * EHActions = cast < IntrinsicInst > ( LPI -> getNextNode ( ) ) ; SmallVector < std :: unique_ptr < ActionHandler > , <NUM_LIT> > ActionList ; parseEHActions ( EHActions , ActionList ) ; assert ( ! ActionList . empty ( ) ) ; CurState += ActionList . size


<s> return MBB . isEHPad ( ) || MBB . hasAddressTaken ( ) || &

MBB == & MBB . getParent ( ) -> front ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [ i

] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>CC ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>CC , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG ,


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; bool HasFP = hasFP ( MF ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int64_t FPDelta = <NUM_LIT> ; if ( IsWin64Prologue ) { assert ( ! MFI . hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI <


<s> case MODE_XI : case MODE_OI : case MODE_TI : scalar_mode = GET_MODE_INNER ( mode ) ; break ; default : gcc_unreachable ( ) ; } if ( evex_reg_p && ! TARGET_AVX512VL && GET_MODE_SIZE ( mode ) < <NUM_LIT> ) { if ( memory_operand ( operands [ <NUM_LIT> ] , mode ) || memory_operand ( operands [ <NUM_LIT> ] , mode ) ) gcc_unreachable ( ) ; size = <NUM_LIT> ; switch ( type ) { case opcode_int : if ( scalar_mode == E_HFmode || scalar_mode == E_BFmode ) opcode = ( misaligned_p ? ( TARGET_AVX512BW ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; break ; case opcode_float : opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; break ; case opcode_double : opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; break ; } } else if ( SCALAR_FLOAT_MODE_P ( scalar_mode ) ) { switch ( scalar_mode ) { case E_HFmode : case E_BFmode : if ( evex_reg_p ) opcode = ( misaligned_p ? ( TARGET_AVX512BW ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else opcode = ( misaligned_p ? ( TARGET_AVX512BW ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; break ; case E_SFmode : opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; break ; case E_DFmode : opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; break ; case E_TFmode : if ( evex_reg_p ) opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; else opcode = misaligned_p ? <STR_LIT> : <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else if ( SCALAR_INT_MODE_P ( scalar_mode ) ) { switch ( scalar_mode ) { case E_QImode : if ( evex_reg_p ) opcode = ( misaligned_p ? ( TARGET_AVX512BW ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else opcode = ( misaligned_p ? ( TARGET_AVX512BW ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; break ; case E_HImode : if ( evex_reg_p ) opcode = ( misaligned_p ? (


<s> FunctionPass * llvm :: create<ISA_LIT>CompressJumpTablesPass ( ) { return new <ISA_LIT>CompressJumpTables (


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( SPE_HIGH_REGNO_P ( regno ) ) return regno - FIRST_SPE_HIGH_REGNO + <NUM_LIT> ; if ( ( format == <NUM_LIT> && write_symbols != DWARF2_DEBUG ) || format == <NUM_LIT> ) return regno ; if ( regno <= <NUM_LIT> ) return regno ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO


<s> if ( TRI -> hasBasePointer ( MF ) ) { unsigned BasePtr = TRI -> getBaseRegister ( ) ; if ( STI . isTarget64BitILP32 ( ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr


<s> unsigned DstScalarBits = DstVT . getScalarSizeInBits ( ) ; unsigned Scale = DstScalarBits / SrcScalarBits ; assert ( SrcScalarBits < DstScalarBits && <STR_LIT> ) ; assert ( SrcVT . getVectorNumElements ( ) >= NumDstElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumDstElts ; i ++ ) { Mask . push_back (


<s> if ( DECL_P ( exp ) && TREE_CODE ( exp ) == FUNCTION_DECL && TREE_PUBLIC ( exp ) && DECL_ONE_ONLY ( exp ) && ! DECL_EXTERNAL ( exp ) && DECL_DECLARED_INLINE_P ( exp ) ) return false ; return default_binds_local_p_1 ( exp , <NUM_LIT> )


<s> if ( FenceOrdering == AtomicOrdering :: SequentiallyConsistent && FenceSSID == SyncScope :: System ) { if ( Subtarget . hasMFence ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; return emitLockedStackOp ( DAG , Subtarget , Chain , dl ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand (


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , true ,

false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> return __builtin_mve_vcaddq_rot270_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b ,


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , FS


<s> Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; Need0FPrefix = true ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } if ( Need0FPrefix ) EmitByte ( <NUM_LIT> , CurByte , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT>


<s> return ( __m128d ) __builtin_ia32_divsd_mask_round ( ( __v2df ) __A , ( __v2df ) __B , (


<s> case <STR_LIT> : { return I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && I -> memoperands ( ) . size ( ) == <NUM_LIT> && GetFrameIndex ( I -> memoperands ( ) . front ( ) ) >= <NUM_LIT> ; } default : return false ; } } ; if ( MI -> getOpcode ( ) != <STR_LIT> || ! IsStackOp ( MI ) ) return false ; if ( MI -> memoperands ( ) . size ( ) == <NUM_LIT> ) return false ; int FI = GetFrameIndex ( MI -> memoperands ( ) . front ( ) ) ; MachineFrameInfo FrameInfo = MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( FI == - <NUM_LIT> || ! FrameInfo . isSpillSlotObjectIndex ( FI ) ) return false ; SmallVector < MachineBasicBlock * > Frontier ; ML -> getExitBlocks (


<s> if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> :


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef CPU ) : MCAsmBackend ( ) , CPU ( CPU ) , MaxNopLength ( ( CPU == <STR_LIT> || CPU == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) { HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT>

&& CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; MVT VT = Op0 . getSimpleValueType ( ) ; if ( ! ( Subtarget . hasDQI ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . hasBWI ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> <ISA_LIT>CC ; if ( isNullConstant ( Op1 ) ) { <ISA_LIT>CC = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return SDValue ( ) ; SDValue KTEST = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op0 ) ; return getSETCC ( <ISA_LIT>CC , KTEST


<s> case V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i ] = d -> perm [ i ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; if ( nelt >= <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; nd . perm [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; } } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt , d -> testing_p ) ) return true ; if ( ! d ->


<s> addPass ( create<ISA_LIT>ModuleISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>16ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine (


<s> HOST_WIDE_INT param_size ; if ( mode == BLKmode ) param_size = int_size_in_bytes ( type ) ; else param_size = GET_MODE_SIZE (


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT>


<s> while ( v -> length ( ) > <NUM_LIT> ) delete v -> pop ( ) ; return


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; assert ( Opc


<s> Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) && ! Subtarget -> slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , VT ) ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; Op = New ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ; if ( EFLAGS . getNode ( ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode


<s> bool <ISA_LIT>AsmParser :: parseDirective<ISA_LIT> ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot (


<s> case MCK_F32 : if ( Op . isReg ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_I32 : if ( Op . isReg ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_F128 : if ( Op . isReg ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_VM512 : if ( Op . isReg ( ) && <STR_LIT>


<s> RegNo = isGP64bit ( ) ? Reg . getGPR64Reg ( ) : Reg . getGPR32Reg ( ) ; if ( RegRange ) { if ( RegNo == <STR_LIT> ) { Regs . push_back ( RegNo ) ; } else { unsigned TmpReg = PrevReg + <NUM_LIT> ; while ( TmpReg <= RegNo ) { if ( ( TmpReg < <STR_LIT> ) || ( TmpReg > <STR_LIT> ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } PrevReg = TmpReg ; Regs . push_back ( TmpReg ++ ) ; } } RegRange = false ; } else { if ( ( PrevReg == <STR_LIT> ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ( ( RegNo < <STR_LIT> ) || ( RegNo > <STR_LIT> ) ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ( PrevReg != <STR_LIT> ) && ( RegNo != PrevReg + <NUM_LIT> ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) { Error ( E , <STR_LIT>


<s> EVT VT = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut . getNode ( )


<s> DenseMap < Instruction * , Instruction * > NewPredicates ; for ( auto * I : MaskedInsts ) { <STR_LIT> ID = I -> getIntrinsicID ( ) ; unsigned PredOp = ID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto * Predicate = dyn_cast < Instruction > ( I -> getArgOperand ( PredOp ) ) ; if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; VectorType * VecTy = getVectorType ( I ) ; Value * NumElements = ComputeElements ( TripCount , VecTy ) ; if ( ! NumElements ) continue ; if ( ! isTailPredicate ( Predicate , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; Predicates . insert ( Predicate ) ; IRBuilder < > Builder ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( NumElements , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( cast < Instruction > ( Predicate ) ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VecTy -> getNumElements ( ) ) ; <STR_LIT> VCTPID ; switch ( VecTy -> getNumElements ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; } Function * VCTP = <STR_LIT> ( M , VCTPID ) ; Value * TailPredicate = Builder . CreateCall ( VCTP , Processed ) ; Predicate -> replaceAllUsesWith ( TailPredicate ) ; NewPredicates [ Predicate ] = cast < Instruction > ( TailPredicate ) ; Value * Remaining = Builder . CreateSub ( Processed , Factor ) ; Processed -> addIncoming ( Remaining , L -> getLoopLatch ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Processed << <STR_LIT> << <STR_LIT> << * TailPredicate << <STR_LIT> ) ; } Cleanup ( NewPredicates , Predicates , L ) ; return


<s> if ( GET_CODE ( addr ) != PLUS || ! REG_P ( XEXP ( addr , <NUM_LIT> ) ) || ! REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) return false ; if ( ISA_HAS_LBX && mode == QImode


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer . EndCOFFSymbolDef ( ) ; S -> setAbsolute ( ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer . EmitAssignment ( S , MCConstantExpr :: Create ( int64_t

( <NUM_LIT> ) , MMI -> getContext ( ) ) ) ;


<s> case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_26_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC16_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_CALL16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_DISP ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_OFST ; break ; case


<s> case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; } Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2Base ( ) || ! Subtarget -> hasFP64 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ) return false ; break ; } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = nullptr ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { if ( Opc == <STR_LIT>


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isSingleFloat ( ) ) for ( unsigned FReg = ( <STR_LIT> ) + <NUM_LIT> ; FReg < <STR_LIT> ;

FReg += <NUM_LIT> ) Reserved . set ( FReg ) ;


<s> unsigned NumSubRegElts = <NUM_LIT> / InSVT . getSizeInBits ( ) ; EVT SubRegVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubRegElts ) ; SmallVector < SDValue , <NUM_LIT> > SubVecs ( NumSubRegs ) ; APInt Mask = APInt :: getLowBitsSet ( InSVT . getSizeInBits ( ) , OutSVT . getSizeInBits ( ) ) ; SDValue MaskVal = DAG . getConstant ( Mask , DL , SubRegVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubRegs ; i ++ ) { SDValue Sub = DAG . getNode ( <STR_LIT> , DL , SubRegVT , In , DAG . getIntPtrConstant ( i * NumSubRegElts , DL ) ) ; SubVecs [ i ] = DAG . getNode ( <STR_LIT> ,


<s> Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal )


<s> if ( epilogue_completed ) { if ( regno == LR_REGNUM ) return <NUM_LIT> ; if ( aarch64_simd_decl_p ( cfun -> decl ) && FP_SIMD_SAVED_REGNUM_P ( regno ) )


<s> SF = <STR_LIT> ; XOF = true ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; XOF = true ; OZF = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } ; CCV = getSF ( SF ) ; if ( XOF ) CCV = Builder . CreateXor ( CCV , getSF ( <STR_LIT> ) ) ; if ( OZF ) CCV = Builder . CreateOr ( CCV , getSF ( <STR_LIT> ) ) ; if ( Inv ) CCV = Builder . CreateNot (


<s> SDNode * <ISA_LIT>SEDAGToDAGISel :: selectAddESubE ( unsigned MOp , SDValue InFlag , SDValue CmpLHS , DebugLoc DL , SDNode * Node ) const { unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; SDNode * AddCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue (


<s> SDValue In1 = Op . getOperand ( <NUM_LIT> ) ; SDValue In2 = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = In2 . getValueType ( ) ; if ( SrcVT . bitsLT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 ) ; else if ( SrcVT . bitsGT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; EVT VecVT ; EVT EltVT ; uint64_t EltMask ; SDValue VecVal1 , VecVal2 ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { EltVT = <STR_LIT> ; VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { EltVT = <STR_LIT> ; VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG


<s> bool HasFastHOps = Subtarget . hasFastHorizontalOps ( ) ; return ! IsSingleSource || IsOptimizingSize


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , CalleeReg , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler )


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == &


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned IsToVec = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( IsToVec ) { DecodeFPR128RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; }


<s> SDValue Trmp = Op . getOperand ( <NUM_LIT> ) ; SDValue FPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; unsigned AS = <NUM_LIT> ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) , AS ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args


<s> rtx op1 = operands [ <NUM_LIT> ] ; rtx condition ; if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) loongarch_emit_float_compare ( & code , & op0 , & op1 ) ; else loongarch_emit_int_compare ( & code , & op0 , &


<s> unsigned <ISA_LIT>TTIImpl :: getVectorTruncCost ( Type * SrcTy , Type * DstTy ) { assert ( SrcTy -> isVectorTy ( ) && DstTy -> isVectorTy ( ) ) ; assert ( SrcTy -> getPrimitiveSizeInBits ( ) > DstTy -> getPrimitiveSizeInBits ( ) && <STR_LIT> ) ; assert ( SrcTy -> getVectorNumElements ( ) == DstTy -> getVectorNumElements ( ) && <STR_LIT> ) ; unsigned NumParts = getNumberOfParts ( SrcTy ) ; if ( NumParts <= <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; unsigned Log2Diff = getElSizeLog2Diff ( SrcTy , DstTy ) ; unsigned VF = SrcTy -> getVectorNumElements ( ) ; for ( unsigned P = <NUM_LIT> ; P < Log2Diff ; ++ P ) { if ( NumParts > <NUM_LIT>


<s> assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsByteShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1


<s> if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! IsShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( ( Shamt != SMPos0 ) || ( SMPos0 + SMSize0 > ValTy . getSizeInBits ( ) ) ) return


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) ) flags |= SECTION_BSS ; return


<s> for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) { Modified |= combineMemAluInBasicBlock ( & * MFI ) ; } return


<s> static DecodeStatus DecodeVecShiftR16Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm


<s> if ( Subtarget . hasSSE41 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue Curr = In ; MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getVectorElementType ( ) != <STR_LIT> ) { Curr = DAG . getNode ( <STR_LIT> , dl , CurrVT , DAG . getUNDEF ( CurrVT ) , Curr ) ; MVT CurrSVT = <STR_LIT> ( CurrVT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; CurrVT = <STR_LIT> ( CurrSVT , CurrVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Curr = DAG . getBitcast ( CurrVT , Curr ) ; } SDValue SignExt = Curr ; if ( CurrVT != InVT ) { unsigned SignExtShift = CurrVT . getVectorElementType ( ) . getSizeInBits ( ) - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr , DAG . getConstant ( SignExtShift , dl , <STR_LIT> ) ) ; } if ( CurrVT == VT ) return SignExt ; if ( VT == <STR_LIT> && CurrVT == <STR_LIT> ) { SDValue Sign = DAG . getNode ( <STR_LIT> , dl , CurrVT , Curr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext = DAG . getVectorShuffle ( CurrVT , dl , SignExt , Sign

, { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> } if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += TARGET_MIPS16 ? <NUM_LIT> : <NUM_LIT> ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_P ( insn ) && INSN_CODE ( insn ) >= <NUM_LIT> ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY : case


<s> char loop_lab [ <NUM_LIT> ] , end_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( end_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = reg2 ; xops [ <NUM_LIT> ] = gen_rtx_REG ( BImode


<s> addPass ( create<ISA_LIT>PreEmitPeepholePass ( ) ) ; addPass ( create<ISA_LIT>ExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass

( create<ISA_LIT>EarlyReturnPass ( ) ) ;


<s> if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ; return ( countLeadingZeros ( Chunk ) + CountTrailingOnes_64 (


<s> void setArgRegsSaveSize ( unsigned s ) { ArgRegsSaveSize =


<s> ExpectedIndex += ExpectedIndexStride ; for ( unsigned n = <NUM_LIT> ; n < CheckStride && I != End ; ++ n , ++ I ) ; } return true


<s> static inline SDValue getPTrue ( SelectionDAG & DAG , SDLoc DL , EVT VT , <STR_LIT> Pattern ) { return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; SchedModel . init ( & ST ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; const MachineOperand *


<s> } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( is64Bit ( ) ) { if ( F && F -> hasFnAttribute ( Attribute ::


<s> } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = isStackAligned ? <STR_LIT> : <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( )


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; if ( CPU . empty ( )


<s> SDLoc dl ( Op ) ; SDNode * N = Op . getNode ( ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Value = N -> getOperand ( <NUM_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; FPHalfs = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPHalfs , FPHalfs , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction (


<s> Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) , Mask -> getType ( ) } , { Ptr

, Builder . getInt32 ( Increment ) , Mask } ) ;


<s> return ( __m64 ) __builtin_arm_waddbhusm ( ( __v4hi ) a , ( __v8qi


<s> if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } Bits >>= <NUM_LIT> ; if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } Bits >>= <NUM_LIT> ; if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } unsigned AddOp = NumBytes > <NUM_LIT> ?


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { if ( Subtarget . isFlavorIntel ( ) ) return new <ISA_LIT>WinTargetAsmInfo ( * this ) ; else switch ( Subtarget


<s> StringRef Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O <<


<s> SDNode * <ISA_LIT>SEDAGToDAGISel :: selectAddESubE ( unsigned MOp , SDValue InFlag , SDValue CmpLHS , DebugLoc DL , SDNode * Node ) const { unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand (


<s> assert ( ! SrcReg2 && <STR_LIT> ) ; bool IsLogical = ( Compare . getDesc ( ) . TSFlags & <STR_LIT> ) != <NUM_LIT> ; return Value == <NUM_LIT> && ! IsLogical && removeIPMBasedCompare ( Compare , SrcReg , MRI ,


<s> } case GATHER : { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getGatherNode ( IntrData -> Opc0 , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case SCATTER : { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getScatterNode ( IntrData -> Opc0 , Op , DAG , Src , Mask , Base , Index , Scale , Chain ) ; } case PREFETCH : { SDValue Hint = Op . getOperand ( <NUM_LIT> ) ; unsigned HintVal ; if ( dyn_cast < ConstantSDNode > ( Hint ) == nullptr || ( HintVal = dyn_cast < ConstantSDNode > ( Hint ) -> getZExtValue ( ) ) > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned Opcode = ( HintVal ? IntrData -> Opc1 : IntrData -> Opc0 ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getPrefetchNode ( Opcode , Op , DAG , Mask , Base , Index , Scale , Chain ) ; } case RDTSC


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> default : return SDValue ( ) ; } SDValue fence = atomic . getOperand ( <NUM_LIT> ) ; if ( fence . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; switch ( atomic . getOpcode ( ) ) { case <STR_LIT> : return DAG . UpdateNodeOperands ( atomic , fence . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . UpdateNodeOperands ( atomic , fence . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT>


<s> return new <ISA_LIT>SETargetLowering ( TM , STI


<s> for ( const auto & MI : Pred -> terminators ( ) ) { if ( ! MI . isBranch ( ) || MI . isIndirectBranch ( ) ) return false ; for ( ConstMIBundleOperands OP ( MI ) ; OP . isValid ( ) ; ++ OP ) { if ( OP -> isJTI (


<s> void <ISA_LIT>InstPrinter :: printU3ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned int Value = MI -> getOperand


<s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; bool NeedsWinCFI = needsWinCFI ( MF ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsWinCFI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) { static const char CFIInst [ ] = { dwarf :: DW_CFA_val_expression , <NUM_LIT> , <NUM_LIT> , static_cast < char > ( unsigned ( dwarf :: DW_OP_breg18 ) ) , static_cast < char > ( - <NUM_LIT> ) & <NUM_LIT> , } ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createEscape ( nullptr , StringRef ( CFIInst , sizeof ( CFIInst ) ) ) ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> :


<s> __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp .


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: ParseShiftExtend ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; std :: string LowerID = IDVal . lower ( ) ; <STR_LIT> Spec = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Spec == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S , E ; S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Spec != <STR_LIT> && Spec != <STR_LIT> && Spec != <STR_LIT> && Spec != <STR_LIT> && Spec != <STR_LIT> ) { if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: EndOfStatement ) || Parser . getTok ( ) . is ( AsmToken :: RBrac ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateShiftExtend ( Spec , <NUM_LIT> , true , S , E ) ) ; return MatchOperand_Success


<s> break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( dyn_cast < ConstantFP > ( CallOperandVal ) ) { weight =


<s> } Register Reg = MRI -> createVirtualRegister ( UnfoldedRC ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; bool Unfolded = TII -> unfoldMemoryOperand ( MF , MI , Reg , true , false , NewMIs ) ; ( void ) Unfolded ; assert ( Unfolded && <STR_LIT> ) ; for ( auto * NewMI : NewMIs ) MBB . insert ( MI . getIterator ( ) , NewMI ) ; if ( MI . isCandidateForCallSiteEntry ( ) ) MF . eraseCallSiteInfo ( & MI ) ; MI . eraseFromParent ( ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto * NewMI : NewMIs ) { NewMI -> dump ( ) ; dbgs ( ) << <STR_LIT> ; } } )


<s> static const char * getRegisterName ( unsigned RegNo ) { return <ISA_LIT>InstPrinter :: getRegisterName ( RegNo )


<s> static DecodeStatus DecodeG8RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , XRegs


<s> if ( REGNO ( reg ) == TP_REGNO || REGNO ( reg ) == GP_REGNO ) if ( mep_interrupt_p ( ) ) return NULL_RTX ; if ( ! cfun -> machine -> reg_save_slot [ REGNO


<s> gcc_assert ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { rtx if_then_else_rtx = SET_SRC ( body ) ; if ( GET_CODE ( if_then_else_rtx ) == IF_THEN_ELSE ) return XEXP (


<s> register_pass ( make_pass_sh_treg_combine ( g , true , <STR_LIT> ) , PASS_POS_INSERT_AFTER , <STR_LIT> , <NUM_LIT> ) ; register_pass ( make_pass_sh_optimize_sett_clrt ( g , <STR_LIT> ) , PASS_POS_INSERT_BEFORE ,