<s> bool <ISA_LIT>LegalizerInfo :: legalizeCTPOP ( MachineInstr & MI , MachineRegisterInfo & MRI , LegalizerHelper & Helper ) const { if ( ! ST -> hasNEON ( ) || MI . getMF ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) return false ; MachineIRBuilder & MIRBuilder = Helper . MIRBuilder ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Val ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; assert ( Ty == MRI . getType ( Dst ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) Val = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Val ) . getReg ( <NUM_LIT> ) ; const LLT V8S8 = LLT :: vector ( <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; Val = MIRBuilder . buildBitcast ( V8S8 , Val ) . getReg ( <NUM_LIT> ) ; auto CTPOP = MIRBuilder . buildCTPOP ( V8S8 , Val ) ; auto UADDLV = MIRBuilder . buildIntrinsic ( <STR_LIT> , { LLT :: scalar ( <NUM_LIT> ) } , false ) . addUse ( CTPOP . getReg ( <NUM_LIT> ) ) ; if ( Size == <NUM_LIT> ) MIRBuilder . buildZExt ( Dst


<s> return ( vector unsigned char ) __builtin_altivec_vsrb ( ( vector signed char ) a1 , ( vector


<s>
void
<ISA_LIT>ATTAsmPrinter
::
printPICJumpTableSetLabel
(
unsigned
uid
,
const
MachineBasicBlock
*
MBB
)
const
{
if
(
!
TAI
->
getSetDirective
(
)
)
return
;
if
(
Subtarget
->
isPICStyleGOT
(
)
)
return
;
O
<<
TAI
->
getSetDirective
(
)
<<
' '
<<
TAI
->
getPrivateGlobalPrefix
(
)
<<
getFunctionNumber


<s> if ( ! SplatVal ) return false ; if ( SplatVal -> getSExtValue ( ) != ( <NUM_LIT> << Scale ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Mask = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Mask . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = dyn_cast < ConstantSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ; if ( ! SplatVal ) return false ; if ( SplatVal -> getZExtValue ( )


<s> if ( ! canWidenShuffleElements ( Mask , WidenedMask ) ) return SDValue ( ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; bool IsV1Zero = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsV2Zero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( ! IsV1Zero && ! IsV2Zero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue


<s> if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; GISelCSEAnalysisWrapper & Wrapper = getAnalysis < GISelCSEAnalysisWrapperPass > ( ) . getCSEWrapper ( ) ; auto * CSEInfo = & Wrapper . get ( TPC . getCSEConfig ( ) ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( )


<s> static unsigned HOST_WIDE_INT ix86_asan_shadow_offset ( void ) { return SUBTARGET_SHADOW_OFFSET


<s> if ( __B >= <NUM_LIT> && __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) lshift = ( __v8hu ) vec_splat_s16 ( __B ) ; else lshift = vec_splats ( ( unsigned short ) __B ) ; result = vec_sl ( ( __v8hi ) __A , lshift ) ; } return ( __m128i


<s> return TargetTriple . isOSDragonFly ( )


<s> PM . add ( create<ISA_LIT>BranchSelectionPass ( ) ) ; return false


<s> return ( uint64x1_t ) __builtin_neon_vextdi ( ( int64x1_t ) __a , (


<s> assert ( Op . getSimpleValueType ( ) . isVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOP ( Op , Subtarget


<s> unsigned Opc = <NUM_LIT> ; bool NeedTrunc = false ; uint64_t Mask = <NUM_LIT> ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op0Reg = emitIntExt ( RetVT , Op0Reg , <STR_LIT> , false ) ; Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg


<s> return isLegalMaskedLoadStore ( DataType ,


<s> assert ( std :: is_sorted ( MI -> begin ( ) + OpNum , MI -> end ( ) , [ & ] ( const MCOperand & LHS , const MCOperand & RHS ) { return MRI . getEncodingValue ( LHS . getReg ( ) ) < MRI . getEncodingValue ( RHS . getReg ( ) ) ; } ) ) ; } O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O <<


<s> return ( __m256 ) __builtin_ia32_cvtdq2ps256_mask ( ( __v8si ) __A , (


<s> const auto & Begin = Indices . begin ( ) ; const auto & Mid = Indices . begin ( ) + Indices . size ( ) / <NUM_LIT> ; const auto & End = Indices . end ( ) ; if ( fitsRegularPattern < int > ( Begin , <NUM_LIT> , Mid , <NUM_LIT> , <NUM_LIT> ) ) Wt = Op -> getOperand ( <NUM_LIT> ) ; else if ( fitsRegularPattern < int > ( Begin , <NUM_LIT> , Mid , Indices . size ( ) , <NUM_LIT> ) ) Wt


<s> Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; SDValue CCReg = End .


<s> } if ( getABI ( ) . IsN32 ( ) ) { MCSymbol * GPSym = MCA . getContext ( ) . getOrCreateSymbol ( <STR_LIT> ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( GPSym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( GPSym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; emitRX ( <STR_LIT> , GPReg , MCOperand :: createExpr ( HiExpr ) , SMLoc ( ) , & STI ) ; emitRRX ( <STR_LIT> , GPReg , GPReg , MCOperand :: createExpr ( LoExpr ) , SMLoc ( ) , & STI ) ; return ; } const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create (


<s> BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign ,


<s> return new <ISA_LIT>AddressTypePromotion


<s> return ! ( PersonalityLocs . empty ( ) && PersonalityIndexLocs . empty


<s> static DecodeStatus DecodeThumbAddrModeIS ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return


<s> if ( ix86_red_zone_used ) gcc_unreachable ( ) ; ix86_output_indirect_branch ( call_op , <STR_LIT> , true ) ; } else output_asm_insn ( <STR_LIT> ,


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N


<s> SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { HasGPSaveArea = true ; GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - get<ISA_LIT>RegisterNumbering ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { HasGPSaveArea = true ; int FI = PFI


<s> unsigned <ISA_LIT>16InstrInfo :: GetAnalyzableBrOpc ( unsigned Opc )


<s> KnownBits Known ; APInt DemandedMask ( APInt :: getSignMask ( SrcVT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Src , DemandedMask , Known , TLO ) ) { DCI . AddToWorklist ( Src . getNode ( ) ) ; DCI . CommitTargetLoweringOpt ( TLO


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget -> getTargetTriple ( ) . getObjectFormat ( ) ==

Triple :: MachO && Subtarget -> is64Bit ( ) ;


<s> static const MachineInstr * getBundledDefMI ( const TargetRegisterInfo * TRI , const MachineInstr * MI , unsigned Reg , unsigned & DefIdx , unsigned & Dist ) { Dist = <NUM_LIT> ; MachineBasicBlock :: const_iterator I = MI


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , MOK_TYPE ) . Cases ( <STR_LIT> , <STR_LIT> , MOK_SIZEOF

) . Cases ( <STR_LIT> , <STR_LIT> , MOK_LENGTHOF ) . Default ( MOK_INVALID ) ;


<s> if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ) return LD -> getExtensionType ( ) == <STR_LIT> && Op . getValueType


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs (


<s> assert ( false && <STR_LIT> ) ; return NULL ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , true , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , true , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , false , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , false , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case


<s> uint64_t <ISA_LIT>GNUInfo :: abiPageSize ( ) const { return


<s> if ( Flags . isByVal ( ) && VA . isMemLoc ( ) ) { const unsigned Size = alignTo ( Flags . getByValSize ( ) ? Flags . getByValSize ( ) : PtrByteSize , PtrByteSize ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , VA . getLocMemOffset ( ) , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; continue ; } if ( Flags . isByVal ( ) ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; const MCPhysReg ArgReg = VA . getLocReg ( ) ; const <ISA_LIT>FrameLowering * FL = Subtarget . getFrameLowering ( ) ; if ( Flags . getNonZeroByValAlign ( ) > PtrByteSize ) report_fatal_error ( <STR_LIT> ) ; const unsigned StackSize = alignTo ( Flags . getByValSize ( ) , PtrByteSize ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( StackSize , mapArgRegToOffsetAIX ( ArgReg , FL ) , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; const TargetRegisterClass * RegClass = Is<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; auto HandleRegLoc = [ & , RegClass , LocVT ] ( const MCPhysReg PhysReg , unsigned Offset ) { const unsigned VReg = MF . addLiveIn ( PhysReg , RegClass ) ; SDValue CopyFrom = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; SDValue Store = DAG . getStore ( CopyFrom . getValue ( <NUM_LIT> ) , dl , CopyFrom , DAG . getObjectPtrOffset ( dl , FIN , Offset ) , MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) ) ; MemOps . push_back ( Store ) ; } ; unsigned Offset = <NUM_LIT> ; HandleRegLoc ( VA . getLocReg ( ) , Offset ) ; Offset += PtrByteSize ; for ( ; Offset != StackSize && ArgLocs [ I ] . isRegLoc ( ) ; Offset += PtrByteSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; const CCValAssign RL = ArgLocs [ I ++ ] ; HandleRegLoc ( RL . getLocReg ( ) , Offset ) ; } if ( Offset != StackSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; assert ( ArgLocs [ I ] . isMemLoc ( ) && <STR_LIT> ) ; ++ I ; } continue ; } EVT ValVT = VA .


<s> if ( TARGET_64BIT ) fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ; else if ( ISA_HAS_MXHC1 ) { fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg + TARGET_LITTLE_ENDIAN ] , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 't' ) { fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 'f' ) { fprintf ( asm_out_file , <STR_LIT> , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg + <NUM_LIT> ] ) ; } else { fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names


<s> case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT , R , BaseShAmt , DAG ) ; } case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT , R , BaseShAmt , DAG ) ; } case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT , R , BaseShAmt , DAG ) ; } } } } if ( ! Subtarget -> is64Bit ( ) && ( VT == <STR_LIT> || ( Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) ) && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [ j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ; } switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; } } return SDValue


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = Start ; Op -> EndLoc = End ; return


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>GVSymbol ( const GlobalValue * GV , unsigned char TargetFlags ) { bool isIndirect = Subtarget -> isTargetMachO ( ) && ( TargetFlags & <STR_LIT> ) && Subtarget -> GVIsIndirectSymbol ( GV , TM . getRelocationModel ( ) ) ; if ( ! isIndirect ) return getSymbol ( GV ) ; MCSymbol * MCSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility (

) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) :


<s> DollarIsPC = true ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; AllowAdditionalComments = false ; AllowQuestionAtStartOfIdentifier = true ; AllowDollarAtStartOfIdentifier = true ; AllowAtAtStartOfIdentifier =


<s> int64_t Stride = <NUM_LIT> ; if ( NewIndex . getOpcode ( ) == <STR_LIT> ) Stride = cast < ConstantSDNode > ( NewIndex . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; else if ( NewIndex . getOpcode ( ) == <STR_LIT> && NewIndex . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue RHS = NewIndex . getOperand ( <NUM_LIT> ) ; if ( auto * Shift = dyn_cast_or_null < ConstantSDNode > ( DAG . getSplatValue ( RHS ) ) ) { int64_t Step = ( int64_t ) NewIndex . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; Stride = Step << Shift -> getZExtValue ( ) ; } } if ( Stride == <NUM_LIT> ) return false ; if ( Stride < std :: numeric_limits < int32_t > :: min ( ) || Stride > std :: numeric_limits < int32_t > :: max ( ) ) return false ; const auto & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; unsigned MaxVScale = Subtarget . getMaxSVEVectorSizeInBits ( ) / <STR_LIT> ; int64_t LastElementOffset = IndexVT . getVectorMinNumElements ( ) * Stride * MaxVScale ; if ( LastElementOffset < std :: numeric_limits < int32_t > :: min ( ) || LastElementOffset > std :: numeric_limits < int32_t > :: max ( ) ) return false ; EVT NewIndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ; Index = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , NewIndexVT , DAG . getTargetConstant ( Stride ,


<s> static HOST_WIDE_INT get_probe_interval ( void ) { if ( flag_stack_clash_protection ) return ( HOST_WIDE_INT_1U


<s> Value * IndexBase ; if ( match ( Index , m_Intrinsic < <STR_LIT> > ( m_Value ( IndexBase ) , m_SpecificInt ( <NUM_LIT> ) ) ) ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Align Alignment = BasePtr -> getPointerAlignment ( II . getModule ( ) -> getDataLayout ( ) ) ; Value * Ptr = Builder . CreateGEP ( BasePtrTy -> getPointerElementType ( ) , BasePtr , IndexBase ) ; Type * VecPtrTy = PointerType :: getUnqual ( Ty ) ; Ptr = Builder . CreateBitCast ( Ptr , VecPtrTy ) ; ( void ) Builder . CreateMaskedStore ( Val , Ptr , Alignment , Mask


<s> VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; } else return false ; if ( Subtarget -> isThumb1Only ( ) ) { assert ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Op -> getOpcode ( ) != <STR_LIT> || ! isNonExt ) return false ; auto * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return false ; Offset = Op -> getOperand ( <NUM_LIT> ) ; Base = Op -> getOperand ( <NUM_LIT> ) ; AM = <STR_LIT> ; return


<s> MCSection * <ISA_LIT>WindowsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( Kind . isReadOnly ( ) ) { if ( C ) { Type * Ty = C -> getType ( ) ; SmallString < <NUM_LIT> > COMDATSymName ; if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) { COMDATSymName = <STR_LIT> ; COMDATSymName += scalarConstantToHexString ( C ) ; } else if ( const auto * VTy = dyn_cast < VectorType > ( Ty ) ) { uint64_t NumBits = VTy -> getBitWidth ( ) ; if ( NumBits == <NUM_LIT> || NumBits == <NUM_LIT> ) { COMDATSymName = NumBits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; for ( int I = VTy -> getNumElements ( ) - <NUM_LIT> , E = - <NUM_LIT> ; I != E ; -- I ) COMDATSymName += scalarConstantToHexString ( C -> getAggregateElement ( I ) ) ; } } if ( ! COMDATSymName . empty ( ) ) { unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; return getContext ( ) . getCOFFSection ( <STR_LIT> , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } } } return TargetLoweringObjectFile :: getSectionForConstant ( Kind


<s> return DecodeMem ( Inst , insn , Address

, Decoder , true , DecodeIntPairRegisterClass ) ;


<s> static DecodeStatus DecoderGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == <NUM_LIT> || RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder


<s> if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fuseable_ops & ARM_FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , <NUM_LIT> ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } return false


<s> return ( __m256i ) __builtin_ia32_psrlv8si_mask ( ( __v8si ) __X , ( __v8si ) __Y , (


<s> MCSubtargetInfo * <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT , CPU ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT ,


<s> SU -> isScheduleHigh = ( AffectsGrouping || SU -> isUnbuffered ) ; Available . insert


<s> inline unsigned getT2SOImmTwoPartFirst ( unsigned Imm ) { assert ( isT2SOImmTwoPartVal ( Imm ) && <STR_LIT> ) ; unsigned V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( Imm ) ) & Imm ; if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return V ; if ( getT2SOImmValSplatVal ( Imm & <NUM_LIT> ) != - <NUM_LIT> ) return Imm & <NUM_LIT> ; assert ( getT2SOImmValSplatVal ( Imm & <NUM_LIT> ) != - <NUM_LIT>


<s> return MO1 . isIdenticalTo ( MO2 ) && ( ! MO1 . isReg ( )

|| ! TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ;


<s> Count = SizeVal / UBytes ; BytesLeft = SizeVal %


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC != CallingConv :: C && CC != CallingConv :: Fast && CC != CallingConv :: <ISA_LIT>_FastCall && CC != CallingConv :: <ISA_LIT>_64_SysV ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( <ISA_LIT>MFInfo -> getBytesToPopOnReturn ( ) != <NUM_LIT> ) return false ; if ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; computeRegisterProperties (


<s> low = mips_const_insns ( mips_subword ( x , false ) ) ; high = mips_const_insns ( mips_subword ( x , true ) ) ; gcc_assert ( low > <NUM_LIT> && high > <NUM_LIT> ) ; return low


<s> void addMemImm8s4OffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Val = Memory . OffsetImm ? Memory .


<s> if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMemImm ( DAG , DL

, <STR_LIT> , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ;


<s> unsigned Imm ; if ( ! isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Imm ) ) return false ; SDLoc dl ( N ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; unsigned SH , MB , ME ; if ( isRotateAndMask ( Val . getNode ( ) , Imm , false , SH , MB , ME ) ) { Val = Val . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Val , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } if ( isRunOfOnes ( Imm , MB , ME ) && Val . getOpcode ( ) != <STR_LIT> ) { SDValue Ops [ ] = { Val , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } if ( Imm == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return true ; } return


<s> void mips_split_call ( rtx insn , rtx call_pattern ) { emit_call_insn ( call_pattern )


<s> SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>cc ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineBasicBlock * ContBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( ContBB ) ; ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; MBB -> addSuccessor ( ContBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( TrapBB ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TrapBB ) ; MI -> eraseFromParent


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Select = pushAddIntoCmovOfConsts ( N , DAG ) ) return Select ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue V = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N )


<s> int shift = exact_log2 ( GET_MODE_UNIT_SIZE ( mode


<s> int32_t Imm = Memory . OffsetImm -> getValue ( ) ; Inst . addOperand ( MCOperand :: CreateImm ( Imm )


<s> return ( __m128 ) __builtin_ia32_maskloadps ( ( const __v4sf *


<s> REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( x ) ) return - <NUM_LIT> ; r0 = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( exact_real_inverse ( DFmode , & r0 ) && ! REAL_VALUE_NEGATIVE (


<s> static unsigned getPrologueDeath ( MachineFunction & MF , unsigned Reg ) { bool IsLiveIn = MF . getRegInfo ( )


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( *


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT>


<s> assert ( Kind == k_SysReg && <STR_LIT> ) ; return SysReg .


<s> for ( i = <NUM_LIT> ; i != NumElts ; ++ i ) { Val = SVOp -> getMaskElt ( i ) ; if ( Val >= <NUM_LIT> ) break ; } if ( Val >= ( int ) NumElts ) Val -= NumElts - NumLaneElts ; assert ( Val - i >


<s> int gp_reg_size ; int fp_reg_size ; long mask ; long gp_save_offset ; long fp_save_offset ; long gp_sp_offset ; long fp_sp_offset ; int initialized ; int num_gp


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg


<s> AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective =


<s> StringRef <ISA_LIT>IntelInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind ) ) ; return <NUM_LIT>


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set (


<s> case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportLinkage ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget ->


<s> SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple TheTriple ( TT ) ; RM = TheTriple . isOSDarwin ( ) ? Reloc :: PIC_ : Reloc :: DynamicNoPIC ; } X -> initMCCodeGenInfo ( RM ,


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS )


<s> unsigned RegNo = CTX . getRegisterInfo ( ) . getEncodingValue ( Reg ) ; switch ( Reg ) { default : return RegNo ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , IDLoc


<s> FOR_EACH_BB_FN ( bb , fn ) { for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { stmt = gsi_stmt ( gsi ) ; if ( is_gimple_call ( stmt ) ) { called_fn_tree = gimple_call_fndecl ( stmt ) ; if ( called_fn_tree !=


<s> exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned storesuccess = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; if ( isThumb2 ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) ) . addReg ( destlo , RegState :: Define ) . addReg ( desthi , RegState :: Define ) . addReg ( ptr ) ) ; } else { unsigned GPRPair0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) ) . addReg ( GPRPair0 , RegState :: Define ) . addReg ( ptr ) ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; } unsigned StoreLo , StoreHi ; if ( IsCmpxchg ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( i == <NUM_LIT> ? destlo : desthi ) . addReg ( i == <NUM_LIT> ? vallo : valhi ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( exitMBB ) ; BB -> addSuccessor ( i == <NUM_LIT> ? contBB : cont2BB ) ; BB = ( i == <NUM_LIT> ? contBB : cont2BB ) ; } StoreLo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; StoreHi = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( Op1 ) { unsigned tmpRegLo = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op1 ) , tmpRegLo ) . addReg ( destlo ) . addReg ( vallo ) ) . addReg ( NeedsCarry ? <STR_LIT> : <NUM_LIT> , getDefRegState ( NeedsCarry ) ) ; unsigned tmpRegHi = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op2 ) , tmpRegHi ) . addReg ( desthi ) . addReg ( valhi ) ) . addReg ( IsMinMax ? <STR_LIT> : <NUM_LIT> , getDefRegState ( IsMinMax ) ) ; StoreLo = tmpRegLo ; StoreHi = tmpRegHi ; } else


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode3Offset ( SDNode * Op , SDValue N , SDValue & Offset , SDValue & Opc ) { return


<s> unsigned PredCond = LastI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( PredCond != <STR_LIT> && PredCond != <STR_LIT> ) return <NUM_LIT> ; SmallVector < MachineInstr * , <NUM_LIT> > IVars , IOps ; getCanonicalInductionVariable ( L , IVars , IOps ) ; for ( unsigned i = <NUM_LIT> ; i < IVars . size ( ) ; ++ i ) { MachineInstr * IOp = IOps [ i ] ; MachineInstr * IV_Inst = IVars [ i ] ; MachineOperand * IV_Opnd ; const MachineOperand * InitialValue ; if ( ! L -> contains ( IV_Inst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { InitialValue = & IV_Inst -> getOperand ( <NUM_LIT> ) ; IV_Opnd = & IV_Inst -> getOperand ( <NUM_LIT> ) ; } else { InitialValue = & IV_Inst -> getOperand ( <NUM_LIT> ) ; IV_Opnd = & IV_Inst -> getOperand ( <NUM_LIT> ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * IOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * IV_Inst ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * InitialValue << <STR_LIT> ) ; for ( MachineRegisterInfo :: reg_iterator RI = MRI -> reg_begin ( IV_Opnd -> getReg ( ) ) , RE = MRI -> reg_end ( ) ; RI != RE ; ++ RI ) { IV_Opnd = & RI . getOperand ( ) ; bool SignedCmp ; MachineInstr * MI = IV_Opnd -> getParent ( ) ; if ( L -> contains ( MI ) && isCompareEqualsImm ( MI , SignedCmp ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == PredReg ) { OldInsts . push_back ( MI ) ; OldInsts . push_back ( IOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isImm (


<s> case <STR_LIT> : Res = ExpandVectorExtension ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static_assert ( MOSuppressPair < ( <NUM_LIT> << MachineMemOperand :: MOTargetNumBits ) , <STR_LIT> ) ; for ( auto * MM : MI


<s> static unsigned int nds32_function_arg_boundary ( machine_mode mode , const_tree type ) { return ( nds32_needs_double_word_align ( mode , type ) ?


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc


<s> if ( GET_CODE ( ind ) == REG ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( wb && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || GET_CODE ( ind ) == POST_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( wb && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( ind , <NUM_LIT> ) )


<s> const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex (


<s> vmlaq_s8 ( int8x16_t a , int8x16_t b , int8x16_t c ) { int8x16_t result


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( )


<s> static void mep_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { int nsave = <NUM_LIT> - ( get_cumulative_args ( cum ) -> nregs + <NUM_LIT> ) ; if ( nsave > <NUM_LIT> ) cfun -> machine -> arg_regs_to_save = nsave ; * pretend_size = nsave


<s> int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt =


<s> unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT>

, Expr , MCFixupKind ( <STR_LIT> ) ) ) ;


<s> MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel ( MILabel ) ; SM . recordStackMap ( * MILabel , MI ) ; unsigned NumShadowBytes = MI . getOperand ( <NUM_LIT> ) . getImm


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx ,


<s> N = N . getOperand ( <NUM_LIT> ) ; } if ( N . getOpcode ( ) != <STR_LIT> ) return false ; unsigned Opc = N . getOperand ( <NUM_LIT> ) -> getOpcode ( ) ; if ( Opc != <STR_LIT> || ! WasTruncated ) { Op = N . getOperand ( <NUM_LIT> ) ; return ! WasTruncated ; } auto * GA = cast < GlobalAddressSDNode > (


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>WinCOFFObjectWriter (


<s> case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( ) ; else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) MAI = new <ISA_LIT>MCAsmInfoMicrosoftCOFF ( ) ; else if ( TheTriple . isOSBinFormatCOFF ( ) ) MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( ) ; else { assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; MAI = new <ISA_LIT>MCAsmInfoELF (


<s> STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI ->


<s> inline vector signed int vec_cmple ( vector float a1 , vector float a2 ) { return ( vector signed int ) __builtin_altivec_vcmpgefp ( ( vector float ) a1 , ( vector float )


<s> if ( ! CmpBB -> isSuccessor ( Tail ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * Head ) << <STR_LIT> << printMBBReference ( * CmpBB ) << <STR_LIT> << printMBBReference ( * Tail ) << '\n' ) ; ++ NumConsidered ; if ( ! trivialTailPHIs ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumPhiRejs ; return false ; } if ( ! Tail -> livein_empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumPhysRejs ; return false ; } if ( ! CmpBB -> empty ( ) && CmpBB -> front ( ) . isPHI ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumPhi2Rejs ; return false ; } if ( ! CmpBB -> livein_empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumPhysRejs ; return false ; } HeadCond . clear ( ) ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; if ( TII -> analyzeBranch ( * Head , TBB , FBB , HeadCond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( ! TBB || HeadCond . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( ! parseCond ( HeadCond , HeadCmpBBCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( TBB != CmpBB ) { assert ( TBB == Tail && <STR_LIT> ) ; HeadCmpBBCC = <STR_LIT> ( HeadCmpBBCC ) ; } CmpBBCond . clear ( ) ; TBB = FBB = nullptr ; if ( TII -> analyzeBranch ( * CmpBB , TBB , FBB , CmpBBCond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( ! TBB || CmpBBCond . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( ! parseCond ( CmpBBCond , CmpBBTailCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( TBB != Tail ) CmpBBTailCC = <STR_LIT> ( CmpBBTailCC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmpBBCC ) << <STR_LIT> << <STR_LIT> ( CmpBBTailCC ) << '\n' ) ; CmpMI = findConvertibleCompare ( CmpBB ) ; if ( ! CmpMI ) return


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) return SDValue ( ) ; Negate = ! Negate ; return SearchLoopIntrinsic ( N . getOperand ( <NUM_LIT> ) , CC , Imm , Negate ) ; } case <STR_LIT> : { auto * Const = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Const ) return SDValue


<s> assert ( ( isNarrowLoad ( * MBBI ) || isPromotableZeroStoreOpcode ( * MBBI ) ) && <STR_LIT> ) ; MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator E = MI . getParent ( ) -> end ( ) ; if ( ! TII -> isCandidateToMergeOrPair ( MI ) ) return false ; if ( isPromotableZeroStoreOpcode ( MI ) && getLdStRegOp ( MI ) . getReg ( ) != <STR_LIT>


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { if ( memory_operand ( op1 , mode ) ) { if ( TARGET_MIPS16 ) { struct mips_address_info addr ; if ( ! mips_classify_address ( & addr , op1 , mode , false ) ) return false ; } return and_load_operand ( op2 ,


<s> SDNode * V = Vec . getNode ( ) ; unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return


<s> else ISARevision = <NUM_LIT> ; } else { ISARevision = <NUM_LIT> ; if ( P . has<ISA_LIT>5 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>4 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>3 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>2 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>1 ( ) ) ISALevel = <NUM_LIT> ; else llvm_unreachable (


<s> builtin_mode_to_type [ V2DFmode ] [ <NUM_LIT> ] = V2DF_type_node ; builtin_mode_to_type [ V4HImode ] [ <NUM_LIT> ] = V4HI_type_node ; builtin_mode_to_type [ V4SImode ] [ <NUM_LIT> ] = V4SI_type_node ; builtin_mode_to_type [ V4SImode ] [ <NUM_LIT> ] = unsigned_V4SI_type_node ; builtin_mode_to_type [ V4SFmode ] [ <NUM_LIT> ] = V4SF_type_node ; builtin_mode_to_type [ V8HImode ] [ <NUM_LIT> ] = V8HI_type_node ; builtin_mode_to_type [ V8HImode ] [ <NUM_LIT> ] = unsigned_V8HI_type_node ; builtin_mode_to_type [ V16QImode ] [ <NUM_LIT> ] = V16QI_type_node ; builtin_mode_to_type [ V16QImode ] [ <NUM_LIT> ] = unsigned_V16QI_type_node ; tdecl = add_builtin_type ( <STR_LIT> , bool_char_type_node ) ; TYPE_NAME ( bool_char_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , bool_short_type_node ) ; TYPE_NAME ( bool_short_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , bool_int_type_node ) ; TYPE_NAME ( bool_int_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , pixel_type_node ) ; TYPE_NAME ( pixel_type_node ) = tdecl ; bool_V16QI_type_node = rs6000_vector_type ( <STR_LIT> , bool_char_type_node , <NUM_LIT> ) ; bool_V8HI_type_node = rs6000_vector_type ( <STR_LIT> , bool_short_type_node , <NUM_LIT> ) ; bool_V4SI_type_node = rs6000_vector_type ( <STR_LIT> , bool_int_type_node , <NUM_LIT> ) ; bool_V2DI_type_node = rs6000_vector_type ( TARGET_POWERPC64 ? <STR_LIT> : <STR_LIT> , bool_long_type_node , <NUM_LIT> ) ; pixel_V8HI_type_node = rs6000_vector_type ( <STR_LIT> , pixel_type_node , <NUM_LIT> ) ; if ( TARGET_PAIRED_FLOAT ) paired_init_builtins ( ) ; if ( TARGET_SPE ) spe_init_builtins ( ) ; if ( TARGET_EXTRA_BUILTINS ) altivec_init_builtins ( ) ; if ( TARGET_HTM ) htm_init_builtins ( ) ; if ( TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT ) rs6000_common_init_builtins ( ) ; ftype = build_function_type_list ( ieee128_float_type_node , const_str_type_node , NULL_TREE ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_NANQ ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_NANSQ ) ; ftype = build_function_type_list ( ieee128_float_type_node , NULL_TREE ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_INFQ ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_HUGE_VALQ ) ; ftype = builtin_function_type ( DFmode , DFmode , DFmode , VOIDmode , RS6000_BUILTIN_RECIP , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RECIP ) ; ftype = builtin_function_type ( SFmode , SFmode , SFmode , VOIDmode , RS6000_BUILTIN_RECIPF , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RECIPF ) ; ftype = builtin_function_type ( DFmode , DFmode , VOIDmode , VOIDmode , RS6000_BUILTIN_RSQRT , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RSQRT ) ; ftype = builtin_function_type ( SFmode , SFmode , VOIDmode , VOIDmode , RS6000_BUILTIN_RSQRTF , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RSQRTF ) ; mode = ( TARGET_64BIT ) ? DImode : SImode ; ftype = builtin_function_type ( mode , mode , mode , VOIDmode , POWER7_BUILTIN_BPERMD , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , POWER7_BUILTIN_BPERMD ) ; ftype = build_function_type_list ( unsigned_intDI_type_node , NULL_TREE ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_GET_TB ) ; if ( TARGET_64BIT ) ftype = build_function_type_list ( unsigned_intDI_type_node , NULL_TREE


<s> BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( FP64 ) { BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg ,

<STR_LIT> ) ) . addReg ( HiReg ) . addReg ( DstReg , RegState :: Implicit ) ;


<s> static inline const MachineInstrBuilder & AddNoT1CC (


<s> if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT>


<s> SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> isVolatile ( ) , S -> isNonTemporal ( ) , S -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG


<s> if ( LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ; return


<s> Hi32 = DAG . getNode ( opcode , dl , <STR_LIT> , Hi32 ) ; SDValue DstReg64 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ; DstReg64 = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , DstReg64 , Hi32 ) ; DstReg64 = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , DstReg64 , Lo32 ) ; return DstReg64


<s> if ( MEM_VOLATILE_P ( mem [ i ] ) ) return false ; extract_base_offset_in_addr ( mem [ i ] , base + i , offset + i ) ; if ( base [ i ] == NULL_RTX || offset [ i ] == NULL_RTX ) return false ; } rclass = REG_P ( reg [ <NUM_LIT> ] ) && FP_REGNUM_P ( REGNO ( reg [ <NUM_LIT> ] ) ) ? FP_REGS : GENERAL_REGS ; for ( int i = <NUM_LIT> ; i < num_insns ; i ++ ) if ( REG_P ( reg [ i ] ) && FP_REGNUM_P ( REGNO ( reg [ i ] ) ) ) { if ( rclass != FP_REGS ) return false ; } else { if ( rclass != GENERAL_REGS ) return false ; } if ( rclass == GENERAL_REGS && load ) for ( int i = <NUM_LIT> ; i < num_insns - <NUM_LIT> ; i ++ ) if ( reg_mentioned_p ( reg [ i ] , mem [ i ] ) ) return false ; for ( int i = <NUM_LIT> ; i < num_insns - <NUM_LIT> ; i ++ ) if ( ! rtx_equal_p ( base [ i ] , base [ i + <NUM_LIT> ] ) ) return false ; for ( int i = <NUM_LIT> ; i < num_insns ; i ++ ) offvals [ i ] = INTVAL ( offset [ i ] ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; qsort ( offvals , num_insns , sizeof ( HOST_WIDE_INT ) , aarch64_host_wide_int_compare ) ; if ( ! ( offvals [ <NUM_LIT> ] == offvals [ <NUM_LIT> ] + msize && offvals [ <NUM_LIT> ] == offvals [ <NUM_LIT> ] + msize ) ) return false ; if ( offvals [ <NUM_LIT> ] - offvals [ <NUM_LIT> ] >= msize * <NUM_LIT> ) return false ; if ( offvals [ <NUM_LIT> ] % msize != offvals [ <NUM_LIT> ] % msize ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem [ <NUM_LIT> ] ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; return true


<s> if ( UniquedVals [ i ] . getNode ( ) == <NUM_LIT> ) continue ; LeadingZero &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isNullValue ( ) ; LeadingOnes &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isAllOnesValue ( ) ; } if ( LeadingZero ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; if ( OpVal . getNode ( ) == <NUM_LIT> ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( OpVal . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; while ( ValSizeInBytes > ByteSize ) { ValSizeInBytes >>= <NUM_LIT> ; if ( ( ( Value >> ( ValSizeInBytes * <NUM_LIT> ) ) & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) != ( Value & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) ) return SDValue ( ) ; } int MaskVal = SignExtend32 ( Value , ByteSize * <NUM_LIT> ) ; if ( MaskVal == <NUM_LIT>


<s> return ; default : gcc_unreachable ( ) ; } } temp = gen_reg_rtx ( imode ) ; if ( imode == GET_MODE ( same ) ) temp2 = same ; else if ( GET_MODE_SIZE ( imode ) >= UNITS_PER_WORD ) temp2 = simplify_gen_subreg ( imode , same , GET_MODE ( same ) , <NUM_LIT> ) ; else temp2 = lowpart_subreg ( imode , same , GET_MODE ( same ) ) ; emit_move_insn ( temp , temp2 ) ; switch ( vmode ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : mips_emit_move ( target , gen_rtx_VEC_DUPLICATE ( vmode , temp ) ) ; break ; case E_V4SFmode : emit_insn ( gen_msa_splati_w_f_scalar ( target , temp ) ) ; break ; case E_V2DFmode : emit_insn ( gen_msa_splati_d_f_scalar ( target , temp ) ) ; break ; default : gcc_unreachable ( ) ; } } else { emit_move_insn ( target , CONST0_RTX ( vmode ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx temp = gen_reg_rtx ( imode ) ; emit_move_insn ( temp , XVECEXP ( vals , <NUM_LIT> , i ) ) ; switch ( vmode ) { case E_V16QImode : emit_insn ( gen_vec_setv16qi ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V8HImode : emit_insn ( gen_vec_setv8hi ( target , temp , GEN_INT


<s> unsigned Shift = getShiftExtendAmount ( ) ; return getShiftExtendType ( ) == <STR_LIT> && ( Shift == <NUM_LIT> || Shift == <NUM_LIT> || Shift == <NUM_LIT>


<s> return ( ( isa < ConstantSDNode > ( Elt ) && cast < ConstantSDNode > ( Elt ) -> getZExtValue ( ) == <NUM_LIT> ) || ( isa < ConstantFPSDNode > ( Elt ) && cast < ConstantFPSDNode > (

Elt ) -> getValueAPF ( ) . isPosZero ( ) ) ) ;


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) && ! Subtarget -> isTargetWindows ( ) ) return false ; return true


<s> if ( to == CALLER_SAVE_REGS || to == POINTER_REGS ) to = GENERAL_REGS ; if ( from == CALLER_SAVE_REGS || from == POINTER_REGS ) from = GENERAL_REGS ; if ( ( from == GENERAL_REGS && to == STACK_REG ) || ( to == GENERAL_REGS && from == STACK_REG ) ) return regmove_cost -> GP2GP ; if ( to == STACK_REG || from == STACK_REG ) return aarch64_register_move_cost ( mode , from , GENERAL_REGS ) + aarch64_register_move_cost ( mode , GENERAL_REGS , to ) ; if ( GET_MODE_SIZE ( mode ) ==


<s> static inline built_in_function complex_divide_builtin_code ( machine_mode mode ) { gcc_assert ( IN_RANGE ( mode , MIN_MODE_COMPLEX_FLOAT , MAX_MODE_COMPLEX_FLOAT ) ) ; int func = BUILT_IN_COMPLEX_DIV_MIN + mode - MIN_MODE_COMPLEX_FLOAT ; return ( built_in_function ) func


<s> assert ( ImmOp . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = cast < <ISA_LIT>MCExpr > ( ImmOp . getExpr ( ) ) ; unsigned FixupKind ; switch ( Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_LO12 : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_GOT_LO12 : assert ( MemSize == <NUM_LIT> && <STR_LIT> ) ; FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : { static const unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr ::


<s> void AnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const SDNode * CallNode ) { PreAnalyzeCallOperands ( Outs , FuncArgs , CallNode ) ; CCState :: AnalyzeCallOperands ( Outs ,


<s> auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) continue ; if ( User -> getOpcode ( ) == <STR_LIT> || User -> getOpcode ( ) == <STR_LIT> || User -> getOpcode ( ) == <STR_LIT> || User -> getOpcode ( ) == <STR_LIT> ) { SDValue OtherOp = User -> getOperand ( <NUM_LIT> ) ; if ( OtherOp . getNode ( ) == N ) OtherOp = User -> getOperand


<s> StringRef getSymName ( ) const { return SymName


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int FPDiff , const SDLoc & dl ) { if ( ! FPDiff )


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) { addPass ( create<ISA_LIT>OptimizePICCallPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true ; } else return


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) != - <NUM_LIT> ) { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; } else { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT>


<s> const char * arm_mangle_type ( const_tree type ) { if ( TARGET_AAPCS_BASED && lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type


<s> if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; } else { assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; O << * DispSpec . getExpr ( ) ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op , O ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <NUM_LIT> , O ) ; unsigned ScaleVal = MI -> getOperand ( Op


<s> return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [

<STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterMCRelocationInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ElfRelocation


<s> void addMemoryIndexed128SImm7Operands ( MCInst & Inst , unsigned N ) const { addMemoryWritebackIndexedOperands ( Inst , N ,


<s> bool <ISA_LIT>DomainReassignment :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( Disable<ISA_LIT>DomainReassignment ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MF . print ( dbgs ( ) ) ) ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI -> hasAVX512 ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; EnclosedEdges . clear ( ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) ) continue ; Closure C ( { MaskDomain } ) ; buildClosure ( C , Reg


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( TM . getSubtargetImpl ( ) -> isDarwin


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr -> getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , e = OperandsToUpdate . size ( ) ; i < e ; i ++ ) OperandsToUpdate [ i ] . first -> setImm ( OperandsToUpdate [ i ] . second ) ; return


<s> int regno = true_regnum ( x ) ; if ( regno == - <NUM_LIT> ) return Q_REGS ; return NO_REGS ; } if ( ( mode == HFmode || mode == HImode || mode == V2QImode ) && ! TARGET_SSE4_1 && SSE_CLASS_P ( rclass ) && ! in_p && MEM_P ( x ) ) { sri -> extra_cost = <NUM_LIT> ; return GENERAL_REGS


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const


<s> bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI , NMBBI ) ; MBBI =


<s> static __inline __m64 __attribute__ ( ( __always_inline__ ) ) _mm_setzero_si64 ( void ) { return ( __m64


<s> void <ISA_LIT>AsmPrinter :: EmitInstrReg ( unsigned Opcode , unsigned Reg ) { MCInst I ; I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand ::


<s> if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_FUNCTION_VERSIONED ( decl )


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( )


<s> vmlaq_u8 ( uint8x16_t a , uint8x16_t b , uint8x16_t c ) { uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> if ( SrcVT . isVector ( ) || DstVT . isVector ( ) || ! SrcVT . isInteger ( ) || ! DstVT


<s> <ISA_LIT>DisassemblerBase ( STI , Info ,


<s> int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M ,

VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == <NUM_LIT> ) ) ;


<s> if ( ( qualifiers & qualifier_poly ) != <NUM_LIT> ) return arm_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( ( qualifiers & qualifier_unsigned ) != <NUM_LIT> ) return arm_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else if ( ( qualifiers & qualifier_predicate ) != <NUM_LIT>


<s> psllh_u ( uint16x4_t s , uint8_t amount ) { return __builtin_loongson_psllh_u ( s ,


<s> <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , IsO32 , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , getTargetMachine ( ) . Options . UseSoftFloat , MF . getFunction ( ) -> getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI ->


<s> return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base ,


<s> vmlaq_n_s32 ( int32x4_t a , int32x4_t b , int32_t c ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> bool Has64BitPointers = Subtarget -> has64BitPointers ( ) ; EVT PtrVT = getPointerTy ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg ; if ( Subtarget -> isTargetNaCl ( ) ) { FrameReg = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; } else { FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; } assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = Has64BitPointers ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG

. getIntPtrConstant ( RegInfo -> getSlotSize ( ) ) ) ;


<s> SDValue StVal = St . getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( VT . isScalableVector ( ) ) return SDValue ( ) ; int NumVecElts = VT . getVectorNumElements ( ) ; if ( ! ( ( ( NumVecElts == <NUM_LIT> || NumVecElts == <NUM_LIT> ) && VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) || ( ( NumVecElts == <NUM_LIT> || NumVecElts == <NUM_LIT> || NumVecElts == <NUM_LIT> ) && VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) ) ) return SDValue ( ) ; if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! StVal . hasOneUse ( ) ) return SDValue ( ) ; if ( St . isTruncatingStore ( ) ) return SDValue ( ) ; if ( DAG . isBaseWithConstantOffset ( St .


<s> BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; assert ( std :: is_sorted ( MF -> begin ( ) , MF -> end ( ) , [ & BBInfo ] ( const MachineBasicBlock & LHS , const MachineBasicBlock & RHS ) { return BBInfo [ LHS . getNumber ( ) ] . postOffset ( ) < BBInfo [ RHS . getNumber ( ) ] . postOffset ( ) ; } ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPUsers . size ( ) << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) { CPUser & U = CPUsers [ i ] ; unsigned UserOffset = getUserOffset ( U ) ; if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , U . getMaxDisp

( ) + <NUM_LIT> , U . NegOk , true ) ) {


<s> if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && SrcVT . isFloatingPoint ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == EVT ( SrcVT ) . changeVectorElementTypeToInteger ( ) ) Src = Src . getOperand ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; APInt SplatVal ; if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == Src . getValueType ( ) && cast < CondCodeSDNode > ( Src . getOperand ( <NUM_LIT> ) ) -> get ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Src . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue And = Src . getOperand ( <NUM_LIT> ) ; if ( And . hasOneUse ( ) && <STR_LIT> ( And . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal ) && SplatVal . isPowerOf2 ( ) ) { MVT VT = Src . getSimpleValueType ( ) ; unsigned BitWidth = VT . getScalarSizeInBits ( ) ; unsigned ShAmt = BitWidth - SplatVal . logBase2 ( ) - <NUM_LIT> ; SDLoc DL ( And ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; if ( VT . getVectorElementType (


<s> static DecodeStatus DecodeZPR3RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler *


<s> if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( <ISA_LIT>SubTarget -> hasSPE ( ) ) { unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg ) ; return true ; } if ( ! IsSigned && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ?


<s> if ( op_mode == VOIDmode ) op_mode = GET_MODE ( op1 ) ; switch ( op_mode ) { case E_QImode : case E_HImode : case E_SImode : cmp_mode = SImode ; icode = CODE_FOR_ccmpsi ; break ; case E_DImode : cmp_mode = DImode ; icode = CODE_FOR_ccmpdi ; break ; case E_SFmode : cmp_mode = SFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf ; break ; case E_DFmode : cmp_mode = DFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; target = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; aarch64_cond = aarch64_get_condition_code_1 ( cc_mode , ( rtx_code ) cmp_code ) ; if ( bit_code != AND ) { prev = gen_rtx_fmt_ee ( REVERSE_CONDITION ( GET_CODE ( prev ) , GET_MODE ( XEXP ( prev , <NUM_LIT> ) ) ) , VOIDmode , XEXP ( prev , <NUM_LIT> ) , const0_rtx ) ; aarch64_cond = AARCH64_INVERSE_CONDITION_CODE ( aarch64_cond ) ; } create_fixed_operand ( & ops [ <NUM_LIT> ] , XEXP ( prev , <NUM_LIT>


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; } assert ( Opc && <STR_LIT> ) ; MFI . setStackID ( FI , StackID ) ; const MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DebugLoc ( ) , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) ; if ( Offset ) MI . addImm (


<s> Op -> RegList . List1From = <NUM_LIT> ; Op -> RegList . List1To = <NUM_LIT> ; Op -> RegList . List2From = <NUM_LIT> ; Op -> RegList . List2To = <NUM_LIT> ; Op -> RegList . List3From = <NUM_LIT> ; Op -> RegList . List3To = <NUM_LIT> ; Op -> RegList . List4From = <NUM_LIT> ; Op -> RegList . List4To = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < reglist . size ( ) ; i += <NUM_LIT> ) { if ( Op -> RegList . List1From == <NUM_LIT> ) { Op -> RegList . List1From = reglist [ i ] ; Op -> RegList . List1To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List2From == <NUM_LIT> ) { Op -> RegList . List2From = reglist [ i ] ; Op -> RegList . List2To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List3From == <NUM_LIT> ) { Op -> RegList . List3From = reglist [ i ] ; Op -> RegList . List3To = reglist [ i +


<s> return ( __m256i ) __builtin_ia32_vpdpbsud256 ( ( __v8si ) __W , ( __v8si )


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TheTriple , const MCTargetOptions & Options ) { bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 , TheTriple ) ; else if ( TheTriple . isOSBinFormatXCOFF ( ) ) MAI = new <ISA_LIT>XCOFFMCAsmInfo ( is<ISA_LIT>64 , TheTriple ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( is<ISA_LIT>64 , TheTriple ) ; unsigned Reg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI

. getDwarfRegNum ( Reg , true ) , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: writeVarArgRegs ( std :: vector < SDValue > & OutChains , const <ISA_LIT>CC & CC , SDValue Chain , const SDLoc & DL , SelectionDAG & DAG ) const { unsigned NumRegs = CC . numIntArgRegs ( ) ; const ArrayRef < MCPhysReg > ArgRegs = CC . intArgRegs ( ) ; const CCState & CCInfo = CC . getCCInfo ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; unsigned RegSize = CC . regSize ( ) ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo (


<s> StringRef Kind ; int RegNum = - <NUM_LIT> ; auto Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEPredicateVector ) ; if ( Res != MatchOperand_Success ) return Res ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEPredicateVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEPredicateVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Slash ) ) return MatchOperand_Success ; if ( ! Kind . empty ( ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; auto Pred = Parser . getTok ( ) . getString ( ) . lower ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const char * ZM = Pred == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ZM , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O


<s> bool <ISA_LIT>FastISel :: TargetSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return SelectCmp ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I ,


<s> for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] == SM_SentinelUndef ) continue ; else if ( Mask [ i ] < <NUM_LIT> &&

Mask [ i ] != SM_SentinelZero ) return false ;


<s> return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg


<s> int <ISA_LIT>TTIImpl :: getMemcpyCost ( const Instruction * I ) { const MemCpyInst * MI = dyn_cast < MemCpyInst > ( I ) ; assert ( MI && <STR_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( MI -> getLength ( ) ) ; const unsigned LibCallCost = <NUM_LIT> ; if ( ! C ) return


<s> bool invert = invertFPCondCodeUser ( ( <STR_LIT> ) CC -> getSExtValue ( ) ) ; return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL ,

True . getValueType ( ) , True , False , Cond ) ;


<s> static DecodeStatus DecodeModImmInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeFPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> mep_expand_epilogue ( ) ; mep_sibcall_epilogue =


<s> StringRef getSymName ( ) const { return SymName


<s> static void rs6000_debug_target_options ( tree args , const char * prefix ) { if ( args == NULL_TREE ) fprintf ( stderr , <STR_LIT> , prefix ) ; else if ( TREE_CODE ( args ) == STRING_CST ) { char * p = ASTRDUP ( TREE_STRING_POINTER ( args ) ) ; char * q ; while ( ( q = strtok ( p , <STR_LIT> ) ) != NULL ) { p = NULL ; fprintf ( stderr , <STR_LIT> , prefix , q ) ; prefix = <STR_LIT> ; } } else if ( TREE_CODE ( args ) == TREE_LIST ) { do { tree value = TREE_VALUE ( args ) ; if ( value ) { rs6000_debug_target_options ( value , prefix ) ; prefix =


<s> unsigned Reg = I -> getReg ( ) ; int FI = I -> getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . isTargetMachO ( ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI -> getObjectOffset ( FI ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; break ; } } if ( HasFP ) { FramePtrOffsetInBlock += MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size + ArgRegsSaveSize ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( <STR_LIT> ) . addImm ( FramePtrOffsetInBlock / <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( FramePtrOffsetInBlock ) { CFAOffset += FramePtrOffsetInBlock ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , MRI -> getDwarfRegNum ( FramePtr , true ) , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } else { unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , MRI -> getDwarfRegNum ( FramePtr , true ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( NumBytes > <NUM_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr :: FrameSetup ) ; if ( ! HasFP ) { CFAOffset -= NumBytes ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } } if ( STI . isTargetELF ( ) && HasFP ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) report_fatal_error ( <STR_LIT> ) ; if ( RegInfo -> hasBasePointer ( MF ) ) AddDefaultPred ( BuildMI ( MBB , MBBI , dl ,

TII . get ( <STR_LIT> ) , BasePtr ) . addReg ( <STR_LIT> ) ) ;


<s> CurFPOData = std :: make_unique < FPOData > ( ) ; CurFPOData -> Function = ProcSym ; CurFPOData -> Begin = emitFPOLabel ( ) ; CurFPOData -> ParamsSize = ParamsSize ; return false


<s> bool isTwoAddr = NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; unsigned i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! <ISA_LIT>InstrInfo :: is<ISA_LIT>_64NonExtLowByteReg ( Reg ) ) continue ; REX |= <NUM_LIT> ; break ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; } break ; case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << Bit ; Bit


<s> machine_mode mode ; if ( ( MEM_P ( op1 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_LOAD ) || ( MEM_P ( op0 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_STORE ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } rtx orig_op0 = NULL_RTX ; mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode


<s> void <ISA_LIT>DAGToDAGISel :: emitFunctionEntryCode ( ) { const Function & F = MF -> getFunction ( ) ; if ( F . hasExternalLinkage ( ) && F . getName ( ) == <STR_LIT>