<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT . isInteger ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 . getOperand ( <NUM_LIT> ) ) if ( ConstantSDNode

* Y1C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) if ( Y1C -> getAPIntValue ( ) == VT . getSizeInBits ( ) - <NUM_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void setLocalStackSize ( uint64_t Size ) { LocalStackSize =


<s> const MachineOperand & BaseReg = MI -> getOperand ( OpNo + <STR_LIT> ) ; unsigned ScaleVal = MI -> getOperand ( OpNo + <STR_LIT> ) . getImm ( ) ; const MachineOperand & IndexReg = MI -> getOperand ( OpNo + <STR_LIT> ) ; const MachineOperand & DispSpec = MI -> getOperand ( OpNo + <STR_LIT> ) ; const MachineOperand & SegReg = MI -> getOperand ( OpNo + <STR_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; if ( SegReg . getReg ( ) ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; O << ':' ; } O << '[' ; bool NeedPlus = false ; if ( HasBaseReg ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; } else


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i

!= e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> } else cr6_form_int = TREE_INT_CST_LOW ( cr6_form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( mode0 ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; switch ( cr6_form_int ) { case <NUM_LIT> : emit_insn ( gen_cr6_test_for_zero ( target ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_cr6_test_for_zero_reverse (


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , Align ( <NUM_LIT> ) ) ; const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; Function :: const_arg_iterator FuncArg = Func . arg_begin ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) && ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_FixedArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , CCInfo . getInRegsParamsCount ( ) > <NUM_LIT> ) ; unsigned CurArgIdx = <NUM_LIT> ; CCInfo . rewindByValRegsInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . isOrigArg ( ) ) { std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ i ] . getOrigArgIndex ( ) ; } EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Ins [ i ] . isOrigArg ( ) && <STR_LIT> ) ; unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , FirstByValReg , LastByValReg ,


<s> MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getSubtarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back (


<s> } else { if ( ContainerVT . isInteger ( ) ) PassThru = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; else PassThru = DAG . getConstantFP ( <NUM_LIT> , DL , ContainerVT ) ; if ( isZerosVector ( Load -> getPassThru ( ) . getNode ( ) ) ) IsPassThruZeroOrUndef = true ; } auto NewLoad = DAG . getMaskedLoad ( ContainerVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Mask , PassThru , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) , Load -> getAddressingMode ( ) , Load -> getExtensionType ( ) ) ; if ( !


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) { return new MCInstrAnalysis ( Info


<s> auto * PtrTy = cast < PointerType > ( I -> getOperand ( TypeOp ) -> getType ( ) ) ; auto * VecTy = cast < FixedVectorType > ( PtrTy -> getElementType ( ) ) ; assert ( VecTy && <STR_LIT> ) ; return VecTy


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles

, float Probability , float Confidence ) const {


<s> static SDValue combinePMULDQ ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( DAG . isConstantIntBuildVectorOrConstantInt ( LHS ) && ! DAG . isConstantIntBuildVectorOrConstantInt ( RHS ) ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , RHS , LHS ) ; if ( <STR_LIT> ( RHS . getNode ( ) ) ) return RHS ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( <NUM_LIT> ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> if ( Add . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Lo = Add . getOperand ( <NUM_LIT> ) ; if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL (


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = <NUM_LIT> ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> ,


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE )


<s> } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstrBuilder MIB ; if ( StackAdj == <NUM_LIT> ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; } else if ( isUInt < <NUM_LIT> > ( StackAdj ) ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) . addImm ( StackAdj ) ; } else { assert ( ! STI -> is64Bit ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , DL , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; } for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) MIB . add ( MBBI -> getOperand ( I ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( MBB . getParent ( ) -> getFunction ( ) . getPersonalityFn ( ) ) ) ; <ISA_LIT>FL -> restoreWin32EHStackPointers ( MBB , MBBI , DL , IsSEH ) ; MBBI -> eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MachineOperand & InArg = MBBI -> getOperand ( <NUM_LIT> ) ; unsigned SaveRbx = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ActualInArg = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; TII -> copyPhysReg ( MBB , MBBI , DL , ActualInArg , InArg . getReg ( ) , InArg . isKill ( ) ) ; unsigned ActualOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewInstr = BuildMI ( MBB , MBBI , DL , TII -> get ( ActualOpc ) ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx

) NewInstr -> addOperand ( MBBI -> getOperand ( Idx ) ) ;


<s> <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1


<s> HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions =


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> unsigned Reg = MO . getReg ( ) ; if ( ! MRI -> use_nodbg_empty ( Reg ) ) { MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) ; if ( llvm :: next ( I ) == MRI -> use_end ( ) && I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) { MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = <NUM_LIT> , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( OPO . isReg ( ) && OPO . isDef ( ) ) { unsigned OPReg = OPO


<s> Target & llvm :: getThe<ISA_LIT>_32Target ( ) { static Target The<ISA_LIT>leTarget ; return


<s> bool Changed = false ; MBB = & BB ; setupBlockStack ( ) ; for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ++ I ) { MachineInstr & MI = * I ; uint64_t Flags = MI . getDesc ( ) . TSFlags ; unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI . isInlineAsm ( ) ) FPInstClass = <STR_LIT> ; if ( MI . isCopy ( ) && isFPCopy ( MI ) ) FPInstClass = <STR_LIT> ; if ( MI . isImplicitDef ( ) && <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) FPInstClass = <STR_LIT> ; if ( MI . isCall ( ) ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = nullptr ; if ( I != BB . begin ( ) ) PrevMI = & * std :: prev ( I ) ; ++ NumFP ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } LLVM_DEBUG (


<s> <ISA_LIT>MCExpr :: VariantKind LHSVariant , RHSVariant ; const MCExpr * LHS = ExtractModifierFromExpr ( BE -> getLHS ( ) , LHSVariant ) ; const MCExpr * RHS = ExtractModifierFromExpr ( BE -> getRHS ( ) , RHSVariant ) ; if ( ! LHS && ! RHS ) return nullptr ; if ( ! LHS ) LHS = BE -> getLHS ( ) ; if ( ! RHS ) RHS = BE -> getRHS ( ) ; if ( LHSVariant == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Variant = RHSVariant ; else if ( RHSVariant == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Variant = LHSVariant ; else if ( LHSVariant == RHSVariant ) Variant = LHSVariant ; else return nullptr ; return MCBinaryExpr :: Create ( BE -> getOpcode ( ) , LHS


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; if ( ! Subtarget . hasE2 ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has2E3 (


<s> bool hasVPOPCNTDQ ( ) const { return


<s> if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } <ISA_LIT>FunctionInfo * AFI = MF . getInfo <


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs (


<s> SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo (


<s> ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; if ( HOp . getValueSizeInBits ( ) == <NUM_LIT> && ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return HOp ; if ( HOp . getValueSizeInBits ( ) == <NUM_LIT> && ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> }


<s> const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) ,


<s> MachineBasicBlock * TargetMBB = MBBInfo -> TBB ; BranchProbability TargetProb = MBPI -> getEdgeProbability ( & MBB , MBBInfo -> TBB ) ; MachineBasicBlock * PredMBB = BranchPath . front ( ) ; TargetMBBInfo * PredMBBInfo = getMBBInfo ( PredMBB ) ; assert ( PredMBBInfo && <STR_LIT> ) ; if ( PredMBBInfo -> Modified ) fixupModifiedCond ( PredMBB ) ; CC = PredMBBInfo -> BranchCode ; if ( ! ( CC == <STR_LIT> && BranchPath . size ( ) == <NUM_LIT> ) ) replaceBrDest ( PredMBB , & MBB , MBBInfo -> FBB ) ; MachineBasicBlock * RootMBB = BranchPath . back ( ) ; TargetMBBInfo * RootMBBInfo = getMBBInfo ( RootMBB ) ; assert ( RootMBBInfo && <STR_LIT> ) ; if ( RootMBBInfo -> Modified ) fixupModifiedCond ( RootMBB ) ; CC = RootMBBInfo -> BranchCode ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator UncondBrI = findUncondBrI ( RootMBB ) ; <STR_LIT> NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = <STR_LIT> ; break ; case <STR_LIT> : NewCC = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( * RootMBB , UncondBrI , RootMBB -> findDebugLoc ( UncondBrI ) , TII -> get ( GetCondBranchFromCond ( NewCC ) ) ) . addMBB ( RootMBBInfo -> FBB ) ; BuildMI ( * RootMBB , UncondBrI , RootMBB -> findDebugLoc ( UncondBrI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( TargetMBB ) ; RootMBB -> addSuccessor ( TargetMBB ) ; fixPHIsInSucc ( TargetMBB , & MBB , RootMBB ) ; RootMBB -> erase ( UncondBrI ) ; } else { replaceBrDest ( RootMBB , RootMBBInfo -> TBB , TargetMBB ) ; } if ( RootMBBInfo -> CmpValue != MBBInfo -> CmpValue ) { MachineInstr * NewCmp = MBBInfo -> CmpInstr ; NewCmp -> removeFromParent ( ) ; RootMBB -> insert ( RootMBBInfo -> CmpInstr , NewCmp ) ; RootMBBInfo -> CmpInstr -> eraseFromParent ( ) ; } auto fixBranchProb = [ & ] ( MachineBasicBlock * NextMBB ) { BranchProbability Prob


<s> if ( prob . initialized_p ( ) ) { msw_skip_prob = rev_prob ; lsw_taken_prob = prob > profile_probability :: never ( ) ? profile_probability :: guessed_always ( ) : profile_probability :: guessed_never ( ) ; } break ; case NE : msw_taken = NE ; msw_taken_prob = prob ; lsw_taken = NE ; lsw_taken_prob = profile_probability :: guessed_never ( ) ; break ; case GTU : case GT : msw_taken = comparison ; if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) break ; if ( comparison != GTU || op2h != CONST0_RTX ( SImode ) ) msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GTU ; break ; case GEU : case GE : if ( op2l == CONST0_RTX ( SImode ) ) msw_taken = comparison ; else { msw_taken = comparison == GE ? GT : GTU ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GEU ; } break ; case LTU : case LT : msw_taken = comparison ; if ( op2l == CONST0_RTX ( SImode ) ) break ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = LTU ; break ; case LEU : case LE : if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) msw_taken = comparison ; else { lsw_taken = LEU ; if ( comparison == LE ) msw_taken = LT ; else if ( op2h != CONST0_RTX ( SImode ) ) msw_taken = LTU ; else { msw_skip = swap_condition ( LTU ) ; break ; } msw_skip = swap_condition ( msw_taken ) ; } break ; default : return false ; } num_branches = ( ( msw_taken != LAST_AND_UNUSED_RTX_CODE ) + ( msw_skip != LAST_AND_UNUSED_RTX_CODE ) + ( lsw_taken != LAST_AND_UNUSED_RTX_CODE ) ) ; if ( comparison != EQ && comparison != NE && num_branches > <NUM_LIT> ) { if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) && prob . initialized_p ( ) && prob . to_reg_br_prob_base ( ) >= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) && prob . to_reg_br_prob_base ( ) <= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ) { msw_taken_prob = prob / <NUM_LIT> ; msw_skip_prob = rev_prob . apply_scale ( REG_BR_PROB_BASE , rev_prob . to_reg_br_prob_base ( ) + REG_BR_PROB_BASE ) ; lsw_taken_prob = prob ; } else { msw_taken_prob = prob ; msw_skip_prob = profile_probability :: guessed_always ( ) ; lsw_taken_prob = prob ; } } operands [ <NUM_LIT> ] = op1h ; operands [ <NUM_LIT> ] = op2h ; if ( msw_taken != LAST_AND_UNUSED_RTX_CODE ) expand_cbranchsi4 ( operands , msw_taken , msw_taken_prob ) ; if ( msw_skip != LAST_AND_UNUSED_RTX_CODE ) { rtx taken_label = operands [ <NUM_LIT> ] ; if ( msw_taken != LAST_AND_UNUSED_RTX_CODE ) { operands [ <NUM_LIT> ] = op1h ; operands [ <NUM_LIT> ] = op2h ; } operands [ <NUM_LIT> ] = skip_label = gen_label_rtx ( ) ; expand_cbranchsi4 ( operands , msw_skip , msw_skip_prob ) ; operands [ <NUM_LIT> ]


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable


<s> bool <ISA_LIT>Subtarget :: enableEarlyIfConversion ( )


<s> temp = vec_vmrghw ( a , a ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( temp ) : ) ; return ( __m128d )


<s> return inMicro<ISA_LIT>Mode ( ) && has<ISA_LIT>32r6 (


<s> update ( MI , MI . getDesc ( ) . getNumOperands ( ) , MI . getNumOperands ( ) ) ; Defs . reset


<s> Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) Ops . push_back ( Op . getOperand ( I ) ) ; assert ( Op -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; SDVTList RawVTs = DAG . getVTList (


<s> unsigned Size = Constraint . size ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 'v' && Constraint [ Size - <NUM_LIT> ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ <NUM_LIT> ] , & Constraint [ Size - <NUM_LIT> ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= <NUM_LIT> && RegNo <= <NUM_LIT> ) { Res . first = <STR_LIT> . getRegister ( RegNo ) ; Res . second = & <STR_LIT> ; } } } return Res


<s> else if ( isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; break ; case <STR_LIT> : { if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; else if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_COPYWIDEN ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_SPLAT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static int trace_reg_uses ( rtx reg , rtx_insn * start_insn , rtx abort_at_insn ) { log_msg ( <STR_LIT> ) ; log_rtx ( reg ) ; log_msg ( <STR_LIT> ) ; log_insn ( start_insn ) ; int count = <NUM_LIT> ; std :: vector <


<s> return { { MachineOperand :: CreateImm ( static_cast < int64_t > ( Pred ) ) , MachineOperand :: CreateReg ( PredReg


<s> for_each_rtx ( x , mips_sim_wait_regs_2


<s> bool isACCRegNumber ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > (


<s> bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B . getOperand ( <NUM_LIT> ) ; if ( NegC ) C = C . getOperand ( <NUM_LIT> ) ; unsigned Opcode ; if ( ! NegMul ) Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , dl ,


<s> IRBuilder < > Builder ( ActiveLaneMask -> getParent ( ) -> getFirstNonPHI ( ) ) ; Value * Index = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; Value * SplatIndex = Builder . CreateVectorSplat ( VectorWidth , Index , <STR_LIT> ) ; SmallVector < Constant * , <NUM_LIT> > Indices ; for ( int i = <NUM_LIT> ; i < VectorWidth ; ++ i ) Indices . push_back ( ConstantInt :: get ( Index -> getType ( ) , i ) ) ; Constant * CV = ConstantVector :: get ( Indices ) ; Value * Induction = Builder . CreateAdd ( SplatIndex , CV , <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplatIndex << <STR_LIT> ; dbgs ( ) << <STR_LIT> << * Induction << <STR_LIT> ) ; auto * Preheader = L -> getLoopPreheader ( ) ; auto * BTC = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; Value * SplatBTC = nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( BTC ) ) { Builder . SetInsertPoint ( Preheader -> getTerminator ( ) ) ; SplatBTC = Builder . CreateVectorSplat ( VectorWidth , C ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplatBTC << <STR_LIT> ) ; } else { Instruction * InsertElem ; for ( auto & V : * Preheader ) { InsertElem = dyn_cast < InsertElementInst > ( & V ) ; if ( ! InsertElem ) continue ; ConstantInt * CI = dyn_cast < ConstantInt > ( InsertElem -> getOperand ( <NUM_LIT> ) ) ; if ( ! CI ) continue ; if ( InsertElem -> getOperand ( <NUM_LIT> ) != BTC || CI -> getSExtValue ( ) != <NUM_LIT> ) continue ; if ( ( SplatBTC = dyn_cast < ShuffleVectorInst > ( * InsertElem -> users ( ) . begin ( ) ) ) ) break ; } } if ( ! SplatBTC ) { Builder . SetInsertPoint ( Preheader -> getTerminator ( ) ) ; Value * Undef = UndefValue :: get ( FixedVectorType :: get ( BTC -> getType ( ) ,


<s> return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> unsigned <STR_LIT> ( SDNode * N , unsigned EltSize , SelectionDAG & DAG ) { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; assert ( isSplatShuffleMask ( SVOp , EltSize ) ) ; if ( DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) return ( <NUM_LIT> / EltSize ) - <NUM_LIT> - ( SVOp -> getMaskElt ( <NUM_LIT> ) / EltSize ) ; else return SVOp -> getMaskElt (


<s> bool isBranchTarget14 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return true ; int64_t Val = MCE -> getValue ( ) ; if ( Val &


<s> Error ( FPUNameLoc , <STR_LIT> ) ; return false ; } for ( auto Feature : Features ) STI . ApplyFeatureFlag ( Feature ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> static DecodeStatus DecodeSTRPreReg ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSORegMemOperand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) )


<s> const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypePaddedSize ( Ty ) ; if ( GVA -> hasInitializer ( ) && GV -> hasLocalLinkage (


<s> return aarch64_sve_ld1rq_ld1ro_operand_p ( op ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_HI16 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_LO16 : OS << <STR_LIT> ; break ; } const MCExpr * Expr = getSubExpr ( ) ; if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) OS


<s> case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: FAdd : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: FSub : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: FMul : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction ::


<s> emit_insn ( gen_vsx_extract_v2di ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , elt ) ) ; return ; case E_V16QImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v16qi ( target , vec , elt ) ) ; return ; } else break ; case E_V8HImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v8hi ( target , vec , elt ) ) ; return ; } else break ; case E_V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , <NUM_LIT> ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case E_V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case E_V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case E_V16QImode : emit_insn ( gen_vsx_extract_v16qi_var ( target , vec , elt ) ) ; return ; default : gcc_unreachable ( ) ; } } gcc_assert ( CONST_INT_P ( elt ) ) ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , INTVAL ( elt ) * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crcc_w_b_w ( char _1 , int _2 ) { return ( int ) __builtin_loongarch_crcc_w_b_w ( ( char ) _1 , ( int )


<s> if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGlobalMergePass ( TM , <NUM_LIT> ) ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isShifter ( ) ) { assert ( <STR_LIT> ( getShifter ( ) ) == <STR_LIT>


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , false ) , DataLayout ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> <STR_LIT> : ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = LowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , GetConstantPoolIndexSymbol ( MO ) ) ; break ; default : MI -> print ( errs


<s> bool pa_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( from == to ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return true ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ; case <STR_LIT>


<s> if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( RegNum == <NUM_LIT> ) return - <NUM_LIT> ; Parser . Lex (


<s> if ( mips_use_pcrel_pool_p [ ( int ) type ] ) return false ; if ( SMALL_INT ( offset ) && mips_symbol_insns ( type , MAX_MACHINE_MODE ) > <NUM_LIT> ) return true ; if ( TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p ( type ) ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; bool UseUpperBits = false ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: AExtUpper : UseUpperBits = true ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt


<s> if ( GET_CODE ( x ) != REG ) return <NUM_LIT> ; regno = REGNO (


<s> void <ISA_LIT>TargetELFStreamer :: emitInst ( uint32_t Inst , char Suffix ) { getStreamer ( ) . emitInst (


<s> if ( offset + sizeof ( T ) > r . size ( ) ) return true ; T ret = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( T ) ; ++ i ) ret |= ( uint64_t ) r [ offset + i ] << ( i * <NUM_LIT> ) ; ptr = ret ; insn -> readerCursor += sizeof (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> uint64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Value < <NUM_LIT> && <STR_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Ctx . GetOrCreateSymbol ( Name . str ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) const { assert ( ! Op . getSimpleValueType ( ) . isVector ( ) ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op ,


<s> SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; if ( ! ArgFlags . isSplit ( ) && PendingMembers . empty ( ) ) return false ; LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Indirect ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; unsigned Reg = State . AllocateReg ( <STR_LIT> ) ; unsigned Offset = Reg ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( Offset ) ; State . addLoc ( It


<s> virtual const TargetSubtargetInfo * getSubtargetImpl (


<s> int <ISA_LIT>TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty , unsigned AS


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << MI -> getOperand ( OpNum ) . getImm ( ) ; return false ; case 'w' : return printModifiedGPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'x' : return printModifiedGPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'H' : case 'Q' : case 'R' : llvm_unreachable ( <STR_LIT> ) ; case 'b' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'h' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 's' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'd' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'q' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'A' : return printSymbolicAddress ( MI -> getOperand ( OpNum ) , false ,


<s> if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == <NUM_LIT> ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + <NUM_LIT> ) ) ; dwarf_par_index = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = <NUM_LIT> , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , <NUM_LIT> , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; } j ++


<s> psrlw_u ( uint32x2_t s , uint8_t amount ) { return __builtin_loongson_psrlw_u ( s , amount


<s> if ( cmpval != <NUM_LIT> && cmpval != <NUM_LIT> ) return - <NUM_LIT> ; int t ; if ( t_reg_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) ) t = <NUM_LIT> ; else if ( negt_reg_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) ) t = <NUM_LIT> ; else return - <NUM_LIT> ; return t ^ ( cmpval


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo &


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( )


<s> const GlobalValue * GV = N -> getGlobal ( ) ; if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo


<s> CCState CCInfo ( CallConv , isVarArg , MF , MF . getTarget ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> unsigned <ISA_LIT>FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV ,


<s> MachineInstr * PredMI = & Pred -> back ( ) ; if ( PredMI -> getOpcode ( ) == <STR_LIT> ) return PredMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) == Succ ; return


<s> unsigned Opc = <NUM_LIT> ; bool NeedTrunc = false ; uint64_t Mask = <NUM_LIT> ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break


<s> for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , SVOp -> getMask ( ) ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { if ( SDValue Elt = getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) { Elts . push_back ( Elt ) ; continue ; } Elts . clear ( ) ; break ; } if ( Elts . size ( ) == VT . getVectorNumElements ( ) ) if ( SDValue LD = EltsFromConsecutiveLoads ( VT ,

Elts , dl , DAG , Subtarget , true ) ) return LD ;


<s> __builtin_neon_vst4di ( ( __builtin_neon_di * ) __a ,


<s> if ( ! isa < StoreInst > ( BI ) && ! isa < MemSetInst > ( BI ) ) { if ( BI -> mayWriteToMemory ( ) || BI -> mayReadFromMemory ( ) ) break ; continue ; } if ( StoreInst * NextStore = dyn_cast < StoreInst > ( BI ) ) { if ( ! NextStore -> isSimple ( ) ) break ; Optional < int64_t > Offset = isPointerOffset ( StartPtr , NextStore -> getPointerOperand ( ) , * DL ) ; if ( ! Offset ) break ; if ( ! IB . addStore ( * Offset , NextStore , DL ) ) break ; LastInst = NextStore ; } else { MemSetInst * MSI = cast < MemSetInst > ( BI ) ; if ( MSI -> isVolatile ( ) || ! isa < ConstantInt > ( MSI -> getLength ( ) ) ) break ; if ( ! isa < ConstantInt > ( MSI -> getValue ( ) ) ) break ; Optional < int64_t > Offset = isPointerOffset ( StartPtr , MSI -> getDest ( ) , * DL ) ; if ( ! Offset ) break ; if ( ! IB . addMemSet ( * Offset


<s> requiresFrameIndexScavenging ( const MachineFunction


<s> bool Change = false ; for ( auto * Cast : Casts ) { auto * II = cast < IntrinsicInst > ( Cast ) ; if ( II -> getIntrinsicID ( ) == <STR_LIT> ) { SmallVector < Instruction * , <NUM_LIT> > DeadStores ; for ( User * U : Cast -> users ( ) ) { StoreInst * Store = dyn_cast < StoreInst > ( U ) ; if ( ! Store )


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag (


<s> static int loongarch_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & generic_arg ) { struct loongarch_arg_info arg ; loongarch_get_arg_info ( & arg , get_cumulative_args ( cum ) , generic_arg . mode ,

generic_arg . type , generic_arg . named , false ) ;


<s> SDValue <ISA_LIT>TargetLowering :: addTokenForArgument ( SDValue Chain , SelectionDAG & DAG , MachineFrameInfo * MFI , int ClobberedFI ) const { SmallVector < SDValue , <NUM_LIT> > ArgChains ; int64_t FirstByte = MFI -> getObjectOffset ( ClobberedFI ) ; int64_t LastByte = FirstByte + MFI -> getObjectSize ( ClobberedFI ) - <NUM_LIT> ; ArgChains . push_back ( Chain ) ; for ( SDNode :: use_iterator U = DAG . getEntryNode ( ) . getNode ( ) -> use_begin ( ) , UE = DAG . getEntryNode ( ) . getNode ( ) -> use_end ( ) ; U != UE ; ++ U ) if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( * U ) ) if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI -> getObjectOffset (


<s> OriginalArgWas<ISA_LIT>F128 . clear (


<s> bool useBWIRegs ( ) const { return hasBWI ( ) && useAVX512Regs


<s> unsigned <ISA_LIT>HazardRecognizer :: getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) )


<s> EVT VT128 = EVT :: getVectorVT ( * Context , OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return Insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; assert ( OpVT . is128BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG


<s> static bool createShuffleMaskFromVSELECT ( SmallVectorImpl < int > & Mask , SDValue Cond ) { if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return false ; unsigned Size = Cond . getValueType ( ) . getVectorNumElements ( ) ; Mask . resize ( Size , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != ( int ) Size ; ++ i ) { SDValue CondElt = Cond . getOperand (


<s> bool isUImm12 ( ) const { return isUImm < <NUM_LIT> > (


<s> if ( ExpectedElt == NumElts ) ExpectedElt = <NUM_LIT> ; if ( M [ i ] < <NUM_LIT> ) continue ; if ( ExpectedElt != static_cast < unsigned > ( M [ i ] ) )


<s> bool hasOp2 ( unsigned Opc ) const { return OpSet2 . contains ( Opc )


<s> Register Reg = CS . getReg ( ) ; int Offset = RegSpillOffsets [ Reg ] ; if ( Offset >= <NUM_LIT> ) { if ( GRRegClass . contains ( Reg ) ) { if ( LowOffset > Offset ) { LowOffset = Offset ; LowGPR = Reg ; } if ( Offset > HighOffset ) { HighOffset = Offset ; HighGPR = Reg ; } } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( RegSize , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI )


<s> return LowerSTATEPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , TM , getSubtargetInfo ( ) , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIPushReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveXMM ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIAllocStack ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISetFrame ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case


<s> static bool isSplatShuffle ( Value * V ) { if ( auto * Shuf = dyn_cast < ShuffleVectorInst > ( V ) ) return is_splat ( Shuf -> getShuffleMask (


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; unsigned IgnoredFrameReg ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; FI . ChangeToImmediate ( Offset ) ; return ; } unsigned MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FIOffset = MFI . getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; if ( Offset != <NUM_LIT> || ! tryOptimizeLEAtoMOV ( II ) ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getOffset ( ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) .


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm8 ( SDValue N , SDValue & Imm ) const { llvm_unreachable (


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( )


<s> unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return nullptr ; if ( Count == <NUM_LIT> ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return nullptr ; if ( VT == <STR_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) { auto * MaskN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( MaskN -> getZExtValue ( ) != RISBG . Mask ) { SDValue NewMask = CurDAG -> getConstant ( RISBG . Mask , VT ) ; N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewMask ) ; return SelectCode ( N ) ; } return nullptr ; } } unsigned Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) ) { Opcode = <STR_LIT> ; OpcodeVT =


<s> bool IsSelfLoop = MBB . isSuccessor ( & MBB ) ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = llvm :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) ) { BundleMI = MI ; continue ; } LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = prior ( NextMII ) ; MI = & *


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass


<s> return ( float32x4_t ) __builtin_neon_vmul_nv4sf ( __a , (


<s> __o = __builtin_aarch64_set_qregoiv2di_ssps ( __o , ( poly64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2v2di ( ( __builtin_aarch64_simd_di *


<s> unsigned <ISA_LIT>FastISel :: emitAnd_ri ( MVT RetVT , unsigned LHSReg , bool LHSIsKill , uint64_t Imm ) { return emitLogicalOp_ri ( <STR_LIT> , RetVT , LHSReg , LHSIsKill


<s> else if ( TARGET_SOFT_FLOAT_ABI ) abi = <STR_LIT> ; else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi )


<s> unsigned LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; if ( PhysRegSize > ValSize && LocSize == ValSize ) { assert ( ( PhysRegSize == <NUM_LIT> || PhysRegSize == <NUM_LIT> ) && <STR_LIT> ) ; auto MIB = MIRBuilder . buildAnyExt ( LLT :: scalar ( PhysRegSize ) , ValVReg ) ; ExtReg = MIB . getReg ( <NUM_LIT> ) ; } else ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg


<s> MI . setDesc ( B . getTII ( ) . get ( TargetOpcode :: G_ZEXT ) ) ; MI . removeOperand ( <NUM_LIT> ) ; Observer . changedInstr ( MI


<s> bool <ISA_LIT>MCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const { Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value !=


<s> static bool isVZIPMask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT>


<s> if ( ! CONST_INT_P ( arg ) || ! IN_RANGE ( INTVAL ( arg ) , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> )


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , (


<s> static unsigned int mips_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return <NUM_LIT> ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - <NUM_LIT>


<s> void <ISA_LIT>PostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DEBUG ( HazardRec -> dumpState ( ) ;


<s> static const char * getName ( ) { return DEBUG_TYPE


<s> SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = Extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1

, CC ) , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , RHS2 , CC ) ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) ->


<s> if ( ! loongarch_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x


<s> TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs (


<s> break ; } case <STR_LIT> : { Register Src1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Src1 ) ; unsigned Opc ; if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S64 ) || Ty == LLT :: fixed_vector ( <NUM_LIT> , P0 ) ) Opc = <STR_LIT> ; else if ( Ty == S64 || Ty == P0 ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SmallVector < Register , <NUM_LIT> > Regs = { Src1 , Src2 } ; Register Tuple = Ty . getSizeInBits ( ) == <NUM_LIT> ? createQTuple ( Regs , MIB ) : createDTuple ( Regs , MIB ) ; auto Store = MIB . buildInstr ( Opc , { } , { Tuple , Ptr } ) ; Store . cloneMemRefs ( I ) ; constrainSelectedInstRegOperands ( * Store , TII , TRI , RBI ) ; break ; } case <STR_LIT> : { Register DstDef = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstUse = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValUse = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SizeUse = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SizeDef = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Memset = MIB . buildInstr ( <STR_LIT> , { DstDef , SizeDef }


<s> bool isSPVFP = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ? true : false ; unsigned RegClassID = isSPVFP ? <STR_LIT> : <STR_LIT> ; unsigned RegD = decodeVFPRd ( insn , isSPVFP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , RegD ) ) ) ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; unsigned char Imm8 =


<s> MRE . r_word0 = ( ( Addr << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1


<s> return ( ( vec_uint4 ) ( si_clz ( ( qword )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static bool isTransformable ( const MachineInstr & MI ) { unsigned Opc = MI


<s> int64_t getConstantMemOff ( ) const { return static_cast < const MCConstantExpr * > ( getMemOff ( ) )


<s> SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; MVT PTy = getPointerTy ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; <ISA_LIT>FunctionInfo * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue UId = DAG . getConstant ( AFI -> createJumpTableUId ( ) , PTy ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex (


<s> static Constant * getSequentialMask ( IRBuilder < > & Builder , unsigned Start , unsigned NumElts ) { SmallVector < Constant * , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) Mask . push_back ( Builder . getInt32 ( Start +


<s> case LT : case LTU : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case GE : case GEU : emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case LE : case LEU : paired_emit_vector_compare ( GE , dest , op0 , op1 , cc_op1 , cc_op0 ) ; return ; case GT : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case EQ : tmp1 = gen_reg_rtx ( V2SFmode ) ; max = gen_reg_rtx


<s> assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( Address ) ) { O << formatHex ( ( uint64_t ) Address ) ; }


<s> unsigned Offset = Insn & <NUM_LIT> ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT>


<s> int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = CountTrailingZeros_64 ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; DCI . CombineTo ( N ,


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand


<s> if ( Tok . is ( AsmToken :: Integer ) ) { Save = Tok . getIntVal ( ) ; SaveIsReg = false ; Parser . Lex ( ) ; } else return reportParseError ( <STR_LIT> ) ; } else Save = getGPR ( Save ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; StringRef


<s> default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = RoundUpToAlignment ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment (


<s> MCAsmParser & Parser = getParser ( ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > TmpOperands ; SmallVector < unsigned , <NUM_LIT> > Regs ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_ParseFail ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( TmpOperands ) != MatchOperand_Success ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * Reg = & static_cast < <ISA_LIT>Operand & > ( * TmpOperands . back ( ) ) ; unsigned RegNo = isGP64bit ( ) ? Reg -> getGPR64Reg ( ) : Reg -> getGPR32Reg ( ) ; Regs . push_back ( RegNo ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) .


<s> offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( current_function_pretend_args_size || cfun -> machine -> uses_anonymous_args || current_function_calls_eh_return || current_function_calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) ) return <NUM_LIT> ; saved_int_regs = arm_compute_save_reg_mask ( ) ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5 ) { if ( ! call_used_regs [ <NUM_LIT> ] ) return <NUM_LIT> ; if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return <NUM_LIT> ; if ( sibling ) { gcc_assert ( GET_CODE ( sibling ) == CALL_INSN ) ; if ( find_regno_fusage ( sibling , USE , <NUM_LIT> ) ) return <NUM_LIT> ; } if ( saved_int_regs & <NUM_LIT> ) return <NUM_LIT> ; } if ( TARGET_INTERWORK && saved_int_regs != <NUM_LIT> ) return <NUM_LIT> ; if ( iscond &&


<s> return TargetTriple . isOSBinFormatCOFF


<s> } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat )


<s> MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg


<s> MIB . addReg ( Addr . getReg ( ) ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . add ( Addr ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( &


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1


<s> if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasXMMInt ( ) ) return <STR_LIT> ; if ( Subtarget -> hasXMM ( ) ) return <STR_LIT> ; } return TargetLowering :: LowerXConstraint ( ConstraintVT )


<s> unsigned LoadDefRegister = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MCSymbol * HandlerLabel = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; unsigned LoadOpcode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned LoadOperandsBeginIdx = <NUM_LIT> ; FM . recordFaultingOp ( FaultMaps :: FaultingLoad , HandlerLabel ) ; MCInst LoadMI ; LoadMI . setOpcode ( LoadOpcode ) ; if ( LoadDefRegister != <STR_LIT> ) LoadMI . addOperand ( MCOperand :: createReg ( LoadDefRegister ) ) ; for ( auto I = MI . operands_begin ( ) + LoadOperandsBeginIdx , E = MI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI

, * I ) ) LoadMI . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> unsigned FrameSize = MFI . getStackSize ( ) ; Align StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlign ( ) : getStackAlign ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize


<s> if ( T . isArch64Bit ( ) && ( Features & <STR_LIT> ) ) { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue (


<s> bool <ISA_LIT>InstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops ) const { if ( NoFusing ) return <NUM_LIT> ; if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ) return false ; break ; } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = <NUM_LIT> ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = &


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Pred == <NUM_LIT> ) return DecodeSETPANInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , Pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> } } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ]


<s> return ( __m128d ) __builtin_ia32_sqrtsd_mask_round ( ( __v2df ) __B , ( __v2df ) __A , (


<s> static inline float getFPImmFloat ( unsigned Imm ) { union { uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= Mantissa <<


<s> if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL -> getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mang -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return


<s> assert ( ( Kind == k_MemoryRegImmImm || Kind ==


<s> case E_V4QImode : if ( TARGET_SSE4_1 ) break ; wmode = V2HImode ; widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & <NUM_LIT> ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << <NUM_LIT> , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> <NUM_LIT> ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec )


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI


<s> emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? <NUM_LIT> : <NUM_LIT> ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x1 , src , x2 ) ) ; if ( iterations > <NUM_LIT> ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr , Builder ) ; if ( ! Store ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent


<s> isEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>MachineFunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls ) return false ; if ( <ISA_LIT>CCInfo . hasByValArg ( ) || FI . hasByvalArg (


<s> return ( __m512i ) __builtin_ia32_pbroadcastq512 ( ( __v2di ) __A , ( __v8di ) _mm512_undefined_epi32 ( )


<s> assert ( ( VT . is128BitVector ( ) && ( VT . getScalarSizeInBits ( ) == <NUM_LIT> || VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) != N1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; SDValue WideVec = N0 . getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVec . getValueType ( ) ; if ( ! WideVT . is256BitVector ( ) || ! isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; APInt ExtIndex0 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; APInt ExtIndex1 = cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ExtIndex1 == <NUM_LIT> && ExtIndex0 == NumElts ) { std :: swap ( ExtIndex0 , ExtIndex1 ) ; ShuffleVectorSDNode :: commuteMask ( NewMask ) ; } if ( ExtIndex0 != <NUM_LIT> || ExtIndex1 != NumElts ) return SDValue ( ) ; if ( NumElts == <NUM_LIT> && isSingleSHUFPSMask ( NewMask


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext


<s> static bool arm_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type


<s> return new <ISA_LIT>PassConfig ( this


<s> unsigned retval = <NUM_LIT> ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( stmt_info && vectype && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) stmt_cost = aarch64_sve_adjust_stmt_cost ( kind , stmt_info , vectype , stmt_cost ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> case 'q' : case 'Q' : case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'f' : case 't' : case 'u' : if ( type -> isFloatingPointTy ( ) ) weight = CW_SpecificReg ; break ; case 'y' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget -> hasMMX ( ) ) weight = CW_SpecificReg ; break ; case 'x' : case 'Y' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget -> hasAVX ( ) ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( dyn_cast < ConstantFP > ( CallOperandVal ) ) { weight = CW_Constant ; } break ; case 'e' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'Z' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <=


<s> else SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; if ( Kind != MCSymbolRefExpr :: VK_None ) O << MCSymbolRefExpr :: getVariantKindName ( Kind ) ; if ( BE || Kind != MCSymbolRefExpr :: VK_None ) { O <<