<s> unsigned Op0 = getFPReg ( MI -> getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI -> getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI -> killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned TOS = getStackEntry ( <NUM_LIT> ) ; if ( Op0 != TOS && Op1 != TOS ) { if ( KillsOp0 ) { moveToTop ( Op0 , I ) ; TOS = Op0 ; } else if ( KillsOp1 ) { moveToTop ( Op1 , I ) ; TOS = Op1 ; } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; const TableEntry * InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable =


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useFastISel (


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module &


<s> if ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : const Function * F = MF . getFunction ( ) ; if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_64_Win64 ) ) return & <STR_LIT> ; else if ( Is64Bit ) return & <STR_LIT> ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & <STR_LIT> ; return &


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE


<s> bool hasBEAREnhancement ( ) const { return


<s> unsigned getGPR32Reg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ; AsmParser . warnIfRegIndexIsAT ( RegIdx . Index , StartLoc ) ; unsigned ClassID = <STR_LIT>


<s> void DecodePSHUFMask ( EVT VT , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits (


<s> unsigned <ISA_LIT>SpeculativeLoadHardeningPass :: extractPredStateFromSP ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt , DebugLoc Loc ) { unsigned PredStateReg = MRI -> createVirtualRegister ( PS -> RC ) ; unsigned TmpReg = MRI -> createVirtualRegister


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; assert ( Subtarget -> hasBMI ( ) && <STR_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand (


<s> void RelaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( <NUM_LIT> && <STR_LIT> )


<s> return ( uint64x1_t ) ( __a >= __AARCH64_INT64_C ( <NUM_LIT> )


<s> d . one_operand_p = false ; d . testing_p = false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] = i * <NUM_LIT> + odd ; if ( expand_vec_perm_1 ( & d ) ) return ; expand_vec_perm_even_odd_1 ( & d


<s> if ( ! cmp ) return false ; if ( negate ) cmp = ix86_expand_int_sse_cmp ( operands [ <NUM_LIT> ] , EQ , cmp , CONST0_RTX ( GET_MODE ( cmp ) ) , NULL , NULL , & negate ) ; gcc_assert ( ! negate ) ; if ( operands [ <NUM_LIT> ] != cmp ) emit_move_insn ( operands [ <NUM_LIT> ] , cmp ) ; return true


<s> Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysCR ( Num , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success


<s> } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , DB ? DB -> Name : <STR_LIT> , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto TSB = <STR_LIT> ( Tok . getString ( ) ) ; auto DB = <STR_LIT> ( Tok . getString ( ) ) ; if ( Mnemonic == <STR_LIT> && ( ! DB || DB -> Encoding != <STR_LIT> ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( Mnemonic == <STR_LIT> && ( ! TSB || TSB -> Encoding != <STR_LIT> ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ! DB && ! TSB ) { TokError ( <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; EVT Ty = Op


<s> else if ( aarch64_evpc_ext ( d ) ) return true ; else if ( aarch64_evpc_dup ( d ) ) return true ; else if ( aarch64_evpc_zip ( d ) ) return true ; else if ( aarch64_evpc_uzp ( d ) ) return true ; else if ( aarch64_evpc_trn ( d ) ) return true ; if ( d -> vec_flags == VEC_SVE_DATA ) return aarch64_evpc_sve_tbl ( d


<s> assert ( isPowerOf2_32 ( NumElts ) && <STR_LIT> ) ; Imm = Imm & ( NumElts - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) ShuffleMask . push_back


<s> bool <ISA_LIT>AsmParser :: expandJalWithRegs ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; MCInst JalrInst ; JalrInst . setLoc ( IDLoc ) ; const MCOperand FirstRegOp = Inst . getOperand ( <NUM_LIT> ) ; const unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { if ( IsCpRestoreSet && inMicro<ISA_LIT>Mode ( ) ) { JalrInst . setOpcode ( <STR_LIT> ) ; JalrInst . addOperand ( FirstRegOp


<s> return ( __m128i ) __builtin_ia32_vprotd ( ( __v4si ) __A ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = QFPRegDecoderTable [ RegNo ] ; if ( Reg == ~ <NUM_LIT> )


<s> return ( int8_t ) __builtin_aarch64_sqmovunhi


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) && MI -> getOperand ( <NUM_LIT> ) . isUse ( ) && <STR_LIT> ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == NullValueReg && MI -> getOperand ( <NUM_LIT> ) . getReg


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! hasThumb ( ) ) return Error (


<s> if ( ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; return Def


<s> static SDValue materializeVectorConstant ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; return getZeroVector ( VT , Subtarget , DAG


<s> SDValue Result = AddCombineToVPADDL ( N , N0 , N1 , DCI , Subtarget ) ; if ( Result . getNode ( ) ) return Result ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI ) ; if ( Result . getNode ( ) ) return Result ; } return SDValue (


<s> return ( uint8x16_t ) __builtin_neon_vceqv16qi ( __a ,


<s> case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> NeedTruncation = true ; ArithOp = Arith ; } } } switch ( ArithOp . getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ArithOp . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> isOne ( ) && ! Subtarget . slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> isAllOnesValue ( ) && ! Subtarget . slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , dl , VT ) ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; Op = New ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT>


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutOps [ ] = { OutLo ,


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( SrcReg ) ; unsigned DstReg = MRI ->


<s> if ( ChangeTo<ISA_LIT>16 ) { if ( PreviousIn<ISA_LIT>16Mode ) return ; OverrideMode = <ISA_LIT>16Override ; PreviousIn<ISA_LIT>16Mode = true ; setHelperClasses<ISA_LIT>16 ( ) ; return ; } else if ( ChangeToNo<ISA_LIT>16 ) { if ( ! PreviousIn<ISA_LIT>16Mode ) return ; OverrideMode = No<ISA_LIT>16Override ; PreviousIn<ISA_LIT>16Mode = false ; setHelperClasses<ISA_LIT>SE ( ) ; return ; } else { if ( OverrideMode == NoOverride ) return ; OverrideMode = NoOverride ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( in<ISA_LIT>16Mode ( ) && ! PreviousIn<ISA_LIT>16Mode ) { setHelperClasses<ISA_LIT>16 ( ) ; PreviousIn<ISA_LIT>16Mode = true ; } else if ( ! in<ISA_LIT>16Mode ( )


<s> static SDValue joinDwords ( SelectionDAG & DAG , SDLoc DL , SDValue Op0 , SDValue Op1 ) { if ( Op0 . isUndef ( ) && Op1 . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( Op0 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; else if ( Op1 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; else { Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> ,


<s> if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) .


<s> if ( InOp . isUndef ( ) ) return DAG . getUNDEF ( NVT ) ; assert ( InVT . getVectorElementType ( ) == NVT . getVectorElementType ( ) && <STR_LIT> ) ; unsigned InNumElts = InVT . getVectorNumElements ( ) ; unsigned WidenNumElts = NVT . getVectorNumElements ( ) ; assert ( WidenNumElts > InNumElts && WidenNumElts % InNumElts == <NUM_LIT> && <STR_LIT> ) ; EVT EltVT = NVT . getVectorElementType ( ) ; SDLoc dl ( InOp ) ; if ( InOp . getOpcode ( ) == <STR_LIT> && InOp . getNumOperands ( ) == <NUM_LIT> ) { SDValue N1 = InOp . getOperand ( <NUM_LIT> ) ; if ( ( <STR_LIT> ( N1 . getNode ( ) ) && FillWithZeroes ) || N1 . isUndef ( ) ) { InOp = InOp . getOperand ( <NUM_LIT>


<s> vld1q_dup_p8 ( const poly8_t * __a ) { return ( poly8x16_t ) __builtin_neon_vld1_dupv16qi ( ( const __builtin_neon_qi *


<s> for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange


<s> unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reg0 != Reg1 ) return false ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( )


<s> SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: WinEH ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT>


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind ( <STR_LIT> ) ; const MCExpr *


<s> bool isThumbTwo ( ) const { return isThumb ( ) && STI . getFeatureBits


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT>


<s> SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( ) ) ; InChain = OverflowArea . getValue ( <NUM_LIT> ) ; SDValue RegSaveArea = DAG . getLoad ( <STR_LIT> , dl , InChain , RegSaveAreaPtr , MachinePointerInfo ( ) ) ; InChain = RegSaveArea . getValue ( <NUM_LIT> ) ; SDValue CC = DAG . getSetCC ( dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue RegConstant = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT . isInteger ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , RegSaveArea , RegConstant ) ; if ( VT . isFloatingPoint ( ) ) OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , OurReg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue IndexPlus1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; InChain = DAG . getTruncStore ( InChain , dl , IndexPlus1 , VT . isInteger ( ) ? VAListPtr : FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl

, PtrVT , CC , OurReg , OverflowArea ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( mode1 == mode2 || ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( mode1 != SFmode && mode2 !=


<s> tree labelname ; tree funname = get_identifier ( XSTR ( operands [ dest_operand_number ] , <NUM_LIT> ) ) ; if ( no_previous_def ( funname ) ) { int line_number = <NUM_LIT> ; rtx label_rtx = gen_label_rtx ( ) ; char * label_buf , temp_buf [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( temp_buf , <STR_LIT> , CODE_LABEL_NUMBER ( label_rtx ) ) ; label_buf = temp_buf [ <NUM_LIT> ] == '*' ? temp_buf + <NUM_LIT> : temp_buf ; labelname = get_identifier ( label_buf ) ; for ( ; insn && GET_CODE ( insn ) != NOTE ; insn = PREV_INSN ( insn ) ) ; if ( insn ) line_number = NOTE_LINE_NUMBER ( insn ) ; add_compiler_branch_island ( labelname , funname , line_number ) ; } else labelname = get_prev_label ( funname ) ; sprintf ( buf , <STR_LIT> , dest_operand_number , IDENTIFIER_POINTER ( labelname ) ) ; } else sprintf ( buf , <STR_LIT>


<s> int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; return <STR_LIT> ( Val , <NUM_LIT>


<s> if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( SImm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; } else


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , VectorType * Tp , ArrayRef < int > Mask , int Index , VectorType * SubTp , ArrayRef < Value * > Args ) { Kind = improveShuffleKindFromMask ( Kind , Mask ) ; if ( ST -> hasVector ( ) ) { unsigned NumVectors = getNumVectorRegs ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo :: SK_ExtractSubvector : return ( Index == <NUM_LIT> ? <NUM_LIT>


<s> static bool isLegalArithImmed ( uint64_t C ) { return ( C >> <NUM_LIT> == <NUM_LIT> ) || ( ( C & <NUM_LIT> ) == <NUM_LIT> && C >> <NUM_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: canUseBlockOperation ( StoreSDNode * Store , LoadSDNode * Load ) const { if ( Load -> getMemoryVT ( ) != Store -> getMemoryVT ( ) ) return false ; if ( Load -> isVolatile ( ) || Store -> isVolatile ( ) ) return false ; if ( Load -> isInvariant ( ) ) return true ; const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) +


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveVariantPCS ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH


) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> emitFunctionEnd ( MachineFunction & MF ) { O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> <<


<s> bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget


<s> SDValue <ISA_LIT>TargetLowering :: LowerSINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) { return Op ; } return SDValue ( ) ; } assert ( SrcVT . getSimpleVT ( ) <= <STR_LIT> &&

SrcVT . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ;


<s> if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) )


<s> bool isS5Imm ( ) const { return Kind == Immediate && isInt < <NUM_LIT> > (


<s> ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT == <STR_LIT> ) { unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , Result32 , true , <STR_LIT> ) ; } else if ( DstVT != <STR_LIT> ) { ResultReg = fastEmit_r ( <STR_LIT> , DstVT . getSimpleVT ( ) , <STR_LIT> , ResultReg , true ) ; if ( ResultReg == <NUM_LIT>


<s> _Unwind_Control_Block * ucbp ; ucbp = unwind_UCB_from_context (


<s> <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel ::


<s> rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely


<s> int64_t Val = MCE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val


<s> const std :: string & getCPUString ( ) const { return CPUString


<s> if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( * InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: createAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT>


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame . getObjectSize ( FI ) , MFFrame . getObjectAlign ( FI ) ) ; return MIB . addFrameIndex ( FI ) . addImm ( Offset ) . addReg ( <NUM_LIT> )


<s> std :: vector < Forward > & getForwardedMustTailRegParms ( ) { return


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name ) { int CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT>

, <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoopsVerify ( ) ) ; addPass ( create<ISA_LIT>VSXCopyPass (


<s> unsigned NecessarySize = UseWReg ? <NUM_LIT> : <NUM_LIT> ; if ( Size != NecessarySize ) TestReg = moveScalarRegClass ( TestReg , UseWReg ? <STR_LIT> : <STR_LIT> , MIB ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ UseWReg ] [ IsNegative ] ; auto TestBitMI = MIB . buildInstr ( Opc ) . addReg ( TestReg ) . addImm ( Bit ) . addMBB ( DstMBB ) ; constrainSelectedInstRegOperands ( * TestBitMI , TII ,


<s> if ( ! CInt ) return nullptr ; auto * VecTy = cast < FixedVectorType > ( II . getType ( ) ) ; assert ( VecTy -> getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; uint8_t Imm = CInt -> getZExtValue ( ) ; uint8_t ZMask = Imm & <NUM_LIT> ; uint8_t DestLane = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t SourceLane = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; ConstantAggregateZero * ZeroVector = ConstantAggregateZero :: get ( VecTy ) ; if ( ZMask == <NUM_LIT> ) return ZeroVector ; int ShuffleMask [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Value * V1 = II . getArgOperand ( <NUM_LIT> ) ; if ( ZMask ) { if ( ( II . getArgOperand ( <NUM_LIT> ) == II . getArgOperand ( <NUM_LIT> ) ) || ( ZMask & ( <NUM_LIT> << DestLane ) ) ) { V1 =


<s> Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt >= <NUM_LIT> ) { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } else OffReg = OffReg .


<s> Register SubTmp = TRI -> getSubReg ( TmpReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( M1 ( <NUM_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SubTmp , getKillRegState ( true ) ) ; MIB . getInstr ( ) -> addRegisterKilled ( TmpReg , TRI , true ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { const unsigned SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned int NumSubRegs = <NUM_LIT> ; copyPhysSubRegs ( MBB , I , DL , DestReg , SrcReg , KillSrc , get ( <STR_LIT> ) , NumSubRegs , SubRegIdx , & getRegisterInfo ( ) ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { const unsigned SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned int NumSubRegs = <NUM_LIT> ; copyPhysSubRegs ( MBB , I , DL , DestReg , SrcReg , KillSrc , get ( <STR_LIT> ) , NumSubRegs , SubRegIdx


<s> SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) { return Op ; } RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) ,


<s> else ix86_tune_features [ i ] = ! ! ( initial_ix86_tune_features [ i ] & ix86_tune_mask ) ; } if ( dump ) { fprintf ( stderr , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; i ++ ) fprintf ( stderr , <STR_LIT> , ix86_tune_feature_names [ i ] , ix86_tune_features [


<s> if ( ! OpVT . isScalarInteger ( ) || OpSize < <NUM_LIT> || isNullConstant ( Y ) ) return SDValue ( ) ; if ( peekThroughBitcasts ( X ) . getValueType ( ) == <STR_LIT> || peekThroughBitcasts ( Y ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; EVT VT = SetCC -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( SetCC ) ; if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . hasAVX2 ( ) ) ) { EVT VecVT = OpSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT


<s> if ( ! sys :: Memory :: setRangeExecutable ( ( void * ) Addr , <NUM_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } void * PtrAddr = JCE . finishGVStub ( GV ) ; addIndirectSymAddr ( Ptr , ( intptr_t


<s> return __builtin_aarch64_lfrintnusfsi ( __a )


<s> SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> mayStore ( ) ) { assert ( DstReg == <STR_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; unsigned Pad = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isImplicit ( ) ) continue ; if ( MO . isUndef ( ) ) { assert ( RegList . empty ( ) && <STR_LIT> ) ; unsigned Width = TargetRegInfo -> getRegSizeInBits ( MO . getReg ( ) , MachineRegInfo ) / <NUM_LIT> ; Pad += Width ; continue ; } RegList . push_back ( MO . getReg ( ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) { ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; if ( Pad ) ATS . emitPad ( Pad ) ; } } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx (


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , unsigned FramePtr ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const <ISA_LIT>RegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - RegInfo -> getSlotSize ( ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx


<s> return isMem512 ( ) && isMemIndexReg


<s> unsigned UpdatedVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & EntryBB = * Fn . begin ( ) ; DebugLoc dl ; MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get (

<STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ;


<s> case <STR_LIT> : return visitBR_JT ( N ) ; case <STR_LIT> : return visitBR2_JT ( N ) ; case <STR_LIT> : return visitRET_FLAG ( N ) ; case <STR_LIT> : return visitINTRET_FLAG ( N ) ; case <STR_LIT> : return visitPIC_ADD ( N ) ; case <STR_LIT> : return visitCMP ( N ) ; case <STR_LIT> : return visitCMN ( N ) ; case <STR_LIT> : return visitCMPZ ( N ) ; case <STR_LIT> : return visitCMPFP ( N ) ; case <STR_LIT> : return visitCMPFPw0 ( N ) ; case <STR_LIT> : return visitFMSTAT ( N ) ; case <STR_LIT> : return visitCMOV ( N ) ; case <STR_LIT> : return visitBCC_i64 ( N ) ; case <STR_LIT> : return visitRBIT ( N ) ; case <STR_LIT> : return visitFTOSI ( N ) ; case <STR_LIT> : return visitFTOUI ( N ) ; case <STR_LIT> : return visitSITOF ( N ) ; case <STR_LIT> : return visitUITOF ( N ) ; case <STR_LIT> : return visitSRL_FLAG ( N ) ; case <STR_LIT> : return visitSRA_FLAG ( N ) ; case <STR_LIT> : return visitRRX ( N ) ; case <STR_LIT> : return visitADDC ( N ) ; case <STR_LIT> : return visitADDE ( N ) ; case <STR_LIT> : return visitSUBC ( N ) ; case <STR_LIT> : return visitSUBE ( N ) ; case <STR_LIT> : return visitVMOVRRD ( N ) ; case <STR_LIT> : return visitVMOVDRR ( N ) ; case <STR_LIT> : return visitEH_SJLJ_SETJMP ( N ) ; case <STR_LIT> : return visitEH_SJLJ_LONGJMP ( N ) ; case <STR_LIT> : return visitTC_RETURN ( N ) ; case <STR_LIT> : return visitTHREAD_POINTER ( N ) ; case <STR_LIT> : return visitDYN_ALLOC ( N ) ; case <STR_LIT> : return visitMEMBARRIER_MCR ( N ) ; case <STR_LIT> : return visitPRELOAD ( N ) ; case <STR_LIT> : return visitVCEQ ( N ) ; case <STR_LIT> : return visitVCEQZ ( N ) ; case <STR_LIT> : return visitVCGE ( N ) ; case <STR_LIT> : return visitVCGEZ ( N ) ; case <STR_LIT> : return visitVCLEZ ( N ) ; case <STR_LIT> : return visitVCGEU ( N ) ; case <STR_LIT> : return visitVCGT ( N ) ; case <STR_LIT> : return visitVCGTZ ( N ) ; case <STR_LIT> : return visitVCLTZ ( N ) ; case <STR_LIT> : return visitVCGTU ( N ) ; case <STR_LIT> : return visitVTST ( N ) ; case <STR_LIT> : return visitVSHL ( N ) ; case <STR_LIT> : return visitVSHRs ( N ) ; case <STR_LIT> : return visitVSHRu ( N ) ; case <STR_LIT> : return visitVRSHRs ( N ) ; case <STR_LIT> : return visitVRSHRu ( N ) ; case <STR_LIT> : return visitVQSHLs ( N ) ; case <STR_LIT> : return visitVQSHLu ( N ) ; case <STR_LIT> : return visitVQSHLsu ( N ) ; case <STR_LIT> : return visitVQSHRNs ( N ) ; case <STR_LIT> : return visitVQSHRNu ( N ) ; case <STR_LIT> : return visitVQSHRNsu ( N


<s> if ( ! isSysReg ( ) ) return false ; return SysReg . MRSReg


<s> return DAG -> getNode ( <STR_LIT> , dl


<s> unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) MIB . add ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MI ->


<s> __inline__ static unsigned long long sh_media_BYTEREV ( unsigned long long mm ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT>


<s> if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) )


<s> MachineInstr * CMPI = MRI -> getVRegDef ( CndReg ) ; if ( CMPI -> getParent ( ) != & BB ) return false ; for ( MachineOperand & MO : CMPI -> operands ( ) ) if ( MO . isReg ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) return false ; return true ; } return false ; } ; auto isEligibleForMoveCmp = [ ] ( MachineBasicBlock & BB ) { return BB . succ_size ( ) == <NUM_LIT> ; } ; if ( ! isEligibleBB ( MBB ) ) return false ; unsigned NumPredBBs = MBB . pred_size ( ) ; if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock * TmpMBB = * MBB . pred_begin ( ) ; if ( isEligibleBB ( * TmpMBB ) ) { PredMBB = TmpMBB ; MBBtoMoveCmp = nullptr ; return true ; } } else if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock :: pred_iterator PI = MBB . pred_begin ( ) ; MachineBasicBlock * Pred1MBB = * PI ; MachineBasicBlock * Pred2MBB = * ( PI + <NUM_LIT> ) ; if ( isEligibleBB ( * Pred1MBB ) && isEligibleForMoveCmp ( * Pred2MBB ) ) { } else if ( isEligibleBB ( * Pred2MBB ) && isEligibleForMoveCmp ( * Pred1MBB ) ) { std :: swap ( Pred1MBB , Pred2MBB ) ; } else return false


<s> } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op .


<s> static int neon_pair_endian_lane_map ( machine_mode mode , int lane ) { int nelem = GET_MODE_NUNITS ( mode ) ; if ( BYTES_BIG_ENDIAN ) lane = neon_endian_lane_map ( mode , lane & ( nelem - <NUM_LIT> ) ) + ( lane &


<s> } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DstVT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( FP ) ) ; updateValueMap ( I , ResultReg ) ; return true


<s> bool isMemImm ( ) const { return Kind ==


<s> } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( aarch64_enable_bti == <NUM_LIT> ) { aarch64_enable_bti = <NUM_LIT> ; aarch64_enable_bti = <NUM_LIT> ; } if ( ! TARGET_ILP32 && accepted_branch_protection_string == NULL ) { aarch64_ra_sign_scope = AARCH64_FUNCTION_NON_LEAF ; aarch64_ra_sign_scope = AARCH64_FUNCTION_NONE ; } if ( TARGET_ILP32 ) error ( <STR_LIT> ) ; aarch64_sve_vg = aarch64_convert_sve_vector_bits ( aarch64_sve_vector_bits ) ; if ( aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE && TARGET_ILP32 ) sorry ( <STR_LIT> ) ; if ( ( aarch64_cpu_string && valid_cpu ) || ( aarch64_tune_string && valid_tune ) ) gcc_assert ( explicit_tune_core != aarch64_none ) ; if ( ( aarch64_cpu_string && valid_cpu ) || ( aarch64_arch_string && valid_arch ) ) gcc_assert ( explicit_arch != aarch64_no_arch ) ; if ( aarch64_track_speculation ) flag_shrink_wrap = <NUM_LIT> ; aarch64_override_options_internal ( &


<s> bool isVecListOneDAllLanes ( ) const { if ( ! isSingleSpacedVectorAllLanes ( ) ) return false ; return VectorList . Count ==


<s> int div = <NUM_LIT> ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX512_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; width = ( width + div - <NUM_LIT> ) /


<s> if ( shift < <NUM_LIT> || shift > <NUM_LIT> ) gcc_unreachable ( ) ; return shift


<s> for ( i = <NUM_LIT> ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; if ( d -> vec_flags & VEC_SVE_DATA ) { rtx pred = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_revbhw ( d -> vmode , pred_mode , d -> target , pred , d -> op0 ) ) ; return true ; } rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d -> op0 )


<s> if ( Val . getOpcode ( ) != <STR_LIT> || ( Val . getValueSizeInBits ( ) > <NUM_LIT> && SingleFloat ) ) return SDValue ( ) ; EVT FPTy = EVT :: getFloatingPointVT ( Val . getValueSizeInBits ( ) ) ; SDValue Tr = DAG . getNode ( <STR_LIT> , SDLoc ( Val ) , FPTy ,


<s> if ( ! member ) continue ; for ( member = OVL_CURRENT ( member ) ; member ; member = OVL_NEXT ( member ) ) { if ( TREE_CODE ( member ) != FUNCTION_DECL ) continue ; if ( DECL_PURE_VIRTUAL_P ( member ) ) continue ; if ( ! DECL_VIRTUAL_P ( member ) ) continue ; if ( lookup_attribute ( attribute_name , DECL_ATTRIBUTES ( member ) ) ) { print_node_brief ( stderr , <STR_LIT> , ctype , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> , attribute_name ) ; print_node_brief ( stderr , <STR_LIT> , member , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; return true ; } } } } print_node_brief ( stderr , <STR_LIT> , ctype , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT>


<s> if ( TT . isOSBinFormatMachO ( ) ) return llvm :: make_unique < TargetLoweringObjectFileMachO > ( ) ; if ( TT . isOSWindows ( ) ) return llvm :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; return llvm :: make_unique < <ISA_LIT>ElfTargetObjectFile > (


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; if ( MO . getReg ( ) != <STR_LIT> ) continue ; assert ( LiveCPSR && <STR_LIT> ) ; if ( MO . isKill ( ) ) { LiveCPSR =


<s> vqmovn_high_u32 ( uint16x4_t a , uint32x4_t b ) { uint16x8_t result = vcombine_u16 ( a , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = std :: min ( OffsetA


, ( __v16sf ) _mm512_setzero_ps ( ) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( ( Ty != <STR_LIT> ) && ( ( Ty != <STR_LIT> ) || ! Subtarget -> hasDSPR2 ( ) ) ) return SDValue ( ) ; return performDSPShiftCombine ( <STR_LIT> , N , Ty , DAG ,


<s> return ( __m64 ) __builtin_arm_tbcstw ( value


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , VT , N0 ,


<s> else emit_insn ( gen_addsi3 ( countreg , countreg , GEN_INT ( - value )


<s> vmvn_u16 ( uint16x4_t __a ) { return ~


<s> static DecodeStatus DecodeVecShiftL8Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftLImm ( Inst , Imm ,


<s> Iter Filler :: replaceWithCompactBranch ( MachineBasicBlock & MBB , Iter Branch , DebugLoc DL ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; unsigned NewOpcode = ( ( ( unsigned ) Branch -> getOpcode ( ) ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & NewDesc = TII -> get ( NewOpcode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Branch , DL , NewDesc ) ; MIB . addReg ( Branch -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MIB . addMBB ( Branch -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; Iter tmpIter = Branch ; Branch = std :: prev ( Branch ) ; MBB . erase ( tmpIter ) ; return Branch


<s> EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N0 ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT>


<s> static bool pa_callee_copies ( cumulative_args_t , const function_arg_info & ) { return !


<s> return new <ISA_LIT>LowerMASSVEntries (


<s> assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , Fast


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateVectorList ( unsigned RegNum , unsigned Count , bool isDoubleSpaced , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_VectorList ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc


<s> ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( N1C && N1C -> getAPIntValue (


<s> return ( __m128 ) __builtin_ia32_rsqrt14ps128_mask ( ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( <STR_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT>


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( Subtarget . enableLongBranchPass ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ; return true


<s> rtx tmp ; tmp = gen_rtx_PLUS ( word_mode , hard_frame_pointer_rtx , TARGET_64BIT ? GEN_INT ( - <NUM_LIT> ) : GEN_INT ( - <NUM_LIT> ) ) ; tmp = gen_rtx_MEM (


<s> if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } else { if ( SImmVal >= <NUM_LIT> && SImmVal


<s> if ( Subtarget . isTargetXPLINK64 ( ) ) return lowerDYNAMIC_STACKALLOC_XPLINK ( Op , DAG ) ; else return lowerDYNAMIC_STACKALLOC_ELF ( Op , DAG


<s> assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; SetJmp3 = nullptr ; CxxLongjmpUnwind = nullptr ; SehLongjmpUnwind = nullptr ; Cookie = nullptr ; return


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new

<ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg ,


<s> if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = ParseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ; if ( Parser . parseExpression (


<s> if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && UseSSEReg && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = <NUM_LIT> ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ROUND_UP ( size , UNITS_PER_WORD ) ; align = <NUM_LIT> ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= <NUM_LIT> * ( unsigned ) BITS_PER_WORD ) align = <NUM_LIT> * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == <NUM_LIT> ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - <NUM_LIT> ) ; incr = fold_convert ( sizetype


<s> bool isMem ( ) const { return Kind ==


<s> GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; if ( ! GEP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Value * GEPPtr = GEP -> getPointerOperand ( ) ; if ( GEPPtr -> getType ( ) -> isVectorTy ( ) ) { return nullptr ; } if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; assert ( cast < VectorType > ( Ty ) -> getNumElements ( ) == cast < VectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ) ; if ( Offsets -> getType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( cast < VectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getScalarSizeInBits ( ) < Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo


<s> return create<ISA_LIT>AsmBackend ( T , STI , MRI


<s> static <ISA_LIT>Operand CreateImm ( const MCExpr * Val ) { <ISA_LIT>Operand Res ; Res . Kind =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT>


<s> if ( NeedsWinCFI ) return invalidateWindowsRegisterPairing ( Reg1 , Reg2 , true ) ; if ( NeedsFrameRecord ) return


<s> static bool HasNestArgument ( const MachineFunction * MF ) { const Function * F = MF -> getFunction


<s> bool LoadFirstElt = ! isNullConstant ( MaskBV -> getOperand ( <NUM_LIT> ) ) ; bool LoadLastElt = ! isNullConstant ( MaskBV -> getOperand ( NumElts - <NUM_LIT> ) ) ; if ( LoadFirstElt && LoadLastElt ) { SDValue VecLd = DAG . getLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMemOperand ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , VecLd , ML -> getPassThru ( ) ) ; return DCI . CombineTo ( ML , Blend , VecLd . getValue ( <NUM_LIT> ) , true ) ; } if ( ML -> getPassThru ( ) . isUndef ( ) ) return SDValue ( ) ; if ( <STR_LIT> ( ML -> getPassThru ( ) . getNode ( ) ) ) return SDValue ( ) ; SDValue NewML = DAG . getMaskedLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMask ( ) , DAG . getUNDEF ( VT ) , ML -> getMemoryVT ( ) , ML -> getMemOperand ( ) , ML -> getExtensionType ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , NewML , ML -> getPassThru ( ) ) ; return DCI . CombineTo ( ML , Blend , NewML . getValue


<s> if ( Layout . size ( ) == <NUM_LIT> ) IsVector = false ; if ( ! IsVector ) Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return IsVector


<s> static void expandLoadStackGuard ( MachineInstrBuilder & MIB , const TargetInstrInfo & TII ) { MachineBasicBlock & MBB = * MIB -> getParent ( ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MIB -> setDebugLoc ( DL ) ; MIB -> setDesc ( TII . get (


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList (


<s> uint8_t index , base ; dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> consumedSIB ) return <NUM_LIT> ; insn -> consumedSIB = true ; switch ( insn -> addressSize ) { case <NUM_LIT> : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; case <NUM_LIT> : insn -> sibIndexBase = SIB_INDEX_EAX ; sibBaseBase = SIB_BASE_EAX ; break ; case <NUM_LIT> : insn -> sibIndexBase = SIB_INDEX_RAX ; sibBaseBase = SIB_BASE_RAX ; break ; } if ( consumeByte ( insn , & insn -> sib ) ) return - <NUM_LIT> ; index = indexFromSIB ( insn -> sib ) | ( xFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; if ( index == <NUM_LIT> ) { insn -> sibIndex = SIB_INDEX_NONE ; } else { insn -> sibIndex = ( SIBIndex ) ( insn -> sibIndexBase + index ) ; } insn -> sibScale = <NUM_LIT> << scaleFromSIB ( insn -> sib ) ; base = baseFromSIB ( insn -> sib ) | ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( base ) { case <NUM_LIT> : case <NUM_LIT> : switch ( modFromModRM ( insn -> modRM ) ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = SIB_BASE_NONE ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_8 ; insn -> sibBase = ( SIBBase ) (


<s> static const char * stripRegisterPrefix ( const char * RegName , unsigned RegNum , unsigned RegEncoding ) { if ( FullRegNames ) { if ( RegNum >= <STR_LIT> && RegNum <= <STR_LIT> ) { const char * CRBits [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return CRBits [ RegEncoding ] ; } return RegName ; } switch ( RegName [ <NUM_LIT> ] ) { case 'r'


<s> struct mep_doloop_end * end ; rtx fallthrough ; if ( loop -> begin == <NUM_LIT> || loop -> end == <NUM_LIT> || loop -> begin -> next != <NUM_LIT> ) return false ; if ( prev_real_insn ( loop -> end -> label )

!= loop -> begin -> insn ) return false ;


<s> case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : { <ISA_LIT>MCExpr :: VariantKind RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_ABS ) { if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_SABS ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( ! IsResolved ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : Value = Value >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : Value = Value >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G3 : Value = Value >> <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( RefKind & <ISA_LIT>MCExpr :: VK_NC ) Value &= <NUM_LIT> ; else if ( Value > <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; } case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc


<s> static SDValue tryConvertSVEWideCompare ( SDNode * N , <STR_LIT> CC , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDValue Comparator = N -> getOperand ( <NUM_LIT> ) ; if ( Comparator . getOpcode ( ) == <STR_LIT> || Comparator . getOpcode ( ) == <STR_LIT> ) { unsigned IID = getIntrinsicID ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Pred = N -> getOperand ( <NUM_LIT> ) ; SDValue Imm ; SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm =

DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ;


<s> return Create ( VK_<ISA_LIT>_LO16 , Expr ,


<s> if ( SymLoc == <ISA_LIT>MCExpr :: VK_GOT && ! IsNC ) return ELF :: R_AARCH64_ADR_GOT_PAGE ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_GOTTPREL && ! IsNC ) return ELF :: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_TLSDESC && ! IsNC ) return ELF :: R_AARCH64_TLSDESC_ADR_PAGE21 ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return ELF :: R_AARCH64_JUMP26 ; case <STR_LIT> : return ELF :: R_AARCH64_CALL26 ; case <STR_LIT> : if ( SymLoc == <ISA_LIT>MCExpr :: VK_GOTTPREL ) return ELF :: R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 ; return ELF :: R_AARCH64_LD_PREL_LO19 ; case <STR_LIT> : return ELF :: R_AARCH64_TSTBR14 ; case <STR_LIT> : return ELF :: R_AARCH64_CONDBR19 ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { case FK_Data_2 : return ELF :: R_AARCH64_ABS16 ; case FK_Data_4 : return ELF :: R_AARCH64_ABS32 ; case FK_Data_8 : return ELF :: R_AARCH64_ABS64 ; case <STR_LIT> : if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) return ELF :: R_AARCH64_TLSLD_ADD_DTPREL_HI12 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) return ELF :: R_AARCH64_TLSLE_ADD_TPREL_HI12 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) return ELF :: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) return ELF :: R_AARCH64_TLSLD_ADD_DTPREL_LO12 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) return ELF :: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) return ELF :: R_AARCH64_TLSLE_ADD_TPREL_LO12 ; if ( RefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) return ELF :: R_AARCH64_TLSDESC_ADD_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_ABS && IsNC ) return ELF :: R_AARCH64_ADD_ABS_LO12_NC ; report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT> : if ( SymLoc == <ISA_LIT>MCExpr :: VK_ABS && IsNC ) return ELF :: R_AARCH64_LDST8_ABS_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_DTPREL && ! IsNC ) return ELF :: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_DTPREL && IsNC ) return ELF :: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_TPREL && ! IsNC ) return ELF :: R_AARCH64_TLSLE_LDST8_TPREL_LO12 ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_TPREL && IsNC ) return ELF :: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC ; report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT> : if ( SymLoc == <ISA_LIT>MCExpr :: VK_ABS && IsNC ) return ELF :: R_AARCH64_LDST16_ABS_LO12_NC ; if ( SymLoc == <ISA_LIT>MCExpr :: VK_DTPREL && ! IsNC ) return ELF


<s> MachineBasicBlock :: iterator ItrMI = MI ; for ( auto I = std :: next ( ItrMI ) , E = BB -> end ( ) ; I != E ; ++ I ) { if ( I -> readsRegister ( <STR_LIT> ) ) return true ; if ( I -> definesRegister ( <STR_LIT> )


<s> if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo >


<s> bool runOnModule ( Module & M ) override { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n'


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> )

) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional


<s> if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , <NUM_LIT> ) ) ) term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT> ) ; } return ix86_delegitimize_address ( x


<s> static __inline vec_uchar16 spu_cntb ( vec_char16 a ) { return ( ( vec_uchar16 ) ( si_cntb ( ( qword ) ( a


<s> rtx mem_push_rtx ; rtx mem_fake_push_rtx ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_push_rtx = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; mem_push_rtx = gen_rtx_MEM ( HImode , mem_push_rtx ) ; mem_fake_push_rtx = gen_rtx_PRE_INC ( Pmode , stack_pointer_rtx ) ; mem_fake_push_rtx = gen_rtx_MEM ( HImode , mem_fake_push_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . stdarg_save_size ) for ( regno = FIRST_ARGUMENT_REGISTER ; regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS ; regno ++ ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout .


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) << S ) ) ; return MCDisassembler :: Success


<s> assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> , size , align / BITS_PER_UNIT


<s> this -> m_children -> push_back ( child


<s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; SMLoc S , E ; switch ( getLexer ( ) . getKind ( ) ) { default : { SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( parseSymbolicImmVal ( Expr ) ) return Error ( S , <STR_LIT> ) ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseVectorList ( Operands ) ; case AsmToken :: Identifier : { if ( isCondCode ) return parseCondCode ( Operands , invertCondCode ) ; if ( ! parseRegister ( Operands ) ) return false ; if ( ! parseOptionalShift ( Operands ) ) return false ; if ( ! parseOptionalExtend ( Operands ) ) return false ; const MCExpr *


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MCStreamer * S = createMachOStreamer ( Ctx , MAB , OS , Emitter , false ) ; new <ISA_LIT>TargetStreamer ( * S ) ; return S ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return create<ISA_LIT>WinCOFFStreamer ( Ctx , MAB , * Emitter , OS ) ; case Triple :: ELF : return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , TheTriple . getArch ( ) ==


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue Zext = VectorZextCombine ( N , DAG , DCI , Subtarget ) ) return Zext ; if ( SDValue R = CMPEQCombine ( N , DAG , DCI , Subtarget ) ) return R ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ( Subtarget -> hasBMI ( ) || Subtarget -> hasTBM ( ) ) && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue ( ) ; if ( isMask_64 ( Mask ) ) { uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift + MaskSize <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Shift | ( MaskSize << <NUM_LIT> ) , VT ) ) ; } } } return SDValue ( ) ; } if ( VT != <STR_LIT> && VT != <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_EVENT_CALL ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBinaryData ( <STR_LIT> ) ; const Register DestRegs [ ] = { <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) &&


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int MaskSplitCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) ,


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple T ( TT ) ; if ( T . isOSDarwin ( ) ) RM = Reloc :: DynamicNoPIC ; else RM = Reloc :: Static ; } X -> InitMCCodeGenInfo ( RM


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<s> poly8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT>


<s> rtx branch_condition_rtx ( void ) const { return condition_rtx_in_insn != NULL ? * condition_rtx_in_insn :


<s> if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MachineInstrBuilder ( MI ) ) ; MI -> getOperand ( <NUM_LIT> )


<s> static DecodeStatus DecodeT2LoadImm12 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= ( Rn << <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler ::


<s> static inline unsigned decodeSaturatePos ( unsigned Opcode , uint32_t insn ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; case <STR_LIT>


<s> } else if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { MVT CVT = <STR_LIT> ( SplatBitSize ) ; Constant * C = SplatBitSize == <NUM_LIT> ? ConstantFP :: get ( Type :: getFloatTy ( * Ctx ) , SplatValue . bitsToFloat ( ) ) : ConstantFP :: get ( Type :: getDoubleTy ( * Ctx ) , SplatValue . bitsToDouble ( ) ) ; SDValue CP = DAG . getConstantPool ( C , PVT ) ; unsigned Repeat = VT . getSizeInBits ( ) / SplatBitSize ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Brdcst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( CVT , Repeat ) , Ld ) ; return DAG . getBitcast ( VT , Brdcst ) ; } else if ( SplatBitSize > <NUM_LIT> ) { MVT CVT = VT . getScalarType ( ) ; Constant * VecC = getConstantVector ( VT , SplatValue , SplatBitSize , * Ctx ) ; SDValue VCP = DAG . getConstantPool ( VecC , PVT ) ; unsigned NumElm = SplatBitSize / VT . getScalarSizeInBits ( ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( VCP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( <STR_LIT> ( CVT , NumElm ) , dl , DAG . getEntryNode ( ) , VCP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Brdcst = DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; return DAG . getBitcast ( VT , Brdcst ) ; } } } return SDValue ( ) ; } bool ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; if ( ! ConstSplatVal && ! BVOp -> isOnlyUserOf ( Ld . getNode ( ) ) ) return SDValue ( ) ; unsigned ScalarSize = Ld . getValueSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits


<s> bool isVecListOneDWordIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( ) ) return


<s> StReg [ i ] = DefiningMI -> getOperand ( <NUM_LIT> * i + <NUM_LIT> ) . getReg ( ) ; StRegKill [ i ] = getKillRegState ( DefiningMI -> getOperand ( <NUM_LIT> * i + <NUM_LIT> ) . isKill ( ) ) ; if ( DefiningMI -> getOperand ( <NUM_LIT> * i + <NUM_LIT> ) . isImm ( ) ) { switch ( DefiningMI -> getOperand ( <NUM_LIT> * i + <NUM_LIT> ) . getImm ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , Subtarget , MOHiFlag , MOLoFlag ) ; if ( isPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , false , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) ,


<s> if ( PVT != <STR_LIT> && PVT != <STR_LIT> ) return SDValue ( ) ; int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI . isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI . setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ int64_t ( RequiredAlign


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>leTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>beTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>leTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>beTarget , create<ISA_LIT>MCRegisterInfo ) ; using <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>leTarget , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>beTarget , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>leTarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>beTarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>leTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>beTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>beTarget , create<ISA_LIT>MCInstPrinter


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( Var ) .


<s> SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef (


<s> auto ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { } ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; if ( OpFlags & <STR_LIT> ) { ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MRI . setRegClass ( ADRP . getReg (


<s> GlobalValue * GV = MO . getGlobal ( ) ; O << Mang -> getMangledName ( GV ) ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; O << Name ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) <<


<s> unsigned char <ISA_LIT>Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return <STR_LIT> ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( <NUM_LIT> ) )


<s> unsigned <ISA_LIT>TTI :: getVectorInstrCost ( unsigned Opcode , Type * Val , unsigned Index ) const { assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; if ( ST -> hasVSX ( ) && Val -> getScalarType ( ) -> isDoubleTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ; return TargetTransformInfo :: getVectorInstrCost ( Opcode , Val , Index ) ; } unsigned LHSPenalty = <NUM_LIT> ; if ( ISD == <STR_LIT> || ISD == <STR_LIT> ) return LHSPenalty + TargetTransformInfo :: getVectorInstrCost ( Opcode , Val , Index ) ; return TargetTransformInfo :: getVectorInstrCost ( Opcode , Val , Index


<s> int mmix_function_arg_regno_p ( int regno , int incoming ) { int first_arg_regnum = incoming ?


<s> EmitAlignment ( <NUM_LIT> ) ; printSuffixedName ( GV , <STR_LIT> , Prefix ) ; if ( Prefix ) O


<s> return ( poly64x2_t ) __builtin_neon_vreinterpretv2div4si ( ( int32x4_t


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> bool hasV8_1aOps ( ) const { return getSTI ( ) . getFeatureBits ( ) [


<s> auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op


<s> ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > <NUM_LIT> && ninsns <= <NUM_LIT> && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 ) ) return <NUM_LIT> ; else return


<s> bool saw_plus ; if ( TARGET_64BIT ) { rtx op0 = disp , op1 ; switch ( GET_CODE ( disp ) ) { case LABEL_REF : return true ; case CONST : if ( GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) != PLUS ) break ; op0 = XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ; op1 = XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) >= <NUM_LIT> * <NUM_LIT> * <NUM_LIT> || INTVAL ( op1 ) < - <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ) break ; if ( GET_CODE ( op0 ) == LABEL_REF ) return true ; if ( GET_CODE ( op0 ) != SYMBOL_REF ) break ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( op0 ) ) return false ; if ( ! SYMBOL_REF_FAR_ADDR_P ( op0 ) && SYMBOL_REF_LOCAL_P ( op0 ) ) return true ; break ; default : break ; } } if ( GET_CODE ( disp ) != CONST ) return <NUM_LIT> ; disp = XEXP ( disp , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( disp ) != UNSPEC || ( XINT ( disp , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( disp , <NUM_LIT> ) != UNSPEC_GOTOFF ) ) return <NUM_LIT> ; if ( GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) != SYMBOL_REF && GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) != LABEL_REF ) return <NUM_LIT> ; return <NUM_LIT> ; } saw_plus = false ; if ( GET_CODE ( disp ) == PLUS ) { if ( GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; disp = XEXP ( disp , <NUM_LIT> ) ; saw_plus = true ; } if ( TARGET_MACHO && darwin_local_data_pic ( disp ) ) return <NUM_LIT> ; if ( GET_CODE ( disp ) !=


<s> EVT VT = Op . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; bool CanFoldLoad = false ; if ( MayFoldVectorLoad ( V2 ) ) CanFoldLoad = true ; if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op ) ) CanFoldLoad = true ; if ( MayFoldVectorLoad ( V1 ) && MayFoldVectorLoad ( V2 ) ) CanFoldLoad = false ; if ( CanFoldLoad ) { if ( HasXMMInt && NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 ,


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 ) { const TargetRegisterClass * UseRC = ( RC ==


<s> case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return mode ; default : gcc_unreachable ( )


<s> static void handleRegMaskClobber ( const uint32_t * RegMask , MCPhysReg Reg , LOHInfo * LOHInfos ) { if ( ! MachineOperand :: clobbersPhysReg ( RegMask ,


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case (

<STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI ) ; return <NUM_LIT>


<s> if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) return false ; bool IsEVEX_V128 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ! ( Desc . TSFlags & <STR_LIT> ) ) ; bool IsEVEX_V256 = ( ! ( Desc . TSFlags & <STR_LIT> ) && ( Desc . TSFlags & <STR_LIT> ) ) ; unsigned NewOpc = <NUM_LIT> ; if ( IsEVEX_V256 ) { auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc )


<s> unsigned <ISA_LIT>ELFObjectWriter :: getEFlags ( ) const { return ELF :: EF_MIPS_NOREORDER | ELF


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedGatherBaseWB ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } ,

{ Ptr , Builder . getInt32 ( Increment ) } ) ;


<s> if ( isRegIdx ( ) ) LLVM_DEBUG ( dbgs ( ) << __func__ << <STR_LIT> << ( RegIdx . RealRegister ? RegIdx . RegInfo -> getName ( RegIdx . RealRegister ) : <STR_LIT> ) << <STR_LIT> << RegIdx . RealRegister


<s> return ( int16x4_t ) __builtin_neon_vget_lowv8hi


<s> __builtin_neon_vst1_lanev4sf ( ( __builtin_neon_sf * )


<s> for ( MachineBasicBlock :: const_succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( * SI != & SuccBB ) for ( MachineBasicBlock :: livein_iterator LI = ( * SI ) -> livein_begin ( ) , LE = ( * SI ) -> livein_end ( ) ; LI


<s> } if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; Error ( SRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false


<s> if ( typesize <= <NUM_LIT> ) { return gen_rtx_REG ( mode , regbase ) ; } else { nregs = ( typesize + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; } if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs != <NUM_LIT> ) ; parms . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( parms . stack + nregs ) ) ; if ( parms . stack ) XVECEXP ( parms . ret , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; parms . nregs = <NUM_LIT> ; parms . intoffset =


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return LowerCONCAT_VECTORSvXi1 ( Op , Subtarget , DAG ) ; assert ( ( VT . is256BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> ) || ( VT . is512BitVector ( ) && ( Op .

getNumOperands ( ) == <NUM_LIT> || Op . getNumOperands ( ) == <NUM_LIT> ) ) ) ;


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > && AB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && CE , bool RelaxAll , bool IncrementalLinkerCompatible ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , std :: move ( AB ) , std :: move ( CE ) , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) .

setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ;