<s> if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; LastFI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( LastFI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Copy , Chain ) ; } if ( isVarArg ) { unsigned NumOfRegs = IsO32 ? <NUM_LIT> : <NUM_LIT> ; const uint16_t * ArgRegs = IsO32 ? O32IntRegs : <ISA_LIT>64IntRegs ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs , NumOfRegs ) ; int FirstRegSlotOffset = IsO32 ? <NUM_LIT> : - <NUM_LIT> ; const TargetRegisterClass * RC = IsO32 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned RegSize = RC -> getSize ( ) ; int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize ; int FirstVaArgOffset ; if ( IsO32 || ( Idx == NumOfRegs ) ) { FirstVaArgOffset = ( CCInfo . getNextStackOffset ( ) + RegSize - <NUM_LIT> ) / RegSize * RegSize ; } else FirstVaArgOffset = RegSlotOffset ; LastFI = MFI -> CreateFixedObject ( RegSize , FirstVaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( LastFI ) ; for ( int StackOffset = RegSlotOffset ; Idx < NumOfRegs ; ++ Idx , StackOffset += RegSize ) { unsigned Reg = AddLiveIn ( DAG . getMachineFunction ( ) , ArgRegs [ Idx ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , <STR_LIT> (


<s> assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return


<s> return ( __m256i ) __builtin_ia32_packuswb256 ( ( __v16hi ) __A , (


<s> switch_to_section ( current_function_section ( ) ) ; vlen = XVECLEN ( table , <NUM_LIT> ) ; for ( idx = <NUM_LIT> ; idx < vlen ; idx ++ ) { fputs ( <STR_LIT> , file ) ; output_asm_label ( XEXP ( XVECEXP ( table , <NUM_LIT> , idx ) , <NUM_LIT> ) ) ; fputc ( '\n' , file )


<s> } else if ( isVPTOpcode ( MI -> getOpcode ( ) ) ) { if ( MI -> getOpcode ( ) != <STR_LIT> ) { assert ( MI -> findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> && <STR_LIT> ) ; CurrentPredicate . insert ( MI ) ; } VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return false ; } bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( IsDef && ! IsUse && VCTP && ! isVCTP (


<s> <ISA_LIT>ConstantPoolSymbol :: ~ <ISA_LIT>ConstantPoolSymbol ( )


<s> if ( ! moffset ) { if ( ! rtx_equal_p ( dest , src ) ) { insn = emit_insn ( gen_rtx_SET ( dest , src ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; } return ; } if ( aarch64_uimm12_shift ( moffset ) ) { insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( moffset < <NUM_LIT> && ( ( ! temp1 && ! can_create_pseudo_p ( ) ) || ! aarch64_move_imm ( moffset , mode ) ) ) { HOST_WIDE_INT low_off = moffset &


<s> assert ( N -> isMachineOpcode ( ) && <STR_LIT> ) ; unsigned Opc = N -> getMachineOpcode ( ) ; const MCInstrDesc & MCID = getInstrInfo ( ) -> get ( Opc ) ; int CondNo = <STR_LIT> ( MCID


<s> void DecodePSWAPMask ( MVT VT , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT . getVectorNumElements ( )


<s> static SDValue performSTORECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( SDValue Split = splitStores ( N , DCI , DAG , Subtarget ) ) return Split ; if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N


<s> else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else assert ( <NUM_LIT> && <STR_LIT> ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , false , false , isKill ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e

; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = <NUM_LIT> ; return


<s> unsigned JumpOffset = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( JumpOffset ) ) ; return MCDisassembler :: Success


<s> if ( auto SwapResult = trySwapVSelectOperands ( N , DAG ) ) return SwapResult ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT CCVT = N0 . getValueType ( ) ; if ( isAllActivePredicate ( DAG , N0 ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( isAllInactivePredicate ( N0 ) ) return N -> getOperand ( <NUM_LIT> ) ; SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) == <STR_LIT> && SetCC . getOperand ( <NUM_LIT> ) == DAG . getCondCode ( <STR_LIT> ) ) { SDValue CmpLHS = SetCC . getOperand ( <NUM_LIT> ) ; EVT VT = CmpLHS . getValueType ( ) ; SDNode * CmpRHS = SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * SplatLHS = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * SplatRHS = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; APInt SplatLHSVal ; if ( CmpLHS . getValueType ( ) == N -> getOperand ( <NUM_LIT> ) . getValueType ( ) && VT . isSimple ( ) && is_contained ( makeArrayRef ( { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , VT . getSimpleVT ( ) . SimpleTy ) && <STR_LIT> ( SplatLHS , SplatLHSVal ) && SplatLHSVal . isOne ( ) && <STR_LIT> ( CmpRHS ) && <STR_LIT> ( SplatRHS ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumElts , DAG . getConstant ( VT . getScalarSizeInBits ( ) - <NUM_LIT> , SDLoc ( N ) , VT . getScalarType ( ) ) ) ; SDValue Val = DAG . getBuildVector ( VT , SDLoc ( N ) , Ops ) ; auto Shift = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CmpLHS , Val ) ; auto Or = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shift , N -> getOperand ( <NUM_LIT> ) ) ; return Or ; } } if ( N0 . getOpcode ( ) != <STR_LIT> || CCVT . getVectorElementCount ( ) != ElementCount :: getFixed ( <NUM_LIT> ) || CCVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ResVT . getSizeInBits ( ) != CmpVT . getSizeInBits ( ) ) return


<s> unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; unsigned FstHalfBegin = ( Imm & <NUM_LIT> ) * HalfSize ; unsigned SndHalfBegin = ( ( Imm >> <NUM_LIT> )


<s> std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( )


<s> if ( getParser ( ) . parseExpression ( EVal ) ) return true ; SMLoc ExprE = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( ExprE , <STR_LIT> ) ; getLexer ( ) . Lex ( ) ; const MCExpr * Res = evaluateRelocExpr ( EVal , VK ) ; if ( ! Res ) return Error ( ExprS , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Res , S , ExprE ) ) ; return false ; } else { MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier


<s> int i ; rtx x ; if ( n_elts != XVECLEN ( vals , <NUM_LIT> ) ) { rtx subtarget = target ; x = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_MODE_INNER ( GET_MODE ( x ) ) == inner_mode ) ; if ( GET_MODE_NUNITS ( GET_MODE ( x ) ) * <NUM_LIT> == n_elts ) { rtx ops [ <NUM_LIT> ] = { XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) } ; if ( inner_mode == QImode || inner_mode == HImode || inner_mode == TImode || inner_mode == HFmode || inner_mode == BFmode ) { unsigned int n_bits = n_elts * GET_MODE_SIZE ( inner_mode ) ; scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode ; n_bits /= GET_MODE_SIZE ( elt_mode ) ; mode = mode_for_vector ( elt_mode , n_bits ) . require ( ) ; inner_mode = mode_for_vector ( elt_mode , n_bits / <NUM_LIT> ) . require ( ) ; ops [ <NUM_LIT> ] = gen_lowpart ( inner_mode , ops [ <NUM_LIT> ] ) ; ops [ <NUM_LIT> ] = gen_lowpart ( inner_mode , ops [ <NUM_LIT> ] ) ; subtarget = gen_reg_rtx ( mode ) ; } ix86_expand_vector_init_concat ( mode , subtarget , ops , <NUM_LIT> ) ; if ( subtarget != target ) emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , subtarget ) ) ; return ; } gcc_unreachable ( ) ; } for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = XVECEXP ( vals


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm ,


<s> static const char * const ABICalls [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> if ( BitSize == <NUM_LIT> ) Val &= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned LZ = countLeadingZeros ( ( uint64_t ) Val ) ; unsigned Shift = ( <NUM_LIT> - LZ ) / <NUM_LIT> ; return Shift < <NUM_LIT>


<s> static const <ISA_LIT>MCExpr * createHi ( const MCExpr * Expr


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV2I64VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV2F64VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32VectorShuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT>


<s> int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - <NUM_LIT> ; reg = XEXP ( op , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( reg ) == REG && CR_REGNO_P ( REGNO ( reg ) ) ) ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = <NUM_LIT> * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; gcc_assert ( ! scc_p || code == EQ || code == GT || code == LT || code == UNORDERED || code == GTU || code == LTU ) ; switch ( code ) { case


<s> Inst . addOperand ( MCOperand :: CreateReg ( VRegs [ getReg ( ) ]


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; int NumElts = VT . getVectorNumElements ( ) ; int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; int LaneSize = NumElts


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T


<s> bool <ISA_LIT>DAGToDAGISel :: selectADDRzri ( SDValue Addr , SDValue & Base , SDValue & Index ,


<s> __builtin_ia32_pmovqb256mem_mask ( ( __v16qi * ) __P ,


<s> static SDValue MaterializeSETB ( const SDLoc & DL , SDValue EFLAGS , SelectionDAG & DAG ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL

, <STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( Pmode , a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { if ( Subtarget -> isTargetMachO ( )


<s> if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { assert ( Type == MachO :: <ISA_LIT>_RELOC_VANILLA && <STR_LIT> ) ; const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( nullptr , Fragment ->


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address , Address + imm + <NUM_LIT> , Decoder ) ; return S


<s> case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerEXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerStore ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFaddFsub ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; if ( RI -> isSubRegisterEq ( Rn , Rt2 ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> )


<s> return ; case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; if ( ! LoadNode -> isVolatile ( ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : ReplaceExtractSubVectorResults ( N , Results , DAG ) ; return ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , V ) ) ; return ; } case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE


<s> FunctionPass * llvm :: create<ISA_LIT>16ISelDag ( <ISA_LIT>TargetMachine &


<s> __rint32x ( double __a ) { return __builtin_aarch64_frint32xdf (


<s> MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? <NUM_LIT> : llvm :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase (


<s> case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; Register dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = CmpOpcode ? F -> CreateMachineBasicBlock ( LLVM_BB ) : nullptr ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; if ( CmpOpcode ) F -> insert ( It , loop2MBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; Register TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( AtomicSize == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( LoadMnemonic ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) .


<s> const MCExpr * SymbolExpr = MCSymbolRefExpr :: Create ( Label , Ctx ) ; Inst . addOperand ( MCOperand :: CreateReg ( Dest ) ) ; Inst . addOperand ( MCOperand :: CreateExpr (


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElt = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > TBLMask ; for ( int Val : ShuffleMask ) { for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; TBLMask . push_back ( DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; } } MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( V2 . getNode ( ) -> isUndef ( ) ) { if ( IndexLen == <NUM_LIT> ) V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V1Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst , DAG . getBuildVector ( IndexVT , DL , makeArrayRef ( TBLMask . data ( ) , IndexLen ) ) ) ; } else { if ( IndexLen == <NUM_LIT> ) { V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V2Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst , DAG . getBuildVector ( IndexVT , DL , makeArrayRef ( TBLMask . data ( ) , IndexLen ) ) ) ; } else


<s> case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } MachineInstr * NewMI = std :: prev ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AsmPrinter :: runOnMachineFunction ( MF ) ; return true


<s> if ( getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) return F -> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> ; else return <NUM_LIT>


<s> <ISA_LIT>_IMM :: expandMOVImm ( Imm , RegSize , Insn ) ; if ( Insn . size ( ) == <NUM_LIT> ) return false ; Imm0 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; Imm1 = Imm


<s> AddedSize += this -> getRegionSize ( ) ; return ; } bool BPChanged = false ; if ( CSRs . size ( ) > <NUM_LIT> && ( ( AddedSize + Offset ) - Scale ) > ( uint64_t ) Scale * <NUM_LIT> ) { Basereg = adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , AddedSize + Offset , true ) ; AddedSize = <NUM_LIT>


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op )


<s> unsigned count = <NUM_LIT> ; while ( * p && isspace ( * p ) && * p != '\n' ) p ++ ; count ++ ; while ( * p && * p != '\n' && strncmp ( p , BaseTAI :: CommentString , strlen ( BaseTAI :: CommentString ) ) != <NUM_LIT> ) { if ( * p == ',' ) count


<s> unsigned type = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return


<s> static __inline qword si_clgtbi ( qword a , unsigned char b ) { return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar


<s> static int stackSlotSize ( ) { return <NUM_LIT>


<s> TII = STI -> getInstrInfo ( ) ; isPositionIndependentOrROPI = STI -> getTargetLowering ( ) -> isPositionIndependent ( ) || STI -> isROPI ( ) ; AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; isThumb1 = AFI -> isThumb1OnlyFunction ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; HasFarJump = false ; bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear (


<s> SDLoc dl ( Op ) ; SDValue SatValue ; uint64_t SatConstant ; bool SatUSat ; if ( ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) && isSaturatingConditional ( Op , SatValue , SatConstant , SatUSat ) ) { if ( SatUSat ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; else return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( countTrailingOnes ( SatConstant ) , dl , VT ) ) ; } SDValue LowerSatConstant ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType (


<s> static void computeCalleeSaveRegisterPairs ( MachineFunction & MF , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI , SmallVectorImpl < RegPairInfo > & RegPairs , bool & NeedShadowCallStackProlog , bool NeedsFrameRecord ) { if ( CSI . empty ( ) ) return ; bool IsWindows = isTargetWindows ( MF ) ; bool NeedsWinCFI = needsWinCFI ( MF ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || CC == CallingConv :: CXX_FAST_TLS || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int ByteOffset = AFI -> getCalleeSavedStackSize ( ) ; int StackFillDir = - <NUM_LIT> ; int RegInc = <NUM_LIT> ; unsigned FirstReg = <NUM_LIT> ; if ( NeedsWinCFI ) { ByteOffset = <NUM_LIT> ; StackFillDir = <NUM_LIT> ; RegInc = - <NUM_LIT> ; FirstReg = Count - <NUM_LIT> ; } int ScalableByteOffset = AFI -> getSVECalleeSavedStackSize ( ) ; bool NeedGapToAlignStack = AFI -> hasCalleeSaveStackFreeSpace ( ) ; for ( unsigned i = FirstReg ; i < Count ; i += RegInc ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: GPR ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: FPR64 ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: FPR128 ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: ZPR ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: PPR ; else llvm_unreachable ( <STR_LIT> ) ; if ( unsigned ( i + RegInc ) < Count ) { Register NextReg = CSI [ i + RegInc ] . getReg ( ) ; bool IsFirst = i == FirstReg ; switch ( RPI . Type ) { case RegPairInfo :: GPR : if ( <STR_LIT> . contains ( NextReg ) && ! invalidateRegisterPairing ( RPI . Reg1 , NextReg , IsWindows , NeedsWinCFI , NeedsFrameRecord , IsFirst ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: FPR64 : if ( <STR_LIT> . contains ( NextReg ) && ! invalidateWindowsRegisterPairing ( RPI . Reg1 , NextReg , NeedsWinCFI , IsFirst ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: FPR128 : if ( <STR_LIT> . contains ( NextReg ) ) RPI


<s> op0 = force_reg ( vmode , v ) ; } } else if ( op0 != CONST0_RTX ( mode ) ) op0 = force_reg ( mode , op0 ) ; mask = ix86_build_signbit_mask ( vmode , <NUM_LIT> , <NUM_LIT> ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_const ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_const ; else copysign_insn = gen_copysigntf3_const ; emit_insn ( copysign_insn ( dest , op0 , op1 , mask ) ) ; } else { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx , rtx , rtx ) ; nmask = ix86_build_signbit_mask ( vmode , <NUM_LIT> , <NUM_LIT> ) ; mask = ix86_build_signbit_mask ( vmode , <NUM_LIT> , <NUM_LIT> ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_var ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_var ; else copysign_insn =


<s> const unsigned MAX_LOADS_IN_LDM = <NUM_LIT> ; SDValue TFOps [ MAX_LOADS_IN_LDM ] ; SDValue Loads [ MAX_LOADS_IN_LDM ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff + DstOff ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i =


<s> uint64_t Imm ; if ( isOpcWithIntImmediate ( OrOpd1 , <STR_LIT> , Imm ) && isBitfieldDstMask ( Imm , BitsToBeInserted , NumberOfIgnoredHighBits , VT ) ) Dst = OrOpd1 -> getOperand ( <NUM_LIT> ) ; else Dst = OrOpd1Val ; SDLoc DL ( N ) ; SDValue Ops [ ] = { Dst , Src , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return true ; } uint64_t Mask0Imm , Mask1Imm ; SDValue And0 = N -> getOperand ( <NUM_LIT> ) ; SDValue And1 = N -> getOperand ( <NUM_LIT> ) ; if ( And0 . hasOneUse ( ) && And1 . hasOneUse ( ) && isOpcWithIntImmediate ( And0 . getNode ( ) , <STR_LIT> , Mask0Imm ) && isOpcWithIntImmediate ( And1 . getNode ( ) , <STR_LIT> , Mask1Imm ) && APInt ( BitWidth , Mask0Imm ) == ~ APInt ( BitWidth , Mask1Imm ) && ( isShiftedMask ( Mask0Imm , VT ) || isShiftedMask ( Mask1Imm , VT ) ) ) { if ( isShiftedMask ( Mask0Imm , VT ) ) { std :: swap ( And0 , And1 ) ; std :: swap ( Mask0Imm , Mask1Imm ) ; } SDValue Src = And1 -> getOperand ( <NUM_LIT> ) ; SDValue Dst = And0 -> getOperand ( <NUM_LIT> ) ; unsigned LSB = countTrailingZeros ( Mask1Imm ) ; int Width = BitWidth - APInt ( BitWidth , Mask0Imm ) . countPopulation ( ) ; SDLoc DL ( N ) ; unsigned ShiftOpc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDNode * LSR = CurDAG -> getMachineNode ( ShiftOpc , DL , VT , Src , CurDAG -> getTargetConstant ( LSB , DL , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> , DL , VT ) ) ; unsigned ImmR = ( BitWidth - LSB ) % BitWidth ; unsigned ImmS = Width - <NUM_LIT> ; SDValue Ops [ ] = { Dst , SDValue ( LSR , <NUM_LIT> ) , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return true


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord (

false ) , HasFPExtension ( false ) , TargetTriple ( TT ) {


<s> return ( __m128d ) __builtin_ia32_haddpd ( ( __v2df ) __X , ( __v2df )


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return


<s> void Emitter < CodeEmitter > :: emitBranchInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . Opcode == <STR_LIT> ) abort ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI


<s> CONST_VECTOR_ELT ( op , i + half_units ) = temp ; } } else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = <NUM_LIT> ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = <NUM_LIT> ; j < XVECLEN ( op , i ) ; ++ j ) swap_const_vector_halves (


<s> Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . OffsetRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> if ( ( Mnemonic == <STR_LIT> && isThumb ( ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) return Mnemonic ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) { unsigned CC = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; PredicationCode = CC ; } } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size (


<s> bool isImmUnsignedi8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return true ; return isImmUnsignedi8Value ( CE ->


<s> if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rda , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: SoftFail ; if ( Rda == Rm ) return MCDisassembler :: SoftFail ; return S ; } if ( ! Check ( S , DecodetGPREvenRegisterClass ( Inst , RdaLo , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPROddRegisterClass ( Inst , RdaHi , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPREvenRegisterClass ( Inst , RdaLo ,


<s> MaskLZ -= ScaleDown ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; KnownBits Known = DAG . computeKnownBits ( X ) ; if ( MaskedHighBits != Known . Zero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; insertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL


<s> static void translateFPRegister ( MCInst & mcInst , uint8_t stackPos ) { assert ( stackPos < <NUM_LIT>


<s> bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) MIB . add ( CPSR ? t1CondCodeOp


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMemBarrierOpt ( <STR_LIT> Opt , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_MemBarrierOpt


<s> if ( set ) { x = SET_SRC ( set ) ; if ( GET_CODE ( x ) == HIGH && absolute_symbolic_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) )

return ! mips_lo_sum_offset_lookup ( htab , XEXP ( x , <NUM_LIT> ) , NO_INSERT ) ;


<s> Register Index = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineIRBuilder MIB ( I ) ; Register TargetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setJumpTableEntryInfo ( JTI , <NUM_LIT> , nullptr ) ; auto JumpTableInst = MIB . buildInstr ( <STR_LIT> , { TargetReg , ScratchReg } , { JTAddr , Index } ) . addJumpTableIndex ( JTI ) ; MIB . buildInstr ( <STR_LIT> , { } , { TargetReg } ) ; I . eraseFromParent


<s> Y = Y . getOperand ( <NUM_LIT> ) ; PeekedThroughZext = true ; } if ( ! IsSub && ! PeekedThroughZext && X . getOpcode ( ) == <STR_LIT> && Y . getOpcode ( ) != <STR_LIT> ) std :: swap ( X , Y ) ; if ( Y . getOpcode ( ) != <STR_LIT> || ! Y . hasOneUse ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) Y . getConstantOperandVal ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { SDValue SBB = materializeSBB ( Y . getNode ( ) , Y . getOperand ( <NUM_LIT> ) , DAG ) ; if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y -> getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; SDValue SBB = materializeSBB ( Y . getNode ( ) , NewEFLAGS , DAG ) ; if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; EVT ZVT = Z . getValueType ( ) ; if ( auto * ConstantX = dyn_cast < ConstantSDNode > ( X


<s> return <STR_LIT> ( Val , Start , End ) ; } } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { End = Parser . getTok ( ) . getLoc ( ) ; return <STR_LIT> ( RegNo ,


<s> const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( isa < ConstantInt > ( * RV ) ) { const Constant * C = cast < Constant > ( RV ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( C , <STR_LIT> ) ; unsigned RetReg = ValLocs [ <NUM_LIT> ] . getLocReg ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo


<s> return false ; } switch ( p_attr -> attr_type ) { case aarch64_attr_custom : gcc_assert ( p_attr -> handler ) ; if ( ! p_attr -> handler ( arg ) ) return false ; break ; case aarch64_attr_bool : { struct cl_decoded_option decoded ; generate_option ( p_attr -> opt_num , NULL , ! invert , CL_TARGET , & decoded ) ; aarch64_handle_option ( & global_options , & global_options_set , & decoded , input_location ) ; break ; } case aarch64_attr_mask : { struct cl_decoded_option decoded ; decoded . opt_index = p_attr -> opt_num ; decoded . value = ! invert ; aarch64_handle_option ( & global_options , & global_options_set , & decoded , input_location ) ; break ; } case aarch64_attr_enum : { gcc_assert ( arg ) ; bool valid ; int value ; valid = opt_enum_arg_to_value ( p_attr -> opt_num , arg , & value , CL_TARGET ) ; if ( valid ) { set_option ( & global_options , NULL , p_attr -> opt_num , value , NULL , DK_UNSPECIFIED , input_location , global_dc ) ; } else { error ( <STR_LIT> , str_to_check , arg ) ; } break ; } default : gcc_unreachable ( ) ; } } return


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr * MI ) { unsigned Idx = isPairedLdSt ( MI ) ? <NUM_LIT> :


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> && Op1 == Op0 -> getOperand ( <NUM_LIT> ) ) { SDValue Op0Op0 = Op0 -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShAmount = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ! ShAmount ) return SDValue ( ) ; if ( Op0Op0 -> getOpcode ( ) != <STR_LIT> && Op0Op0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ExtendTy = cast < VTSDNode > ( Op0Op0 -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; unsigned TotalBits = ShAmount -> getZExtValue ( )


<s> return getSubtargetImpl ( ) -> getRegisterInfo (


<s> switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : return ! strict ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : return SPE_CONST_OFFSET_OK ( offset ) ; case DFmode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; case DImode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; if ( mode == DFmode || ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; case TFmode : case TImode : if ( mode == TFmode || !


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) >>


<s> if ( Opcode == <STR_LIT> ) { unsigned Temp = Reg1 ; Reg1 = Reg2 ; Reg2 = Temp ; } I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand :: CreateReg ( Reg1 )


<s> if ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) return NULL_RTX ; return gen_rtx_REG ( Pmode


<s> Value * <ISA_LIT>IREmitter :: visitSRL_FLAG ( const SDNode


<s> if ( VECTOR_TYPE_P ( type1 ) && VECTOR_TYPE_P ( type2 ) && ! TYPE_INDIVISIBLE_P ( type1 ) && ! TYPE_INDIVISIBLE_P ( type2 ) && ( <STR_LIT> ( type1 ) != <STR_LIT> ( type2 ) ) ) return N_ ( <STR_LIT> ) ; return


<s> MCELFStreamer :: EmitValueImpl ( Value , Size , Loc ) ; Labels . clear (


<s> static inline unsigned GetCopOpc1 ( uint32_t insn , bool CDP ) { return CDP ? slice ( insn , <NUM_LIT> , <NUM_LIT> )

: slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>OptimizeLEAPass :: findLEAs ( const MachineBasicBlock & MBB , MemOpMap & LEAs ) { unsigned Pos = <NUM_LIT> ; for ( auto & MI : MBB ) { InstrPos [ & MI ] = Pos += <NUM_LIT> ; if ( isLEA ( MI ) ) LEAs [ getMemOpKey ( MI , <NUM_LIT> ) ] . push_back ( const_cast < MachineInstr * >


<s> static section * ia64_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && GET_MODE_SIZE ( mode ) <= ia64_section_threshold &&

! TARGET_NO_SDATA ) return sdata_section ;


<s> } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return nullptr ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return nullptr ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( Subtarget -> isMClass ( ) ) { int SYSmValue = getMClassRegisterMask ( SpecialReg , <STR_LIT> , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return nullptr ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; } if ( SpecialReg == <STR_LIT>


<s> SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getVectorElementType ( ) ; unsigned SrcEltBits = SrcSVT . getSizeInBits ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; const APInt & IdxC = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; if ( IdxC . uge ( NumSrcElts ) ) return SDValue ( ) ; SDValue SrcBC = peekThroughBitcasts ( Src ) ; if ( <STR_LIT> == SrcBC . getOpcode ( ) ) { SDValue SrcOp = SrcBC . getOperand ( <NUM_LIT> ) ; EVT SrcOpVT = SrcOp . getValueType ( ) ; if ( SrcOpVT . isScalarInteger ( ) && VT . isInteger ( ) && ( SrcOpVT . getSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> ) { unsigned Scale = SrcOpVT . getSizeInBits ( ) / SrcEltBits ; unsigned Offset = IdxC . urem ( Scale ) * SrcEltBits ; if ( Offset == <NUM_LIT> ) { SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , SrcVT . getScalarType ( ) ) ; SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , VT ) ; return SrcOp ; } } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && SrcBC . hasOneUse ( ) ) { auto * MemIntr = cast < MemIntrinsicSDNode > ( SrcBC ) ; unsigned SrcBCWidth = SrcBC . getScalarValueSizeInBits ( ) ; if ( MemIntr -> getMemoryVT ( ) . getSizeInBits ( ) == SrcBCWidth && VT . getSizeInBits ( ) == SrcBCWidth && SrcEltBits == SrcBCWidth ) { SDValue Load = DAG . getLoad ( VT , dl , MemIntr -> getChain ( ) , MemIntr -> getBasePtr ( ) , MemIntr -> getPointerInfo ( ) , MemIntr -> getOriginalAlign ( ) , MemIntr -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( MemIntr , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) && SrcBC . getValueType ( ) . isInteger ( ) && ( SrcBC . getScalarValueSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> && SrcBC . getScalarValueSizeInBits ( ) == SrcBC . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) { unsigned Scale = SrcBC . getScalarValueSizeInBits ( ) / SrcEltBits ; if ( IdxC . ult ( Scale ) ) { unsigned Offset = IdxC . getZExtValue ( ) * SrcVT . getScalarSizeInBits ( ) ; SDValue Scl = SrcBC . getOperand ( <NUM_LIT> ) ; EVT SclVT = Scl . getValueType ( ) ; if ( Offset


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==


<s> unsigned getBaseRegister ( ) const { return BasePtr


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder &

MIRBuilder , CallLoweringInfo & Info ) const {


<s> SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; assert ( SVT == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> void AnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn ) { IsFixed . resize ( Outs . size (


<s> const TargetRegisterClass * SizeRegClass = MRI . getRegClass ( sizeVReg ) ; unsigned tmpSizeVReg = MRI . createVirtualRegister ( SizeRegClass ) ; unsigned tmpSizeVReg2 = MRI . createVirtualRegister ( SizeRegClass ) ; unsigned physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) , tmpSizeVReg ) . addReg ( sizeVReg ) . addMBB ( BB ) . addReg ( tmpSizeVReg2 ) . addMBB ( blockMBB ) ; BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( tmpSizeVReg ) . addImm ( ProbeSize ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; BuildMI ( blockMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , tmpSizeVReg2 ) . addReg ( tmpSizeVReg ) . addImm ( ProbeSize ) ; BuildMI ( blockMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor ( testMBB ) ; BuildMI ( tailMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addReg ( tmpSizeVReg ) ; BuildMI ( tailMBB , DL , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( physSPReg ) ; tailMBB -> splice ( tailMBB -> end ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; tailMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( testMBB ) ; MI . eraseFromParent (


<s> case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND ) ) { * total = <NUM_LIT> ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = <NUM_LIT> ; return true ; } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) ; int cost , const_ok = const_ok_for_arm ( i ) ; unsigned HOST_WIDE_INT masked_const ; cost = <NUM_LIT> ; if ( ! const_ok ) cost += <NUM_LIT> ; masked_const = i & <NUM_LIT> ; if ( masked_const != <NUM_LIT> && masked_const != <NUM_LIT> ) { masked_const = i & <NUM_LIT> ; if ( masked_const == <NUM_LIT> || masked_const == <NUM_LIT> ) cost += <NUM_LIT> ; else cost


<s> if ( arm_ccfsm_state == <NUM_LIT> && ( unsigned ) arm_target_label == labelno && ! strcmp ( prefix , <STR_LIT> ) ) { arm_ccfsm_state =


<s> for ( save_mask = high = low = <NUM_LIT> , reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_regs [ reg ] && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_regs [ reg ] || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , <NUM_LIT> , <NUM_LIT> ) ) ) ) { if ( low == <NUM_LIT> ) low = reg ; high = reg ; save_mask |= <NUM_LIT> << reg ; } if ( low != <NUM_LIT> && fixed_reg == <NUM_LIT> && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < <NUM_LIT> ) { save_mask |= ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; if ( low == <NUM_LIT> ) low = <NUM_LIT> ; if ( high == <NUM_LIT> || low == high ) high = low + <NUM_LIT> ; } pushed_mask = ( HOST_WIDE_INT_M1U << low ) & ~ ( HOST_WIDE_INT_M1U << ( high + <NUM_LIT> ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = <NUM_LIT> ; * highest = <NUM_LIT> ; * register_mask =


<s> for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { MachineInstr * DefMIToErase = nullptr ; if ( TII -> convertToImmediateForm ( MI , & DefMIToErase ) ) { Changed = true ; NumRRConvertedInPreEmit ++ ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( DefMIToErase


<s> CSFPRegsSize += FGR32RegSize ; } else if ( <STR_LIT> . contains ( Reg ) ) { FPUBitmask |= ( <NUM_LIT> << RegNum ) ; CSFPRegsSize += AFGR64RegSize ; HasAFGR64Reg = true ; } else if ( <STR_LIT> . contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } FPUTopSavedRegOff = FPUBitmask ? ( HasAFGR64Reg ? - AFGR64RegSize : - FGR32RegSize ) : <NUM_LIT> ; CPUTopSavedRegOff = CPUBitmask ? - CSFPRegsSize - CPURegSize : <NUM_LIT> ; <ISA_LIT>TargetStreamer & TS =


<s> return CONST_OK_FOR_J ( value ) ; case 'K' : return CONST_OK_FOR_K ( value ) ; case 'L' : return CONST_OK_FOR_L ( value ) ; case 'M' : return CONST_OK_FOR_M ( value ) ; case 'N' : return CONST_OK_FOR_N ( value ) ; case 'O' : return CONST_OK_FOR_O ( value ) ; case 'P' : return CONST_OK_FOR_P (


<s> case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return lowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerSIGN_EXTEND_VECTOR_INREG ( Op , DAG ) ; case


<s> bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { if ( UpdateMF ) MFI . setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: get<ISA_LIT>16RetHelperMask ( ) { return


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( auto & MO : MI -> operands


<s> if ( Subtarget -> isTargetCygMing ( ) ) { TargetLowering :: ArgListTy Args ; auto & DL = CurDAG -> getDataLayout ( ) ; TargetLowering :: CallLoweringInfo CLI ( * CurDAG ) ; CLI . setChain ( CurDAG -> getRoot ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * CurDAG -> getContext ( ) ) , CurDAG -> getExternalSymbol ( <STR_LIT> , TLI -> getPointerTy ( DL ) ) , std :: move ( Args ) , <NUM_LIT> ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; std :: pair < SDValue , SDValue > Result = TLI . LowerCallTo


<s> if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , SDLoc ( LD ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD

-> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;


, Mask , Subtarget , DAG ) ) return Result ;


<s> EVT VT = BV -> getValueType ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SDValue InVec0 = DAG . getUNDEF ( VT ) ; SDValue InVec1 = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExpectedOpcode = <STR_LIT> ; unsigned NextExpectedOpcode = <STR_LIT> ; bool AddFound = false ; bool SubFound = false ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ||

! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ;


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> static void getMaxByValAlign ( Type * Ty , Align & MaxAlign , Align MaxMaxAlign ) { if ( MaxAlign == MaxMaxAlign ) return ; if ( VectorType * VTy = dyn_cast < VectorType > ( Ty ) ) { if ( MaxMaxAlign >= <NUM_LIT> && VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) >= <NUM_LIT> ) MaxAlign = Align ( <NUM_LIT> ) ; else if ( VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) >= <NUM_LIT> && MaxAlign < <NUM_LIT> ) MaxAlign = Align ( <NUM_LIT> ) ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty


<s> recovery -> push_back ( memRestoreInst ) ; unsigned int valReg = strInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned int memReg = strInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * MoveValRegM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( valReg ) . addReg ( getSlaveReg2 ( valReg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * MoveValRegD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( valReg ) ) . addReg ( getSlaveReg2 ( valReg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * MoveMemRegM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( memReg ) . addReg ( getSlaveReg2 ( memReg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * MoveMemRegD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( memReg ) ) . addReg ( getSlaveReg2 ( memReg ) ) . addImm ( <NUM_LIT> ) ; recovery -> push_back ( MoveValRegM ) ; recovery -> push_back ( MoveValRegD ) ; recovery -> push_back ( MoveMemRegM ) ; recovery -> push_back ( MoveMemRegD ) ; MachineInstr * jumpBack = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( sourceMB ) ; recovery -> push_back ( jumpBack )


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoadStoreOpt ) addPass


<s> static inline ShiftOpc getShiftOpcForNode ( SDValue N ) { switch ( N . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; unsigned NewReg = <NUM_LIT> ; int NewImm = <NUM_LIT> ; bool ATUsed ; adjust<ISA_LIT>StackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( isPIC && STI . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( RegInfo -> getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; ATUsed = expandRegLargeImmPair ( <STR_LIT> , - StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( MFI -> adjustsStack ( ) ) { expandRegLargeImmPair ( <STR_LIT> , RAOffset , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( NewImm )


<s> paddw_s ( int32x2_t s , int32x2_t t ) { return __builtin_loongson_paddw_s ( s ,


<s> rtx reg ; rtx offset ; rtx wcgr ; rtx sum ; if ( ! MEM_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( sum = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != PLUS || ! REG_P ( reg = XEXP ( sum , <NUM_LIT> ) ) || ! CONST_INT_P ( offset = XEXP ( sum , <NUM_LIT> )

) || ( ( INTVAL ( offset ) < <NUM_LIT> ) && ( INTVAL ( offset ) > - <NUM_LIT> ) ) ) return <STR_LIT> ;


<s> bool <ISA_LIT>FastISel :: is<ISA_LIT>NEONPred ( const MachineInstr * MI ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> || AFI ->

isThumb2Function ( ) ) return MI -> isPredicable ( ) ;


<s> return ( int16x8_t ) __builtin_neon_vmullsv8qi ( __a ,


<s> static bool isFunctionGlobalAddress ( SDValue Callee ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> ) return false ; return G -> getGlobal ( ) ->


<s> return __builtin_ia32_vcvtph2psx128_mask ( __A , _mm_setzero_ps ( ) , ( __mmask8 )


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo (


<s> if ( Opcode == <STR_LIT> ) { assert ( MRI -> getRegClass ( PHIInput -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == & <STR_LIT> && <STR_LIT> ) ; PHIOps . push_back ( { PHIInput -> getOperand ( <NUM_LIT> ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { Register AccReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * PHIInput -> getParent ( ) , PHIInput , PHIInput -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , AccReg ) ; PHIOps . push_back ( { MachineOperand :: CreateReg ( AccReg , false ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { assert ( ChangedPHIMap . count ( PHIInput ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * PrimedAccPHI = ChangedPHIMap . lookup ( PHIInput ) ; PHIOps . push_back ( { MachineOperand :: CreateReg ( PrimedAccPHI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } } Register AccReg = Dst


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA , E , false ,


<s> virtual void Initialize ( MCContext & Ctx , const TargetMachine


<s> return ConstantPools -> addEntry ( Streamer ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegList ( SmallVectorImpl < unsigned > & Regs , SMLoc StartLoc , SMLoc EndLoc , <ISA_LIT>AsmParser & Parser ) { assert ( Regs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; auto Op = make_unique < <ISA_LIT>Operand > ( k_RegList , Parser ) ; Op -> RegList . List = new SmallVector < unsigned , <NUM_LIT> > ( Regs . begin ( ) , Regs . end ( ) ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc


<s> SDValue ZeroC = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue AllZeros = DAG . getSplatBuildVector ( ResVT , dl , ZeroC ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , AllZeros , Promoted , ZeroC ) ; } SDValue Undef = DAG . getUNDEF ( ResVT ) ; if ( NumOfOperands > <NUM_LIT> ) { unsigned NumOfDefinedOps = <NUM_LIT> ; unsigned OpIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands ; i ++ ) if ( ! Op . getOperand ( i ) . isUndef ( ) ) { NumOfDefinedOps ++ ; OpIdx = i ; } if ( NumOfDefinedOps == <NUM_LIT> ) return Undef ; if ( NumOfDefinedOps == <NUM_LIT> ) { unsigned SubVecNumElts = Op . getOperand ( OpIdx ) . getValueType ( ) . getVectorNumElements ( ) ; SDValue IdxVal = DAG . getIntPtrConstant ( SubVecNumElts * OpIdx , dl ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , Op . getOperand ( OpIdx ) , IdxVal ) ; } MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && V1 . getValueType ( ) . getVectorNumElements ( ) == NumElems / <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getSizeInBits ( ) >= <NUM_LIT> ) return Op ; bool IsZeroV1 = <STR_LIT> ( V1 .


<s> return <STR_LIT> ( N -> getZExtValue ( )


<s> bool IsOnlyPredicatedOn ( MachineInstr


<s> case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ?


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo ( ) ,


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT>


<s> switch ( Subtarget -> getTargetABI ( ) ) { case <ISA_LIT>Subtarget :: O32 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N32 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: EABI :


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) )


<s> return getMovi32Value ( MI , MI . getOperand (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; unsigned RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) . addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , getCRFromCRBit ( DestReg ) ) . addReg ( RegO

, RegState :: Kill ) . addReg ( getCRFromCRBit ( DestReg ) , RegState :: Implicit ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( )


<s> static DecodeStatus decodeCondBrTarget ( MCInst & Inst , unsigned Imm ,


<s> return true ; } ; auto LHS = In . getOperand ( <NUM_LIT> ) ; auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; auto AVGBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , SDValue Op0 , SDValue Op1 ) { return DAG . getNode ( <STR_LIT> , DL , Op0 . getValueType ( ) , Op0 , Op1 ) ; } ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return SplitBinaryOpsAndApply ( DAG , Subtarget , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] , AVGBuilder ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT>


<s> else set = gen_rtx_SET ( reg , mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; debug_rtx ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set


<s> } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( !


<s> if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; UseOneConstNR = false


<s> assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( N -> getOpcode ( )

== <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && <STR_LIT> ) ;


<s> return CurDAG -> getRegister ( <ISA_LIT>16SPAliasReg , TLI .


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; Chain = DAG . getCopyToReg ( StackPointer . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , Sub , SDValue ( ) ) ; SDVTList VTLs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ptr = DAG . getFrameIndex ( <ISA_LIT>FI -> getDynAllocFI ( ) , getPointerTy ( ) ) ; SDValue Ops [ ] = { Chain , Ptr , Chain .


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( Is256BitVec && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; if ( NumElts == <NUM_LIT> && Is256BitVec ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++


<s> return gen_frame_set ( reg , frame_reg , offset


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection (


<s> SDValue <STR_LIT> ( SDValue Ptr , SDValue ByteStride , PackElem Part ) const { if ( Part == PackElem ::


<s> if ( OpWidth == <NUM_LIT> ) return ! Subtarget . is64Bit ( ) ; else if ( OpWidth == <NUM_LIT> ) return Subtarget . hasCmpxchg16b ( ) ; else return false


<s> tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 .

NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ;


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCMN ( MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; bool Is32Bit = ( MRI . getType ( LHS . getReg

( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isImm ( ) ) { Inst . addOperand ( MCOperand :: CreateExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; if ( ! Memory . OffsetRegNum ) { <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub ,


<s> Register Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; TII . loadRegFromStack ( MBB , I , VR , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode

:: COPY ) , Dst ) . addReg ( VR , RegState :: Kill ) ;


<s> MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Dest ) ; } unsigned ReturnReg = ( PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; BlockAddress * BA = BlockAddress :: get ( const_cast < Function * > ( MF . getFunction ( ) ) , const_cast < BasicBlock * > ( DestMBB -> getBasicBlock ( ) ) ) ; DestMBB -> setHasAddressTaken ( ) ; SDValue BlockPtr = DAG . getBlockAddress (


<s> const unsigned I = LittleEndian ? ( <NUM_LIT> - II - <NUM_LIT> ) : II ; Buffer [ <NUM_LIT> - II - <NUM_LIT> ] = uint8_t (


<s> static __inline float sh_media_FGETSCR ( void ) { float f ; __asm volatile ( <STR_LIT> :


<s> RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG


<s> <ISA_LIT>_32ATTAsmParser ( const Target & T , MCAsmParser & _Parser ) : <ISA_LIT>ATTAsmParser ( T , _Parser ) { Is64Bit =


<s> const ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C1 = C1Node -> getSExtValue ( ) ; const APInt C1C2 = C1Node -> getAPIntValue ( ) * C2Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C1 ) || isLegalAddImmediate ( C1C2 . getSExtValue ( )


<s> return <ISA_LIT>ProcFamily == IntelAtom


<s> const char * x86DisassemblerGetInstrName ( unsigned Opcode ,


<s> if ( ! optimize_size && amount != <NUM_LIT> ) return <NUM_LIT> ; if ( high_regs_pushed != <NUM_LIT> ) return <NUM_LIT> ; if ( l_mask == <NUM_LIT> && ( for_prologue || TARGET_BACKTRACE || ( live_regs_mask & <NUM_LIT> << LR_REGNUM ) == <NUM_LIT> || TARGET_INTERWORK || crtl -> args . pretend_args_size != <NUM_LIT> ) ) return <NUM_LIT> ; if ( for_prologue && ( ( flag_pic && arm_pic_register != INVALID_REGNUM ) || ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > <NUM_LIT> ) ) ) return <NUM_LIT> ; reg_base = <NUM_LIT> ; n_free = <NUM_LIT> ; if ( ! for_prologue ) { size = arm_size_return_regs ( ) ; reg_base = ARM_NUM_INTS ( size ) ; live_regs_mask >>= reg_base ; } while ( reg_base + n_free < <NUM_LIT> && ! ( live_regs_mask & <NUM_LIT> ) && ( for_prologue || call_used_regs [ reg_base + n_free ] ) ) { live_regs_mask >>= <NUM_LIT> ; n_free ++ ; } if ( n_free == <NUM_LIT> ) return <NUM_LIT> ; gcc_assert ( amount / <NUM_LIT> * <NUM_LIT> == amount ) ; if ( amount >= <NUM_LIT> && ( amount - n_free * <NUM_LIT> ) < <NUM_LIT> ) return ( amount - <NUM_LIT> ) / <NUM_LIT> ; if ( amount <= n_free * <NUM_LIT> ) return


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS


<s> case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_ES ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_FS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_GS ; break ; default : debug ( <STR_LIT> ) ; return - <NUM_LIT> ; } if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; hasOpSize = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; hasAdSize = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; default : isPrefix = FALSE ; break ; } if ( isPrefix ) dbgprintf ( insn , <STR_LIT> , byte ) ; } insn -> vexSize = <NUM_LIT> ; if ( byte == <NUM_LIT> ) { uint8_t byte1 ; if ( lookAtByte ( insn , & byte1 ) ) { dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( insn -> mode == MODE_64BIT || ( byte1 & <NUM_LIT> ) == <NUM_LIT> ) { insn -> vexSize = <NUM_LIT> ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } else { unconsumeByte ( insn ) ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } if ( insn -> vexSize == <NUM_LIT> ) { insn -> vexPrefix [ <NUM_LIT> ] = byte ; consumeByte ( insn , & insn -> vexPrefix [ <NUM_LIT> ] ) ; consumeByte ( insn , & insn -> vexPrefix [ <NUM_LIT> ] ) ; if ( insn -> mode == MODE_64BIT ) { insn -> rexPrefix = <NUM_LIT> | ( wFromVEX3of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | ( rFromVEX2of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | ( xFromVEX2of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) | ( bFromVEX2of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ) ; } switch ( ppFromVEX3of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) ) { default : break ; case VEX_PREFIX_66 : hasOpSize = TRUE


<s> inline uint8_t getBaseOpcodeFor ( uint64_t TSFlags ) { return TSFlags >>


<s> llvm :: FastISel * <STR_LIT> ( MachineFunction & mf , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < const Instruction * , <NUM_LIT> > & cil ) { return new <ISA_LIT>FastISel ( mf , vm , bm ,


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsN64 = TT . isArch64Bit ( ) && ! IsN32 ; bool HasRelocationAddend = TT . isArch64Bit ( ) ; auto * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , HasRelocationAddend , IsN64 , TT . isLittleEndian ( ) ) ; return createELFObjectWriter ( MOTW , OS , TT . isLittleEndian ( )


<s> bool has<ISA_LIT>32r6 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>32r6 ||


<s> assert ( <STR_LIT> == <STR_LIT> + NumRegs - <NUM_LIT> && <STR_LIT> ) ; reg -= <STR_LIT> ; return reg < NumRegs ? ( int )


<s> assert ( N . getOpcode ( ) == <STR_LIT> ) ; const GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( N ) ; <ISA_LIT>ISelAddressMode AM ; AM . GV = GA -> getGlobal ( ) ; AM . Disp += GA -> getOffset ( ) ; AM . SymbolFlags = GA -> getTargetFlags ( ) ; MVT VT = N . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { AM . Scale = <NUM_LIT> ; AM . IndexReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } getAddressOperands ( AM , SDLoc ( N ) , VT , Base ,


<s> assert ( getRelocationModel ( ) != Reloc :: Default && <STR_LIT> ) ; if ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { if ( is64Bit ) setRelocationModel ( Reloc :: PIC_ ) ; else if ( ! Subtarget . isTargetDarwin ( ) ) setRelocationModel ( Reloc :: Static ) ; } if ( getRelocationModel ( ) == Reloc :: Static && Subtarget . isTargetDarwin ( ) && is64Bit ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle (


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( LD -> getAlignment ( ) >= MemVT . getSizeInBits ( ) / <NUM_LIT> ) || ( ( MemVT != <STR_LIT> ) && ( MemVT != <STR_LIT> ) ) ) return SDValue ( ) ; bool IsLittle = Subtarget -> isLittle ( ) ; EVT VT = Op . getValueType ( ) ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; SDValue Chain = LD -> getChain ( ) , Undef = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) ; if ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) { SDValue LDL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return createLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = createLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT>

) || ( ExtType == <STR_LIT> ) ) return LWR ;


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( Offset


<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) const { assert ( ! Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , Op , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) , Align ( <NUM_LIT> )

, false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = <STR_LIT> ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = <NUM_LIT> ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = <STR_LIT> ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = <NUM_LIT> ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF , IsThreadLocal ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && !


<s> static bool isCalleeSavedRegister ( unsigned Reg , const MCPhysReg * CSRegs ) { for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) if ( Reg == CSRegs [ i ] ) return true ; return false


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; int NumElements = VT . getVectorNumElements ( ) ; SDLoc DL ( Op ) ; bool Is1BitVector = ( VT . getVectorElementType ( ) == <STR_LIT> ) ; assert ( ( VT . getSizeInBits ( ) != <NUM_LIT> || Is1BitVector ) && <STR_LIT> ) ; bool V1IsUndef = V1 . isUndef ( ) ; bool V2IsUndef = V2 . isUndef ( ) ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , DL , V1 , V2 , NewMask ) ; } int MaskUpperLimit = Mask . size ( ) * ( V2IsUndef ? <NUM_LIT> : <NUM_LIT> ) ; ( void ) MaskUpperLimit ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return - <NUM_LIT> <= M && M < MaskUpperLimit ; } ) && <STR_LIT> ) ; SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << getRegisterName ( MO2 . getReg


<s> void <ISA_LIT>AsmPrinter :: EmitInstrReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg ) { MCInst


<s> if ( HARD_REGNO_NREGS ( regno , mode ) == <NUM_LIT> || ! ( (

regno ) & <NUM_LIT> ) ) return <NUM_LIT> ;


<s> static SDValue getUnpackh ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { SmallVector < int , <NUM_LIT> > Mask ; createUnpackShuffleMask ( VT , Mask , false ,


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm ,


<s> if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else IAH . Out ( <STR_LIT> + Name ) ; swapFPIntParams ( PV , M , IAH , LE , false ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( LocalName + <STR_LIT> + Name ) ; new UnreachableInst ( FStub -> getContext (


<s> return ! ( TARGET_HITACHI || ca -> renesas_abi