<s> if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .

addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> bool <ISA_LIT>ElimCompare :: convertToBRCT ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = MI . getOpcode ( ) ; unsigned BRCT ; if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else return false ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get (


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( )


<s> if ( flag_split_stack ) bitmap_set_bit ( regs


<s> uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return ( code == CONST_INT && INTVAL ( index ) < CSKY_LD32_MAX_OFFSET ( SImode ) && INTVAL ( index )

>= <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget -> hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N00 , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp ) ; } } return SDValue


<s> void <ISA_LIT>AsmParser :: expandInstruction ( MCInst & Inst , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return expandLoadImm ( Inst ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw


<s> return DAG -> getVectorShuffle ( VT , dl


<s> static SDValue combine<ISA_LIT>ShufflesRecursively ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { return combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , true , DAG


<s> isCand = isCMOVWithZeroOrAllOnesLHS ( N0 , isAND ) ; if ( isCand ) std :: swap ( N0 , N1 ) ; } if ( ! isCand ) return SDValue ( ) ; unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> } else if ( dwords > numregs ) { int pushregs = numregs ; if ( TARGET_SHCOMPACT ) ca -> stack_regs += numregs ; while ( pushregs < NPARM_REGS ( SImode ) - <NUM_LIT> && ( CALL_COOKIE_INT_REG_GET ( ca -> call_cookie , NPARM_REGS ( SImode ) - pushregs ) == <NUM_LIT> ) ) { ca -> call_cookie &= ~ CALL_COOKIE_INT_REG ( NPARM_REGS ( SImode ) - pushregs , <NUM_LIT> ) ; pushregs ++ ; } if ( numregs == NPARM_REGS ( SImode ) ) ca -> call_cookie |= CALL_COOKIE_INT_REG ( <NUM_LIT> , <NUM_LIT> ) | CALL_COOKIE_STACKSEQ ( numregs - <NUM_LIT> ) ; else ca -> call_cookie |= CALL_COOKIE_STACKSEQ ( numregs ) ; } } if ( GET_SH_ARG_CLASS ( mode2 ) == SH_ARG_FLOAT && ( named || ! ca -> prototype_p ) ) { if ( mode2 == SFmode && ca -> free_single_fp_reg ) ca -> free_single_fp_reg = <NUM_LIT> ; else if ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { int numfpregs = MIN ( ( GET_MODE_SIZE ( mode2 ) + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> , NPARM_REGS ( SFmode ) - ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; ca -> arg_count [ ( int ) SH_ARG_FLOAT ] += numfpregs ; if ( TARGET_SHCOMPACT && ! ca -> prototype_p ) { if ( ca -> outgoing && numregs > <NUM_LIT> ) do { ca -> call_cookie |= ( CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - numregs + ( ( numfpregs - <NUM_LIT> ) / <NUM_LIT> ) , <NUM_LIT> + ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] - numfpregs ) / <NUM_LIT> ) ) ; } while ( numfpregs -= <NUM_LIT> ) ; } else if ( mode2 == SFmode && ( named ) && ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) ) ca ->

free_single_fp_reg = FIRST_FP_PARM_REG - numfpregs + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] + <NUM_LIT> ;


<s> SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Shift = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else cerr << <STR_LIT> ; cerr << <STR_LIT> << Disp << <STR_LIT> ; cerr << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else cerr << <STR_LIT> ; cerr << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else cerr << <STR_LIT> ; cerr << <STR_LIT> ; cerr << <STR_LIT> ; if ( ES ) cerr << ES ; else cerr << <STR_LIT> ; cerr << <STR_LIT> << JT << <STR_LIT> <<


<s> const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok .


<s> VPTBlock . advanceVPTState ( ) ; } const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { if ( CC != <STR_LIT> && ! <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , SoftFail ) ; I -> setImm ( CC ) ; ++ I


<s> SDValue HiOp = B . getOperand ( i + j + <NUM_LIT> ) ; if ( IsSigned ) { LoOp = DAG . getAnyExtOrTrunc ( LoOp , dl , <STR_LIT> ) ; HiOp = DAG . getAnyExtOrTrunc ( HiOp , dl , <STR_LIT> ) ; LoOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoOp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; HiOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiOp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { LoOp = DAG . getZExtOrTrunc ( LoOp , dl , <STR_LIT> ) ; HiOp = DAG . getZExtOrTrunc ( HiOp , dl , <STR_LIT> ) ; } LoOps . push_back ( LoOp ) ; HiOps . push_back ( HiOp ) ; } } BLo = DAG . getBuildVector ( ExVT , dl , LoOps ) ; BHi = DAG . getBuildVector ( ExVT , dl , HiOps ) ; } else if ( IsSigned ) { BLo = DAG . getBitcast ( ExVT , getUnpackl ( DAG , dl , VT , Zero , B ) ) ; BHi = DAG . getBitcast ( ExVT , getUnpackh ( DAG , dl , VT , Zero , B ) ) ; } else { BLo = DAG . getBitcast ( ExVT , getUnpackl ( DAG , dl , VT , B , Zero ) ) ; BHi = DAG . getBitcast ( ExVT , getUnpackh ( DAG , dl , VT , B , Zero ) ) ; } unsigned MulOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue RLo = DAG . getNode ( MulOpc , dl , ExVT , ALo , BLo ) ; SDValue RHi = DAG . getNode ( MulOpc ,


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address ,

Decoder ) ) ) return MCDisassembler :: Fail ;


<s> inline vector signed char vec_and ( vector signed char a1 , vector signed char a2 ) { return ( vector signed char ) __builtin_altivec_vand ( ( vector signed int


<s> static SDValue getTargetVShiftNode ( unsigned Opc , SDLoc dl , MVT VT , SDValue SrcOp , SDValue ShAmt , SelectionDAG & DAG ) { MVT SVT = ShAmt . getSimpleValueType ( ) ; assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ; if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc =


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue (


<s> static rtx rs6000_debug_legitimize_reload_address ( rtx x , machine_mode mode , int opnum , int type , int ind_levels , int * win ) { rtx ret = rs6000_legitimize_reload_address ( x , mode , opnum , type , ind_levels , win ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , GET_MODE_NAME ( mode ) , opnum , type , ind_levels


<s> bool isNameEqual ( const std :: string & Other , const FeatureBitset & FeatureBits ) const { if ( FeatureBitSet . any ( ) && ( FeatureBitSet & FeatureBits ) . none ( ) ) return false ; return Name == Other


<s> fprintf ( stream , <STR_LIT> , align / BITS_PER_UNIT ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; fprintf ( stream , <STR_LIT> , align / BITS_PER_UNIT ) ; ASM_OUTPUT_LABEL ( stream ,


<s> unsigned int f ; secname = ACONCAT ( ( <STR_LIT> , fp_ret_p ? <STR_LIT> : <STR_LIT> , fnname , NULL ) ) ; stubname = ACONCAT ( ( <STR_LIT> , fp_ret_p ? <STR_LIT> : <STR_LIT> , fnname , NULL ) ) ; stubid = get_identifier ( stubname ) ; stubdecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , stubid , build_function_type_list ( void_type_node , NULL_TREE ) ) ; set_decl_section_name ( stubdecl , secname ) ; DECL_RESULT ( stubdecl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; fprintf ( asm_out_file , <STR_LIT> , ( fp_ret_p ? ( GET_MODE ( retval ) == SFmode ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) , fnname ) ; separator = <STR_LIT> ; for ( f = ( unsigned int ) fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> , separator , ( f & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; separator = <STR_LIT> ; } fprintf ( asm_out_file , <STR_LIT> ) ; assemble_start_function ( stubdecl , stubname ) ; mips_start_function_definition ( stubname , false ) ; if ( fp_ret_p ) { fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ RETURN_ADDR_REGNUM ] ) ; } else { if ( TARGET_EXPLICIT_RELOCS ) { output_asm_insn ( <STR_LIT> , & fn ) ; output_asm_insn ( <STR_LIT> , & fn ) ; } else output_asm_insn ( <STR_LIT> , & fn ) ; } mips_output_args_xfer ( fp_code , 't' ) ; if ( fp_ret_p ) { output_asm_insn ( MIPS_CALL ( <STR_LIT> , & fn , <NUM_LIT> , - <NUM_LIT> ) , & fn ) ; fprintf ( asm_out_file , <STR_LIT> ) ; switch ( GET_MODE ( retval ) ) { case SCmode : mips_output_32bit_xfer ( 'f' , GP_RETURN + TARGET_BIG_ENDIAN , TARGET_BIG_ENDIAN ? FP_REG_FIRST + <NUM_LIT> : FP_REG_FIRST ) ; mips_output_32bit_xfer ( 'f' , GP_RETURN + TARGET_LITTLE_ENDIAN , TARGET_LITTLE_ENDIAN ? FP_REG_FIRST + <NUM_LIT> : FP_REG_FIRST ) ; if ( GET_MODE ( retval ) == SCmode && TARGET_64BIT ) { fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_RETURN + TARGET_BIG_ENDIAN ] , reg_names [ GP_RETURN + TARGET_BIG_ENDIAN ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_RETURN + TARGET_LITTLE_ENDIAN ] , reg_names

[ GP_RETURN + TARGET_LITTLE_ENDIAN ] ) ;


<s> if ( CONST_INT_P ( src ) ) { HOST_WIDE_INT val = INTVAL ( src ) ; emit_set_insn ( dest , GEN_INT ( val & <NUM_LIT> ) ) ; if ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) { emit_set_insn ( gen_rtx_ZERO_EXTRACT ( SImode , dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ; insn = get_last_insn ( ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( src ) ) ; } return ; } emit_set_insn ( dest , gen_rtx_HIGH ( SImode , src ) ) ; emit_set_insn ( dest , gen_rtx_LO_SUM ( SImode , dest ,


<s> bool need_align = true ; rtx lab ; label_ref_list_t ref ; bool have_df = false ; for ( int i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; if ( p -> mode == HImode ) { if ( need_align ) { scan = emit_insn_after ( gen_align_2 ( ) , scan ) ; need_align = false ; } for ( lab = p -> label ; lab ; lab = LABEL_REFS ( lab ) ) scan = emit_label_after ( lab , scan ) ; scan = emit_insn_after ( gen_consttable_2 ( p -> value , const0_rtx ) , scan ) ; for ( ref = p -> wend ; ref ; ref = ref -> next ) { lab = ref -> label ; scan = emit_insn_after ( gen_consttable_window_end ( lab ) , scan ) ; } } else if ( p -> mode == DFmode ) have_df = true ; } need_align = true ; if ( start ) { scan = emit_insn_after ( gen_align_4 ( ) , scan ) ; need_align = false ; for ( ; start != barrier ; start = NEXT_INSN ( start ) ) if ( NONJUMP_INSN_P ( start ) && recog_memoized ( start ) == CODE_FOR_casesi_worker_2 ) { rtx src = SET_SRC ( XVECEXP ( PATTERN ( start ) , <NUM_LIT> , <NUM_LIT> ) ) ; rtx lab = XEXP ( XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; scan = emit_label_after ( lab , scan ) ; } } if ( TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df ) { rtx_insn * align_insn = NULL ; scan = emit_label_after ( gen_label_rtx ( ) , scan ) ; scan = emit_insn_after ( gen_align_log ( GEN_INT ( <NUM_LIT> ) ) , scan ) ; need_align = false ; for ( int i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; switch ( p -> mode ) { case E_HImode : break ; case E_SImode : case E_SFmode : if ( align_insn && ! p -> part_of_sequence_p ) { for ( lab = p -> label ; lab ; lab = LABEL_REFS ( lab ) ) emit_label_before ( lab , align_insn ) ; emit_insn_before ( gen_consttable_4 ( p -> value , const0_rtx ) , align_insn ) ; for ( ref = p -> wend ; ref ; ref = ref -> next ) { lab = ref -> label ; emit_insn_before ( gen_consttable_window_end ( lab ) , align_insn ) ; } delete_insn ( align_insn ) ; align_insn = NULL ; continue ; } else { for ( lab = p -> label ; lab ; lab = LABEL_REFS ( lab ) ) scan = emit_label_after ( lab , scan ) ; scan = emit_insn_after ( gen_consttable_4 ( p -> value , const0_rtx ) ,


<s> Thumb2HazardRecognizer ( const InstrItineraryData & ItinData )


<s> __v4di mask = __extension__ ( __v4di ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> } ; return ( __m256i ) __builtin_ia32_gatherdiv4di ( src , base , ( __v4di ) index , mask ,


<s> return ( GET_CODE ( x ) == REG && ! GR_REGNO_P ( REGNO ( x ) ) && REGNO ( x ) <


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsNegativeBranch = true ; IsTestAndBranch = true ; break ; } if ( IsTestAndBranch && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; assert ( MI -> getParent ( ) && <STR_LIT> ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; if ( ! ( DefMI -> getOpcode ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ! ( DefMI -> getOpcode ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( DefMI -> findRegisterDefOperandIdx ( <STR_LIT> , true ) != - <NUM_LIT> ) return false ; <STR_LIT> CC = ( <STR_LIT> ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool CheckOnlyCCWrites = true ; if ( modifiesConditionCode ( DefMI , MI , CheckOnlyCCWrites , & getRegisterInfo ( ) ) ) return false ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI -> getOperand ( TargetBBInMI ) . getMBB ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( IsNegativeBranch ) CC = <STR_LIT> ( CC ) ; BuildMI ( RefToMBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; MI -> eraseFromParent ( ) ; return


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; <STR_LIT> CC = <STR_LIT> ; <STR_LIT> ExtraCC = <STR_LIT> ; if ( optimizeSelect ( SI ) ) return true ; if ( foldXALUIntrinsic ( CC , I , Cond ) ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; } else if ( isa < CmpInst > ( Cond ) && cast < CmpInst > ( Cond ) -> hasOneUse ( ) && isValueAvailable ( Cond ) ) { const auto * Cmp = cast < CmpInst > ( Cond ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate ( Cmp ) ; const Value * FoldSelect = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_FALSE : FoldSelect = SI -> getFalseValue ( ) ; break ; case CmpInst :: FCMP_TRUE : FoldSelect = SI -> getTrueValue ( ) ; break ; } if ( FoldSelect ) { unsigned SrcReg = getRegForValue ( FoldSelect ) ; if ( ! SrcReg ) return false ; updateValueMap ( I , SrcReg ) ; return true ; } if ( ! emitCmp ( Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> isUnsigned ( ) ) ) return false ; CC = getCompareCC ( Predicate ) ; switch ( Predicate ) { default : break ; case CmpInst ::


<s> <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; DebugLoc DL ; <STR_LIT> SpillGPRs = ZFI -> getSpillGPRRegs ( ) ; if ( SpillGPRs . LowGPR ) { assert ( SpillGPRs . LowGPR != SpillGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , SpillGPRs . LowGPR , false ) ; addSavedGPR ( MBB , MIB , SpillGPRs . HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( SpillGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } } return true


<s> MachineInstrBuilder MIB ( MF , NewMI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( i == OpNo


<s> SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , GA , NULL

, <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ; if ( Modified ) AFI -> setHasITBlocks ( true


<s> } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DefIdx << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; dumpSwapVector ( )


<s> if ( ( TheTriple . getArch ( ) == Triple :: armeb ) || ( TheTriple . getArch ( ) == Triple :: thumbeb ) ) IsLittleEndian = false ; AlignmentIsInBytes = false ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; switch ( TheTriple . getOS ( ) ) { case Triple :: Bitrig : case Triple :: NetBSD : ExceptionsType = ExceptionHandling ::


<s> assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( Subtarget -> hasSSE3 ( ) ) if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT>


<s> uint32_t Value = <NUM_LIT> ; if ( OddSPReg ) Value |= ( uint32_t ) AFL_FLAGS1_ODDSPREG ; return Value


<s> if ( ST -> hasPOPCNTD ( ) && TyWidth <= <NUM_LIT> ) return PSK_FastHardware ; return


<s> const TargetFrameLowering * TFI = MF .

getSubtarget ( ) . getFrameLowering ( ) ;


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , A ,


<s> if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return


<s> default : gcc_unreachable ( ) ; } break ; case TYPE_DIV : switch ( get_attr_size ( insn ) ) { case SIZE_32 : cost = COSTS_N_INSNS ( n - <NUM_LIT> ) + rs6000_cost -> divsi ; break ; case SIZE_64 : cost = COSTS_N_INSNS ( n - <NUM_LIT> ) + rs6000_cost -> divdi ; break ; default : gcc_unreachable ( ) ; } break ; case TYPE_FP : cost = n * rs6000_cost -> fp ; break ; case TYPE_DMUL : cost = n * rs6000_cost -> dmul ; break ; case TYPE_SDIV : cost = n * rs6000_cost


<s> bool simplifyCode ( ) { bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < AllCRLogicalOps . size ( ) ; i

++ ) Changed |= handleCROp ( AllCRLogicalOps [ i ] ) ;


<s> bool isCondCode ( ) const { return Kind


<s> } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; MakeLibCallOptions


<s> if ( ! isImm ( ) ) return false ; if ( dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ) return true ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Align = <NUM_LIT> << scale ; int64_t Max = Align * ( (


<s> uint64_t src = pIsland . getParent ( ) -> getSection ( ) . addr ( ) + pIsland . offset ( ) + pIsland . size ( ) ; if ( isValidForADRP ( src , dest ) ) { m_pData = ADRP_TEMPLATE ; m_Name = <STR_LIT> ; m_Size = sizeof ( ADRP_TEMPLATE ) ; getFixupList ( ) . clear ( ) ; addFixup ( <NUM_LIT> , <NUM_LIT> , llvm

:: ELF :: R_AARCH64_ADR_PREL_PG_HI21 ) ;


<s> return false ; } ; auto TryOptSelectCst = [ & Opc , & True , & False , & CC , Is32Bit , & MRI , & Optimized ] ( ) { if ( Optimized ) return false ; auto TrueCst = getConstantVRegValWithLookThrough ( True , MRI ) ; auto FalseCst = getConstantVRegValWithLookThrough ( False , MRI ) ; if ( ! TrueCst && ! FalseCst ) return false ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; if ( TrueCst && FalseCst ) { int64_t T = TrueCst -> Value . getSExtValue ( ) ; int64_t F = FalseCst -> Value . getSExtValue ( ) ; if ( T == <NUM_LIT> && F == <NUM_LIT> ) { Opc = Is32Bit ? <STR_LIT> : <STR_LIT> ; True = ZReg ; False = ZReg ; return true ; } if ( T == <NUM_LIT> && F == - <NUM_LIT> ) { Opc = Is32Bit ? <STR_LIT> : <STR_LIT> ; True = ZReg ; False = ZReg ; return true ; } } if ( TrueCst ) { int64_t T = TrueCst -> Value . getSExtValue ( ) ; if ( T == <NUM_LIT> ) { Opc = Is32Bit ? <STR_LIT> : <STR_LIT> ; True = False ; False = ZReg ; CC = <STR_LIT> ( CC ) ; return true ; } if ( T == - <NUM_LIT> ) { Opc = Is32Bit ? <STR_LIT> : <STR_LIT> ; True = False ; False = ZReg ; CC = <STR_LIT> ( CC ) ; return true ; } } if ( FalseCst ) { int64_t F = FalseCst -> Value . getSExtValue ( ) ; if ( F == <NUM_LIT> ) { Opc = Is32Bit ? <STR_LIT> : <STR_LIT> ; False = ZReg ; return true ; } if ( F == - <NUM_LIT> ) { Opc = Is32Bit ? <STR_LIT> : <STR_LIT> ; False = ZReg ; return true ; } } return false ; } ; Optimized |= TryFoldBinOpIntoSelect ( False , True , false ) ; Optimized |= TryFoldBinOpIntoSelect ( True , False , true ) ; Optimized |= TryOptSelectCst ( ) ; auto SelectInst = MIB . buildInstr ( Opc , { Dst } , { True , False } ) . addImm ( CC ) ; constrainSelectedInstRegOperands ( * SelectInst , TII , TRI ,


<s> return ( __A [ <NUM_LIT> ] > __B [ <NUM_LIT> ]


<s> auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI . memoperands ( ) ) ; SetCCI . eraseFromParent (


<s> unsigned OpIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands ; i ++ ) if ( ! Op . getOperand ( i ) . isUndef ( ) ) { NumOfDefinedOps ++ ; OpIdx = i ; } if ( NumOfDefinedOps == <NUM_LIT> ) return Undef ; if ( NumOfDefinedOps == <NUM_LIT> ) { unsigned SubVecNumElts = Op . getOperand ( OpIdx ) . getValueType ( ) . getVectorNumElements ( ) ; SDValue IdxVal = DAG . getIntPtrConstant ( SubVecNumElts * OpIdx , dl ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , Op . getOperand ( OpIdx ) , IdxVal ) ; } MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && V1 . getValueType ( ) . getVectorNumElements ( ) == NumElems / <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getSizeInBits (


<s> return getStandardCSEConfigForOpt ( TM -> getOptLevel


<s> DenseMap < unsigned , unsigned > :: const_iterator I = CPEClones . find ( CloneIdx ) ; if ( I != CPEClones . end ( )


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> hasCalleeSaveStackFreeSpace (


<s> if ( CM == CodeModel :: Default ) CM = RM == Reloc :: PIC_ ? CodeModel :: Medium : CodeModel :: Small ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> MCDisassembler :: DecodeStatus <ISA_LIT>GenericDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { CommentStream = & CStream ; InternalInstruction Insn ; memset ( & Insn , <NUM_LIT> , sizeof ( InternalInstruction ) ) ; Insn . bytes = Bytes ; Insn . startLocation = Address ; Insn . readerCursor = Address ; Insn . mode = fMode ; if ( Bytes . empty ( ) || readPrefixes ( & Insn ) || readOpcode ( & Insn ) || getInstructionID ( & Insn , MII . get ( ) ) || Insn . instructionID == <NUM_LIT> || readOperands ( & Insn ) ) { Size = Insn . readerCursor - Address ; return Fail ; } Insn . operands = x86OperandSets [ Insn . spec -> operands ] ; Insn . length = Insn . readerCursor


<s> if ( CONST_DOUBLE_P ( immediate ) && GET_MODE_CLASS ( mode ) == MODE_INT ) { unsigned HOST_WIDE_INT ival ; if ( ! aarch64_reinterpret_float_as_int ( immediate , & ival ) ) gcc_unreachable ( ) ; immediate = gen_int_mode ( ival , mode ) ; } machine_mode vmode ; int width = GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; vmode = aarch64_simd_container_mode ( mode ,


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <ISA_LIT>ScalarSSEf32 ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : <NUM_LIT> ; case <STR_LIT>


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectPostStoreLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( CurDAG -> getTargetConstant ( LaneNo , <STR_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return St


<s> void Warning ( SMLoc L , const Twine & Msg ) { getParser ( ) . Warning (


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; return


<s> } unsigned PtrReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( PtrReg ) . isPointer ( ) && <STR_LIT> ) ; if ( ! I . hasOneMemOperand ( ) ) return false ; const MachineMemOperand * MemOp = * I . memoperands_begin ( ) ; unsigned NumBytesToStore = MemOp -> getSize ( ) ; unsigned Opc = getStlxrOpcode ( NumBytesToStore ) ; if ( ! Opc ) return false ; auto StoreMI = MIRBuilder . buildInstr ( Opc , { StatReg } ,


<s> EVT VT = SetCC -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( SetCC ) ; if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . hasAVX2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) ) { auto BW = Subtarget . hasBWI ( ) ; EVT VecVT = OpSize == <NUM_LIT> ? ( BW ? <STR_LIT> : <STR_LIT> ) : OpSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT CmpVT = OpSize == <NUM_LIT> ? ( BW ? <STR_LIT> : <STR_LIT> ) : VecVT ; SDValue Cmp ; if ( IsOrXorXorCCZero ) { SDValue A = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue D = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp1 = DAG . getSetCC ( DL , CmpVT , A , B , <STR_LIT> ) ; SDValue Cmp2 = DAG . getSetCC ( DL , CmpVT , C , D , <STR_LIT> ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , CmpVT , Cmp1 , Cmp2 ) ; } else { SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT , Y ) ; Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY , <STR_LIT> ) ; } if ( OpSize == <NUM_LIT> && BW ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; if ( OpSize == <NUM_LIT> ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; SDValue MovMsk = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cmp ) ; SDValue FFFFs = DAG . getConstant ( OpSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> , DL ,


<s> void addSImm7s8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE


<s> unsigned Opc = MI . getOpcode ( ) ; assert ( ! ( FMA3Group . isIntrinsic ( ) && ( SrcOpIdx1 == <NUM_LIT> || SrcOpIdx2 == <NUM_LIT> ) ) && <STR_LIT> ) ; unsigned Case = getThreeSrcCommuteCase ( MI . getDesc ( ) . TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; assert ( Case < <NUM_LIT> && <STR_LIT> ) ; const unsigned Form132Index = <NUM_LIT> ; const unsigned Form213Index = <NUM_LIT> ; const unsigned Form231Index = <NUM_LIT> ; static const unsigned FormMapping [ ] [ <NUM_LIT> ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [


<s> const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) -> getParent ( ) ; unsigned char OpFlag = Subtarget . classifyGlobalReference ( nullptr , * Mod ) ; unsigned WrapperKind = <STR_LIT> ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( isPositionIndependent ( ) && ! Subtarget . is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT


<s> case <STR_LIT> : case <STR_LIT> : DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , Mask , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , Mask , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; assert ( ( KnownZero & KnownOne ) ==


<s> bool isLabelImm16 ( ) const { if ( isConstantImm ( ) ) { return isUInt < <NUM_LIT> > ( getConstantImm ( ) ) ; } return isImm ( ) && isAcceptableSymbolRef


<s> if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue GOTEntryHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTEntryHi , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , ParmReg , TGA ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TLSAddr ) ; return DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue GOTEntryHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; bool Changed = false ; CmpConv . runOnMachineFunction (


<s> } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; unsigned DefReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DefIdx << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( DefReg ) ) { int UseIdx = SwapMap [ & UseMI ] ; if ( SwapVector [ UseIdx ] . VSEMI -> getOpcode ( ) != MI -> getOpcode ( ) ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> PrivateLabelPrefix = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString =


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_simple_begin ( void ) { if ( __builtin_expect ( __builtin_tbegin ( <NUM_LIT> ) , <NUM_LIT> )


<s> int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( <STR_LIT> ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != <STR_LIT>

) for ( auto & MO : MRI -> use_nodbg_operands ( <STR_LIT> ) ) MO . setIsKill ( false ) ;


<s> return SelectShiftedRegister ( N , true , Reg , Shift


<s> bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , static_cast < EVT > ( <STR_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo (


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) .

addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VT , Ops1 , <NUM_LIT> ) ; } else


<s> return addLeaOffset ( MIB , Offset ) . addReg (


<s> warning ( <NUM_LIT> , <STR_LIT> ) ; return ; } * dash = '\0' ; comma = strchr ( dash + <NUM_LIT> , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , str ) ; return ; } last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT>


<s> int pos ; int i ; rtx_insn * tmp ; rtx load_mem , str_mem ; if ( is_store_insn ( last_scheduled_insn , & str_mem ) ) load_store_pendulum -- ; else if ( is_load_insn ( last_scheduled_insn , & load_mem ) ) load_store_pendulum ++ ; else return cached_can_issue_more ; if ( ( load_store_pendulum == <NUM_LIT> ) || ( * pn_ready <= <NUM_LIT> ) ) return cached_can_issue_more ; if ( load_store_pendulum == <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { int first_store_pos = - <NUM_LIT> ; pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) ) { rtx str_mem2 ; if ( first_store_pos == - <NUM_LIT> ) first_store_pos = pos ; if ( is_store_insn ( last_scheduled_insn , & str_mem2 ) && adjacent_mem_locations ( str_mem , str_mem2 ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initSubtargetFeatures ( CPU , FS


<s> static const __vector unsigned int __perm_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __result = ( ( __vector unsigned long long ) vec_vbpermq ( ( __vector unsigned char ) __A , ( __vector unsigned char ) __perm_mask ) ) ; return __result [ <NUM_LIT> ] ; return __result [


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case


__v4si ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getSpillTarget ( ) const { return Subtarget . hasP9Vector ( ) ? <NUM_LIT>


<s> unsigned NEONThumb2DupPostEncoder ( const MachineInstr & MI ,


<s> Fits = true ; } else if ( ( NumBytes & <NUM_LIT> ) == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) ; BaseReg = <STR_LIT> ; continue ; } if ( BaseReg == <STR_LIT>


<s> const static unsigned NumOps = <NUM_LIT> ; const static bool S = true ; const static bool U = false ; const static unsigned Copy = TargetOpcode :: COPY ; const static struct DivRemEntry { const TargetRegisterClass * RC ; unsigned LowInReg ; unsigned HighInReg ; struct DivRemResult { unsigned OpDivRem ; unsigned OpSignExtend ; unsigned OpCopy ; unsigned DivRemResultReg ; bool IsOpSigned ; } ResultTable [ NumOps ] ; } OpTable [ NumTypes ] = { { & <STR_LIT> , <STR_LIT> , <NUM_LIT> , { { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , S } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , S } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , U } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , } ; MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned TypeIndex , OpIndex ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; if ( ! Subtarget -> is64Bit ( ) ) return false ; break ; } switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SDiv : OpIndex = <NUM_LIT> ; break ; case Instruction :: SRem : OpIndex = <NUM_LIT> ; break ; case Instruction :: UDiv : OpIndex = <NUM_LIT> ; break ; case Instruction :: URem : OpIndex =


<s> __rv . __o = __builtin_neon_vld3_dupv4hi ( ( const __builtin_neon_hi * ) __a ) ; return __rv .


<s> unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue Symbol = withTargetFlags ( Op , callTF , DAG ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Callee , Symbol , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getRegisterMask ( Mask ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> enum rs6000_reg_type from_type , to_type ; bool altivec_p = ( ( from_class == ALTIVEC_REGS ) || ( to_class == ALTIVEC_REGS ) ) ; from_type = reg_class_to_reg_type [ ( int ) from_class ] ; to_type = reg_class_to_reg_type [ ( int ) to_class ] ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , ( secondary_reload_info * ) <NUM_LIT> , altivec_p ) ) return false ; if ( IS_FP_VECT_REG_TYPE ( from_type ) || IS_FP_VECT_REG_TYPE ( to_type ) ) return true ; return


<s> unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; } if ( Subtarget -> isABI_O32 ( ) ) { if ( RegVT == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; if ( RegVT == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , VA . getLocReg ( ) + <NUM_LIT> , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordLoadArgsFI ( FI , - ( ArgSize + ( FirstStackArgLoc + VA . getLocMemOffset ( ) ) ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg (


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i


<s> bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT>


<s> case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = getFMA3Group ( MI . getOpcode ( ) , MI


<s> switch ( MI -> getOpcode ( ) ) { default : break ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O ,


<s> static const MCPhysReg IntRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const <ISA_LIT>CCState * <ISA_LIT>State = static_cast < <ISA_LIT>CCState * > ( & State ) ; static const MCPhysReg F32Regs [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg FloatVectorIntRegs [ ] = { <STR_LIT> , <STR_LIT> } ; if ( ArgFlags . isByVal ( ) ) return true ; if ( ArgFlags . isInReg ( ) && ! Subtarget . isLittle ( ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; bool isVectorFloat = <ISA_LIT>State -> WasOriginalArgVectorFloat ( ValNo ) ; if ( ValVT ==


<s> SDLoc DL ( Op ) ; EVT DstTy = Op . getValueType ( ) ; SDValue Value = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT TheVT = Value . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return SDValue ( ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> ; if ( ! IsSigned && DstTy != <STR_LIT> ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; if ( IsStrict ) Chain = Op . getOperand ( <NUM_LIT> ) ; else Chain = DAG . getEntryNode ( ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue Sub ; if ( IsStrict ) { Sub = DAG . getNode ( <STR_LIT> , DL , { TheVT , <STR_LIT> } , { Chain , Value , ThreshVal


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) if ( dyn_cast < ConstantSDNode > ( Bvec -> getOperand ( i ) ) != FirstElt ) return false ; ConstVal = FirstElt -> getZExtValue (


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) { unsigned idx = Count - i - <NUM_LIT> ; unsigned Reg1 = CSI [ idx ] . getReg ( ) ; unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ idx ] . getFrameIdx ( ) << <STR_LIT> << CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ; const int Offset = ( i == <NUM_LIT> ) ? - Count : i ; assert ( ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( StrOpc == <STR_LIT> || StrOpc == <STR_LIT> ) MIB . addReg ( <STR_LIT> , RegState :: Define ) ; MBB . addLiveIn ( Reg1 ) ; MBB . addLiveIn (


<s> unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op ) ) ; unsigned IntReg = <ISA_LIT>MoveToIntReg ( DstVT , ResultReg ) ; if ( IntReg == <NUM_LIT> )


<s> return __builtin_mve_vldrhq_uv8hi ( ( __builtin_neon_hi * )


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> static MCSymbolizer * create<ISA_LIT>ExternalSymbolizer ( const Triple & TT , LLVMOpInfoCallback GetOpInfo , LLVMSymbolLookupCallback SymbolLookUp , void * DisInfo , MCContext * Ctx , std :: unique_ptr < MCRelocationInfo > && RelInfo ) { return new llvm :: <ISA_LIT>ExternalSymbolizer ( * Ctx , move (

RelInfo ) , GetOpInfo , SymbolLookUp , DisInfo ) ;


<s> return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction (

) -> hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( )


<s> unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( ) ) ) { MCOperand CalleeMCOp ; switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress


<s> Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - <NUM_LIT> || MemOffset > <NUM_LIT> ) { expandMemInst ( Inst , IDLoc , Instructions , MCID .


<s> for ( unsigned i = OpNo ; i < Inst . getNumOperands ( ) ; ++ i ) { unsigned OpReg = Inst . getOperand ( i ) . getReg ( ) ; if ( OpReg == Reg ) containsReg = true ; if ( ! is<ISA_LIT>LowRegister ( OpReg ) && ( ! HiReg || OpReg != HiReg ) ) return true ; } return false


<s> const SDNodeFlags Flags = N -> getFlags ( ) ; if ( Flags . hasVectorReduction ( ) ) { if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; if ( SDValue MAdd = combineLoopMAddPattern ( N , DAG , Subtarget ) ) return MAdd ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , true ) && shouldUseHorizontalOp ( Op0 == Op1 , DAG , Subtarget ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HADDBuilder ) ; } if ( SDValue V = combineIncDecVector ( N


<s> unsigned getMemOffsetReg ( ) const { assert ( isMem ( ) && <STR_LIT> ) ; return Mem .


<s> if ( count != <NUM_LIT> ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode


<s> Parser . EatToEndOfStatement ( ) ; return Error ( Loc , ErrorMsg


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( CC == CallingConv :: CFGuard_Check ) return CSR_Win_AAPCS_CFGuard_Check_RegMask ; if ( CC == CallingConv :: SwiftTail ) { return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftTail_RegMask


<s> } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return ; if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; unsigned NewReg = ScratchFPReg ; duplicateToTop ( FirstFPRegOp , NewReg , MI ) ; FirstFPRegOp = NewReg ; } assert ( StackTop == <NUM_LIT> && <STR_LIT> ) ; if ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp ) { assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; moveToTop ( FirstFPRegOp , MI ) ; } assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; assert ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp &&


<s> else cfun -> machine -> frame_filler = <NUM_LIT> ; if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return reg_save_size + cfun -> machine -> regsave_filler ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return cfun -> machine -> frame_filler + frame_size ; if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return reg_save_size + cfun -> machine -> regsave_filler + cfun ->


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock (


<s> emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , StackOffset :: getFixed ( Amount ) , TII ) ; } } else if ( CalleePopAmount != <NUM_LIT> ) { assert ( CalleePopAmount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , StackOffset :: getFixed ( - ( int64_t ) CalleePopAmount ) , TII ) ; } return MBB . erase ( I


<s> static inline bool mode_supports_vmx_dform ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX

] & RELOAD_REG_OFFSET ) != <NUM_LIT> ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass (


<s> storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex


<s> Acc = CreateSMLADCall ( VecLd0 , VecLd1 , Acc , InsertAfter ) ; InsertAfter = Acc ; } if ( Acc != Reduction . Phi ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; Reduction . AccIntAdd -> replaceAllUsesWith ( Acc ) ; return true


<s> static void ia64_file_start ( void ) { ia64_flag_var_tracking = flag_var_tracking ; flag_var_tracking = <NUM_LIT> ; default_file_start ( ) ; emit_safe_across_calls ( )


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; int Immediate = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int Shift = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ParamLoadedValue ( MachineOperand :: CreateImm ( Immediate << Shift )


<s> switch ( CC ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned FGR32RegSize = <STR_LIT> . getSize ( ) ; unsigned AFGR64RegSize = <STR_LIT> . getSize ( ) ; bool HasAFGR64Reg = false ; unsigned CSFPRegsSize = <NUM_LIT> ; for ( const auto & I : CSI ) { unsigned Reg = I . getReg ( ) ; unsigned RegNum = TRI -> getEncodingValue ( Reg ) ; if ( <STR_LIT> . contains ( Reg ) ) { FPUBitmask |= ( <NUM_LIT>


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> std :: unique_ptr < TargetInstrInfo :: PipelinerLoopInfo > <ISA_LIT>InstrInfo :: analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const { MachineBasicBlock :: iterator I = LoopBB -> getFirstTerminator ( ) ; MachineBasicBlock * Preheader = * LoopBB -> pred_begin ( ) ; if ( Preheader == LoopBB ) Preheader = * std :: next ( LoopBB -> pred_begin ( ) ) ; MachineFunction * MF = Preheader -> getParent ( ) ; if ( I != LoopBB -> end ( ) && isBDNZ ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited ; if ( MachineInstr * LoopInst = findLoopInstr ( * Preheader , Visited ) ) { Register LoopCountReg = LoopInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; return std :: make_unique < <ISA_LIT>PipelinerLoopInfo > ( LoopInst , & * I , LoopCount ) ; } } return


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredMingwAlloca ( MachineInstr * MI , MachineBasicBlock * BB , DenseMap < MachineBasicBlock * , MachineBasicBlock * > * EM ) const { const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * F = BB


<s> static bool mips_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode


<s> return gen_rtx_PLUS ( Pmode , sum , GEN_INT ( low_int ) ) ; } else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( ( TARGET_HARD_FLOAT && TARGET_FPRS ) || TARGET_POWERPC64 || ( ( ( mode != DImode && mode != DFmode ) || TARGET_E500_DOUBLE ) && mode != TFmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && mode != TImode ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( ALTIVEC_VECTOR_MODE ( mode ) ) { rtx reg ; if ( GET_CODE ( x ) == PLUS ) return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) , force_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; reg = force_reg ( Pmode , x ) ; return reg ; } else if ( SPE_VECTOR_MODE ( mode ) || ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DImode ) ) ) { if ( mode == DImode ) return NULL_RTX ; if ( GET_CODE ( x ) == PLUS ) { rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; op1 = force_reg ( Pmode , op1 ) ; if ( GET_CODE ( op2 ) != REG && ( GET_CODE ( op2 ) != CONST_INT || ! SPE_CONST_OFFSET_OK ( INTVAL ( op2 ) ) ) ) op2 = force_reg ( Pmode , op2 ) ; return gen_rtx_PLUS ( Pmode , op1 , op2 ) ; } return force_reg ( Pmode , x ) ; } else if ( TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic && GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> || ( ( TARGET_HARD_FLOAT && TARGET_FPRS ) && mode == DFmode ) ) ) { rtx reg = gen_reg_rtx


<s> if ( GET_CODE ( symbol ) == PLUS && CONST_INT_P ( XEXP ( symbol , <NUM_LIT> ) ) ) symbol = XEXP ( symbol , <NUM_LIT> ) ; if ( GET_CODE ( symbol ) == LABEL_REF || ( GET_CODE ( symbol ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( symbol ) == <NUM_LIT> ) || ( GET_CODE ( symbol ) == UNSPEC && ( XINT ( symbol , <NUM_LIT> ) == UNSPEC_GOTPCREL || XINT ( symbol , <NUM_LIT> ) == UNSPEC_PCREL || XINT ( symbol , <NUM_LIT> ) == UNSPEC_GOTNTPOFF ) ) ) return true ; } } return false


<s> op = copy_insn ( op ) ; for_each_rtx ( & op , mips_rewrite_small_data_1 , <NUM_LIT> ) ; return


<s> bool isMemOffs64 ( ) const { return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size || Mem . Size


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT>


<s> static bool sh_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( <NUM_LIT> && ( ! TARGET_SHCOMPACT || crtl -> args . info . stack_regs == <NUM_LIT> ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || ( decl && ! TREE_PUBLIC ( decl )

) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ;


<s> rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , <NUM_LIT> ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , <NUM_LIT> ) == UNSPEC_TP ) { addr_space_t as = DEFAULT_TLS_SEG_REG ; * x = XEXP ( * x , <NUM_LIT> - i ) ; * loc = replace_equiv_address_nv ( * loc , addr , true ) ; set_mem_addr_space ( * loc , as ) ; return ; } } x = & XEXP ( *


<s> MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_FRAME_INDEX ) { addOffset ( MIB , <NUM_LIT> ) ; } else { MachineOperand & InxOp = I . getOperand ( <NUM_LIT> ) ; I . addOperand ( InxOp ) ; InxOp . ChangeToImmediate ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } return constrainSelectedInstRegOperands ( I , TII , TRI , RBI


<s> assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue FltOfs = DAG . getSelect ( DL , TheVT , Cmp , DAG . getConstantFP ( <NUM_LIT> , DL , TheVT ) , ThreshVal ) ; if ( IsStrict ) { Value = DAG . getNode ( <STR_LIT> , DL , { TheVT , <STR_LIT> } , { Chain , Value , FltOfs } ) ; Chain = Value . getValue ( <NUM_LIT> ) ; } else Value = DAG . getNode ( <STR_LIT> , DL , TheVT , Value , FltOfs ) ; } MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MPI ) ; SDVTList Tys = DAG . getVTList ( TheVT , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot } ; unsigned FLDSize = TheVT . getStoreSize ( ) ; assert ( FLDSize <= MemSize && <STR_LIT> ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , FLDSize , FLDSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , TheVT , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , MemSize , MemSize ) ; SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , DstTy , MMO ) ; SDValue Res = DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MPI ) ; Chain = Res . getValue


<s> EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( InVT . isScalableVector ( ) || ! useSVEForFixedLengthVectorVT ( InVT ) ) return SDValue


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedDisjointWriteback = true ; WritebackReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Val & ( <NUM_LIT> << i ) ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , i , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( NeedDisjointWriteback && WritebackReg == Inst . end ( ) [ - <NUM_LIT> ] . getReg ( ) ) Check ( S , MCDisassembler :: SoftFail ) ; } } return S


<s> return PA_HARD_REGNO_MODE_OK ( regno , mode


<s> int MaskUpperLimit = OrigMask . size ( ) * ( V2IsUndef ? <NUM_LIT> : <NUM_LIT> ) ; ( void ) MaskUpperLimit ; assert ( llvm :: all_of ( OrigMask , [ & ] ( int M ) { return - <NUM_LIT> <= M && M < MaskUpperLimit ; } ) && <STR_LIT> ) ; APInt KnownUndef , KnownZero ; computeZeroableShuffleElements ( OrigMask , V1 , V2 , KnownUndef , KnownZero ) ; APInt Zeroable = KnownUndef | KnownZero ; if ( Zeroable . isAllOnesValue ( ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; bool V2IsZero = ! V2IsUndef && <STR_LIT> ( V2 . getNode ( ) ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( OrigMask , Zeroable , V2IsZero , WidenedMask ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , OrigMask , Subtarget , DAG ) ) return Broadcast ; MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( find ( WidenedMask , SM_SentinelZero ) != WidenedMask . end ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; if ( canonicalizeShuffleMaskWithCommute ( Mask ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; switch ( fcode ) { case IA64_BUILTIN_BSP : if ( ! target || ! register_operand ( target , DImode ) ) target = gen_reg_rtx ( DImode ) ; emit_insn ( gen_bsp_value ( target ) ) ; target = convert_memory_address ( ptr_mode , target ) ; return target ; case IA64_BUILTIN_FLUSHRS : emit_insn ( gen_flushrs ( ) ) ; return const0_rtx


<s> int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + <NUM_LIT> ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return false ; std :: string LowerReg = Tok . getString ( ) . lower ( ) ; size_t DotPos = LowerReg . find ( '.' ) ; RegNum = MatchRegisterName ( LowerReg . substr ( <NUM_LIT> , DotPos ) ) ; if ( RegNum == <STR_LIT> ) { RegNum = StringSwitch < unsigned > ( LowerReg . substr ( <NUM_LIT> , DotPos ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; } if ( RegNum == <STR_LIT> ) return false ; SMLoc S = Tok . getLoc ( ) ; RegEndLoc = SMLoc :: getFromPointer ( S . getPointer ( ) + DotPos ) ; if ( DotPos == StringRef :: npos ) { Layout = StringRef ( ) ; } else { LayoutLoc = SMLoc :: getFromPointer ( S . getPointer ( ) + DotPos + <NUM_LIT> ) ; std :: string LayoutText = LowerReg . substr ( DotPos , StringRef :: npos ) ; Layout = StringSwitch < const char * > ( LayoutText ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Layout . size ( ) == <NUM_LIT> ) { return false ; } } return true


<s> extract_insn_cached ( insn ) ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( REG_P ( recog_data . operand [ i ]

) && REGNO ( recog_data . operand [ i ] ) >= <NUM_LIT> ) return true ;


<s> MVT ExtVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( supportedVectorShiftWithBaseAmnt ( ExtVT , Subtarget , Opcode ) ) { unsigned LogicalOp = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned Logical<ISA_LIT>Op = getTargetVShiftUniformOpcode ( LogicalOp , false ) ; BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; SDValue BitMask = DAG . getConstant ( - <NUM_LIT> , dl , ExtVT ) ; BitMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , BaseShAmt , Subtarget , DAG ) ; if ( Opcode != <STR_LIT> ) BitMask = getTargetVShiftByConstNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , <NUM_LIT> , DAG ) ; BitMask = DAG . getBitcast ( VT , BitMask ) ; BitMask = DAG . getVectorShuffle ( VT , dl , BitMask , BitMask , SmallVector < int , <NUM_LIT> > ( NumElts , <NUM_LIT> ) ) ; SDValue Res = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , DAG . getBitcast ( ExtVT , R ) , BaseShAmt , Subtarget , DAG ) ; Res = DAG . getBitcast ( VT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , BitMask ) ; if ( Opcode == <STR_LIT> ) { SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , ExtVT ) ; SignMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , SignMask , BaseShAmt , Subtarget , DAG ) ; SignMask = DAG . getBitcast ( VT , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; } return Res ; } } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = <NUM_LIT> / Amt . getScalarValueSizeInBits ( ) ; std :: vector < SDValue >


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Base , Offset , OutVT } ; SDValue Load = DAG . getNode ( Opcode , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( RetVT . isInteger ( ) && ( RetVT != HwRetVt ) ) Load = DAG . getNode ( <STR_LIT> , DL , RetVT , Load . getValue ( <NUM_LIT> ) ) ; if ( RetVT . isFloatingPoint ( ) ) Load = DAG . getNode ( <STR_LIT> ,


<s> MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , MCA . getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { llvm_unreachable ( <STR_LIT>


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> static Optional < Instruction * > instCombineSVEPTest ( InstCombiner & IC , IntrinsicInst & II ) { IntrinsicInst * Op1 = dyn_cast < IntrinsicInst > ( II . getArgOperand ( <NUM_LIT> ) ) ; IntrinsicInst * Op2 = dyn_cast < IntrinsicInst > ( II . getArgOperand ( <NUM_LIT> ) ) ; if ( Op1 && Op2 && Op1 -> getIntrinsicID ( ) == <STR_LIT> && Op2 -> getIntrinsicID ( ) == <STR_LIT> && Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) == Op2 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Value * Ops [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) , Op2 -> getArgOperand ( <NUM_LIT> ) } ; Type * Tys [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; auto * PTest = Builder . CreateIntrinsic ( II . getIntrinsicID ( ) , Tys , Ops ) ; PTest -> takeName ( & II ) ; return IC . replaceInstUsesWith (


<s> MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Add ,

DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>QPXLoadSplatPass ( )


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ) return false ; return


<s> if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = get<ISA_LIT>SubSuperRegister ( RegNo , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo


<s> setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( std :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( std :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn =


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> hasStackRealignment ( * MF ) ) return true ; return findScratchNonCalleeSaveRegister ( TmpMBB


<s> } else return ; } else return ; } gcc_assert ( ! arm_ccfsm_state || reverse ) ; if ( ! JUMP_P ( insn ) ) return ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) > <NUM_LIT> ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( reverse || ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == PC && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) ) { int insns_skipped ; int fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; rtx_insn * this_insn = start_insn ; rtx label = <NUM_LIT> ; if ( reverse ) { if ( ! seeking_return ) label = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) { label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; then_not_else = FALSE ; } else if ( ANY_RETURN_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) { seeking_return = <NUM_LIT> ; return_code = GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ; } else if ( ANY_RETURN_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) { seeking_return = <NUM_LIT> ; return_code = GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ; then_not_else = FALSE ; } else gcc_unreachable ( ) ; for ( insns_skipped = <NUM_LIT> ; ! fail && ! succeed && insns_skipped ++ < max_insns_skipped ; ) { rtx scanbody ; this_insn = next_nonnote_insn ( this_insn ) ; if ( ! this_insn ) break ; switch ( GET_CODE ( this_insn ) ) { case CODE_LABEL : if ( this_insn == label ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case BARRIER : this_insn = next_nonnote_insn ( this_insn ) ; if ( this_insn && this_insn == label ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case CALL_INSN : if ( arm_arch5t ) { fail = TRUE ; break ; } this_insn = next_nonnote_insn ( this_insn ) ; if ( this_insn && BARRIER_P ( this_insn ) ) this_insn = next_nonnote_insn ( this_insn ) ; if ( this_insn && this_insn == label && insns_skipped < max_insns_skipped ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case JUMP_INSN : scanbody = PATTERN ( this_insn ) ; if ( GET_CODE ( scanbody ) == SET && GET_CODE ( SET_DEST ( scanbody ) ) ==


<s> union { qword q ; unsigned long long l [ <NUM_LIT> ] ; } x ; x . l [ <NUM_LIT> ] = l ; return ( x


<s> return parseRegister ( Operands , RegCR


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Val = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand (


<s> case <STR_LIT> : CanFold = VT . isFloatingPoint ( ) ; break ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , SVOp -> getMask ( ) ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i