<s> case <STR_LIT> : { unsigned ShAmt = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> << ShAmt ) . addReg ( InRegLEA , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill2 = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned InRegLEA2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , InRegLEA , true , InRegLEA , false ) ; } else { if ( Subtarget . is64Bit ( ) ) InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA2 , RegState :: Define , SubReg ) . addReg ( Src2 , getKillRegState ( IsKill2 ) ) ; addRegReg ( MIB , InRegLEA , true , InRegLEA2 ,


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_<ISA_LIT>_AllRegs_Vector_SaveList : CSR_<ISA_LIT>_AllRegs_SaveList ; if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction (

) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_SaveList ;


<s> if ( Add . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Lo = Add . getOperand ( <NUM_LIT> ) ; if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType (


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> reverseCC ; if ( NeedsAdditionalEqualityCC ( CC , NULL , & reverseCC ) ) { std :: swap ( TrueV , FalseV ) ; } <STR_LIT> simpleCC = GetSimpleCC ( reverseCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( simpleCC , <STR_LIT> ) ) ; Ops . push_back (


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm ( )


<s> unsigned CFIIndex = MF . getMMI ( ) . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get

( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> void <ISA_LIT>LoadStoreOpt :: moveLiveRegsBefore ( const MachineBasicBlock & MBB , MachineBasicBlock :: const_iterator Before ) { if ( ! LiveRegsValid ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveOuts ( MBB ) ; LiveRegPos = MBB . end ( ) ; LiveRegsValid = true


<s> SDValue SetOrSelCC = InnerIsSel ? FalseRes : FalseRes . getOperand ( <NUM_LIT> ) ; if ( SetOrSelCC . getOpcode ( ) != <STR_LIT> && SetOrSelCC . getOpcode ( ) != <STR_LIT> ) return false ; if ( ! SetOrSelCC . hasOneUse ( ) || ( ! InnerIsSel && ! FalseRes . hasOneUse ( ) ) ) return false ; SDValue InnerLHS = SetOrSelCC . getOperand ( <NUM_LIT> ) ; SDValue InnerRHS = SetOrSelCC . getOperand ( <NUM_LIT> ) ; <STR_LIT> InnerCC = cast < CondCodeSDNode > ( SetOrSelCC . getOperand ( InnerIsSel ? <NUM_LIT> : <NUM_LIT> ) ) -> get ( ) ; if ( InnerIsSel ) { ConstantSDNode * SelCCTrueConst = dyn_cast < ConstantSDNode > ( SetOrSelCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SelCCFalseConst = dyn_cast < ConstantSDNode > ( SetOrSelCC . getOperand ( <NUM_LIT> ) ) ; if ( ! SelCCTrueConst || ! SelCCFalseConst ) return false ; int64_t SelCCTVal = SelCCTrueConst -> getSExtValue ( ) ; int64_t SelCCFVal = SelCCFalseConst -> getSExtValue ( ) ; if ( SelCCTVal == - <NUM_LIT> && SelCCFVal == <NUM_LIT> ) { std :: swap ( InnerLHS , InnerRHS ) ; } else if ( SelCCTVal != <NUM_LIT> || SelCCFVal != - <NUM_LIT> ) return false ; } if ( InnerCC == <STR_LIT> || InnerCC == <STR_LIT> ) { IsUnCmp = true ; InnerCC = ( InnerCC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } bool InnerSwapped = false ; if ( LHS == InnerRHS && RHS == InnerLHS ) InnerSwapped = true ; else if ( LHS != InnerLHS || RHS != InnerRHS ) return false ; switch ( CC ) { case <STR_LIT> : if ( ! InnerIsSel ) return false ; if ( InnerCC != <STR_LIT> && InnerCC != <STR_LIT>


<s> initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; return false


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> FixupBWInstPass ( ) : MachineFunctionPass ( ID


<s> static __inline void si_stqx ( qword a , qword b , qword c ) { vec_st ( ( vec_uchar16 ) ( a ) , si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( b ) , ( vec_uint4 ) ( c ) ) ) )

, ( vector unsigned char * ) ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MRI


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE


<s> return ( uint16x4_t ) __builtin_neon_vcvtnuv4hf (


<s> static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) return <STR_LIT> ; assert ( TT . isArch32Bit ( )


<s> assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( GV -> isWeakForLinker ( ) && GV -> isDeclaration ( ) && RelocM == Reloc :: Static ) { SDValue PoolAddr ; PoolAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr ; } if ( Alignment == <NUM_LIT> ) { const PointerType * GVPtrTy = cast < PointerType > ( GV -> getType ( ) ) ; if ( GVPtrTy -> getElementType ( ) -> isSized ( ) ) { Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) { GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getEntryNode ( ) , GlobalRef ) ; } if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalRef , DAG .


<s> static rtx iq2000_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { int reg = GP_RETURN ; machine_mode mode = TYPE_MODE ( valtype ) ; int unsignedp = TYPE_UNSIGNED ( valtype )


<s> return DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , negOp , cast < AtomicSDNode > ( Node ) -> getSrcValue ( ) ,

cast < AtomicSDNode > ( Node ) -> getAlignment ( ) ) ;


<s> if ( ExtOpCode != <STR_LIT> && ExtOpCode != <STR_LIT> && ExtOpCode != <STR_LIT> ) return SDValue ( ) ; SDValue Orig = Ext -> getOperand ( <NUM_LIT> ) ; if ( Store -> getMemoryVT ( ) != Orig -> getValueType ( <NUM_LIT> ) ) return SDValue ( ) ; return DAG . getStore ( Store -> getChain ( ) , SDLoc ( Store ) , Orig , Store -> getBasePtr ( ) , Store -> getPointerInfo ( ) , Store -> getAlign ( ) ) ; } return SDValue (


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> unsigned CondMovOpc ; const TargetRegisterClass * RC ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; unsigned Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; unsigned Src2Reg = getRegForValue ( SI -> getFalseValue ( ) ) ; unsigned CondReg = getRegForValue ( Cond ) ; if ( ! Src1Reg || ! Src2Reg || ! CondReg ) return false ; unsigned ZExtCondReg = createResultReg ( & <STR_LIT> ) ; if ( ! ZExtCondReg ) return false ; if ( ! emitIntExt ( <STR_LIT> , CondReg , <STR_LIT> , ZExtCondReg , true ) ) return false ; unsigned ResultReg = createResultReg ( RC ) ; unsigned TempReg = createResultReg ( RC ) ; if ( ! ResultReg || ! TempReg ) return false ; emitInst ( TargetOpcode :: COPY , TempReg ) . addReg ( Src2Reg ) ; emitInst ( CondMovOpc , ResultReg ) . addReg ( Src1Reg ) . addReg ( ZExtCondReg ) . addReg ( TempReg ) ; updateValueMap ( I


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ; return


<s> if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl


<s> if ( MI . isDebugValue ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( <STR_LIT> ) ) return true ; return


<s> param_string_cst = TREE_OPERAND ( EXPR_CHECK ( param_string_cst ) , <NUM_LIT> ) ; } gcc_assert ( param_string_cst ) ; if ( fn_code == IX86_BUILTIN_CPU_IS ) { tree ref ; tree field ; tree final ; unsigned int field_val = <NUM_LIT> ; unsigned int NUM_ARCH_NAMES = sizeof ( arch_names_table ) / sizeof ( struct _arch_names_table ) ; for ( i = <NUM_LIT> ; i < NUM_ARCH_NAMES ; i ++ ) if ( strcmp ( arch_names_table [ i ] . name , TREE_STRING_POINTER ( param_string_cst ) ) == <NUM_LIT> ) break ; if ( i == NUM_ARCH_NAMES ) { error ( <STR_LIT> , TREE_STRING_POINTER ( param_string_cst ) ) ; return integer_zero_node ; } field = TYPE_FIELDS ( __processor_model_type ) ; field_val = arch_names_table [ i ] . model ; if ( field_val > M_CPU_TYPE_START && field_val < M_CPU_SUBTYPE_START ) { field = DECL_CHAIN ( field ) ; field_val -= M_CPU_TYPE_START ; } if ( field_val > M_CPU_SUBTYPE_START ) { field = DECL_CHAIN ( DECL_CHAIN ( field ) ) ; field_val -= M_CPU_SUBTYPE_START ; } ref = build3 ( COMPONENT_REF , TREE_TYPE ( field ) , __cpu_model_var , field , NULL_TREE ) ; final = build2 ( EQ_EXPR , unsigned_type_node , ref , build_int_cstu ( unsigned_type_node , field_val ) ) ; return build1 ( CONVERT_EXPR , integer_type_node , final ) ; } else if ( fn_code == IX86_BUILTIN_CPU_SUPPORTS ) { tree ref ; tree array_elt ; tree field ; tree final ; unsigned int field_val = <NUM_LIT> ; unsigned int NUM_ISA_NAMES = sizeof ( isa_names_table ) / sizeof ( struct _isa_names_table ) ; for ( i = <NUM_LIT> ; i < NUM_ISA_NAMES ; i ++ ) if ( strcmp ( isa_names_table [ i ] . name , TREE_STRING_POINTER ( param_string_cst ) ) == <NUM_LIT> ) break ; if ( i == NUM_ISA_NAMES ) { error ( <STR_LIT> , TREE_STRING_POINTER ( param_string_cst ) ) ; return integer_zero_node ; } field = TYPE_FIELDS ( __processor_model_type ) ; while ( DECL_CHAIN ( field ) ) field = DECL_CHAIN ( field ) ; ref = build3 ( COMPONENT_REF , TREE_TYPE ( field ) , __cpu_model_var , field , NULL_TREE ) ; array_elt = build4 ( ARRAY_REF , unsigned_type_node , ref , integer_zero_node ,


<s> return ( __m128i ) __builtin_ia32_compressdi128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_si128 ( )


<s> std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( ) ; if ( Op != nullptr ) RegNum = Op -> getReg ( ) ; return ( Op == nullptr


<s> auto & GlobalOp = MI . getOperand ( <NUM_LIT> ) ; auto * GV = GlobalOp . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) return false ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) != <STR_LIT> ) return false ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t MinOffset = - <NUM_LIT> ; for ( auto & UseInstr : MRI . use_nodbg_instructions ( Dst ) ) { if ( UseInstr . getOpcode ( ) !=

TargetOpcode :: G_PTR_ADD ) return false ;


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) { int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; BlendMask = scaleVectorShuffleBlendMask ( BlendMask , Mask . size ( ) , Scale ) ; MVT BlendVT = VT . getSizeInBits ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , BlendVT , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } LLVM_FALLTHROUGH ; case <STR_LIT> : { int Scale = <NUM_LIT> / VT . getVectorNumElements ( ) ; BlendMask = scaleVectorShuffleBlendMask ( BlendMask , Mask . size ( ) , Scale ) ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } case <STR_LIT> : { assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT>


<s> case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; break ; } return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( * this , MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( * this , MO , ExtraCode [ <NUM_LIT> ] , O ) ; printOperand ( * this , MI , OpNo , O ) ; return false ; case 'P' : printPCRelImm ( * this , MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( * this , MI , OpNo , O , nullptr , AsmVariant ) ; return false


<s> int NumSublanesPerLane = NumSublanes / NumLanes ; int NumEltsPerSublane = NumElts / NumSublanes ; SmallVector < int , <NUM_LIT> > CrossLaneMask ; SmallVector < int , <NUM_LIT> > InLaneMask ( NumElts , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > CrossLaneMaskLarge ( NumSublanes , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcSublane = M / NumEltsPerSublane ; int DstLane = i / NumEltsPerLane ; bool Found = false ; int DstSubStart = DstLane * NumSublanesPerLane ; int DstSubEnd = DstSubStart + NumSublanesPerLane ; for ( int DstSublane = DstSubStart ; DstSublane < DstSubEnd ; ++ DstSublane ) { if ( ! isUndefOrEqual ( CrossLaneMaskLarge [ DstSublane ] , SrcSublane ) ) continue ; Found = true ; CrossLaneMaskLarge [ DstSublane ] = SrcSublane ; int DstSublaneOffset = DstSublane * NumEltsPerSublane ; InLaneMask [ i ] = DstSublaneOffset + M % NumEltsPerSublane ; break ; } if ( ! Found ) return SDValue ( ) ; } narrowShuffleMaskElts ( NumEltsPerSublane , CrossLaneMaskLarge , CrossLaneMask ) ; if ( ! CanUseSublanes ) { int NumIdentityLanes


<s> bool shouldBuildLookupTables ( ) const { return false


( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> switch ( classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) ) { case EHPersonality :: MSVC_<ISA_LIT>SEH : return <NUM_LIT> ; case EHPersonality :: MSVC_CXX : return <NUM_LIT> ; default : break ; } report_fatal_error (


<s> static bool get_memref_parts ( rtx mem , rtx * base , HOST_WIDE_INT * offset , HOST_WIDE_INT * size ) { rtx addr_rtx ; if ( MEM_SIZE_KNOWN_P ( mem ) ) * size = MEM_SIZE ( mem ) ; else return false ; addr_rtx = ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; * offset = <NUM_LIT> ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , <NUM_LIT> ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , <NUM_LIT> ) ) ; addr_rtx = XEXP (


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return StackOffset :: getFixed ( ResolveFrameIndexReference ( MF , FI , FrameReg ,


<s> int size ; const char * section ; if ( rx_small_data_limit == <NUM_LIT> ) return false ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) || DECL_COMMON ( decl ) ) return false ; section = DECL_SECTION_NAME ( decl ) ; if ( section ) return ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) || ( strcmp (


<s> Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth =


<s> if ( isa < UndefValue > ( COp ) ) { CS << <STR_LIT> ; } else if ( auto * CI = dyn_cast < ConstantInt > ( COp


<s> if ( INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) && INTVAL ( in1_idx0

) != INTVAL ( in1_idx1 ) ) return false ;


<s> return ( __m512i ) __builtin_ia32_permvarqi512_mask ( ( __v64qi ) __B , ( __v64qi ) __A , ( __v64qi ) _mm512_undefined_epi32 ( ) , ( __mmask64 )


<s> unsigned PtrSize = TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getPointerSize ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolValue ( Stubs [ i ] . second . getPointer ( )


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return InstrInfo . get


<s> } ; for ( MachineInstr & MI : reverse ( MBB ) ) { if ( MI . isPHI ( ) ) break ; if ( HasTileOperand ( MRI , MI ) ) HasUnconfigTile = true ; if ( MI . isCall ( ) && HasUnconfigTile ) { MachineBasicBlock :: iterator I ; if ( LastShapeMI && dominates ( MBB , MI , LastShapeMI ) ) I = ++ LastShapeMI -> getIterator ( ) ; else I = ++ MI . getIterator ( ) ; Config ( * I ) ; HasUnconfigTile = false ; continue ; } if ( ! isTileDef ( MRI , MI ) ) continue ; if ( LastShapeMI && dominates ( MBB , MI , LastShapeMI ) ) Config ( * ( ++ LastShapeMI -> getIterator ( ) ) ) ; MachineOperand * RowMO = & MI . getOperand ( <NUM_LIT> ) ; MachineOperand * ColMO = & MI . getOperand ( <NUM_LIT> ) ; MachineInstr * RowMI = MRI -> getVRegDef ( RowMO -> getReg ( ) ) ; MachineInstr * ColMI = MRI -> getVRegDef ( ColMO -> getReg ( ) ) ; if ( RowMI -> getParent ( ) == & MBB ) { if ( ! LastShapeMI ) LastShapeMI =


<s> unsigned getMaxInterleaveFactor ( unsigned VF ) { return ST -> getMaxInterleaveFactor


<s> OperandMatchResultTy Result = MatchOperandParserImpl ( * Operands , Mnemonic ) ; if ( Result == MatchOperand_Success ) return Result ; if ( Result == MatchOperand_ParseFail ) { Parser . eatToEndOfStatement ( ) ; return Result ; } std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( ) ; if ( ! Op ) Op =


<s> unsigned Offset = i * ScalarSize ; SDValue Ptr = DAG . getMemBasePlusOffset ( Store -> getBasePtr ( ) , Offset , DL ) ; SDValue Scl = DAG . getNode ( <STR_LIT> , DL , StoreSVT , StoredVal , DAG . getIntPtrConstant ( i , DL ) ) ; SDValue Ch = DAG . getStore ( Store -> getChain ( ) , DL , Scl , Ptr , Store -> getPointerInfo ( ) . getWithOffset ( Offset ) , MinAlign ( Alignment , Offset )

, Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> emit_stack_probe ( stack_pointer_rtx ) ; last = emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; } else { HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = size & - PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size - size ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } last = emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; release_scratch_register_on_entry ( & sr ) ; } gcc_assert ( cfun -> machine -> fs . cfa_reg != stack_pointer_rtx ) ; if ( size > <NUM_LIT> ) { rtx expr = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( expr , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - size ) ) ; XVECEXP ( expr , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope + size ) ) ; add_reg_note ( last , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( last ) = <NUM_LIT> ; cfun -> machine -> fs . sp_offset += size ; } emit_insn ( gen_blockage ( )


<s> EVT OutVT = <STR_LIT> ( <STR_LIT> ( FromBits ) , <STR_LIT> / FromBits ) ; PackedOp = DAG . getNode ( UnpackHigh , SDLoc ( PackedOp ) , OutVT , PackedOp ) ; } while ( FromBits != ToBits


<s> if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return true ; gcc_assert ( ! op_true == ! op_false ) ; if ( ! op_true || ! ix86_valid_mask_cmp_mode ( cmp_mode ) ) return false ; if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ; return true


<s> EVT ContainerVT = getContainerForFixedLengthVector ( DAG , InVT ) ; SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 ,


<s> SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue BV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , pshufbMask ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , BV ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & ShufMask [ <NUM_LIT> ] ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( VT ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( TT ) , CPU , Options . MCOptions ) ) , DL ( computeDataLayout ( isLittle , ABI ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) +

<STR_LIT> , isLittle , * this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) {


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : BytesInStackArgArea ( <NUM_LIT> ) , ArgumentStackToRestore ( <NUM_LIT> ) , HasStackFrame ( false ) , NumLocalDynamicTLSAccesses ( <NUM_LIT> ) , VarArgsStackIndex ( <NUM_LIT> ) , VarArgsGPRIndex ( <NUM_LIT> ) , VarArgsGPRSize ( <NUM_LIT> ) , VarArgsFPRIndex ( <NUM_LIT> ) , VarArgsFPRSize ( <NUM_LIT> ) { ( void


<s> unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int32_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; loadImmediate ( ImmValue , ATReg , <STR_LIT> , true , false , IDLoc ,


<s> OptForSize = MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>TargetLowering :: isAllActivePredicate ( SelectionDAG & DAG , SDValue N


<s> void <ISA_LIT>SEInstrInfo :: expandEhReturn ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ADDU = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned RA = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned T9 = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) , RA ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) , SP ) . addReg ( SP )


<s> } case 'v' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; LLVM_FALLTHROUGH ; case 'x' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) ) weight = CW_Register ; break ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M'


<s> assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MF -> push_back ( restoreMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = getTargetMachine ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo *


) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> , __R ) ;


<s> SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ResTy ) ; SDValue Bit = DAG . getNode ( <STR_LIT> , DL , ResTy , One , truncateVecElts ( Op , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , Op -> getOperand ( <NUM_LIT>

) , DAG . getNOT ( DL , Bit , ResTy ) ) ;


<s> MachineBasicBlock * MBB = & * MBBI ; unsigned MBBId = MBB -> getNumber ( ) ; assert ( ! MBBId || BBInfo [ MBBId - <NUM_LIT> ] . postOffset ( ) <= BBInfo [ MBBId ] . Offset ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << CPUsers . size ( ) << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) { CPUser & U =


<s> return Subtarget . in<ISA_LIT>16Mode ( )


<s> if ( PreOp ) return LPAC :: makePreOp ( AluCode ) ; if ( PostOp ) return LPAC :: makePostOp ( AluCode ) ; return AluCode


<s> static SDValue foldMaskedMergeImpl ( SDValue And0_L , SDValue And0_R , SDValue And1_L , SDValue And1_R , SDLoc DL , SelectionDAG & DAG ) { if ( ! isBitwiseNot ( And0_L , true ) || ! And0_L -> hasOneUse ( ) ) return SDValue ( ) ; SDValue NotOp = And0_L -> getOperand ( <NUM_LIT> ) ; if ( NotOp == And1_R ) std :: swap ( And1_R , And1_L ) ; if ( NotOp != And1_L ) return SDValue ( ) ; EVT VT = And1_L -> getValueType ( <NUM_LIT> ) ; SDValue Freeze_And0_R = DAG . getNode ( <STR_LIT> , SDLoc ( ) , VT , And0_R ) ; SDValue Xor0 = DAG . getNode ( <STR_LIT> , DL , VT , And1_R , Freeze_And0_R ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL ,


<s> rtx cache = GEN_INT ( val ) ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = cache ; return gen_rtx_CONST_VECTOR ( mode


<s> int fma_node :: get_parity ( ) { return this -> m_head -> regno


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> || ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else return Error ( Loc , <STR_LIT> ) ; Parser . Lex ( ) ; Amount =


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string <ISA_LIT>Name = CPU ; if ( <ISA_LIT>Name . empty ( ) ) <ISA_LIT>Name = <STR_LIT> ; std :: string FullFS = FS ; ParseSubtargetFeatures ( <ISA_LIT>Name , FullFS


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( )


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { unsigned Size = <NUM_LIT> << getFixupKindLog2Size ( Fixup . getKind ( ) ) ; assert ( Fixup . getOffset ( ) + Size <= Data . size ( ) && <STR_LIT> ) ; assert ( isIntN ( Size * <NUM_LIT> + <NUM_LIT> , Value ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ] = uint8_t


<s> return LowerUINT_TO_FP_i32 ( Op , DAG ) ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , NULL , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , NULL , <NUM_LIT> ) ; return BuildFILD ( Op , <STR_LIT> ,


<s> void EmitSIBByte ( unsigned SS , unsigned Index , unsigned Base , unsigned &


<s> return DecodeCAS ( MI , insn , Address , Decoder , false , false


<s> if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) && ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID ) ; } } if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( createThumb2ITBlockPass (


<s> int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; int NumEltsPerLane = NumElts / NumLanes ; SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; PermMask [ i ] = ( DstLane * NumEltsPerLane ) + ( M % NumEltsPerLane ) ; } SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; for ( int DstLane = <NUM_LIT> ; DstLane != NumLanes ; ++ DstLane ) { int SrcLane = SrcLaneMask [ DstLane ] ; if ( <NUM_LIT> <= SrcLane ) for ( int j = <NUM_LIT> ; j != NumEltsPerLane ; ++ j ) { LaneMask [ ( DstLane * NumEltsPerLane ) + j ] = ( SrcLane * NumEltsPerLane ) + j ; } } int NumIdentityLanes = <NUM_LIT> ; bool OnlyShuffleLowestLane = true ; for ( int i = <NUM_LIT> ; i != NumLanes ; ++ i ) { if ( isSequentialOrUndefInRange ( PermMask , i * NumEltsPerLane , NumEltsPerLane , i * NumEltsPerLane ) ) NumIdentityLanes ++ ; else if ( SrcLaneMask [ i ] != <NUM_LIT> && SrcLaneMask [ i ] != NumLanes ) OnlyShuffleLowestLane = false ; } if ( OnlyShuffleLowestLane && NumIdentityLanes == ( NumLanes - <NUM_LIT> ) ) return SDValue ( ) ; SDValue LanePermute = DAG . getVectorShuffle ( VT , DL , V1 , V2 , LaneMask ) ; return DAG . getVectorShuffle ( VT , DL , LanePermute , DAG . getUNDEF ( VT )


<s> IPMConversion Conversion = getIPMConversion ( CCValid , CCMask ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; if ( Conversion . XORValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . XORValue , DL , <STR_LIT> ) ) ; if ( Conversion . AddValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . AddValue , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . Bit , DL , <STR_LIT> ) ) ; if ( Conversion . Bit != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return Result


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ForLoadFold ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( RestoreMBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( RestoreMBB ) ; auto RestoreMBBI = RestoreMBB -> begin ( ) ; BuildMI ( * RestoreMBB , RestoreMBBI , DL , TII . get (


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , const SMLoc & Loc ) override { if ( const MCSymbolRefExpr * SRE = dyn_cast_or_null < MCSymbolRefExpr > ( Value ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL && ! ( Size == <NUM_LIT> ) ) getContext ( ) . FatalError ( Loc , <STR_LIT> ) ; EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value , Size


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT>


<s> if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair : if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) . contains ( Op . getReg ( ) ) ) return Match_Success ; break ; } return Match_InvalidOperand


<s> bool UsedMask [ ] = { false , false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else


<s> } const APInt & V = Bits [ i ] ; assert ( V . getBitWidth ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; if ( Split ) { Ops . push_back ( DAG . getConstant ( V . trunc ( <NUM_LIT> ) , dl , EltVT ) ) ; Ops . push_back ( DAG . getConstant ( V . lshr ( <NUM_LIT> ) . trunc ( <NUM_LIT> ) , dl , EltVT ) ) ; } else if ( EltVT == <STR_LIT> ) { APFloat FV ( APFloat :: IEEEsingle ( ) , V ) ; Ops . push_back ( DAG . getConstantFP ( FV , dl , EltVT ) ) ; } else if ( EltVT == <STR_LIT> ) { APFloat FV ( APFloat :: IEEEdouble ( ) , V ) ; Ops . push_back ( DAG . getConstantFP ( FV , dl , EltVT ) ) ; } else { Ops . push_back ( DAG . getConstant ( V , dl , EltVT ) ) ; } } SDValue ConstsNode = DAG . getBuildVector ( ConstVecVT , dl ,


__artificial__ ) ) _mm256_setzero_ph ( void ) {


<s> static bool will_be_in_index_register ( const_rtx x ) { return GET_CODE ( x ) == UNSPEC && ( XINT ( x ,


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , Ty , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX )


<s> getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint ,


<s> return ( poly64x2_t ) __builtin_neon_vdup_nv2di ( (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) return * CM


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT>


<s> case InlineAsm :: Constraint_Zy : const TargetRegisterInfo * TRI = <ISA_LIT>SubTarget -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp ) ; return false


<s> LastFPdOpCycleIdx = UINT_MAX ; DEBUG ( CurGroupDbg = <STR_LIT> ;


<s> SDValue Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) ) ; return Chain


<s> bool allocateSeparateGVMemory ( ) const override { return true ; return false


<s> splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , <NUM_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo (


<s> static MachineOperand * getCallTargetRegOpnd ( MachineInstr & MI ) { if ( MI . getNumOperands ( )


<s> default : break ; case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBITCASTCombine ( N , DAG ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> x = gen_rtx_REG ( value_mode , FP_RETURN ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode


<s> } unsigned int word = vsx_const -> words [ <NUM_LIT> ] ; int sign_word = ( ( word & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( EASY_VECTOR_15 ( sign_word ) ) return <NUM_LIT> ; return vsx_const -> words [


<s> protected : const <ISA_LIT>Subtarget * Subtarget ; protected : LEONMachineFunctionPass ( TargetMachine & tm , char &


SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ;


<s> rs6000_debug_target_options ( args , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; if ( flags ) fprintf ( stderr , <STR_LIT> , flags ) ; fprintf ( stderr , <STR_LIT> ) ; } old_optimize = build_optimization_node ( & global_options ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options ) ; rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; ret = rs6000_inner_target_options ( args , true ) ; if ( ret ) { ret = rs6000_option_override_internal ( false ) ; new_target = build_target_option_node ( & global_options ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options ) ; if ( ! new_target )


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: sparc , true > X (


<s> void arm_lang_object_attributes_init ( void )


<s> if ( ImmWithLSL . ShiftAmount >= RegWidth ) return false ; <ISA_LIT>MCExpr :: VariantKind Modifier ; if ( isNonConstantExpr ( ImmWithLSL . Val , Modifier ) ) { if ( ! ImmWithLSL . ImplicitAmount ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumModifiers ; ++ i ) if ( PermittedModifiers [ i ] == Modifier ) return true ; return false ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmWithLSL . Val ) ; return CE && CE -> getValue ( ) >= <NUM_LIT> && CE ->


<s> MCSymbol * <ISA_LIT>AsmPrinter :: GetGlobalValueSymbol ( const GlobalValue * GV ) const { SmallString < <NUM_LIT> > NameStr ; Mang -> getNameWithPrefix ( NameStr , GV , false ) ; MCSymbol * Symb = OutContext . GetOrCreateSymbol ( NameStr . str ( ) ) ; if ( Subtarget -> isTargetCygMing


<s> SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false ,


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> )


<s> default : break ; case <STR_LIT> : case <STR_LIT> : DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; assert ( ( KnownZero & KnownOne ) ==


<s> bool aarch64_address_valid_for_prefetch_p ( rtx x , bool strict_p ) { struct aarch64_address_info addr ; bool res = aarch64_classify_address ( & addr , x


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction (


<s> bool hardenSlsBlr ( ) const { return HardenSlsBlr


<s> Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else


<s> SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const char * <ISA_LIT>16HelperFunction = nullptr ; bool Need<ISA_LIT>16Helper = false ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy (


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest ,

source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ;


<s> LivePhysRegs LiveRegs ( TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineBasicBlock * RestMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( MCPhysReg R : LiveRegs ) RestMBB -> addLiveIn ( R ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( MCPhysReg R : LiveRegs )


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_avg_pu16 ( __m64 __A , __m64 __B ) { __vector unsigned short a , b , c ; a = ( __vector unsigned short ) vec_splats ( __A ) ; b = ( __vector unsigned short ) vec_splats ( __B ) ; c = vec_avg ( a , b ) ; return ( __m64 ) ( ( __vector long long )


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto & Args = F . getArgumentList ( ) ; unsigned ArgIdx = <NUM_LIT> ; for ( auto & Arg


<s> MCCodeEmitter * llvm :: create<ISA_LIT>LEMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI ,


<s> Type * OpTy = nullptr ; if ( CmpInst * CI = dyn_cast < CmpInst > ( I -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; else if ( Instruction * LogicI = dyn_cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( LogicI -> getNumOperands ( ) == <NUM_LIT> ) if ( CmpInst * CI0 = dyn_cast < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) if ( isa < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI0 -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy != nullptr ) { if ( VF == <NUM_LIT> ) { assert ( ! OpTy -> isVectorTy ( ) && <STR_LIT> ) ; return OpTy ; } Type * ElTy = OpTy -> getScalarType ( ) ; return VectorType :: get ( ElTy


<s> RegisterTarget < Triple :: sparc , true > X ( The<ISA_LIT>Target , <STR_LIT> ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { return makeAddress ( Op


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { int64_t Value = MI -> getOperand ( OpNum ) .


<s> Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = <STR_LIT> ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = <STR_LIT> ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = <STR_LIT> ; } } if ( ! Opc ) return false ; Register Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; Register Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; if ( NeedExtraOp ) Src1Reg = emitLogicalOp_ri ( <STR_LIT> ,


<s> void setShouldRestoreSPFromFP ( bool s


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; SDValue PSHUFBMask [ <NUM_LIT>


<s> virtual const TargetFrameInfo * getFrameInfo (


<s> if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; } } printOperand ( MI , OpNo ) ; return


<s> FunctionPass * llvm :: create<ISA_LIT>IndirectThunksPass (


<s> if ( getLoadStoreBaseOp ( MI ) . getReg ( ) == <STR_LIT> && STI . getFrameLowering ( ) -> getTransientStackAlign

( ) >= Align ( <NUM_LIT> ) ) return true ;


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > (


<s> return getTM < <ISA_LIT>TargetMachine >


<s> bool reseveCallFrame = TFI -> hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT>


<s> assert ( * Args [ i ] >= <NUM_LIT> && <STR_LIT> ) ; assert ( * Args [ i ] < ( int ) Args . size ( ) * <NUM_LIT> && <STR_LIT> ) ; if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != * Args [ i ] ) return false ; } return true


<s> if ( isImm ( ) ) { Inst . addOperand ( MCOperand :: CreateExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> return Kind == k_VectorList && ! VectorList .


<s> case <STR_LIT> : return MCDisassembler :: Fail ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! U ) { if ( imm == <NUM_LIT> ) imm = INT32_MIN ; else imm = - imm


<s> void <ISA_LIT>AsmPrinter :: EmitJumpTable ( const MachineInstr * MI ) { unsigned Opcode = MI -> getOpcode ( ) ; int OpNum = <NUM_LIT> ; if ( Opcode == <STR_LIT> ) OpNum = <NUM_LIT> ; else if ( Opcode == <STR_LIT> ) OpNum = <NUM_LIT> ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( MBB


<s> return ( __m128d ) __builtin_ia32_movsd ( ( __v2df ) __A , ( __v2df )


<s> void addSystemPStateFieldOperands ( MCInst & Inst


<s> if ( Opcode == TargetOpcode :: LOAD_STACK_GUARD ) return false ; if ( I . isCopy ( ) ) return selectCopy ( I , MRI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I , CoverageInfo ) ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; switch ( I . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_STORE : case TargetOpcode :: G_LOAD : return selectLoadStoreOp ( I , MRI , MF ) ; case TargetOpcode :: G_GEP : case TargetOpcode :: G_FRAME_INDEX : return selectFrameIndexOrGep ( I , MRI , MF ) ; case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return selectShift ( I , MRI , MF ) ; case TargetOpcode :: G_SDIV


<s> unsigned StackAlign = TFI -> getStackAlignment ( ) ; assert ( StackAlign >= <NUM_LIT> && isPowerOf2_32 ( StackAlign ) && <STR_LIT> ) ; unsigned StackProbeSize = <NUM_LIT> ; const Function & Fn = MF . getFunction ( ) ; if ( Fn . hasFnAttribute ( <STR_LIT> ) ) Fn . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT>


<s> virtual const char * getPassName ( )


<s> if ( ( <NUM_LIT> + ( MMIX_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) ) ) / <NUM_LIT> != <NUM_LIT> )


<s> if ( ( flags & OPTION_MASK_MFPGPR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P9_VECTOR ) !=


<s> } if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } if ( TII -> isLdStPairSuppressed ( MI ) ) { ++ MBBI ; break ; } bool MergeForward = false ; int SExtIdx = - <NUM_LIT> ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , MergeForward , SExtIdx , ScanLimit ) ; if ( Paired != E ) { MBBI = mergePairedInsns ( MBBI , Paired , MergeForward , SExtIdx ) ; Modified = true ; ++ NumPairCreated ; if ( isUnscaledLdst ( MI -> getOpcode ( ) ) ) ++ NumUnscaledPairCreated ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } MachineBasicBlock :: iterator Update = findMatchingUpdateInsnForward ( MBBI , ScanLimit , <NUM_LIT> ) ; if ( Update != E ) { MBBI = mergePostIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPostFolded ; break ; } if ( isUnscaledLdst ( Opc ) ) { ++ MBBI ; break ; } Update = findMatchingUpdateInsnBackward ( MBBI , ScanLimit ) ; if ( Update != E ) { MBBI = mergePreIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPreFolded ; break ; } int Value = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * TII -> getRegClass ( MI -> getDesc ( ) , <NUM_LIT> ,

TRI , * ( MBB . getParent ( ) ) ) -> getSize ( ) ;


<s> if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> return __builtin_mve_vaddq_n_sv16qi ( __a ,


<s> bool sh_legitimize_reload_address ( rtx * p , machine_mode mode , int opnum , int itype ) { enum reload_type type = ( enum reload_type ) itype ; const int mode_sz = GET_MODE_SIZE ( mode ) ; if ( sh_lra_p ( ) ) return false ; if ( GET_CODE ( * p ) == PLUS && CONST_INT_P ( XEXP ( * p , <NUM_LIT> ) ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( * p , <NUM_LIT> ) , true ) ) { const HOST_WIDE_INT offset = INTVAL ( XEXP ( * p , <NUM_LIT> ) ) ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , offset ) ; if ( TARGET_SH2A && mode == DFmode && ( offset & <NUM_LIT> ) ) { push_reload ( * p , NULL_RTX , p , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return true ; } if ( TARGET_SH2E && mode == SFmode ) { * p = copy_rtx ( * p ) ; push_reload ( * p , NULL_RTX , p , NULL , BASE_REG_CLASS ,


<s> else if ( TARGET_VSX && dest_vsx_p ) { if ( mode_supports_dq_form ( mode ) && quad_address_p ( XEXP ( src , <NUM_LIT> ) , mode , true ) ) return <STR_LIT> ; else if ( TARGET_P9_VECTOR ) return <STR_LIT> ; else if ( mode == V16QImode || mode == V8HImode || mode == V4SImode ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && dest_vmx_p ) return <STR_LIT> ; else if ( dest_fp_p ) return <STR_LIT> ; } else if ( src_regno >= <NUM_LIT> && MEM_P ( dest ) ) { if ( src_gpr_p ) { if ( TARGET_QUAD_MEMORY && quad_load_store_p ( dest , src ) ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && src_vmx_p && altivec_indexed_or_indirect_operand ( dest , mode ) ) return <STR_LIT> ; else if ( TARGET_VSX && src_vsx_p ) { if ( mode_supports_dq_form ( mode ) && quad_address_p ( XEXP ( dest , <NUM_LIT> ) , mode , true ) ) return <STR_LIT> ; else if ( TARGET_P9_VECTOR ) return <STR_LIT> ; else if ( mode == V16QImode || mode == V8HImode || mode == V4SImode ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && src_vmx_p )


<s> void addDupAlignedMemory16Operands ( MCInst & Inst ,


<s> SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI -> isFixedObjectIndex ( FI ) ) return false ; return Offset == MFI -> getObjectOffset ( FI ) &&


<s> void clearFeatureBits ( unsigned Feature , StringRef FeatureString ) { if ( STI . getFeatureBits ( ) & Feature ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString


<s> if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num , S


<s> case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( StrOpc ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOStore ) ; return


<s> return __builtin_ia32_vcvtph2uqq512_mask_round ( __A , _mm512_setzero_si512 ( ) , (


<s> log_msg ( <STR_LIT> ) ; rtx & comp = trace . branch_condition_rtx_ref ( ) ; rtx_code rev_cmp_code = reversed_comparison_code ( comp , trace . cbranch_insn ) ; if ( rev_cmp_code == UNKNOWN ) log_return (


<s> rtx addr = XEXP ( call_op , <NUM_LIT> ) ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx ) { if ( parts . index ) { addr = gen_rtx_MULT ( Pmode , parts . index , GEN_INT ( parts . scale ) ) ; addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , addr ) ; } else addr = stack_pointer_rtx ; rtx disp ; if ( parts . disp != NULL_RTX ) disp = plus_constant ( Pmode , parts . disp , UNITS_PER_WORD ) ; else disp = GEN_INT ( UNITS_PER_WORD ) ; addr = gen_rtx_PLUS ( Pmode , addr , disp ) ; call_op = gen_rtx_MEM ( GET_MODE ( call_op ) , addr ) ; } } output_asm_insn ( push_buf , & call_op ) ; ix86_output_jmp_thunk_or_indirect ( thunk_name , regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file )


<s> bool isN64 ( ) const { return Subtarget -> isABI_N64


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt


<s> if ( ! HiddenGVStubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( StringMap < std :: string > :: iterator I = HiddenGVStubs . begin ( ) , E = HiddenGVStubs . end ( ) ; I != E ; ++ I ) O << I -> getKeyData ( ) << <STR_LIT> << TAI -> getData32bitsDirective ( ) << I -> second << '\n' ; } O << <STR_LIT> ; } else if ( Subtarget -> isTargetCygMing ( ) ) { for ( StringSet < > :: iterator i = CygMingStubs . begin ( ) , e = CygMingStubs . end ( ) ; i != e ; ++ i ) { O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> << COFF :: C_EXT << <STR_LIT> << ( COFF :: DT_FCN << COFF :: N_BTSHFT ) << <STR_LIT> ; } } if ( ! DLLExportedGVs . empty ( ) || ! DLLExportedFns . empty ( ) ) { TargetLoweringObjectFileCOFF & TLOFMacho = static_cast < TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getCOFFSection ( <STR_LIT> , true , SectionKind :: getMetadata ( ) ) ) ; for ( StringSet < > :: iterator i = DLLExportedGVs . begin ( ) , e = DLLExportedGVs . end ( ) ; i != e ; ++ i ) O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> ; for ( StringSet < > :: iterator i = DLLExportedFns . begin ( ) , e = DLLExportedFns . end ( ) ; i != e ; ++ i ) O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> ; } return AsmPrinter :: doFinalization


<s> return __builtin_ia32_vcvttph2uqq256_mask ( __A , _mm256_setzero_si256 ( ) ,


<s> enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; if ( code == LT || code == LE ) return pru_output_ltle_signed_cbranch ( operands , is_near ) ; else if ( code == GT || code == GE ) return pru_output_gtge_signed_cbranch (


<s> vtrnq_u8 ( uint8x16_t a , uint8x16_t b ) { return ( uint8x16x2_t ) { vtrn1q_u8 ( a , b ) , vtrn2q_u8 ( a ,


<s> if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = <STR_LIT> ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = <STR_LIT> ; Cost = <NUM_LIT> ; break ; case


<s> bool nds32_n10_last_load_to_ex_p ( rtx_insn * producer


<s> static bool isNarrowLoad ( MachineInstr & MI ) { return isNarrowLoad ( MI . getOpcode ( )


<s> if ( need_atomic_barrier_p ( model , true ) )


<s> if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT>


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ! Subtarget . is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; Register Reg = VA . getLocReg ( ) ; switch ( Reg ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ++ NumInRegs == MaxInRegs ) return false ; break ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; } bool CalleeWillPop = <STR_LIT> ( CalleeCC , Subtarget . is64Bit ( ) , isVarArg , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; if ( unsigned BytesToPop = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( )


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { Triple TheTriple ( TT ) ; unsigned RA = ( TheTriple . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X = new MCRegisterInfo


<s> SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> ,


<s> void <ISA_LIT>AsmPrinter :: PrintMemReference ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( isMem ( * MI , OpNo ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( OpNo + <STR_LIT> ) ; if ( Segment . getReg ( ) ) { PrintModifiedOperand ( MI , OpNo + <STR_LIT> , O ,


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx


<s> static DecodeStatus DecodeT2AddrModeImm0_1020s4 ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S =


<s> if ( Reg == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , true , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError (


<s> case MachineOperand :: MO_Immediate : { if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) != <NUM_LIT> ) O << <STR_LIT> ; O << MO . getImm ( ) ; break ; } case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; GlobalValue * GV = MO . getGlobal ( ) ; std :: string Name = Mang -> getValueName ( GV ) ; bool isExt = ( GV -> isDeclaration ( ) || GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) ) ; if ( isExt && isCallOp && Subtarget -> isTargetDarwin ( ) && TM . getRelocationModel ( ) != Reloc :: Static ) { printSuffixedName ( Name , <STR_LIT> ) ; FnStubs . insert ( Name ) ; } else O << Name ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; if ( GV -> hasExternalWeakLinkage ( ) ) ExtWeakSymbols . insert ( GV ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; if ( isCallOp && Subtarget -> isTargetDarwin ( ) && TM . getRelocationModel (


<s> MCFragment * findAssociatedFragment ( ) const


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; <STR_LIT> TargetFlags = <STR_LIT> ; if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags = <STR_LIT> ; else if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) TargetFlags = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; SDLoc DL ( Op ) ; ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine


<s> LastCMOV = & * NextMIIt ; NextMIIt = next_nodbg ( NextMIIt , ThisMBB -> end ( ) ) ; } } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } auto DbgEnd = MachineBasicBlock :: iterator ( LastCMOV ) ; auto DbgIt = MachineBasicBlock :: iterator ( MI ) ; while ( DbgIt != DbgEnd ) { auto Next = std :: next ( DbgIt ) ; if ( DbgIt -> isDebugInstr ( ) ) SinkMBB -> push_back ( DbgIt -> removeFromParent ( ) ) ; DbgIt = Next ; } SinkMBB -> splice ( SinkMBB -> end ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FalseMBB -> addSuccessor ( SinkMBB ) ; BuildMI ( ThisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( CC ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; createPHIsForCMOVsInSinkBB ( MIItBegin , MIItEnd , ThisMBB , FalseMBB , SinkMBB ) ; ThisMBB -> erase ( MIItBegin , MIItEnd ) ; return SinkMBB


<s> if ( SDValue NewOp = combineExtractWithShuffle ( N , DAG , DCI , Subtarget ) ) return NewOp ; SDValue InputVector = N -> getOperand ( <NUM_LIT> ) ; SDValue EltIdx = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = InputVector . getValueType ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( InputVector ) ; if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( VT == <STR_LIT> && InputVector . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( EltIdx ) && isa < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ) { uint64_t ExtractedElt = N -> getConstantOperandVal ( <NUM_LIT> ) ; uint64_t InputValue = InputVector . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t Res = ( InputValue >> ExtractedElt ) & <NUM_LIT> ; return DAG . getConstant ( Res , dl , <STR_LIT> ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combineHorizontalPredicateResult ( N , DAG , Subtarget ) ) return Cmp ; if ( SrcVT != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT>


<s> O << <STR_LIT> << formatImm ( Op . getImm ( ) * <NUM_LIT> ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t


<s> Value * <ISA_LIT>IREmitter :: visitVMOVRRD ( const SDNode * N


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_cvtusepi32_storeu_epi8 ( void *


<s> static unsigned getShuffleSHUFImmediate ( ShuffleVectorSDNode * N ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; assert ( ( VT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; assert ( ( NumLaneElts == <NUM_LIT> || NumLaneElts == <NUM_LIT> || NumLaneElts == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Shift = ( NumLaneElts >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT>


<s> break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } break ; case <NUM_LIT> : if ( Constraint [ <NUM_LIT> ] == 'T' ) { switch ( Constraint [ <NUM_LIT>


<s> bool hasP8Altivec ( ) const { return HasP8Altivec


<s> if ( Subtarget . hasXOP ( ) && Ty -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ||

Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ;


<s> for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { for ( MachineBasicBlock :: iterator MI = MFI -> begin ( ) , ME = MFI -> end ( ) ; MI != ME ; ) { Modified |= runOnInstruction ( & * MI ++ ) ; } } for ( std :: set < MachineInstr * > :: iterator I = DeadInstr . begin ( ) , E = DeadInstr . end ( ) ; I != E ; ++ I ) { ( * I ) -> eraseFromParent


<s> SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> optForMinSize ( ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ; for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I -> getBlock ( ) ) ) Changed = true ; return Changed


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue OutVal = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : OutVal = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , OutVal ) ; break ; case CCValAssign :: ZExt


<s> void addAlignedMemory32Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst ,


<s> getT2SORegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits


<s> bool isOriginalInst ( MachineInstr * inst ) { for ( unsigned int opcount = <NUM_LIT> ; opcount < inst -> getNumOperands ( ) ; opcount ++ ) if ( inst -> getOperand ( opcount ) . isReg ( ) ) if ( ! isGPR ( inst -> getOperand ( opcount ) .


<s> bool <ISA_LIT>TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == <NUM_LIT> ) return false ; if ( Subtarget . hasXOP ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> || Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; if ( Subtarget . hasBWI ( ) && Bits == <NUM_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , true ) && shouldCombineToHorizontalOp (


<s> int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1