<s> if ( Base != NewBase && Offset >= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; Base = NewBase ; BaseKill = false ; } AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } Base = NewBase ; BaseKill = true ; } bool isDef = ( isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode , Mode ) ; if ( ! Opcode ) return false ; bool Writeback = isThumb1 ; if ( Opcode == <STR_LIT> && isThumb1 ) for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) if ( Base == Regs [ I ] . first ) { Writeback = false ; break ; } if ( isThumb1 && Writeback && ! BaseKill ) return false ; MachineInstrBuilder MIB ; if ( Writeback ) { if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) ; } else { MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getKillRegState ( BaseKill ) ) ; } MIB . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned i = <NUM_LIT> ; i != NumRegs ; ++ i ) MIB = MIB . addReg ( Regs [ i ] . first , getDefRegState ( isDef ) | getKillRegState ( Regs [ i ] . second ) ) ; for ( unsigned i = <NUM_LIT> , e = ImpDefs . size ( ) ; i != e ; ++ i ) MIB . addReg ( ImpDefs [ i ] , RegState :: ImplicitDefine ) ; return true


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . is256BitVector ( ) && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! MI . findRegisterDefOperand ( <STR_LIT> ) -> isDead ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value :


<s> MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr ,

MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ;


<s> explicit <ISA_LIT>PagerandoOptimizer ( ) :


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget -> hasV6T2Ops (


<s> bool <ISA_LIT>MCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst )


<s> result . push_back ( v [ i ] ) ; if ( i + <NUM_LIT> < v [ i ] . first && i + <NUM_LIT> < v . size ( ) && v [ i + <NUM_LIT> ] . first != v [ i ] . first + <NUM_LIT> ) result . push_back ( { v [ i

] . first + <NUM_LIT> , LegalizerInfo :: Unsupported } ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPic0 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA .


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; TC -> dump ( ) ; dbgs ( ) << <STR_LIT> ; EC -> dump ( ) ; dbgs ( ) << <STR_LIT> << VectorWidth << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ceil -> dump ( ) ; ) ; bool Zero = SE -> getMinusSCEV ( SE -> getBackedgeTakenCount ( L ) , SE -> getUDivExpr ( SE -> getAddExpr ( SE -> getMulExpr ( Ceil , VW ) , SE -> getNegativeSCEV ( VW ) ) , VW ) ) -> isZero ( ) ; if ( ! Zero ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } auto * IV = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; auto * IVExpr = SE -> getSCEV ( IV ) ; auto * AddExpr = dyn_cast < SCEVAddRecExpr > ( IVExpr ) ; if ( ! AddExpr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; IVExpr -> dump ( ) ) ; return false ; } if ( AddExpr -> getLoop ( ) != L ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * Base = dyn_cast < SCEVConstant > ( AddExpr -> getOperand ( <NUM_LIT> ) ) ; if ( ! Base || ! Base -> isZero ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * Step = dyn_cast < SCEVConstant > ( AddExpr -> getOperand ( <NUM_LIT> ) ) ; if ( ! Step ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddExpr -> getOperand ( <NUM_LIT> ) -> dump ( ) ) ; return false ; } auto StepValue = Step -> getValue ( ) -> getSExtValue ( ) ; if ( VectorWidth == StepValue ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StepValue << <STR_LIT> << VectorWidth << <STR_LIT> ) ; return


<s>
}
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
unsigned
ErrorInfoIgnore
;
unsigned
Match1
,
Match2
,
Match3
,
Match4
;
Match1
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match2
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match3
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match4
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Op
->
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
(
Match1
==
Match_Success
)
+
(
Match2
==
Match_Success
)
+
(
Match3
==
Match_Success
)
+
(
Match4
==
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
Match1
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match2
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match3
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match4
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
!=
NumMatches
;
++
i
)
{
if
(
i
!=
<NUM_LIT>
)
OS
<<
<STR_LIT>
;
if
(
i
+
<NUM_LIT>
==
NumMatches
)
OS
<<
<STR_LIT>
;
OS
<<
<STR_LIT>
<<
Base
<<
MatchChars
[
i
]
<<
<STR_LIT>
;
}
OS
<<
<STR_LIT>
;
Error
(
IDLoc
,
OS
.
str
(
)
)
;
return
true
;
}
if
(
(
Match1
==
Match_MnemonicFail
)
&&
(
Match2
==
Match_MnemonicFail
)
&&
(
Match3
==
Match_MnemonicFail
)
&&
(
Match4
==
Match_MnemonicFail
)
)
{
if
(
!
WasOriginallyInvalidOperand
)
{
Error
(
IDLoc
,
<STR_LIT>
+
Base
+
<STR_LIT>
)
;
return
true
;
}
SMLoc
ErrorLoc
=
IDLoc
;
if
(
OrigErrorInfo
!=
~
<NUM_LIT>
)
{
if
(
OrigErrorInfo
>=
Operands
.
size
(
)
)
return


<s> rtx sh_treg_combine :: touched_insn ( rtx i ) { m_touched_insns . push_back ( i ) ; return i


<s> return ( __m128i ) __builtin_ia32_vpcomlew ( ( __v8hi ) __A ,


<s> static unsigned char csky_class_max_nregs ( reg_class_t rclass ,


<s> MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( createTLOF

( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) {


) _mm_setzero_hi ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool isS16Imm ( ) const { return Kind == Expression || ( Kind == Immediate && isInt


<s> unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT>


<s> MCSymbol * Label = getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MCELFStreamer :: EmitLabel ( Label )


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) -> getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> +


<s> void FPS :: popStackAfter ( MachineBasicBlock :: iterator & I ) { MachineInstr & MI = * I ; const DebugLoc & dl = MI . getDebugLoc ( ) ; ASSERT_SORTED ( PopTable ) ; popReg ( ) ; int Opcode = Lookup ( PopTable , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) I -> RemoveOperand ( <NUM_LIT> ) ; MI . dropDebugNumber ( ) ; } else { if ( doesInstructionSetFPSW ( MI ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: iterator Next = getNextFPInstruction ( I ) ; if ( Next != MBB . end ( ) && Next

-> readsRegister ( <STR_LIT> ) ) I = Next ;


<s> static SDValue lowerVectorShuffle ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; int NumElements = VT . getVectorNumElements ( ) ; SDLoc dl ( Op ) ; bool Is1BitVector = ( VT . getScalarType ( ) == <STR_LIT> ) ; assert ( ( VT . getSizeInBits ( ) != <NUM_LIT> || Is1BitVector ) && <STR_LIT> ) ; bool V1IsUndef = V1 . getOpcode ( ) == <STR_LIT> ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , NewMask ) ; } SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; if ( Zeroable . all ( ) ) return getZeroVector ( VT , Subtarget , DAG , dl ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( Mask


<s> void <ISA_LIT>InstrInfo :: setExecutionDomain ( MachineInstr & MI , unsigned Domain ) const { assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ; uint16_t dom = ( MI . getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; assert ( dom && <STR_LIT> ) ; const uint16_t * table = lookup ( MI . getOpcode ( ) , dom , ReplaceableInstrs ) ; if ( ! table ) { assert ( ( Subtarget . hasAVX2 ( ) || Domain < <NUM_LIT> ) && <STR_LIT> ) ; table = lookup ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX2 ) ; } if ( ! table ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512 ) ; if ( table && Domain == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT>


<s> TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>Target , create<ISA_LIT>ElfRelocation ) ; TargetRegistry :: RegisterMCInstrAnalysis (


<s> int val = ( unsigned int ) MI -> getOperand ( OpNo


<s> while ( MBBI != E ) { for ( ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( MI . isCall ( ) || MI . isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI . isDebugInstr ( ) ) MI2LocMap [ & MI ] = ++ Loc ; if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI . getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; auto FindBases = [ & ] ( Base2InstMap & Base2Ops , BaseVec & Bases ) { MapIt BI = Base2Ops . find ( Base ) ; if ( BI == Base2Ops . end ( ) ) { Base2Ops [ Base ] . push_back ( & MI ) ; Bases . push_back ( Base ) ; return ; } for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } ; if ( isLd ) FindBases ( Base2LdsMap , LdBases ) ; else FindBases ( Base2StsMap , StBases ) ; if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ; Base2StsMap . clear


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>64R2 ( )


<s> bool IsKnown ( ) const { return ThisABI


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> ,


<s> return FI <= OutArgFIRange . first && FI >=


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! STI -> in<ISA_LIT>16Mode ( ) || ! <ISA_LIT>Subtarget :: useConstantIslands ( ) ) { return false ; } TII = ( const <ISA_LIT>16InstrInfo * ) MF -> getTarget ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! PrescannedForConstants ) prescanForConstants ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> static MachineInstr * canFoldIntoMOVCC ( unsigned Reg , const MachineRegisterInfo & MRI , const TargetInstrInfo * TII ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return <NUM_LIT> ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return <NUM_LIT> ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return <NUM_LIT> ; if ( ! MI -> isPredicable ( ) ) return <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return <NUM_LIT> ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg


<s> emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } unsigned Lo = Imm & <NUM_LIT> ; if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else { } return


<s> case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction


<s> const MCPhysReg * <ISA_LIT>BaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ==


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; return


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; unsigned Opc = Op . getOpcode ( ) ; if ( VT . isVector ( ) ) return LowerVectorCTLZ ( Op , dl , Subtarget , DAG ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; if ( Opc ==


<s> const char * name ; if ( ! TREE_PUBLIC ( decl ) || DECL_COMMON ( decl ) || DECL_INITIAL ( decl ) == NULL_TREE || DECL_INITIAL ( decl ) == error_mark_node || ( flag_zero_initialized_in_bss && initializer_zerop ( DECL_INITIAL ( decl ) ) ) ) return ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME


<s> O << <STR_LIT> ; printMemReference ( MI ,


<s> for ( const MachineInstr & MI : MBB ) Size += TII -> GetInstSizeInBytes ( MI ) ; BlockInfo [ MBB . getNumber ( ) ] . Size


<s> FunctionPass * llvm :: create<ISA_LIT>AddressTypePromotionPass ( ) { return new <ISA_LIT>AddressTypePromotion


<s> } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand ::


<s> if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> ,


<s> Value * <ISA_LIT>IREmitter :: visitVMOVDRR (


<s> TRI = ST . getRegisterInfo ( ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( * MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF -> front ( ) ) ; bool Changed = false ; for ( auto ML : * MLI ) { if ( ! ML -> getParentLoop ( )


<s> continue ; } uint64_t PermuteOp = ( M >> <NUM_LIT> ) & <NUM_LIT> ; if ( PermuteOp == <NUM_LIT> ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } if ( PermuteOp != <NUM_LIT> ) { ShuffleMask . clear ( ) ; return ; } uint64_t Index = M & <NUM_LIT> ; ShuffleMask . push_back ( (


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> Register <ISA_LIT>FunctionInfo :: getCapGlobalBaseReg ( MachineFunction & MF ) { if ( CapGlobalBaseReg ) return CapGlobalBaseReg ; const TargetRegisterClass * RC = & <STR_LIT> ; return CapGlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister


<s> DiagnosticPredicate isSVEPattern ( ) const { if ( ! isImm ( ) ) return DiagnosticPredicateTy :: NoMatch ; auto * MCE = dyn_cast < MCConstantExpr > (


<s> set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! modified_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) ) && ! side_effects_p

( PATTERN ( t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) {


<s> return true ; } scalar_float_mode mode ; if ( GET_CODE ( value ) != CONST_DOUBLE || ! is_a < scalar_float_mode > ( GET_MODE ( value ) , & mode ) || GET_MODE_BITSIZE ( mode ) > HOST_BITS_PER_WIDE_INT || GET_MODE_BITSIZE ( mode ) > GET_MODE_BITSIZE ( DFmode ) ) return false ; unsigned HOST_WIDE_INT ival = <NUM_LIT> ; long res [ <NUM_LIT> ] ; real_to_target ( res , CONST_DOUBLE_REAL_VALUE ( value ) , REAL_MODE_FORMAT ( mode ) ) ; if ( mode == DFmode ) { int order = BYTES_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ; ival = zext_hwi ( res [ order ] , <NUM_LIT> ) ; ival |= ( zext_hwi ( res [ <NUM_LIT> - order ] , <NUM_LIT> ) << <NUM_LIT> ) ; } else ival = zext_hwi ( res [ <NUM_LIT> ] , <NUM_LIT> ) ; * intval = ival


<s> __builtin_altivec_stvebx ( ( vector signed char ) a1 , a2


<s> return sh_media_LDHI_L ( p , <NUM_LIT> ) | sh_media_LDLO_L (


<s> case <NUM_LIT> : if ( ! ST -> hasBWI ( ) ) PromEltTyBits = <NUM_LIT> ; break ; case <NUM_LIT> : if ( ! ST -> hasVBMI ( ) ) PromEltTyBits = <NUM_LIT> ; break ; case <NUM_LIT> : if ( ST -> hasBWI ( ) ) { if ( ST -> hasVBMI ( ) ) PromEltTyBits = <NUM_LIT> ; else PromEltTyBits = <NUM_LIT> ; break ; } if ( ST -> hasDQI ( ) ) { PromEltTyBits = <NUM_LIT> ; break ; } return bailout ( ) ; default : return bailout ( ) ; } auto * PromEltTy = IntegerType :: getIntNTy ( EltTy -> getContext ( ) , PromEltTyBits ) ; auto * SrcVecTy = FixedVectorType :: get ( EltTy , VF ) ; auto * PromSrcVecTy = FixedVectorType :: get ( PromEltTy , VF ) ; int NumDstElements = VF * ReplicationFactor ; auto * PromDstVecTy = FixedVectorType :: get ( PromEltTy , NumDstElements ) ; auto * DstVecTy = FixedVectorType :: get ( EltTy , NumDstElements ) ; MVT LegalSrcVecTy = TLI -> getTypeLegalizationCost ( DL , SrcVecTy ) . second ; MVT LegalPromSrcVecTy = TLI -> getTypeLegalizationCost ( DL , PromSrcVecTy ) . second ; MVT LegalPromDstVecTy = TLI -> getTypeLegalizationCost ( DL , PromDstVecTy ) . second ; MVT LegalDstVecTy = TLI -> getTypeLegalizationCost ( DL , DstVecTy ) . second ; if ( ! LegalSrcVecTy . isVector ( ) || ! LegalPromSrcVecTy . isVector ( ) || ! LegalPromDstVecTy . isVector ( ) || ! LegalDstVecTy . isVector ( ) ) return bailout ( ) ; if ( PromEltTyBits != EltTyBits ) { InstructionCost PromotionCost ; PromotionCost += getCastInstrCost ( Instruction :: SExt , PromSrcVecTy , SrcVecTy , TargetTransformInfo :: CastContextHint :: None , CostKind ) ; PromotionCost += getCastInstrCost ( Instruction :: Trunc , DstVecTy , PromDstVecTy , TargetTransformInfo :: CastContextHint :: None , CostKind ) ; return PromotionCost + getReplicationShuffleCost ( PromEltTy , ReplicationFactor , VF , DemandedDstElts , CostKind ) ; } assert ( LegalSrcVecTy . getScalarSizeInBits ( ) == EltTyBits && LegalSrcVecTy . getScalarType ( ) == LegalDstVecTy . getScalarType ( ) && <STR_LIT> <STR_LIT> ) ; unsigned NumEltsPerDstVec = LegalDstVecTy . getVectorNumElements ( ) ; unsigned NumDstVectors = divideCeil ( DstVecTy -> getNumElements ( ) , NumEltsPerDstVec


<s> Op -> Barrier . Data = Str . data ( ) ; Op -> Barrier . Length = Str . size ( ) ; Op -> Barrier . HasnXSModifier = HasnXSModifier ; Op -> StartLoc = S ; Op -> EndLoc = S


<s> void insert ( MachineInstr * MI ) { Insts . push_back ( MI


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * Gep = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! Gep || Gep -> getOpcode ( ) != TargetOpcode :: G_GEP ) return None ; if ( ! MRI . hasOneUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return None ; return {


<s> static void build_sv_uint_offset ( function_builder & b , const char *

signature , const function_group_info & group ) {


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; default : return


<s> CONST_SECTION_FUNCTION \ SDATA_SECTION_FUNCTION \ SBSS_SECTION_FUNCTION void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf ( asm_out_file , <STR_LIT> , SDATA_SECTION_ASM_OP ) ;


<s> bool <ISA_LIT>InstructionSelector :: tryOptSelect ( MachineInstr & I ) const { MachineIRBuilder MIB ( I ) ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( CondDefReg ) ) { for ( const MachineInstr & UI : MRI . use_nodbg_instructions ( CondDefReg ) ) { if ( CondDef == & UI ) continue ; if ( UI . getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { MachineInstr * Cmp ; CmpInst :: Predicate Pred ; std :: tie ( Cmp , Pred ) = emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; if ( ! Cmp ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N


<s> unsigned OffsetReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain .


<s> static type_suffix_index find_type_suffix_for_scalar_type ( const_tree type ) { for ( unsigned int suffix_i = <NUM_LIT> ; suffix_i < NUM_TYPE_SUFFIXES ; ++ suffix_i ) if ( ! type_suffixes [ suffix_i ] . bool_p ) { vector_type_index vector_i = type_suffixes [ suffix_i ] . vector_type ; if ( matches_type_p ( scalar_types [ vector_i ] , type ) ) return type_suffix_index ( suffix_i ) ; } return


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> ) return false ; break ; } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , isZExt , false ) ) return false ; MI -> eraseFromParent (


<s> if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case UDIV : case MOD : case UMOD : factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / <NUM_LIT> ; if ( factor == <NUM_LIT> ) factor = <NUM_LIT> ; * total = factor * factor * COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : case MINUS : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / UNITS_PER_WORD ; if ( factor == <NUM_LIT> ) factor = <NUM_LIT> ; * total = factor * COSTS_N_INSNS ( <NUM_LIT> ) ; return true


<s> return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && ! TargetTriple .


<s> APFloat RealVal ( FPImm . Val ) ; uint32_t ImmVal ; return A64Imms :: isFPImm ( RealVal ,


<s> assert ( Kind == k_ShiftedImm && <STR_LIT> ) ; return ShiftedImm


<s> MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; if ( OpFlags & <STR_LIT> ) { ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; } MIRBuilder . buildInstr ( <STR_LIT> , { DstReg } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> | <STR_LIT> ) ; MI . eraseFromParent ( ) ; return


<s> void <ISA_LIT>InstPrinter :: printNEONModImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , <NUM_LIT> ) ; MIRBuilder . buildLoad ( ValVReg , Addr


<s> Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; return false


<s> if ( VT . getSimpleVT ( ) . getScalarType ( ) == <STR_LIT> ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == <NUM_LIT>


<s> bc = ( vec_uchar16 ) ( b ) ; dc = vec_sel ( vec_sub ( bc , ac ) , vec_sub ( ac , bc ) , vec_cmpgt ( ac , bc ) ) ; return ( ( qword ) ( dc


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned descriptorTOCAnchorOffset ( ) const { assert ( usesFunctionDescriptors ( ) &&


<s> break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = ( ArgVT . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; Align Alignment = DL . getABITypeAlign ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; if ( ! emitStore ( ArgVT , ArgReg , Addr , MMO )


<s> assert ( LHSReg && RHSReg && <STR_LIT> ) ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return <NUM_LIT> ; if ( ShiftImm >= RetVT . getSizeInBits ( ) ) return <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII .


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const { return RI


<s> } else log_return ( other_set_found , <STR_LIT> ) ; gcc_assert ( new_entry . cstore_type != cstore_unknown ) ; log_msg ( <STR_LIT> ) ; new_entry . setcc = find_set_of_reg_bb ( m_ccreg , prev_nonnote_nondebug_insn_bb ( new_entry . cstore . insn ) ) ; if ( new_entry . setcc . set_src ( ) == NULL_RTX ) log_return ( set_found , <STR_LIT> ) ; else if ( GET_CODE ( new_entry . setcc . set_rtx ) == SET ) { log_insn ( new_entry . setcc . insn ) ; log_msg ( <STR_LIT> ) ; return set_found ; } else log_return ( set_found , <STR_LIT> ) ; } log_return ( set_not_found ,


<s> assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <STR_LIT> , cast < MemSDNode >


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO .


<s> union { vec_uint4 v ; unsigned long long ll [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . ll [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) ( shmask . v


<s> if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD - <NUM_LIT> ) /


<s> Register Fd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * GPRRC = IsFGR64on<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; unsigned MTC1Opc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : ( IsFGR64on<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ; Register COPYOpc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; Register Wtemp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register WPHI = Wtemp ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp ) . addReg ( Ws ) ; if ( IsFGR64 ) { WPHI = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WPHI ) . addReg ( Wtemp ) ; } Register Rtemp = RegInfo . createVirtualRegister ( GPRRC ) ; Register FPRPHI = IsFGR64on<ISA_LIT>32 ? RegInfo . createVirtualRegister ( & <STR_LIT> ) : Fd ; BuildMI ( * BB , MI , DL , TII -> get ( COPYOpc ) , Rtemp ) . addReg ( WPHI ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( MTC1Opc ) , FPRPHI ) . addReg


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( SrcReg ,


<s> CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i +


<s> unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; auto Costs = std :: make_unique < OutlinerCosts > ( Subtarget ) ; unsigned FrameID = <NUM_LIT> ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs -> FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs -> CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs ->


<s> if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( Opcode , DL , { LoadVT , <STR_LIT> } , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( VT . isFloatingPoint ( ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case

TYPE_VK2 : \ case TYPE_VK4 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ case TYPE_VK32 : \ case TYPE_VK64 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> static rtx prev_args [ <NUM_LIT> ] [ <NUM_LIT> ] ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; reg ++ ) if ( prev_args [ reg ] [ <NUM_LIT> ] == x && prev_args [ reg ] [ <NUM_LIT> ] == y ) break ; if ( reg == <NUM_LIT> ) { reg = next_fcc_reg ; prev_args [ reg ] [ <NUM_LIT> ] = x ; prev_args [ reg ] [ <NUM_LIT> ] = y ; next_fcc_reg = ( next_fcc_reg + <NUM_LIT> ) & <NUM_LIT> ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode ,


<s> } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) return false ; CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources . insert ( V ) ; if ( ! isSink ( V ) && ! isSource ( V ) ) { if ( auto * I = dyn_cast < Instruction > ( V ) ) { for ( auto & U : I


<s> static __inline void si_stqd ( qword a ,


<s> SmallVector < unsigned , <NUM_LIT> > Match ; FeatureBitset ErrorInfoMissingFeatures ; FeatureBitset MissingFeatures ; if ( Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> ) { auto * <ISA_LIT>Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] . get ( ) ) ; if ( <ISA_LIT>Op -> isImm ( ) ) { const auto * CE = dyn_cast < MCConstantExpr > ( <ISA_LIT>Op -> getImm ( ) ) ; unsigned Size = getPointerWidth ( ) ; if ( CE && ( isIntN ( Size , CE -> getValue ( ) ) || isUIntN ( Size , CE -> getValue ( ) ) ) ) { SmallString < <NUM_LIT> > Tmp ; Tmp += Base ; Tmp += ( is64BitMode ( ) ) ? <STR_LIT> : ( is32BitMode ( ) ) ? <STR_LIT> : ( is16BitMode ( ) ) ? <STR_LIT> : <STR_LIT> ; Op . setTokenValue ( Tmp ) ; Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , false ) ) ; Op . setTokenValue ( Base ) ; } } } if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfoIgnore , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } UnsizedMemOp -> Mem . Size


<s> if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P (


<s> SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ,


<s> if ( LocVT . SimpleTy == <STR_LIT> ) RegList = XRegList ; else if ( LocVT . SimpleTy == <STR_LIT> ) RegList = HRegList ; else if ( LocVT . SimpleTy == <STR_LIT> || LocVT . is32BitVector ( ) ) RegList = SRegList ; else if ( LocVT . SimpleTy == <STR_LIT> || LocVT . is64BitVector ( ) ) RegList = DRegList ; else if ( LocVT . SimpleTy == <STR_LIT> || LocVT . is128BitVector ( ) ) RegList = QRegList ; else { return false ; } SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ; State . addLoc ( It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( State . getMachineFunction ( )


<s> addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass


<s> EVT ValTy = Addr . getValueType ( ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( )


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeRROperand ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) { O << <STR_LIT> ; printRegName ( O , RegNum


<s> Error ( L , <STR_LIT> ) ; return false ; } else { Error ( L , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) ,


<s> HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasAddiLoadFusion = false ; HasAddisLoadFusion = false ; IsISA3_0 = false ; IsISA3_1 = false ; UseLongCalls = false ; SecurePlt = false ; VectorsUseTwoUnits = false ; Use<ISA_LIT>PreRASchedStrategy = false ; Use<ISA_LIT>PostRASchedStrategy = false ; PairedVectorMemops =


<s> unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . InRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . ResultReg = ResultReg ; CLI . NumResultRegs = <NUM_LIT> ; } return true


<s> return llvm :: make_unique < <ISA_LIT>MachObjectWriter > (


<s> void <ISA_LIT>AsmPrinter :: EmitAndCountInstruction ( MCInst & Inst ) { OutStreamer -> emitInstruction ( Inst , getSubtargetInfo ( ) ) ; SMShadowTracker . count ( Inst , getSubtargetInfo ( )


<s> __arm_vstrwq_scatter_base_wb_u32 ( uint32x4_t * __addr , const int


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_BR24 ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_THUMB_RELOC_BR22 ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_HALF ) ; Log2Size = <NUM_LIT> ; return true ; case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_HALF ) ; Log2Size = <NUM_LIT> ; return true ; case <STR_LIT> : RelocType = unsigned ( MachO :: <ISA_LIT>_RELOC_HALF ) ; Log2Size = <NUM_LIT> ; return true ; case


<s> int SlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , FPDiff - SlotSize , false , false ) ; EVT VT = Is64Bit ? <STR_LIT>


<s> virtual const char * getPassName ( ) const { return


<s> Type * BCSrcTy = BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( BCTy -> getVectorNumElements ( ) == BCSrcTy


<s> if ( MI -> getOperand ( <STR_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <STR_LIT> ) . getReg ( ) ; } return


<s> if ( ! SawChainSeparater ) ChainNum = ( unsigned ) sqrt ( ( double ) EleNum ) ; CBucket . ChainSize = ( unsigned ) ( EleNum / ChainNum ) ; if ( CBucket . ChainSize * ChainNum != EleNum ) return false ; if ( SawChainSeparater ) { for ( unsigned i = <NUM_LIT> ; i < CBucket . ChainSize ; i ++ ) for ( unsigned j = <NUM_LIT> ; j < ChainNum ; j ++ ) if ( CBucket . Elements [ i ] . Offset != SE -> getMinusSCEV ( CBucket . Elements [ i + j * CBucket . ChainSize ] . Offset , CBucket . Elements [ j * CBucket . ChainSize ] . Offset ) ) return false ; } for ( unsigned i = <NUM_LIT> ; i < ChainNum ; i ++ ) CBucket . ChainBases . push_back ( CBucket . Elements [ i * CBucket . ChainSize ] ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> default : debug ( <STR_LIT> ) ; return true ; case ENCODING_REG : translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; CASE_ENCODING_RM : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false


<s> if ( GET_MODE ( def_reg ) == DImode ) return reg_overlap_p ( def_reg , use_reg ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; gcc_assert ( REG_P ( use_reg ) || GET_CODE ( use_reg ) == SUBREG ) ; if ( REG_P ( def_reg ) ) { if REG_P ( use_reg ) { if ( ! TARGET_BIG_ENDIAN ) return REGNO ( def_reg ) == REGNO ( use_reg ) + <NUM_LIT> ; else return REGNO ( def_reg ) == REGNO ( use_reg ) ; } else return true


<s> return __builtin_aarch64_sshll_nv8qi ( __a ,


<s> if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ; return


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeImm8Offset ( SDNode * Op , SDValue N , SDValue & OffImm ) { return false


<s> const <ISA_LIT>TargetLowering * getTargetLowering (


<s> OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case


<s> Register DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . hasOneUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasMinSize ( ) ) return true ; if ( ! STI . hasLSLFast (


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cmpgt_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = ( __vector signed short ) vec_cmpgt ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 =


<s> rtx arm_gen_store_multiple ( int * regs , int count , rtx basereg , int write_back , rtx basemem , HOST_WIDE_INT


<s> CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant (


<s> return SupportedVectorShiftWithImm ( VT ,


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitAtomicBinary ( MachineInstr & MI , MachineBasicBlock * BB , unsigned AtomicSize , unsigned BinOpcode , unsigned CmpOpcode , unsigned CmpPred ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto LoadMnemonic = <STR_LIT> ; auto StoreMnemonic = <STR_LIT> ; switch ( AtomicSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; assert ( Subtarget . hasPartwordAtomics ( ) && <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; assert ( Subtarget . hasPartwordAtomics ( ) && <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; Register dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = CmpOpcode ? F -> CreateMachineBasicBlock ( LLVM_BB ) : nullptr ; MachineBasicBlock * exitMBB = F ->


<s> MVT LegalVT = ( TLI . getTypeToTransformTo ( * DAG . getContext ( ) , EltVT ) ) . getSimpleVT ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , LegalVT , In , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Res ) ; } assert ( ( In . getSimpleValueType ( ) . is256BitVector ( ) || In . getSimpleValueType ( ) . is512BitVector ( ) )


<s> if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , arg . type ) ; else if ( res > <NUM_LIT> ) { nregs ++ ; if ( res > <NUM_LIT> && warn_psabi ) inform ( input_location ,


<s> if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > (


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } DEBUG ( dbgs ( ) << Parser . getTok ( ) . getKind ( ) << <STR_LIT> ) ; return


<s> static bool IsTailCallConvention ( CallingConv :: ID CC ) { return ( CC == CallingConv :: Fast || CC == CallingConv


<s> assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl ,


<s> unsigned Reg = matchRegisterByNumber ( Tok . getIntVal ( ) , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op


<s> return ( int32x2_t ) __builtin_neon_vsras_nv2si ( __a ,


<s> break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { Value * Op = * i ; if ( const StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; Disp += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; } else if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) ; if ( IndexReg == <NUM_LIT> ) return false ; } else goto unsupported_gep ; } } if ( ! isInt32 ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) return true ; AM = SavedAM ; break ; unsupported_gep : break ; } } if ( GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( )


<s> CodeModel :: Model CM = DAG . getTarget ( ) . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , CM ) ) { if ( isInt < <NUM_LIT> > ( Offset ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset =


<s> void setDecorationStyle ( NameDecorationStyle style ) { DecorationStyle = style


<s> unsigned Index = Address - R -> Base ; if ( Bytes . size ( ) <=


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O ) ; O << <STR_LIT>


<s> builtin_define ( <STR_LIT> ) ; } builtin_define ( <STR_LIT> ) ; RS6000_CPU_CPP_ENDIAN_BUILTINS ( ) ; if ( TARGET_LONG_DOUBLE_128 ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; if ( TARGET_IEEEQUAD ) builtin_define ( <STR_LIT> ) ; else builtin_define ( <STR_LIT> ) ; } switch ( TARGET_CMODEL ) { case CMODEL_MEDIUM : builtin_define ( <STR_LIT> ) ; break ; case CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } switch ( rs6000_current_abi ) { case ABI_V4 : builtin_define ( <STR_LIT> ) ; break ; case ABI_AIX : builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; break ; case ABI_ELFv2 : builtin_define ( <STR_LIT> ) ; break ; case ABI_DARWIN : builtin_define ( <STR_LIT> ) ; break ; default : break ; } if ( BYTES_BIG_ENDIAN || ( rs6000_altivec_element_order == <NUM_LIT> ) ) builtin_define ( <STR_LIT> ) ; else builtin_define ( <STR_LIT> ) ; if ( TARGET_SOFT_FLOAT || ! TARGET_FPRS ) builtin_define ( <STR_LIT> ) ; if ( ( TARGET_MACHO && rs6000_darwin64_abi ) || DEFAULT_ABI == ABI_ELFv2 || ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) ) builtin_define ( <STR_LIT> ) ; if ( rs6000_xilinx_fpu ) { builtin_define ( <STR_LIT> ) ; if ( rs6000_single_float && ! rs6000_double_float ) { if ( rs6000_simple_fpu ) builtin_define ( <STR_LIT>


<s> return ( __m128i ) __builtin_ia32_pmovzxbq128_mask ( ( __v16qi ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8


<s> inline static uint64_t getImmVal ( const


<s> } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * GVSym ; else O << '(' << * GVSym << ')' ; printOffset ( MO . getOffset ( ) , O ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const MCSymbol * SymToPrint ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) , true ) ; } SymToPrint = StubSym . getPointer ( ) ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * SymToPrint ; else O << '(' << * SymToPrint << '(' ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case


<s> EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ( ! Subtarget -> hasFMA ( ) && ! Subtarget -> hasFMA4 ( ) && ! Subtarget -> hasAVX512 ( ) ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B .


<s> static MachineBasicBlock * insertDivByZeroTrap ( MachineInstr & MI , MachineBasicBlock & MBB , const TargetInstrInfo & TII , bool Is64Bit , bool IsMicro<ISA_LIT> ) { if ( NoZeroDivCheck ) return & MBB ; MachineBasicBlock :: iterator I ( MI ) ; MachineInstrBuilder MIB ; MachineOperand & Divisor = MI . getOperand ( <NUM_LIT> ) ; MIB = BuildMI ( MBB , std :: next ( I ) , MI . getDebugLoc ( ) , TII . get ( IsMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Divisor .

getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>WinCOFFObjectWriter ( OS


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , true ) ; case <STR_LIT> : case <STR_LIT> : return emitSEL_D ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , false , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPseudoSELECT ( MI , BB , true , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue LSEL = DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , LHS , True , False , LHS . getOperand ( <NUM_LIT> ) ) ; SDValue RSEL = DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , RHS , True , False , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , LSEL ,


<s> BBInfo . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) computeBlockSize


<s> case <STR_LIT> : if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op00 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op00 . getOpcode ( ) == <STR_LIT> ) { Tmp1 = LowerVectorIntExtend ( Op00 , Subtarget , DAG ) ; if ( Tmp1 . getNode ( ) ) { EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; if ( ExtraEltVT == <STR_LIT> || ExtraEltVT == <STR_LIT> || ExtraEltVT == <STR_LIT> ) { SDValue Tmp1Op0 = Tmp1 . getOperand ( <NUM_LIT> ) ; assert ( Tmp1Op0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction &


<s> next_feature_string = strchr ( curr_feature_string , ',' ) ; if ( next_feature_string ) * next_feature_string ++ = '\0' ; if ( * curr_feature_string == '^' ) { curr_feature_string ++ ; clear = true ; } for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; i ++ ) { if ( ! strcmp ( curr_feature_string , ix86_tune_feature_names [ i ] ) ) { ix86_tune_features [ i ] = ! clear


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNoGINV (


<s> if ( Imm == <NUM_LIT> || Imm == ~ <NUM_LIT> || ( RegSize != <NUM_LIT> && ( Imm >> RegSize != <NUM_LIT> || Imm == ~ <NUM_LIT> ) ) ) return false ; unsigned Size = RegSize ; do { Size /= <NUM_LIT> ; uint64_t Mask = ( <NUM_LIT> << Size ) - <NUM_LIT> ; if ( ( Imm & Mask ) != ( ( Imm >> Size ) & Mask ) ) { Size *= <NUM_LIT> ; break ; } } while ( Size > <NUM_LIT> ) ; uint32_t CTO , I ; uint64_t Mask = ( ( uint64_t ) - <NUM_LIT> ) >> ( <NUM_LIT> - Size ) ; Imm &= Mask ; if ( isShiftedMask_64 ( Imm ) ) { I = countTrailingZeros ( Imm ) ; assert ( I < <NUM_LIT> && <STR_LIT> ) ; CTO = countTrailingOnes ( Imm >> I ) ; } else { Imm |= ~ Mask ; if ( ! isShiftedMask_64 ( ~ Imm ) ) return false ; unsigned CLO = countLeadingOnes ( Imm ) ; I = <NUM_LIT> - CLO ; CTO = CLO + countTrailingOnes ( Imm ) - ( <NUM_LIT> - Size ) ; } assert ( Size > I && <STR_LIT> ) ; unsigned Immr = ( Size - I ) & ( Size - <NUM_LIT> ) ; uint64_t NImms = ~ ( Size - <NUM_LIT> ) << <NUM_LIT> ; NImms |= ( CTO - <NUM_LIT> ) ; unsigned N = ( ( NImms >> <NUM_LIT> ) & <NUM_LIT> ) ^ <NUM_LIT> ; Encoding = ( N << <NUM_LIT> ) | ( Immr << <NUM_LIT> ) | ( NImms & <NUM_LIT> ) ; return true


<s> } } ; assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; int RegisterFileMoveCost = <NUM_LIT> ; if ( Index == - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { assert ( isa < FixedVectorType > ( Val ) && <STR_LIT> ) ; Align VecAlign = DL . getPrefTypeAlign ( Val ) ; Align SclAlign = DL . getPrefTypeAlign ( ScalarType ) ; if ( Opcode == Instruction :: ExtractElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } if ( Opcode == Instruction :: InsertElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Store , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index % NumElts ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) { assert ( ( LT . second . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubVecs = LT . second . getSizeInBits ( ) / <NUM_LIT> ; SubNumElts = NumElts / NumSubVecs ; if ( SubNumElts <= Index ) { RegisterFileMoveCost += ( Opcode == Instruction :: InsertElement ? <NUM_LIT> : <NUM_LIT> ) ; Index %= SubNumElts ; } } if ( Index == <NUM_LIT> ) { if ( ScalarType -> isFloatingPointTy ( ) ) return RegisterFileMoveCost ; if ( ScalarType -> isIntegerTy ( ) && Opcode == Instruction :: ExtractElement ) return <NUM_LIT> + RegisterFileMoveCost ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode


<s> void DecodeMOVHLPSMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = NElts / <NUM_LIT> ; i != NElts

; ++ i ) ShuffleMask . push_back ( NElts + i ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return


<s> static inline int andcosts ( rtx x ) { int i ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( TARGET_SHMEDIA ) { if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) || EXTRA_CONSTRAINT_C16 ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } if ( i == <NUM_LIT> || i == <NUM_LIT> ) return <NUM_LIT> ; if ( CONST_OK_FOR_K08 ( i ) ) return <NUM_LIT> ; if ( CONST_OK_FOR_I08 ( i ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet =


<s> assert ( CE != nullptr && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( CE


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> void <ISA_LIT>MCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == <NUM_LIT> && isMicro<ISA_LIT> ( STI ) ) { emitInstruction ( Val >> <NUM_LIT> , <NUM_LIT> , STI , OS ) ; emitInstruction ( Val , <NUM_LIT> ,


<s> for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) .


<s> case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFNEGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTRUNCATECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return performFMaxNumCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformBLENDICombine ( N ,


<s> for ( MachineBasicBlock :: iterator miI = std :: next ( Itr ) , miE = BB -> end ( ) ; miI != miE ; ++ miI ) { const MachineInstr & mi = * miI ; if ( mi . readsRegister ( <STR_LIT> ) ) return true ; if ( mi . definesRegister ( <STR_LIT> ) ) return false ; } for ( MachineBasicBlock :: succ_iterator sItr = BB -> succ_begin ( ) , sEnd = BB -> succ_end ( ) ; sItr != sEnd ; ++ sItr ) { MachineBasicBlock * succ =


<s> } if ( ( pstate_field == <STR_LIT> || pstate_field == <STR_LIT> || pstate_field == <STR_LIT> ) && crm > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; auto PState = <STR_LIT> ( pstate_field ) ; if ( PState && PState -> haveFeatures ( Decoder -> getSubtargetInfo ( ) . getFeatureBits (


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF ) . test


<s> t = __ev_mwhumi ( a , b ) ; return __ev_addusiaaw ( t


<s> TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; const auto * GA = cast < GlobalAddressSDNode > ( Op ) ; auto * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <STR_LIT> ) ; SDValue Offset = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetConstantPool ( CPV , PtrVT , Align ( <NUM_LIT> ) ) ) , MachinePointerInfo :: getConstantPool (


<s> const MachineOperand & Def = * MRI -> def_begin ( VirtReg ) ; MachineInstr * MI = const_cast < MachineInstr * > ( Def . getParent ( ) ) ; unsigned OpCode = MI -> getOpcode ( ) ; switch ( OpCode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; ShapeT Shape ( & MO1 , & MO2 , MRI ) ; VRM -> assignVirt2Shape ( VirtReg , Shape


<s> FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( StackSlot ) ; MachineMemOperand * MMO ; if ( FI ) { int SSFI = FI -> getIndex ( ) ; MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , ByteSize , ByteSize ) ; } else { MMO = cast < LoadSDNode > ( StackSlot ) -> getMemOperand ( ) ; StackSlot = StackSlot . getOperand ( <NUM_LIT> ) ; } SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , SrcVT , MMO ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueType ( ) . getSizeInBits (


<s> fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; half = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; xa = expand_simple_binop ( mode , PLUS , xa , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xi = gen_reg_rtx ( int_mode_for_mode ( mode ) . require ( ) ) ; expand_fix ( xi , xa , <NUM_LIT>


<s> return ( int8x16_t ) __builtin_neon_vshl_nv16qi


<s> if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return Opc ; if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? Opcodes .


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> bool hasD16 ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT>


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F )


<s> if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) &


<s> Value * <ISA_LIT>IREmitter :: visitPMULUDQ ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( FP_REG_P ( regno ) && MSA_SUPPORTED_MODE_P ( mode ) ) return true ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == <NUM_LIT> || ( MIN_FPRS_PER_FMT == <NUM_LIT> && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= <NUM_LIT> && ( regno & <NUM_LIT> ) != <NUM_LIT> ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & <NUM_LIT> ) != <NUM_LIT> ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass

== MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ;


<s> SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1


<s> OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> emitLabel ( Target


<s> Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT

. is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) {


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic


<s> bool hasVectorPackedDecimalEnhancement2 ( )


<s> static bool vr4130_true_reg_dependence_p ( rtx


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue (


<s> rtx set = gen_rtx_SET ( dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; } else if ( MEM_P ( src ) && ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , <NUM_LIT> ) ; rtx src_reg = XEXP ( pmv , <NUM_LIT> ) ; rtx src_mod = XEXP ( pmv , <NUM_LIT> ) ; rtx set = gen_rtx_SET ( src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM (


<s> if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + <NUM_LIT> ; case TYPE_LOAD : case TYPE_SLOAD : case TYPE_FPLOAD : if ( dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE ) { if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET || GET_CODE ( SET_DEST ( dep_pat ) ) != MEM || GET_CODE ( SET_SRC ( pat ) ) != MEM || ! rtx_equal_p ( XEXP ( SET_DEST ( dep_pat ) , <NUM_LIT> ) , XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) ) return cost + <NUM_LIT> ; return cost +


<s> return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = llvm :: <STR_LIT> ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( )


) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const { if ( MBB . empty ( )


<s> parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = ( getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) ; IsCpRestoreSet = false ; CpRestoreOffset = - <NUM_LIT> ; Triple TheTriple ( sti . getTargetTriple ( ) ) ; if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) ==

Triple :: mips64 ) ) IsLittleEndian = false ;


<s> return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || isLittleEndian ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false


<s> inline vector unsigned int vec_vmuleuh ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned int ) __builtin_altivec_vmuleuh ( ( vector signed short ) a1 , ( vector


<s> static DecodeStatus DecodeFGRH32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void


<s> <STR_LIT> ExtType = LD -> getExtensionType ( ) ; bool InsertTo64 = false ; if ( VT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = true ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return nullptr ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; Done = true ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT>