<s> case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: ExtractValue : return <ISA_LIT>SelectExtractValue ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; UpdateValueMap ( I , Reg ) ; return true ; } } return


<s> void <ISA_LIT>InstrInfo :: expandLOCPseudo ( MachineInstr & MI , unsigned

LowOpcode , unsigned HighOpcode ) const {


<s> void <ISA_LIT>InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT>


<s> SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff ,

dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , false , false , <NUM_LIT> ) ;


<s> PM . add ( createBasicTargetTransformInfoPass ( getTargetLowering ( ) ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> Target & llvm :: getThe<ISA_LIT>64LETarget (


<s> auto & DL = DCT . getDataLayout ( ) ; auto getRegOffset = [ & ] ( unsigned Reg ) { return DCT . getRegSetDesc ( ) . getRegSizeOffsetInRegSet ( Reg , DL , DCT . getMRI ( ) ) . second ; } ; std :: string IAStr ; raw_string_ostream ( IAStr ) << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> << getRegOffset ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ; Type * IAArgTypes [ ] = { RegSet -> getType ( ) , ExternalFunc -> getType ( ) } ; InlineAsm * IA = InlineAsm :: get ( FunctionType :: get ( Builder . getVoidTy ( ) , IAArgTypes , false ) , IAStr , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , true , false ) ; Builder . CreateCall ( IA , { RegSet , ExternalFunc


<s> return ( __m128i ) __builtin_ia32_punpckhwd128 ( ( __v8hi ) __A , (


<s> if ( ! ElemN ) return <NUM_LIT> ; SDValue Vec = Value . getOperand ( <NUM_LIT> ) ; EVT VT = Vec . getValueType ( ) ; unsigned Elem = ElemN -> getZExtValue ( ) ; if ( Elem >= VT . getVectorNumElements ( ) ) return <NUM_LIT> ; SDValue Base , Disp , Index ; if ( ! selectBDVAddr12Only ( Store -> getBasePtr ( ) , ElemV , Base , Disp , Index ) || Index . getValueType ( ) != VT . changeVectorElementTypeToInteger ( ) ) return <NUM_LIT> ; SDLoc DL ( Store ) ; SDValue Ops [ ] = { Vec , Base , Disp , Index , CurDAG -> getTargetConstant ( Elem , DL

, <STR_LIT> ) , Store -> getChain ( ) } ;


<s> static __inline qword si_cgth ( qword a , qword


<s> static bool or1k_frame_pointer_required ( ) { return ( crtl


<s> Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( getPointerTy ( ) ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; const unsigned Reg = ( Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned SPReg = RegInfo ->


<s> if ( insn -> mode == MODE_64BIT ) return prefix >= <NUM_LIT>


<s> CommentString = <STR_LIT> ; CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; UseDataRegionDirectives = true ; ExceptionsType = ExceptionHandling ::


<s> SDValue TlsReadTp ; if ( NaClReadTp == NULL ) TlsReadTp = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; else TlsReadTp = DAG . getGlobalAddress ( NaClReadTp , DL , PtrVT ) ; ArgListTy Args ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , PtrTy , TlsReadTp , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult


<s> SDValue DataToStore = N -> getValue ( ) ; MVT VT = DataToStore . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; SDValue Mask = N -> getMask ( ) ; SDLoc dl ( Op ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , Mask ,

N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> isTruncatingStore ( ) ) ;


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; } else { MCSymbol * TOCOffset = <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ; const MCExpr * TOCOffsetDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCOffset , OutContext ) , GlobalEntryLabelExp , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCOffsetDeltaExpr ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } MCSymbol * LocalEntryLabel = <ISA_LIT>FI -> getLocalEPSymbol ( ) ; OutStreamer -> EmitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: createSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitLocalEntry ( cast < MCSymbolELF


<s> NopInst . addOperand ( MCOperand :: CreateImm (


<s> REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) <<


<s> bool runOnMachineFunction ( MachineFunction


<s> return ( __m128i ) __builtin_ia32_aesdec128 ( ( __v2di


<s> LivePhysRegs LiveRegs ( TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineBasicBlock * RestMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) RestMBB -> addLiveIn ( * I ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MoveMBB -> addLiveIn ( * I ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ; MBB . addSuccessor ( RestMBB ) ; MBB . addSuccessor ( MoveMBB ) ; BuildMI ( * MoveMBB , MoveMBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MI . getOperand ( <NUM_LIT> ) ) ) ; MoveMBB -> addSuccessor ( RestMBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LOCRMuxJumps ++ ; return


<s> return ( GET_CODE ( x ) == SYMBOL_REF && startswith ( XSTR ( x , <NUM_LIT>


<s> if ( I == MemOp2RegOpTable . end ( ) ) return <NUM_LIT> ; bool FoldedLoad = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; bool FoldedStore = I -> second . second & ( <NUM_LIT> <<


<s> if ( opCode == <STR_LIT> ) return <STR_LIT> ; if ( opCode == <STR_LIT> ) return <STR_LIT> ; if ( opCode == <STR_LIT> ) return <STR_LIT> ; if ( opCode == <STR_LIT> )


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( )


<s> if ( ( State . I == <NUM_LIT> ) && ( State . SaveCount == <NUM_LIT> ) ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; } } if ( State . I < State . SaveCount ) { assert ( State . I < State . MaxSaved && <STR_LIT> ) ; State . Saved [ State . I ++ ] = Inst ; if ( State . I < State . SaveCount ) return true ; } assert ( State . I == State . SaveCount && State . SaveCount > <NUM_LIT> && <STR_LIT> ) ; State . RecursiveCall = true ; switch ( State . Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardCall ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardJmp ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardReturn ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardLoadOrStore ( State . I , State . Saved


<s> assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue V = lowerV2X128Shuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 ,

Mask , Zeroable , Subtarget , DAG ) ) return Shift ;


<s> const char * name ; name = fcode == RS6000_OVLD_VEC_SPLATS ? <STR_LIT> : <STR_LIT> ; if ( fcode == RS6000_OVLD_VEC_SPLATS && nargs != <NUM_LIT> ) { error ( <STR_LIT> , name ) ; * res = resolved ; return error_mark_node ; } if ( fcode == RS6000_OVLD_VEC_PROMOTE && nargs != <NUM_LIT> ) { error ( <STR_LIT> , name ) ; * res = resolved ; return error_mark_node ; } if ( fcode == RS6000_OVLD_VEC_PROMOTE && ! INTEGRAL_TYPE_P ( TREE_TYPE ( ( * arglist ) [ <NUM_LIT> ] ) ) ) { * res = resolved_bad ; return error_mark_node ; } tree arg = ( * arglist ) [ <NUM_LIT> ] ; tree type = TREE_TYPE ( arg ) ; if ( ! SCALAR_FLOAT_TYPE_P ( type ) && ! INTEGRAL_TYPE_P ( type ) ) { * res = resolved_bad ; return error_mark_node ; } bool unsigned_p = TYPE_UNSIGNED ( type ) ; int size ; switch ( TYPE_MODE ( type ) ) { case E_TImode : type = unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node ; size =


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF


<s> aarch64_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; aarch64_simd_types [ Uint64x1_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Poly8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype = build_distinct_type_copy ( unsigned_intQI_type_node ) ; aarch64_simd_types [ Poly16_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype = build_distinct_type_copy ( unsigned_intHI_type_node ) ; aarch64_simd_types [ Poly64_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype = build_distinct_type_copy ( unsigned_intDI_type_node ) ; aarch64_simd_types [ Poly128_t ] . eltype = aarch64_simd_types [ Poly128_t ] . itype = build_distinct_type_copy ( unsigned_intTI_type_node ) ; aarch64_simd_types [ Poly8x8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly8x16_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly16x4_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly16x8_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly64x1_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Poly64x2_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Float32x2_t ] . eltype = float_type_node ; aarch64_simd_types [ Float32x4_t ] . eltype = float_type_node ; aarch64_simd_types [ Float64x1_t ] . eltype = double_type_node ; aarch64_simd_types [ Float64x2_t ] . eltype = double_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = aarch64_simd_types [ i ] . eltype ; enum machine_mode mode = aarch64_simd_types [ i ] .


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Immediate , Parser ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> return ( AlignBoundary != Align :: None (


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( )


<s> struct unw_reg_state * rs = alloc_reg_state ( ) ; memcpy ( rs , & sr -> curr , sizeof (


<s> EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; APInt KnownUndef , KnownZero ; unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnes ( NumElts ) ; return getTargetShuffleInputs ( Op , DemandedElts , Inputs , Mask , KnownUndef , KnownZero , DAG ,


<s> static DecodeStatus readInstruction64 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint64_t & Insn , bool IsLittleEndian ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = IsLittleEndian ? ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) : ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t

) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; const MCExpr * E = MO . getExpr ( ) ; MCFixupKind Kind ; if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( E ) ) { const int64_t Value = MCE


<s> MVT VecVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; unsigned NumElemsPerChunk = VecWidth / VecVT . getScalarSizeInBits ( ) ; return getI8Imm ( Index /


<s> bool hasPOPCNTFalseDeps ( ) const { return HasPOPCNTFalseDeps


<s> Type * BCTy = BitCast -> getType ( ) ; Type * BCSrcTy = BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( BCTy -> getVectorNumElements ( ) == BCSrcTy -> getVectorNumElements ( )


<s> return __builtin_mve_vrndaq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) ,


<s> SDValue EltCount = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getValueType ( MeasureVT ) ) ; EltCount = DAG . getZExtOrTrunc ( EltCount , dl , EltType


<s> return true ; } if ( Offset > <NUM_LIT> ) { if ( Opcode == <STR_LIT> ) { removeOperands ( MI , FrameRegIdx ) ; MachineInstrBuilder MIB ( & MI ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Mask ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Mask ) ; } Offset = ( Offset - Mask * Scale ) ; MachineBasicBlock :: iterator NII = llvm :: next ( II ) ; emitThumbRegPlusImmediate ( MBB , NII , DestReg , DestReg , Offset , TII , * this , dl ) ; } else { emitThumbConstant ( MBB , II , DestReg , Offset , TII , * this , dl ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( DestReg , false , false , true ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false ) ; if ( Opcode == <STR_LIT> ) { MachineInstrBuilder MIB ( & MI ) ; AddDefaultPred ( MIB ) ; } } return true ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset


<s> const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledValue ( ) ; if ( isa < InlineAsm > ( Callee ) || isa < IntrinsicInst > ( CI ) ) return false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CC = CS . getCallingConv ( ) ; PointerType * PT = cast < PointerType > ( CS . getCalledValue ( ) -> getType ( ) ) ; FunctionType * FTy = cast < FunctionType > ( PT -> getElementType ( ) ) ; if ( FTy -> isVarArg ( ) ) return false ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( Enable<ISA_LIT>LongCalls ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( CS . arg_size ( ) ) ; ArgRegs . reserve ( CS . arg_size ( ) ) ; ArgVTs . reserve ( CS . arg_size ( ) ) ; ArgFlags . reserve ( CS . arg_size ( ) ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt


<s> void <ISA_LIT>MachObjectWriter :: Record<ISA_LIT>ScatteredHalfRelocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) { uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: <ISA_LIT>_RELOC_HALF ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; if ( ! A -> getFragment ( ) ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; return ; } uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; return ; } Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; case <STR_LIT> : ThumbBit = <NUM_LIT> ; break ; } if ( Type == MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ) { uint32_t OtherHalf = MovtBit ? ( FixedValue & <NUM_LIT> ) : ( ( FixedValue & <NUM_LIT> ) >> <NUM_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( OtherHalf << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE


<s> if ( optimize > <NUM_LIT> && selected_cpu -> tune -> max_case_values != <NUM_LIT> ) return selected_cpu


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo


<s> MachineInstrBuilder MIB { MF , I } ; bool isSExt = false ; using namespace TargetOpcode ; switch ( I . getOpcode ( ) ) { case G_SEXT : isSExt = true ; LLVM_FALLTHROUGH ; case G_ZEXT : { LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLT SrcTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; switch ( SrcSize ) { case <NUM_LIT> : { I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( isSExt ) { unsigned SExtResult = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AndResult = MRI . createVirtualRegister ( & <STR_LIT> ) ; I . getOperand ( <NUM_LIT> ) . setReg ( AndResult ) ; auto InsertBefore = std :: next ( I . getIterator ( ) ) ; auto SubI = BuildMI ( MBB , InsertBefore , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( SExtResult ) . addUse ( AndResult ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : case G_GEP : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FADD : if ( ! selectFAdd ( MIB , TII , MRI ) ) return false ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_CONSTANT : { unsigned Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getType ( Reg ) .

getSizeInBits ( ) != <NUM_LIT> ) return false ;


<s> MCOperand ATReg = MCOperand :: CreateReg ( <STR_LIT> ) ; BaseReg = ATReg ; MCInsts . resize ( <NUM_LIT> ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , ATReg , ZEROReg , MCOperand :: CreateImm ( Hi ) ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , ATReg , ATReg , SPReg ) ; } MCInst St


<s> if ( count == <NUM_LIT> && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - <NUM_LIT> ) base_reg -= <NUM_LIT> ; count ++ ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + <NUM_LIT> ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - ( count * <NUM_LIT> + <NUM_LIT> ) ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT (


<s> bool hasDiv ( ) const { return HasDiv


<s> bool is64Bit = Triple . getArch ( ) == Triple :: x86_64 ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit )


<s> return __arm_vcvtmq_m_u32_f32 ( __inactive ,


<s> if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler


<s> while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( type != error_mark_node && TYPE_MODE ( type ) == DFmode ) align = MAX ( align , <NUM_LIT> ) ; } return align


<s> if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI


<s> return __builtin_ia32_movmskpd ( ( __v2df ) __A )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) ) ; return true ; } return


<s> return ( ( vec_ullong2 ) ( si_dftsv ( ( qword ) ( a ) , b


<s> const TargetInstrDesc & Desc = MI -> getDesc ( ) ; bool IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; bool Is64BitMode = TM . getSubtargetImpl ( ) -> is64Bit ( ) ; unsigned Size = GetInstSizeWithDesc ( * MI , & Desc , IsPIC ,


<s> static unsigned int mips_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY


<s> osize = rsize ; } t = build2 ( NE_EXPR , boolean_type_node , unshare_expr ( off ) , build_int_cst ( TREE_TYPE ( off ) , <NUM_LIT> ) ) ; addr = build3 ( COND_EXPR , ptr_type_node , t , NULL_TREE , NULL_TREE ) ; t = fold_convert ( TREE_TYPE ( off ) , build_int_cst ( NULL_TREE , rsize ) ) ; t = build2 ( POSTDECREMENT_EXPR , TREE_TYPE ( off ) , off , t ) ; t = fold_convert ( sizetype , t ) ; t = fold_build1 ( NEGATE_EXPR , sizetype , t ) ; t = fold_build_pointer_plus ( top , t ) ; if ( BYTES_BIG_ENDIAN && rsize > size ) t = fold_build_pointer_plus_hwi ( t , rsize - size ) ; COND_EXPR_THEN ( addr ) = t ; if ( osize > UNITS_PER_WORD ) { t = fold_build_pointer_plus_hwi ( unshare_expr ( ovfl ) , osize - <NUM_LIT> ) ; u = build_int_cst ( TREE_TYPE ( t ) , - osize ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , u ) ; align = build2 ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , unshare_expr ( ovfl ) , t ) ; } else align = NULL ; u = fold_convert ( TREE_TYPE ( ovfl ) , build_int_cst ( NULL_TREE , osize ) ) ; t = build2 ( POSTINCREMENT_EXPR , TREE_TYPE ( ovfl ) , ovfl , u ) ; if ( BYTES_BIG_ENDIAN && osize > size ) t = fold_build_pointer_plus_hwi ( t , osize - size ) ; if ( align ) t = build2 ( COMPOUND_EXPR , TREE_TYPE ( t ) , align , t ) ; COND_EXPR_ELSE ( addr ) = t ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } if ( indirect_p ) addr = build_va_arg_indirect_ref ( addr ) ; return addr


<s> bool IsDouble = StringSwitch < bool > ( Mnemonic . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT>

, true ) . Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> int64_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( this -> TRI -> hasBasePointer ( MF ) ) { if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; <ISA_LIT>FI -> setHasSEHFramePtrSave ( true ) ; <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i -


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: ParseOperand ( StringRef Mnemonic ) { if ( isParsingIntelSyntax ( ) ) return


<s> temp . val [ <NUM_LIT> ] = vcombine_u8 ( __tab . val [ <NUM_LIT> ] , __tab . val [ <NUM_LIT> ] ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; result = ( uint8x8_t ) __builtin_aarch64_tbx4v8qi ( ( int8x8_t ) __r , __o , ( int8x8_t ) __idx ) ; return result


<s> bool isCOP0AsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_COP0 && RegIdx . Index


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; return AddCombineTo64bitUMAAL ( N , DCI


<s> return ( poly8x8_t ) __builtin_neon_vreinterpretv8qidi


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case


<s> bool gate ( function * ) { return ! TARGET_LINUX_ABI &&


<s> int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> &&


<s> SDValue Src0 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; SDValue Src1 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpc0 = Src0 . getOpcode ( ) ; unsigned SrcOpc1 = Src1 . getOpcode ( ) ; EVT SrcVT0 = Src0 . getValueType ( ) ; EVT SrcVT1 = Src1 . getValueType ( ) ; if ( ! Src1 . isUndef ( ) && ( SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1 ) ) return SDValue ( ) ; switch ( SrcOpc0 ) { case <STR_LIT> : { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> : if ( SrcVT0 == <STR_LIT> ) { uint64_t Mask = Src0 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask & <NUM_LIT> ) != ( ( Mask >> <NUM_LIT> ) & <NUM_LIT> ) ) break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Src1 . isUndef ( ) || Src0 . getOperand ( <NUM_LIT> ) == Src1 . getOperand ( <NUM_LIT> ) ) { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V


<s> static const MCPhysReg CU64BitRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const MCPhysReg * CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs ; for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ; return - <NUM_LIT>


<s> break ; case Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case Token


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T ,


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_H44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_M44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_L44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HH ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HM ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT13 ) . Case ( <STR_LIT> , VK_Sparc_R_DI<ISA_LIT>32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_LO10 ) . Case ( <STR_LIT>

, VK_<ISA_LIT>_TLS_LDM_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_LOX10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LDX ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_LOX10 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op ,


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; } OS << <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerAAPCS_VASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue VAList = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue Stack = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackIndex ( ) , PtrVT ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , Stack , VAList , MachinePointerInfo ( SV ) , Align ( <NUM_LIT> ) ) ) ; int GPRSize = FuncInfo -> getVarArgsGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRIndex ( ) , PtrVT ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , GRTop , DAG . getConstant ( GPRSize , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ) ; } int FPRSize = FuncInfo -> getVarArgsFPRSize ( ) ; if ( FPRSize > <NUM_LIT> ) { SDValue VRTop ,


<s> if ( ( ( mask2 == <NUM_LIT> || ( mask2 & ix86_isa_flags2 ) != <NUM_LIT> ) && ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( mask2 == OPTION_MASK_ISA2_AVXIFMA ) || ( mask2 == ( OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] .


<s> switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return Z ; case NE : return <NUM_LIT> ; case CS : return C ; case CC : return <NUM_LIT> ; case MI : return N ; case PL : return <NUM_LIT> ; case VS : return V ; case VC :


<s> return code == MEM || ( TARGET_SH4 &&


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { EVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } } return true


<s> return __arm_vqdmlsdhxq_s32 ( __inactive ,


<s> if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , NULL , <NUM_LIT> , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , DstVT , dl , Store , MemTmp , NULL , <NUM_LIT> , MemVT , false , false , <NUM_LIT> ) ; -- I


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return


<s> MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( DefReg ) ) { int UseIdx = SwapMap [ & UseMI ] ; SwapVector [ UseIdx ] . WillRemove = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( UseMI . dump ( ) ) ; } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { int Repr = EC -> getLeaderValue ( SwapVector [ EntryIdx ] . VSEId ) ; if ( ! SwapVector [ Repr ] . WebRejected ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; int DefIdx = SwapMap [ DefMI ] ; SwapVector [ DefIdx ] . WillRemove = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ) ; } } else if ( SwapVector [ EntryIdx ] . IsSwappable && SwapVector [ EntryIdx ] . SpecialHandling != <NUM_LIT> ) { int Repr = EC -> getLeaderValue ( SwapVector [ EntryIdx


<s> return __builtin_mve_vdupq_m_n_uv8hi ( __inactive ,


) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> FrameReg = RI -> getFrameRegister ( MF ) ; int64_t Offset = ( MFFrame . getObjectOffset ( FI ) + MFFrame . getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea


<s> if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) &&


<s> return false ; } StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement (


<s> Opcode = <STR_LIT> ; IsRightShift = false ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; } if ( IsRightShift && ShiftAmount <= - <NUM_LIT> && ShiftAmount >= - ( int ) ElemBits ) return DAG . getNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - ShiftAmount , <STR_LIT> ) ) ; else if ( ! IsRightShift && ShiftAmount >= <NUM_LIT> && ShiftAmount < ElemBits ) return DAG . getNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ShiftAmount , <STR_LIT> ) ) ; return SDValue


<s> TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; for ( Target * T : { & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , createThumbMCInstrAnalysis ) ; for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>LEAsmBackend ) ; } for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>BEAsmBackend


<s> assert ( ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX2 ( ) || Domain < <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX2 ( MI -> getOpcode ( ) , dom ) ; } assert ( table && <STR_LIT> ) ; MI -> setDesc ( get ( table [ Domain -


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef Triple , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , Triple , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , Subtarget ( Triple , CPU , FS ) , InstrInfo ( * this )

, FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; break ; } } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combinePCMPAnd1 ( N , DAG ) ) return ShiftRight ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget . hasBMI ( ) && ! Subtarget . hasTBM ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> && N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue ( ) ; if ( isMask_64 ( Mask ) ) { uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift + MaskSize <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG .

getConstant ( Shift | ( MaskSize << <NUM_LIT> ) , DL , VT ) ) ;


<s> Chain ( MachineInstr * MI , unsigned Idx , Color C ) : StartInst ( MI ) , LastInst ( MI ) , KillInst ( nullptr ) , StartInstIdx ( Idx ) , LastInstIdx ( Idx ) , KillInstIdx ( <NUM_LIT> ) , LastColor ( C ) { Insts . insert (


<s> static SDValue LowerSIGN_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_Mask ( Op , Subtarget , DAG ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i


<s> assert ( Displacement >= <NUM_LIT> ) ; if ( Displacement == <NUM_LIT> ) { EmitLEA ( Op , VT , Reg , Out ) ; return ; } int64_t Residue ; std :: unique_ptr < <ISA_LIT>Operand > NewOp = AddDisplacement ( Op , Displacement , Ctx , & Residue ) ; EmitLEA ( * NewOp , VT , Reg , Out ) ; while ( Residue != <NUM_LIT> ) { const MCConstantExpr * Disp = MCConstantExpr :: Create ( ApplyDisplacementBounds ( Residue ) , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > DispOp = <STR_LIT> ( <NUM_LIT> , Disp , Reg , <NUM_LIT> , <NUM_LIT>


<s> TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ; SDValue Offset ; switch ( model ) { case TLSModel :: GeneralDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; break ; } case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel ::


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Tok = Parser . getTok ( ) . getIdentifier ( ) ; if ( Tok [ <NUM_LIT> ] != 'c' && Tok [ <NUM_LIT> ] != 'C' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex (


<s> return SelectAddrModeIndexedBitWidth ( N , true , <NUM_LIT>


<s> static SDValue lowerV8I64VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG


<s> return ( ( vec_double2 ) ( si_shlqby ( ( qword ) ( a ) , si_from_uint (


<s> SDValue <ISA_LIT>TargetLowering :: LowerSIGN_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op -> getValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; DebugLoc dl = Op -> getDebugLoc ( ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT>


<s> needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F ->

getFnAttributes ( ) . hasStackAlignmentAttr ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> else start_regno = <NUM_LIT> ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , <NUM_LIT> ) ) ; if ( total_bytes < <NUM_LIT> ) { dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_label ( byte_mode_loop ) ; nds32_emit_post_inc_load_store ( tmp , src_itr , QImode , true ) ; nds32_emit_post_inc_load_store ( tmp , dst_itr , QImode ,


<s> SDValue OpsY3 [ ] = { TmpY2 , TmpE2 , TmpY2 , TmpPR } ; TmpY3 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsY3 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpY3 . getValue ( <NUM_LIT> ) ; SDValue OpsQ0 [ ] = { Tmp1 , TmpY3 , F0 , TmpPR } ; TmpQ0 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ0 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ0 . getValue ( <NUM_LIT> ) ; SDValue OpsR0 [ ] = { Tmp2 , TmpQ0 , Tmp1 , TmpPR } ; TmpR0 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsR0 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpR0 . getValue ( <NUM_LIT> ) ; SDValue Ops [ ] = { TmpF5 , TmpY3 , TmpR0 , TmpQ0 , TmpPR } ; Result = CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; Chain = SDValue ( Result , <NUM_LIT> ) ; return Result ; } else { SDValue TmpQ2 , TmpR2 , TmpQ3 , TmpQ ; SDValue OpsQ2 [ ] = { TmpF3 , TmpY2 , F0 , TmpPR } ; TmpQ2 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ2 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ2 . getValue ( <NUM_LIT> ) ; SDValue OpsR2 [ ] = { TmpF4 , TmpQ2 , TmpF3 , TmpPR } ; TmpR2 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsR2 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpR2 . getValue ( <NUM_LIT> ) ; SDValue OpsQ3 [ ] = { TmpF5 , TmpR2 , TmpY2 , TmpQ2 , TmpPR } ; TmpQ3 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ3 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ3 . getValue ( <NUM_LIT> ) ; if ( isSigned ) TmpQ = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ3 ) , <NUM_LIT> ) ; else TmpQ = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ3 ) , <NUM_LIT> ) ; Chain = TmpQ . getValue ( <NUM_LIT> ) ; if ( isModulus ) { SDValue FPminusB = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , minusB ) , <NUM_LIT> ) ; Chain = FPminusB . getValue ( <NUM_LIT> ) ; SDValue Remainder = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ , FPminusB , TmpF1 ) , <NUM_LIT> ) ; Chain = Remainder . getValue ( <NUM_LIT> ) ; Result = CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Remainder ) ; Chain = SDValue ( Result , <NUM_LIT> ) ; } else


<s> return __builtin_mve_vmulltq_int_uv16qi ( __a ,


<s> unsigned basereg = is64BitMode ( ) ? <STR_LIT> : <STR_LIT> ; return ( Op . isMem ( ) && ( Op . Mem . SegReg == <NUM_LIT> || Op . Mem . SegReg == <STR_LIT> ) && isa < MCConstantExpr > ( Op . Mem . Disp ) && cast < MCConstantExpr > ( Op . Mem . Disp ) -> getValue (

) == <NUM_LIT> && Op . Mem . BaseReg == basereg && Op . Mem . IndexReg == <NUM_LIT> ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _saveprevssp ( void ) { __builtin_ia32_saveprevssp (


<s> void <ISA_LIT>LongBranch :: replaceBranch ( MachineBasicBlock & MBB , Iter Br , DebugLoc DL , MachineBasicBlock * MBBOpnd ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; unsigned NewOpc = TII -> getOppositeBranchOpc ( Br -> getOpcode ( ) ) ; const MCInstrDesc & NewDesc = TII -> get ( NewOpc ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB ( MBBOpnd ) ; assert ( Br -> isBundledWithSucc ( ) ) ; MachineBasicBlock :: instr_iterator II ( Br ) ; MIBundleBuilder ( & * MIB ) . append ( ( ++ II ) -> removeFromBundle ( ) ) ; Br -> eraseFromParent


<s> static rtx gen_fr_spill_x ( rtx dest , rtx src , rtx


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo

. getNextStackOffset ( ) , <NUM_LIT> ) ;


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx rval


<s> bool isUImm ( ) const { if ( ! isImm ( ) ) return false ; return isa < MCConstantExpr > ( getImm (


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformADDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case


<s> unsigned getPointerSize ( ) { if ( is16BitMode ( ) ) return <NUM_LIT> ; if ( is32BitMode ( ) ) return <NUM_LIT> ; if ( is64BitMode ( ) ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , N -> getValueType ( <NUM_LIT> ) ) ; unsigned Opc = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( SN -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( SN , Opc , N -> getValueType ( <NUM_LIT> ) , TFI , getSmallIPtrImm ( Offset , dl ) ) ; return CurDAG -> getMachineNode ( Opc , dl , N -> getValueType (


<s> } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; <STR_LIT> BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != <STR_LIT> && LastOpc == <STR_LIT> ) { int SecondNumOp = SecondLastInst -> getNumOperands ( ) ; TBB = SecondLastInst -> getOperand ( SecondNumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; for ( int i = <NUM_LIT> ; i < SecondNumOp - <NUM_LIT> ; i ++ ) { Cond . push_back ( SecondLastInst -> getOperand ( i ) ) ; } FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( ( SecondLastOpc == <STR_LIT> ) && ( LastOpc == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return true


<s> assert ( ! MI . isBundle ( ) && <STR_LIT> ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT>


<s> getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; setAction ( { G_ICMP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s8 } , { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 , s8 ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 , s64 ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } , { s64 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s64 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; setAction ( { G_MERGE_VALUES , s128 } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , s128 } , Legal ) ; setAction ( { G_MERGE_VALUES , <NUM_LIT> , s128 }


<s> { <STR_LIT> , cygwin_d_handle_target_object_format } , { NULL


<s> static __inline vec_ushort8 spu_sumb ( vec_uchar16 a , vec_uchar16 b ) { return ( ( vec_ushort8 ) ( si_sumb ( ( qword ) (


<s> bool IsPop = isPopOpcode ( MI -> getOpcode ( ) ) ; bool IsPush = isPushOpcode ( MI -> getOpcode ( ) ) ; if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; }


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Size + Imm ; return


<s> for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if ( MRI -> isPhysRegUsed ( reg ) ) return false ; return


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == nullptr && ( Subtarget -> isTargetGlibc ( ) || Subtarget -> isTargetAndroid (

) || Subtarget -> isTargetFuchsia ( ) ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) {


<s> default : break ; case <STR_LIT> : case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) , CmpLHS ; unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; std :: pair < SDNode * , SDNode * > LoHi = selectMULT ( Node , MultOpc , DL , NodeTy , true , true ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . first , <NUM_LIT> ) ) ; if ( ! SDValue ( Node , <NUM_LIT> ) . use_empty ( ) ) ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( LoHi . second , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ?


<s> if ( isTailCall ) { if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else


<s> if ( isVEXTMask ( ShuffleMask , VT , ReverseVEXT , Imm ) ) { if ( ReverseVEXT ) std :: swap ( V1 , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; unsigned WhichResult ; if ( isVTRNMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVUZPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >>


<s> static int ia32_multipass_dfa_lookahead ( void ) { if ( ix86_tune ==


<s> if ( ! BaseT :: isStridedAccess ( Ptr ) ) return NumVectorInstToHideOverhead ; if ( ! BaseT :: getConstantStrideStep ( SE , Ptr ) ) return <NUM_LIT> ; } return BaseT :: getAddressComputationCost ( Ty


<s> if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; IRBuilder < > Builder ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getAlign ( ) ) ; Loaded -> setAtomic (


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false ,


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT>


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = isN64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDiu = isN64 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isN64 ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDiu ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = *


<s> if ( NewMBB == OldMBB ) return ; for ( auto MI = MBB -> instr_begin ( ) , ME = MBB -> instr_end ( ) ; MI != ME && MI -> isPHI ( ) ; ++ MI ) for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( )

+ <NUM_LIT> ; i != e ; i += <NUM_LIT> ) {


<s> return __builtin_mve_vcaddq_rot90_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame . getObjectSize

( FI ) , MFFrame . getObjectAlign ( FI ) ) ;


<s> if ( SDValue BlendOp = lowerVSELECTtoVectorShuffle ( Op , Subtarget , DAG ) ) return BlendOp ; MVT CondVT = Cond . getSimpleValueType ( ) ; unsigned CondEltSize = Cond . getScalarValueSizeInBits ( ) ; if ( CondEltSize == <NUM_LIT> ) return Op ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue Mask = DAG . getSetCC ( dl , MaskVT , Cond , DAG . getConstant ( <NUM_LIT> , dl , CondVT ) , <STR_LIT> ) ; return DAG . getSelect ( dl , VT , Mask , LHS , RHS ) ; } if ( CondEltSize != EltSize ) { if ( CondEltSize != DAG . ComputeNumSignBits ( Cond ) ) return SDValue ( ) ; MVT NewCondSVT = <STR_LIT> ( EltSize ) ; MVT NewCondVT = <STR_LIT> ( NewCondSVT , NumElts ) ; Cond = DAG . getSExtOrTrunc ( Cond , dl , NewCondVT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cond , LHS , RHS ) ; } switch ( VT . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) return Op ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : { MVT CastVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ; Cond = DAG . getBitcast ( CastVT ,


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned EltSize = Op . getScalarValueSizeInBits ( ) ; unsigned Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned EltBits ; if ( <STR_LIT> ( Imm , EltBits


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Reg != <STR_LIT> ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) +


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CallerCC , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return CCInfo . getNextStackOffset ( ) <= FuncInfo -> getBytesInStackArgArea


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) ) { * PredCost = <NUM_LIT> ; } if ( ! ItinData ) return MI . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < <NUM_LIT> ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlign ( )


<s> if ( MRI . getType ( ExtReg ) . getSizeInBits ( ) == <NUM_LIT> ) return ExtReg ; Register NarrowReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto Copy = MIB . buildCopy ( { NarrowReg } , { ExtReg } ) ; selectCopy ( * Copy , TII , MRI , TRI , RBI ) ; return Copy . getReg ( <NUM_LIT>


<s> return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitCOPY_FW ( MI , BB ) ; case <STR_LIT> : return emitCOPY_FD ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FW ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FD ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : return emitFILL_FW ( MI , BB ) ; case <STR_LIT> : return emitFILL_FD ( MI , BB ) ; case <STR_LIT> : return emitFEXP2_W_1 ( MI , BB ) ; case <STR_LIT>


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain ,


<s> void addLOHDirective ( MCLOHType Kind , const MILOHArgs & Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind


<s> if ( CostKind == TTI :: TCK_RecipThroughput && ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) ) { return


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_None : switch ( InstrInfo . get ( MI . getOpcode ( ) ) . TSFlags ) { case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : FixupKind = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCHI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCLO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFHI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFFLO : FixupKind = <STR_LIT>


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) .

addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredWinAlloca ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetMachO ( ) ) ; <ISA_LIT>FrameLowering :: emitStackProbeCall ( * BB -> getParent ( ) , * BB , MI , DL ) ; MI -> eraseFromParent ( ) ; return BB


<s> return __builtin_mve_vrhaddq_sv4si ( __a ,


<s> assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range2 . first = std :: min ( Range2 . first , M ) ; Range2 . second = std :: max ( Range2 . second , M ) ; } } } if ( ! ( <NUM_LIT> <= Range1 . first && Range1 . second < NumEltsPerLane ) || ! ( <NUM_LIT> <= Range2 . first && Range2 . second < NumEltsPerLane ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> && ( Blend1 || Blend2 ) ) return SDValue ( ) ; auto RotateAndPermute = [ & ] ( SDValue Lo , SDValue Hi , int RotAmt , int Ofs ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Rotate = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , DAG . getBitcast ( ByteVT , Hi ) , DAG . getBitcast ( ByteVT , Lo ) , DAG . getConstant ( Scale * RotAmt , DL , <STR_LIT> ) ) ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int Lane = <NUM_LIT> ; Lane != NumElts ; Lane += NumEltsPerLane ) { for ( int Elt = <NUM_LIT> ; Elt != NumEltsPerLane ; ++ Elt ) { int M = Mask [ Lane +


<s> if ( ! Root . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns


<s> case InlineAsm :: Constraint_p : case InlineAsm :: Constraint_ZT : Form = <STR_LIT> ; DispRange = <STR_LIT> ; break ; } if ( selectBDXAddr ( Form , DispRange , Op , Base , Disp , Index ) ) { const TargetRegisterClass * TRC = Subtarget -> getRegisterInfo ( ) -> getPointerRegClass ( * MF ) ; SDLoc DL ( Base ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , DL , <STR_LIT> ) ; if ( Base . getOpcode ( ) != <STR_LIT> && Base . getOpcode ( ) != <STR_LIT> ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , DL , Base . getValueType ( ) , Base , RC ) , <NUM_LIT> ) ; } if ( Index . getOpcode ( ) != <STR_LIT> ) { Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , DL , Index . getValueType ( ) , Index , RC ) , <NUM_LIT> ) ; } OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; OutOps . push_back ( Index ) ; return false ; } return true


<s> case 'c' : if ( TARGET_PREFER_AVX128 ) { if ( ! TARGET_AVX ) str = <STR_LIT> ; else str = <STR_LIT> ; } else if ( ! TARGET_AVX ) str = <STR_LIT> ; break ; case 'd' : if ( TARGET_PREFER_AVX128 ) { if ( ! TARGET_AVX2 ) str = <STR_LIT> ; else str = <STR_LIT> ; } else if ( ! TARGET_AVX2 ) str = <STR_LIT> ; break ; case 'e' : if ( TARGET_PREFER_AVX256 ) { if ( ! TARGET_AVX512F ) str = <STR_LIT> ; else str = <STR_LIT> ; } else if ( ! TARGET_AVX512F ) str = <STR_LIT> ; break ; default : gcc_unreachable (


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_DISPATCHSETUP ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand (

<NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> BuildMI ( MBB , I , DL , get ( TargetOpcode :: COPY ) , FReg ) . addReg ( FalseReg ) ; TrueReg = TReg ; FalseReg = FReg ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . hasMiscellaneousExtensions3 ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addImm ( CCValid )


<s> if ( ! CPEClones . insert ( std :: make_pair ( CPCloneIdx , CPIdx )

) . second ) llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue LowOp = Ops [ Low ] ; SDValue HighOp = Ops [ High ] ; if ( HighOp . getOpcode ( ) == <STR_LIT> ) return Op ; if ( LowOp . getOpcode ( ) == <STR_LIT> ) { int64_t Value = int32_t ( cast < ConstantSDNode > ( LowOp ) -> getZExtValue ( ) ) ; if ( ! isInt < <NUM_LIT> > ( Value ) ) return Op ; } if ( HighOp . getOpcode ( ) == <STR_LIT> && HighOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * MaskNode = cast < ConstantSDNode > ( HighOp . getOperand ( <NUM_LIT> ) ) ; uint64_t Mask = MaskNode -> getZExtValue ( ) | Masks [ High ] ; if ( ( Mask >> <NUM_LIT> ) == <NUM_LIT> ) HighOp = HighOp . getOperand ( <NUM_LIT> ) ; } SDLoc DL ( Op ) ; SDValue Low32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LowOp ) ; SDValue SubReg32 = DAG . getTargetConstant ( <STR_LIT> , <STR_LIT>


<s> static inline int extract_22 ( unsigned word ) { return sign_extend ( GET_FIELD ( word , <NUM_LIT> , <NUM_LIT> ) | GET_FIELD ( word , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( word , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT>

| GET_FIELD ( word , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | ( word & <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( getTheThumbLETarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( getTheThumbBETarget


<s> SymGOTMap & getSymGOTPLTMap ( ) { return m_SymGOTPLTMap


<s> static void rename_fma_node ( fma_forest * forest , fma_node * node ) { node -> rename ( forest


<s> if ( unsorted_regs [ i ] < <NUM_LIT> || ( TARGET_THUMB1 && unsorted_regs [ i ] > LAST_LO_REGNUM ) || unsorted_regs [ i ] > <NUM_LIT> || ( i != nops - <NUM_LIT> && unsorted_regs [ i ] == base_reg ) ) return <NUM_LIT> ; if ( unsorted_regs [ i ] == SP_REGNUM && base_reg != SP_REGNUM ) return <NUM_LIT> ; unsorted_offsets [ i ] = INTVAL ( offset ) ; if ( i == <NUM_LIT> || unsorted_offsets [ i ] < unsorted_offsets [ order [ <NUM_LIT> ] ] ) order [ <NUM_LIT> ] = i ; } else return <NUM_LIT> ; } if ( ! compute_offset_order ( nops , unsorted_offsets , order , check_regs ? unsorted_regs : NULL ) ) return <NUM_LIT> ; if ( saved_order ) memcpy ( saved_order , order , sizeof order ) ; if ( base ) { * base = base_reg ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) regs [ i ] = unsorted_regs [ check_regs ? order [ i ] : i ] ; * load_offset = unsorted_offsets [ order [ <NUM_LIT> ] ] ; } if ( TARGET_THUMB1 && ! peep2_reg_dead_p ( nops , base_reg_rtx ) ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_32BIT && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == - <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( const_ok_for_arm ( unsorted_offsets [ order [ <NUM_LIT> ] ] ) || const_ok_for_arm ( - unsorted_offsets [ order [ <NUM_LIT> ] ] ) ) ldm_case = <NUM_LIT> ; else return <NUM_LIT> ; if ( ! multiple_operation_profitable_p ( false , nops , ldm_case == <NUM_LIT> ? unsorted_offsets [ order [

<NUM_LIT> ] ] : <NUM_LIT> ) ) return <NUM_LIT> ;