<s> mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) )


<s> static bool needsPrologueENDBR ( MachineFunction & MF , const Module * M ) { Function & F = MF . getFunction ( ) ; if ( F . doesNoCfCheck ( ) ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; unsigned ArgNo = <NUM_LIT> ; for ( auto & Arg : Args ) { EVT VT = TLI . getValueType ( DL , Arg . Ty ) ; MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; unsigned NumRegs = TLI . getNumRegistersForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; BuildVectorSDNode * C = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) || EltTy . getSizeInBits ( ) < SplatBitSize ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned Lg2 = SplatValue . countTrailingZeros ( ) ; SmallVector < SDValue , <NUM_LIT> > Sz ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , EltTy ) ) ; SDValue SGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getNode ( <STR_LIT> , dl , VT , & Sz [ <NUM_LIT> ] , NumElts ) ) ; SmallVector < SDValue , <NUM_LIT> > Amt ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - Lg2 , EltTy ) ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , dl , VT , SGN , DAG . getNode ( <STR_LIT> , dl , VT , & Amt [ <NUM_LIT> ] , NumElts ) ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SmallVector < SDValue , <NUM_LIT> > Lg2Amt ( NumElts , DAG . getConstant ( Lg2 , EltTy ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , dl , VT , ADD , DAG . getNode ( <STR_LIT> , dl , VT , & Lg2Amt [ <NUM_LIT> ] , NumElts ) ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ; SmallVector < SDValue , <NUM_LIT> > V ( NumElts , DAG . getConstant ( <NUM_LIT> , EltTy ) ) ; SDValue Zero = DAG . getNode ( <STR_LIT> , dl , VT , & V [ <NUM_LIT> ] , NumElts ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Zero , SRA ) ; } return SDValue


<s> SDLoc dl ( V . getNode ( ) ) ; SDValue VLo = DAG . getAnyExtOrTrunc ( V , dl , <STR_LIT> ) ; SDValue VHi = DAG . getAnyExtOrTrunc ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , dl , <STR_LIT> ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; if ( isBigEndian ) std :: swap ( VLo , VHi ) ; SDValue RegClass = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT> ,


<s> if ( CONTROL_REGNO_P ( regno ) ) return CONTROL_REGS ; if ( CR_REGNO_P ( regno ) ) { int i , j ; for ( i = USER0_REGS ; i <= USER3_REGS ; ++ i ) { if ( ! TEST_HARD_REG_BIT ( reg_class_contents [ i ] , regno ) ) continue ; for ( j = <NUM_LIT> ; j < N_REG_CLASSES ; ++ j ) { enum reg_class sub = reg_class_subclasses [ i ] [ j ] ; if ( sub == LIM_REG_CLASSES ) return i ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ sub ] ,


<s> EVT VT0 = Op0 . getValueType ( ) ; EVT VT1 = Op1 . getValueType ( ) ; if ( VT0 != VT1 || ! VT0 . isSimple ( ) || ! VT0 . isInteger ( ) ) return SDValue ( ) ; APInt SplatVal ; if ( ! <STR_LIT> ( Op1 . getNode ( ) , SplatVal ) || ! SplatVal . isMask ( ) ) return SDValue ( ) ; if ( isBitwiseNot ( Op0 ) ) return SDValue ( ) ; if ( ! SupportedVectorShiftWithImm ( VT0 . getSimpleVT ( ) , Subtarget , <STR_LIT> ) ) return SDValue ( ) ; unsigned EltBitWidth = VT0 . getScalarSizeInBits ( ) ; if ( EltBitWidth != DAG . ComputeNumSignBits ( Op0 ) ) return SDValue ( ) ; SDLoc DL ( N


<s> for ( const auto & BB : L -> blocks ( ) ) for ( auto & J : * BB ) { Value * PtrValue = nullptr ; Type * PointerElementType = nullptr ; PtrValue = getPointerOperandAndType ( & J , & PointerElementType ) ; if ( ! PtrValue ) continue ; if ( PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE -> getSCEVAtScope ( PtrValue , L ) ; const SCEVAddRecExpr * LARSCEV = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ; if ( ! LARSCEV || LARSCEV -> getLoop ( ) !=


<s> for ( const SMLoc & Loc : FnStartLocs ) Parser . Note


<s> rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op1 , op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = op0 ; if ( ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return


<s> static DecodeStatus DecodeCCRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateReg ( RegNo )


<s> return __builtin_mve_vrev32q_sv16qi (


<s> if ( is_ms_hook ) { int i , filler_count = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; unsigned int filler_cc = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < filler_count ; i += <NUM_LIT> ) fprintf ( out_file , ASM_LONG <STR_LIT> , filler_cc ) ; } SUBTARGET_ASM_UNWIND_INIT ( out_file ) ; ASM_OUTPUT_LABEL ( out_file , fname ) ; if ( is_ms_hook ) { if ( TARGET_64BIT ) { fputs ( ASM_BYTE <STR_LIT>


<s> static bool CC_<ISA_LIT>NoMoreRegs ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { for ( unsigned i = <NUM_LIT> ; i < NumArgRegs ; ++ i ) State . AllocateReg ( <ISA_LIT>ArgRegs [ i ] ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isScalableVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128Call ( Op , DAG ,


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; <ISA_LIT>IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; if ( F . isVarArg ( ) ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetVarArgRegs ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; int VaArgOffset ; unsigned RegSize = <NUM_LIT> ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( CCInfo . getCallingConv ( ) ) - ( int ) ( RegSize * ( ArgRegs . size ( ) - Idx ) ) ; } MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( RegSize , VaArgOffset , true ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I


<s> <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Flags ; Flags = checkBoolTestSetCCCombine ( EFLAGS , CC


<s> if ( isa < ScalableVectorType > ( ValTy ) ) return getArithmeticReductionCostSVE ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; if ( IsPairwiseForm ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry CostTblNoPairwise [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( CostTblNoPairwise , ISD ,

MTy ) ) return LT . first * Entry -> Cost ;


<s> static MachineOperand & getDispOperand ( MachineInstr * MI ) { int AddrOffset = getAddrOffset ( MI ) ; return MI -> getOperand ( AddrOffset + <STR_LIT>


<s> continue ; } assert ( SrcVT . getSizeInBits ( ) == <NUM_LIT> * VT . getSizeInBits ( ) ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; unsigned Imm = Src . MinElt * getExtFactor ( VEXTSrc1 ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy ) continue ; assert ( ShuffleVT . getVectorElementType ( ) == SmallestEltTy ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , ShuffleVT , Src . ShuffleVec ) ; Src . WindowScale = SrcEltTy . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; Src . WindowBase *= Src . WindowScale ; } DEBUG ( for ( auto Src : Sources ) assert ( Src . ShuffleVec . getValueType ( ) == ShuffleVT ) ; ) ; SmallVector < int , <NUM_LIT> > Mask ( ShuffleVT . getVectorNumElements ( ) , - <NUM_LIT> ) ; int BitsPerShuffleLane = ShuffleVT . getVectorElementType ( ) . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) == <STR_LIT> ) continue ; auto Src = std :: find ( Sources . begin ( ) , Sources . end ( ) , Entry . getOperand ( <NUM_LIT> ) ) ; int EltNo = cast < ConstantSDNode > ( Entry . getOperand ( <NUM_LIT>


<s> void <ISA_LIT>MCCodeEmitter :: EmitByte ( unsigned char C , raw_ostream & OS ) const { OS << ( char )


<s> int tr0_used ; if ( ! current_function_is_leaf ) return - <NUM_LIT> ; tr0_used = flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_used_regs [ regno ] && ! regs_ever_live [


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE


<s> return ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) || reg_no >= FIRST_PSEUDO_REGISTER ; } else if ( ( ( code == POST_MODIFY || code == PRE_MODIFY ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && XEXP ( op , <NUM_LIT> ) == XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) && REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) || ( reload_completed && code == PLUS && REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ) { reg_no = REGNO ( XEXP ( op , <NUM_LIT> ) ) ; if ( code == PLUS ) val = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; else val = INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; switch ( mode ) { case


<s> unsigned HOST_WIDE_INT mask = INTVAL ( operands [ <NUM_LIT> ] ) ; int bs0 , bs1 , p , len ; if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; for ( bs0 = <NUM_LIT> ; bs0 < <NUM_LIT> ; bs0 ++ ) if ( ( mask & ( <NUM_LIT> << bs0 ) ) != <NUM_LIT> ) break ; for ( bs1 = bs0 ; bs1 < <NUM_LIT> ; bs1 ++ ) if ( ( mask & ( <NUM_LIT>


<s> return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I , * CoverageInfo ) ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; switch ( I . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_STORE : case TargetOpcode :: G_LOAD : return selectLoadStoreOp ( I , MRI , MF ) ; case TargetOpcode :: G_PTR_ADD : case TargetOpcode :: G_FRAME_INDEX : return selectFrameIndexOrGep ( I , MRI , MF ) ; case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_CONCAT_VECTORS : return selectMergeValues ( I , MRI , MF ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode ::


<s> return ( __m128 ) __builtin_ia32_loadhps ( ( __v4sf ) __A , ( __v2si *


<s> static void arm_init_fp16_builtins ( void ) { tree fp16_type = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( fp16_type ) = <NUM_LIT> ; layout_type ( fp16_type )


<s> return ( __m128 ) __builtin_ia32_cmpleps ( ( __v4sf )


<s> static DecodeStatus DecodeVecShiftR64Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler


<s> if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( )


<s> Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; UpdateValueMap ( I , ResultReg


<s> bool <ISA_LIT>ConstantIslands :: isLongFormOffsetInRange ( unsigned UserOffset , unsigned TrialOffset , const CPUser & U ) { return isOffsetInRange ( UserOffset , TrialOffset , U .


<s> unsigned <ISA_LIT>CodeEmitter :: getTLSRegEncoding ( const MachineInstr &


<s> static MCInst lowerRILow ( const MachineInstr * MI , unsigned Opcode ) { if ( MI -> isCompare ( ) ) return MCInstBuilder ( Opcode ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( )

) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; auto * SrcTy = toVectorTy (


<s> int32_t OffImm = ( int32_t ) MO1 . getImm ( ) / <NUM_LIT> ; if ( OffImm != <NUM_LIT> ) { O << <STR_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm


<s> rtx mmix_get_hard_reg_initial_val ( enum machine_mode mode , int regno ) { return get_hard_reg_initial_val ( mode ,


<s> unsigned int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = i ; return ( x . q


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isFPCmp = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; if ( isFPCmp ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Opc = FPBranchCodeToOpc ( GetFPBranchCodeFromCond ( CC ) ) ; BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; } else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator i = BB -> succ_begin ( ) , e = BB -> succ_end ( ) ; i != e ; ++ i ) { EM -> insert ( std :: make_pair ( * i , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * i ) ; } while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB


<s> add_reg_note ( insn , REG_CFA_ADJUST_CFA , t ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; for ( unsigned int i = low ; i <= high ; i ++ ) add_reg_note

( insn , REG_CFA_RESTORE , gen_rtx_REG ( word_mode , i ) ) ;


<s> unsigned getCallSymbolOpValue ( const MCInst & MI , unsigned Idx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Idx ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO


<s> inline unsigned getSORegOffset ( unsigned Op ) { return Op >> <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter


<s> if ( ! NeedsDwarfAsyncUnwindInfo . hasValue ( ) ) NeedsDwarfAsyncUnwindInfo = needsDwarfUnwindInfo ( ) && MF . getFunction ( ) .

getUWTableKind ( ) == UWTableKind :: Async ;


<s> if ( count_op != count_ideal ) return false ; for ( i = <NUM_LIT> ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , <NUM_LIT> , i ) ; rtx elt_ideal = XVECEXP ( ideal , <NUM_LIT> , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal


<s> SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back (


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) ) return ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlign ( ) >= Align ( <NUM_LIT> ) ) return ; if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! SavedRegs . test ( <STR_LIT> + NumSpills


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> if ( INTVAL ( cookie ) & CALL_LONG && SYMBOL_REF_P ( func_desc ) ) { gcc_assert ( rs6000_pcrel_p ( ) ) ; func_desc = rs6000_longcall_ref ( func_desc , tlsarg ) ; } else gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; if ( GET_CODE ( func_desc ) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2 ) { r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , r12 ) ; } call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( <NUM_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> ; i < numArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i + <NUM_LIT> ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } BuildMI ( * BB , MI , dl , TII -> get ( Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg


<s> unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo ) . getImm ( ) ; return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == TargetOpcode :: STACKMAP || MI -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || ( isInt < <NUM_LIT> > ( Offset ) && ( Offset % offsetMinAlign ( *


<s> return ( poly64x2_t ) __builtin_neon_vbslv2di ( ( int64x2_t ) __a ,


<s> return ( Kind == k_Register && Reg . Kind == RegKind :: SVEDataVector ) && <ISA_LIT>MCRegisterClasses [ Class ] . contains (


<s> if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; unsigned Src1Reg = getRegForValue ( SI -> getTrueValue


<s> decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_FABSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_FABSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_COPYSIGNQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_COPYSIGNQ ] =


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind


<s> SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty ,

Hi ) , DAG . getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> const MCOperand & RegOp = MI -> getOperand ( OpNo ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( OffsetOp . isImm ( ) ) { O << OffsetOp . getImm ( ) ; } else { assert ( OffsetOp . isExpr ( ) && <STR_LIT> ) ; printExpr ( OffsetOp . getExpr ( ) , O , MAI ) ; } assert ( RegOp . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( RegOp . getReg


<s> default : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } DebugLoc


<s> void addImm0_65535Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE


<s> return __builtin_neon_vrndmv8hf ( __a )


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>_MC :: <ISA_LIT>MCInstrAnalysis (


<s> ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ; isKill = true ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return


<s> SDValue RetAddrFI = getReturnAddrFrameIndex ( DAG ) ; FuncInfo -> setLRStoreRequired ( ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , RetAddrFI , NULL ,

<NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> int64_t Offset = Op . getImm ( ) * <NUM_LIT> ; if ( PrintBranchImmAsAddress ) O << formatHex ( Address + Offset ) ; else O << <STR_LIT> << formatImm ( Offset ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t TargetAddress ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( TargetAddress ) ) { O << formatHex ( TargetAddress ) ; } else { MI -> getOperand ( OpNum ) . getExpr ( ) ->


<s> return MIB . addReg ( Reg1 , false , false , isKill1 ) . addImm ( <NUM_LIT> ) . addReg ( Reg2 , false

, false , isKill2 ) . addImm ( <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printSystemPStateField ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; if ( Valid ) O << StringRef ( Name . str ( ) ) . upper ( ) ; else O << <STR_LIT> <<


<s> if ( vec_flags & VEC_ANY_SVE ) sve_costs = aarch64_tune_params . vec_costs -> sve ; if ( sve_costs ) { unsigned int latency = aarch64_sve_in_loop_reduction_latency ( vinfo , stmt_info , vectype , sve_costs ) ; if ( latency ) return latency ; } if ( vec_flags == <NUM_LIT> ) { if ( FLOAT_TYPE_P ( vectype ) ) return vec_costs -> scalar_fp_stmt_cost ; return vec_costs ->


<s> static const int INSTR_DISTANCE_THRESHOLD = <NUM_LIT> ; CurInst = I ; bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I != CurInst ) { if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD ) break ; if ( usesRegister ( p , CurInst ) == RU_Write ) { return CurInst ; } InstrDistance += TII -> getInstrLatency ( TM

-> getInstrItineraryData ( ) , CurInst ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = <NUM_LIT> * <NUM_LIT> ; MFI -> setStackSize (


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT>


<s> Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return


<s> if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; break ; case


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregciv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregciv4si ( __o


<s> inline SDValue getI32Imm ( unsigned Imm


<s> void <ISA_LIT>TargetLowering :: computeMaskedBitsForTargetNode ( const SDValue Op , const APInt & Mask , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( Mask . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT>


<s> const <ISA_LIT>Subtarget & SubTarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I


<s> bool enableEarlyIfConversion ( ) const override { return hasISEL (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getParser ( ) . Lex ( ) ; unsigned NewReg = RegOpnd . getGPR32Reg ( ) ; if ( IsPicEnabled ) GPReg = NewReg ; getTargetStreamer ( ) . emitDirectiveCpLocal ( NewReg ) ; return false


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ; setIndexedStoreAction ( im , VT . getSimpleVT ( ) , Legal


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ; bool isAdd = <STR_LIT> (


<s> bool isTargetWindows ( ) const { return TargetTriple . getOS ( ) == Triple ::


<s> Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT ANDVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , ANDVT , DAG . getNode ( <STR_LIT> , dl , ANDVT , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , ANDVT , Mask ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT>


<s> return MachinePointerInfo ( MF . getPSVManager ( )


<s> assert ( std :: is_sorted ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) ) && std :: is_sorted ( std :: begin ( IntrinsicsWithChain ) , std :: end ( IntrinsicsWithChain ) ) && <STR_LIT> ) ; assert ( ( std :: adjacent_find ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) ) == std :: end ( IntrinsicsWithoutChain ) ) && ( std :: adjacent_find ( std :: begin ( IntrinsicsWithChain ) , std ::

end ( IntrinsicsWithChain ) ) == std :: end ( IntrinsicsWithChain ) ) && <STR_LIT> ) ;


<s> PHINode * PhiInst = dyn_cast < PHINode > ( * Use ) ; Instruction * InsertionPoint ; if ( PhiInst ) InsertionPoint = PhiInst -> getIncomingBlock ( Use . getOperandNo ( ) )


<s> void setSRetReturnReg ( unsigned Reg


<s> int32_t i [ <NUM_LIT> ] ; } u ; u . v = a ; return u . i [ pos


<s> assert ( ( Value == <NUM_LIT> || Value == <NUM_LIT> ) && <STR_LIT> ) ; return


<s> static DecodeStatus decodeBDXAddr64Disp20Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CmpInst :: FCMP_FALSE : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: FCMP_OEQ : Predicate = CmpInst :: FCMP_ORD ; break ; case CmpInst :: FCMP_OGT : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: FCMP_OGE : Predicate = CmpInst :: FCMP_ORD ; break ; case CmpInst :: FCMP_OLT : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: FCMP_OLE : Predicate = CmpInst :: FCMP_ORD ; break ; case CmpInst :: FCMP_ONE : Predicate = CmpInst :: FCMP_FALSE ; break ; case CmpInst :: FCMP_ORD : Predicate = CmpInst :: FCMP_ORD ; break ; case CmpInst :: FCMP_UNO : Predicate = CmpInst ::


<s> return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , SubVec , ZeroIdx ) ; if ( Vec . isUndef ( ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( <STR_LIT> ( Vec . getNode ( ) ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; if ( ShiftRight != <NUM_LIT> ) SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( ShiftRight , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( IdxVal + SubVecNumElems == NumElems ) { SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( SubVecNumElems * <NUM_LIT> == NumElems ) { Vec = DAG . getNode ( <STR_LIT> , dl , SubVecVT , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , Vec , ZeroIdx ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems - IdxVal , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; } Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , SubVec ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } NumElems = WideOpVT . getVectorNumElements ( ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef ,


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2sidi ( ( int64x1_t )


<s> if ( getParser ( ) . ParseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , <NUM_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma )


<s> SDValue Arg = ShAmtOp . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; if ( Arg != BaseShAmt ) { return SDValue ( ) ; } } } else if ( ShAmtOp . getOpcode ( ) == <STR_LIT> && isSplatMask ( ShAmtOp . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; SDValue ValOp = N -> getOperand ( <NUM_LIT> ) ; switch ( N -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; break ; case <STR_LIT>


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>Target

, mcld :: create<ISA_LIT>DiagLineInfo ) ;


<s> static int matchShuffleAsByteRotate ( MVT VT , SDValue & V1 , SDValue & V2 , ArrayRef < int > Mask ) { if ( any_of ( Mask , [ ] ( int M ) { return M == SM_SentinelZero ; } ) ) return - <NUM_LIT> ; SmallVector < int ,


<s> auto StatusOrErr = RealVal . convertFromString ( Desc -> Repr , APFloat :: rmTowardZero ) ; if ( ! StatusOrErr || * StatusOrErr != APFloat ::


<s> unsigned NumHalfElts = NumElts / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumHalfElts ; ++ l ) ShuffleMask . push_back ( l + NumHalfElts ) ; for ( unsigned h = <NUM_LIT> ; h != NumHalfElts ; ++ h ) ShuffleMask . push_back


<s> const MCOperand & BaseReg = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg .


<s> static EVT getPackedVectorTypeFromPredicateType ( LLVMContext & Ctx , EVT PredVT ) { if ( ! PredVT . isScalableVector ( ) || PredVT . getVectorElementType (


<s> static reg_class_t arm_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t rclass ) { if ( TARGET_32BIT ) return


<s> aarch64_general_init_builtins ( ) ; <STR_LIT> (


<s> unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> ,


<s> b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT


<s> static DecodeStatus DecodeStoreFP ( MCInst & Inst , unsigned insn , uint64_t

Address , const MCDisassembler * Decoder ) {


<s> SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , <NUM_LIT> ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end (


<s> vpminnmqd_f64 ( float64x2_t a ) { return __builtin_aarch64_reduc_smin_scal_v2df ( a


<s> MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineLoopInfo >


<s> if ( ConstExpr ) { int64_t Value = ConstExpr -> getValue ( ) ; return ( ( Value & ~ <NUM_LIT> ) == <NUM_LIT> ) ; } return


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveNaN2008 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_NAN2008 ; MCA . setELFHeaderEFlags (


<s> static bool classof ( const <ISA_LIT>MCExpr


<s> } if ( ! HasVCTP || MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; ( void ) MIBuilder ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ) ; DeadInstructions . push_back ( & MI ) ; } for ( MachineInstr * DeadInstruction : DeadInstructions )

DeadInstruction -> eraseFromParent ( ) ;


<s> emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; use_sibcall_p = ( mips_function_ok_for_sibcall ( function , NULL ) && const_call_insn_operand ( fnaddr , Pmode ) ) ; if ( ! use_sibcall_p && ( mips_got_symbol_type_p ( mips_classify_symbol ( fnaddr , SYMBOL_CONTEXT_LEA ) ) ) ) { cfun -> machine -> global_pointer = TARGET_CALL_SAVED_GP ? <NUM_LIT> : GLOBAL_POINTER_REGNUM ; cfun -> machine -> must_initialize_gp_p = true ; SET_REGNO ( pic_offset_table_rtx , cfun -> machine -> global_pointer ) ; mips_emit_loadgp ( ) ; } temp1 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; temp2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { mips_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = mips_add_offset ( temp2 , temp1 , vcall_offset ) ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } if ( use_sibcall_p ) { insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { if ( TARGET_USE_PIC_FN_ADDR_REG && ! TARGET_MIPS16 && ! mips_dangerous_for_la25_p ( fnaddr ) ) temp1 = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; mips_load_call_address ( MIPS_CALL_SIBCALL , temp1 , fnaddr ) ; if ( TARGET_USE_PIC_FN_ADDR_REG && REGNO ( temp1 ) != PIC_FUNCTION_ADDR_REGNUM ) mips_emit_move ( gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) , temp1 ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } insn = get_insns ( ) ; split_all_insns_noflow ( ) ; mips16_lay_out_constants ( true ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT>


<s> if ( pFormat . hasGOTPLT ( ) ) applyOne ( llvm :: ELF :: DT_PLTGOT , pFormat . getGOTPLT ( )


<s> auto BII = BB . getFirstInstrTerminator ( ) ; if ( BB . succ_size ( ) == <NUM_LIT> && BII != BB . instr_end ( ) && ( * BII ) . getOpcode ( ) == <STR_LIT> && ( * BII ) . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned CndReg = ( * BII ) . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( CndReg ) || ! MRI -> hasOneNonDBGUse ( CndReg ) ) return false ; MachineInstr * CMPI = MRI -> getVRegDef ( CndReg ) ; for ( MachineOperand & MO : CMPI -> operands ( ) ) if ( MO . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return false ; return true ; } return false ; } ; auto isEligibleForMoveCmp = [ ] ( MachineBasicBlock & BB ) { return BB . succ_size ( ) == <NUM_LIT> ; } ; if ( ! isEligibleBB ( MBB ) ) return false ; unsigned NumPredBBs = MBB . pred_size ( ) ; if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock * TmpMBB = * MBB . pred_begin ( ) ; if ( isEligibleBB ( * TmpMBB ) ) { PredMBB = TmpMBB ; MBBtoMoveCmp = nullptr ; return true ; } } else if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock :: pred_iterator PI = MBB . pred_begin ( ) ; MachineBasicBlock * Pred1MBB = * PI ; MachineBasicBlock * Pred2MBB = * ( PI + <NUM_LIT> ) ; if ( isEligibleBB ( * Pred1MBB ) && isEligibleForMoveCmp ( * Pred2MBB ) ) { } else if ( isEligibleBB ( * Pred2MBB ) && isEligibleForMoveCmp ( * Pred1MBB ) ) { std :: swap ( Pred1MBB , Pred2MBB ) ; } else return false ; MachineInstr * BI = & * MBB . getFirstInstrTerminator ( ) ; MachineInstr * CMPI = MRI -> getVRegDef ( BI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( int I = <NUM_LIT> ; I <= <NUM_LIT> ; I ++ ) if ( CMPI -> getOperand ( I ) . isReg ( ) ) { MachineInstr * Inst = MRI -> getVRegDef ( CMPI -> getOperand ( I ) . getReg ( ) ) ; if ( Inst -> getParent ( ) == & MBB && Inst -> getOpcode


<s> X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Y ) ; Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X , Y ) ; X = DAG . getNode ( <STR_LIT> , dl ,


<s> if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return <NUM_LIT> ; if ( mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return <NUM_LIT> ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return ( ( TARGET_SHMEDIA ? <NUM_LIT> : TARGET_FMOVD ? <NUM_LIT> : <NUM_LIT> ) * ( ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ) ; if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return <NUM_LIT> ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS


<s> auto Zero = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Zero || Zero -> Value . getSExtValue ( ) != <NUM_LIT> ) return false ; if ( ! MinSize ) { if ( auto Size = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) { if ( Size -> Value . getSExtValue ( ) <= <NUM_LIT> ) return false ; } } MIRBuilder . setInstrAndDebugLoc ( MI


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( (


<s> if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask


<s> PLTEntryBase * plt_entry = pParent . getSymPLTMap ( ) . lookUp ( pSym ) ; assert ( plt_entry != NULL


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; initialize ( MF ) ; if ( ! collectISELInstructions ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DumpISELInstructions ( ) ; expandAndMergeISELs (


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned Ws1 = RegInfo . createVirtualRegister ( RC ) ; unsigned Ws2 = RegInfo . createVirtualRegister ( RC ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT>


<s> } label = gen_label_rtx ( ) ; emit_label_after ( label , after ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( GET_CODE ( XEXP ( XEXP ( set , <NUM_LIT> ) , i ) ) == LABEL_REF ) { rtx ref = XEXP ( XEXP ( set , <NUM_LIT> ) , i ) ; if ( LABEL_NUSES ( XEXP ( ref , <NUM_LIT> ) ) == <NUM_LIT> ) delete_insn ( XEXP ( ref , <NUM_LIT> ) ) ; XEXP ( ref , <NUM_LIT> ) = label ; LABEL_NUSES ( label ) ++ ; JUMP_LABEL ( insn ) = label ; } INSN_CODE ( insn ) =


<s> if ( ! flags ) { fprintf ( stderr , DEBUG_FMT_S , string , <STR_LIT> ) ; return ; } start_column += fprintf ( stderr , DEBUG_FMT_WX , string , flags ) ; cur_column = start_column ; for ( i = <NUM_LIT> ; i < num_elements ; i ++ ) { bool invert = opts [ i ] . invert ; const char * name = opts [ i ] . name ; const char * no_str = <STR_LIT> ; HOST_WIDE_INT mask = opts [ i ] . mask ; size_t len = comma_len + prefix_len + strlen ( name ) ; if ( ! invert ) { if ( ( flags & mask ) == <NUM_LIT> ) { no_str = <STR_LIT> ; len += strlen ( <STR_LIT> ) ; } flags &= ~ mask ; } else { if ( ( flags & mask ) != <NUM_LIT> ) { no_str = <STR_LIT> ; len += strlen ( <STR_LIT> ) ; } flags |= mask ; } cur_column += len ; if ( cur_column > max_column ) { fprintf ( stderr , <STR_LIT> , ( int ) start_column , <STR_LIT> ) ; cur_column = start_column + len ; comma = <STR_LIT> ; } fprintf ( file , <STR_LIT> , comma , prefix , no_str , name ) ; comma = <STR_LIT> ; comma_len = strlen


<s> for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr . getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx ) { MachineOperand & MO = Instr . getOperand ( OpIdx ) ; const TargetRegisterClass * OpRegCstraints = Instr . getRegClassConstraint ( OpIdx , TII , TRI ) ; if ( ! OpRegCstraints ) continue ; if ( MO . isFI ( ) ) continue ; assert ( MO . isReg ( ) && <STR_LIT> ) ; Register Reg = MO . getReg ( ) ; if ( Register :: isPhysicalRegister (


<s> Builder . SetInsertPoint ( & II ) ; Align Alignment = BasePtr -> getPointerAlignment ( II . getModule ( ) -> getDataLayout ( ) ) ; Value * Ptr = Builder . CreateGEP ( cast < VectorType > ( Ty ) -> getElementType ( ) , BasePtr , IndexBase ) ; Type * VecPtrTy = PointerType :: getUnqual ( Ty ) ; Ptr = Builder . CreateBitCast ( Ptr , VecPtrTy ) ; ( void ) Builder . CreateMaskedStore ( Val , Ptr , Alignment


<s> std :: string getNextCallSiteMagicPrivate ( ) { sgx_callsite_magic_index_private


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex


<s> bool isMem128 ( ) const { return Kind == Memory && ( ! Mem . Size ||


<s> if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { UpdateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; } unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , InputReg , true , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg


<s> Value * <ISA_LIT>IREmitter :: visitXTEST ( const SDNode * N


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup , Value , IsPCRel , nullptr ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i :


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return CE -> getValue


<s> struct unw_reg_info * r ; if ( ! desc_is_active ( qp , t , sr ) ) return ; if ( x ) where = UNW_WHERE_BR ; else if ( ytreg & <NUM_LIT> ) where = UNW_WHERE_FR ; r = sr -> curr . reg + decode_abreg


<s> Opc = isSub ? <STR_LIT> : <STR_LIT> ; assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( DstNotEqBase ) { if ( is<ISA_LIT>LowRegister ( DestReg ) && is<ISA_LIT>LowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; const MCInstrDesc & MCID = TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , MCID , DestReg ) . setMIFlags ( MIFlags ) ) ; AddDefaultPred ( MIB . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ) . setMIFlags ( MIFlags ) ; } BaseReg = DestReg ; } unsigned Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; while ( Bytes ) { unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; ThisVal /= Scale ; if ( isTwoAddr ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( NeedCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( DestReg ) . addImm ( ThisVal ) ; MIB = AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MIFlags ) ; } else { bool isKill = BaseReg != <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( NeedCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( BaseReg , getKillRegState ( isKill ) ) . addImm


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitMonitor ( MachineInstr * MI , MachineBasicBlock * BB ) const { DebugLoc dl = MI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned MemOpc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI -> eraseFromParent


<s> static SDValue detectAVX512SSatPattern ( SDValue In , EVT VT , const <ISA_LIT>Subtarget & Subtarget , const TargetLowering & TLI ) { if ( ! TLI . isTypeLegal ( In . getValueType ( ) ) ) return SDValue ( ) ; if ( ! isSATValidOnAVX512Subtarget ( In . getValueType ( ) , VT , Subtarget ) ) return SDValue ( ) ; return detectSSatPattern ( In


<s> bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> while ( state -> insns_left == <NUM_LIT> || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state , insn ) >=

<NUM_LIT> ) ) mips_sim_next_cycle ( state ) ;


<s> Parser . Lex ( ) ; SMLoc IdxRegLoc = Tok . getLoc ( ) ; if ( ParseRegister ( IndexReg , IdxRegLoc , End ) ) return ErrorOperand ( IdxRegLoc , <STR_LIT> ) ; Scale = Val ; } else if ( getLexer ( ) . is ( AsmToken :: RBrac ) ) { const MCExpr * ValExpr = MCConstantExpr :: Create ( Val , getContext ( ) ) ; Disp = isPlus ? ValExpr : MCConstantExpr :: Create ( <NUM_LIT> - Val , getContext ( ) ) ; } else return ErrorOperand ( PlusLoc , <STR_LIT> ) ; } else if ( getLexer ( ) . is ( AsmToken :: Identifier ) ) { End = Tok . getLoc ( ) ; if ( ! IndexReg ) ParseRegister ( IndexReg , Start , End ) ; else if ( getParser ( ) . ParseExpression ( Disp , End ) ) return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: RBrac ) ) { ExpectRBrac = false ; Parser . Lex ( ) ; End = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { ExpectRBrac = true ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( Disp , End ) ) return <NUM_LIT> ; } } else if ( ExpectRBrac ) { if ( getParser ( ) . ParseExpression ( Disp , End ) ) return <NUM_LIT> ; } if ( ExpectRBrac ) { if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return ErrorOperand ( End , <STR_LIT> ) ; Parser . Lex ( ) ; End = Tok . getLoc ( ) ; } if ( Tok . getString ( ) . startswith ( <STR_LIT> ) ) { SmallString < <NUM_LIT> > Err ; const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , & NewDisp , Err ) ) return ErrorOperand ( Tok . getLoc ( ) , Err ) ; Parser . Lex


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS

, Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( llvm :: make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> case ELF :: R_MIPS_PC21_S2 : case ELF :: R_MIPS_PC26_S2 : case ELF :: R_MIPS_PC18_S3 : case ELF :: R_MIPS_PC19_S2 : case ELF :: R_MIPS_PCHI16 : case ELF :: R_MIPS_PCLO16 : case ELF :: R_MIPS_COPY : case ELF :: R_MIPS_JUMP_SLOT : case ELF :: R_MIPS_NUM : case ELF :: R_MIPS_PC32 : case ELF :: R_MIPS_EH : case ELF :: R_MICROMIPS_26_S1 : case ELF :: R_MICROMIPS_GPREL16 : case ELF :: R_MICROMIPS_LITERAL : case ELF :: R_MICROMIPS_PC7_S1 : case ELF :: R_MICROMIPS_PC10_S1 : case ELF :: R_MICROMIPS_PC16_S1 : case ELF :: R_MICROMIPS_CALL16 : case ELF :: R_MICROMIPS_GOT_DISP : case ELF :: R_MICROMIPS_GOT_HI16 : case ELF :: R_MICROMIPS_GOT_LO16 : case ELF :: R_MICROMIPS_SUB : case ELF :: R_MICROMIPS_HIGHER : case ELF :: R_MICROMIPS_HIGHEST : case ELF :: R_MICROMIPS_CALL_HI16 : case ELF :: R_MICROMIPS_CALL_LO16 : case ELF :: R_MICROMIPS_SCN_DISP : case ELF :: R_MICROMIPS_JALR : case ELF :: R_MICROMIPS_HI0_LO16 : case ELF :: R_MICROMIPS_TLS_GD : case ELF :: R_MICROMIPS_TLS_LDM : case ELF :: R_MICROMIPS_TLS_DTPREL_HI16 : case ELF :: R_MICROMIPS_TLS_DTPREL_LO16 : case ELF :: R_MICROMIPS_TLS_GOTTPREL : case ELF :: R_MICROMIPS_TLS_TPREL_HI16 : case ELF :: R_MICROMIPS_TLS_TPREL_LO16 : case ELF :: R_MICROMIPS_GPREL7_S2 : case ELF :: R_MICROMIPS_PC23_S2 : case ELF :: R_MICROMIPS_PC21_S1 : case ELF :: R_MICROMIPS_PC26_S1 : case ELF :: R_MICROMIPS_PC18_S3 : case ELF :: R_MICROMIPS_PC19_S2 : return true ; case ELF :: R_MIPS16_26 : case ELF :: R_MIPS16_GPREL : case ELF :: R_MIPS16_CALL16 : case ELF :: R_MIPS16_TLS_GD : case ELF :: R_MIPS16_TLS_LDM : case ELF :: R_MIPS16_TLS_DTPREL_HI16 : case ELF :: R_MIPS16_TLS_DTPREL_LO16 : case ELF


<s> SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , GA ) ; } SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo


<s> return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } LO16 -> setMemRefs ( MI . memoperands_begin ( )


<s> ScoreboardHazardRecognizer ( ItinData ) , TII ( tii ) , TRI ( tri ) , STI ( sti ) , LastMI ( <NUM_LIT> ) , ITBlockSize


<s> } else if ( is_inverted_ccreg ( new_entry . cstore . set_src ( ) ) ) { log_msg ( <STR_LIT> ) ; new_entry . cstore_type = cstore_inverted ; } else if ( REG_P ( new_entry . cstore . set_src ( ) ) ) { new_entry . cstore_reg_reg_copies . push_back ( new_entry . cstore ) ; reg = new_entry . cstore . set_src ( ) ; i = new_entry . cstore . insn ; log_msg ( <STR_LIT> ) ; log_rtx ( reg ) ; log_msg ( <STR_LIT> ) ; continue ; } else log_return ( other_set_found , <STR_LIT> ) ; gcc_assert ( new_entry . cstore_type != cstore_unknown ) ; log_msg ( <STR_LIT> ) ; new_entry . setcc = find_set_of_reg_bb ( m_ccreg , prev_nonnote_insn_bb ( new_entry . cstore . insn ) ) ; if ( new_entry . setcc . set_src ( ) == NULL_RTX ) log_return ( set_found , <STR_LIT> ) ; else if ( GET_CODE ( new_entry . setcc . set_rtx ) == SET ) { log_insn ( new_entry . setcc . insn


<s> const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( )


<s> case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) . getSizeInBits ( ) ; ( void ) SrcSz ; assert ( SrcSz == Known . getBitWidth ( ) ) ; assert ( DstSz > SrcSz ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Known = Known . sext ( DstSz ) ; else { Known = Known . zext ( DstSz , true ) ; } assert ( DstSz == Known . getBitWidth ( )


<s> return AsmFlavor != Unset ? unsigned ( AsmFlavor


<s> if ( isAllOnes ( Mask ) ) return Op ; if ( MaskVT . bitsGT ( Mask . getValueType ( ) ) ) { EVT newMaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , MaskVT . getSizeInBits ( ) ) ; VMask = DAG . getBitcast ( MaskVT , DAG . getNode ( <STR_LIT> , dl , newMaskVT , Mask ) ) ; } else { EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT>


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else report_fatal_error


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 ) ; unsigned Flavour = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; unsigned RA = is<ISA_LIT>64 ? <STR_LIT>


<s> return ( unsigned short ) __builtin_loongarch_iocsrrd_h ( ( unsigned int ) _1


<s> bool hasV8_1aOps ( ) const { return HasV8_1aOps


<s> j += <NUM_LIT> ; } else if ( j != PC_REGNUM ) { if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else j ++ ; } else j ++ ; if ( offset > <NUM_LIT> ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = emit_insn ( tmp ) ; arm_add_cfa_adjust_cfa_note ( tmp , offset , stack_pointer_rtx , stack_pointer_rtx ) ; offset = <NUM_LIT> ; } if ( saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ) { par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT>


<s> int <ISA_LIT>FrameInfo :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { unsigned FrameReg ; return getFrameIndexReference ( MF , FI


<s> unsigned Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT>


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X


<s> bool <ISA_LIT>InstructionSelector :: emitInsertSubreg ( unsigned DstReg , unsigned SrcReg , MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; unsigned SubIdx = <STR_LIT> ; if ( ! DstTy . isVector ( ) || ! SrcTy . isVector ( ) ) return false ; assert ( SrcTy . getSizeInBits ( ) < DstTy . getSizeInBits ( ) && <STR_LIT>


<s> inline static uint64_t mimm2Val ( uint64_t Val ) { if ( Val == <NUM_LIT> ) return <NUM_LIT> ; if ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) return ( uint64_t ) ( ( <NUM_LIT> << <NUM_LIT>


<s> bool isCK802 ( ) const { return <ISA_LIT>ProcFamily ==


<s> Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo (


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) return true ; if ( NumElts == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true )

|| isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ;


<s> int last_argument_regno = NDS32_FIRST_GPR_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - <NUM_LIT> ; int rb_eh_data = cfun -> machine -> eh_return_data_first_regno ; int re_eh_data = cfun -> machine -> eh_return_data_last_regno ; int first_eh_data_regno = EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ; int rb_callee_saved = cfun -> machine -> callee_saved_first_gpr_regno ; int re_callee_saved = cfun -> machine -> callee_saved_last_gpr_regno ; if ( reg_mentioned_p ( gen_rtx_REG ( SImode , last_argument_regno ) , par_rtx ) ) { operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_va_args ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_va_args ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT> ; } if ( reg_mentioned_p ( gen_rtx_REG ( SImode , first_eh_data_regno ) , par_rtx ) ) { operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_eh_data ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_eh_data ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT> ; } if ( TARGET_V3PUSH && ! nds32_isr_function_p ( current_function_decl ) && ( cfun -> machine -> va_args_size == <NUM_LIT> ) ) { int sp_adjust


<s> bool Changed = false ; for ( MachineFunction :: iterator I = MF -> begin ( ) ; I != MF -> end ( ) ; ++ I ) { MachineBasicBlock & MBB = * I ; MachineBasicBlock :: iterator J = MBB . getFirstTerminator ( ) ; if ( J == MBB . end ( ) ) continue ; MachineInstr & MI = * J ; if ( MI . isConditionalBranch ( ) && ! isBlockInRange ( MI , * getDestBlock ( MI ) ) ) { fixupConditionalBranch ( MI ) ; ++ NumRelaxed ; Changed = true


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd5 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RC != <STR_LIT> && RC != <STR_LIT> ) return RC -> getRawAllocationOrder ( MF ) ; if ( HintType == <STR_LIT> ) { if ( isPhysicalRegister ( HintReg ) && getRegisterPairEven ( HintReg , MF ) == <NUM_LIT> ) return RC -> getRawAllocationOrder ( MF ) ; if ( ! TFI -> hasFP ( MF ) ) { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPREven1 ) ; else return makeArrayRef ( GPREven4 ) ; } else if ( FramePtr == <STR_LIT> ) { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPREven2 ) ; else return makeArrayRef ( GPREven5 ) ; } else { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPREven3 ) ; else return makeArrayRef ( GPREven6 ) ; } } else if ( HintType == <STR_LIT> ) { if ( isPhysicalRegister ( HintReg ) && getRegisterPairOdd ( HintReg , MF ) == <NUM_LIT> ) return RC -> getRawAllocationOrder ( MF ) ; if ( ! TFI -> hasFP ( MF ) ) { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPROdd1 ) ; else return makeArrayRef ( GPROdd4 ) ; } else if ( FramePtr == <STR_LIT>


<s> addPass ( create<ISA_LIT>PreRegAlloc ( ) ) ; return true


<s> assert ( CFP -> isNullValue ( ) && <STR_LIT> ) ; MVT VT ; if ( ! isTypeLegal ( CFP -> getType ( ) , VT ) ) return <NUM_LIT> ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; bool Is64Bit = ( VT == <STR_LIT> ) ; unsigned ZReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; return fastEmitInst_r ( Opc , TLI . getRegClassFor (


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; if ( Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm


<s> } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs ,


<s> TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; if ( ! Subtarget . is64Bit ( ) || Subtarget . isCallingConvWin64 ( MF . getFunction ( ) -> getCallingConv ( ) ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getMemBasePlusOffset ( FIN , <NUM_LIT> , DL ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> , DL ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , RSFIN , FIN , MachinePointerInfo ( SV , Subtarget . isTarget64BitLP64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) return parseDirectiveNaN ( ) ; if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpDWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDataDirective ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const mcld :: Target & pTarget , const std


<s> int FI = cast < FrameIndexSDNode > ( Loc ) -> getIndex ( ) ; int BFI = cast < FrameIndexSDNode > ( BaseLoc ) -> getIndex ( ) ; int FS = MFI . getObjectSize ( FI ) ; int BFS = MFI . getObjectSize ( BFI ) ; if ( FS != BFS || FS != ( int ) Bytes ) return false ; return MFI . getObjectOffset ( FI ) == ( MFI . getObjectOffset ( BFI ) + Dist * Bytes ) ; } SDValue Base1 = Loc , Base2 = BaseLoc ; int64_t Offset1 = <NUM_LIT> , Offset2 = <NUM_LIT> ; getBaseWithConstantOffset ( Loc , Base1 , Offset1 , DAG ) ; getBaseWithConstantOffset ( BaseLoc , Base2 , Offset2 , DAG ) ; if ( Base1 == Base2 && Offset1 == ( Offset2 + Dist * Bytes ) ) return true ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; const GlobalValue * GV1 = nullptr ; const GlobalValue * GV2 = nullptr ; Offset1 = <NUM_LIT> ; Offset2 = <NUM_LIT> ; bool isGA1 = TLI . isGAPlusOffset ( Loc . getNode ( ) , GV1 , Offset1 ) ; bool isGA2 = TLI . isGAPlusOffset ( BaseLoc . getNode ( ) , GV2 , Offset2 ) ; if ( isGA1 && isGA2 && GV1 == GV2 ) return Offset1 == (


_mm_mwait ( unsigned int __E , unsigned int __H ) {


<s> bool WaitInsert :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: StrictFP ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! isX87Instruction ( * MI ) ) continue ; if ( ! ( MI -> mayRaiseFPException ( ) || MI -> mayLoadOrStore ( ) ) || isX87ControlInstruction ( * MI ) ) continue ; MachineBasicBlock :: iterator AfterMI = std :: next ( MI ) ; if ( AfterMI != MBB . end ( ) && isX87Instruction ( * AfterMI ) && ! isX87NonWaitingControlInstruction ( * AfterMI ) ) continue ; BuildMI ( MBB , AfterMI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> return ! ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ||

RC == & <STR_LIT> || RC == & <STR_LIT> ) ;


<s> static bool or1k_return_in_memory ( const_tree type , const_tree ) { const HOST_WIDE_INT size = int_size_in_bytes


<s> split_const ( address , & base , & offset ) ; return loongarch_unspec_address_offset ( base , offset , symbol_type


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = make_unique < <ISA_LIT>Operand > ( KindReg , StartLoc , EndLoc ) ; Op -> Reg . Kind = Kind


<s> if ( MayStore ) return ! Defs . insert ( V ) || Uses . count ( V ) || SeenNoObjStore || SeenNoObjLoad ; Uses . insert


<s> return base -> vectors_per_tuple ( )


<s> IsKillSet = true ; for ( int i = <NUM_LIT> , e = EndMI . getNumOperands ( ) ; i != e ; ++ i ) if ( i != UseIndex ) clearOperandKillInfo ( EndMI , i ) ; } MachineBasicBlock :: reverse_iterator It = EndMI ; MachineBasicBlock :: reverse_iterator E = EndMI . getParent ( ) -> rend ( ) ; It ++ ; MachineOperand * MO = nullptr ; for ( ; It != E ; ++ It ) { if ( It -> isDebugInstr ( ) || It -> isPosition ( ) ) continue ; for ( int i = <NUM_LIT> , e = It -> getNumOperands ( ) ; i != e ; ++ i ) clearOperandKillInfo ( * It , i ) ; if ( ! IsKillSet ) { if ( ( MO = It -> findRegisterUseOperand ( RegNo , false , & getRegisterInfo ( ) ) ) ) { IsKillSet = true ; MO -> setIsKill ( true ) ; continue ; } else if ( ( MO = It -> findRegisterDefOperand ( RegNo , false , true , & getRegisterInfo ( ) ) ) ) { assert ( & * It == & StartMI &&


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitMEMBARRIER ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> int reg ; static int next_fcc_reg = <NUM_LIT> ; static rtx prev_args [ <NUM_LIT> ] [ <NUM_LIT> ] ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; reg ++ ) if ( prev_args [ reg ] [ <NUM_LIT> ] == x && prev_args [ reg ] [ <NUM_LIT> ] == y ) break ; if ( reg == <NUM_LIT> ) { reg = next_fcc_reg ; prev_args [ reg ] [ <NUM_LIT> ] = x ; prev_args [ reg ] [ <NUM_LIT> ] = y ; next_fcc_reg = ( next_fcc_reg + <NUM_LIT> ) & <NUM_LIT> ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE (


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > (


<s> case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case


<s> static DecodeStatus readInstruction32 ( const MemoryObject & region , uint64_t address , uint64_t & size , uint32_t & insn ) { uint8_t Bytes [ <NUM_LIT> ] ; if ( region . readBytes ( address , <NUM_LIT> , Bytes


<s> return ( __m128 ) __builtin_ia32_scalefss_mask_round ( ( __v4sf ) __A , ( __v4sf ) __B , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 )


<s> assert ( ( Subtarget . hasAVX2 ( ) || Domain < <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX2 ( MI . getOpcode ( ) , dom ) ; } assert ( table && <STR_LIT> ) ; MI . setDesc ( get ( table [


<s> vec_uint4 v ; unsigned short s [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . s [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) )

>> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ;


<s> SExtVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) { SExtVT = <STR_LIT> ; break ; } return SDValue ( ) ; } ; SDValue V = DAG . getNode ( <STR_LIT> , DL , SExtVT , Src ) ; if ( SExtVT == <STR_LIT> ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( V , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } else if ( SExtVT == <STR_LIT> || SExtVT == <STR_LIT> ) { V = getPMOVMSKB ( DL , V


<s> void clearModuleFeatureBits ( uint64_t Feature , StringRef FeatureString ) { clearFeatureBits ( Feature , FeatureString ) ; AssemblerOptions . front ( ) -> setFeatures ( STI . getFeatureBits


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl ,

<STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;