<s> dbgprintf ( insn , <STR_LIT> ) ; int vvvv ; if ( insn -> vectorExtensionType == TYPE_EVEX ) vvvv = ( v2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> | vvvvFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) vvvv = vvvvFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) vvvv &= <NUM_LIT> ; insn -> vvvv = static_cast < Reg > ( vvvv ) ; return


<s> Align Alignment ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; const Align PtrAlign = Align ( PtrSize ) ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrAlign ) ) ; MachineInstrBuilder DstPtr ; if ( Alignment > PtrAlign ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Alignment . value ( )


<s> Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy ) . getValue ( <NUM_LIT> ) ; SDValue Ops1 [ <NUM_LIT> ] = { Chain . getValue ( <NUM_LIT> ) , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; if ( Subtarget -> hasDivide ( ) ) return false ; RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = RTLIB :: SDIV_I8 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SDIV_I16 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SDIV_I32 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SDIV_I64 ; else if ( VT == <STR_LIT> ) LC = RTLIB :: SDIV_I128 ; assert ( LC != RTLIB ::


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( uint64x1_t ) ( __a < ( float64x1_t


<s> SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr


<s> MachineBasicBlock * target = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get


<s> if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) .


<s> SDLoc DL ( Op ) ; if ( ! Subtarget -> is64Bit ( ) || Subtarget -> isTargetWin64 ( ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } unsigned PointerSize = TD -> getPointerSize ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT>


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ; O << <STR_LIT>


<s> case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMADDSUB ( N , DAG , DCI ) ; case <STR_LIT> : return combineMOVMSK ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>GatherScatter ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineGatherScatter ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorCompare ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combinePMULDQ ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineKSHIFT ( N , DAG , DCI ) ; case <STR_LIT> : return combineFP16_TO_FP ( N , DAG , Subtarget ) ; case <STR_LIT>


<s> if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ; } Root -> replaceAllUsesWith ( Load ) ; Root -> eraseFromParent (


<s> GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; GVSym -> setContainingCsect ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym ) ; EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; OutStreamer -> EmitLabel ( EmittedInitSym ) ; EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemOffset ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( ( Value & <NUM_LIT> ) == <NUM_LIT> &&

Value <= <NUM_LIT> && Value >= - <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec .


<s> void print<ISA_LIT>Operands ( OperandVector & Operands ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Operands . size (


<s> MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn ) ) ) ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getImm16 ( insn ) ) ) ; else if ( Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getBitfieldInvMask ( insn ) ) ) ; else { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( getLsb ( insn ) ) ) ; if ( Opcode == <STR_LIT> ) { if ( getMsb ( insn ) < getLsb ( insn ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; return false


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) .


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( ! isi32Load ( Opcode ) && ! isi32Store ( Opcode ) ) return


<s> return ; } const MachineOperand & MO1 = MI -> getOperand ( Op ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB .


<s> Inst . addOperand ( MCOperand :: createReg ( VSRpRegs [ RegNo >> <NUM_LIT> ] ) ) ; return MCDisassembler ::


<s> unsigned Opc = getLoadStoreOp ( DstTy , RegBank , TargetOpcode :: G_LOAD , Alignment ) ; const ConstantFP * CFP = I . getOperand ( <NUM_LIT> ) . getFPImm ( ) ; unsigned CPI = MF . getConstantPool ( ) -> getConstantPoolIndex ( CFP , Alignment ) ; MachineInstr * LoadInst = nullptr ; unsigned char OpFlag = STI . classifyLocalReference ( nullptr ) ; if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { Register AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Alignment ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg )


<s> if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += <NUM_LIT> * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) return true ; } else return true ; } return


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL64 ( const Target & T , const MCRegisterInfo & MRI


<s> return __builtin_loongson_paddb_u ( s ,


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , (


<s> return ! Revert && FoundAllComponents ( ) && VCTP && ! CannotTailPredicate && ML


<s> return ( Attributes & ( <ISA_LIT>FMA3KMergeMasked |

<ISA_LIT>FMA3KZeroMasked ) ) != <NUM_LIT> ;


<s> bool need_barrier_p = maybe_ne ( get_frame_size ( ) + cfun -> machine -> frame . saved_varargs_size , <NUM_LIT> ) ; if ( maybe_gt ( final_adjust , crtl -> outgoing_args_size ) || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } rtx tmp0_rtx = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; rtx tmp1_rtx = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( frame_pointer_needed && ( maybe_ne ( final_adjust , <NUM_LIT> ) || cfun -> calls_alloca ) ) aarch64_add_offset ( Pmode , stack_pointer_rtx , hard_frame_pointer_rtx , - callee_offset , tmp1_rtx , tmp0_rtx , callee_adjust == <NUM_LIT> ) ; else aarch64_add_sp ( tmp1_rtx , tmp0_rtx , final_adjust , true ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; if ( aarch64_simd_decl_p ( cfun -> decl ) ) aarch64_restore_callee_saves ( TFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; else aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != <NUM_LIT> || maybe_gt ( initial_adjust , <NUM_LIT> ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; cfi_ops = NULL ; } aarch64_add_sp ( tmp0_rtx , tmp1_rtx , initial_adjust , ( ! can_inherit_p || ! crtl -> is_leaf || df_regs_ever_live_p ( EP0_REGNUM ) ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( aarch64_return_address_signing_enabled ( ) && ( for_sibcall || ! TARGET_ARMV8_3 || crtl -> calls_eh_return ) ) { insn = emit_insn ( gen_autisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( crtl -> calls_eh_return ) { emit_insn ( gen_add2_insn ( stack_pointer_rtx , EH_RETURN_STACKADJ_RTX )


<s> } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } SmallVector < uint64_t , <NUM_LIT> > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * <NUM_LIT> ) ; SmallVector < unsigned , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> __builtin_ia32_scatterpfqps ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , ( int const


<s> Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Opc = Old -> getOpcode ( ) ; int PIdx = Old -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( PIdx ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , Pred , PredReg ) ; } else


<s> const InstrItineraryData & getInstrItineraryData (


<s> unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( IdxVal , dl ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } N2 = DAG . getIntPtrConstant ( IdxVal << <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return Op ; } return SDValue ( )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> int64_t Val = CE -> getValue ( ) ; int64_t Min = - ( <NUM_LIT> * ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ; int64_t Max = <NUM_LIT> * ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) ; return ( Val % <NUM_LIT> ) == <NUM_LIT> &&


<s> for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return false


<s> DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ; return


<s> split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , INTVAL (


<s> unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { KnownBits MKnown ; CurDAG -> computeKnownBits ( Op1 . getOperand ( <NUM_LIT> ) , MKnown ) ; bool CanFoldMask = InsertMask == MKnown . One . getZExtValue ( ) ; unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && CanFoldMask && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SH = ( SHOpc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } } SH &= <NUM_LIT> ; SDValue Ops [ ] = { Op0 , Op1 , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME


<s> void <ISA_LIT>GNULDBackend :: defineGOTSymbol ( IRBuilder & pBuilder ) { if ( m_pGOTSymbol != NULL ) { pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( *

( m_pGOTPLT -> begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ;


<s> rtx op0 , op1 , ret ; op0 = ix86_compare_op0 ; op1 = ix86_compare_op1 ; if ( second_test ) * second_test = NULL_RTX ; if ( bypass_test ) * bypass_test = NULL_RTX ; if ( ix86_compare_emitted ) { ret = gen_rtx_fmt_ee ( code , VOIDmode , ix86_compare_emitted , const0_rtx ) ; ix86_compare_emitted =


<s> int cost_symbol_ref = rtx_cost ( x , Pmode , MEM , <NUM_LIT> , speed ) ; cost_symbol_ref /= COSTS_N_INSNS ( <NUM_LIT> ) ; return cost_symbol_ref + addr_cost -> imm_offset ; } else { return addr_cost -> register_offset ; } } switch ( info . type ) { case ADDRESS_LO_SUM : case ADDRESS_SYMBOLIC : case ADDRESS_REG_IMM : cost += addr_cost -> imm_offset ; break ; case ADDRESS_REG_WB : if ( c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY ) cost += addr_cost -> pre_modify ; else if ( c == POST_INC || c == POST_DEC || c == POST_MODIFY ) cost += addr_cost -> post_modify ; else gcc_unreachable ( ) ; break ; case ADDRESS_REG_REG : cost += addr_cost -> register_offset ; break ; case ADDRESS_REG_SXTW : cost += addr_cost -> register_sextend ; break ; case ADDRESS_REG_UXTW : cost += addr_cost -> register_zextend ; break ; default : gcc_unreachable ( ) ; } if ( info . shift > <NUM_LIT> ) { if ( known_eq ( GET_MODE_BITSIZE ( mode ) , <NUM_LIT> ) ) cost += addr_cost -> addr_scale_costs . hi ; else if ( known_eq ( GET_MODE_BITSIZE ( mode ) , <NUM_LIT> ) ) cost += addr_cost -> addr_scale_costs . si ; else if ( known_eq ( GET_MODE_BITSIZE ( mode ) , <NUM_LIT> ) ) cost += addr_cost -> addr_scale_costs . di ; else cost += addr_cost -> addr_scale_costs


<s> switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> do { MergedCandidates = false ; Cand1 . clear ( ) ; Cand2 . clear ( ) ; Cand1 . BranchBlock = & MBB ; if ( ! canCoalesceBranch ( Cand1 ) ) break ; Cand2 . BranchBlock = Cand1 . BranchTargetBlock ; if ( ! canCoalesceBranch ( Cand2 ) ) break ; assert ( MPDT -> dominates ( Cand2 . BranchTargetBlock , Cand1 . BranchBlock ) && <STR_LIT> ) ; if ( ! identicalOperands ( Cand1 . Cond , Cand2 . Cond ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Cand1 . BranchBlock -> getNumber ( ) <<

<STR_LIT> << Cand2 . BranchBlock -> getNumber ( ) << <STR_LIT> ) ;


<s> bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo , isPIC , DAG


<s> Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static && TLI . getPointerTy ( DL ) == <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addGlobalAddress ( GV ) ; } else { unsigned Opc = TLI . getPointerTy ( DL ) == <STR_LIT> ? ( Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; } return


<s> return ( uint64x1_t ) { vcvtmd_u64_f64 ( __a


<s> bool dumpConstPool ( ) const { return


<s> static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo ,


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv2di ( __a )


<s> Len /= <NUM_LIT> ; Idx /= <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back ( i + Idx ) ; for ( int i = Len ; i != <NUM_LIT> ; ++ i ) ShuffleMask .


<s> static bool iq2000_print_operand_punct_valid_p ( unsigned char code ) { return iq2000_print_operand_punct [


<s> if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : !


<s> case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q'


<s> return * ( getContext ( ) . getRegisterInfo ( ) . getRegClass ( RC ) . begin


<s> OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; if ( ! NoNanDirective ) STI . isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( STI . isGP32bit ( ) ) OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; } getTargetStreamer ( ) . updateABIInfo ( STI ) ; if ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) getTargetStreamer ( ) . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) getTargetStreamer ( )


<s> SDValue Lane = Op1 . getOperand ( <NUM_LIT> ) ; EVT ResTy = N -> getValueType ( <NUM_LIT> ) ; EVT VecResTy ; SDLoc DL ( N ) ; assert ( Vec . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Vec . getValueType ( ) == <STR_LIT> ) VecResTy = <STR_LIT> ; else if ( Vec . getValueType ( ) == <STR_LIT> ) VecResTy = <STR_LIT> ; else assert ( <NUM_LIT> && <STR_LIT> ) ; SDValue Convert = DAG . getNode ( <STR_LIT> , DL , VecResTy , IID , Vec , Shift ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> SDValue Result = DAG . getAtomic ( Node -> getOpcode ( ) , dl , <STR_LIT> , Tys , Ops . data ( ) , Ops . size ( ) , cast < MemSDNode > ( Node ) -> getMemOperand ( ) , AN -> getSuccessOrdering ( ) , AN -> getFailureOrdering ( ) , AN -> getSynchScope ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( )


<s> const DenseMap < int , unsigned > & getWinEHXMMSlotInfo ( ) const { return WinEHXMMSlotInfo ;


<s> const char * prefix = <STR_LIT> ; const char * suffix = <STR_LIT> ; if ( TARGET_SPE ) { gcc_assert ( ( sel & SAVRES_REG ) == SAVRES_GPR ) ; if ( ( sel & SAVRES_SAVE ) ) prefix = info -> spe_64bit_regs_used ? <STR_LIT> : <STR_LIT> ; else prefix = info -> spe_64bit_regs_used ? <STR_LIT> : <STR_LIT> ; if ( ( sel & SAVRES_LR ) ) suffix = <STR_LIT> ; } else if ( DEFAULT_ABI == ABI_V4 ) { if ( TARGET_64BIT ) goto aix_names ; if ( ( sel & SAVRES_REG ) == SAVRES_GPR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else if ( ( sel & SAVRES_REG ) == SAVRES_FPR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else if ( ( sel & SAVRES_REG ) == SAVRES_VR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else abort ( ) ; if ( ( sel & SAVRES_LR ) ) suffix


<s> if ( Add . first == nullptr ) return nullptr ; Value * OffsetsIncoming = Add . first ; int64_t Immediate = Add . second ; if ( OffsetsIncoming != Phi ) return nullptr ; Builder . SetInsertPoint ( & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; unsigned NumElems = cast < FixedVectorType > ( OffsetsIncoming -> getType ( ) ) -> getNumElements ( ) ; Instruction * ScaledOffsets = BinaryOperator :: Create ( Instruction :: Shl , Phi -> getIncomingValue ( <NUM_LIT> - IncrementIndex ) , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( TypeScale ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Add , ScaledOffsets , Builder . CreateVectorSplat ( NumElems , Builder . CreatePtrToInt ( BasePtr , cast < VectorType > ( ScaledOffsets -> getType ( ) ) -> getElementType ( ) ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Sub , OffsetsIncoming , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( Immediate ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; Phi -> setIncomingValue ( <NUM_LIT> - IncrementIndex , OffsetsIncoming ) ; Builder . SetInsertPoint ( I ) ; Value * EndResult ; Value * NewInduction ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) { Value * Load = tryCreateMaskedGatherBaseWB ( I , Phi , Builder , Immediate ) ; EndResult = Builder . CreateExtractValue ( Load , <NUM_LIT> , <STR_LIT> ) ; NewInduction = Builder . CreateExtractValue ( Load , <NUM_LIT> , <STR_LIT> ) ; } else { NewInduction = tryCreateMaskedScatterBaseWB ( I , Phi , Builder , Immediate ) ; EndResult = NewInduction ; } Instruction * AddInst = cast < Instruction > ( Offsets ) ; AddInst -> replaceAllUsesWith ( NewInduction ) ; AddInst -> eraseFromParent


<s> Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0


<s> case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill2 = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned InRegLEA2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , InRegLEA , true , InRegLEA , false ) ; } else { if ( Subtarget . is64Bit ( ) ) InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA2 , RegState :: Define , SubReg ) . addReg ( Src2 , getKillRegState ( IsKill2 ) ) ; addRegReg ( MIB , InRegLEA , true , InRegLEA2 , true ) ; } if ( LV && IsKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , * InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( IsDead ) ) . addReg ( OutRegLEA , RegState :: Kill , SubReg ) ; if ( LV ) { LV -> getVarInfo ( InRegLEA ) . Kills


<s> it != ie ; ++ it ) { if ( it -> m_Inputs . count ( & pInput ) ) break ; gotSize += ( <ISA_LIT>GOT0Num + it -> m_LocalNum + it -> m_GlobalNum ) ; if ( it == m_MultipartList . begin ( ) ) gotSize += getGlobalNum ( ) -


<s> } if ( ABI . IsO32 ( ) && IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { MVT LocVT = VA . getLocVT ( ) ; assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Load = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; InVals . push_back ( Load ) ; OutChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; } } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ i ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; break ; } } if ( ! OutChains .


<s> if ( CSI . empty ( ) ) return false ; static LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target (


<s> m_Section . setSize ( size ) ; uint32_t offset = <NUM_LIT> ; SectionData :: iterator frag , fragEnd = m_pSectionData -> end ( ) ; for ( frag = m_pSectionData -> begin ( ) ; frag != fragEnd ; ++ frag ) { frag -> setOffset ( offset ) ; offset += frag -> size (


<s> assert ( CPI < ConstPoolId2AddrMap .


<s> MachineBasicBlock * DestBB = MI -> getOperand ( TargetOperand ) . getMBB ( ) ; if ( isBBInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return fixupUnconditionalBr ( Br ) ; return fixupConditionalBr ( Br


<s> const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Off , getContext


<s> case <STR_LIT> : return combineLOAD ( N , DCI ) ; case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineVECTOR_SHUFFLE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : return combineFP_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : return combineBR_CCMASK ( N , DCI ) ; case <STR_LIT> : return combineSELECT_CCMASK ( N , DCI ) ; case <STR_LIT> : return combineGET_CCMASK ( N , DCI ) ; case <STR_LIT>


<s> static void addHints ( ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const TargetRegisterClass * RC , const MachineRegisterInfo * MRI ) { SmallSet < unsigned , <NUM_LIT> > CopyHints ; CopyHints . insert ( Hints . begin ( ) , Hints . end ( ) ) ; Hints . clear ( ) ; for ( MCPhysReg Reg : Order ) if ( CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI

-> isReserved ( Reg ) ) Hints . push_back ( Reg ) ;


<s> return ( cum -> outgoing && ( ( mode == BLKmode ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode )

) % SH_MIN_ALIGN_FOR_CALLEE_COPY == <NUM_LIT> ) ) ;


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name , bool is64BitReg ) { int CC ; CC = matchCPURegisterName ( Name ) ; if ( CC != - <NUM_LIT> ) return matchRegisterByNumber ( CC , is64BitReg ? <STR_LIT> : <STR_LIT> ) ; CC = matchFPURegisterName ( Name ) ; if ( CC != - <NUM_LIT> ) return matchRegisterByNumber ( CC , isFP64 ( ) ? <STR_LIT>


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: mergePredStateIntoSP ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt , DebugLoc Loc , unsigned PredStateReg ) { Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( PredStateReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> ,


<s> if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) { } return ! I -> isBarrier (


<s> if ( ST . hasCmpBccFusion ( ) || ST . hasArithmeticBccFusion ( ) ) { bool CmpOnly = ! ST . hasArithmeticBccFusion ( ) ; if ( isArithmeticBccPair ( FirstMI , SecondMI , CmpOnly ) ) return true ; } if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseCryptoEOR ( ) && isCryptoEORPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAddress ( ) && isAddressLdStPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseCCSelect ( ) && isCCSelectPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseArithmeticLogic ( ) && isArithmeticLogicPair ( FirstMI , SecondMI ) ) return true ; return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( shiftLo >> <NUM_LIT> == <NUM_LIT> ) return Fail ; DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rd ,


<s> uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; } break ; } case <STR_LIT> : { EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ElemBitSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) ResNode = tryGather ( Node , <STR_LIT> ) ; else if ( ElemBitSize == <NUM_LIT> ) ResNode = tryGather ( Node , <STR_LIT> ) ; break ; } case <STR_LIT>


<s> NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( isIntrinsic ) { VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && ( ! CInc || CInc -> getZExtValue ( ) != NumBytes ) ) { continue ; } EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment


<s> if ( counters . failed_loads ) fprintf ( dump_file , <STR_LIT> , counters . failed_loads ) ; fprintf ( dump_file , <STR_LIT> , counters . stores , counters . adjacent_stores ) ; if ( counters . failed_stores ) fprintf ( dump_file , <STR_LIT> , counters . failed_stores ) ; fprintf ( dump_file , <STR_LIT> ) ; } df_remove_problem ( df_chain ) ; df_process_deferred_rescans ( ) ; df_set_flags ( DF_RD_PRUNE_DEAD_DEFS


<s> static SDValue lowerToAddSubOrFMAddSub ( const BuildVectorSDNode * BV , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue Opnd0 , Opnd1 ; if ( ! isAddSub ( BV , Subtarget , DAG , Opnd0 , Opnd1 ) )


) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> mantissa = w . elt ( <NUM_LIT> ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ; if ( ( mantissa & mask ) != <NUM_LIT> ) return false ; mantissa >>= point_pos - <NUM_LIT> ; if ( mantissa == <NUM_LIT> ) return false ; mantissa &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; gcc_assert ( mantissa <= <NUM_LIT> ) ; exponent = <NUM_LIT> - exponent ; return ( exponent >= <NUM_LIT>


<s> int32x4x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = (


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind >= FirstLiteralRelocationKind ) return

MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ;


<s> MMO = cast < LoadSDNode > ( StackSlot ) -> getMemOperand ( ) ; StackSlot = StackSlot . getOperand ( <NUM_LIT> ) ; } SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( SrcVT ) } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , SrcVT , MMO ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( SSFISize , SSFISize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; Tys = DAG . getVTList ( <STR_LIT> )


<s> bool <ISA_LIT>InterleavedAccessGroup :: lowerIntoOptimizedSequence ( ) { SmallVector < Instruction * , <NUM_LIT> > DecomposedVectors ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; if ( ! decompose ( Inst , Factor , VecTy , DecomposedVectors ) ) return false ; SmallVector < Value * , <NUM_LIT> > TransposedVectors ; transpose_4x4 ( DecomposedVectors ,


<s> if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . startswith ( <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> == <NUM_LIT> ) ; Reg >>= <NUM_LIT> ; } } else if ( Prefix == <STR_LIT> ) RC = TRI -> getRegClass ( <STR_LIT> ) ; else if ( Prefix == <STR_LIT> ) { RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; } else if ( Prefix == <STR_LIT> ) { if ( Reg == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RC = getRegClassFor


<s> SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , DL , <STR_LIT> ) , Cmp . getValue ( <NUM_LIT> ) ) ; if ( Op . getSimpleValueType ( ) == <STR_LIT> ) { SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; } return SetCC


<s> const char * output_adjust_stack_and_probe ( rtx reg ) { static int labelno = <NUM_LIT> ; char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = stack_pointer_rtx ; xops [ <NUM_LIT> ] = GEN_INT ( PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = const0_rtx ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = stack_pointer_rtx ; xops [ <NUM_LIT> ] = reg ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file )


<s> if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , & sparc_tls_symbol_ref_1 , <NUM_LIT>


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) , false ) ; addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( )


<s> MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start , getContext ( ) ) ; Symbol -> setVariableValue (


<s> inline bool base_reg_disp :: is_disp ( void ) const { return reg_ == NULL_RTX &&


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B )


<s> printOperand ( MI , OpNo , O ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo , O ) ; return false


<s> void Thumb1FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; unsigned Align = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( Align ) ; unsigned NumBytes = MFI -> getStackSize ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned BasePtr = RegInfo -> getBaseRegister ( ) ; NumBytes = ( NumBytes + <NUM_LIT> ) & ~ <NUM_LIT> ; MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( ArgRegsSaveSize ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - ArgRegsSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo ,

- NumBytes , MachineInstr :: FrameSetup ) ;


<s> bool hasIFMA ( ) const { return HasIFMA


<s> return reinterpret_cast < const <ISA_LIT>Subtarget & >


<s> CurType . Size = CurType . ElementSize ; break ; case IES_INIT : case IES_CAST : assert ( ! BracCount && <STR_LIT> ) ; State = IES_LBRAC ; break ; } MemExpr = true ; BracCount ++ ; return false


<s> OutStreamer -> EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * Anon = MCSymbolRefExpr :: create ( AnonSymbol , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: create ( LazyPtr , OutContext ) ; const MCExpr * Sub = MCBinaryExpr :: createSub ( LazyPtrExpr , Anon , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( Anon ) ) ; OutStreamer -> EmitLabel ( AnonSymbol ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubHa16 = <ISA_LIT>MCExpr :: createHa ( Sub , true , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubHa16 ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubLo16 = <ISA_LIT>MCExpr :: createLo ( Sub , true , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubLo16 ) . addExpr ( SubLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer -> SwitchSection ( LSPSection ) ; OutStreamer -> EmitLabel ( LazyPtr ) ; OutStreamer -> EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; MCSymbol * DyldStubBindingHelper = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) { OutStreamer -> EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } else { OutStreamer -> EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } } OutStreamer -> AddBlankLine ( )


<s> unsigned OpCmode = getNEONModImmOpCmode ( ModImm ) ; unsigned Imm8 = getNEONModImmVal ( ModImm ) ; uint64_t Val = <NUM_LIT> ; if ( OpCmode == <NUM_LIT> ) { Val = Imm8 ; EltBits = <NUM_LIT> ; } else if ( ( OpCmode & <NUM_LIT> ) == <NUM_LIT> ) { unsigned ByteNum = ( OpCmode & <NUM_LIT> ) >> <NUM_LIT> ; Val = Imm8 << ( <NUM_LIT> * ByteNum ) ; EltBits = <NUM_LIT> ; } else if ( ( OpCmode & <NUM_LIT> ) == <NUM_LIT> ) { unsigned ByteNum = ( OpCmode & <NUM_LIT> ) >> <NUM_LIT> ; Val = Imm8 << ( <NUM_LIT> * ByteNum ) ; EltBits =


<s> unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; unsigned StackOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register StackReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SPReg = Subtarget . is<ISA_LIT>64 (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateNumericReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { DEBUG ( dbgs ( ) << <STR_LIT> << Index << <STR_LIT> ) ; return CreateReg ( Index , RegKind_Numeric , RegInfo , S , E


<s> } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j )

|| ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) ) return false ;


<s> F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , DL , TII -> get


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT> -


<s> bool hasGuardedStorage ( ) const { return HasGuardedStorage


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDValue Narrow = N -> getOperand ( <NUM_LIT> ) ; EVT NarrowVT = Narrow . getValueType ( ) ; SDValue Op = PromoteMaskArithmetic ( Narrow . getNode ( ) ,


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ; if ( TheTriple . isOSWindows ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } return createELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll


<s> analysis_result result = element_info . analyze ( TREE_TYPE ( type ) ) ; if ( result != IS_PST ) return result ; tree nelts_minus_one = array_type_nelts ( type ) ; if ( ! tree_fits_uhwi_p ( nelts_minus_one ) ) return DOESNT_MATTER ; unsigned HOST_WIDE_INT count = tree_to_uhwi ( nelts_minus_one ) ; if ( count > MAX_PIECES ) return DOESNT_MATTER ; count += <NUM_LIT> ; if ( count * element_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; poly_uint64 element_bytes ; if ( ! poly_int_tree_p ( TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) , & element_bytes ) ) gcc_unreachable ( ) ; gcc_assert ( ! element_info . pieces . is_empty ( ) ) ; for ( unsigned int i = <NUM_LIT> ; i < count ; ++ i ) for ( unsigned int j = <NUM_LIT> ; j < element_info . pieces . length ( ) ; ++ j ) { piece p = element_info . pieces [ j ] ; p . offset += i


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BimmX16MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( isBBInRange ( MI , DestBB , BimmX16MaxDisp ) ) { Br . MaxDisp = BimmX16MaxDisp ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } else { DestBB -> setAlignment ( Align ( <NUM_LIT> ) ) ; Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return true


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_MemoryImm ) ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = <NUM_LIT> ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc


<s> if ( ! isHLASMAlpha ( RawLabel [ <NUM_LIT> ] ) ) return ! Error ( Loc , <STR_LIT> <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < RawLabel . size ( ) ; ++ I ) if ( ! isHLASMAlnum ( RawLabel [ I ] ) )


<s> } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; } return false


<s> return isRegOperand ( Base ) && isRegOperand ( Index ) &&


<s> else if ( ClUncheckedLdSt == UncheckedAlways ) return true ; unsigned FrameSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i

) FrameSize += MFI -> getObjectSize ( i ) ;


<s> return ( __m128 ) __builtin_ia32_addps ( ( __v4sf )


<s> std :: unique_ptr < MCObjectTargetWriter > llvm ::

create<ISA_LIT>ObjectWriter ( uint8_t OSABI ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( Subtarget -> isFPOnlySP ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op .

getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; updateValueMap ( I ,


<s> FunctionPass * llvm :: create<ISA_LIT>LongBranchPass


<s> bool hasHardQuad ( ) const { return HasHardQuad


<s> vmull_p8 ( poly8x8_t a , poly8x8_t b ) { poly16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> fputs ( <STR_LIT> , f ) ; } else { if ( ASSEMBLER_DIALECT == <NUM_LIT> ) { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; if ( ASSEMBLER_DIALECT == <NUM_LIT> ) fputs ( <STR_LIT> , f ) ; else fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f


<s> if ( ( ShuffleKind == <NUM_LIT> && ! isLE ) || ( ShuffleKind == <NUM_LIT> && isLE ) ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else if ( ShuffleKind == <NUM_LIT> ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ( ShiftAmt + i ) & <NUM_LIT> ) ) return - <NUM_LIT> ; } else return - <NUM_LIT> ; if ( ShuffleKind == <NUM_LIT> && isLE ) ShiftAmt = <NUM_LIT> - ShiftAmt ; return ShiftAmt


<s> return ( __mmask8 ) __builtin_ia32_cmpsh_mask_round ( __B ,


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( )


<s> EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return materializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return


<s> if ( ! TARGET_IEEE_FP ) return <NUM_LIT> ; switch ( code ) { case UNLE : case UNLT : case LTGT : case GT : case GE : case UNORDERED : case ORDERED : case UNEQ : return <NUM_LIT> ; break ; case LT : case NE


<s> MachineInstr * <ISA_LIT>BaseInstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode *


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) ) ; return


<s> else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ; else llvm_unreachable (


<s> bool handled_one = false ; if ( arm_except_unwind_info ( & global_options ) != UI_TARGET ) return ; if ( ! ( flag_unwind_tables || crtl -> uses_eh_lsda ) && ( TREE_NOTHROW ( current_function_decl ) || crtl -> all_throwers_are_sibcalls ) ) return ; if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , <NUM_LIT> ) ; goto found ; case REG_CFA_REGISTER : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; } { rtx dest , src ; unsigned reg ; src = SET_SRC ( pat ) ; dest = SET_DEST ( pat ) ; gcc_assert ( src == stack_pointer_rtx || IS_PAC_REGNUM ( REGNO ( src ) ) ) ; reg = REGNO ( dest ) ; if ( IS_PAC_REGNUM ( REGNO ( src ) ) )

arm_unwind_emit_set ( out_file , PATTERN ( insn ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return


<s> void <ISA_LIT>ConditionalCompares :: updateLoops ( ArrayRef < MachineBasicBlock * > Removed ) { if ( ! Loops ) return ; for ( unsigned i = <NUM_LIT> , e = Removed . size ( ) ; i != e ; ++ i ) Loops -> removeBlock (


<s> static DecodeStatus decodeShiftImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Offset = ( Insn &


<s> mep_expand_setcc_1 ( LTU , op2 , op1 , const1_rtx ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_XOR ( SImode , op2 , const1_rtx ) ) ) ; return true ; case LE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == <NUM_LIT> ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) + <NUM_LIT> ) ; return mep_expand_setcc_1 ( LT , dest , op1 , op2 ) ; case LEU : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == - <NUM_LIT> ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) + <NUM_LIT> , SImode ) ) ; return mep_expand_setcc_1 ( LTU , dest , op1 , op2 ) ; case GE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == trunc_int_for_mode ( <NUM_LIT> , SImode ) ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) - <NUM_LIT> ) ; return mep_expand_setcc_1 ( GT , dest , op1 , op2 ) ; case GEU : if ( GET_CODE ( op2 ) != CONST_INT || op2 == const0_rtx ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG , bool IsSigned ) { SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT OpVT = Vec . getValueType ( ) ; unsigned Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( OpVT == <STR_LIT> && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == OpVT . getSizeInBits ( ) ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } if ( VT . getSizeInBits ( ) > OpVT . getSizeInBits ( ) ) { assert ( Vec . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> &&


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveCpsetup ( unsigned RegNo , int RegOrOffset , const MCSymbol & Sym , bool IsReg ) { if ( ! Pic || ! ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ; MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCInst Inst ; if ( IsReg ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegOrOffset ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain


<s> if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << printReg ( FullReg ) << <STR_LIT> ) ; eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ; unsigned OpReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( OpReg ) ) break ; MachineInstr * Def = MRI -> getVRegDef


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found =


<s> MCSymbol * FallthroughLabel ; if ( IsConditional ) { FallthroughLabel = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ( static_cast < <STR_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( MCSymbolRefExpr :: create ( FallthroughLabel , OutContext ) ) ) ; RetInst = MCInst ( ) ; RetInst . setOpcode ( <STR_LIT> ) ; } OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , RetInst ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT>


<s> Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned TmpReg1 = <ISA_LIT>Materialize32BitInt ( Imm , RC ) ; if ( ! Shift ) return TmpReg1 ; unsigned TmpReg2 ; if ( Imm ) { TmpReg2 = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addReg ( TmpReg1 ) . addImm ( Shift ) . addImm ( <NUM_LIT> - Shift ) ; } else TmpReg2 = TmpReg1 ; unsigned TmpReg3 , Hi , Lo


<s> <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue SymAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; } else llvm_unreachable (


<s> static bool mips_canonicalize_comparison ( enum rtx_code * code , rtx * cmp1 , enum machine_mode mode ) { HOST_WIDE_INT original , plus_one ; if ( GET_CODE ( * cmp1 ) != CONST_INT ) return false ; original = INTVAL ( * cmp1 ) ; plus_one = trunc_int_for_mode ( ( unsigned HOST_WIDE_INT ) original + <NUM_LIT> , mode ) ; switch ( * code ) { case LE


<s> void <ISA_LIT>InstPrinter :: printFPR ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI ->


<s> <ISA_LIT>DisassemblerBase ( STI , Info ,


<s> static bool SupportedVectorShiftWithImm ( MVT VT , const <ISA_LIT>Subtarget * Subtarget , unsigned Opcode ) { if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . is512BitVector ( ) && ( VT . getScalarSizeInBits ( ) > <NUM_LIT> || Subtarget -> hasBWI ( ) ) ) return true ; bool LShift = VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ; bool AShift = LShift && ( Subtarget -> hasVLX ( ) || (

VT != <STR_LIT> && VT != <STR_LIT> ) ) ;


<s> return <NUM_LIT> - MI . getOperand ( Op


<s> unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; for ( auto Candidate : <STR_LIT> ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == Candidate ) { IsDef = true ; break ; } } if ( IsDef ) continue ; Regs [ FoundRegs ++ ] =


<s> static DecodeStatus DecodeLoadQFP ( MCInst & Inst , unsigned insn

, uint64_t Address , const void * Decoder ) {


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg )


<s> Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> ret = <NUM_LIT> ; } else { clonei -> vecsize_mangle = <STR_LIT> [ num ] ; ret = <NUM_LIT> ; } clonei -> mask_mode = VOIDmode ; switch ( clonei -> vecsize_mangle ) { case 'b' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'c' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'd' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'e' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; if ( TYPE_MODE ( base_type ) == QImode ) clonei -> mask_mode = DImode ; else clonei -> mask_mode = SImode ; break ; } if ( clonei -> simdlen == <NUM_LIT> ) { if ( SCALAR_INT_MODE_P ( TYPE_MODE ( base_type ) ) ) clonei -> simdlen = clonei -> vecsize_int ; else clonei -> simdlen = clonei -> vecsize_float ; clonei -> simdlen /= GET_MODE_BITSIZE ( TYPE_MODE ( base_type ) ) ; } else if ( clonei -> simdlen


<s> unsigned Base = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset


<s> if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep && ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_extern ) && ( flag_cf_protection & CF_RETURN ) ) error ( <STR_LIT> <STR_LIT> ) ; } if ( cfun -> machine -> function_return_type == indirect_branch_unset ) { tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; if ( attr != NULL ) { tree args = TREE_VALUE ( attr ) ; if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine -> function_return_type = ix86_function_return ; if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ( ( cfun -> machine -> function_return_type == indirect_branch_thunk_extern ) || ( cfun -> machine -> function_return_type == indirect_branch_thunk ) ) ) error ( <STR_LIT> <STR_LIT> , ( ( cfun -> machine -> function_return_type == indirect_branch_thunk_extern ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( cfun -> machine -> function_return_type != indirect_branch_keep && ( cfun -> machine -> function_return_type != indirect_branch_thunk_extern ) && ( flag_cf_protection &


<s> emit_insn ( gen_movsi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( mode == DImode ) { gcc_assert ( TARGET_ARCH64 ) ; emit_insn ( gen_movdi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } } if ( symbolic_operand ( operands [ <NUM_LIT> ] , mode ) ) { operands [ <NUM_LIT> ] = sparc_legitimize_pic_address ( operands [ <NUM_LIT> ] , reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ; return false ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) && ( SPARC_FP_REG_P ( REGNO ( operands [ <NUM_LIT> ] ) ) || SCALAR_FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = CONST0_RTX ( mode ) ; if ( ( TARGET_VIS || REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG ) && ( const_zero_operand ( operands [ <NUM_LIT> ] , mode ) || const_all_ones_operand ( operands [ <NUM_LIT> ] , mode ) ) ) return false ; if ( REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG && ( mode == SFmode || ( mode == DFmode && ! can_create_pseudo_p ( ) ) ) ) return false ; operands [ <NUM_LIT> ] = force_const_mem ( mode , operands [ <NUM_LIT> ] ) ; if ( ! reload_in_progress ) operands [ <NUM_LIT> ] = validize_mem ( operands [ <NUM_LIT> ] ) ; return false ; } if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == HIGH || input_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; switch ( mode ) { case QImode : break ; case HImode : case SImode : sparc_emit_set_const32 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; case DImode : sparc_emit_set_const64 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; case TImode : { rtx high , low ; split_double ( operands [ <NUM_LIT> ] , & high , & low ) ; emit_insn ( gen_movdi ( operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , TImode ) , high ) ) ; emit_insn ( gen_movdi ( operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , TImode ) , low ) ) ; } return true ; default : gcc_unreachable ( )


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT


<s> static DecodeStatus DecodePCRelLabel19 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { int64_t ImmVal = Imm ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler (


<s> Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; default : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; SegmentReg = <STR_LIT> ; break ; } unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . EmitBytes ( <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : OS . EmitInstruction ( MCInstBuilder ( Opc ) , STI ) ; break ; case <STR_LIT> : OS . EmitInstruction ( MCInstBuilder ( Opc ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) , STI ) ; break ; case <STR_LIT>


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Prefetch , Ctx ) ; Op -> Prefetch . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> static reg_class_t sparc_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { enum reg_class rclass = ( enum reg_class ) rclass_i ; sri -> icode = CODE_FOR_nothing ; sri -> extra_cost = <NUM_LIT> ; if ( FP_REG_CLASS_P ( rclass ) && ( mode == HImode || mode == QImode ) && ( GET_CODE ( x ) == MEM || ( ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) && true_regnum ( x ) == - <NUM_LIT> ) ) ) return GENERAL_REGS ; if ( TARGET_ARCH32 && rclass == EXTRA_FP_REGS && mode == DFmode && GET_CODE ( x ) == MEM && ! mem_min_alignment ( x , <NUM_LIT> ) ) return FP_REGS ; if ( ( ( TARGET_CM_MEDANY && symbolic_operand ( x , mode ) ) || ( TARGET_CM_EMBMEDANY && text_segment_operand ( x , mode ) ) ) && ! flag_pic ) { if ( in_p ) sri -> icode = direct_optab_handler


<s> return __builtin_mve_vornq_fv4sf ( __a ,


<s> unsigned KnownBits = BBI . internalKnownBits ( ) ; UserOffset += ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; U . KnownAlignment = ( KnownBits >= <NUM_LIT> ) ; if ( isThumb && U .

KnownAlignment ) UserOffset &= ~ <NUM_LIT> ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG .

getTargetConstant ( Cond , dl , <STR_LIT> ) , EFLAGS ) ;


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS


<s> return ( ( * given == <NUM_LIT> && * canonical == <NUM_LIT> ) || ( strcmp (

canonical , <STR_LIT> ) == <NUM_LIT> && strcasecmp ( given , <STR_LIT> ) == <NUM_LIT> ) ) ;


<s> StoreSDNode * St = cast < StoreSDNode > ( Op . getNode ( ) ) ; EVT MemVT = St -> getMemoryVT ( ) ; if ( MemVT == <STR_LIT> ) return LowerF128Store ( Op , DAG ) ; if ( MemVT == <STR_LIT> ) { SDValue Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , St -> getValue ( ) ) ; SDValue Chain = DAG . getStore ( St -> getChain ( ) , dl , Val , St -> getBasePtr ( ) , St -> getPointerInfo ( ) ,

St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) , St -> getAAInfo ( ) ) ;


<s> if ( ! Val . hasOneUse ( ) ) return false ; unsigned Opcode = Val -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { if ( Val -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; CanNegate = true ; MustBeFirst = false ; return true ; } if ( Depth > <NUM_LIT> ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { bool IsOR = Opcode == <STR_LIT> ; SDValue O0 = Val -> getOperand ( <NUM_LIT> ) ; SDValue O1 = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateL ; bool MustBeFirstL ; if ( ! canEmitConjunction ( O0 , CanNegateL , MustBeFirstL , IsOR , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; bool MustBeFirstR ; if ( ! canEmitConjunction ( O1 , CanNegateR , MustBeFirstR , IsOR , Depth + <NUM_LIT> ) )


<s> MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT>


<s> bool <ISA_LIT>16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue &


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( UncondBrOpc ) ) . addMBB ( TBB ) ; else BuildCondBr ( MBB , TBB , DL , Cond ) ; return <NUM_LIT>


<s> if ( SDValue Value = combineTruncateExtract ( SDLoc ( N ) , MemVT , SN -> getValue ( ) , DCI ) ) { DCI . AddToWorklist ( Value . getNode ( ) ) ; return DAG . getTruncStore ( SN -> getChain ( ) , SDLoc ( SN ) , Value , SN -> getBasePtr ( ) , SN -> getMemoryVT ( ) , SN -> getMemOperand ( ) ) ; } } if ( ! SN -> isTruncatingStore ( ) && ! SN -> isVolatile ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT , SN -> getMemOperand ( ) ) ; } return SDValue (


<s> return <NUM_LIT> ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return <NUM_LIT> ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return <NUM_LIT> ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return <NUM_LIT> ; case CPU_POWER8 : case CPU_POWER9


<s> static __inline__ double __fsel ( double x , double y , double z ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) { SDValue BAHi = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue BALo = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue BAGOTOffset = DAG . getBlockAddress ( BA , ValTy , true , GOTFlag ) ; BAGOTOffset = DAG . getNode ( <STR_LIT> , dl , ValTy , BAGOTOffset ) ; SDValue BALOOffset = DAG . getBlockAddress ( BA , ValTy , true , OFSTFlag ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , BAGOTOffset , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , ValTy , BALOOffset ) ; return DAG . getNode ( <STR_LIT> , dl , ValTy , Load , Lo


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __bsfq ( long long


<s> EVT VT = Sext -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue Add = Sext -> getOperand ( <NUM_LIT> ) ; if ( Add . getOpcode ( ) != <STR_LIT> || ! Add -> getFlags ( ) -> hasNoSignedWrap ( ) ) return SDValue ( ) ; auto * AddOp1 = dyn_cast < ConstantSDNode > ( Add . getOperand ( <NUM_LIT> ) ) ; if ( ! AddOp1 ) return SDValue ( ) ; bool HasLEAPotential = false ; for ( auto * User : Sext -> uses ( ) ) { if ( User -> getOpcode ( ) == <STR_LIT> || User -> getOpcode ( ) == <STR_LIT> ) { HasLEAPotential =


<s> const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( MergeMI ) : getLdStBaseOp ( I ) ; if ( ! MergeForward ) { for ( MachineOperand & MO : MergeMI -> operands ( ) ) if ( MO . isReg ( ) && MO . isKill ( ) ) { BuildMI ( * MergeMI -> getParent ( ) , MergeMI , MergeMI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: KILL ) , MO . getReg ( ) ) . addReg ( MO . getReg ( ) ) ; MO . setIsKill ( false ) ; } } MachineInstr * RtMI , * Rt2MI ; if ( getLdStOffsetOp ( I ) . getImm ( ) == getLdStOffsetOp ( MergeMI ) . getImm ( ) + OffsetStride ) { RtMI = MergeMI ; Rt2MI = I ; } else { RtMI = I ; Rt2MI = MergeMI ; } int OffsetImm = getLdStOffsetOp ( RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /= <NUM_LIT> ; } DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; if ( isNarrowLoad ( Opc ) ) { MachineInstr * RtNewDest = MergeForward ? I : MergeMI ; if ( ! Subtarget -> isLittleEndian ( ) ) std :: swap ( RtMI , Rt2MI ) ; MachineInstr * NewMemMI , * BitExtMI1 , * BitExtMI2 ; NewMemMI = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addOperand ( getLdStRegOp ( RtNewDest ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * MergeMI ) ) ; ( void ) NewMemMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printVectorListFourAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI

-> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> void LLVMInitializePowerPCAsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > A ( The<ISA_LIT>32Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > B ( The<ISA_LIT>64Target


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) ) { if ( N -> getOpcode ( ) == <STR_LIT> ) return performSetccAddFolding ( N , DAG ) ; return SDValue ( ) ; } SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( LHS . getOpcode ( ) != <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) || LHS . getOpcode ( ) != RHS . getOpcode ( ) ) return SDValue ( ) ; unsigned ExtType = LHS . getOpcode ( ) ; if ( isEssentiallyExtractSubvector ( LHS . getOperand ( <NUM_LIT> ) ) ) { RHS = tryExtendDUPToExtractHigh ( RHS . getOperand ( <NUM_LIT> ) ,


<s> const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = countTrailingZeros ( v ) ; uint32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; assert ( v != <NUM_LIT> && lsb < <NUM_LIT> && msb < <NUM_LIT> &&


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinCFINop ( bool Wide ) { if ( Wide ) emit<ISA_LIT>WinUnwindCode ( Win64EH :: UOP_WideNop , - <NUM_LIT> , <NUM_LIT> ) ; else emit<ISA_LIT>WinUnwindCode ( Win64EH :: UOP_Nop , -


<s> if ( next == NULL ) return false ; return INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) ==


<s> auto & Subtarget = MF . getSubtarget ( ) ; const auto & TII = Subtarget . getInstrInfo ( ) ; auto TRI = Subtarget . getRegisterInfo ( ) ; auto RBI = Subtarget . getRegBankInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; MachineInstr * FirstCmp = nullptr , * LastCmp = nullptr ; for ( auto & MI : instructionsWithoutDebug ( MBB . begin ( ) , MBB . end ( ) ) ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( ! FirstCmp ) FirstCmp = & MI ; else LastCmp = & MI ; } } LiveRegUnits LRU ( * MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ) ; LRU . addLiveOuts ( MBB ) ; bool NZCVDead = LRU . available ( <STR_LIT> ) ; bool InsideCmpRange = false ; for ( auto & II : instructionsWithoutDebug ( MBB . rbegin ( ) , MBB . rend ( ) ) ) { LRU . stepBackward ( II ) ; if ( LastCmp ) { if ( InsideCmpRange && & II == FirstCmp ) InsideCmpRange = false ; else if ( & II == LastCmp ) InsideCmpRange = true ; } bool NZCVDeadAtCurrInstr = LRU . available ( <STR_LIT> ) ; if ( NZCVDead && NZCVDeadAtCurrInstr && II . definesRegister ( <STR_LIT> ) ) { unsigned NewOpc = getNonFlagSettingVariant ( II . getOpcode ( ) ) ; int DeadNZCVIdx = II . findRegisterDefOperandIdx ( <STR_LIT>


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS &&

MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> return ( ! BYTES_BIG_ENDIAN ? PAD_UPWARD : ( ( mode == BLKmode ? ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && int_size_in_bytes ( type ) < ( PARM_BOUNDARY / BITS_PER_UNIT ) ) : ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY && GET_MODE_CLASS ( mode ) == MODE_INT ) )


<s> return ( vector unsigned int ) __builtin_altivec_vupklpx ( ( vector signed