<s> case <STR_LIT> : return R_<ISA_LIT>_64_PC32 ; case <STR_LIT> : return R_<ISA_LIT>_64_32 ; case <STR_LIT> : return R_<ISA_LIT>_64_32S ; case <STR_LIT> : return R_<ISA_LIT>_64_64 ; case <STR_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( MachineRelTy ) { case <STR_LIT> : return R_386_PC32 ; case <STR_LIT> : return R_386_32


<s> const MCInstrDesc & InstDesc = MCII -> get ( Inst . getOpcode ( ) ) ; return ( InstDesc . isConditionalBranch ( ) && ( AlignBranchType & <ISA_LIT>AlignBranchKind :: AlignBranchJcc ) ) || ( InstDesc . isUnconditionalBranch ( ) && ( AlignBranchType & <ISA_LIT>AlignBranchKind :: AlignBranchJmp ) ) || ( InstDesc . isCall ( ) && ( AlignBranchType & <ISA_LIT>AlignBranchKind :: AlignBranchCall )

) || ( InstDesc . isReturn ( ) && ( AlignBranchType & <ISA_LIT>AlignBranchKind :: AlignBranchRet ) ) || ( InstDesc . isIndirectBranch ( ) && ( AlignBranchType & <ISA_LIT>AlignBranchKind :: AlignBranchIndirect ) ) ;


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode


<s> EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ( SecondHalfOfMandatoryField & <NUM_LIT> ) >> <NUM_LIT> , <NUM_LIT> ) ; uint32_t GPRSaved = <NUM_LIT> ; unsigned GPRBegin = Subtarget -> is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned GPREnd = Subtarget -> is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned Reg = GPRBegin ; Reg <= GPREnd ; ++ Reg ) { if ( MRI . isPhysRegModified ( Reg ) ) { GPRSaved = GPREnd - Reg + <NUM_LIT> ; break ; } } SecondHalfOfMandatoryField |= ( GPRSaved << TracebackTable :: GPRSavedShift ) & TracebackTable :: GPRSavedMask ; GENBOOLCOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , HasVectorInfo ) ; GENBOOLCOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , HasExtensionTable ) ; GENVALUECOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , GPRSaved ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ( SecondHalfOfMandatoryField & <NUM_LIT> ) >> <NUM_LIT> , <NUM_LIT> ) ; uint32_t NumberOfFixedPara = FI -> getFixedParamNum ( ) ; SecondHalfOfMandatoryField |= ( NumberOfFixedPara << TracebackTable :: NumberOfFixedParmsShift ) & TracebackTable :: NumberOfFixedParmsMask ; GENVALUECOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , NumberOfFixedParms ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ( SecondHalfOfMandatoryField & <NUM_LIT> ) >> <NUM_LIT> , <NUM_LIT> ) ; SecondHalfOfMandatoryField |= TracebackTable :: HasParmsOnStackMask ; uint32_t NumberOfFPPara = FI -> getFloatingPointParamNum ( ) ; SecondHalfOfMandatoryField |= ( NumberOfFPPara << TracebackTable :: NumberOfFloatingPointParmsShift ) & TracebackTable :: NumberOfFloatingPointParmsMask ; GENVALUECOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , NumberOfFloatingPointParms ) ; GENBOOLCOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , HasParmsOnStack ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( SecondHalfOfMandatoryField & <NUM_LIT> , <NUM_LIT> ) ; if ( NumberOfFixedPara || NumberOfFPPara ) { assert ( ( SecondHalfOfMandatoryField & TracebackTable :: HasVectorInfoMask ) == <NUM_LIT> && <STR_LIT> ) ; uint32_t ParaType = FI -> getParameterType ( ) ; CommentOS << <STR_LIT> << XCOFF :: parseParmsType ( ParaType , NumberOfFixedPara + NumberOfFPPara ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ParaType , sizeof ( ParaType ) ) ; } OutStreamer -> AddComment ( <STR_LIT> ) ; if ( FirstHalfOfMandatoryField & TracebackTable :: HasTraceBackTableOffsetMask ) { MCSymbol * FuncSectSym = getObjFileLowering ( ) . getFunctionEntryPointSymbol ( & ( MF -> getFunction ( ) ) , TM ) ; OutStreamer -> emitAbsoluteSymbolDiff ( FuncEnd , FuncSectSym , <NUM_LIT> ) ; } if ( FirstHalfOfMandatoryField & TracebackTable :: IsInterruptHandlerMask ) report_fatal_error ( <STR_LIT> ) ; if ( FirstHalfOfMandatoryField & TracebackTable :: HasControlledStorageMask ) report_fatal_error ( <STR_LIT> ) ; if ( FirstHalfOfMandatoryField & TracebackTable :: IsFunctionNamePresentMask ) { StringRef Name = MF -> getName ( ) . substr ( <NUM_LIT> , INT16_MAX


<s> } if ( isThumbTwo ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! inITBlock ( ) || ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) != static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) ) return true ; if ( isThumbTwo ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! inITBlock ( ) ) ) return true ; if ( isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && ( Operands . size ( ) == <NUM_LIT> || Operands . size ( ) == <NUM_LIT> ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <STR_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) || ( Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) ) ) ) return true ; return false


<s> const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg ( ) ) ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( Subtarget .


<s> if ( Sym ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * Expr ; if ( Sym -> isVariable ( ) ) Expr = Sym -> getVariableValue ( ) ; else return false ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { <STR_LIT> Kind = ( <STR_LIT> ) RegKind ; const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const StringRef DefSymbol = Ref -> getSymbol ( ) . getName ( ) ; if ( DefSymbol . startswith ( <STR_LIT> ) ) { int RegNum = - <NUM_LIT> ; APInt IntVal ( <NUM_LIT> , - <NUM_LIT> ) ; if ( ! DefSymbol . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) ) RegNum = matchRegisterByNumber ( IntVal . getZExtValue ( ) , is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; else { switch ( Kind ) { case <STR_LIT> : case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) , FP_FORMAT_D ) ; break ; case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) , FP_FORMAT_S ) ; break ; case <STR_LIT> : case <STR_LIT> : default : RegNum = matchRegisterName ( DefSymbol . substr ( <NUM_LIT> ) , is<ISA_LIT>64 ( ) ) ; break ; } } if ( RegNum >


<s> if ( ! STI -> hasV5TEOps ( ) ) return false ; unsigned Scale = <NUM_LIT> ; unsigned Opcode = Op0 -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { if ( OffImm < <NUM_LIT> ) { if ( OffImm < - <NUM_LIT> ) return false ; }


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } MachineFrameInfo * MFI = MF


<s> if ( auto * E = dyn_cast < <ISA_LIT>MCExpr > ( X ) ) return getRegNo ( ) == E -> getRegNo ( ) ; return false


<s> void print<ISA_LIT>Operands ( OperandVector & Operands ) { for ( size_t i = <NUM_LIT> ; i < Operands


<s> if ( any_of ( Ins , [ ] ( const <STR_LIT> & IA ) { return IA . Flags . isByVal ( ) ; } ) ) return false ; if ( any_of ( Outs , [ ] ( const <STR_LIT> & OA ) { return OA . Flags . isByVal ( ) ; } ) ) return false ; if ( Caller . getCallingConv ( ) != CalleeCC && needStackSlotPassParameters ( Subtarget , Outs ) ) return false ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) return false ; if ( ! callsShareTOCBase ( & Caller , Callee

, getTargetMachine ( ) ) ) return false ;


<s> int modrm = ix86_get_modrm_for_rop ( insn , recog_data . operand , recog_data . n_operands , & opno0 , & opno1 ) ; if ( modrm < <NUM_LIT> || ! ix86_rop_should_change_byte_p ( modrm ) || opno0 == opno1 ) continue ; rtx oldreg = recog_data . operand [ opno1 ] ; preprocess_constraints ( insn ) ; const operand_alternative * alt = which_op_alt ( ) ; int i ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( i != opno1 && alt [ i ] . earlyclobber && reg_overlap_mentioned_p ( recog_data . operand [ i ] , oldreg ) ) break ; if ( i < recog_data . n_operands ) continue ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , REGNO

( oldreg ) , reg_class_names [ alt [ opno1 ] . cl ] ) ;


<s> if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> ,

<STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( ) ) ;


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm


<s> if ( ! TARGET_64BIT || cum -> call_abi == MS_ABI ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; save_area = frame_pointer_rtx ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ; bnd_reg = cum -> bnd_regno + cum -> force_bnd_pass ; if ( chkp_function_instrumented_p ( current_function_decl ) ) for ( i = cum -> regno ; i < max ; i ++ ) { rtx addr = plus_constant ( Pmode , save_area , i * UNITS_PER_WORD ) ; rtx ptr = gen_rtx_REG ( Pmode , x86_64_int_parameter_registers [ i ] ) ; rtx bounds ; if ( bnd_reg <= LAST_BND_REG ) bounds = gen_rtx_REG ( BNDmode , bnd_reg ) ; else { rtx ldx_addr = plus_constant ( Pmode , arg_pointer_rtx , ( LAST_BND_REG - bnd_reg ) * GET_MODE_SIZE ( Pmode ) ) ; bounds = gen_reg_rtx ( BNDmode ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_ldx ( bounds , ldx_addr , ptr ) : gen_bnd32_ldx ( bounds , ldx_addr , ptr ) ) ; } emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C )

) return <ISA_LIT>MaterializeGV ( GV ) ;


<s> unsigned AccReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const MCInstrDesc & MCID1 = TII -> get ( MulOpc ) ; const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm (


<s> BlockMask = VPTMaskValue :: TTTT ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , RDA , NewOpcode ) ; if ( VCMP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( BlockMask ) ; } finalizeBundle ( Block , MachineBasicBlock :: instr_iterator ( MIBuilder . getInstr ( ) ) , MBIter


<s> df_insn_rescan ( new_insn ) ; if ( dump_file ) { unsigned int new_uid = INSN_UID ( new_insn ) ; fprintf ( dump_file , <STR_LIT> , i , new_uid ) ; } df_insn_delete ( insn ) ; remove_insn ( insn


<s> Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( TID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT> ) ; Binary |= ShiftAmt


<s> rtx mips_loongson_ext2_prefetch_cookie ( rtx write , rtx ) { if ( INTVAL ( write ) == <NUM_LIT> ) return GEN_INT ( INTVAL ( write ) ) ; if ( INTVAL ( write ) == <NUM_LIT> ) return GEN_INT ( INTVAL


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned TyWidth ) { assert ( isPowerOf2_32 ( TyWidth ) &&


<s> imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) )


<s> for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( R -> getOperandUse ( <NUM_LIT> ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState ( isKill ) ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back ( MIB


<s> NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MIB ) ; MIB . addMBB ( NextBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII ->

get ( <STR_LIT> ) ) . addMBB ( DestBB ) ;


<s> DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << GetOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp ) return true ; } else { if ( BrOffset - DestOffset <= MaxDisp )


<s> fixTCReturn ( MF , MBB ) ; return ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } }


<s> if ( ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER (


<s> static SDValue LowerScalarVariableShift ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = getTargetVShiftUniformOpcode ( Opcode , false ) ; unsigned <ISA_LIT>OpcV = getTargetVShiftUniformOpcode ( Opcode , true ) ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , Subtarget , DAG ) ; } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [ j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ; } if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Op . getOpcode ( ) ) ) return DAG . getNode ( <ISA_LIT>OpcV , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> if ( LocalIdx < HalfEltsPerLane ) { DemandedLHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx + <NUM_LIT> ) ; DemandedLHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx + <NUM_LIT> ) ; } else { LocalIdx -= HalfEltsPerLane ; DemandedRHS . setBit ( LaneIdx + <NUM_LIT> * LocalIdx + <NUM_LIT> ) ; DemandedRHS . setBit ( LaneIdx + <NUM_LIT> *


<s> auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { llvm_unreachable ( <STR_LIT> )


<s> return Subtarget . is64Bit ( ) ? <STR_LIT>


<s> iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < <ISA_LIT>PLT0 > ( ( * it ) ) . getValue ( ) , <ISA_LIT>PLT0 :: EntrySize ) ; result += <ISA_LIT>PLT0 :: EntrySize ; ++ it ; <ISA_LIT>PLT1 * plt1 = <NUM_LIT> ; <ISA_LIT>PLT :: iterator ie = end (


<s> static void iq2000_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_CODE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE + GET_MODE_SIZE ( Pmode ) ) ; emit_move_insn ( mem , chain_value


<s> if ( offset == <NUM_LIT> ) return base_align ; return min ( base_align ,


<s> if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; } else { MI . setOpcode ( <STR_LIT>


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS , IsLittleEndian


<s> return ( vector signed short ) __builtin_altivec_vmulosb ( ( vector signed char ) a1


<s> machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > <NUM_LIT> ) return false ; if ( ! d -> perm [ <NUM_LIT> ] . is_constant ( & odd ) || ( odd != <NUM_LIT> && odd != <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , odd , <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , nelt + odd , <NUM_LIT> ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1


<s> return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> MachineBasicBlock :: iterator LastChange = MBB -> begin ( ) ; unsigned SmallestDef = TargetReg ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ) { MachineInstr * MI = & * I ; ++ I ; if ( MI -> isCopy ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) && ! MRI -> isReserved ( DefReg ) && ( TargetReg == DefReg || TRI -> isSuperRegister ( DefReg , TargetReg ) ) ) { DEBUG ( dbgs (


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Op . getOperand ( i * <NUM_LIT> + <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; return DAG . getNode ( <STR_LIT> ,


<s> SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) { if ( UndefElts [ i ] ) continue ; int VecIdx = Scale * Idx + i ; ShuffleMask [ VecIdx ] = EltBits [ i ] . isNullValue ( ) ? SM_SentinelZero : VecIdx ; } if ( SDValue Shuffle = combine<ISA_LIT>ShufflesRecursively ( { SrcVec } , <NUM_LIT> , SrcVec , ShuffleMask , { } , <NUM_LIT> , false , DAG , Subtarget ) )

return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shuffle , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ;


<s> const <ISA_LIT>TargetLowering * llvm :: create<ISA_LIT>SETargetLowering ( <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) { return new <ISA_LIT>SETargetLowering ( TM , STI


<s> case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( )


<s> while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - <NUM_LIT> ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; } } newsym = alloca ( <NUM_LIT> + strlen ( asmname ) + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ; return get_identifier_with_length ( newsym , sprintf ( newsym , <STR_LIT> , prefix , asmname , total / BITS_PER_UNIT


<s> if ( MI -> getOperand ( OpNo ) . isExpr ( ) && isa < MCBinaryExpr > ( MI -> getOperand ( OpNo ) . getExpr ( ) ) ) { O <<


<s> static DecodeStatus DecodeTS1AMI64 ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeCAS ( MI , insn , Address ,

Decoder , false , true , DecodeI64RegisterClass ) ;


<s> return interferenceGraphRetrieval [ virtReg ] ; } else { LiveRange * LR = new LiveRange ( virtReg ) ; interferenceGraph . insert ( LR ) ; interferenceGraphRetrieval [ virtReg ]


<s> static rtx legitimize_pe_coff_symbol ( rtx addr , bool inreg ) { if ( ! TARGET_PECOFF ) return NULL_RTX ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( addr ) ) return legitimize_dllimport_symbol ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx t = legitimize_dllimport_symbol ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ; } } if ( ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC ) return NULL_RTX ; if ( GET_CODE ( addr ) == SYMBOL_REF && ! is_imported_p ( addr ) && SYMBOL_REF_EXTERNAL_P ( addr ) && SYMBOL_REF_DECL ( addr ) ) return legitimize_pe_coff_extern_decl ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && ! is_imported_p ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) )

&& SYMBOL_REF_EXTERNAL_P ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) && SYMBOL_REF_DECL ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressELF ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ) { if ( NC -> getZExtValue ( ) * <NUM_LIT> == LdSt -> getMemoryVT ( ) . getSizeInBits ( )

) Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( )


<s> static DecodeStatus DecodeBranch16Target ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int BranchOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( BranchOffset > <NUM_LIT> ) BranchOffset = - <NUM_LIT> * ( <NUM_LIT> - BranchOffset ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0


<s> case Instruction :: Sub : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; auto * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits ( ) ) return false ; unsigned NumDstEls = DstTyL . first * DstTyL . second . getVectorNumElements ( ) ; unsigned NumSrcEls = SrcTyL . first * SrcTyL .


<s> bool isT2SOImmNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value ) == - <NUM_LIT> && <STR_LIT> ( ~


<s> if ( Use -> isMachineOpcode ( ) ) return <NUM_LIT> ; StoreSDNode * STN = cast < StoreSDNode > ( * Use ) ; unsigned MemVTSize = STN -> getMemoryVT ( ) . getSizeInBits ( ) ; if ( MemVTSize == <NUM_LIT> || Use . getOperandNo ( ) != <NUM_LIT> ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , MemVTSize ) ; continue ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Use . getOperandNo ( ) != <NUM_LIT> ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , <NUM_LIT> ) ; continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Use . getOperandNo ( ) != <NUM_LIT> ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , <NUM_LIT> ) ; continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Use . getOperandNo ( ) != <NUM_LIT> ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation ,


<s> return ( vector unsigned short ) __builtin_altivec_vpkswus ( ( vector signed int ) a1 , ( vector


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ;


<s> case <STR_LIT> : { StructType * ST = dyn_cast < StructType > ( ExpectedType ) ; if ( ! ST ) return nullptr ; unsigned NumElts = Inst -> arg_size ( ) - <NUM_LIT> ; if ( ST -> getNumElements ( ) != NumElts ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { if ( Inst -> getArgOperand ( i ) -> getType ( ) != ST -> getElementType ( i ) ) return nullptr ; } Value * Res = UndefValue :: get ( ExpectedType ) ; IRBuilder < > Builder ( Inst ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { Value * L = Inst -> getArgOperand ( i ) ; Res = Builder . CreateInsertValue ( Res , L , i ) ; } return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst -> getType ( ) == ExpectedType ) return


<s> unsigned GPReg = IsN64 ? <STR_LIT> : <STR_LIT> ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI


<s> static unsigned copyPhysRegOpcode_AVX512 ( unsigned & DestReg , unsigned & SrcReg ) { if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg

) || <STR_LIT> . contains ( SrcReg ) ) ) return <STR_LIT> ;


<s> const MCExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: CreateAdd ( Expr , OffsetExpr , Ctx ) ; } return MCOperand :: CreateExpr (


<s> op1 = force_reg ( Pmode , op1 ) ; if ( REG_POINTER ( op1 ) ) std :: swap ( op0 , op1 ) ; if ( virt_or_elim_regno_p ( REGNO ( op0 ) ) ) { base = expand_binop ( Pmode , add_optab , op0 , offset_rtx , NULL_RTX , true , OPTAB_DIRECT ) ; return gen_rtx_PLUS ( Pmode , base , op1 ) ; } base = expand_binop ( Pmode , add_optab , op0 , op1 , NULL_RTX , true , OPTAB_DIRECT ) ; x = gen_rtx_PLUS ( Pmode , base , offset_rtx ) ; } HOST_WIDE_INT size ; if ( GET_MODE_SIZE ( mode ) . is_constant ( & size ) ) { HOST_WIDE_INT base_offset = aarch64_anchor_offset ( offset , size , mode ) ; if ( base_offset != <NUM_LIT> ) { base = plus_constant ( Pmode , base , base_offset ) ; base = force_operand ( base , NULL_RTX ) ; return plus_constant ( Pmode , base ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget . isAIXABI ( ) ) return LowerGlobalTLSAddressAIX ( Op , DAG ) ; return LowerGlobalTLSAddressLinux ( Op , DAG


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> return ( __m128i ) __builtin_ia32_pmovsqw128_mask ( ( __v2di ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) -


<s> MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk = false ; break ; } } if ( ! OptOk ) continue ; for ( -- PrevI ; PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ; -- PrevI ) ; MachineInstr * LeaMI = PrevI ; if ( ( LeaMI -> getOpcode ( ) != <STR_LIT> && LeaMI -> getOpcode ( ) != <STR_LIT> ) || LeaMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) OptOk = false ; if ( ! OptOk ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> << * AddrMI << <STR_LIT> << * LeaMI ) ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock :: iterator MI_JT = MI ; MachineInstr * NewJTMI = BuildMI ( * MBB , MI_JT , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( MI -> getOperand ( JTOpIdx + <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ; unsigned NewSize = TII -> GetInstSizeInBytes ( NewJTMI ) ; unsigned OrigSize = TII -> GetInstSizeInBytes ( AddrMI ) ; OrigSize += TII -> GetInstSizeInBytes ( LeaMI ) ; OrigSize += TII -> GetInstSizeInBytes ( MI ) ; AddrMI -> eraseFromParent ( )


<s> if ( ! first_exit_blocks_p ) return false ; exit_bb = e -> src ; first_exit_blocks_p = false


<s> return ( __m128 ) __builtin_ia32_subss_mask_round ( ( __v4sf ) __A , ( __v4sf ) __B , ( __v4sf ) _mm_setzero_ps ( ) ,


<s> for ( const std :: pair < unsigned , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ; return


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == ( <NUM_LIT> << <NUM_LIT> ) ) ) return false ; else if ( isDSPControlWrite ) { Src = MI . getOperand ( <NUM_LIT> ) ; Dest = MI . getOperand ( <NUM_LIT> ) ; } else { Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( MI . isMoveReg (


<s> return __builtin_ia32_movmskps ( ( __v4sf


<s> const <ISA_LIT>TargetLowering * llvm :: create<ISA_LIT>16TargetLowering ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>16TargetLowering (


<s> if ( mutex -> depth == <NUM_LIT> ) { mutex -> owner = <NUM_LIT> ; if ( InterlockedDecrement ( & mutex -> counter ) >= <NUM_LIT> ) return ReleaseSemaphore ( mutex -> sema , <NUM_LIT> , NULL ) ? <NUM_LIT> : <NUM_LIT> ; } return


<s> ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Subtarget . isISA3_0 ( ) || ! Subtarget . is<ISA_LIT>64 ( ) || N0 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> || CN1 == nullptr || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue ExtsSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( ExtsSrc . getOpcode ( ) == <STR_LIT> && ExtsSrc . getOperand ( <NUM_LIT> ) . getOpcode ( ) ==


<s> order [ i ] = order [ i - <NUM_LIT> ] ; for ( j = <NUM_LIT> ; j < nops ; j ++ ) if ( unsorted_regs [ j ] > unsorted_regs [ order [ i - <NUM_LIT> ] ] && ( order [ i ] == order [ i - <NUM_LIT> ] || unsorted_regs [ j ] < unsorted_regs [ order [ i ] ] ) ) order [ i ] = j ; if ( order [ i ] == order [ i - <NUM_LIT> ] ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ i ] ] != unsorted_offsets [ order [ i - <NUM_LIT> ] ] + <NUM_LIT> ) return <NUM_LIT> ; } if ( base ) { * base = base_reg ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) regs [ i ] = unsorted_regs [ order [ i ] ] ; * load_offset = unsorted_offsets [ order [ <NUM_LIT> ] ] ; } if ( unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == <NUM_LIT> ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == - <NUM_LIT> ) return <NUM_LIT> ; if ( nops == <NUM_LIT> && arm_ld_sched ) return <NUM_LIT> ; return ( const_ok_for_arm ( unsorted_offsets [ order [ <NUM_LIT> ] ] ) || const_ok_for_arm ( - unsorted_offsets [ order [ <NUM_LIT> ] ] ) )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast

< ConstantSDNode > ( Op1 ) -> isNullValue ( ) ;


<s> return create<ISA_LIT>MachObjectWriter ( OS , true , MachO :: CPU_TYPE_<ISA_LIT>_64 ,


<s> get<ISA_LIT>BranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; } return MO . getImm ( ) >>


<s> switch ( T . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys ,

Ops , array_lengthof ( Ops ) , T , MMO ) ;


<s> bool result ; int code = GET_CODE ( x ) ; gcc_assert ( current_tune -> insn_extra_cost ) ; result = arm_rtx_costs_internal ( x , ( enum rtx_code ) code , ( enum rtx_code ) outer_code , current_tune -> insn_extra_cost , total , speed ) ; if ( dump_file && arm_verbose_cost ) { print_rtl_single ( dump_file , x ) ; fprintf ( dump_file , <STR_LIT> , speed ? <STR_LIT> : <STR_LIT> , * total , result ? <STR_LIT> : <STR_LIT> ) ; } return result


<s> EVT VT = Mul -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = performBuildShuffleExtendCombine ( Mul -> getOperand (


<s> if ( Fast ) * Fast = Subtarget -> isUnalignedMemAccessFast (


<s> ZeroReg = <STR_LIT> ; } if ( ! DstReg ) return false ; for ( MachineRegisterInfo :: use_iterator U = MRI -> use_begin ( DstReg ) , E = MRI -> use_end ( ) ; U != E ; ) { MachineOperand & MO = U . getOperand ( ) ; unsigned OpNo = U . getOperandNo ( ) ; MachineInstr * MI = MO . getParent ( ) ; ++ U ; if ( MI -> isPHI ( ) || MI -> isRegTiedToDefOperand ( OpNo ) || MI -> isPseudo ( ) ) continue ; MO . setReg ( ZeroReg ) ; } return true


<s> if ( GET_CODE ( x ) != LO_SUM ) return false ; if ( ! REG_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; if ( ! INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT>


<s> <ISA_LIT>MCAsmInfoGNUCOFF :: <ISA_LIT>MCAsmInfoGNUCOFF ( const Triple & Triple ) { assert ( Triple . isOSWindows ( ) && <STR_LIT> ) ; if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling :: WinEH ; } else { ExceptionsType = ExceptionHandling


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWin64 ( ) ) return & <STR_LIT> ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> SDLoc DL ( N ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op1 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op0 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; EVT SetCCType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 ) ; SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0 , Op0 , <STR_LIT> ) ; return DAG . getSelect ( DL , VT , IsOp0Nan , Op1


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) .


<s> DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ; } else { DefCycle = RegNo + <NUM_LIT> ; } return DefCycle


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) == <NUM_LIT> && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return false ; return reg_classes_intersect_p ( FP_REGS ,


<s> if ( isInt < <NUM_LIT> > ( Imm ) ) { AM . Disp = static_cast < int32_t > ( Imm ) ; AM . Base . Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; return ; } } } else if ( I . getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) { AM . Base . FrameIndex = I . getOperand ( <NUM_LIT> ) . getIndex


<s> static void mpushpop_str ( char * stringbuffer , const char * mnemonic , char * mask ) { if ( strlen ( mask ) > <NUM_LIT> || crx_interrupt_function_p ( ) ) sprintf ( stringbuffer , <STR_LIT> , mnemonic , mask ) ; else sprintf ( stringbuffer , <STR_LIT> , mnemonic , mask


<s> return ( int64x1_t ) __builtin_neon_vreinterpretdiv4hi ( (


<s> int words = ia64_function_arg_words ( arg . type , arg . mode ) ; int offset = ia64_function_arg_offset ( cum , arg . type , words ) ; if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return <NUM_LIT> ; if ( words + cum -> words +

offset <= MAX_ARGUMENT_SLOTS ) return <NUM_LIT> ;


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { if ( UpdateMF ) MFI . setStackSize ( <NUM_LIT> ) ; return <NUM_LIT>


<s> if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( )


<s> if ( isSingleInputShuffleMask ( Mask ) ) { V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Blend ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL


<s> VariantKind getKind ( ) const { return Kind


<s> return parseRegister ( Operands , RegGR , <STR_LIT> , <ISA_LIT>Operand


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL ,


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getTLSCallPreservedMask ( ) const { if ( TT . isOSDarwin ( ) ) return CSR_<ISA_LIT>_TLS_Darwin_RegMask ; assert ( TT . isOSBinFormatELF ( ) && <STR_LIT> ) ; return


<s> if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT LongTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : LongTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT ,


<s> case GTU : std :: swap ( op0 , op1 ) ; cond = swap_condition ( cond ) ; break ; default : gcc_unreachable ( ) ; } mips_emit_binary ( cond , dest , op0 , op1 ) ; if ( negate ) emit_move_insn ( dest , gen_rtx_NOT ( GET_MODE ( dest ) , dest ) ) ; break ; case E_V4SFmode : case E_V2DFmode : switch ( cond ) { case UNORDERED : case ORDERED : case EQ : case NE : case UNEQ : case UNLE : case UNLT : break ; case LTGT : cond = NE ; break ; case UNGE : cond = UNLE ; std :: swap ( op0 , op1 ) ; break ; case UNGT : cond = UNLT ; std :: swap ( op0 , op1 ) ; break ; case LE : unspec = UNSPEC_MSA_FSLE ; break ; case LT : unspec = UNSPEC_MSA_FSLT ; break ; case GE : unspec = UNSPEC_MSA_FSLE ; std :: swap ( op0 , op1 ) ; break ; case GT : unspec = UNSPEC_MSA_FSLT ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( unspec < <NUM_LIT> ) mips_emit_binary ( cond , dest , op0 , op1 ) ; else { rtx x = gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( <NUM_LIT> , op0 , op1


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { IsPIC = isPIC


<s> bits = real_to_target ( NULL , & r , HFmode ) ; if ( WORDS_BIG_ENDIAN ) assemble_zeros ( <NUM_LIT> ) ; assemble_integer ( GEN_INT ( bits ) , <NUM_LIT> , BITS_PER_WORD , <NUM_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemDisp ( ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Observer . changedInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate (

CmpInst :: getSwappedPredicate ( Pred ) ) ;


<s> else if ( Align & <NUM_LIT> ) Repeats . AVT = <STR_LIT> ; else Repeats . AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( Repeats . BytesLeft ( ) > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) { Repeats . AVT = <STR_LIT> ; } } bool Use64BitRegs = Subtarget . isTarget64BitLP64 ( ) ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , DAG . getIntPtrConstant ( Repeats . Count ( ) , dl ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( Repeats . AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( Repeats . BytesLeft ( ) ) { unsigned Offset = Repeats . Size - Repeats .


<s> void mips_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; compute_frame_size ( get_frame_size ( ) ) ; gcc_assert ( ( cfun -> machine -> frame . mask >> <NUM_LIT> ) & <NUM_LIT>


<s> if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Idx = <NUM_LIT> ; const TargetRegisterClass * RC32 = TLI . getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; bool is32Bit = TLI . getValueType ( I -> getType ( ) )


<s> if ( EltSize < <NUM_LIT> || EltSize > <NUM_LIT> ) return false ; Register IdxReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( IdxReg , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value . getSExtValue ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; if ( VecSize < <NUM_LIT> ) { MachineInstr * ScalarToVec = emitScalarToVector ( VecSize , & <STR_LIT> , SrcReg , MIB ) ; if ( ! ScalarToVec ) return false ; SrcReg = ScalarToVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineInstr * InsMI = emitLaneInsert ( None , SrcReg , EltReg , LaneIdx , EltRB , MIB ) ; if ( VecSize < <NUM_LIT> ) { Register DemoteVec = InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = getMinClassForRegBank ( * RBI . getRegBank ( DemoteVec , MRI , TRI ) , VecSize ) ; if ( RC != & <STR_LIT> && RC != & <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SubReg = <NUM_LIT> ; if ( ! getSubRegForClass ( RC , TRI , SubReg ) ) return false ; if ( SubReg != <STR_LIT> && SubReg != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VecSize << <STR_LIT> ) ; return false ; } MIB . buildInstr ( TargetOpcode :: COPY , { DstReg } , { } ) . addReg ( DemoteVec , <NUM_LIT> , SubReg ) ; RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ; } else { InsMI -> getOperand ( <NUM_LIT> ) . setReg (


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setAvailableFeatures ( AssemblerOptions . front ( ) -> getFeatures ( ) ) ; AssemblerOptions . back ( ) -> setFeatures ( AssemblerOptions . front ( ) -> getFeatures ( ) ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>0 ( ) ; return false


<s> rtx_insn * insn = emit_insn ( gen_window_save ( increment ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ) ) ; add_reg_note ( insn , REG_CFA_WINDOW_SAVE , const0_rtx ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode

, hard_frame_pointer_rtx , INCOMING_FRAME_SP_OFFSET ) ) ;


<s> if ( P . hasDSP ( ) ) ASESet |= <STR_LIT> ; if ( P . hasDSPR2 ( ) ) ASESet |= <STR_LIT> ; if ( P . hasMSA ( ) ) ASESet |= <STR_LIT> ; if ( P . inMicro<ISA_LIT>Mode ( ) ) ASESet


<s> gcc_assert ( REG_P ( slot ) ) ; res = gen_reg_rtx ( BNDmode


<s> if ( DisableBackwardSearch ) return false ; RegDefsUses RegDU ( * MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MemDefsUses MemDU ( * TM . getDataLayout ( ) , MBB . getParent ( ) -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( * Slot ) ; if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB , std :: next ( Filler ) . base ( ) ) ; MIBundleBuilder ( MBB , Slot , std :: next ( Slot , <NUM_LIT> ) ) ; ++


<s> SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Log2b = Log2_32 ( VT . getSizeInBits ( ) ) ; SDLoc dl ( Op ) ; SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Cmp -> getOperand ( <NUM_LIT> ) ) ; SDValue Trunc = DAG . getZExtOrTrunc ( Clz , dl , <STR_LIT> ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trunc , DAG . getConstant ( Log2b , dl , <STR_LIT> ) ) ; return


<s> OutStreamer -> EmitSymbolAttribute ( Stub . second . getPointer ( ) , MCSA_IndirectSymbol ) ; const char HltInsts [ ] = <STR_LIT> ; OutStreamer -> EmitBytes ( StringRef ( HltInsts , <NUM_LIT> ) ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub .


<s> if ( opts -> x_align_loops <= <NUM_LIT> ) opts -> x_align_loops = aarch64_tune_params . loop_align ; if ( opts -> x_align_jumps <= <NUM_LIT> ) opts -> x_align_jumps = aarch64_tune_params . jump_align ; if ( opts -> x_align_functions <= <NUM_LIT> ) opts -> x_align_functions = aarch64_tune_params . function_align ; } if ( opts -> x_nopcrelative_literal_loads == <NUM_LIT> ) aarch64_nopcrelative_literal_loads = false ; if ( opts -> x_nopcrelative_literal_loads == <NUM_LIT> && ! TARGET_FIX_ERR_A53_843419 ) aarch64_nopcrelative_literal_loads


<s> static rtx loongarch_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! IMM12_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand (


<s> SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC ) ; if ( ! EFLAGS ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> const <ISA_LIT>InstrInfo * getInstrInfo


<s> SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { V0 , SubReg0 , V1 , SubReg1 ,


<s> static bool isHighReg ( unsigned int Reg ) { if ( <STR_LIT> . contains ( Reg ) ) return true ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; return


<s> std :: unique_ptr < PBQPRAConstraint > <ISA_LIT>Subtarget :: getCustomPBQPConstraints ( ) const { if ( ! isCortexA57 ( ) ) return nullptr ; return llvm :: make_unique <


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( *


<s> bool <ISA_LIT>MCInstLower :: lowerLongBranch ( const MachineInstr * MI , MCInst & OutMI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : lowerLongBranchLUi ( MI , OutMI ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_LO ) ; return true ; case <STR_LIT> : unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_HI ) ; else if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_LO ) ; else report_fatal_error ( <STR_LIT> ) ; return


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = getDataLayout ( ) -> getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . vol = true ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy ->


<s> bool mips_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift =


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI ::


<s> vpminq_u8 ( uint8x16_t a , uint8x16_t b ) { return ( uint8x16_t ) __builtin_aarch64_uminpv16qi ( ( int8x16_t ) a , ( int8x16_t


<s> const TargetRegisterClass * QPRs = TRI . getRegClass ( <STR_LIT> ) ; SetVector < MachineInstr * > FalseLanesUnknown ; SmallPtrSet < MachineInstr * , <NUM_LIT> > FalseLanesZero ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Predicated ; MachineBasicBlock * Header = ML . getHeader ( ) ; for ( auto & MI : * Header ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; bool isPredicated = isVectorPredicated ( & MI ) ; bool retainsOrReduces = retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ; if ( isPredicated ) Predicated . insert ( & MI ) ; if ( producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) FalseLanesZero . insert ( & MI ) ; else if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; else if ( ! isPredicated && retainsOrReduces ) return false ; else if ( ! isPredicated ) FalseLanesUnknown . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > NonPredicated ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; NonPredicated . insert ( MI ) ; break ; } } if ( ! NonPredicated . contains ( MI ) ) Predicated . insert ( MI ) ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveOutMIs ; SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ; ML . getExitBlocks ( ExitBlocks ) ; assert ( ML . getNumBlocks ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ExitBlocks . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock * ExitBB = ExitBlocks . front (


<s> static const TargetRegisterClass * getRegClassForTypeOnBank ( LLT Ty , const RegisterBank & RB , const RegisterBankInfo & RBI , bool GetAllRegSet = false ) { if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; return


<s> TargetJITInfo :: StubLayout <ISA_LIT>JITInfo :: getStubLayout (


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : return AP . getSymbol ( MO . getGlobal ( ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return AP . GetCPISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return AP . GetJTISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_BlockAddress : return AP . GetBlockAddressSymbol ( MO . getBlockAddress


<s> if ( ! NegN2 ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , false , true , false ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ,

NegN2 , N -> getOperand ( <NUM_LIT> ) ) ;


<s> } else ATS . emitTextAttribute ( <STR_LIT> , CPUString ) ; } ATS . emitAttribute ( <STR_LIT> , getArchForCPU ( CPUString , & STI ) ) ; if ( STI . hasV7Ops ( ) || isV8M ( & STI ) ) { if ( STI . isAClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , STI . has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( isV8M ( & STI ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( STI . hasNEON ( ) ) { if ( STI . hasFP<ISA_LIT>v8 ( ) ) { if ( STI . hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , STI . hasV8_1aOps ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? ( STI . isFPOnlySP ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? ( STI . isFPOnlySP ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasVFP3 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? ( STI . isFPOnlySP ( ) ? ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) ) : ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> ,


<s> static __inline qword si_ai ( qword a , int b ) { return ( ( qword ) ( vec_add ( ( vec_int4 ) ( a ) , vec_splat ( (

vec_int4 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static int I = <NUM_LIT> ; if ( Out . hasRawTextSupport ( ) ) { return false ; } static bool RecurseGuard = false ; if ( RecurseGuard ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( ( I == <NUM_LIT> ) && ( SaveCount == <NUM_LIT> ) ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; } } if ( I < SaveCount ) { assert ( I < MaxSaved && <STR_LIT> ) ; Saved [ I ++ ] = Inst ; if ( I < SaveCount ) return true ; } assert ( I == SaveCount && SaveCount > <NUM_LIT> && <STR_LIT> ) ; RecurseGuard = true ; switch ( Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( I , Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardCall ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardJmp ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitGuardReturn ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitGuardLoadOrStore ( I , Saved , Out ) ; break ; case <STR_LIT> : EmitGuardLoadOrStoreTst ( I , Saved , Out ) ; break ; case


<s> isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; if ( isThumb1 ) { delete RS ; return false ; } bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = *


<s> break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } if ( NumBits > <NUM_LIT> ) { MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset = - ImmedOffset ; else ImmedOffset |= <NUM_LIT> << NumBits ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset = - ImmedOffset ; else ImmedOffset |= <NUM_LIT>


<s> dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( GET_CODE ( dest ) == JUMP_INSN && GET_CODE ( PATTERN (


<s> Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_SecRel_2 : return <NUM_LIT> ; case FK_SecRel_4 : return


<s> static int mips_sched_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED ,


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SType


<s> SDValue Ops [ ] = { GA , Reg } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , VT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , false , true


<s> bool mips_cannot_change_mode_class ( enum machine_mode from , enum machine_mode to , enum reg_class class ) { if ( MIN ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) <= UNITS_PER_WORD && MAX ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) > UNITS_PER_WORD ) { if ( TARGET_BIG_ENDIAN ) { if ( FP_INC > <NUM_LIT> && reg_classes_intersect_p ( FP_REGS , class ) ) return true ; } else { if ( reg_classes_intersect_p ( ACC_REGS , class ) ) return


<s> Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue


<s> unsigned j , e = d -> perm [ i ] ; unsigned which = ( e >= nelt ) ; if ( e >= nelt ) e -= nelt ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ which ] [ i * eltsz + j ] = GEN_INT ( e * eltsz + j ) ; rperm [ <NUM_LIT> - which ] [ i * eltsz + j ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; l = gen_reg_rtx ( V16QImode ) ; op = gen_lowpart ( V16QImode , d -> op0 ) ; emit_insn ( gen_ssse3_pshufbv16qi3 ( l , op ,


<s> if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT>


<s> unsigned Idx ; for ( Idx = <NUM_LIT> ; Idx != array_lengthof ( LdStNInstInfo ) ; ++ Idx ) if ( LdStNInstInfo [ Idx ] . Opcode == Opcode


<s> for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ;

I != E ; ++ I ) if ( * I == NextBB ) return true ;


<s> MVT InnerVT = V . getSimpleValueType ( ) ; MVT InnerEltVT = InnerVT . getVectorElementType ( ) ; if ( OpEltVT == InnerEltVT ) { assert ( OpVT == InnerVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V . getOperand ( <NUM_LIT> ) ) ; } if ( InnerEltVT . getSizeInBits ( ) < InputBits ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( OpVT , V ) ) ; } if ( Opcode == <STR_LIT> && V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) == InputBits ) { SDValue ExtractedV = V . getOperand ( <NUM_LIT> ) ; SDValue OrigV = ExtractedV . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( ExtractedV . getOperand ( <NUM_LIT> ) ) ) { MVT OrigVT = OrigV . getSimpleValueType ( ) ; if ( OrigVT . getSizeInBits ( ) > OpVT . getSizeInBits ( ) ) { int Ratio = OrigVT . getSizeInBits ( ) / OpVT . getSizeInBits ( ) ; OrigVT = <STR_LIT> ( OrigVT . getVectorElementType ( ) , OrigVT . getVectorNumElements ( ) / Ratio ) ; OrigV = DAG . getNode ( <STR_LIT> , DL , OrigVT , OrigV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } Op = DAG . getBitcast ( OpVT , OrigV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } } return SDValue (


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return -


<s> break ; default : return Optional < BlockBRNZ > ( ) ; } BlockBRNZ Desc ; Desc . IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; Desc . Regs . push_back ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Desc . Zero = Zero ; Desc . Nonzero = Nonzero ; const Register & Reg0 = Desc . Regs [ <NUM_LIT> ] ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> isPHI ( ) ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg0 ) { unsigned NumOperands = MI -> getNumOperands (


<s> static unsigned translateShiftImm ( unsigned imm ) { if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return imm


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static bool convert64i32to64ri8 ( MCInst & Inst , unsigned Opcode , bool isCmp = false ) { if ( ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || ! isImmSExti64i8Value ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) return false ; return convertToSExti8 ( Inst , Opcode


<s> if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) || ! isPredicated ( DepMI )


<s> unsigned <ISA_LIT>16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI


<s> return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && M16_REG_P ( REGNO ( addr . reg ) ) && offset_predicate ( addr .


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O


<s> OptIncDec = ! ST . slowIncDec ( ) || Func . getFunction ( ) . optForMinSize ( ) ; OptLEA = ST . LEAusesAG ( ) || IsSlowLEA || IsSlow3OpsLEA ; if ( ! OptLEA && ! OptIncDec ) return false ; TSM . init ( & Func . getSubtarget ( ) ) ; TII = ST . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> if ( CPUString != <STR_LIT> && CPUString != <STR_LIT> ) ATS . emitTextAttribute ( <STR_LIT> , CPUString ) ; ATS . emitAttribute ( <STR_LIT> , getArchForCPU ( CPUString , Subtarget ) ) ; if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isAClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> ,


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> assert ( isParsingInlineAsm ( ) && <STR_LIT> ) ; Val = nullptr ; StringRef LineBuf ( Identifier . data ( ) ) ; void * Result = SemaCallback -> LookupInlineAsmIdentifier ( LineBuf , Info , IsUnevaluatedOperand ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; assert ( End . getPointer ( ) <= EndPtr


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; else if ( TheTriple . isWindowsItaniumEnvironment ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoGNU ( ) ; else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; unsigned Reg = MRI . getDwarfRegNum


<s> return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? !


<s> } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerVectorShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerVectorShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Unpack ; if ( ! IsBlendSupported && Subtarget . hasSSSE3 ( ) ) { bool V1InUse , V2InUse ; return lowerVectorShuffleAsBlendOfPSHUFBs ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable


<s> SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; if ( Subtarget . hasAVX512 ( ) ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Amt , EltSizeInBits , UndefElts , EltBits ) ) { if ( ! UndefElts && llvm :: all_of ( EltBits , [ EltBits ] ( APInt & V ) { return EltBits [ <NUM_LIT> ] == V ; } ) ) { unsigned Op = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; uint64_t RotateAmt = EltBits [ <NUM_LIT> ] . urem ( EltSizeInBits ) ; return DAG . getNode ( Op , DL , VT , R , DAG . getConstant ( RotateAmt , DL , <STR_LIT> ) ) ; } } return Op ; } assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( Subtarget . hasXOP ( ) && <STR_LIT> ) ; assert ( ( Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) ) return Lower256IntArith ( Op , DAG ) ; assert ( VT . is128BitVector ( ) && <STR_LIT>


<s> tree id ; if ( deferred_plabels == <NUM_LIT> ) deferred_plabels = ( struct deferred_plabel * ) ggc_alloc ( sizeof ( struct deferred_plabel ) ) ; else deferred_plabels = ( struct deferred_plabel * ) ggc_realloc ( deferred_plabels , ( ( n_deferred_plabels + <NUM_LIT> ) * sizeof ( struct deferred_plabel ) ) ) ; i = n_deferred_plabels ++ ; deferred_plabels [ i ] . internal_label = gen_label_rtx ( ) ; deferred_plabels [ i ] . symbol = symbol ; id = maybe_get_identifier ( targetm . strip_name_encoding ( fname ) ) ; if ( id ) mark_referenced