<s> static unsigned toCallerWindow ( unsigned Reg ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return Reg - <STR_LIT> + <STR_LIT> ; return


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA ==


<s> return __builtin_aarch64_ushll_nv4hi_uus ( __a ,


<s> RegDU . setUnallocatableRegs ( * MBB . getParent ( ) ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) , RegDU , * IM , Filler ) ) return false ; insertDelayFiller ( Filler , BrMap ) ; addLiveInRegs ( Filler , * SuccBB ) ; Filler -> eraseFromParent (


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .

addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ;


<s> last = adjust_address ( op , QImode , width / BITS_PER_UNIT - <NUM_LIT> ) ; if ( TARGET_BIG_ENDIAN ) * left = first , * right = last ; else * left = last , * right = first ; return


<s> int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; uint64_t encoding = <STR_LIT> (


<s> return ; } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , <NUM_LIT> ) ; accum_rtx_p = & XEXP ( fma_rtx , <NUM_LIT> ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , <NUM_LIT> ) ; if ( accum_rtx_p != chain -> loc ) continue ; if ( this -> get_fma_node ( chain -> insn ) ) continue ; child_fma = new fma_node ( node , chain ) ; node -> add_child ( child_fma


<s> return <ISA_LIT>Lowering . SelectAddressRegRegOnly ( N , Base , Index ,


<s> int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ int64_t ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) { SDLoc DL ( Ptr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , DL , Ptr . getValueType ( ) ) ) ; } int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask (


<s> rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { crtl -> stack_realign_needed = stack_realign ; crtl -> stack_realign_finalized = true


<s> if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { APInt MKZ , MKO ; CurDAG -> computeKnownBits ( Op1 . getOperand ( <NUM_LIT> ) , MKZ , MKO ) ; bool CanFoldMask = InsertMask == MKO . getZExtValue ( ) ; unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && CanFoldMask && isInt32Immediate ( Op1

. getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) {


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn ,


<s> Function * F = BB -> getParent ( ) ; IRBuilder < > Builder ( & F -> getEntryBlock ( ) . front ( ) ) ; const DataLayout & DL = M -> getDataLayout ( ) ; unsigned AllocaAS = DL . getAllocaAddrSpace ( ) ; Type * V256I32Ty = VectorType :: get ( Builder . getInt32Ty ( ) , <NUM_LIT> , false ) ; AllocaInst * AllocaRes = new AllocaInst ( V256I32Ty , AllocaAS , <STR_LIT> , & F -> getEntryBlock ( ) . front ( ) ) ; BasicBlock :: iterator Iter = AllocaRes -> getIterator ( ) ; ++ Iter ; Builder . SetInsertPoint ( & * Iter ) ; Value * I8Ptr = Builder . CreateBitCast ( AllocaRes , Builder . getInt8PtrTy ( ) ) ; return I8Ptr


<s> FunctionPass * llvm :: create<ISA_LIT>NaClRewritePass ( ) { return new <ISA_LIT>NaClRewritePass (


<s> bool <ISA_LIT>LegalizerInfo :: legalizeIntrinsic ( LegalizerHelper & Helper , MachineInstr & MI ) const { return


<s> return getSubtargetImpl ( ) -> getSelectionDAGInfo ( )


<s> static int mips_fp_div_cost ( machine_mode mode


<s> tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; gcc_assert ( SYMBOL_REF_LOCAL_P ( funexp ) ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function ( ) ; reload_completed =


<s> if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , <NUM_LIT> ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source


<s> fma_node * func_fma_steering :: get_fma_node ( rtx_insn * insn ) { fma_node * * fma_slot ; fma_slot = this -> m_insn_fma_head_map -> get (


<s> for ( const char * const * I = ABICalls ; I != <NUM_LIT> ; ++ I ) if ( strcmp ( CalleeName , * I ) == <NUM_LIT> ) return true ; return false


<s> if ( TARGET_DEBUG_STACK ) debug_stack_info ( info ) ; if ( info -> first_fp_reg_save < <NUM_LIT> && ! TARGET_MACHO && ! TARGET_ELF ) { char * name ; int regno = info -> first_fp_reg_save - <NUM_LIT> ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) == <NUM_LIT> ) { bool lr = ( info -> savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR ) != <NUM_LIT> ; int sel = SAVRES_SAVE | SAVRES_FPR | ( lr ? SAVRES_LR : <NUM_LIT> ) ; name = rs6000_savres_routine_name ( regno , sel ) ; fprintf ( file , <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( LoExpr ) ) ; getStreamer ( ) . EmitInstruction (


<s> SDLoc dl ( Op . getNode ( ) ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Insert128BitVector ( Vec , SubVec ,


<s> static bool isFunctionGlobalAddress ( SDValue Callee ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee )


<s> static llvm :: once_flag InitializeRegisterBankFlag ; static auto InitializeRegisterBankOnce = [ & ] ( ) { const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass


<s> if ( ! attrs ) return ; if ( ! lookup_attribute ( <STR_LIT> , attrs ) && ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( node ) ) ) { if ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , attrs ) ; else if ( lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) ) { tree * tail ; for ( tail = attributes ; attrs ; attrs =


<s> static void ia64_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size , int bs_size ) { rtx r2 = gen_rtx_REG ( Pmode , GR_REG ( <NUM_LIT> ) ) ; rtx r3 = gen_rtx_REG ( Pmode , GR_REG ( <NUM_LIT> ) ) ; rtx p6 = gen_rtx_REG ( BImode , PR_REG ( <NUM_LIT> ) ) ; emit_insn ( gen_bsp_value ( r3 ) ) ; emit_move_insn ( r2 , GEN_INT ( - ( first + size ) ) ) ; emit_insn ( gen_rtx_SET ( p6 , gen_rtx_fmt_ee ( LTU , BImode , r3 , stack_pointer_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( r3 , plus_constant ( Pmode , r3 , <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( r2 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , r2 ) ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_fmt_ee ( NE , VOIDmode , p6 , const0_rtx ) , gen_rtx_SET ( p6 , gen_rtx_fmt_ee ( GEU , BImode , r3 , r2 ) ) ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_ZERO_EXTRACT ( DImode , r3 , GEN_INT ( <NUM_LIT> ) , const0_rtx ) , const0_rtx ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_fmt_ee ( NE , VOIDmode , p6 , const0_rtx ) , gen_rtx_TRAP_IF ( VOIDmode , const1_rtx , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( bs_size > <NUM_LIT> ) emit_stack_probe ( r3 ) ; if ( size == <NUM_LIT> ) ; else if ( size <= PROBE_INTERVAL ) emit_stack_probe ( r2 ) ; else if ( size <= <NUM_LIT> * PROBE_INTERVAL ) { HOST_WIDE_INT i


<s> if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , SSatVal ) ; if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG , Subtarget ) ; if ( Mid ) return truncateVectorWithPACK ( <STR_LIT> , VT , Mid , DL , DAG , Subtarget ) ; } else if ( SVT == <STR_LIT> || Subtarget . hasSSE41 ( ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL , DAG , Subtarget ) ; } } return SDValue (


<s> if ( ! Subtarget -> useConstIslands ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs (


<s> if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent


<s> SDValue Extract = DAG . getNode ( <STR_LIT> , dl , MemVT , Load , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getNode ( ExtOpcode , dl , Op . getValueType ( ) , Extract ) ; } MVT ExtVT = <STR_LIT> ( VT . getScalarType ( ) , <NUM_LIT> ) ; SDValue ExtVec = DAG . getNode ( ExtOpcode , dl , ExtVT , Load ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDValue Load = DAG . getLoad ( MemVT , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getMemOperand ( ) ) ; assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( ExtOpcode , dl , Op . getValueType ( ) , Load ) ; } if ( NumElts <= <NUM_LIT> ) { SDValue Load = DAG . getLoad ( <STR_LIT> , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getMemOperand ( ) ) ; assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; SDValue BitVec = DAG . getBitcast ( <STR_LIT> , Load ) ; if ( NumElts == <NUM_LIT> ) return DAG . getNode ( ExtOpcode , dl , VT , BitVec ) ; if ( Subtarget . hasVLX


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xrstor64 ( void * __P , long long __M ) { return __builtin_ia32_xrstor64 ( __P ,


<s> NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; if ( ! FuncInfo -> isLeafProc ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MaybeAlign RuntimeAlign = NeedsStackRealignment ? MaybeAlign ( MFI . getMaxAlign ( ) ) : None ; assert ( ( RuntimeAlign == None || ! FuncInfo -> isLeafProc ( ) ) && <STR_LIT> ) ; emitSPAdjustment ( MF , MBB , MBBI , - ( int64_t ) NumBytes , RuntimeAlign ) ; if ( hasBP (


<s> extern __inline __m128d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_i64gather_pd ( __m128d src , double const * base , __m128i index , __m128d mask , const int scale ) { return ( __m128d ) __builtin_ia32_gatherdiv2df ( ( __v2df ) src , base , ( __v2di ) index , ( __v2df )


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: isITBlockTerminator ( MCInst & Inst ) const { const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; if ( MCID . isTerminator ( ) || ( MCID . isCall ( ) && Inst . getOpcode ( ) != <STR_LIT> ) || MCID . isReturn (

) || MCID . isBranch ( ) || MCID . isIndirectBranch ( ) ) return true ;


<s> Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } unsigned Opcode = Node -> getOpcode ( ) ; SDNode * ResNode = nullptr ; switch ( Opcode ) { case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; goto or_xor ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; or_xor : if ( ! ResNode && Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) if ( auto * Op1 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Val = Op1 -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) ) Node = splitLargeImmediate ( Opcode , Node , Node -> getOperand ( <NUM_LIT> ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! ResNode ) ResNode = tryRISBGZero ( Node ) ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid .


<s> if ( MaskNode . getOpcode ( ) == <STR_LIT> && MaskNode . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; unsigned ElementSplit = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; SDValue MaskOp = MaskNode . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskOp ) ) { SplitElementToMask ( CN -> getAPIntValue ( ) ) ; RawMask . append ( ( VT . getVectorNumElements ( ) - <NUM_LIT> ) * ElementSplit , <NUM_LIT> ) ; return true ; } return false ; } if ( MaskNode . getOpcode ( ) != <STR_LIT> ) return false ; if ( llvm :: all_of ( MaskNode -> ops ( ) , <STR_LIT> ) ) { RawMask . append ( VT . getSizeInBits ( ) / MaskEltSizeInBits , <NUM_LIT> ) ; return true ; } if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; for ( SDValue Op : MaskNode -> ops ( ) ) { if ( auto * CN = dyn_cast < ConstantSDNode > ( Op . getNode (

) ) ) SplitElementToMask ( CN -> getAPIntValue ( ) ) ;


<s> bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = PushPopMIs . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = PushPopMIs [ i ] ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add

( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , OpEltSizeInBits ) && ! HasAnyUndefs && SplatValue . getBitWidth ( ) == OpEltSizeInBits ) return DAG . getConstant ( SplatValue , DL , DstVT ) ; } return SDValue ( ) ; } ; bool Widen = ! ( Subtarget . hasVLX ( ) || VT . is512BitVector ( ) ) ; MVT DstVT = VT ; if ( Widen ) DstVT = <STR_LIT> ( SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SmallVector < SDValue > SrcOps ( Ops . begin ( ) , Ops . end ( ) ) ; for ( SDValue & Op : SrcOps ) { MVT OpVT = Op .


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmfaa ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < ThumbLETargetMachine > A (


<s> unsigned Mask = VT . getVectorNumElements ( ) - <NUM_LIT> ; if ( Index <= Mask ) return Op ; } MVT IntVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT IntVecVT = <STR_LIT> ( IntVT , VT . getVectorNumElements ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , IntVecVT , DAG . getNode ( <STR_LIT> , DL , IntVecVT , Op0 ) , DAG . getNode

( <STR_LIT> , DL , IntVT , Op1 ) , Op2 ) ;


<s> Op -> Cop . Val = CopVal ; Op -> StartLoc


<s> if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) IsLittleEndian = false ; if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation =


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ; return


<s> return ! Subtarget . is<ISA_LIT>64 (


<s> static DecodeStatus DecoderForMRRC2AndMCRR2 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned CRm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned opc1 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned cop = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm ( opc1 ) ) ; if ( Inst . getOpcode ( ) ==


<s> if ( Reg != <NUM_LIT> ) MI -> getOperand ( OpNo ) . setReg

( get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ) ;


<s> } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N , Subtarget ) ) { return false ; } if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap (


<s> return ( __m512d ) __builtin_ia32_loadupd512_mask ( ( const __v8df * ) __P ,


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; emitJumpTableAddress ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , <STR_LIT> ) ; emitWordLE ( Binary )


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget -> isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty


<s> shift = exact_log2 ( INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) != ( HOST_WIDE_INT ) <NUM_LIT> << shift ) shift = - <NUM_LIT> ; } else if ( ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) && GET_MODE ( x ) == DImode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ASHIFT && GET_MODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == DImode && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { type = ( GET_CODE ( x ) == SIGN_EXTRACT ) ? ADDRESS_REG_SXTW : ADDRESS_REG_UXTW ; index = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; shift = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> + shift || INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> ) shift = - <NUM_LIT> ; } else if ( GET_CODE ( x ) == AND && GET_MODE ( x ) == DImode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ASHIFT && GET_MODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == DImode && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { type = ADDRESS_REG_UXTW ; index = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; shift = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) != ( HOST_WIDE_INT ) <NUM_LIT> << shift ) shift = - <NUM_LIT> ; } else if ( GET_CODE ( x ) == MULT && GET_MODE ( x ) == Pmode && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == Pmode && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { type = ADDRESS_REG_REG ; index = XEXP ( x , <NUM_LIT> ) ; shift = exact_log2 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; } else if ( GET_CODE ( x ) == ASHIFT && GET_MODE ( x ) == Pmode && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == Pmode && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { type = ADDRESS_REG_REG ; index = XEXP ( x ,


<s> MachineOperand & OfsOp = LdSt . getOperand ( LdSt . getNumExplicitOperands ( ) - <NUM_LIT> ) ; assert ( OfsOp . isImm ( ) && <STR_LIT> ) ; return OfsOp


<s> if ( merge_argno == DEFAULT_MERGE_ARGNO ) merge_argno = nops == <NUM_LIT> && pred == PRED_m ? <NUM_LIT> : <NUM_LIT> ; if ( merge_argno == <NUM_LIT> ) return args [ argno ++


<s> union { _Float16 _Complex a ; float b ; } u = { . a = __A } ; return ( __m128h ) _mm_set1_ps ( u . b


<s> if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( hasBP ( MF ) ) MRI . setPhysRegUsed ( BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex (


<s> SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; assert ( Kind == MCSymbolRefExpr :: VK_None || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_LO || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_HI ) ; OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset >


<s> static __inline qword si_ceqb ( qword a , qword b ) { return ( ( qword ) ( vec_cmpeq ( ( vec_uchar16 ) ( a ) , ( vec_uchar16


<s> SDValue OuFlag = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * DSPCtrlField = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , CstOne , InFlag ) ; SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( DSPCtrlField , <NUM_LIT> ) , OuFlag , CstOne ) ; SDValue Ops [ <NUM_LIT> ] = { SDValue ( DSPCtrlField , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CstOne , SDValue ( Carry , <NUM_LIT> ) } ; SDNode * DSPCFWithCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; SDValue Zero = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue InsOps [ <NUM_LIT> ] = { Zero , OuFlag , CstOne , SDValue ( DSPCFWithCarry , <NUM_LIT> ) } ; SDNode * DSPCtrlFinal = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , InsOps ) ; SDNode * WrDSP = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( DSPCtrlFinal , <NUM_LIT> ) , CstOne ) ; SDValue Operands [ <NUM_LIT> ] = { LHS , RHS , SDValue ( WrDSP , <NUM_LIT> ) } ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , VT , <STR_LIT> ,


<s> else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> || ( TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 , strict


<s> } if ( Reg2NumMap . find ( Reg ) != Reg2NumMap . end ( ) ) { Nums . push_back ( Reg2NumMap [ Reg ] ) ; } else { Reg2NumMap [ Reg ] = Num ; Num2ValMap [ Num ] = NULL ; Nums . push_back ( Num ) ; Num ++ ; } } else if ( Operand . isImm ( ) ) { int64_t Imm = Operand . getImm ( ) ; if ( Imm2NumMap . find ( Imm ) != Imm2NumMap . end ( ) ) { Nums . push_back ( Imm2NumMap [ Imm ] ) ; } else { Imm2NumMap [ Imm ] = Num ; Num2ValMap [ Num ] = NULL ; Nums . push_back ( Num ) ; Num ++ ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( DefReg != <NUM_LIT> ) { if ( Reg2NumMap . find ( DefReg ) != Reg2NumMap . end ( ) ) { unsigned int Num = Reg2NumMap [ DefReg ] ; Val * Val = Num2ValMap [ Num ] ; if ( Val != NULL && Val -> Nums . size ( ) == Nums . size ( ) && std :: equal ( Val -> Nums . begin ( ) , Val -> Nums . end


<s> if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * SRAConstant = dyn_cast < ConstantSDNode > ( SRASrc1 ) ; EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != NULL && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = <STR_LIT> ; if ( Subtarget -> isThumb2 ( ) ) Opcode = <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , VT , ADDSrc0 ) ; } return


<s> const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; else emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size


<s> case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple :: MacOSX : case Triple


<s> static bool isSupportedType ( const DataLayout & DL , const <ISA_LIT>TargetLowering & TLI , Type * T ) { EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT . isFloatingPoint ( ) ) ) return false ; unsigned VTSize = VT . getSimpleVT ( )


<s> emit_insn ( gen_add2_insn ( base_tmp , element_offset ) ) ; } new_addr = gen_rtx_PLUS ( Pmode , op0 , base_tmp ) ; } } else { emit_move_insn ( base_tmp , addr ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } if ( GET_CODE ( new_addr ) == PLUS ) { rtx op1 = XEXP ( new_addr , <NUM_LIT> ) ; addr_mask_type addr_mask ; int scalar_regno = regno_or_subregno ( scalar_reg ) ; gcc_assert ( scalar_regno < FIRST_PSEUDO_REGISTER ) ; if ( INT_REGNO_P ( scalar_regno ) ) addr_mask = reg_addr [ scalar_mode ] . addr_mask [ RELOAD_REG_GPR ] ; else if ( FP_REGNO_P ( scalar_regno ) ) addr_mask = reg_addr [ scalar_mode ] . addr_mask [ RELOAD_REG_FPR ] ; else if ( ALTIVEC_REGNO_P ( scalar_regno ) ) addr_mask = reg_addr [ scalar_mode ] . addr_mask [ RELOAD_REG_VMX ] ; else gcc_unreachable ( ) ; if ( REG_P ( op1 ) || SUBREG_P ( op1 ) ) valid_addr_p = ( addr_mask & RELOAD_REG_INDEXED ) != <NUM_LIT> ; else valid_addr_p = ( addr_mask & RELOAD_REG_OFFSET ) != <NUM_LIT> ; } else if ( REG_P ( new_addr ) || SUBREG_P ( new_addr ) ) valid_addr_p = true ; else valid_addr_p = false ; if ( ! valid_addr_p ) { emit_move_insn ( base_tmp , new_addr ) ; new_addr = base_tmp


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCoprocOption ( unsigned Val , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand >


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CMovI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( CurStateReg == PS -> InitialReg ) CMovs . push_back ( & * CMovI ) ; CurStateReg = UpdatedStateReg ; } PS -> SSA . AddAvailableValue ( & CheckingMBB , CurStateReg ) ; } ; std :: vector < <STR_LIT> > UncondCodeSeq ; for ( auto * CondBr : CondBrs ) { MachineBasicBlock & Succ = * CondBr -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int & SuccCount = SuccCounts [ & Succ ] ; <STR_LIT> Cond = <STR_LIT> ( * CondBr ) ; <STR_LIT> InvCond = <STR_LIT> ( Cond ) ; UncondCodeSeq . push_back ( Cond ) ; BuildCheckingBlockForSuccAndConds ( MBB , Succ , SuccCount , CondBr , UncondBr , { InvCond } ) ; -- SuccCount ; } MBB . normalizeSuccProbs ( ) ; if ( ! UncondSucc ) continue ; assert ( SuccCounts [ UncondSucc ] == <NUM_LIT> && <STR_LIT> <STR_LIT> <STR_LIT> ) ; llvm :: sort ( UncondCodeSeq ) ; UncondCodeSeq . erase ( std :: unique ( UncondCodeSeq . begin ( ) , UncondCodeSeq . end ( ) ) , UncondCodeSeq . end ( ) ) ; BuildCheckingBlockForSuccAndConds ( MBB , * UncondSucc , <NUM_LIT> , UncondBr , UncondBr


<s> SDValue <ISA_LIT>TargetLowering :: LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT>


<s> if ( matchShuffleWithPACK ( VT , PackVT , V1 , V2 , PackOpcode , Mask , DAG , Subtarget ) ) return DAG . getNode ( PackOpcode ,

DL , VT , DAG . getBitcast ( PackVT , V1 ) , DAG . getBitcast ( PackVT , V2 ) ) ;


<s> static tree aarch64_simd_builtin_type ( machine_mode mode , bool unsigned_p , bool poly_p ) { if ( poly_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned


<s> } } MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { if ( IndexLen == <NUM_LIT> ) V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V1Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst , DAG . getNode ( <STR_LIT> , DL , IndexVT , makeArrayRef ( TBLMask . data ( ) , IndexLen ) ) ) ; } else { if ( IndexLen == <NUM_LIT> ) { V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V2Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst


<s> rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_referenced_p ( x ,


<s> diff = ( mips_get_compress_off_flags ( DECL_ATTRIBUTES ( olddecl ) ) ^ mips_get_compress_off_flags ( DECL_ATTRIBUTES ( newdecl ) ) ) ; if ( diff ) error ( <STR_LIT> , DECL_NAME ( newdecl ) , mips_get_compress_off_name ( diff ) ) ; return merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand >


<s> } const MCInstrDesc * MCID = & MI -> getDesc ( ) ; unsigned NewOpc = convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false


<s> else { section * s ; char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL ) ; switch_to_section ( s


<s> nds32_split_shiftrtdi3 ( dst , src , shiftamount , true


<s> unsigned FP = <STR_LIT> ; unsigned ZERO = <STR_LIT> ; unsigned ADDu = <STR_LIT> ; unsigned ADDiu = <STR_LIT> ; unsigned StackAlign = getStackAlignment ( ) ; unsigned RegSize = <NUM_LIT> ; unsigned LocalVarAreaOffset = <ISA_LIT>FI -> needGPSaveRestore ( ) ? ( MFI -> getObjectOffset ( <ISA_LIT>FI -> getGPFI ( ) ) + RegSize ) : <ISA_LIT>FI -> getMaxCallFrameSize ( ) ; uint64_t StackSize = RoundUpToAlignment ( LocalVarAreaOffset , StackAlign ) + RoundUpToAlignment ( MFI -> getStackSize ( ) , StackAlign ) ; MFI -> setStackSize ( StackSize ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else { <ISA_LIT>FI -> setEmitNOAT ( ) ; expandLargeImm ( SP , - StackSize , TII , MBB , MBBI , dl ) ; } MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) )


<s> if ( ! LeftShift && isMask_32 ( C1 ) ) { uint32_t C3 = countLeadingZeros ( C1 ) ; if ( C2 < C3 ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C3 - C2 , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( C3 , DL , <STR_LIT> ) ) ; } } if ( LeftShift && isShiftedMask_32 ( C1 ) ) { uint32_t C3 = countLeadingZeros ( C1 ) ; if ( C2 + C3 < <NUM_LIT> && C1 == ( ( - <NUM_LIT> << ( C2 + C3 ) ) >> C3 ) ) { SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT>

) , DAG . getConstant ( C2 + C3 , DL , <STR_LIT> ) ) ;


<s> if ( Subtarget -> isDarwin ( ) ) return new <ISA_LIT>DarwinAsmPrinter ( tm , std :: move ( Streamer ) ) ; return new <ISA_LIT>LinuxAsmPrinter ( tm , std :: move


<s> static unsigned getBitExtrOpcode ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> for ( unsigned BTI = <NUM_LIT> , BTE = Block . NumTerminators ; BTI != BTE ; ++ BTI ) { assert ( Position . Address <= TI -> Address && <STR_LIT> ) ; if ( mustRelaxBranch ( * TI , Position . Address ) ) relaxBranch ( * TI ) ; skipTerminator ( Position , * TI , false ) ; ++ TI


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef


<s> int64_t Offset = <NUM_LIT> * ( Subtarget . isLittle ( ) ? N : ( <NUM_LIT> - N ) ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = FP64 ? & <STR_LIT> : & <STR_LIT> ; const TargetRegisterClass * RC2 = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC ) ; TII . storeRegToStack ( MBB , I , SrcReg , Op1 . isKill ( ) , FI , RC , & RegInfo , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & RegInfo , Offset ) ; return true ; } return false


<s> static SDValue LowerMUL ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; SDNode * N0 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * N1 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; unsigned NewOpc = <NUM_LIT> ; if ( isSignExtended ( N0 , DAG ) && isSignExtended ( N1 , DAG ) ) NewOpc = <STR_LIT> ; else if ( isZeroExtended ( N0 , DAG ) && isZeroExtended ( N1 , DAG ) ) NewOpc = <STR_LIT> ; else if ( VT == <STR_LIT> ) return


<s> bool nds32_vector_mode_supported_p ( machine_mode mode ) { if ( mode == V4QImode || mode == V2HImode ) return NDS32_EXT_DSP_P ( ) ; return


<s> if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isABI_N32 ( ) || isABI_N64 ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; else { assert ( isABI_O32 ( ) && <STR_LIT> ) ; stackAlignment = Align


<s> MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; <ISA_LIT>FI = MFunc . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI = & MFunc . getFrameInfo ( ) ; TRI = ST -> getRegisterInfo ( ) ; CfgSS = - <NUM_LIT> ; unsigned NumVirtRegs = MRI -> getNumVirtRegs ( ) ; bool HasVirtTileReg = false ; for ( unsigned I = <NUM_LIT> , E = NumVirtRegs ; I != E ; ++ I ) { Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI -> getRegClass ( VirtReg ) -> getID ( ) == <STR_LIT> ) { HasVirtTileReg =


<s> unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) return CE -> getValue ( ) % <NUM_LIT> == <NUM_LIT> ; return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> (


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; DecodeStatus S = MCDisassembler :: Success ; if ( Rt == Rn || Rn == Rt2 ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return


<s> unsigned <ISA_LIT>TargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , ( unsigned ) DL .


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> ) return EmitTest ( Op0 , <ISA_LIT>CC , DAG ) ; DebugLoc dl = Op0 . getDebugLoc ( ) ; if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1 ) ; return SDValue ( Sub . getNode ( ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> assert ( OffsetOfNextBlock == BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) ; if ( BBHasFallthrough ( UserMBB ) && OffsetIsInRange ( UserOffset , OffsetOfNextBlock + ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) , U . MaxDisp , U . NegOk , U . IsSoImm ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; if ( & UserMBB -> back ( ) == UserMI ) assert ( BBHasFallthrough ( UserMBB ) && <STR_LIT> ) ; NewMBB = llvm :: next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; BuildMI ( UserMBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < CPUsers . size ( ) && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! OffsetIsInRange ( Offset , EndInsertOffset , U . MaxDisp , U . NegOk , U . IsSoImm ) ) { BaseInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; EndInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; } EndInsertOffset += CPUsers [ CPUIndex ] . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } } DEBUG ( errs ( ) << <STR_LIT> ) ; NewMBB = SplitBlockBeforeInstr ( prior


<s> Idx = PHI -> getBasicBlockIndex ( BackEdgeBB ) ; if ( Idx < <NUM_LIT> ) continue ; Value * EC ; if ( ! match ( PHI -> getIncomingValue ( Idx ) , m_Add ( m_Specific ( PHI ) , m_ElementCount ( m_Value ( EC ) ) ) ) ) continue ; VectorType * ECTy = dyn_cast < VectorType > ( EC -> getType ( ) ) ; if ( ! ECTy || ! ECTy -> isScalable ( ) ) continue ; if ( ECTy -> getNumElements ( ) != ElementCountTy -> getNumElements ( ) ) continue ; return PHI


<s> rtx legitimize_pic_address ( rtx orig , machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { if ( tls_symbolic_operand ( orig , Pmode ) != TLS_MODEL_NONE ) return orig ; if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) ) ) { if ( reg == NULL_RTX ) reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_FDPIC && GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( orig ) ) { if ( SYMBOL_REF_WEAK ( orig ) ) emit_insn ( gen_symGOTFUNCDESC2reg ( reg , orig ) ) ; else emit_insn ( gen_symGOTOFFFUNCDESC2reg ( reg , orig ) ) ; } else if ( TARGET_FDPIC && ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_DECL ( orig ) && ( TREE_READONLY ( SYMBOL_REF_DECL ( orig ) ) || SYMBOL_REF_EXTERNAL_P ( orig ) || DECL_SECTION_NAME ( SYMBOL_REF_DECL ( orig ) ) ) ) ) ) emit_insn ( gen_symGOT2reg ( reg , orig ) ) ; else emit_insn ( gen_symGOTOFF2reg ( reg , orig


<s> static bool isXor1OfSetCC ( SDValue Op ) { if ( Op . getOpcode ( ) != <STR_LIT>


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( unsigned InnerVT = ( unsigned ) <STR_LIT> ; InnerVT <= ( unsigned ) <STR_LIT> ; ++ InnerVT ) setTruncStoreAction ( VT . getSimpleVT ( ) , ( <STR_LIT> ) InnerVT , Expand ) ; } setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT (


<s> if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) In = N -> getOperand ( <NUM_LIT> ) ; else In = N -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( In ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getAlignment ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = getProperNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) , DAG ) ; if ( Convert -> getOpcode ( ) == <STR_LIT> || Convert -> getOpcode ( ) == <STR_LIT> ) DCI . CombineTo ( N , Convert . getValue ( <NUM_LIT> ) , Convert . getValue ( <NUM_LIT> ) ) ; else DCI . CombineTo ( N , Convert


<s> if ( IMM12_OPERAND ( frame -> total_size ) ) return frame -> total_size ; HOST_WIDE_INT min_first_step = LARCH_STACK_ALIGN ( frame -> total_size - frame -> fp_sp_offset ) ; HOST_WIDE_INT max_first_step = IMM_REACH /


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { return SelectionDAGISel :: runOnMachineFunction ( MF


<s> void \ init_section ( ) \ { \ if ( ( ! TARGET_ELF ) && in_section != in_init ) \ { \ fprintf ( asm_out_file , <STR_LIT> , INIT_SECTION_ASM_OP ) ; \ in_section =


<s> return ( uint8x16_t ) __builtin_aarch64_ashlv16qi ( (


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( AP . lowerOperand ( MO , MCOp )


<s> getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; auto & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ? ABI .

GetFramePtr ( ) : ABI . GetStackPtr ( ) ;


<s> if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return cfun -> machine -> frame . total_size ==


<s> FunctionPass * llvm :: create<ISA_LIT>ProtectReturnSupport (


<s> case E_HCmode : case E_SFmode : case E_SCmode : case E_DFmode : case E_DCmode : case E_TFmode : case E_SDmode : case E_DDmode : case E_TDmode : regno = FIRST_SSE_REG ; break ; case E_XFmode : case E_XCmode : regno = FIRST_FLOAT_REG ; break ; case E_TCmode


<s> return ! any_of ( M , [ & ] ( const Function & F ) { StringRef AttrVal = F . getFnAttribute ( Attr ) . getValueAsString ( ) ; return parseDenormalFPAttribute ( AttrVal


<s> if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; <ISA_LIT>AddressMode


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) ) { SExtVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) { SExtVT = <STR_LIT> ; break ; } return SDValue ( ) ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getNode ( <STR_LIT> , DL , SExtVT , N0 ) ; if ( SExtVT == <STR_LIT> ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( V , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( Op0 . getValueType ( ) == <STR_LIT> && ( ( isa < ConstantSDNode > ( Op0 ) && ! cast < ConstantSDNode > ( Op0 ) -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( isa < ConstantSDNode > ( Op1 ) && ! cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) && ! Subtarget . isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 .


<s> DOP_ENTRY_HSD ( ps , inst , ty ) { <STR_LIT> ## _S , { <STR_LIT> ## _S , <STR_LIT>


<s> ArrayRef < int > M1 , M2 ; Value * S1Op1 , * S2Op1 ; if ( ! match ( Op1 , m_Shuffle ( m_Value ( S1Op1 ) , m_Undef ( ) , m_Mask ( M1 ) ) ) || ! match ( Op2 , m_Shuffle ( m_Value ( S2Op1 ) , m_Undef ( ) , m_Mask ( M2 ) ) ) ) return false ; if ( ! areTypesHalfed ( S1Op1 , Op1 ) || ! areTypesHalfed ( S2Op1 , Op2 ) || ! extractHalf ( S1Op1 , Op1 ) || ! extractHalf ( S2Op1 , Op2 ) ) return false ; int M1Start = - <NUM_LIT> ; int M2Start = - <NUM_LIT> ; int NumElements = cast < FixedVectorType > ( Op1 -> getType ( )


<s> if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return SDValue ( ) ; SDLoc dl ( N ) ; if ( NumElts < <NUM_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstantFP ( <NUM_LIT> , dl , SrcVT ) ) ; EVT CvtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , std :: max ( <NUM_LIT> , NumElts ) ) ; SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , CvtVT , Src , DAG . getTargetConstant ( <NUM_LIT>


<s> AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag (


<s> int offset = UNITS_PER_WORD * ( GPR_ARG_LAST + <NUM_LIT> - GPR_ARG_FIRST ) ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , offset ) ; return gen_rtx ( PLUS , Pmode , virtual_incoming_args_rtx , GEN_INT ( -


<s> EmitLabel ( Symbol , Loc , F ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF


<s> getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) .


<s> ++ MFI ) for ( MachineBasicBlock :: iterator I = MFI -> begin ( ) ; I != MFI -> end ( ) ; ++ I ) replaceUsesWithZeroReg ( MRI ,


<s> auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Cond ) ; ( void ) SetI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SetI -> dump


<s> return ( __m128d ) __builtin_ia32_rcp28sd_round ( ( __v2df )


<s> if ( GET_MODE ( arg ) != mode && register_operand ( arg , VOIDmode ) && GET_MODE_SIZE ( GET_MODE ( arg ) ) == GET_MODE_SIZE ( mode ) ) return simplify_gen_subreg ( mode , arg , GET_MODE ( arg ) , <NUM_LIT> ) ; return arg


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) { CondBrMBBOperand = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = A64InvertCondCode ( CC ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; } else { MachineInstrBuilder InvertedMI ; int InvertedOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; } InvertedMI = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( InvertedOpcode ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { InvertedMI . addOperand ( MI -> getOperand ( i ) ) ; if ( MI -> getOperand ( i ) . isMBB ( ) ) CondBrMBBOperand = i ; } MI -> eraseFromParent


<s> if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsl ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex ( ) ; if ( St == Rrx ) return


<s> if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ; return selectAddrDefault ( Addr , Base


<s> cvtLdWriteBackRegAddrMode2 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addAddrMode2Operands ( Inst , <NUM_LIT> ) ;


<s> initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != <STR_LIT> && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner (


<s> clobbers . safe_push ( gen_rtx_REG ( SImode , CA_REGNO ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CA_REGNO ) ; return NULL


<s> Relocator :: Size <ISA_LIT>_64Relocator :: getSize ( Relocation :: Type pType ) const { return <ISA_LIT>_64ApplyFunctions [ pType ] .


<s> bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment ( ) == Triple :: GNUX32 ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> :


<s> bool <ISA_LIT>TTI :: isLegalMaskedStore ( Type * DataType , int Consecutive ) const { return isLegalMaskedLoad ( DataType ,


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( )


<s> std :: unique_ptr < ScheduleDAGMutation > createPowerPCMacroFusionDAGMutation ( ) { return createMacroFusionDAGMutation (


<s> std :: bitset < <NUM_LIT> > Zeroable ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Elt = Op -> getOperand ( i ) ; Zeroable [ i ] = ( Elt . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Elt ) ) ; } assert ( Zeroable . size ( ) - Zeroable . count ( ) > <NUM_LIT> && <STR_LIT> ) ; SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op -> getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG


<s> for ( BasicBlock * PredBB : predecessors ( BB ) ) { auto PredEndState = FinalStates . find ( PredBB ) ; if ( PredEndState == FinalStates . end ( ) ) return OverdefinedState ; if ( isa < CatchReturnInst > ( PredBB -> getTerminator ( ) ) ) return OverdefinedState ; int PredState = PredEndState -> second ; assert ( PredState != OverdefinedState && <STR_LIT> ) ; if ( CommonState == OverdefinedState


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS4 ( SDValue Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base , OffImm


<s> if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Opc == G_ZEXT ) return Size ==


<s> case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return LowerFNEGorFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm7s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Reg , Imm7 ; bool isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm7 , Fixups , STI ) ; uint32_t Binary = ( Imm7 >> <NUM_LIT> ) & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg <<


<s> if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ( bitpos & <NUM_LIT> ) != <NUM_LIT> ) regno ++ ; int pos = bitpos / BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , <NUM_LIT> , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; data -> nregs += <NUM_LIT> ; regno += GET_MODE_SIZE (


<s> fprintf ( file , <STR_LIT> PROFILE_COUNT_REGISTER <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , mcount_name ) ; } else { fprintf ( file , <STR_LIT> PROFILE_COUNT_REGISTER <STR_LIT> , LPREFIX , labelno ) ; x86_print_call_or_nop ( file , mcount_name ) ; } if ( flag_record_mcount || lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) ) { const char * sname = <STR_LIT> ; if ( current_fentry_section ( & sname ) ) ; else if ( fentry_section ) sname = fentry_section ; fprintf ( file , <STR_LIT> , sname ) ; fprintf ( file , <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file ,


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) ->


<s> MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( III . ZeroIsSpecialNew ) { unsigned RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegToModify ) ) { const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify , NewRC ) ; } } } if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill (

DefMI , MI , ForwardKilledOperandReg ) ;


<s> MCTargetStreamer & TS = Parser . getStreamer ( ) . getTargetStreamer ( ) ; return static_cast < <ISA_LIT>TargetStreamer & > ( TS


<s> AddrOffset += <STR_LIT> ( Desc ) ; MachineOperand & p = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( p . isReg ( ) && p . getReg ( ) != <STR_LIT> ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( q . isReg ( ) && q . getReg ( ) != <STR_LIT> ) { seekLEAFixup ( q , I


<s> SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) ) ; Offset += <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , DL ,


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand (


<s> if ( isa < CatchReturnInst > ( BB -> getTerminator ( ) ) ) return OverdefinedState ; int CommonState = OverdefinedState ; for ( BasicBlock * SuccBB : successors ( BB ) ) { auto SuccStartState = InitialStates . find ( SuccBB ) ; if ( SuccStartState == InitialStates . end ( ) )


<s> SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( VT . getVectorNumElements ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getNode ( <STR_LIT> , DL , ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + VT . getVectorNumElements ( ) / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getNode ( <STR_LIT> , DL , ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedVT . getSizeInBits ( ) , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr (


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst )


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> MemInst . setOpcode ( IsLoad ? <STR_LIT> : <STR_LIT> ) ; MemInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; MemInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; MemInst . addOperand ( MCOperand :: createImm ( StackOffset ) ) ; if ( ! isInt < <NUM_LIT> > ( StackOffset ) ) expandMemInst ( MemInst , IDLoc , Instructions , IsLoad , true ) ; else Instructions . push_back


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static void emitPostLd ( MachineBasicBlock * BB , MachineInstr * Pos , const TargetInstrInfo * TII , const DebugLoc & dl , unsigned LdSize , unsigned Data , unsigned AddrIn , unsigned AddrOut , bool IsThumb1 , bool IsThumb2 ) { unsigned LdOpc = getLdOpcode ( LdSize , IsThumb1 , IsThumb2 ) ; assert ( LdOpc != <NUM_LIT> && <STR_LIT> ) ; if ( LdSize >= <NUM_LIT> ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; } else if ( IsThumb1 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; MachineInstrBuilder MIB = BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) ; MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( AddrIn ) . addImm ( LdSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2


hasEHFunclets ( ) ) restoreWinEHStackPointersInParent ( MF ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> return new <ISA_LIT>AsmBackend ( T , MRI , STI . getTargetTriple ( ) , STI . getCPU


<s> imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , group_name [ group ] , path , byte_len ) ; fprintf ( file , <STR_LIT> , num_imm_operand , num_imm32_operand ,


<s> BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent ( ) ; MachineInstr * BrMI = MBB -> getFirstTerminator ( ) ; BuildMI ( * MBB , BrMI , BrMI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( Cmp ) . addOperand ( BrMI -> getOperand ( <NUM_LIT> ) ) ; BrMI -> eraseFromParent ( ) ; MBB -> updateTerminator ( ) ; ++


<s> if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( ! Ld -> isVolatile ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue ( <NUM_LIT> ) ) ; return FILDChain ; } } return SDValue ( )


<s> static void extractParts ( Register Reg , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , LLT Ty , int NumParts , SmallVectorImpl < Register > & VRegs ) { for ( int I = <NUM_LIT> ; I < NumParts ; ++ I ) VRegs . push_back ( MRI . createGenericVirtualRegister ( Ty ) ) ; MIRBuilder . buildUnmerge ( VRegs , Reg


<s> AddInstr ( SeqLs , Inst ( ORi , Imm & <NUM_LIT> )


<s> void addMemNoOffsetT2Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> if ( GET_MODE ( op ) == V4SFmode || GET_MODE ( op ) == V2SFmode ) tmp = gen_lowpart ( SImode , tmp ) ; return INTVAL (


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { llvm :: RegisterTarget < llvm :: Triple :: stackpu2 > X ( llvm ::


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MII )


<s> if ( MJTI == <NUM_LIT> ) return false ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> , e = T2JumpTables . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = T2JumpTables [ i ] ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size


<s> rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , frame_pattern , REG_NOTES (


<s> NewOpc = <STR_LIT> ; } else if ( Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else { return false ; } if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( * Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset =


<s> unsigned sx = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeAS ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } return MCDisassembler


<s> emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr =


<s> rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( modreg , modmem ) ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_32BIT ) emit_insn ( gen_tls_get_addrsi ( dest , modreg , tmpreg ) ) ; else emit_insn ( gen_tls_get_addrdi ( dest , modreg , tmpreg ) ) ; return dest ; } else if ( TARGET_32BIT ) { tlsreg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tls_get_tpointer ( tlsreg ) ) ; } else { tlsreg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; xcoff_tls_exec_model_detected = true ; } tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_MINUS ( Pmode , addr , tlsreg ) ) ; dest = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , tmpreg , tlsreg


<s> break ; case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_JUMP19 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_JUMP11 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_JUMP8 ; break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS8 ; break ; } break ; case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS16 ; break ; } break ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedGatherBaseWB ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty

-> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ;


<s> enum rtx_code code ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; if ( code == GE || code == GEU || code == LE || code == LEU || code == NE ) { gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) ; PUT_CODE ( operands [ <NUM_LIT> ] , reverse_condition ( code ) ) ; return <STR_LIT>


<s> ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } Reference CCRefs ( getRegReferences ( MI , <STR_LIT> ) ) ; if ( CCRefs . Def ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( CompleteCCUsers && CCRefs . Use ) CCUsers . push_back ( MI ) ; } return Changed


<s> typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_ssaddv2si3 ( ( v2si ) mm , ( v2si )


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo


<s> else if ( * q == '.' ) last_period = q ; } len = strlen ( after_last_slash ) + strlen ( section_desc ) + <NUM_LIT> ; * buf = ( char * ) xmalloc ( len ) ; p = * buf ; * p ++ = '_' ; for ( q = after_last_slash ; * q ; q ++ ) { if ( q == last_period ) { strcpy ( p , section_desc ) ; p += strlen ( section_desc ) ; break ; } else if ( ISALNUM ( * q ) ) * p ++ = * q ; } if ( last_period == <NUM_LIT> ) strcpy ( p , section_desc ) ; else * p


<s> void clear ( ) { Refs = AvailableDomains = Dist = <NUM_LIT> ; Instrs . clear


<s> bool <ISA_LIT>InstructionSelector :: select (


<s> static void mips_deallocate_stack ( rtx base , rtx offset , HOST_WIDE_INT new_frame_size ) { if ( base == stack_pointer_rtx && offset == const0_rtx ) return ; mips_frame_barrier ( ) ; if ( offset == const0_rtx ) { emit_move_insn ( stack_pointer_rtx , base ) ; mips_epilogue_set_cfa ( stack_pointer_rtx , new_frame_size ) ; } else if ( TARGET_MIPS16 && base != stack_pointer_rtx ) { emit_insn ( gen_add3_insn ( base , base , offset ) ) ; mips_epilogue_set_cfa ( base , new_frame_size ) ; emit_move_insn ( stack_pointer_rtx , base ) ; } else { emit_insn ( gen_add3_insn ( stack_pointer_rtx , base , offset ) ) ; mips_epilogue_set_cfa ( stack_pointer_rtx ,


<s> if ( ! I -> isCall ( ) ) return false ; unsigned structSizeOpNum = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; } const MachineOperand & MO = I ->


unsigned long long __X , unsigned long long __Y ) {


<s> std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool has<ISA_LIT>16Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool hasNo<ISA_LIT>16Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool HasMicro<ISA_LIT>Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool HasNoMicro<ISA_LIT>Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get


<s> if ( matchShuffleAsEXTRQ ( VT , V1 , V2 , Mask , BitLen , BitIdx , Zeroable ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , DAG . getTargetConstant ( BitLen , DL , <STR_LIT> ) , DAG . getTargetConstant ( BitIdx , DL , <STR_LIT> ) ) ; if ( matchShuffleAsINSERTQ ( VT , V1 , V2 , Mask , BitLen , BitIdx ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ? V1 : DAG . getUNDEF ( VT

) , V2 ? V2 : DAG . getUNDEF ( VT ) , DAG . getTargetConstant ( BitLen , DL , <STR_LIT> ) , DAG . getTargetConstant ( BitIdx , DL , <STR_LIT> ) ) ;


<s> break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI -> getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned DReg = TRI -> getMatchingSuperReg ( Reg , <STR_LIT>


<s> MachineInstrBuilder MIB1 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , Reg1 ) ; MIB1 . addImm ( Amount ) ; MachineInstrBuilder MIB2 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , Reg2 ) ; MIB2 . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineInstrBuilder MIB3 = BuildMI ( MBB , I , DL , get ( <STR_LIT> )


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering


<s> else size = GET_MODE_SIZE ( mode ) ; if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > <NUM_LIT> && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ; else return <NUM_LIT>


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lwpval64 ( unsigned long long __data2 , unsigned int __data1 , unsigned


<s> char * q ; while ( ( q = strtok ( p , <STR_LIT> ) ) != NULL ) { bool error_p = false ; bool not_valid_p = false ; const char * cpu_opt = NULL ; p = NULL ; if ( strncmp ( q , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { int cpu_index = rs6000_cpu_name_lookup ( q + <NUM_LIT> ) ; if ( cpu_index >= <NUM_LIT> ) rs6000_cpu_index = cpu_index ; else { error_p = true ; cpu_opt = q + <NUM_LIT> ; } } else if ( strncmp ( q , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { int tune_index = rs6000_cpu_name_lookup ( q + <NUM_LIT> ) ; if ( tune_index >= <NUM_LIT> ) rs6000_tune_index = tune_index ; else { error_p = true ; cpu_opt = q + <NUM_LIT> ; } } else { size_t i ; bool invert = false ; char * r = q ; error_p = true ; if ( strncmp ( r , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { invert = true ; r += <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_opt_masks ) ; i ++ ) if ( strcmp ( r , rs6000_opt_masks [ i ] . name ) == <NUM_LIT> ) { HOST_WIDE_INT mask = rs6000_opt_masks [ i ] . mask ; if ( ! rs6000_opt_masks [ i ] . valid_target ) not_valid_p = true ; else { error_p = false ; rs6000_isa_flags_explicit |= mask ; if ( mask == OPTION_MASK_VSX && ! invert ) mask |= OPTION_MASK_ALTIVEC ; if ( rs6000_opt_masks [ i ] . invert ) invert = ! invert ; if ( invert ) rs6000_isa_flags &= ~ mask ; else rs6000_isa_flags |=


<s> return __builtin_mve_vmlsldavxq_sv4si ( __a ,


<s> bool isTargetMachO ( ) const { return TargetTriple .


<s> int regno2 ; for ( regno2 = regno + <NUM_LIT> ; ( saved_regs_mask & ( <NUM_LIT> << regno2 ) ) == <NUM_LIT> ; regno2 ++ ) ; reg1 = gen_rtx_REG ( SImode , regno ) ; reg2 = gen_rtx_REG ( SImode , regno2 ) ; if ( first ) { rtx insn ; first = false ; mem1 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ; mem2 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * ( num_regs - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * ( num_regs ) ) ) ; tmp1 = gen_rtx_SET ( VOIDmode , mem1 , reg1 ) ; tmp2 = gen_rtx_SET ( VOIDmode , mem2 , reg2 ) ; RTX_FRAME_RELATED_P ( tmp0 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) = <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp0 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp1 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp2 ; insn = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } else { mem1 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) ; mem2 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * ( i + <NUM_LIT> ) ) ) ; tmp1 = gen_rtx_SET ( VOIDmode , mem1 , reg1 ) ; tmp2 = gen_rtx_SET ( VOIDmode , mem2 , reg2 ) ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) = <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp1 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp2 ; emit_insn ( par ) ; } tmp1 = gen_rtx_SET ( VOIDmode , gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) , reg1 ) ; tmp2 = gen_rtx_SET ( VOIDmode , gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * ( i + <NUM_LIT> ) ) ) , reg2 ) ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) =


<s> return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) || Parser . getTok ( ) . is ( AsmToken :: LParen ) || Parser . getTok ( ) . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) Parser . Lex ( ) ; E = Parser . getTok ( ) . getLoc ( ) ; bool isNegative = getParser ( ) . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * Offset , * AdjustedOffset ; if ( getParser ( ) . parseExpression ( Offset ) ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Offset ) ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) CE = MCConstantExpr :: create ( std :: numeric_limits < int32_t > :: min ( ) , getContext ( ) ) ; AdjustedOffset = CE ; } else AdjustedOffset = Offset ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , AdjustedOffset , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , false , S , E ) ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex


<s> const TargetRegisterClass * RC = & <STR_LIT> ; Register DestReg = createResultReg ( RC ) ; unsigned TempReg1 = materialize32BitInt ( Imm >> <NUM_LIT> , & <STR_LIT> ) ; unsigned TempReg2 = materialize32BitInt ( Imm & <NUM_LIT> , & <STR_LIT> ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg2 )


<s> int pru_can_use_return_insn ( void ) { if ( ! reload_completed || crtl ->


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Reg , Imm8 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT>


<s> outs ( ) << <STR_LIT> ; outs ( ) << MBB << <STR_LIT> ; } outs ( ) << <STR_LIT> ; return


<s> MCContext & getContext ( ) { return getStreamer ( )


<s> assert ( MO2 . isImm ( ) && <STR_LIT> ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) O << <STR_LIT> << translateShiftImm ( <STR_LIT> (


<s> ( MI -> getParent ( ) ) -> addSuccessor ( NewBB ) ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; for ( MachineBasicBlock :: iterator IAfterJAL = ++ MI , E = NewBB -> end ( ) ; IAfterJAL != E ; ++ IAfterJAL ) { NewBB -> remove ( IAfterJAL ) ; NewBB -> insert ( E , IAfterJAL ) ; } return NewBB