<s> if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( flagSettingOpcodeVariant ( MI -> getOpcode ( ) ) != <STR_LIT> ) { bool isSafe = false ; SmallVector < std :: pair < MachineOperand * , LPCC :: CondCode > , <NUM_LIT> > OperandsToUpdate ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } LPCC :: CondCode CC ; CC = ( LPCC :: CondCode ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { LPCC :: CondCode NewCC = getOppositeCondition ( CC ) ; if ( NewCC == LPCC :: ICC_T ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT>


<s> if ( NumVecs == <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLd ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SDValue SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned Sub0 = ( is64BitVector ? <STR_LIT> : <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N ,

Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ;


<s> auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType


<s> if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal (


<s> uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getUnqualifiedName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; OutStreamer -> emitLabel ( EmittedInitSym ) ; llvm :: for_each ( GOAliasMap [ GV ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getSymbol ( Alias ) ) ; } ) ; emitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer (


<s> return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter :: getOSABI (


<s> if ( IsPreDec ) Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; else Opc = IsFloat ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , Pos , DebugLoc ( ) , TII . get ( Opc ) ) ; if ( IsPreDec ) MIB .


<s> const TargetFrameInfo & TFI = * TM . getFrameInfo ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , StackSlot ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Chain , StackSlot , NULL , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ,


<s> } else return SDValue ( ) ; } if ( nextIndex != Vec . getValueType ( ) . getVectorNumElements ( ) || Vec . getValueType ( ) . getVectorElementType ( ) == VT . getVectorElementType ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; EVT inputLaneType = Vec . getValueType ( ) . getVectorElementType ( ) ; switch ( inputLaneType . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> bool sh_treg_combine :: is_inverted_ccreg (


<s> MachineBasicBlock :: iterator BundleStart = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ClearMask >> <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I -> getOperand ( <NUM_LIT> )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , false ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , true ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; } MI . addOperand ( MCOperand :: CreateReg ( RegEnum ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { APInt immRaw = VFPExpandImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT>

) , Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ;


<s> else { unsigned HOST_WIDE_INT p [ <NUM_LIT> ] ; long l [ <NUM_LIT> ] ; real_to_target ( l , CONST_DOUBLE_REAL_VALUE ( in ) , TFmode ) ; if ( FLOAT_WORDS_BIG_ENDIAN ) { p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; } else { p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; } out [ <NUM_LIT> ] = GEN_INT ( p [ <NUM_LIT> ] ) ; out [ <NUM_LIT> ] = GEN_INT ( p [ <NUM_LIT> ] ) ; } break ; case MEM : { rtx base = XEXP ( in , <NUM_LIT> ) ; rtx offset ; switch ( GET_CODE ( base ) ) { case REG : if ( ! reversed ) { out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_INC ( Pmode , base ) , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , dead ? <NUM_LIT> : gen_rtx_POST_DEC ( Pmode , base ) , <NUM_LIT> ) ; } else { emit_insn ( gen_adddi3 ( base , base , GEN_INT ( <NUM_LIT> ) ) ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_DEC ( Pmode , base ) , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_address ( in , DImode , <NUM_LIT> ) ; } break ; case POST_INC : gcc_assert ( ! reversed && ! dead ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , <NUM_LIT> , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , <NUM_LIT> , <NUM_LIT> ) ; break ; case POST_DEC : gcc_assert ( ! reversed && ! dead ) ; base = XEXP ( base , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_INC ( Pmode , base ) , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_MODIFY ( Pmode , base , plus_constant ( Pmode , base , - <NUM_LIT> ) ) , <NUM_LIT> ) ; break ; case POST_MODIFY : gcc_assert ( ! reversed && ! dead ) ; offset = XEXP ( base , <NUM_LIT> ) ; base = XEXP ( base ,


<s> static unsigned int rest_of_handle_insert_vzeroupper ( void ) { if ( TARGET_VZEROUPPER && flag_expensive_optimizations && ! optimize_size ) { for ( int i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ; g -> get_passes ( ) -> execute_pass_mode_switching ( ) ; } ix86_add_reg_usage_to_vzerouppers ( ) ; return <NUM_LIT>


<s> return IsISR && ( FI == ISRDataRegFI [ <NUM_LIT> ] || FI == ISRDataRegFI [


<s> if ( Mcpu == <STR_LIT> || Mcpu == <STR_LIT> || Mcpu == <STR_LIT> || Mcpu == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; <ISA_LIT>TargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - <NUM_LIT> ; ++ I ) assert ( Comp ( * I , * ( I + <NUM_LIT> ) ) ) ; return std :: binary_search ( LibCalls , End , CallSym ,


<s> SDValue False = N -> getOperand ( <NUM_LIT> ) ; EVT FalseTy = False . getValueType ( ) ; if ( ! FalseTy . isInteger ( ) ) return SDValue ( ) ; ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( False ) ; if ( ! CN || CN -> getZExtValue ( ) ) return SDValue ( ) ; const DebugLoc DL = N -> getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( DL , SetCC . getValueType ( ) , SetCC . getOperand ( <NUM_LIT> ) , SetCC .

getOperand ( <NUM_LIT> ) , <STR_LIT> ( CC , true ) ) ;


<s> if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) -


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr


<s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Release : return nullptr ; case AtomicOrdering :: Acquire : case AtomicOrdering ::


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { if ( lowerLongBranch ( MI , OutMI ) ) return ; OutMI . setOpcode ( MI -> getOpcode (


<s> rtx mem = gen_const_mem ( ptr_mode , addr ) ; if ( Pmode != ptr_mode ) mem = gen_rtx_SIGN_EXTEND ( Pmode


<s> if ( UnsupportedFPMode ) return false ; Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) return false ; Opc = <STR_LIT> ; break ; default : return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstStore ( Opc , SrcReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; unsigned Align = <NUM_LIT> ; unsigned Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand ::

MOLoad , MFI . getObjectSize ( FI ) , Align ) ;


<s> bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( * MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap (


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case


<s> CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ; else CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) { return forceScalarizeMaskedGather ( VTy , Alignment


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; O << getRegisterName ( Reg -


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> static const <ISA_LIT>MCExpr * CreateGOTLo12 ( const MCExpr *


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; auto * IdxC = dyn_cast < ConstantSDNode > ( Idx ) ; if ( VecVT . getVectorElementType ( ) == <STR_LIT> ) return ExtractBitFromMaskVector ( Op , DAG , Subtarget ) ; if ( ! IdxC ) { return SDValue ( ) ; } unsigned IdxVal = IdxC -> getZExtValue ( ) ; if ( VecVT . is256BitVector ( ) || VecVT . is512BitVector ( ) ) { Vec = extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getIntPtrConstant ( IdxVal , dl ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { if ( IdxVal == <NUM_LIT> && ! <STR_LIT> ( Op ) && ! ( Subtarget . hasSSE41 ( ) && <STR_LIT> ( Op ) ) ) { if ( Subtarget . hasFP16 ( ) ) return Op ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; } SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Extract ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal


<s> virtual const <ISA_LIT>SelectionDAGInfo *


<s> int n_var = <NUM_LIT> , one_var = - <NUM_LIT> ; bool all_same = true ; rtx x , mem ; int i ; x = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; if ( ! CONST_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) ) n_var = <NUM_LIT> , one_var = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! CONST_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) ) ++ n_var , one_var = i ; if ( ! rtx_equal_p ( x , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) all_same = false ; } if ( n_var == <NUM_LIT> ) { rtx constant = aarch64_simd_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same ) { x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; aarch64_emit_move ( target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; rtx index = GEN_INT ( one_var ) ; enum insn_code icode ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; aarch64_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals


<s> EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { UpdateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; } unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , InputReg , true , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> bool <ISA_LIT>GNULDBackend :: finalizeTargetSymbols ( ) { return true


<s> MVT FullVT = getFullRegisterType ( VT ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . NOT ( A2 ) ; SDValue TmpAns = b . OR ( b . AND ( A1 , Tmp ) , b . AND ( b . SHL < <NUM_LIT> > ( b . AND ( A1 , Tmp ) ) , b . OR ( A1 , Tmp ) ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , TmpAns , b . SRL <


<s> static unsigned getLinkageSize ( bool is<ISA_LIT>64 , bool isDarwinABI , bool isELFv2ABI ) { if ( isDarwinABI || is<ISA_LIT>64 ) return ( isELFv2ABI ? <NUM_LIT> : <NUM_LIT> ) * ( is<ISA_LIT>64 ? <NUM_LIT> :


<s> MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { const MachineOperand & MO_Sym = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand MO_TLSDESC_LO12 ( MO_Sym ) , MO_TLSDESC ( MO_Sym ) ; MCOperand Sym , SymTLSDescLo12 , SymTLSDesc ; MO_TLSDESC_LO12 . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; MO_TLSDESC . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; MCInstLowering . lowerOperand ( MO_Sym , Sym ) ; MCInstLowering . lowerOperand ( MO_TLSDESC_LO12 , SymTLSDescLo12 ) ; MCInstLowering . lowerOperand ( MO_TLSDESC , SymTLSDesc ) ; MCInst Adrp ; Adrp . setOpcode ( <STR_LIT> ) ; Adrp . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Adrp . addOperand ( SymTLSDesc ) ; EmitToStreamer ( * OutStreamer , Adrp ) ; MCInst Ldr ; Ldr . setOpcode ( <STR_LIT> ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( SymTLSDescLo12 ) ; Ldr . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitToStreamer ( * OutStreamer , Ldr ) ; MCInst Add ; Add . setOpcode ( <STR_LIT> ) ; Add . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Add . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Add . addOperand ( SymTLSDescLo12 ) ; Add . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <NUM_LIT> ) ) ) ; EmitToStreamer ( * OutStreamer , Add ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( <STR_LIT>


<s> operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; if ( ! cfun -> machine -> fp_size && ! cfun -> machine -> gp_size && ! cfun -> machine -> lp_size && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) { return <STR_LIT> ; } else { if ( REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) pop_en4_only_p = <NUM_LIT> ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , pop_en4_only_p ? <STR_LIT> : <STR_LIT> , cfun -> machine -> fp_size ? <STR_LIT> : <STR_LIT> , cfun -> machine -> gp_size ? <STR_LIT> : <STR_LIT> , cfun -> machine -> lp_size ? <STR_LIT> : <STR_LIT> ) ; } } output_asm_insn ( pattern , operands


<s> switch ( AddrMode ) { case <STR_LIT> : CodesizeEstimate += <NUM_LIT> ; return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; } return false


<s> bool <ISA_LIT>TargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const { return


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; if ( VT . is256BitVector ( ) ) { SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) , Vec , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; Vec = Insert128BitVector ( InsV , Vec , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clob


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS ,


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( is64Bit ( ) && IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } return


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( OpFlag )


<s> SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , PtrTy , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ) ; } case <STR_LIT> : { ConstantPoolSDNode * CN = cast < ConstantPoolSDNode > ( Node ) ; const Constant * C = CN -> getConstVal ( ) ; SDValue CP = CurDAG -> getTargetConstantPool ( C , CN -> getValueType ( <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , CP ) ; return NULL ; } case <STR_LIT> : { SDNode * ResNode = <NUM_LIT> ; if ( cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) == <NUM_LIT> ) { EVT Ty = Node -> getValueType ( <NUM_LIT> ) ; assert ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && <STR_LIT> ) ; uint16_t Register = Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ResNode = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , Register , Ty ) . getNode ( ) ; } if ( ! ResNode ) { ResNode = TrySelectToMoveImm ( Node ) ; } if ( ResNode ) return ResNode ; ResNode = SelectToLitPool ( Node ) ; assert ( ResNode && <STR_LIT> ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; Node = ResNode ; break ; } case <STR_LIT> : { if ( A64Imms :: isFPImm ( cast < ConstantFPSDNode > ( Node ) -> getValueAPF (


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { if ( TargetTriple . getArch ( ) == Triple :: sic ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { CPU = <STR_LIT> ; } else if ( CPU == <STR_LIT> ) { CPU = <STR_LIT> ; return * this ; } else if ( CPU != <STR_LIT> && CPU != <STR_LIT> ) { CPU = <STR_LIT> ; } } else { errs ( ) << <STR_LIT> << TargetTriple . getArch ( ) << <STR_LIT>


<s> bool <ISA_LIT>MachineFunctionInfo :: globalBaseRegFixed ( ) const { return


<s> bool IsO32 ( ) const { return ThisABI == ABI ::


<s> return __builtin_ia32_vcvtph2qq128_mask ( __B , _mm_setzero_si128 ( ) ,


<s> imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeAddrModeImm12Operand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> unsigned MaxRegs = <NUM_LIT> ; unsigned RegMask = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MaxRegs ; ++ I ) if ( ( RegMask & ( <NUM_LIT> << I ) ) != <NUM_LIT> ) ++ NumRegs ; O << <STR_LIT> ; unsigned Printed = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MaxRegs ; ++ I ) { unsigned Reg = RegMask & ( <NUM_LIT> << I ) ; if ( Reg == <NUM_LIT> ) continue ; O << getRegisterName ( MatrixZADRegisterTable [ I ]


<s> } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumbFunction ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( AFI -> isThumb2Function ( ) && FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } if ( RegInfo -> hasBasePointer ( MF ) ) { FrameReg = RegInfo ->


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , MII ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits


<s> machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vsldoi_v4sf || icode == CODE_FOR_altivec_vsldoi_v2df || icode == CODE_FOR_altivec_vsldoi_v4si || icode == CODE_FOR_altivec_vsldoi_v8hi || icode == CODE_FOR_altivec_vsldoi_v16qi ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vsx_xxpermdi_v2df || icode == CODE_FOR_vsx_xxpermdi_v2di || icode == CODE_FOR_vsx_xxpermdi_v2df_be || icode == CODE_FOR_vsx_xxpermdi_v2di_be || icode == CODE_FOR_vsx_xxpermdi_v1ti || icode == CODE_FOR_vsx_xxpermdi_v4sf || icode == CODE_FOR_vsx_xxpermdi_v4si || icode == CODE_FOR_vsx_xxpermdi_v8hi || icode == CODE_FOR_vsx_xxpermdi_v16qi || icode == CODE_FOR_vsx_xxsldwi_v16qi || icode == CODE_FOR_vsx_xxsldwi_v8hi || icode == CODE_FOR_vsx_xxsldwi_v4si || icode == CODE_FOR_vsx_xxsldwi_v4sf || icode == CODE_FOR_vsx_xxsldwi_v2di || icode == CODE_FOR_vsx_xxsldwi_v2df ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vsx_set_v2df || icode == CODE_FOR_vsx_set_v2di || icode == CODE_FOR_bcdadd_v16qi || icode == CODE_FOR_bcdadd_v1ti || icode == CODE_FOR_bcdadd_lt_v16qi || icode == CODE_FOR_bcdadd_lt_v1ti || icode == CODE_FOR_bcdadd_eq_v16qi || icode == CODE_FOR_bcdadd_eq_v1ti || icode == CODE_FOR_bcdadd_gt_v16qi || icode == CODE_FOR_bcdadd_gt_v1ti || icode == CODE_FOR_bcdsub_v16qi || icode == CODE_FOR_bcdsub_v1ti || icode == CODE_FOR_bcdsub_lt_v16qi || icode == CODE_FOR_bcdsub_lt_v1ti || icode == CODE_FOR_bcdsub_eq_v16qi || icode == CODE_FOR_bcdsub_eq_v1ti || icode == CODE_FOR_bcdsub_gt_v16qi || icode == CODE_FOR_bcdsub_gt_v1ti ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfp_ddedpd_dd || icode == CODE_FOR_dfp_ddedpd_td ) { STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfp_denbcd_dd || icode == CODE_FOR_dfp_denbcd_td || icode == CODE_FOR_dfp_denbcd_v16qi ) { STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg0 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfp_dscli_dd || icode == CODE_FOR_dfp_dscli_td || icode == CODE_FOR_dfp_dscri_dd || icode == CODE_FOR_dfp_dscri_td ) { STRIP_NOPS ( arg1 )


<s> addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass

( create<ISA_LIT>OptimizeBarriersPass ( ) ) ;


<s> mips_split_move ( dest , src , mips_insn_split_type ( insn )


<s> if ( Desc . getRecurrenceType ( ) -> isFP128Ty ( ) ) return false ; RecurrenceDescriptor :: RecurrenceKind RecKind = Desc . getRecurrenceKind ( ) ; switch ( RecKind ) { default : break ; case RecurrenceDescriptor :: RK_IntegerAdd : case RecurrenceDescriptor :: RK_IntegerAnd : case RecurrenceDescriptor :: RK_IntegerOr : case RecurrenceDescriptor :: RK_IntegerXor : case RecurrenceDescriptor :: RK_FloatAdd : return true ; } if ( ( RecKind == RecurrenceDescriptor :: RK_FloatMinMax ) || ( RecKind == RecurrenceDescriptor :: RK_IntegerMinMax ) ) { switch ( Desc . getMinMaxRecurrenceKind ( ) ) { default : break ; case RecurrenceDescriptor :: MRK_SIntMax : case RecurrenceDescriptor :: MRK_SIntMin : case RecurrenceDescriptor :: MRK_UIntMax : case RecurrenceDescriptor :: MRK_UIntMin : case RecurrenceDescriptor


<s> Op -> RegList . List2From = reglist [ i ] ; Op -> RegList . List2To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List3From == <NUM_LIT> ) { Op -> RegList . List3From = reglist [ i ] ; Op -> RegList . List3To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List4From == <NUM_LIT> ) { Op -> RegList . List4From = reglist [ i ] ; Op -> RegList . List4To = reglist [ i + <NUM_LIT> ] ; } else { assert ( <NUM_LIT> ) ; } } Op -> StartLoc = S


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return false


<s> if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList


<s> case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformINTRINSIC_WO_CHAINCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : { if ( getTargetMachine ( ) . getOptLevel ( ) > CodeGenOpt :: None ) return PerformINSERTPSCombine ( N , DAG , Subtarget ) ; break ; } case <STR_LIT> : return PerformBUILD_VECTORCombine ( N ,


<s> static SDValue PerformADDCCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { return AddCombineTo64bitMLAL ( N ,


<s> case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP5 : insn -> opcodeType = MAP5 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP6 : insn -> opcodeType = MAP6 ; return consume ( insn , insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) ; return true ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP5 : insn -> opcodeType = MAP5 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP6 : insn -> opcodeType = MAP6 ; return consume ( insn , insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consume ( insn , insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) ; return true ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consume ( insn , insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType =


<s> if ( fndecl != NULL_TREE && TREE_CODE ( fndecl ) == FUNCTION_DECL ) call_abi = ix86_function_abi ( fndecl ) ; else call_abi = ix86_function_type_abi ( fndecl ) ; if ( TARGET_64BIT && call_abi == MS_ABI )


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ; return true


<s> assert ( ( Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) ) return Lower256IntArith ( Op , DAG ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( auto * BVAmt = dyn_cast < BuildVectorSDNode > ( Amt ) ) { if ( auto * RotateConst = BVAmt -> getConstantSplatNode


<s> unsigned CSSize = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getCalleeSavedStackSize ( ) ; return alignTo ( CSSize + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ,


<s> FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi


<s> MVT OpVT = A . getSimpleValueType ( ) ; MVT VT = <STR_LIT> ( <STR_LIT> , OpVT . getVectorNumElements (


<s> Value * <ISA_LIT>TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAtLeastAcquire ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr ,


<s> void relaxInstruction ( const MCInst & Inst ,


<s> return ( __m256d ) __builtin_ia32_insertf64x2_256_mask ( ( __v4df ) __A , ( __v2df )


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes ,

unsigned Alignment , unsigned AddrSpace ) const {


<s> static SDValue getAbsolute ( SelectionDAG & DAG , SDLoc DL , SDValue Op , bool IsNegative ) { Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op ) ; if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <NUM_LIT>


<s> if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitPad ( CE ->


<s> case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitCOPY_FW ( MI , BB ) ; case <STR_LIT> : return emitCOPY_FD ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FW ( MI , BB ) ; case <STR_LIT> : return emitINSERT_FD ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitINSERT_DF_VIDX ( MI , BB , <NUM_LIT> , true ) ; case <STR_LIT> : return emitFILL_FW ( MI , BB ) ; case <STR_LIT> : return emitFILL_FD ( MI , BB ) ; case <STR_LIT> : return emitFEXP2_W_1 ( MI , BB ) ; case <STR_LIT> : return emitFEXP2_D_1 ( MI , BB ) ; case <STR_LIT> : return emitCapFloat32Load ( MI , BB ) ; case <STR_LIT> : return emitCapFloat64Load ( MI , BB ) ; case <STR_LIT> : return emitCapFloat32Store ( MI , BB ) ; case


<s> if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> Parser . Lex ( ) ; if ( Kind . empty ( ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: SVEVector , S , getLoc ( ) , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { return MatchOperand_Success ; } Parser . Lex ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) { return MatchOperand_NoMatch ; } StringRef value = TokE . getString ( ) ; const char * extTypeName = getGPROffsetExtTypeName ( value ) ; if ( ! extTypeName ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( extTypeName , false , SS


<s> unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo (


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName )


<s> const MCExpr * Disp ; const MCExpr * Length ; if ( parseAddress ( Base , Disp , Index , IsVector , Length , Regs , RegKind ) ) return MatchOperand_ParseFail ; if ( IsVector && MemKind != BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! IsVector && MemKind == BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Index && MemKind != BDXMem && MemKind != BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Length && MemKind != BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length && MemKind == BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; return DAG


<s> static unsigned bitmap_popcount ( const sbitmap bmap ) { unsigned int count = <NUM_LIT>


<s> for ( int Shift = <NUM_LIT> ; Shift <= RegWidth - <NUM_LIT> ; Shift += <NUM_LIT> ) if ( ( Value & ~ ( <NUM_LIT> <<


<s> } rtx cstore_pat = PATTERN ( e . cstore . insn ) ; if ( GET_CODE ( cstore_pat ) == PARALLEL ) for ( int i = <NUM_LIT> ; i < XVECLEN ( cstore_pat , <NUM_LIT> ) ; ++ i ) { rtx x = XVECEXP ( cstore_pat , <NUM_LIT> , i ) ; if ( x != e . cstore . set_rtx && GET_CODE ( x ) == SET && reg_referenced_p ( m_ccreg , x ) ) { log_msg ( <STR_LIT> ) ; log_insn ( e . cstore . insn ) ; log_return ( false , <STR_LIT> ) ; } } if ( modified_in_p ( m_ccreg , e . cstore . insn ) && ! ( reg_dead_after_insn ( m_ccreg , e . cstore . insn ) || reg_unused_after_insn ( m_ccreg , e . cstore . insn ) ) ) { log_msg ( <STR_LIT> ) ; log_insn ( e . cstore . insn ) ; log_return ( false , <STR_LIT> ) ; } rtx_insn * prev_insn = e . cstore . insn ; for ( std :: vector < set_of_reg > :: const_reverse_iterator i = e . cstore_reg_reg_copies . rbegin ( ) ; i != e . cstore_reg_reg_copies . rend ( ) ; ++ i ) { if ( ! reg_dead_after_insn ( i -> set_src ( ) , i ->


<s> set_mem_size ( mem , GET_MODE_SIZE ( mode ) ) ; do_load_for_compare ( dest , mem , mode


<s> Inst . addOperand ( MCOperand :: createImm ( CE ->


<s> assert ( StackOffsetOperand . isImm ( ) && <STR_LIT> ) ; getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ; assert ( Scale != <NUM_LIT> && <STR_LIT> ) ; int64_t NewImm = ( Offset + <NUM_LIT> ) / Scale ; StackOffsetOperand . setImm (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BB ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return EmitLoweredTLSAddr ( MI , BB ) ; case <STR_LIT> : return EmitLoweredCatchRet ( MI , BB ) ; case <STR_LIT> : return EmitLoweredCatchPad ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return EmitLoweredSegAlloca ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : return EmitLoweredTLSCall ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return EmitLoweredSelect ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : { DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned PushF = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned Pop = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * Push = BuildMI ( * BB , MI , DL , TII -> get ( PushF ) ) ; Push -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( Pop ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; return BB ; } case <STR_LIT> : case <STR_LIT> : { DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned Push = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned PopF = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , MI , DL , TII -> get ( Push ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( PopF ) ) ; MI . eraseFromParent ( ) ; return BB ; } case <STR_LIT> : case <STR_LIT> : return EmitLoweredAtomicFP ( MI , BB


<s> static bool needsFP ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> if ( mergedOpcode ( MI . getOpcode ( ) , false ) == <NUM_LIT> ) return false ; const MachineMemOperand * MemOperand = * MI . memoperands_begin


<s> const MCExpr * Expr = getMemOffset ( ) ; addExpr ( Inst ,


<s> Opc = getBroadcastOpcode ( I , RC , Subtarget ) ; } else { unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlignment ( ) >= Alignment ; Opc = getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , Subtarget ) ; } Load = DAG . getMachineNode ( Opc , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load ) , MMOs ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; BeforeOps . insert ( BeforeOps . end ( ) , AfterOps . begin ( ) , AfterOps . end ( ) ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isNullConstant ( BeforeOps [ <NUM_LIT> ] ) ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += Scale ) { int StartIdx = - <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != Scale ; ++ j ) { int EltIdx = SVOp -> getMaskElt ( i + j ) ; if ( EltIdx < <NUM_LIT> )


<s> SDLoc DL ( Op ) ; EVT DstTy = Op . getValueType ( ) ; if ( ! IsSigned && ! isIntegerTypeFTOL ( DstTy ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; if ( ! IsSigned && isIntegerTypeFTOL ( DstTy ) ) Opc = <STR_LIT> ; else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc =


<s> if ( ! isShuffleMaskConsecutive ( SVOp , NumZeros , NumElems - <NUM_LIT> , <NUM_LIT> , NumElems , OpSrc ) ) return false ; isLeft = true ; ShAmt = NumZeros ; ShVal = SVOp -> getOperand ( OpSrc ) ; return


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val )


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( create<ISA_LIT>ParallelDSPPass (


<s> PM . add ( create<ISA_LIT>ExpandPseudoPass ( * this


<s> SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getValueType ( ) != <STR_LIT> )


<s> unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode (


<s> static bool CC_<ISA_LIT>_AAPCS_Custom_f64 ( unsigned & ValNo , EVT & ValVT , EVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ; return true


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; auto & TPC = getAnalysis < TargetPassConfig > (


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Offset , PseudoSourceValue :: getGOT


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = getFrameRegister ( MF ) ; int64_t Offset = ( TFI -> getFrameIndexOffset ( MF , FrameIndex ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; const MCExpr * Expr = MO . getExpr ( ) ; const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( SExpr && SExpr -> getSubExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef && <STR_LIT> ) ; const MCSymbolRefExpr * SymExpr = cast < MCSymbolRefExpr > ( SExpr -> getSubExpr ( ) ) ; assert ( SymExpr -> getSymbol ( ) . getName ( ) == <STR_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; } MCFixupKind Kind = MCFixupKind ( SExpr -> getFixupKind ( ) ) ; Fixups . push_back ( MCFixup :: create (


<s> print_rtl_single ( dump_file , i ) ; fprintf ( dump_file , <STR_LIT> ) ; } rtx_insn * seq = split_insns ( PATTERN ( i ) , curr_insn ) ; if ( seq == NULL ) return std :: make_pair ( i , i ) ; for ( rtx_insn * s = seq ; s != NULL ; s = NEXT_INSN ( s ) ) if ( INSN_P ( s ) && rtx_equal_p ( PATTERN ( s ) , PATTERN ( i ) ) ) return std :: make_pair ( i , i ) ; unshare_all_rtl_in_chain ( seq ) ; rtx_insn * seqlast = seq ; while ( NEXT_INSN ( seqlast ) != NULL ) seqlast = NEXT_INSN ( seqlast ) ; if ( rtx_insn * iprev = PREV_INSN ( i ) ) SET_NEXT_INSN ( iprev ) = seq ; if ( rtx_insn * inext = NEXT_INSN ( i ) ) SET_PREV_INSN ( inext ) = seqlast ; SET_PREV_INSN ( seq ) = PREV_INSN ( i ) ; SET_NEXT_INSN ( seqlast ) = NEXT_INSN ( i ) ; SET_PREV_INSN ( i ) = NULL ; SET_NEXT_INSN ( i ) = NULL ; for ( i = seq ; ; i = NEXT_INSN ( i ) ) { std :: pair < rtx_insn * , rtx_insn * > ii = sh_try_split_insn_simple ( i , curr_insn , n + <NUM_LIT> ) ; if ( i == seq ) seq = ii .


<s> CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = <STR_LIT> ; } else if ( el_mode == SFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = <STR_LIT> ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) : TargetLowering ( TM ) , Subtarget ( & STI ) { setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT>


<s> SDValue Cmp ; if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; else Cmp = DAG . getNode ( <STR_LIT> ,


<s> return __builtin_mve_vqrshlq_n_uv8hi ( __a ,


<s> return ! TARGET_SH4 || TARGET_FMOVD ||


<s> if ( ! isInt < <NUM_LIT> > ( Offset ) ) { BuildMI ( * MI . getParent ( ) , II , DL , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( static_cast < uint32_t > ( Offset ) >> <NUM_LIT> ) ; BuildMI ( * MI . getParent ( ) , II , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( Offset & <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , DL , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { BuildMI ( * MI . getParent ( ) , II , DL , HasNegOffset ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg ) . addReg ( Reg ) . addImm ( LPCC :: ICC_T ) ; MI . eraseFromParent ( ) ; return ; } if ( isSPLSOpcode ( MI . getOpcode ( ) ) || isRMOpcode ( MI . getOpcode ( ) ) ) { MI . setDesc ( TII -> get ( getRRMOpcodeVariant ( MI . getOpcode ( ) ) ) ) ; if ( HasNegOffset ) { assert ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == LPAC :: ADD ) && <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( LPAC :: SUB ) ; } } else llvm_unreachable ( <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> bool Done = false ; while ( ! Done ) { bool UpdateLocLex = true ; if ( Tok . getString ( ) . startswith ( <STR_LIT> ) ) break ; if ( SM . getStopOnLBrac ( ) && getLexer ( ) . getKind ( ) == AsmToken :: LBrac ) break ; AsmToken :: TokenKind TK = getLexer ( ) . getKind ( ) ; switch ( TK ) { default : { if ( SM . isValidEndState ( ) ) { Done = true ; break ; } return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } case AsmToken :: EndOfStatement : { Done = true ; break ; } case AsmToken :: String : case AsmToken :: Identifier : { unsigned TmpReg ; const MCExpr * Val ; SMLoc IdentLoc = Tok . getLoc ( ) ; StringRef Identifier = Tok . getString ( ) ; if ( TK != AsmToken :: String && ! ParseRegister ( TmpReg , IdentLoc , End ) ) { SM . onRegister ( TmpReg ) ; UpdateLocLex = false ; break ; } else { if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else { if ( Identifier . find ( '.' ) != StringRef :: npos ) { return false ; } else { InlineAsmIdentifierInfo & Info = SM . getIdentifierInfo ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return true ; } } SM . onIdentifierExpr ( Val , Identifier ) ; UpdateLocLex = false ; break ; } return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } case AsmToken :: Integer : { StringRef ErrMsg ; if ( isParsingInlineAsm ( ) && SM . getAddImmPrefix ( ) ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , Tok . getLoc ( ) ) ; SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal (


<s> Value * <ISA_LIT>IREmitter :: visitINTRET_FLAG ( const SDNode


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( <NUM_LIT> ) , DarwinDirective ( <STR_LIT> ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , Is<ISA_LIT>64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( CPUName == <STR_LIT> ) CPUName = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName )


<s> static rtx gen_gpr_to_xmm_move_src ( enum machine_mode vmode , rtx gpr ) { switch ( GET_MODE_NUNITS ( vmode ) ) { case <NUM_LIT> : gcc_unreachable ( ) ; case <NUM_LIT> : return gen_rtx_VEC_CONCAT ( vmode , gpr , CONST0_RTX ( GET_MODE_INNER ( vmode ) ) ) ; default : return gen_rtx_VEC_MERGE ( vmode , gen_rtx_VEC_DUPLICATE ( vmode , gpr ) , CONST0_RTX ( vmode )


<s> if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load || insn_entry [ uid2 ] . is_store ) return false ; break ; } rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) ) return ( MEM_ALIGN ( dest ) >= <NUM_LIT> ) ; } return false


<s> ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = const_double_from_real_value ( r_pow , DFmode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode


<s> if ( EnableMachineCombinerPass ) addPass ( &


<s> uint64_t SatWidth = SatVT . getScalarSizeInBits ( ) ; uint64_t DstWidth = DstVT . getScalarSizeInBits ( ) ; assert ( SatWidth <= DstWidth && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { SrcVal = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , SrcVal ) ; SrcVT = <STR_LIT> ; } else if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) ) && DstVT == SatVT && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ; if ( DstWidth < SatWidth ) return SDValue ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sextOrSelf ( DstWidth ) , DL , DstVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sextOrSelf ( DstWidth ) , DL , DstVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , Min , MaxC ) ; } else


<s> break ; case SECCAT_DATA_REL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_BSS : sname = <STR_LIT> ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = <STR_LIT> ; flags = <NUM_LIT> ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( sname ) { if ( ! DECL_P ( decl ) ) return get_section (


<s> if ( ! TARGET_LINK_STACK ) return ; get_ppc476_thunk_name ( name ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section )


<s> unsigned SIndex = <NUM_LIT> ; unsigned EIndex = MemOps . size ( ) ; do { const MachineInstr * MI = MemOps [ SIndex ] . MI ; int Offset = MemOps [ SIndex ] . Offset ; const MachineOperand & PMO = getLoadStoreRegOp ( * MI ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( PReg ) ; unsigned Latest = SIndex ; unsigned Earliest = SIndex ; unsigned Count = <NUM_LIT> ; bool CanMergeToLSDouble = STI -> isThumb2 ( ) && isNotVFP && isValidLSDoubleOffset ( Offset ) ; if ( STI -> isCortexM3 ( ) && isi32Load ( Opcode ) && PReg == getLoadStoreBaseOp ( * MI ) . getReg ( ) ) CanMergeToLSDouble = false ; bool CanMergeToLSMulti = true ; if ( STI -> isSwift ( ) && ! isNotVFP && ( PRegNum % <NUM_LIT> ) == <NUM_LIT> ) CanMergeToLSMulti = false ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) CanMergeToLSMulti = CanMergeToLSDouble = false ; for ( unsigned I = SIndex + <NUM_LIT> ; I < EIndex ; ++ I , ++ Count ) { int NewOffset = MemOps [ I ] . Offset ; if ( NewOffset != Offset + ( int ) Size ) break ; const MachineOperand & MO = getLoadStoreRegOp ( * MemOps [ I ] . MI ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) break ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; bool PartOfLSMulti = CanMergeToLSMulti ; if ( PartOfLSMulti ) { if ( RegNum <= PRegNum ) PartOfLSMulti = false ; else if ( ! isNotVFP && RegNum != PRegNum + <NUM_LIT> ) PartOfLSMulti = false ; } bool PartOfLSDouble = CanMergeToLSDouble && Count <= <NUM_LIT> ; if ( ! PartOfLSMulti && ! PartOfLSDouble ) break ; CanMergeToLSMulti &= PartOfLSMulti ; CanMergeToLSDouble &= PartOfLSDouble ; unsigned Position = MemOps [ I ] . Position ; if ( Position < MemOps [ Latest ] . Position ) Latest = I ; else if ( Position > MemOps [ Earliest ] . Position ) Earliest = I ; Offset += Size ; PRegNum = RegNum ; } MergeCandidate * Candidate = new ( Allocator


<s> bool <ISA_LIT>ElimCompare :: convertToLoadAndTest ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = TII -> getLoadAndTest ( MI . getOpcode ( ) ) ; if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers


<s> if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( is64Bit


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( create<ISA_LIT>DeadRegisterDefinitions


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N , SDValue & Offset , SDValue & Opc ) { unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( FlagSfiLoad && ( Op -> getOpcode ( ) == <STR_LIT> ) ) || ( FlagSfiStore && ( Op -> getOpcode ( ) == <STR_LIT> ) ) ; Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! restrict_addressing_modes_for_nacl && Sh ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { return AsmPrinter :: runOnMachineFunction


<s> fprintf ( asm_out_file , <STR_LIT> , * ( const char * const * )

directive , XCOFF_CSECT_DEFAULT_ALIGNMENT_STR ) ;


<s> Iter Filler ; RegDU . setCallerSaved ( * Slot ) ; if ( searchRange ( MBB , llvm :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Filler ) ) { MBB . splice ( llvm :: next ( Slot


<s> BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT>


<s> return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv2di


<s> MemRefBegin += <STR_LIT> ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; OffsetIsScalable = false ; BaseOps . push_back ( BaseOp


<s> void <ISA_LIT>MachObjectWriter :: Record<ISA_LIT>Relocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) { const MCFixupKind FK = Fixup . getKind ( ) ; const unsigned Log2Size = getFixupKindLog2Size ( FK ) ; const bool IsPCRel = Writer -> isFixupKindPCRel ( Asm , FK ) ; const unsigned RelocType = getRelocType ( Target , FK , IsPCRel ) ; if ( Target . getSymB ( ) && RelocType != MachO :: <ISA_LIT>_RELOC_BR24 && RelocType != MachO :: <ISA_LIT>_RELOC_BR14 ) { RecordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; return ; } const MCSymbolData * SD = nullptr ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = RelocType ; if ( Target . isAbsolute


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) return Error ( L , <STR_LIT> ) ; bool WasThumb = isThumb ( ) ; Triple T ; MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( <STR_LIT> , ( <STR_LIT> + <STR_LIT> ( ID ) ) . str ( ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; FixModeAfterArchChange ( WasThumb , L ) ; getTargetStreamer ( ) . emitArch ( ID


<s> unsigned imod = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> unsigned flags = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> Triple TheTriple ( TT ) ; bool isV9 = ( TheTriple . getArch ( ) == Triple :: sparcv9 ) ; if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { MCInst Inst ; unsigned MatchResult ; MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( MatchResult ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ; ++ I ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand


<s> const_rtx operand2 = XEXP ( expr , <NUM_LIT> ) ; return ( REG_P ( operand1 ) && REG_P ( operand2 ) ) ; } return false


<s> const char * output_387_reg_move ( rtx insn , rtx * operands ) { if ( REG_P ( operands [ <NUM_LIT> ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [


<s> inline vector signed short vec_vupkhsb ( vector signed


<s> return ( ( qword ) ( vec_splat ( ( vec_uint4 ) ( si_from_uint ( ( unsigned int )


<s> switch ( E -> getKind ( ) ) { case MCExpr :: Target : case MCExpr :: Constant : return nullptr ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( E ) ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; default : return nullptr ; } return MCSymbolRefExpr :: create ( & SRE -> getSymbol ( ) , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = ExtractModifierFromExpr ( UE -> getSubExpr ( ) , Variant ) ; if ( ! Sub ) return nullptr ; return MCUnaryExpr :: create ( UE -> getOpcode ( ) , Sub , Context ) ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; <ISA_LIT>MCExpr :: VariantKind LHSVariant , RHSVariant ; const MCExpr * LHS = ExtractModifierFromExpr ( BE -> getLHS ( ) , LHSVariant ) ; const MCExpr * RHS = ExtractModifierFromExpr ( BE -> getRHS ( ) , RHSVariant ) ; if ( ! LHS && ! RHS ) return nullptr ; if ( ! LHS ) LHS = BE -> getLHS ( ) ; if ( ! RHS ) RHS


<s> static DecodeStatus DecodeT2AddrModeImm7s4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7S4 ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


REG || REGNO ( elt_reg ) != GP_REGNUM ) return false ;


<s> bool <ISA_LIT>AsmParser :: canUseATReg ( )


<s> MachineInstr * DefMI = getForwardingDefMI ( MI , ForwardingOperand , SeenIntermediateUse ) ; if ( ! DefMI ) return false ; assert ( ForwardingOperand < MI . getNumOperands ( ) && <STR_LIT> ) ; bool IsForwardingOperandKilled = MI . getOperand ( ForwardingOperand ) . isKill ( ) ; bool KillFwdDefMI = ! SeenIntermediateUse && IsForwardingOperandKilled ; if ( KilledDef && KillFwdDefMI ) * KilledDef = DefMI ; if ( RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) != <STR_LIT> && transformToNewImmFormFedByAdd ( MI , * DefMI , ForwardingOperand ) ) return true ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; bool HasImmForm = instrHasImmForm ( MI . getOpcode ( ) , IsVFReg , III , PostRA


<s> b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmple ( a , b ) ; return ( __m128d ) _mm_setr_pd ( c [ <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFSINCOS ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetDarwin ( ) ) ; SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const Align StackAlign = DL . getPrefTypeAlign ( RetTy ) ; int FrameIdx = MFI . CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt =


<s> auto Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; const MCExpr * Expr = Fixup . getValue ( ) ; switch ( static_cast < unsigned > ( Fixup . getKind ( ) ) ) { default : { const MCFixupKindInfo & Info = MAB . getFixupKindInfo ( Fixup . getKind ( ) ) ; report_fatal_error ( Twine ( <STR_LIT> ) + Info . Name ) ; } case FK_Data_4 : switch ( Modifier ) { default : return COFF :: IMAGE_REL_ARM64_ADDR32 ; case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_ARM64_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_ARM64_SECREL ; } case FK_Data_8 : return COFF :: IMAGE_REL_ARM64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_ARM64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_ARM64_SECREL ; case <STR_LIT> : if ( const <ISA_LIT>MCExpr * A64E = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind = A64E -> getKind ( ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 ) return COFF :: IMAGE_REL_ARM64_SECREL_LOW12A ; if ( RefKind == <ISA_LIT>MCExpr :: VK_SECREL_HI12 ) return COFF :: IMAGE_REL_ARM64_SECREL_HIGH12A ; } return COFF :: IMAGE_REL_ARM64_PAGEOFFSET_12A ; case <STR_LIT> : case <STR_LIT> : case


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 : return


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; HasLEB128 = true


<s> bool HasAnyUndefs ; if ( ! Subtarget -> hasMSA ( ) || ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; if ( Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget -> isLittle ( ) ) && SplatBitSize <= <NUM_LIT> ) { if ( SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> ) return SDValue ( ) ; if ( SplatValue . isSignedIntN ( <NUM_LIT> ) ) return Op ; EVT ViaVecTy ; switch ( SplatBitSize ) { default : return SDValue ( ) ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : return SDValue ( ) ; } SDValue Result = DAG . getConstant ( SplatValue , ViaVecTy ) ; if ( ViaVecTy != ResTy ) Result = DAG . getNode ( <STR_LIT> , SDLoc ( Node ) , ResTy , Result ) ; return


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( IMMEDIATE ) ; Op -> Imm . Value = Value ; Op -> StartLoc = Start ; Op -> EndLoc = End ; return


<s> UsedRegs . insert ( Reg ) ; if ( IsLoad ) { for ( const MachineOperand & MO : MI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isDead ( ) ) continue ; assert ( MO . isImplicit ( ) ) ; unsigned DefReg = MO . getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) != ImpDefs . end ( ) ) continue ; if ( MI -> readsRegister ( DefReg ) ) continue ; ImpDefs . push_back ( DefReg ) ; } } } typedef MachineBasicBlock :: iterator iterator ; MachineInstr * LatestMI = Cand . Instrs [ Cand . LatestMIIdx ] ; iterator InsertBefore = std :: next ( iterator ( LatestMI ) ) ; MachineBasicBlock & MBB = * LatestMI -> getParent ( ) ; unsigned Offset = getMemoryOpOffset ( * First ) ; unsigned Base = getLoadStoreBaseOp ( * First ) . getReg ( ) ; bool BaseKill = LatestMI -> killsRegister ( Base ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags (


<s> void <ISA_LIT>InstPrinter :: printMemOperandEA ( const MCInst * MI , int opNum , const MCSubtargetInfo & STI , raw_ostream & O ) { printOperand ( MI , opNum ,


<s> assert ( VT . isSimple ( ) && <STR_LIT> ) ; bool needsLowering = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT>


<s> if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; In = DAG . getBitcast ( InVT , In ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) { assert ( <NUM_LIT> &&


<s> if ( getStackEntry ( <NUM_LIT> ) == FPRegNo ) { popStackAfter ( I ) ; return ; } I = freeStackSlotBefore ( ++ I ,


<s> case Instruction :: FCmp : return false ; case Instruction :: ICmp : case Instruction :: Add : return ScalarBits < <NUM_LIT> && ( ScalarBits * cast < VectorType > ( Ty ) -> getNumElements ( ) ) % <NUM_LIT> == <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return false


<s> int NumOps = getNumMemOps ( cast < IntrinsicInst > ( I )


<s> buf -> cpr1_size = pInfo . m_Cpr1Size ; buf -> cpr2_size = pInfo . m_Cpr2Size ; buf -> fp_abi = pInfo . m_FpAbi ; buf -> isa_ext = pInfo . m_IsaExt ; buf -> ases = pInfo .


<s> void <ISA_LIT>Relocator :: scanRelocation ( Relocation & pReloc , IRBuilder & pLinker , Module & pModule , LDSection & pSection , Input & pInput ) { if ( LinkerConfig :: Object == config ( ) . codeGenType ( ) ) return ; ResolveInfo * rsym = pReloc . symInfo ( ) ; assert ( rsym != NULL


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; Value = SignExtend32 < <NUM_LIT> >


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBUtils -> adjustBBSize ( MBB , TII -> getInstSizeInBytes ( MBB -> back ( ) ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBUtils -> adjustBBSize ( MBB , TII -> getInstSizeInBytes ( MBB -> back ( ) ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false ,


<s> for ( reg = LAST_TARGET_REG ; reg >= FIRST_TARGET_REG ; reg -- ) if ( ( ! call_really_used_regs [ reg ] || interrupt_handler ) && ! TEST_HARD_REG_BIT ( * live_regs_mask , reg ) ) stack_space += GET_MODE_SIZE ( REGISTER_NATURAL_MODE ( reg ) ) ; return


<s> } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_<ISA_LIT>_PURECODE ; TextSection = Ctx . getELFSection ( <STR_LIT> , Type , Flags , <NUM_LIT> , <STR_LIT> ,


<s> ConstantPools -> emitAll ( Streamer ) ; if ( MarkBTIProperty ) emitNoteSection (

ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel


<s> SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL ,


<s> Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock (


<s> LLVMContext * Context = DAG . getContext ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT ANDVT = VT . is128BitVector ( ) ? <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> EVT VT = Op . getValueType ( ) ; SDValue Zero = DAG . getConstant (


<s> unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , getScratchReg ( ) , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { assert ( StackTop > <NUM_LIT> && <STR_LIT> ) ; -- StackTop


<s> static std :: string computeFSAdditions ( StringRef FS , CodeGenOpt :: Level OL , const Triple & TT ) { std :: string FullFS = std :: string ( FS ) ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch (


<s> <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue Base ; if ( is64Bit ) { Base = GetTLSADDR ( DAG , DAG . getEntryNode ( ) , GA , nullptr , PtrVT , <STR_LIT> , <STR_LIT> , true ) ; } else { SDValue InFlag ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Base = GetTLSADDR ( DAG , Chain , GA , & InFlag


<s> void loongarch_emit_binary ( enum rtx_code code , rtx target , rtx op0


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> return ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( TM

. getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ;