<s> if ( isZeroCost ( DefTID . Opcode ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; else return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT>


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst ) ; else Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> return ( __m128 ) __builtin_ia32_movss ( ( __v4sf ) __A ,


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , ( Is64Bit ) ? true : false ) ; return createELFObjectWriter ( MOTW , OS , IsLittleEndian


<s> bool hasStackFrame ( ) const { return


<s> unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_NOREORDER ; MCA . setELFHeaderEFlags (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo ++ )


<s> unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset &= ~ ( ( <NUM_LIT> << LogAlign ) - <NUM_LIT> ) ; BaseInsertOffset -= UPad ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset >= BBInfo [ UserMBB -> getNumber ( ) + <NUM_LIT> ] . Offset ) BaseInsertOffset = BBInfo [ UserMBB -> getNumber ( ) + <NUM_LIT> ] . Offset - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = WorstCaseAlign ( BaseInsertOffset + <NUM_LIT> , LogAlign , KnownBits ) + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset = RoundUpToAlignment ( EndInsertOffset , <NUM_LIT> << getCPELogAlign ( U . CPEMI ) ) + U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ; } -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getITInstrPredicate ( MI , PredReg ) ; if ( CC != <STR_LIT> ) MI = LastIT ; } NewMBB = splitBlockBeforeInstr (


<s> MachineBasicBlock * PredMBB = nullptr ; if ( MBB -> pred_size ( ) == <NUM_LIT> ) PredMBB = * MBB -> pred_begin ( ) ; if ( MBB -> pred_size ( ) == <NUM_LIT> && Loop != nullptr &&


<s> case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT>


<s> MachineInstr & BrMI = * MBB -> getFirstTerminator ( ) ; BuildMI ( * MBB , BrMI , BrMI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( Cmp ) . add ( BrMI . getOperand ( <NUM_LIT> ) ) ; BrMI . eraseFromParent (


<s> MCSymbol * <ISA_LIT>FunctionInfo :: getPICOffsetSymbol ( ) const { const DataLayout * DL = MF . getTarget ( )


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , &


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI


<s> static unsigned computeBytesPoppedByCalleeForSRet ( const <ISA_LIT>Subtarget * Subtarget , CallingConv :: ID CC , const CallBase * CB ) { if ( Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT ( ) ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv :: HiPE || CC == CallingConv :: Tail ) return <NUM_LIT> ; if ( CB ) if ( CB -> arg_empty ( ) || ! CB -> paramHasAttr ( <NUM_LIT> , Attribute :: StructRet

) || CB -> paramHasAttr ( <NUM_LIT> , Attribute :: InReg ) || Subtarget -> isTargetMCU ( ) ) return <NUM_LIT> ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx


<s> } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize


<s> else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , RelocCST , false ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , RelocCST , false ) ; MCE . addRelocation ( MR ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( Disp ) ; else MCE . emitWordLE ( (


<s> LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! LN -> isVolatile ( ) ) { SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getAlignment ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT>


<s> SmallVector < ArgInfo , <NUM_LIT> > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , OutArgs , DL , MRI , Info . CallConv ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) OutArgs . back ( ) . Flags [ <NUM_LIT> ] . setZExt ( ) ; } SmallVector < ArgInfo , <NUM_LIT> > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , MRI , F . getCallingConv ( ) ) ; bool CanTailCallOpt = isEligibleForTailCallOptimization ( MIRBuilder , Info , InArgs , OutArgs ) ; if ( Info . IsMustTailCall && ! CanTailCallOpt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( CanTailCallOpt ) return lowerTailCall ( MIRBuilder , Info , OutArgs ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , Info . CallConv ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isN64 ( ) ) return DecodeGPR64RegisterClass (


<s> if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C


<s> vld1q_u32 ( const uint32_t * __a ) { return ( uint32x4_t ) __builtin_neon_vld1v4si ( ( const


<s> } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; OS << '[' ; Op . getExpr ( ) -> print ( OS


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else if ( NumBytes ) { ++ NumRedZoneFunctions ; } return ; } int FPOffset = <NUM_LIT> ; if ( HasFP ) { assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> && ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; FPOffset = - ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) * <NUM_LIT> ; assert ( FPOffset >= <NUM_LIT> && <STR_LIT> ) ; } while ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; if ( NumBytes ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) TII -> copyPhysReg ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , false ) ; if ( needsFrameMoves ) { const DataLayout * TD = MF . getTarget ( ) . getDataLayout ( ) ; const int StackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( HasFP ) { unsigned Reg = RegInfo -> getDwarfRegNum ( FramePtr , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> * StackGrowth ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned LR = RegInfo -> getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , LR , StackGrowth ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg , <NUM_LIT> * StackGrowth ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; }


<s> return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT


<s> static rtx mips_frame_set ( rtx mem , rtx reg ) { rtx set ; set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; return


<s> Inst . addOperand ( MCOperand :: createImm (


<s> SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isa < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { GA = cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getGlobal ( ) ; Offset = cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ->


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( )

, false , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DOUT << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { cerr << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && prior ( Start ) != PrevI ) -- Start ; cerr << <STR_LIT> ; Start -> print ( * cerr . stream ( ) , & MF . getTarget ( ) ) ; while ( ++ Start != next ( I ) ) { } } dumpStack ( ) ; ) ; Changed = true ; } assert ( isStackEmpty ( ) && <STR_LIT> ) ; return


<s> const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) { setUsesTOCBasePtr ( * MBB -> getParent ( ) ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) . cloneMemRefs ( MI ) ; } unsigned BaseReg ; if ( MF -> getFunction ( ) . hasFnAttribute ( Attribute :: Naked

) ) BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , SupReg ) . addReg (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { unsigned lsb = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned widthm1 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( widthm1 >= <NUM_LIT> - lsb ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool hasWritebackToken = ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isToken ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) ; bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , Rn , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> + hasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( ! listContainsBase && ! hasWritebackToken && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( listContainsBase && hasWritebackToken ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { if ( listContainsReg ( Inst , <NUM_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT>


<s> case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFP_TO_SINTCombine ( N , DAG ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine (


<s> } assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; unsigned FixupKind ; switch ( cast < MCSymbolRefExpr > ( Expr ) ->


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , * FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg


<s> return __builtin_aarch64_crc32b ( __a ,


<s> O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' :


<s> SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL


<s> static bool aarch64_simd_vector_alignment_reachable ( const_tree type , bool is_packed ) { if ( is_packed )


<s> const MCExpr * getMemOff ( ) const { assert ( ( Kind == k_MemoryImm )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; std :: pair < int , MVT > LT = TLI

-> getTypeLegalizationCost ( DL , VecTy ) ;


<s> return __builtin_mve_vmulq_m_n_uv4si ( __arm_vuninitializedq_u32 ( ) ,


<s> } if ( ! OneUseConstantOp && ! HasVariableMask ) return SDValue ( ) ; APInt UndefElts ( NumMaskElts , <NUM_LIT> ) ; APInt ZeroElts ( NumMaskElts , <NUM_LIT> ) ; APInt ConstantElts ( NumMaskElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > ConstantBitData ( NumMaskElts , APInt :: getNullValue ( MaskSizeInBits ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { UndefElts . setBit ( i ) ; continue ; } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts . setBit ( i ) ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( ! Bits


<s> SDValue Sel = Op . getOperand ( <NUM_LIT> ) ; SDValue Other = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Sel ) ; if ( isOneConstant ( Other ) && <STR_LIT> ( Sel ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Sel -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnesValue ( ) && CFVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS .


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ; return static_cast < <ISA_LIT>TargetStreamer & > (


<s> HasV6Ops = false ; HasV6MOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseInlineJumpTables = ! NoInlineJumpTables ; UseConstIslands = true ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false


<s> Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBInfo [ MBB -> getNumber ( ) ] .


<s> StringRef getPassName ( ) const override { return


<s> BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) , <STR_LIT> , <STR_LIT> ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> )


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MoveToFPReg ( EVT VT , unsigned SrcReg ) { if ( VT == <STR_LIT> ) return <NUM_LIT> ; unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( VT )


<s> void WinEHStatePass :: insertRestoreFrame ( BasicBlock * BB ) { Instruction * Start = BB -> getFirstInsertionPt ( ) ; if ( match ( Start , m_Intrinsic < <STR_LIT> > ( ) ) ) return ; IRBuilder < > Builder ( Start


<s> if ( ! Subtarget . hasBMI ( ) ) return false ; if ( VT != <STR_LIT> && VT != <STR_LIT> )


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( GA ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; unsigned char GVFlags = Subtarget . classifyGlobalReference ( GV ) ; if ( GVFlags &


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; return <STR_LIT> ( MCE -> getValue


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_DISPATCHSETUP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG ,


<s> return ( int16x4_t ) __builtin_neon_vqnegv4hi


<s> if ( Imm < <NUM_LIT> && Imm != ( int ) <NUM_LIT> ) { isNegativeImm = true ; Imm = - Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } } else if ( const ConstantFP * ConstFP = dyn_cast < ConstantFP > ( Src2Value ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) if ( ConstFP -> isZero ( ) && ! ConstFP -> isNegative ( ) ) UseImm = true ; } unsigned CmpOpc ; bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB


<s> unsigned AluCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return LPAC :: isPostOp ( AluCode ) && usesGivenOffset (


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isSwift ( ) ) { int UOps = <NUM_LIT> + NumRegs ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return X


<s> uint64_t CharReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t This1Reg = MRI . createVirtualRegister ( RC ) ; uint64_t This2Reg = MRI . createVirtualRegister ( RC ) ; uint64_t End2Reg = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This1Reg ) . addReg ( Start1Reg ) . addMBB ( StartMBB ) . addReg ( End1Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This2Reg ) . addReg ( Start2Reg ) . addMBB ( StartMBB ) . addReg ( End2Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( CharReg ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( End1Reg , RegState :: Define ) . addReg ( End2Reg , RegState :: Define ) . addReg ( This1Reg ) . addReg ( This2Reg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> addLiveIn ( <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitCMPFP ( const SDNode *


<s> return ( __m128i ) __builtin_ia32_cvttpd2uqq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8


<s> OS << <STR_LIT> << <ISA_LIT>CondCodeToString ( getCondCode ( ) ) << <STR_LIT> ; break ; case k_CCOut : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_ITCondMask : { static const char * MaskStr [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( ( ITMask . Mask & <NUM_LIT> ) == ITMask . Mask ) ; OS << <STR_LIT> << MaskStr [ ITMask . Mask ] << <STR_LIT> ; break ; } case k_CoprocNum : OS << <STR_LIT> << getCoproc ( ) << <STR_LIT> ; break ; case k_CoprocReg : OS << <STR_LIT> << getCoproc ( ) << <STR_LIT> ; break ; case k_CoprocOption : OS << <STR_LIT> << CoprocOption . Val << <STR_LIT> ; break ; case k_MSRMask : OS << <STR_LIT> << getMSRMask ( ) << <STR_LIT> ; break ; case k_Immediate : getImm ( ) -> print ( OS ) ; break ; case k_MemBarrierOpt : OS << <STR_LIT> << MemBOptToString ( getMemBarrierOpt ( ) ) << <STR_LIT> ; break ; case k_Memory : OS << <STR_LIT> << <STR_LIT> << Memory . BaseRegNum ; OS << <STR_LIT> ; break ; case k_PostIndexRegister : OS << <STR_LIT> << ( PostIdxReg . isAdd ? <STR_LIT> : <STR_LIT> ) << PostIdxReg . RegNum ; if ( PostIdxReg . ShiftTy != <STR_LIT> ) OS << <STR_LIT> ( PostIdxReg . ShiftTy ) << <STR_LIT> << PostIdxReg . ShiftImm ; OS << <STR_LIT> ; break ; case k_ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT>


<s> bool IsSubWord = ( BitSize < <NUM_LIT> ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = earlyUseOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; int64_t Disp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand Src2 = earlyUseOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; unsigned BitShift = ( IsSubWord ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; unsigned NegBitShift = ( IsSubWord ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( IsSubWord ) BitSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockAfter ( MI ,


<s> SDLoc dl ( Op ) ; const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext (


<s> void <ISA_LIT>AsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) { if ( PromotedGlobals . count ( GV


<s> unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT>


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( const auto * CI = dyn_cast < ConstantInt > ( Op0 ) ) { if ( CI -> isZero ( ) ) SrcReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else if ( const auto * CF = dyn_cast < ConstantFP > ( Op0 ) ) { if ( CF -> isZero ( ) && ! CF -> isNegative ( ) ) { VT = <STR_LIT> ( VT . getSizeInBits ( ) ) ; SrcReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } } if ( ! SrcReg ) SrcReg = getRegForValue ( Op0 ) ; if ( ! SrcReg ) return false ; Address Addr ; if ( ! computeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return false ; if ( ! emitStore ( VT , SrcReg , Addr , createMachineMemOperandFor


<s> length = strlen ( symb ) ; symbol_name = alloca ( length + <NUM_LIT> ) ; GEN_SYMBOL_NAME_FOR_SYMBOL ( symbol_name , symb , length ) ; sprintf ( lazy_ptr_name , <STR_LIT> , label ) ; if ( MACHOPIC_PURE ) machopic_picsymbol_stub_section ( ) ; else machopic_symbol_stub_section ( ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; if ( MACHOPIC_PURE ) { fprintf ( file , <STR_LIT> , label , label ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name , label ) ; fprintf ( file , <STR_LIT> ) ; } else fprintf ( file , <STR_LIT> , lazy_ptr_name ) ; fprintf ( file , <STR_LIT> , binder_name ) ; if ( MACHOPIC_PURE ) { fprintf ( file , <STR_LIT> , lazy_ptr_name , label ) ; fprintf ( file , <STR_LIT> ) ; } else fprintf ( file , <STR_LIT> , lazy_ptr_name ) ; fprintf ( file , <STR_LIT> ) ; machopic_lazy_symbol_ptr_section ( ) ; fprintf ( file , <STR_LIT> ,


<s> SDValue <ISA_LIT>TargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL (


<s> if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , false ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HSUBBuilder ) ; } if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; if ( SDValue V = combineSubToSubus ( N , DAG , Subtarget ) ) return V ; return combineAddOrSubToADCOrSBB ( N


<s> if ( isa < ConstantPointerNull > ( Op1 ) ) Op1 = Constant :: getNullValue ( TD . getIntPtrType ( Op0 -> getContext ( ) ) ) ; if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( MBB , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C ->


<s> return isMemNoOffset ( false , <NUM_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( MF , dl , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) .

addImm ( Offset ) . addMetadata ( MDPtr ) ;


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_RegMask ; if ( CC == CallingConv :: PreserveMost ) return


<s> unsigned Half = NumElems / <NUM_LIT> ; SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i != Half ; ++ i ) { Mask . push_back ( i + Half ) ; Mask . push_back ( i + NumElems + Half ) ; } return DAG . getVectorShuffle ( VT , dl , V1 , V2 ,


<s> const TargetRegisterClass * getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const override { if ( RC == & <STR_LIT> ) return &


<s> Opcode = <STR_LIT> ; LHS = LHS . getOperand ( <NUM_LIT> ) ; } else if ( isNullConstant ( RHS ) && ! isUnsignedIntSetCC ( CC ) ) { if ( LHS . getOpcode ( ) == <STR_LIT> ) { const SDValue ANDSNode = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , MVT_CC ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesWith ( LHS , ANDSNode ) ; return ANDSNode . getValue ( <NUM_LIT> ) ; } else if ( LHS . getOpcode ( ) == <STR_LIT> ) { return LHS . getValue (


<s> else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT>


<s> unsigned FPRPHI = IsFGR64on<ISA_LIT>32 ? RegInfo . createVirtualRegister ( & <STR_LIT> ) : Fd ; BuildMI ( * BB , MI , DL , TII -> get ( COPYOpc ) , Rtemp ) . addReg ( WPHI ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( MTC1Opc ) , FPRPHI ) . addReg ( Rtemp ) ; if ( IsFGR64on<ISA_LIT>32 ) { unsigned Rtemp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Rtemp2 ) . addReg ( WPHI ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( FPRPHI ) . addReg ( Rtemp2 ) ; } MI . eraseFromParent


<s> return Opc == <STR_LIT> || Opc == <STR_LIT>


<s> EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue (


<s> AnalyzeRetResult ( State , Args ) ; std :: reverse ( RVLocs . begin ( ) , RVLocs . end (


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos


<s> void <ISA_LIT>ExpandISEL :: handleSpecialCases ( BlockISELList & BIL , MachineBasicBlock * MBB ) { IsTrueBlockRequired = false ; IsFalseBlockRequired = false ; auto MI = BIL . begin ( ) ; while ( MI != BIL . end ( ) ) { assert ( isISEL ( * * MI ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * MI << <STR_LIT> ) ; MachineOperand & Dest = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( ! IsADDIInstRequired && ! IsORIInstRequired ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumRemoved ++ ; ( * MI ) -> eraseFromParent ( ) ; MI = BIL . erase ( MI ) ; continue ; } if ( useSameRegister ( TrueValue , FalseValue ) && ( BIL . size ( ) == <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumFolded ++ ; BuildMI ( * MBB , ( * MI ) , dl , TII -> get ( isISEL8 ( * * MI ) ? <STR_LIT>

: <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( FalseValue ) ;


<s> if ( Extract . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * ExtOp = dyn_cast < ConstantSDNode > ( Extract . getOperand ( <NUM_LIT> ) ) ; if ( ! ExtOp ) return false ; Index = ExtOp -> getZExtValue ( ) ; if ( Input && Input != Extract . getOperand ( <NUM_LIT> ) ) return false ; if ( ! Input ) Input = Extract . getOperand ( <NUM_LIT> ) ; Elems = Elems << <NUM_LIT> ; Index = DAG . getDataLayout ( ) . isLittleEndian ( ) ? Index : Index << <NUM_LIT> ; Elems |= Index ; return true ; } ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; i ++ ) { if ( ! isSExtOfVecExtract ( N -> getOperand ( i ) ) ) { return SDValue ( ) ; } } int TgtElemArrayIdx ; int InputSize = Input . getValueType ( ) . getScalarSizeInBits ( ) ; int OutputSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits (


<s> Inst . addOperand ( MCOperand :: CreateImm ( Add - Imm ) ) ; return


<s> return ( uint16x8_t ) __builtin_neon_vshru_nv8hi ( ( int16x8_t )


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; S -> EmitBundleAlignMode ( Log2 ( MIPS_NACL_BUNDLE_ALIGN ) ) ; return S


<s> if ( mem ) return MIB . addImm ( Offset ) . addFrameIndex ( FI ) ; else return MIB . addFrameIndex ( FI )


<s> if ( ! insn -> can_be_optimized ( ) || insn -> is_asm ( ) || insn ->

has_volatile_refs ( ) || insn -> has_pre_post_modify ( ) ) return NULL_RTX ;


<s> } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_SaveList : CSR_64_SwiftError_SaveList ; if ( IsWin64 ) return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList


<s> if ( ShiftName != LowerOp && ShiftName != UpperOp ) { Error ( Parser . getTok ( ) . getLoc ( ) , Op + <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val < Low || Val > High


<s> if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , MemStart , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . parseParenExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex (


<s> addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass


<s> vabdl_high_u32 ( uint32x4_t a , uint32x4_t b ) { uint64x2_t result


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false


<s> unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) { setUsesTOCBasePtr ( * MBB -> getParent ( ) ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } unsigned BaseReg ; if ( MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; else BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( BaseReg ) . addImm ( BPOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getNoPreservedMask ( ) ) ; BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB (


<s> HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple )

&& IN_RANGE ( multiple , - <NUM_LIT> , <NUM_LIT> ) ) ;


<s> if ( Op . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getValueType ( ) != <STR_LIT> ) return Op ; RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128Call ( Op ,


<s> static void mips_output_32bit_xfer ( char direction , unsigned int gpreg , unsigned int


<s> if ( mode == V16QImode ) lvx = gen_altivec_lvx_v16qi ( dest_exp , src_exp ) ; else if ( mode == V8HImode ) lvx = gen_altivec_lvx_v8hi ( dest_exp , src_exp ) ; else if ( mode == V8HFmode ) lvx = gen_altivec_lvx_v8hf ( dest_exp , src_exp ) ; else if ( mode == V4SImode ) lvx = gen_altivec_lvx_v4si ( dest_exp , src_exp ) ; else if ( mode == V4SFmode ) lvx = gen_altivec_lvx_v4sf (


<s> OriginalArgWasFloat . push_back ( ArgTy -> isFloatingPointTy ( ) ) ; OriginalArgWasFloatVector . push_back ( ArgTy -> isVectorTy ( )


<s> MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB


<s> EVT VT = V . getValueType ( ) ; DebugLoc dl = V . getDebugLoc ( ) ; if ( VT . is128BitVector ( ) ) { V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else if ( VT . is256BitVector ( ) ) { int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo , EltNo + <NUM_LIT> , EltNo +

<NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> } ;


<s> if ( ! ThisIsNonZero && ! NextIsNonZero ) continue ; SDValue Elt ; if ( ThisIsNonZero ) { if ( NumZero || NextIsNonZero ) Elt = DAG . getZExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; else Elt = DAG . getAnyExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; } if ( NextIsNonZero ) { SDValue NextElt = Op . getOperand ( i + <NUM_LIT> ) ; if ( i == <NUM_LIT> && NumZero ) NextElt = DAG . getZExtOrTrunc ( NextElt , dl , <STR_LIT> ) ; else NextElt = DAG . getAnyExtOrTrunc ( NextElt , dl , <STR_LIT> ) ; NextElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NextElt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( ThisIsNonZero ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NextElt , Elt ) ; else Elt = NextElt ; } if ( ! V ) { if ( i != <NUM_LIT> || NumZero ) V = getZeroVector ( <STR_LIT> ,


<s> bool has<ISA_LIT>3 ( ) const { return <ISA_LIT>ArchVersion >= <ISA_LIT>3


<s> return decodeRegisterClass ( Inst , RegNo


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts *


<s> bool is<ISA_LIT>32 ( ) const { return <ISA_LIT>ArchVersion


<s> return ( ( HOST_WIDE_INT_UC ( <NUM_LIT> ) << highest_bit_set

) - ( HOST_WIDE_INT_1U << lowest_bit_set ) ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( )


<s> bool <ISA_LIT>IndirectThunks :: doInitialization ( Module &


<s> tree prev_tree = target_option_current_node ; tree cur_tree ; struct cl_target_option * prev_opt ; struct cl_target_option * cur_opt ; if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { cur_tree = arm_valid_target_attribute_tree ( args , & global_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( prev_tree ) ) ; return false ; } target_option_current_node = cur_tree ; arm_configure_build_target ( & arm_active_target , TREE_TARGET_OPTION ( cur_tree ) , false ) ; arm_option_reconfigure_globals ( ) ; } prev_opt = TREE_TARGET_OPTION (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Value = CE -> getValue ( ) ; unsigned Imm =


<s> if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; unsigned Opc = <STR_LIT> ( CC , RC


<s> void hppa_va_start ( tree valist , rtx nextarg ) { nextarg = expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist


<s> else while ( expandAddress ( AM , true ) || ( AM . Index . getNode ( ) && expandAddress ( AM , false ) ) ) continue ; if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) return false ; LLVM_DEBUG ( AM . dump


<s> } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; Chain = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( SubIdx + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , Chain ) ; return NULL


<s> isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) ,

GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> if ( VT == <STR_LIT> ) Addr . Offset = ( <ISA_LIT>SubTarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; unsigned ResultReg


<s> const SDLoc & dl = SDLoc ( Op ) ; const GlobalValue * GV = nullptr ; int64_t Offset = <NUM_LIT> ; const char * ExternalSym = nullptr ; if ( const auto * G = dyn_cast < GlobalAddressSDNode > ( Op ) ) { GV = G -> getGlobal ( ) ; Offset = G -> getOffset ( ) ; } else { const auto * ES = cast < ExternalSymbolSDNode > ( Op ) ; ExternalSym = ES -> getSymbol ( ) ; } const Module & Mod = * DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; unsigned char OpFlags ; if ( ForCall ) OpFlags = Subtarget . classifyGlobalFunctionReference ( GV , Mod ) ; else OpFlags = Subtarget . classifyGlobalReference ( GV , Mod ) ; bool HasPICReg = isGlobalRelativeToPICBase ( OpFlags ) ; bool NeedsLoad = isGlobalStubReference ( OpFlags ) ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; auto PtrVT = getPointerTy ( DAG


<s> RegisterTargetMachine < ThumbTargetMachine > Y (


<s> case CallingConv :: C : case CallingConv :: <ISA_LIT>_StdCall : { NestReg = <STR_LIT> ; FunctionType * FTy = Func -> getFunctionType ( ) ; const AttributeSet & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . hasAttribute ( Idx , Attribute :: InReg ) ) InRegCount += ( TD -> getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: Fast : NestReg = <STR_LIT> ; break ; } SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr , Disp ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Disp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPtr , Addr ) ; const unsigned char MOV32ri = <NUM_LIT> ; const unsigned char N86Reg = TRI -> getEncodingValue ( NestReg ) & <NUM_LIT> ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( MOV32ri | N86Reg , dl , <STR_LIT> ) , Trmp , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; const unsigned char JMP = <NUM_LIT> ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT>


<s> tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ <NUM_LIT> ] = tmp ; } else { CLEAR_HARD_REG_SET ( regset ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DImode , & regset ) ; if ( tmp != NULL_RTX ) { operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; } else { SET_HARD_REG_SET ( regset ) ; CLEAR_HARD_REG_BIT ( regset , regno % <NUM_LIT> == <NUM_LIT> ? regno + <NUM_LIT> : regno - <NUM_LIT> ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ regno % <NUM_LIT> == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] = tmp ; } } gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) % <NUM_LIT> == <NUM_LIT> ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; } } if ( offsets [ <NUM_LIT> ] > offsets [ <NUM_LIT> ] ) { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( const_store ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; } if ( gap != <NUM_LIT> ) return false ; if ( operands_ok_ldrd_strd ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , base , offset , false , load ) ) return true ; if ( TARGET_THUMB2 ) return false ; if ( load && commute ) { std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( operands_ok_ldrd_strd ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , base , offset , false , load )


<s> if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , <NUM_LIT> ) ; else if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE (


<s> addDSPCtrlRegOperands ( false , MI , MF ) ; break ; case <STR_LIT> : addDSPCtrlRegOperands ( true , MI , MF ) ; break ; default : replaceUsesWithZeroReg ( MRI , MI


<s> if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveRegP ( Reg , Offset ) ; return


<s> return ( __m256i ) __builtin_ia32_vpopcountq_v4di_mask ( ( __v4di ) __A , ( __v4di )


<s> assert ( MF . getName ( ) . startswith ( getThunkPrefix ( ) ) ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ & MF ] ( auto T ) { return T . Name == MF . getName ( ) ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; Register ThunkReg = ThunkIt -> Reg ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; assert ( MF . size ( ) == <NUM_LIT> ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; Entry -> addLiveIn ( ThunkReg ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT>

) . addReg ( <STR_LIT> ) . addReg ( ThunkReg ) . addImm ( <NUM_LIT> ) ;


<s> static Optional < Instruction * > instCombineSVEDupX ( InstCombiner & IC , IntrinsicInst & II ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; auto * RetTy = cast < ScalableVectorType > ( II


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; MachineInstr * VRegDef = RegInfo . getUniqueVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return VRegDef && VRegDef -> isImplicitDef


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup .

getOffset ( ) + i ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) processBasicBlock ( * I ) ; if ( checkFnHasLiveInYmm ( MRI ) ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( )


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue Res = tryCombineToBFI ( N , DCI , Subtarget ) ; if ( Res . getNode ( ) ) return


<s> SDValue <ISA_LIT>TargetLowering :: getGlobalReg ( SelectionDAG & DAG , EVT Ty ) const { <ISA_LIT>MachineFunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return DAG . getRegister ( FI -> getGlobalBaseReg ( )


<s> for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx + NumElts ) ) return false ; Idx += <NUM_LIT>


<s> EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk -


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { addPass ( create<ISA_LIT>CallFrameOptimization


<s> static ReverseIter getNonDebugInstr ( ReverseIter B , ReverseIter E ) { for ( ; B != E ; ++ B ) if ( ! B -> isDebugValue


<s> return is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) && ( ! Memory . OffsetRegNum || is<ISA_LIT>LowRegister ( Memory .


<s> SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ; Res = DAG . getNode ( <STR_LIT> , dl


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const <ISA_LIT>RegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - RegInfo -> getSlotSize ( ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; Offset = MaxOffset - Offset + saveAreaOffset ; if ( HasFP && FramePtr == Reg ) continue ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg ,


<s> return ( int64x2_t ) __builtin_aarch64_saddw2v4si


<s> unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa (


<s> RegisterTarget < Triple :: kudeyar > X (


<s> case <STR_LIT> : { Register PredReg ; <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) .


<s> int Size = Mask . size ( ) ; int Scale = <NUM_LIT> / Size ; for ( int Shift = <NUM_LIT> ; Shift < Size ; Shift ++ ) { int ByteShift = Shift * Scale ; bool ZeroableRight = true ; for ( int i = Size - Shift ; i < Size ; i ++ ) { ZeroableRight &= Zeroable [ i ] ; } if ( ZeroableRight ) { bool ValidShiftRight1 = isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Size - Shift , Shift ) ; bool ValidShiftRight2 = isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Size - Shift , Size + Shift ) ; if ( ValidShiftRight1 || ValidShiftRight2 ) { SDValue & TargetV = ValidShiftRight1 ? V1 : V2 ; SDValue V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> getContainingCsect ( ) ) ; OutStreamer -> emitLabel ( CurrentFnDescSym ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( )


<s> RegisterTargetMachine < <ISA_LIT>32TargetMachine > X ( getThe<ISA_LIT>32Target ( )


<s> bool <ISA_LIT>TargetELFStreamer :: emitDirectiveCpRestore ( int Offset , std :: function < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer :: emitDirectiveCpRestore ( Offset , GetATReg ,


<s> case <STR_LIT> : return combineSIGN_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineMERGE ( N , DCI ) ; case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : return combineBR_CCMASK ( N ,


__v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void addRotImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> SDValue Lo64 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg128 ) ; if ( DAG . getDataLayout ( ) . isLittleEndian ( ) ) { if ( isV9 ) Lo64 = DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Lo64 ) ; else Lo64 = LowerF64Op ( Lo64 , dl , DAG , Op . getOpcode ( ) ) ; } else { if ( isV9 ) Hi64 = DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Hi64 ) ; else Hi64 = LowerF64Op ( Hi64 , dl , DAG , Op . getOpcode (


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , SDLoc dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags ,


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Prefetch , Ctx ) ; Op -> Prefetch . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; addPass ( create<ISA_LIT>TLSDynamicCallPass ( )


<s> Register Reg = MatchRegisterName ( RegName ) ; if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) { const MCRegisterInfo * MRI = Subtarget -> getRegisterInfo ( ) ; unsigned DwarfRegNum = MRI -> getDwarfRegNum (


<s> if ( ! insn ) return false ; reg = gen_rtx_REG ( SImode , regno ) ; for ( insn = NEXT_INSN ( insn ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn

) && mep_reg_set_p ( reg , insn ) ) return true ;


<s> if ( Fast ) * Fast = true ; return true


<s> return __builtin_loongson_punpcklhw_u ( s


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind ) ) ; return


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue


<s> } else if ( ! Overlap ) { if ( Clobber ) { TryMerge = true ; Advance = true ; } if ( CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( Offset , Reg , isKill , Position , MBBI ) ) ; ++ NumMemOps ; Advance = true ; } else { for ( MemOpQueueIter I = MemOps . begin ( ) , E = MemOps . end ( ) ; I != E ; ++ I ) { if ( Offset < I -> Offset ) { MemOps . insert ( I , MemOpQueueEntry ( Offset , Reg , isKill , Position , MBBI ) ) ; ++ NumMemOps ; Advance = true ; break ; } else if ( Offset == I -> Offset ) { break ; } } } } } } if ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == E ) TryMerge = true ; } else if ( Advance ) { ++ Position ; ++ MBBI ; if ( MBBI == E ) TryMerge = true ; } else TryMerge = true ; if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( & <STR_LIT> ) ; RS -> forward ( std :: prev ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( std :: prev ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( std :: prev ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ; CurrOpc = - <NUM_LIT> ; CurrSize = <NUM_LIT> ; CurrPred = <STR_LIT> ; CurrPredReg = <NUM_LIT> ; if ( NumMemOps ) { MemOps . clear (


<s> args [ <NUM_LIT> ] = save_expr ( args [ <NUM_LIT> ] ) ; args [ <NUM_LIT> ] = save_expr ( args [ <NUM_LIT> ] ) ; vec < tree , va_gc > * params = make_tree_vector ( ) ; vec_safe_push ( params , args [ <NUM_LIT> ] ) ; vec_safe_push ( params , args [ <NUM_LIT> ] ) ; tree as_c_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDEC ) as_c_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_ADDC ] ; else as_c_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_SUBC ] ; tree call1 = altivec_resolve_overloaded_builtin ( loc , as_c_builtin , params ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , args [ <NUM_LIT> ] ) ; vec_safe_push ( params , args [ <NUM_LIT> ] ) ; tree as_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDEC ) as_builtin = rs6000_builtin_decls


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B ( getThe<ISA_LIT>64elTarget ( )


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { return isLegalAddImmediate (


<s> SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates


<s> MMI = & getAnalysis < MachineModuleInfo > ( ) ; Module & M = const_cast < Module & > ( * MMI -> getModule ( ) ) ; if ( ! MF . getName ( ) . startswith ( ThunkNamePrefix ) ) { if ( InsertedThunks ) return false ; if ( ! STI -> useRetpoline ( ) || STI -> useRetpolineExternalThunk ( ) ) return false ; if ( Is64Bit ) createThunkFunction ( M , R11ThunkName ) ; else for ( StringRef Name : { EAXThunkName , ECXThunkName , EDXThunkName , EDIThunkName } ) createThunkFunction ( M , Name ) ; InsertedThunks = true


<s> getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind ::


<s> aarch64_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; aarch64_simd_types [ Poly8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype = build_distinct_type_copy ( unsigned_intQI_type_node ) ; TYPE_STRING_FLAG ( aarch64_simd_types [ Poly8_t ] . eltype ) = false ; aarch64_simd_types [ Poly16_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype = build_distinct_type_copy ( unsigned_intHI_type_node ) ; aarch64_simd_types [ Poly64_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype = build_distinct_type_copy ( unsigned_intDI_type_node ) ; aarch64_simd_types [ Poly128_t ] . eltype = aarch64_simd_types [ Poly128_t ] . itype = build_distinct_type_copy ( unsigned_intTI_type_node ) ; aarch64_simd_types [ Poly8x8_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly8x16_t ] . eltype = aarch64_simd_types [ Poly8_t ] . itype ; aarch64_simd_types [ Poly16x4_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly16x8_t ] . eltype = aarch64_simd_types [ Poly16_t ] . itype ; aarch64_simd_types [ Poly64x1_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Poly64x2_t ] . eltype = aarch64_simd_types [ Poly64_t ] . itype ; aarch64_simd_types [ Float16x4_t ] . eltype = aarch64_fp16_type_node ; aarch64_simd_types [ Float16x8_t ] . eltype = aarch64_fp16_type_node ; aarch64_simd_types [ Float32x2_t ] . eltype = float_type_node ; aarch64_simd_types [ Float32x4_t ] . eltype = float_type_node ; aarch64_simd_types [ Float64x1_t ] . eltype = double_type_node ; aarch64_simd_types [ Float64x2_t ] . eltype = double_type_node ; aarch64_simd_types [ Bfloat16x4_t ] . eltype = bfloat16_type_node ; aarch64_simd_types [ Bfloat16x8_t ] . eltype = bfloat16_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = aarch64_simd_types [ i ]


<s> do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; O << format ( <STR_LIT> , Op . getImm (


<s> const uint16_t * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return CSR_FIQ_SaveList ; }


<s> EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . isABI_N64 ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrTy , Offset ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address


<s> PM . add ( createBasicTargetTransformInfoPass (


<s> void <ISA_LIT>InstPrinter :: printBranchOperand ( const MCInst * MI , unsigned OpNo


<s> void extendOutArgFIRange ( int FirstFI , int LastFI ) { if ( ! OutArgFIRange . second ) OutArgFIRange . first = FirstFI ; OutArgFIRange . second =


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: csky > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ,


<s> if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> )


<s> static SDValue LowerAVXCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( Op ) ; MVT ResVT = Op . getSimpleValueType ( ) ; assert ( ( ResVT . is256BitVector ( ) || ResVT . is512BitVector ( ) ) && <STR_LIT> ) ; unsigned NumOperands = Op . getNumOperands ( ) ; unsigned NumZero = <NUM_LIT> ; unsigned NumNonZero = <NUM_LIT> ; unsigned NonZeros = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) { SDValue SubVec = Op . getOperand ( i ) ; if ( SubVec . isUndef ( ) ) continue ; if ( <STR_LIT> ( SubVec . getNode ( ) ) ) ++ NumZero ; else { assert ( i < sizeof ( NonZeros ) * CHAR_BIT ) ; NonZeros |= <NUM_LIT> << i ; ++ NumNonZero ; } } if ( NumNonZero >


&& class1 == get_attr_vr4130_class ( vr4130_last_insn ) ) return true ;


<s> unsigned EltBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; EVT EltVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EltBits * <NUM_LIT> ) ; auto HalfEC = VT . getVectorElementCount ( ) / <NUM_LIT> ; return EVT :: getVectorVT ( * DAG . getContext (


<s> if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isSafe = false ; I = CmpInstr ; E = MI -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return