<s> __arm_vldrbq_u8 ( uint8_t const * __base ) { return __builtin_mve_vldrbq_uv16qi ( ( __builtin_neon_qi * )


<s> setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setTruncStoreAction ( VT , <STR_LIT> , Expand ) ; } MVT PtrVT = <STR_LIT> ( TM . getPointerSizeInBits ( <NUM_LIT> ) ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT IntVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; LegalizeAction Act = ( IntVT == <STR_LIT> ) ? Promote : Legal ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == <NUM_LIT> || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm (


<s> struct declare_alias_data data = { file , false } ; strcpy ( buffer , name ) ; p = strchr ( buffer , '$' ) ; while ( p ) { * p = '_' ; dollar_inside ++ ; p = strchr ( p + <NUM_LIT> , '$' ) ; } if ( TREE_PUBLIC ( decl ) ) { if ( ! RS6000_WEAK || ! DECL_WEAK ( decl ) ) { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( rs6000_xcoff_visibility ( decl ) , file ) ; putc ( '\n' , file ) ; } } else { if ( dollar_inside ) { fprintf ( file , <STR_LIT> , buffer , name ) ; fprintf ( file , <STR_LIT> , buffer , name ) ; } fputs ( <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT


<s> unsigned Case = getThreeSrcCommuteCase ( MI . getDesc ( ) . TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; assert ( Case < <NUM_LIT> && <STR_LIT> ) ; const unsigned Form132Index = <NUM_LIT> ; const unsigned Form213Index = <NUM_LIT> ; const unsigned Form231Index = <NUM_LIT> ; static const unsigned FormMapping [ ] [ <NUM_LIT> ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [


<s> case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM : case MachineCombinerPattern :: REASSOC_XY_BCA : case MachineCombinerPattern :: REASSOC_XY_BAC : reassociateFMA ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; default : TargetInstrInfo :: genAlternativeCodeSequence ( Root , Pattern , InsInstrs ,


<s> void set ( size_type Idx ) { V . set ( Idx )


<s> GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; return getGlobalAddr<ISA_LIT> ( N , Ty , DAG


<s> return ( __m128i ) __builtin_ia32_vphadduwq (


<s> if ( T -> isPointerTy ( ) ) return true ; if ( T -> isFloatingPointTy ( ) ) return true ; if ( T -> isAggregateType


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; case <STR_LIT>


<s> static HOST_WIDE_INT aarch64_clamp_to_uimm12_shift ( HOST_WIDE_INT val ) { gcc_assert ( ( val & <NUM_LIT> ) == val ) ; if ( ( ( val & <NUM_LIT> ) << <NUM_LIT> )


<s> if ( ! Arg ) return SDValue ( ) ; EVT VT = Arg . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; SDLoc DL ( N ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; return DAG . getBitcast ( OrigVT , NewNode ) ; } if ( Arg . hasOneUse ( ) && Subtarget . hasAnyFMA ( ) ) { switch ( Arg . getOpcode ( ) ) { case <STR_LIT> : case


<s> return ! ( isa < SelectInst > ( Inst ) && OpIdx


<s> link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! VECTOR_MODE_P ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link ->


<s> static void EmitHiLo ( MCStreamer & OutStreamer , MCSymbol * GOTSym , <ISA_LIT>MCExpr :: VariantKind HiKind , <ISA_LIT>MCExpr :: VariantKind LoKind , MCOperand & RD , MCContext & OutContext , const MCSubtargetInfo & STI ) { MCOperand hi = create<ISA_LIT>MCOperand ( HiKind


<s> Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; } else { Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> : <STR_LIT> , Memory . ShiftImm , Memory . ShiftType ) ; } Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createReg ( Memory .


<s> case FK_GPRel_4 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } ; if ( ! Op . hasOneUse ( ) ) return <NUM_LIT> ; if ( isSupportedExtend ( Op ) ) return <NUM_LIT> ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) if ( ConstantSDNode * ShiftCst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { uint64_t Shift = ShiftCst -> getZExtValue ( ) ; if ( isSupportedExtend ( Op . getOperand ( <NUM_LIT> ) ) ) return ( Shift <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Shift <= <NUM_LIT> ) || ( VT == <STR_LIT> && Shift <= <NUM_LIT> ) ) return <NUM_LIT> ; } return


<s> if ( P <= <NUM_LIT> ) return P ; if ( P < <NUM_LIT> ) return <NUM_LIT> + ( P - <NUM_LIT> ) * <NUM_LIT> ; if ( P <= <NUM_LIT> ) return <NUM_LIT> + ( P - <NUM_LIT> ) ; if ( P < <NUM_LIT> ) return <NUM_LIT> + ( P - <NUM_LIT> ) * <NUM_LIT> ; return <NUM_LIT> + ( P - <NUM_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; MCSubtargetInfo & STI = copySTI ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( AssemblerOptions . front ( ) -> getFeatures ( ) ) ) ; STI . setFeatureBits ( AssemblerOptions . front ( ) -> getFeatures ( ) ) ; AssemblerOptions . back ( ) -> setFeatures ( AssemblerOptions


<s> return ( float32x4_t ) __builtin_neon_vreinterpretv4sfti ( ( __builtin_neon_ti


<s> Register ThunkReg = ThunkIt -> Reg ; bool isThumb = ThunkIt -> isThumb ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; Entry -> addLiveIn ( ThunkReg ) ; if ( isThumb ) BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ThunkReg ) . add ( predOps


<s> static __inline unsigned long long sh_media_MPERM_W ( unsigned long long mm , unsigned int mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) )


<s> MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugValue ( ) ) ++ I ; if ( I != E ) { unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( I , NPredReg ) ; if ( NCC == CC || NCC == OCC ) return true ; } return


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return <ISA_LIT>Materialize64BitInt


<s> return Subtarget -> isThumb ( ) ? llvm :: <STR_LIT> : llvm ::


<s> unsigned EAX = <NUM_LIT> , EBX = <NUM_LIT> , ECX = <NUM_LIT> , EDX = <NUM_LIT> ; union { unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( GetCpuIDAndInfo ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) HasCMov = true ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; HasCLMUL = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasFMA3 = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasAVX = ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasAES = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; DetectFamilyModel ( EAX , Family , Model ) ; IsBTMemSlow = IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ; if ( Family == <NUM_LIT> && Model == <NUM_LIT> ) IsUAMemFast = true ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; Has<ISA_LIT>_64 = ( EDX >> <NUM_LIT> ) & <NUM_LIT> ; HasSSE4A = IsAMD && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasFMA4 = IsAMD && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT>


<s> const Function * F = MF . getFunction ( ) ; if ( Subtarget . hasQPX ( ) && Size >= <NUM_LIT> && ( ! IsMemset || Size >= <NUM_LIT> ) && ( ! SrcAlign || SrcAlign >= <NUM_LIT> ) && ( ! DstAlign || DstAlign >= <NUM_LIT> ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return <STR_LIT> ; } if ( Subtarget . hasAltivec ( ) && Size >= <NUM_LIT> && ( ( ( ! SrcAlign || SrcAlign >= <NUM_LIT> ) && ( ! DstAlign || DstAlign >= <NUM_LIT> ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return <STR_LIT> ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } return


<s> const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand ( MO ) ) ; } OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand ( <NUM_LIT> )


<s> std :: string FName = Dec -> getDisassembler ( ) -> getFunctionName ( Tgt ) ; Module * Mod = IRB -> GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; FunctionType * FT = FunctionType :: get ( Type :: getPrimitiveType ( Mod -> getContext ( ) , Type :: VoidTyID ) , false ) ; Twine TgtAddr ( Tgt ) ; AttributeSet AS ; AS = AS . addAttribute ( Mod -> getContext ( ) , AttributeSet :: FunctionIndex , <STR_LIT> , TgtAddr . str ( ) ) ; Value * Proto = Mod -> getOrInsertFunction ( FName , FT , AS ) ; IRB -> CreateCall ( dyn_cast < Value > ( Proto ) ) ; VisitMap [ N


<s> static unsigned getSubOpcode ( bool Is64Bit , int64_t Amount ) { if ( Is64Bit ) return isInt < <NUM_LIT> > ( Amount )


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit (


<s> int fldi_ok ( void ) { return ! TARGET_SH4 || TARGET_FMOVD ||


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; if ( ! hasThumb ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( ! isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) .


<s> unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / vectorWidth ) * ElemsPerChunk ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , makeArrayRef ( Vec -> op_begin ( ) + NormalizedIdxVal ,


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv (


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI , bool IsLittleEndian , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , ( Is64Bit ) ? true : false


<s> bool Modified = false ; bool enableNarrowLdOpt = enableNarrowLdMerge ( Fn ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowLdOpt ) ; return Modified


<s> void printlea64_32mem ( const MCInst *


<s> MachineInstr * FirstOp = nullptr ; MachineInstr * LastOp = nullptr ; int LastOffset = <NUM_LIT> ; unsigned LastOpcode = <NUM_LIT> ; unsigned LastBytes = <NUM_LIT> ; unsigned NumMove = <NUM_LIT> ; for ( int i = Ops . size ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MachineInstr * Op = Ops [ i ] ; unsigned Loc = MI2LocMap [ Op ] ; if ( Loc <= FirstLoc ) { FirstLoc = Loc ; FirstOp = Op ; } if ( Loc >= LastLoc ) { LastLoc = Loc ; LastOp = Op ; } unsigned LSMOpcode = getLoadStoreMultipleOpcode ( Op -> getOpcode ( ) , <STR_LIT> ) ; if ( LastOpcode && LSMOpcode != LastOpcode ) break ; int Offset = getMemoryOpOffset ( Op ) ; unsigned Bytes = getLSMultipleTransferSize ( Op ) ; if ( LastBytes ) { if ( Bytes != LastBytes || Offset != ( LastOffset + ( int ) Bytes ) ) break ; } LastOffset = Offset ; LastBytes = Bytes ; LastOpcode = LSMOpcode ; if ( ++ NumMove == <NUM_LIT> ) break ; } if ( NumMove <= <NUM_LIT> ) Ops . pop_back ( ) ; else { SmallPtrSet < MachineInstr * , <NUM_LIT> > MemOps ; SmallSet < unsigned , <NUM_LIT> > MemRegs ; for ( int i = NumMove - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned FirstReg = <NUM_LIT> , SecondReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc =


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI ,


<s> } unsigned FrontendSize = <NUM_LIT> ; void * Decl = nullptr ; bool IsGlobalLV = false ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { FrontendSize = Info . Var . Type * <NUM_LIT> ; Decl = Info . Var . Decl ; IsGlobalLV = Info . Var . IsGlobalLV ; } if ( IsGlobalLV && ( BaseReg || IndexReg ) ) { Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ) ; return false ; } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ; Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale

, Start , End , Size , <STR_LIT> , Identifier , Decl , FrontendSize ) ) ;


<s> void override_options ( void ) { if ( TARGET_G_FLOAT ) REAL_MODE_FORMAT ( DFmode )


<s> sprintf ( buf , <STR_LIT> , arm_data_section_count ++ ) ; return buf


<s> loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getVectorIndex


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE2 ( ) { if ( ! Subtarget . hasSSE2 ( ) ) return ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v16s8 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s64 , v2s64 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_MUL , v8s16 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPEXT , s64 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPEXT , <NUM_LIT> , s32 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPTRUNC , s32 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPTRUNC , <NUM_LIT> , s64 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { TargetOpcode :: G_FCONSTANT , s64 } , LegacyLegalizeActions :: Legal ) ; for ( const auto & Ty : { v16s8 , v32s8 , v8s16 , v16s16 , v4s32 , v8s32 , v2s64 , v4s64 } ) { LegacyInfo . setAction ( { G_CONCAT_VECTORS , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty


<s> MachinePointerInfo <ISA_LIT>MachineFunctionInfo :: callPtrInfo ( const GlobalValue


<s> old_reg = head -> regno ; best_reg = find_rename_reg ( head , superclass , & unavailable , old_reg , false ) ; bool ok = regrename_do_replace ( head , best_reg ) ; gcc_assert ( ok ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , head -> id , reg_names

[ best_reg ] , reg_class_names [ superclass ] ) ;


<s> if ( ( unsigned ) CC != ABI . GetDefaultDataCapability ( ) ) { ErrorIfNotPending ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( CC == - <NUM_LIT> ) { if ( Name [ <NUM_LIT> ] == 'c' ) { if ( Name == <STR_LIT> ) { CC = <STR_LIT> ; } else { StringRef NumString = Name . substr ( <NUM_LIT> ) ; int IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal < <NUM_LIT> || IntVal > <NUM_LIT> ) return - <NUM_LIT> ; if ( IntVal == <NUM_LIT> ) CC = <NUM_LIT> ; else CC = <STR_LIT> + IntVal - <NUM_LIT> ; } } else { int InvalidReg = StringSwitch < int > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( InvalidReg ) { ErrorIfNotPending ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> <STR_LIT> + Name + <STR_LIT> + Twine ( InvalidReg ) + <STR_LIT> <STR_LIT> , Parser . getTok ( ) . getLocRange ( ) ) ; return - <NUM_LIT> ; } CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ; } } if ( CC == <NUM_LIT>


<s> MemVT = MemVT . changeTypeToInteger ( ) ; } SDValue NewLoad = DAG . getMaskedLoad ( LoadVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Pg , DAG . getUNDEF ( LoadVT ) , MemVT , Load -> getMemOperand ( ) , Load -> getAddressingMode ( ) , Load -> getExtensionType ( ) ) ; SDValue Result = NewLoad ; if ( VT . isFloatingPoint ( ) && Load -> getExtensionType ( ) == <STR_LIT> ) { EVT ExtendVT = ContainerVT . changeVectorElementType ( Load -> getMemoryVT ( ) . getVectorElementType ( ) ) ; Result = getSVESafeBitCast ( ExtendVT , Result , DAG ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Pg , Result , DAG . getUNDEF ( ContainerVT ) ) ; } Result = convertFromScalableVector ( DAG , VT


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) + <NUM_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; unsigned offset = NumBytes - VA . getLocMemOffset ( ) - VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getIntPtrConstant ( offset , dl ) ) ; SDValue MemOp ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal (


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB .


<s> continue ; } if ( ! PrevVCMP || ! IsVPNOTEquivalent ( Instr , * PrevVCMP ) ) { PrevVCMP = & Instr ; continue ; } Register PrevVCMPResultReg = PrevVCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & Instr , Instr . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( Instr . getOperand ( <NUM_LIT> ) ) . addReg ( PrevVCMPResultReg ) ; addUnpredicatedMveVpredNOp ( MIBuilder ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Instr . dump ( ) ) ; if ( PrevVCMPResultKiller ) PrevVCMPResultKiller -> setIsKill ( false ) ; DeadInstructions . push_back ( & Instr


<s> static bool nds32_can_eliminate ( const int from_reg , const int to_reg ) { if ( from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM ) return true ; if ( from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM )


<s> return getBits ( insn , <NUM_LIT> , <NUM_LIT>


<s> } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = <NUM_LIT> ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } OpcodeTablePtr = &


<s> if ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CONSTANT ( decl ) || ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && (

! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , <NUM_LIT> ) ) = <NUM_LIT> ;


<s> CommentString = <STR_LIT> ; SupportsDebugInformation = true


<s> } else if ( const auto * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( Target ) ; if ( FuncInfo . BPI ) { auto BranchProbability = FuncInfo . BPI -> getEdgeProbability ( BI -> getParent ( ) , Target -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( Target , BranchProbability ) ; } else FuncInfo . MBB -> addSuccessorWithoutProb ( Target ) ; return true ; } else { <STR_LIT> CC = <STR_LIT> ; if ( foldXALUIntrinsic ( CC , I , BI -> getCondition ( ) ) ) { Register CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( ! CondReg ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } Register CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned Opcode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Opcode = <STR_LIT> ; } const MCInstrDesc & II = TII . get ( Opcode ) ; Register ConstrainedCondReg = constrainOperandRegClass ( II , CondReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( ConstrainedCondReg ) . addImm ( <NUM_LIT> ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB


<s> APInt SignificantBitsToBeInserted = BitsToBeInserted . zextOrTrunc ( BitWidth ) ; return ( SignificantDstMask & SignificantBitsToBeInserted ) == <NUM_LIT> && ( SignificantDstMask | SignificantBitsToBeInserted )


<s> int EndOffset = BeginOffset + NumSubElts * EltBitWidth ; if ( BeginOffset <= BitOffset && BitOffset < EndOffset ) { BitOffset -= BeginOffset ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } assert ( ( BitOffset % NumEltBits ) == <NUM_LIT> && <STR_LIT> ) ; BroadcastIdx = BitOffset / NumEltBits ; bool BitCastSrc = V . getScalarValueSizeInBits ( ) != NumEltBits ; if ( BitCastSrc && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerShuffleAsTruncBroadcast ( DL , VT , V , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; if ( ! BitCastSrc && ( ( V . getOpcode ( ) == <STR_LIT> && V . hasOneUse ( ) ) || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! BroadcastFromReg && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( <STR_LIT> ( V . getNode ( ) ) && cast < LoadSDNode > ( V ) -> isSimple ( ) ) { if ( ! Subtarget . is64Bit ( ) && VT . getScalarType ( ) == <STR_LIT> ) { BroadcastVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; Opcode = ( BroadcastVT . is128BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) ? <STR_LIT> : Opcode ; } LoadSDNode * Ld = cast < LoadSDNode > ( V ) ; SDValue BaseAddr = Ld -> getOperand ( <NUM_LIT> ) ; EVT SVT = BroadcastVT . getScalarType ( ) ; unsigned Offset = BroadcastIdx * SVT . getStoreSize ( ) ; assert ( ( int ) ( Offset * <NUM_LIT> ) == BitOffset && <STR_LIT> ) ; SDValue NewAddr = DAG . getMemBasePlusOffset ( BaseAddr , Offset , DL ) ; V = DAG . getLoad ( SVT , DL , Ld -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Ld -> getMemOperand ( ) , Offset , SVT . getStoreSize ( ) ) ) ; DAG . makeEquivalentMemoryOrdering ( Ld , V ) ; } else if ( ! BroadcastFromReg ) { return SDValue ( ) ; } else if ( BitOffset


<s> CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; } } } SDValue Cmp ; <STR_LIT> <ISA_LIT>CC ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { const ConstantSDNode * RHSC = cast < ConstantSDNode > ( RHS ) ; if ( ( RHSC -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) && cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed ( -


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( VA . getLocReg ( ) == PhysReg && <STR_LIT> ) ; auto ValSize = VA . getValVT ( ) . getSizeInBits ( ) ; auto LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; assert ( ValSize <=


<s> auto * ZCPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPV ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( ZCPV -> getGlobalValue ( ) ) , getModifierVariantKind ( ZCPV -> getModifier ( ) ) , OutContext ) ; uint64_t Size = getDataLayout ( ) . getTypeAllocSize ( ZCPV -> getType ( ) ) ; OutStreamer -> EmitValue ( Expr , Size


<s> unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( Alignment >= DataSize && ( DataSize == <NUM_LIT> || DataSize == <NUM_LIT> ) ) return DataSize == <NUM_LIT> ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ; return false


<s> static DecodeStatus DecodeSIMM7 ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { uint64_t tgt = SignExtend64 < <NUM_LIT> > ( insn ) ; MI . addOperand ( MCOperand :: createImm (


<s> static inline unsigned getT1Rd ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn


<s> static inline bool hasInefficientLEABaseReg ( const MachineOperand & Base , const MachineOperand & Index ) { return Base . isReg ( ) && isInefficientLEAReg ( Base

. getReg ( ) ) && isRegOperand ( Index ) ;


<s> gcc_assert ( MEM_P ( src ) && MEM_P ( dst ) ) ; rtx tmp_reg = gen_reg_rtx ( mode ) ; nds32_emit_load_store ( tmp_reg , src , mode , addr_offset , true ) ; nds32_emit_load_store ( tmp_reg , dst , mode ,


<s> int FPOffset = MFI -> getObjectOffset ( FI ) + <NUM_LIT> ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) ; bool isFixed = MFI -> isFixedObjectIndex ( FI ) ; bool UseFP = false ; if ( AFI -> hasStackFrame ( ) ) { if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( hasFP ( MF ) && ! RegInfo -> hasBasePointer ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { if ( PreferFP || MFI -> hasVarSizedObjects ( ) || FPOffset >= <NUM_LIT> || ( FPOffset >= - <NUM_LIT> && Offset > - FPOffset ) ) UseFP = true ; } } assert ( ( isFixed || ! RegInfo -> needsStackRealignment (

MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ;


<s> ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg


<s> SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasFullFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRetAddrStack = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; Has8MSecExt = false ; HasCrypto = false ; HasCRC = false ; HasRAS = false


<s> if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCastsSafe ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads


<s> if ( In . getOpcode ( ) != <STR_LIT> ) Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; } SDLoc dl ( Op ) ; MVT VT = <STR_LIT> ( std :: max ( ( int ) Op . getValueType ( ) . getSizeInBits ( ) , <NUM_LIT> ) ) ; return DAG . getConstant ( Immediate , dl ,


<s> <ISA_LIT>DCBasicBlock :: ~ <ISA_LIT>DCBasicBlock ( ) { auto * BB = getBasicBlock ( ) ; if ( BB -> size ( ) > <NUM_LIT> ) if ( auto * TI = dyn_cast < TerminatorInst > ( & *

std :: prev ( BB -> end ( ) , <NUM_LIT> ) ) ) Builder . SetInsertPoint ( TI ) ;


<s> return BaseType == FrameIndexBase || IndexReg . getNode ( ) != nullptr ||


<s> else insn = gen_call_value_nogp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; } else { if ( sibcall_p ) insn = gen_sibcall_gp ( addr ) ; else if ( ! retval ) insn = gen_call_gp ( addr , b0 ) ; else insn = gen_call_value_gp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn


<s> rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen =


<s> return ( int32x2_t ) __builtin_neon_vnegv2si (


<s> unsigned InstMaskStart = <NUM_LIT> - MaskEnd - <NUM_LIT> , InstMaskEnd = <NUM_LIT> - MaskStart - <NUM_LIT> ; if ( InstCnt ) * InstCnt += <NUM_LIT> ; if ( Repl32 ) { assert ( InstMaskStart >= <NUM_LIT> && <STR_LIT> ) ; assert ( InstMaskEnd >= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart - <NUM_LIT> , dl ) , getI32Imm ( InstMaskEnd - <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskStart == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskEnd , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT>


<s> DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( start


<s> for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>elTarget ( ) , & getThe<ISA_LIT>64Target ( ) , & getThe<ISA_LIT>64elTarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterELFStreamer ( *


<s> const LLT v8s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; for ( auto Ty : { v16s16 , v8s32 } ) LegacyInfo . setAction ( { G_MUL , Ty } , LegacyLegalizeActions :: Legal ) ; for ( const auto & Ty : { v64s8 , v32s16 , v16s32 , v8s64 } ) { LegacyInfo . setAction ( { G_CONCAT_VECTORS , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , LegacyLegalizeActions ::


<s> return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand (


<s> CUMULATIVE_ARGS * args_so_farp = get_cumulative_args ( args_so_farp_v ) ; if ( args_so_farp -> regs + <NUM_LIT> < MMIX_MAX_ARGS_IN_REGS ) * pretend_sizep = ( MMIX_MAX_ARGS_IN_REGS - ( args_so_farp -> regs + <NUM_LIT> ) ) * <NUM_LIT> ; if ( ( <NUM_LIT> + ( MMIX_FUNCTION_ARG_SIZE ( mode , vartype ) ) ) / <NUM_LIT> != <NUM_LIT> ) internal_error (


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo &


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { emitFrameDirective ( ) ; SmallString < <NUM_LIT> >


<s> static unsigned int mips_autovectorize_vector_modes ( vector_modes * modes , bool ) { if ( ISA_HAS_MSA ) modes -> safe_push (


<s> if ( IS_NESTED ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_STACKALIGN ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_CMSE_ENTRY ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , ( HOST_WIDE_INT ) crtl -> args . size , crtl -> args . pretend_args_size , ( HOST_WIDE_INT ) get_frame_size ( ) ) ; asm_fprintf ( f , <STR_LIT> , frame_pointer_needed , cfun -> machine -> uses_anonymous_args ) ; if ( cfun -> machine -> lr_save_eliminated ) asm_fprintf (


<s> return false ; if ( <ISA_LIT>CCInfo . hasByValArg ( ) || FI .


<s> case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT>


) : default_hidden_stack_protect_fail ( ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget >


<s> void llvm :: initializeAnnotationsInference ( PassRegistry &


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR64DecoderTable [ RegNo ] )


<s> <ISA_LIT>BasicMCBuilder ( <ISA_LIT>BasicMCBuilder & B ) : Opcode ( B . Opcode ) , Format ( B . Format ) , NumOps ( B . NumOps ) , Disasm ( B . Disasm ) , SP ( B . SP ) { Err =


<s> static unsigned getAbsoluteReloc ( unsigned Kind ) { switch ( Kind ) { case FK_Data_1 : return ELF :: R_390_8 ; case FK_Data_2 : return ELF :: R_390_16 ; case FK_Data_4 : return ELF :: R_390_32 ; case FK_Data_8 : return


<s> static Target The<ISA_LIT>64elTarget ; return The<ISA_LIT>64elTarget


<s> bool isCK804 ( ) const { return <ISA_LIT>ProcFamily


<s> vqtbx3_u8 ( uint8x8_t r , uint8x16x3_t tab , uint8x8_t idx ) { __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x8_t ) __builtin_aarch64_qtbx3v8qi ( ( int8x8_t ) r , __o , (


<s> } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL_RTX && aarch64_simd_valid_immediate ( const_vec , NULL ) ) return const_vec ; else if ( ( const_dup = aarch64_simd_dup_constant ( vals ) ) != NULL_RTX ) return const_dup ; else if ( const_vec != NULL_RTX ) return const_vec ; else return


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType (


<s> } else { const fltSemantics & Sem = APFloat :: IEEEsingle ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , SrcVT , Op1 , Mask1 ) ; if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { const fltSemantics & Sem = APFloat :: IEEEdouble ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { const fltSemantics & Sem = APFloat :: IEEEsingle ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT>


<s> int nelt = GET_MODE_NUNITS ( mode ) ; if ( ! INTEGRAL_MODE_P ( mode ) ) return false ; if ( ! ( MEM_P ( mem ) ) || ! SYMBOL_REF_P ( XEXP ( mem , <NUM_LIT> ) ) || ! CONSTANT_POOL_ADDRESS_P ( XEXP ( mem , <NUM_LIT> ) ) ) return false ; rtx constant = get_pool_constant ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return false ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , <NUM_LIT> ) ; if ( constant == nullptr || GET_CODE ( constant ) != CONST_VECTOR ) return false ; } for ( int i = <NUM_LIT> ; i != nelt ; i ++ ) perm [ i ]

= UINTVAL ( XVECEXP ( constant , <NUM_LIT> , i ) ) ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue Max = DAG . getNode ( <STR_LIT> , DL , VT


<s> EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( ResultVT , dl , Vec -> ops ( ) . slice ( IdxVal , ElemsPerChunk ) ) ; SDValue VecIdx = DAG . getIntPtrConstant ( IdxVal ,


<s> const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CallerCC , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return CCInfo . getNextStackOffset ( ) <= FuncInfo -> getBytesInStackArgArea


<s> unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function >


<s> const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( operand ) ; gcc_assert ( GET_MODE ( operand ) == SFmode ) ; REAL_VALUE_TO_TARGET_SINGLE ( * rv ,


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { Inst . setOpcode (


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( EVT VT ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) return TypeWidenVector ; if ( VT . isScalableVector ( ) && ( VT . getVectorNumElements ( ) == <NUM_LIT> ) ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT


<s> static rtx gen_load_const_gp ( rtx reg ) { return PMODE_INSN ( gen_load_const_gp , (


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB . getReg ( <NUM_LIT> ) ; auto TrueReg = MIB . getReg ( <NUM_LIT> ) ; auto FalseReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . MOVCCr ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; MIB -> eraseFromParent (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) return SDValue ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getNode ( <STR_LIT> ,


<s> const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( int & I : EhDataRegFI ) { const TargetRegisterClass & RC = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64


<s> return ( __m512 ) __builtin_ia32_getexpps512_mask ( ( __v16sf ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) -


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; const TargetMachine & TM = DAG . getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , Hi ) ; } return DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi


<s> case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } Register ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; if ( <STR_LIT> ( ScratchReg ) ) EncodedBytes = <NUM_LIT> ; else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addOperand ( CalleeMCOp ) ) ; if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT> ) ; EmitNops ( * OutStreamer , NumBytes - EncodedBytes , Subtarget ->


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getLogAlignment ( ) , MIPS_NACL_BUNDLE_LOG_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; TS . setUsesMicro<ISA_LIT> ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( )

) TS . emitDirectiveSet<ISA_LIT>16 ( ) ;


<s> reg = gen_rtx_REG ( SImode , regno ) ; sym = gen_rtx_SYMBOL_REF ( SImode , symbol ) ; emit_insn ( gen_movsi_topsym_s ( reg , sym


<s> switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> RegisterTarget < Triple :: cahp > X ( getThe<ISA_LIT>Target

( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; int LocalM = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + LaneSize ; if ( RepeatedMask [ i % LaneSize ] < <NUM_LIT> ) RepeatedMask [ i % LaneSize ]


<s> Value * <ISA_LIT>IREmitter :: visitSFENCE (


<s> void rs6000_expand_vector_set ( rtx target , rtx val , int elt ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx reg = gen_reg_rtx ( mode ) ; rtx mask , mem , x ; int width = GET_MODE_SIZE ( inner_mode ) ; int i ; val = force_reg ( GET_MODE ( val ) , val ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) { rtx insn = NULL_RTX ; rtx elt_rtx = GEN_INT ( elt ) ; if ( mode == V2DFmode ) insn = gen_vsx_set_v2df ( target , target , val , elt_rtx ) ; else if ( mode == V2DImode ) insn = gen_vsx_set_v2di ( target , target , val , elt_rtx ) ; else if ( TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_UPPER_REGS_DI && TARGET_POWERPC64 ) { if ( mode == V4SImode ) insn = gen_vsx_set_v4si_p9 ( target , target , val , elt_rtx ) ; else if ( mode == V8HImode ) insn = gen_vsx_set_v8hi_p9 ( target , target , val , elt_rtx ) ; else if ( mode == V16QImode ) insn = gen_vsx_set_v16qi_p9 ( target , target , val , elt_rtx ) ; } if ( insn ) { emit_insn ( insn ) ; return ; } } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == <NUM_LIT> ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) XVECEXP ( mask , <NUM_LIT> , i ) = GEN_INT ( i ) ; for ( i = <NUM_LIT> ; i < width ; ++ i ) XVECEXP ( mask , <NUM_LIT> , elt * width + i ) = GEN_INT ( i


<s> bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , - SPOffsetFromCFA - Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) { int Offset = usePackedStack ( MF ) ? <STR_LIT> - <NUM_LIT> : <NUM_LIT> ; BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; } } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else


<s> void markRegisterUsed ( int registerIndex ) { UsedRegisters . push_back (


<s> Align <ISA_LIT>TargetLowering :: getAlignmentForPreciseBounds ( uint64_t Size ) const { if ( ! Subtarget . isCheri ( ) ) return Align ( ) ; if ( Subtarget . isCheri128 ( ) ) { return Align ( cc128_get_required_alignment ( Size ) ) ; } assert ( Subtarget . isCheri256 ( ) ) ; return Align


<s> bool <ISA_LIT>Subtarget :: enablePostMachineScheduler ( ) const { return PostRAScheduler


<s> if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( int_size_in_bytes ( type ) < <NUM_LIT> ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) { if ( TARGET_DEBUG_ARG ) fprintf (


<s> virtual const char * getPassName ( ) const { return


<s> unsigned int <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return TargetInstrInfo :: isStoreToStackSlot ( MI ,


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout


<s> } context -> fpsr_loc = & ( sc -> sc_ar_fpsr ) ; context -> pfs_loc = & ( sc -> sc_ar_pfs ) ; context -> lc_loc = & ( sc -> sc_ar_lc ) ; context -> unat_loc = & ( sc -> sc_ar_unat ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> br_loc [ <NUM_LIT> ] = & ( sc -> sc_br [ <NUM_LIT> ] ) ; context -> pr = sc -> sc_pr ; context -> psp = sc -> sc_gr [ <NUM_LIT> ] ; context -> gp = sc -> sc_gr [ <NUM_LIT> ] ; fs -> no_reg_stack_frame = <NUM_LIT> ; if ( sc -> sc_rbs_base ) { long ndirty , loadrs = sc -> sc_loadrs >> <NUM_LIT> ; unsigned long alt_bspstore = context -> bsp - loadrs ; unsigned long bspstore ; unsigned long * ar_bsp = ( unsigned long * ) ( sc -> sc_ar_bsp ) ; ndirty = ia64_rse_num_regs ( ( unsigned long * ) alt_bspstore

, ( unsigned long * ) context -> bsp ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { if ( EmitFPOData


<s> Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveWord ( <NUM_LIT> , DirectiveID .


<s> return __aarch64_vset_lane_any ( * __src ,


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr


<s> return count == <NUM_LIT> ? ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? validize_mem ( gen_rtx_MEM ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , - <NUM_LIT> ) ) ) : get_hard_reg_initial_val ( Pmode

, MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ) : NULL_RTX ;


<s> Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext (


<s> TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; UseDataRegionDirectives = MarkedJTDataRegions ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfFDESymbolsUseAbsDiff = T . isMacOSX ( ) && ! T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; if ( T . isMacOSX ( ) && T . isMacOSXVersionLT ( <NUM_LIT> ,

<NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ;


<s> } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> ,


<s> Instruction * <ISA_LIT>PromoteConstant :: findInsertionPoint ( Value :: user_iterator & Use ) { PHINode * PhiInst = dyn_cast < PHINode > ( * Use ) ; Instruction * InsertionPoint ; if ( PhiInst ) InsertionPoint = PhiInst -> getIncomingBlock ( Use

. getOperandNo ( ) ) -> getTerminator ( ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , bool * Fast ) const { if ( Disable<ISA_LIT>Unaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) return false ; if ( VT == <STR_LIT>


<s> cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , <NUM_LIT> , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = <NUM_LIT> ; rvec [ <NUM_LIT> ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > <NUM_LIT> || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k -


<s> if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , static_cast < MCFixupKind >


<s> const char * function_resolver :: get_scalar_type_name ( type_suffix_index type


<s> if ( Subtarget -> hasV8Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isMClass ( ) && Subtarget -> hasDSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV4TOps ( ) ) return


<s> EVT ViaVecTy = ResVecTy ; SDLoc DL ( Op ) ; SDValue LaneA ; SDValue LaneB = Op -> getOperand ( <NUM_LIT> ) ; if ( ResVecTy == <STR_LIT> ) { LaneA = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ViaVecTy = <STR_LIT> ; } else LaneA = LaneB ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> static void mmix_file_start ( void ) { default_file_start (


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const


<s> if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT>

, Chain , Dst , Src , CSize -> getZExtValue ( ) ) ;


<s> if ( info -> altivec_save_offset ) fprintf ( stderr , <STR_LIT> , info -> altivec_save_offset ) ; if ( info -> spe_gp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_save_offset ) ; if ( info -> vrsave_save_offset ) fprintf ( stderr , <STR_LIT> , info -> vrsave_save_offset ) ; if ( info -> lr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> lr_save_offset ) ; if ( info -> cr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> cr_save_offset ) ; if ( info -> toc_save_offset ) fprintf ( stderr , <STR_LIT> , info -> toc_save_offset ) ; if ( info -> varargs_save_offset ) fprintf ( stderr , <STR_LIT> , info -> varargs_save_offset ) ; if ( info -> total_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> total_size ) ; if ( info -> vars_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> vars_size ) ; if ( info -> parm_size ) fprintf ( stderr , <STR_LIT> , info -> parm_size ) ; if ( info -> fixed_size ) fprintf ( stderr , <STR_LIT> , info -> fixed_size ) ; if ( info -> gp_size ) fprintf ( stderr , <STR_LIT> , info -> gp_size ) ; if ( info -> spe_gp_size ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_size ) ; if ( info -> fp_size ) fprintf ( stderr , <STR_LIT> , info -> fp_size ) ; if ( info -> altivec_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_size ) ; if ( info -> vrsave_size ) fprintf ( stderr , <STR_LIT> , info -> vrsave_size ) ; if ( info -> altivec_padding_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_padding_size ) ; if ( info -> spe_padding_size ) fprintf ( stderr , <STR_LIT> , info -> spe_padding_size ) ; if ( info -> lr_size ) fprintf ( stderr , <STR_LIT>


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return true ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 -> getOpcode ( ) != <STR_LIT> && N1 -> getOpcode ( ) != <STR_LIT> && N1 -> getOpcode ( ) != <STR_LIT> && N1 -> getOpcode ( ) != <STR_LIT> ) return true ; if ( auto * Const = dyn_cast < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ) { if ( Const -> getAPIntValue ( ) . ult ( <NUM_LIT> ) )


<s> if ( Opc != TargetOpcode :: G_GLOBAL_VALUE ) return false ; auto GV = I . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) { return false ; } if ( TM . getCodeModel ( ) != CodeModel :: Small ) return <NUM_LIT> ; <ISA_LIT>AddressMode AM ; AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc = getLeaOP ( Ty , STI ) ; I . setDesc ( TII . get ( NewOpc )


<s> static int iq2000_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - <NUM_LIT> ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> , UNITS_PER_WORD ) ; return


<s> static inline tree def_builtin_const2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin2 ( mask , name , tcode , code


<s> if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ; if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x


<s> } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI -> setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI -> setObjectZExt ( FI , true ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { MFI -> setObjectSExt ( FI


<s> if ( rs6000_abi_string == <NUM_LIT> ) return ; else if ( ! strcmp ( rs6000_abi_string , <STR_LIT> ) ) rs6000_altivec_abi = <NUM_LIT> ; else if ( ! strcmp ( rs6000_abi_string , <STR_LIT> ) ) rs6000_altivec_abi = <NUM_LIT> ; else error ( <STR_LIT>


<s> case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMADDSUB ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMOVMSK ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> machine_mode mode1 = Pmode ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 ,


<s> return __builtin_loongson_pcmpgtw_s ( s


<s> static void findTemporariesForLR ( const BitVector & GPRsNoLRSP , const BitVector & PopFriendly , const LivePhysRegs & UsedRegs , unsigned & PopReg , unsigned & TmpReg , MachineRegisterInfo & MRI ) { PopReg = TmpReg = <NUM_LIT> ; for ( auto Reg : GPRsNoLRSP .


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_CONSTANT ) && <STR_LIT> ) ; const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; if ( RBI . getRegBank ( DefReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) return false ; uint64_t Val = <NUM_LIT> ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; I . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Val ) ; } else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned


<s> static bool arm_macro_fusion_p ( void ) { return current_tune -> fuseable_ops !=


<s> return insn -> prefixPresent [ prefix ] == <NUM_LIT> && insn -> prefixLocations [ prefix


<s> if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) )


<s> if ( Data != std :: end ( IntrinsicsWithoutChain ) && * Data == IntrinsicToFind ) return Data ; return nullptr


<s> ResTys . push_back ( <STR_LIT> ) ; return CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops , <NUM_LIT> ) ; } EVT RegVT = GetNEONSubregVT ( VT ) ; if ( NumVecs == <NUM_LIT> ) { unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , MemUpdate , MemOpc , Align , Pred , PredReg , Chain } ; std :: vector < EVT > ResTys ( <NUM_LIT> , VT ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops , <NUM_LIT> ) ; Chain = SDValue ( VLd , <NUM_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) { SDNode * Q = PairDRegs ( VT , SDValue ( VLd , <NUM_LIT> * Vec ) , SDValue ( VLd , <NUM_LIT> * Vec + <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , Vec ) , SDValue ( Q , <NUM_LIT> ) ) ; } } else { MemOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( true ) , <STR_LIT> ) ; std :: vector < EVT > ResTys ( NumVecs , RegVT ) ; ResTys . push_back ( MemAddr . getValueType ( ) ) ; ResTys . push_back (


<s> const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opc ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; assert ( NumOps >= <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; ElemSize esize = ESizeNA ; if ( Flag == N2V_VectorDupLane ) { assert ( Opc >= <STR_LIT> && Opc <= <STR_LIT> && <STR_LIT> ) ; esize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? ESize8 : ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? ESize16 : ESize32 ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeNEONRd ( insn ) ) ) ) ; ++ OpIdx ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeNEONRm ( insn ) ) ) ) ; ++ OpIdx ; int Idx ; while ( OpIdx < NumOps && ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; ++ OpIdx ; } if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { unsigned imm = <NUM_LIT> ; if ( Flag == N2V_VectorDupLane ) imm =


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val


<s> const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; unsigned NumBytes = <NUM_LIT> ; const MCInstrDesc & Desc = MI .


<s> static __inline__ void sh_media_NOP (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo ) .


<s> void altivec_expand_lvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( VOIDmode , tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , tmp , tmp , sel )


<s> rtx src_check = copy_addr_to_reg ( XEXP ( src , <NUM_LIT> ) ) ; if ( GET_MODE ( src_check ) == SImode ) emit_insn ( gen_andsi3 ( src_check , src_check , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_anddi3 ( src_check , src_check , GEN_INT ( <NUM_LIT> ) ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_check , GEN_INT ( <NUM_LIT> - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_LT ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , pc_rtx , lab_ref ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += <NUM_LIT>


<s> const uint32_t <ISA_LIT>v6T2_NopEncoding = <NUM_LIT> ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & <NUM_LIT> ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8 (


<s> int <ISA_LIT>TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode &


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==


<s> static bool maskMatters ( RxSBGOperands & RxSBG , uint64_t Mask ) { if ( RxSBG . Rotate != <NUM_LIT> ) Mask = ( ( Mask << RxSBG . Rotate ) | ( Mask >> ( <NUM_LIT> - RxSBG


<s> break ; } aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; if ( TARGET_SVE ) { int bits ; if ( ! BITS_PER_SVE_VECTOR . is_constant ( & bits ) ) bits = <NUM_LIT> ; builtin_define_with_int_value ( <STR_LIT> , bits ) ; } aarch64_def_or_undef ( TARGET_SVE , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE_I8MM , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE_F32MM , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE_F64MM , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE2 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE2_AES , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE2_BITPERM , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE2_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SVE2_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_LSE , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_AES , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_FRINT , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_TME , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_RNG , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_MEMTAG , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( aarch_bti_enabled ( ) , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; if ( aarch_ra_sign_scope != AARCH_FUNCTION_NONE ) { int v = <NUM_LIT> ; if ( aarch_ra_sign_key == AARCH_KEY_A ) v |= <NUM_LIT> ; if ( aarch_ra_sign_key == AARCH_KEY_B )


<s> bool i386_pe_type_dllimport_p ( tree


<s> void printOffsetUImm12Operand ( const MCInst * MI , unsigned OpNum ,


<s> void <ISA_LIT>TargetStreamer :: emitCurrentConstantPool


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && isWorthFoldingADDlow ( N ) ) { GlobalAddressSDNode * GAN = dyn_cast < GlobalAddressSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Base = N . getOperand ( <NUM_LIT> ) ; OffImm = N . getOperand ( <NUM_LIT> ) ; if ( ! GAN ) return true ; const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; const DataLayout * DL = TLI -> getDataLayout ( ) ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) ) Alignment = DL -> getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue (


<s> rtx op0 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; rtx op1 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; if ( operands [ <NUM_LIT> ] != const1_rtx && operands [ <NUM_LIT> ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , <NUM_LIT> ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU


<s> if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getBitcast ( VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } return SDValue


<s> static unsigned translateShiftImm ( unsigned imm ) { assert ( ( imm & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( imm == <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } switch ( Opc2 ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( StringRef TT , StringRef CPU , StringRef FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) { ParseSubtargetFeatures ( CPU


<s> return false ; } if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function & Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func . getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( * Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm


<s> case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR


<s> FunctionPass * create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( isI32Insn ( User , N ) ) continue ; return SDValue ( ) ; } SDValue SubI32 = DAG . getTargetConstant ( <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; case CodeModel :: Large


<s> offset = rs6000_machopic_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else { rtx mem = force_const_mem ( Pmode , orig ) ; return machopic_legitimize_pic_address ( mem , Pmode , reg ) ; } } return gen_rtx_PLUS ( Pmode , base


<s> if ( ! HasI64Out ) return DAG . getNode ( Opc , DL , Op -> value_begin ( ) , Op -> getNumValues ( ) , Ops . begin ( ) , Ops . size ( ) ) ; SDValue Intr = DAG . getNode ( Opc , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops . begin ( ) , Ops . size ( ) ) ; SDValue OutLo = DAG . getCopyFromReg ( Intr . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , Intr . getValue ( <NUM_LIT> ) ) ; SDValue OutHi = DAG . getCopyFromReg ( OutLo . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , OutLo . getValue ( <NUM_LIT> ) ) ; SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutLo


<s> static DecodeStatus decodeSPE8Operands ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { uint64_t Base = Imm >> <NUM_LIT> ; uint64_t Disp = Imm


<s> bool IsAligned = Alignment == <NUM_LIT> || Alignment >= MemVT . getSizeInBits ( ) / <NUM_LIT> ; if ( RegVT . is256BitVector ( ) && Subtarget -> isUnalignedMem32Slow ( ) && ! DCI . isBeforeLegalizeOps ( ) && ! IsAligned && Ext == <STR_LIT> ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ; NewVec = Insert128BitVector ( NewVec , Load2 , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , NewVec , TF


<s> static bool sparc_vector_mode_supported_p ( machine_mode