<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( TLI . isTypeLegal ( VT ) ) if ( SDValue AddSub = combineShuffleToAddSubOrFMAddSub ( N , Subtarget , DAG ) ) return AddSub ; if ( ! DCI . isBeforeLegalize ( ) && DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . isUndef ( ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue BC0 = N0 . getOperand ( <NUM_LIT> ) ; EVT SVT = BC0 . getValueType ( ) ; unsigned Opcode = BC0 . getOpcode ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = VT . isInteger ( ) ; break ; case


<s> StringRef getPassName ( ) const override { return


<s> FuncInfo -> setSpillsCR ( ) ; } for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FrameIdx ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF


<s> SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; return Result


<s> if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; long TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator II = U -> op_begin ( ) + <NUM_LIT> , IE = U -> op_end ( ) ; II != IE ; ++ II , ++ GTI ) { const Value * Op = * II ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U ,


<s> enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return <NUM_LIT> ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code ==


<s> unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( maxCallFrameSize ) ; MBB . erase ( II )


<s> case 'D' : mmix_output_condition ( stream , x , ( code == 'D' ) ) ; return ; case 'e' : if ( TARGET_FCMP_EPSILON ) fprintf ( stream , <STR_LIT> ) ; return ; case 'm' : if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , HOST_WIDEST_INT_PRINT_DEC , ( HOST_WIDEST_INT ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'p' : fprintf ( stream , <STR_LIT> , cfun -> machine -> highest_saved_stack_register + <NUM_LIT> ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( HOST_WIDEST_INT ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( HOST_WIDEST_INT ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ; case <NUM_LIT> : break ; default : internal_error ( <STR_LIT> , code ) ; } switch ( GET_CODE ( modified_x ) ) { case REG : regno = REGNO ( modified_x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) internal_error ( <STR_LIT> , regno ) ; fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( regno ) ] ) ; return ; case MEM : output_address ( XEXP ( modified_x , <NUM_LIT> ) ) ; return ; case CONST_INT : if ( INTVAL ( modified_x ) > - <NUM_LIT> && INTVAL ( modified_x ) < <NUM_LIT> ) fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( modified_x ) ) ) ; else fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( modified_x ) ) & ( unsigned int ) ~ <NUM_LIT> ) ; return ; case CONST_DOUBLE : mmix_output_octa ( stream , mmix_intval ( modified_x ) , <NUM_LIT> ) ; return ; case CONST


<s> const MCExpr * Sub = MCBinaryExpr :: CreateSub ( LazyPtrExpr , Anon , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( Anon ) ) ; OutStreamer . EmitLabel ( AnonSymbol ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubHa16 = <ISA_LIT>MCExpr :: CreateHa ( Sub , true , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubHa16 ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; const MCExpr * SubLo16 = <ISA_LIT>MCExpr :: CreateLo ( Sub , true , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( SubLo16 ) . addExpr ( SubLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; OutStreamer . SwitchSection ( LSPSection ) ; OutStreamer . EmitLabel ( LazyPtr ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; MCSymbol * DyldStubBindingHelper = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; if ( is<ISA_LIT>64 ) { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } else { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: Create ( LazyPtr , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * LazyPtrHa16 = <ISA_LIT>MCExpr :: CreateHa ( LazyPtrExpr , true , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( LazyPtrHa16 ) ) ; const MCExpr * LazyPtrLo16 = <ISA_LIT>MCExpr :: CreateLo ( LazyPtrExpr , true , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> )

. addExpr ( LazyPtrLo16 ) . addExpr ( LazyPtrLo16 ) . addReg ( <STR_LIT> ) ) ;


<s> GlobalHeap . push_back ( <NUM_LIT> ) ; Subtarget = & TM . getSubtarget


<s> rtx high ; high = GEN_INT ( offset ) ; offset = <NUM_LIT> ; high = aarch64_force_temporary ( mode , temp , high ) ; reg = aarch64_force_temporary ( mode , temp , gen_rtx_PLUS ( mode , high ,


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg


<s> do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } fixTCReturn ( MF , MBB ) ; if ( ArgRegsSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl


<s> rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( vcall_offset < <NUM_LIT> ) ; emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( SPARC_SIMM13_P ( vcall_offset ) ) ; else if ( ! fixed_regs [ <NUM_LIT> ] && vcall_offset < - <NUM_LIT> ) { rtx scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch2 , vcall_offset_rtx ) ; vcall_offset_rtx = scratch2 ; } else { rtx increment = GEN_INT ( - <NUM_LIT> ) ; while ( ! SPARC_SIMM13_P ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch , increment ) ) ; vcall_offset += <NUM_LIT> ; } vcall_offset_rtx = GEN_INT ( vcall_offset ) ; } emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , scratch , vcall_offset_rtx ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( flag_delayed_branch ) { funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { rtx spill_reg , seq , scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( flag_pic ) { spill_reg = gen_rtx_REG ( word_mode , <NUM_LIT> ) ; start_sequence ( ) ; load_got_register ( ) ; scratch = sparc_legitimize_pic_address ( funexp , scratch ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_and_preserve ( seq , spill_reg , pic_offset_table_rtx ) ; } else if ( TARGET_ARCH32 ) { emit_insn ( gen_rtx_SET ( scratch , gen_rtx_HIGH ( SImode , funexp ) ) ) ; emit_insn ( gen_rtx_SET ( scratch , gen_rtx_LO_SUM ( SImode , scratch , funexp ) ) ) ; } else { switch ( sparc_cmodel ) { case CM_MEDLOW


<s> static DecodeStatus DecodeTestAndBranch ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { uint64_t Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t bit = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; bit |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t dst = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT>


<s> static unsigned getDRegFromQReg ( unsigned QReg ) { switch ( QReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> PM . add ( create<ISA_LIT>ISelDag ( * this , getOptLevel ( ) ) ) ; return


<s> static rtx or1k_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { if ( arg . end_marker_p ( ) ) return NULL_RTX ; CUMULATIVE_ARGS * cum = get_cumulative_args


<s> static bool loongarch_split_move_insn_p ( rtx dest , rtx src ) { return loongarch_split_move_p ( dest ,


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> isReturn ( ) && <STR_LIT> ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Align = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( Align ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned

) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return


<s> return ( vector signed short ) __builtin_altivec_vupklsb ( ( vector signed char )


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT> ) ; MCTargetStreamer & TS = * getParser ( ) . getStreamer (


<s> auto MaybeBit = getConstantVRegValWithLookThrough ( AndInst -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! MaybeBit || ! isPowerOf2_64 ( MaybeBit -> Value ) ) return false ; uint64_t Bit = Log2_64 ( static_cast < uint64_t > ( MaybeBit -> Value ) ) ; Register TestReg = AndInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Invert = Pred == CmpInst :: Predicate :: ICMP_NE ; emitTestBit ( TestReg , Bit , Invert , DstMBB , MIB ) ; return true


<s> if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE ) return true ; if ( precision == LONG_LONG_TYPE_SIZE ) return true ; return false ; case MODE_FLOAT : if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return


<s> bool WasOriginalArgFloat ( unsigned ValNo ) { return OriginalArgWasFloat [ ValNo


<s> if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; default : break ; } if ( Is64Bit )


<s> else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_LDBL128 ) == RS6000_BTM_LDBL128 ) { if ( ! TARGET_HARD_FLOAT ) error ( <STR_LIT> , name , <STR_LIT> ) ; else error ( <STR_LIT> , name , TARGET_IEEEQUAD ? <STR_LIT> : <STR_LIT> ) ; } else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128_HW ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128 ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64 ) ) == ( RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64 ) ) error ( <STR_LIT> , name , <STR_LIT>


<s> CLEAR_HARD_REG_SET ( prologue_used ) ; CLEAR_HARD_REG_SET ( set_up_by_prologue ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , STACK_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , ARG_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , HARD_FRAME_POINTER_REGNUM ) ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { crtl -> stack_realign_needed = stack_realign ; crtl -> stack_realign_finalized = true ; return ; } } if ( crtl -> drap_reg ) { basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; if ( ! REGNO_REG_SET_P ( DF_LR_IN ( bb ) , REGNO ( crtl -> drap_reg ) ) ) { crtl -> drap_reg = NULL_RTX ; crtl -> need_drap = false ; } } else cfun -> machine -> no_drap_save_restore = true ; frame_pointer_needed = false ; stack_realign = false ; crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> stack_alignment_estimated = incoming_stack_boundary ; if ( crtl -> preferred_stack_boundary > incoming_stack_boundary ) crtl -> preferred_stack_boundary = incoming_stack_boundary ; df_finish_pass ( true ) ; df_scan_alloc ( NULL ) ; df_scan_blocks ( ) ; df_compute_regs_ever_live ( true ) ; df_analyze ( ) ; } crtl -> stack_realign_needed =


<s> case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : case RecurKind :: SelectICmp : case RecurKind :: SelectFCmp : return true


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT>


<s> unsigned NumBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT ,


<s> return getTM < <ISA_LIT>TargetMachine >


<s> if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT>


<s> EVT VT = <STR_LIT> ; EVT WideVT = <STR_LIT> ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != VT ) return Op ; SDValue ShiftAmt = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue HiLHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS , ShiftAmt ) ; SDValue HiRHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS , ShiftAmt ) ; SDValue Args [ ] = { HiLHS , LHS , HiRHS ,


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = ( CC < <NUM_LIT> ) ? ( CC + <NUM_LIT> ) : CC ; break ; } O << <ISA_LIT>ARCCondCodeToString ( ( <STR_LIT> ) CC


<s> Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence


<s> DEBUG ( MF . print ( dbgs ( ) ) ) ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI -> hasAVX512 ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; EnclosedEdges . clear ( ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; unsigned ClosureID = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) )


<s> return ( __m512i ) __builtin_ia32_vplzcntq_512_mask ( ( __v8di ) __A ,


<s> if ( MFI -> isPredecessor ( MFI ) ) { I = -- MFI -> end ( ) ; return true ; } else return false ; } -- I ; return


<s> SDValue Tmp = b . XOR ( A1 , A2 ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . XOR ( Tmp , b . SHL < <NUM_LIT> > ( b . AND ( b . NOT ( A1 ) , A2 ) ) ) , Tmp ) ; } llvm_unreachable (


<s> return __builtin_ia32_ucomilt ( ( __v4sf ) __A , (


<s> SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_AVX512 ( Op , Subtarget , DAG ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> getTargetStreamer ( ) . emitARM64WinCFISaveNext (


<s> AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else { return AddCombineTo64bitMLAL ( AddeNode , DCI , Subtarget ) ; } if ( ! isNullConstant ( UmlalNode -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ( isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode ) || ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) ) ) { SelectionDAG & DAG = DCI . DAG ; SDValue Ops [ ] = { UmlalNode -> getOperand ( <NUM_LIT> ) , UmlalNode -> getOperand ( <NUM_LIT>

) , UmlalNode -> getOperand ( <NUM_LIT> ) , AddHi } ;


<s> if ( ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) { if ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isToken ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) RegIdx = <NUM_LIT> ; if ( static_cast < <ISA_LIT>Operand * > ( Operands [ RegIdx ] ) -> isReg ( ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( static_cast < <ISA_LIT>Operand * > ( Operands [ RegIdx ] ) -> getReg ( ) ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( static_cast < <ISA_LIT>Operand * >

( Operands [ RegIdx ] ) -> getReg ( ) ) ) ) return true ;


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { if ( RegSet . count ( Reg ) ) return true ; for ( const uint16_t * Alias = TM . getRegisterInfo ( ) -> getAliasSet ( Reg ) ; * Alias ; ++ Alias ) if ( RegSet . count ( * Alias ) ) return true ; return


<s> if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; OffsetInBytes += LoadSizeInBytes ; TotalBytesLoaded += LoadSizeInBytes ; Alignment = std :: min ( Alignment , LoadSizeInBytes ) ; } unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , Val ) ) ; return ; } } unsigned MemCpySize = ByValSizeInBytes -


<s> rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; emit_update = ( saved_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) ? <NUM_LIT> : <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; if ( emit_update


<s> ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , getPointerTy ( ) , CP -> getAlignment ( ) , CP -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy (


<s> return StringSwitch < bool > ( SymName ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , true ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>

, <STR_LIT> , true ) . Default ( false ) ;


<s> machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; rtx res = aarch64_sve_emit_int_cmp ( target , pred_mode , code ,


<s> return ( poly64x2_t ) __builtin_neon_vextv2di ( ( int64x2_t ) __a , (


<s> void <ISA_LIT>BaseInstrInfo :: restoreLRFromStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState ::


<s> return ( int32x4_t ) __builtin_neon_vrhaddsv4si (


<s> tree f_stack , f_grtop , f_vrtop , f_groff , f_vroff ; tree stack , grtop , vrtop , groff , vroff ; tree t ; int gr_save_area_size ; int vr_save_area_size ; int vr_offset ; cum = & crtl -> args . info ; gr_save_area_size = ( NUM_ARG_REGS - cum -> aapcs_ncrn ) * UNITS_PER_WORD ; vr_save_area_size = ( NUM_FP_ARG_REGS - cum -> aapcs_nvrn ) * UNITS_PER_VREG ; if ( TARGET_GENERAL_REGS_ONLY ) { if ( cum -> aapcs_nvrn > <NUM_LIT> ) sorry ( <STR_LIT> , <STR_LIT> ) ; vr_save_area_size = <NUM_LIT> ; } f_stack = TYPE_FIELDS ( va_list_type_node ) ; f_grtop = DECL_CHAIN ( f_stack ) ; f_vrtop = DECL_CHAIN ( f_grtop ) ; f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = AARCH64_ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t ,


<s> if ( arg0 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; scratch1 = gen_reg_rtx ( mode0 ) ; scratch2 = gen_reg_rtx ( mode0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , scratch1 , scratch2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target


<s> return getMemScale ( MI . getOpcode ( )


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { int AssemblerDialect = Ctx . getAsmInfo ( ) -> getAssemblerDialect ( ) ; return new ( Ctx ) <ISA_LIT>MCExpr (


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter (


<s> static inline unsigned long * ia64_rse_rnat_addr ( unsigned long


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( new <ISA_LIT>ExecutionDepsFix ( ) ) ; if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass


<s> SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , false ) ) return Ld ; } } if ( auto * Ld = dyn_cast < LoadSDNode > ( peekThroughOneUseBitcasts ( SubVec2 ) ) ) { if ( SubVec2 == SubVec && <STR_LIT> ( Ld ) && areOnlyUsersOf ( SubVec2 . getNode ( ) , { Op , Vec } ) && ! Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec ) ; } } } } if ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && SubVecVT . is128BitVector ( ) ) return insert128BitVector ( Vec , SubVec ,


<s> } if ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && SubVecVT . is128BitVector ( ) ) return Insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( OpVT . is512BitVector ( ) && SubVecVT . is256BitVector ( ) ) return Insert256BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( OpVT . getVectorElementType ( ) == <STR_LIT> ) { if ( IdxVal == <NUM_LIT> && Vec . getOpcode ( ) == <STR_LIT> ) return Op ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Undef = DAG . getUNDEF ( OpVT ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) ; if ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; SDValue Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec2 ,


<s> REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName != <STR_LIT> && ShiftName != <STR_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . ParseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> static void sparc_init_builtins ( void ) { if ( TARGET_VIS )


<s> int32_t HighestOne = - <NUM_LIT> ; uint32_t NonzeroEntries = <NUM_LIT> ; int SignedDigit [ <NUM_LIT> ] = { <NUM_LIT> } ; int64_t E = std :: abs ( MulAmt ) ; int S = ( MulAmt < <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; int I = <NUM_LIT> ; while ( E > <NUM_LIT> ) { int ZI = <NUM_LIT> ; if ( E % <NUM_LIT> == <NUM_LIT> ) { ZI = <NUM_LIT> - ( E % <NUM_LIT> ) ; if ( ZI != <NUM_LIT> ) ++ NonzeroEntries ; } SignedDigit [ I ] = S * ZI ; if ( SignedDigit [ I ] == <NUM_LIT> ) HighestOne = I ; E = ( E - ZI ) / <NUM_LIT> ; ++ I ; } int32_t InstrRequired = <NUM_LIT> * NonzeroEntries


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc dl ( Op ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst ) return SDValue ( ) ; unsigned Val = Cst -> getZExtValue ( ) ; unsigned Size = Op . getValueType ( ) . getSizeInBits ( ) ; if ( Val == <NUM_LIT> ) return Op ; if ( Size == <NUM_LIT> && Val * VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) return Op ; return SDValue (


<s> ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , ops ) ; return


<s> return isRegSeqTemplate < <STR_LIT> , <STR_LIT> > (


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _pext_u32 ( unsigned int __X , unsigned int __Y ) { return _pext_u64 ( __X ,


<s> return ( vector unsigned int ) __builtin_altivec_vmaxuw ( ( vector signed int ) a1 , (


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI , AllOnes ) ) return Result ; if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ; return SDValue (


<s> return ( __m512bh ) __builtin_ia32_cvtne2ps2bf16_v32hi


<s> assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; if ( InVT . getSizeInBits ( ) > <NUM_LIT> ) { assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Scale = VT . getScalarSizeInBits ( )


<s> assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) , V1 ) ; } if ( SDValue Shift = lowerVectorShuffleAsBitShift ( DL , <STR_LIT> , V1 ,


<s> return getSubtargetImpl ( ) -> getDataLayout


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , (


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return ( __m512i ) __builtin_ia32_loaddquqi512_mask ( ( __v64qi * ) __P , ( __v64qi ) _mm512_setzero_hi ( ) , (


<s> SDValue Value0 , Value1 ; std :: tie ( Value0 , Value1 ) = splitVector ( StoredVal , DAG , DL ) ; unsigned HalfAlign = ( StoredVal . getValueType ( ) . is256BitVector ( ) ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand (


<s> case PROCESSOR_R5500 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : return <NUM_LIT> ; case PROCESSOR_SB1


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { return makeAddress ( Op


<s> SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; switch ( AsmPieces . size ( ) ) { default : return false ; case <NUM_LIT> : AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString

( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) {


<s> SDValue MUL ( SDValue A , SDValue B ) { MVT VT = A . getSimpleValueType ( ) ; return DAG -> getNode ( <STR_LIT> , dl , VT , A ,


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>16InstrInfo ( <ISA_LIT>TargetMachine &


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'y' : { const char * RegName = <STR_LIT> ; if ( ! Subtarget . isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName << <STR_LIT> ; printOperand ( MI , OpNo , O ) ; return false ; } case 'U' : case 'X' : { assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; return false


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> auto CASDesired = MRI . createGenericVirtualRegister ( s128 ) ; auto CASNew = MRI . createGenericVirtualRegister ( s128 ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASDesired } , { } ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASNew } , { } ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; CAS = MIRBuilder . buildInstr ( Opcode , { CASDst } , { CASDesired , CASNew , Addr } ) ; MIRBuilder . buildExtract ( { DstLo } , { CASDst } , <NUM_LIT> ) ; MIRBuilder . buildExtract ( { DstHi } , { CASDst } , <NUM_LIT> ) ; } else { auto Ordering = ( * MI . memoperands_begin ( ) ) -> getMergedOrdering ( ) ; unsigned Opcode ; switch ( Ordering ) { case AtomicOrdering :: Acquire : Opcode =


<s> setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; for ( MVT FPVT : <STR_LIT> ( ) ) { for ( MVT OtherFPVT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , FPVT , OtherFPVT , Expand ) ; setTruncStoreAction ( FPVT , OtherFPVT , Expand ) ; } } for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setTruncStoreAction ( VT , <STR_LIT> , Expand ) ; } MVT PtrVT = <STR_LIT> ( TM . getPointerSizeInBits ( <NUM_LIT> ) ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT IntVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> &&


<s> if ( get<ISA_LIT>Subtarget ( ) . hasVSX ( ) ) addPass ( create<ISA_LIT>VSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true


<s> return getTargetTriple ( ) . getOS ( ) == Triple :: IOS && ! getTargetTriple ( ) .

isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> return ( uint16x8_t ) __builtin_aarch64_ashlv8hi ( ( int16x8_t )


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( )


<s> if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getScalarSizeInBits ( ) < Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> int numArgs = mInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & mInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <NUM_LIT> ; int valArgIndx = <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits


<s> size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; return CEIL ( size


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; auto * And1C = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! And1C ) return false ; APInt MaskVal = And1C -> getAPIntValue ( ) ; unsigned MaskLZ = MaskVal . countLeadingZeros ( ) ; if ( ! MaskLZ || ( VT == <STR_LIT> && MaskLZ == <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> && MaskLZ >= <NUM_LIT> ) { MaskLZ -= <NUM_LIT> ; MaskVal = MaskVal . trunc ( <NUM_LIT> ) ; } SDValue And0 = And -> getOperand ( <NUM_LIT> ) ; APInt HighZeros = APInt :: getHighBitsSet ( MaskVal . getBitWidth ( ) , MaskLZ ) ; APInt NegMaskVal = MaskVal | HighZeros ; unsigned MinWidth = NegMaskVal . getMinSignedBits ( ) ; if ( MinWidth > <NUM_LIT> || ( MinWidth > <NUM_LIT> && MaskVal . getMinSignedBits ( ) <= <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> && MaskVal . getBitWidth ( ) < <NUM_LIT> ) { NegMaskVal = NegMaskVal . zext ( <NUM_LIT> ) ; HighZeros = HighZeros . zext ( <NUM_LIT> ) ; } if ( ! CurDAG -> MaskedValueIsZero ( And0 , HighZeros ) ) return false ; if ( NegMaskVal . isAllOnes ( ) ) { ReplaceNode ( And , And0 . getNode ( ) ) ; return


<s> V = NegV ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( Vec , DAG , LegalOperations , CodeSize ) ) { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegV , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , NegA != NegB , NegC , false ) ; SelectionDAG :: FlagInserter FlagsInserter ( DAG , Flags ) ; if ( IsStrict ) { assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( NewOpcode , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , A , B , C } ) ; }


<s> static inline unsigned getT1tRd ( uint32_t insn ) { return slice ( insn , <NUM_LIT> ,


<s> StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer * TStreamer = static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer


<s> const auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsWin64 = Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ; unsigned FixedObject = IsWin64 ? alignTo ( AFI -> getVarArgsGPRSize ( ) , <NUM_LIT> ) : <NUM_LIT> ; unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize


<s> void <ISA_LIT>ATTInstPrinter :: printSSECC ( const MCInst * MI , unsigned Op , raw_ostream & O ) { switch ( MI -> getOperand ( Op ) . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( is64Bit ) PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AssemblerDialect =


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; O << MO . getImm


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasThumb2DSP ( ) && ( FlagsVal & <NUM_LIT> ) ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal


<s> const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; const TargetRegisterClass & RC = * MRI . getRegClass ( DstReg ) ; assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( TRI . getRegSizeInBits ( RC ) / <NUM_LIT>


<s> bool SeenDef = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { if ( MO . isUse ( ) ) return false ; SeenDef = true ; } } if ( SeenDef ) return true ; ++ Iter ; while ( Iter != E && Iter -> isDebugValue ( ) ) ++ Iter ; } if ( Iter == E ) { for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugValue ( ) ) -- Iter ; bool SawKill =


<s> rtx elem = RTVEC_ELT ( vec , i ) ; if ( ! mips_constant_elt_p ( elem ) ) RTVEC_ELT ( vec , i ) = CONST0_RTX ( GET_MODE (


<s> spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; } return


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonalityIndex ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnwindRaw ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveMovSP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveAlign ( DirectiveID . getLoc


<s> mode = V2DImode ; dest = adjust_address ( dest , V2DImode , <NUM_LIT> ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source ,


<s> if ( MCTargetOptions :: cheriCapabilityTableABI ( ) == CheriCapabilityTableABI :: Pcrel ) { MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const GlobalValue * FName = & MF . getFunction ( ) ; Register Tmp1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register Tmp2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Tmp1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ABIGlobalCapReg ) . addReg ( getCapEntryPointReg ( ) ) . addReg ( Tmp2 ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , CapGlobalBaseReg ) . addReg ( ABIGlobalCapReg ) ; }


<s> Instruction * BroadcastSplat = nullptr ; Constant * Const = nullptr ; if ( ! match ( Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction

( IV ) , m_Zero ( ) ) ) ) return false ;


<s> SDLoc dl ( Op ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op .

getOperand ( <NUM_LIT> ) , FIdx , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> if ( Subtarget -> isAIXABI ( ) && Subtarget -> hasP10Vector ( ) ) return <STR_LIT> ; if ( Subtarget -> hasP9Vector ( ) )


<s> assert ( Op . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; return insert1BitVector ( Op , DAG


<s> unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ;


<s> unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode ( I -> getOpcode ( ) ) : getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB ; if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) { ++ NumPreFolded ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { ++ NumPostFolded ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) <<


<s> MachineMemOperand * <ISA_LIT>InstrInfo :: GetMemOperand ( MachineBasicBlock & MBB , int FI , MachineMemOperand :: Flags Flags ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI )

, Flags , MFI . getObjectSize ( FI ) , Align ) ;


<s> int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII , address , fMode ) ; if (


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( Prefix , StartLoc ,


<s> static SDValue combine<ISA_LIT>GatherScatter ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { auto * MemOp = cast < <ISA_LIT>MaskedGatherScatterSDNode > ( N ) ; SDValue BasePtr = MemOp -> getBasePtr ( ) ; SDValue Index = MemOp -> getIndex ( ) ; SDValue Scale = MemOp -> getScale ( ) ; SDValue Mask = MemOp -> getMask ( ) ; if ( ( Index . getOpcode ( ) == <STR_LIT> || ( Index . getOpcode ( ) == <STR_LIT> && Index . getOperand ( <NUM_LIT> ) == Index . getOperand ( <NUM_LIT> ) ) ) && isa < ConstantSDNode > ( Scale ) && BasePtr . getScalarValueSizeInBits ( ) == Index . getScalarValueSizeInBits ( ) ) { unsigned ShiftAmt = Index . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : Index . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t ScaleAmt = cast < ConstantSDNode > ( Scale ) -> getZExtValue ( ) ; uint64_t NewScaleAmt = ScaleAmt * ( <NUM_LIT> << ShiftAmt ) ; if ( isPowerOf2_64 ( NewScaleAmt ) && NewScaleAmt <= <NUM_LIT> ) { SDValue NewIndex = Index . getOperand ( <NUM_LIT> ) ; SDValue NewScale = DAG . getTargetConstant ( NewScaleAmt , SDLoc ( N ) , Scale . getValueType ( ) ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return getAVX2GatherNode ( N -> getOpcode ( ) , SDValue ( N , <NUM_LIT> ) , DAG , MemOp -> getOperand ( <NUM_LIT> ) , Mask , MemOp -> getBasePtr ( ) , NewIndex , NewScale , MemOp -> getChain ( ) , Subtarget ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return getScatterNode ( N -> getOpcode ( ) , SDValue ( N , <NUM_LIT> ) , DAG , MemOp -> getOperand ( <NUM_LIT> ) , Mask , MemOp -> getBasePtr ( ) , NewIndex , NewScale , MemOp -> getChain ( ) , Subtarget ) ; } } if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI


<s> return __builtin_aarch64_fmulxv2sf ( __a ,


<s> if ( TARGET_64BIT_CR_REGS && ( regclass == CR_REGS || regclass == LOADABLE_CR_REGS ) && ( GET_MODE_SIZE ( to ) < <NUM_LIT> || GET_MODE_SIZE ( from )


<s> void Warning ( SMLoc L , const Twine


<s> if ( errorToBool ( StatusOrErr . takeError ( ) ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( isNegative ) RealVal . changeSign ( ) ; if ( AddFPZeroAsLiteral && RealVal . isPosZero ( ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; } else Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( RealVal , * StatusOrErr == APFloat :: opOK , S , getContext ( ) ) ) ; } Parser . Lex ( ) ; return MatchOperand_Success


<s> return ( int16x4_t ) __builtin_neon_vdup_nv4hi ( (


<s> static bool nds32_needs_double_word_align ( machine_mode mode , const_tree type ) { unsigned int align ; align = NDS32_MODE_TYPE_ALIGN (


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > (


<s> int single_const_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( big_const_operand ( op , mode ) || GET_CODE ( op ) == CONST || GET_CODE ( op ) == LABEL_REF || GET_CODE ( op ) == SYMBOL_REF ) return <NUM_LIT> ; return <NUM_LIT>


<s> return getTM < <ISA_LIT>TargetMachine >


<s> int getVariadicStackIdx ( ) const { return


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op


<s> } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; MCSym = Get<ISA_LIT>GVSymbol ( GV ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( MAI -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create (

ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ;


<s> Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; UnscaledOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmIdx = <NUM_LIT> ; IsSigned = true ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmIdx = <NUM_LIT> ; IsSigned = true ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmIdx = <NUM_LIT> ; IsSigned = true ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; } Offset += MI . getOperand ( ImmIdx ) . getImm ( ) * Scale ; bool useUnscaledOp = false ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> || ( Offset < <NUM_LIT> && UnscaledOp != <NUM_LIT> ) ) useUnscaledOp = true ; unsigned MaskBits ; if ( IsSigned ) { MaskBits = <NUM_LIT> ; Offset /= Scale ; } else if ( UnscaledOp == <NUM_LIT> || useUnscaledOp ) { MaskBits = <NUM_LIT> ; IsSigned = true ; Scale = <NUM_LIT> ; } else { MaskBits = <NUM_LIT> ; IsSigned = false ; Offset /= Scale ; } int MaxOff = ( <NUM_LIT> << ( MaskBits - IsSigned ) )


<s> MSRReg = SysReg -> Writeable ? SysReg -> Encoding : - <NUM_LIT> ; } else MRSReg = MSRReg = <STR_LIT> ( Tok . getString ( ) ) ; auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( )


<s> const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR : return MCFixupKind ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR_HI16 : return MCFixupKind ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR_LO16


<s> bool <ISA_LIT>FastISel :: selectFPTrunc ( const Instruction * I ) { Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isFloatTy ( ) || ! V -> getType ( ) -> isDoubleTy ( ) ) return false ; Register Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; Register ResultReg = createResultReg (


<s> const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; bool is32Bit = TLI . getValueType ( I -> getType ( ) ) == <STR_LIT> ; const TargetRegisterClass * RC = is32Bit ? RC32 : RC64 ; unsigned SrcReg = is32Bit ? GPR32ArgRegs [ Idx ] : GPR64ArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; UpdateValueMap ( I , ResultReg


<s> static bool mayTailCallThisCC ( CallingConv :: ID


<s> assert ( Elements . size ( ) == NumElems ) ; return DAG -> getNode ( <STR_LIT> , dl , VT , Elements


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } Register ValReg = getRegForValue


<s> COFF :: IMAGE_FILE_MACHINE_I386 ) , Is64Bit (


<s> void <ISA_LIT>ELFStreamer :: FinishImpl ( ) { MCTargetStreamer & TS = getTargetStreamer ( ) ; <ISA_LIT>TargetStreamer & ATS = static_cast < <ISA_LIT>TargetStreamer


<s> return ( __m128i ) __builtin_ia32_pmovqw512_mask ( ( __v8di ) __A , ( __v8hi )

_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_HI12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_HI12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12_NC : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC_LO12 : FixupKind = <STR_LIT>


<s> SDValue L1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue HRes = DAG . getNode ( Opcode , DL , <STR_LIT> , H0 , H1 ) ; SDValue LRes = DAG . getNode ( Opcode , DL , <STR_LIT> , L0 , L1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , HRes , LRes ) ; } return DAG . getNode ( Opcode , DL ,


<s> } else if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) ; O << markup ( <STR_LIT> ) << '$' << formatImm ( Imm ) << markup ( <STR_LIT> ) ; if ( CommentStream && ! HasCustomInstComment && ( Imm > <NUM_LIT> || Imm < - <NUM_LIT> ) ) { if ( Imm == ( int16_t ) ( Imm ) ) * CommentStream << format ( <STR_LIT> PRIX16 <STR_LIT> , ( uint16_t ) Imm ) ; else if ( Imm == ( int32_t ) ( Imm ) ) * CommentStream << format ( <STR_LIT> PRIX32 <STR_LIT> , ( uint32_t ) Imm ) ; else * CommentStream << format ( <STR_LIT> PRIX64 <STR_LIT> , ( uint64_t ) Imm ) ; } } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << markup ( <STR_LIT> ) << '$' ; Op . getExpr ( ) -> print ( O ,


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype ) ,


<s> if ( Ty -> isHalfTy ( ) || Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) return true ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) return true ; return false


<s> unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg = fastEmitInst_rri ( Opc , RC , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CC ) ; updateValueMap ( I


_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved , vr_saved ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; gr_saved = NUM_ARG_REGS - local_cum . aapcs_ncrn ; vr_saved = NUM_FP_ARG_REGS - local_cum . aapcs_nvrn ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == <NUM_LIT> ) ; vr_saved = <NUM_LIT> ; } if ( ! no_rtl ) { if ( gr_saved > <NUM_LIT> ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > <NUM_LIT> ) { machine_mode mode = TImode ; int off , i ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY


<s> llvm :: FastISel * <STR_LIT> ( MachineFunction & mf , MachineModuleInfo * mmi , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , <NUM_LIT> > & cil ) { return new <ISA_LIT>FastISel ( mf , mmi , dw , vm ,


<s> APInt UndefElts ( NumMaskElts , <NUM_LIT> ) ; APInt ZeroElts ( NumMaskElts , <NUM_LIT> ) ; APInt ConstantElts ( NumMaskElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > ConstantBitData ( NumMaskElts , APInt :: getZero ( MaskSizeInBits ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { UndefElts . setBit ( i ) ; continue ; } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts . setBit ( i ) ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( !


<s> auto Op = MI -> getOperand ( OpNum ) ; auto CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str = condCodeToString ( CC ) ; O <<


<s> static tree sh_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( bdesc ) ) return error_mark_node ; if ( ! bdesc [ code ] . is_enabled ( ) )


<s> unsigned getFCCReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_FCC ) && <STR_LIT>


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Lo = DAG . getNode ( ExtOpc , dl , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( ExtOpc , dl , <STR_LIT> , Hi ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask , APInt & UndefElts ) { SmallVector < APInt , <NUM_LIT> > EltBits ; if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits , true , false ) )


<s> if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != <NUM_LIT> )

add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ;


<s> static void mips_set_tuning_info ( void ) { if ( mips_tuning_info . initialized_p && mips_tuning_info . arch == mips_arch && mips_tuning_info . tune == mips_tune && mips_tuning_info . mips16_p == TARGET_MIPS16 ) return ; mips_tuning_info . arch = mips_arch ; mips_tuning_info . tune = mips_tune ; mips_tuning_info . mips16_p = TARGET_MIPS16 ; mips_tuning_info . initialized_p = true ; dfa_start ( ) ; struct mips_sim state ; mips_sim_init ( & state , alloca ( state_size ( ) )


<s> static bool shouldScheduleAdjacent ( const TargetInstrInfo & TII , const TargetSubtargetInfo & TSI , const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { const <ISA_LIT>InstrInfo & II = static_cast < const <ISA_LIT>InstrInfo & > ( TII ) ; const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( TSI ) ; unsigned FirstOpcode = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpcode = SecondMI . getOpcode ( ) ; if ( ST . hasArithmeticBccFusion ( ) ) if ( SecondOpcode == <STR_LIT> ) switch ( FirstOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! II . hasShiftedReg ( * FirstMI ) ; case <STR_LIT> : return true ; } if ( ST . hasArithmeticCbzFusion ( ) ) if ( SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> ) switch ( FirstOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDLoc DL ( N ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( LHS ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! TrueC || ! FalseC ) return SDValue ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS . getValueType ( ) ) ) return SDValue ( ) ; bool NeedsCondInvert = false ; if ( TrueC -> getAPIntValue ( ) . ult ( FalseC -> getAPIntValue ( ) ) && ( Cond . getOpcode ( ) == <STR_LIT> || ( Cond . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) ) ) { NeedsCondInvert = true ; std :: swap ( TrueC , FalseC ) ; } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; return DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , DL , <STR_LIT> ) ) ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; return DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { APInt Diff = TrueC -> getAPIntValue (


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; return false


<s> assert ( Op . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand


<s> I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_FRAME_INDEX ) { addOffset ( MIB , <NUM_LIT> ) ; } else { MachineOperand & InxOp = I . getOperand ( <NUM_LIT> ) ; I . addOperand ( InxOp ) ; InxOp . ChangeToImmediate ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } return constrainSelectedInstRegOperands ( I , TII , TRI ,


<s> DecodeStatus <ISA_LIT>64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>6432 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size =


<s> static bool is128BitUnpackShuffleMask ( ArrayRef < int > Mask ) { MVT EltVT = <STR_LIT> ( <NUM_LIT> / Mask . size ( ) ) ; MVT VT = <STR_LIT> ( EltVT , Mask . size ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SmallVector < int , <NUM_LIT> >


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ; AsmParser . warnIfAssemblerTemporary ( RegIdx


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * MBB ) const { llvm_unreachable (


<s> HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 =


<s> CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register NewVal = MRI . createVirtualRegister ( RC ) ; Register RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; Register RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; Register RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( UpdateMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB -> addSuccessor ( UseAltMBB ) ; MBB = UseAltMBB ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedAltVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB = UpdateMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addMBB ( LoopMBB ) . addReg ( RotatedAltVal ) . addMBB ( UseAltMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal )

. addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ;


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT>


<s> PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } else continue ; } else continue ; unsigned PtrAddrSpace = PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ; if ( PtrAddrSpace ) continue ; if ( ST && ST -> hasAltivec ( ) && PtrValue -> getType ( ) -> getPointerElementType ( ) -> isVectorTy ( ) ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE -> getSCEVAtScope ( PtrValue , L ) ; if ( const SCEVAddRecExpr * LARSCEV = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ) { if ( LARSCEV -> getLoop ( ) != L ) continue ; } else { continue ; } bool FoundBucket = false ; for ( unsigned i = <NUM_LIT> , e = Buckets . size ( ) ; i != e ; ++ i ) for ( Bucket :: iterator K = Buckets [ i ] . begin ( ) , KE = Buckets [ i ] . end ( ) ; K != KE ; ++ K ) { const SCEV * Diff = SE -> getMinusSCEV ( K -> first , LSCEV ) ; if ( isa < SCEVConstant > ( Diff ) ) { Buckets [ i ] . insert ( std :: make_pair ( LSCEV , MemI ) ) ; FoundBucket = true ; break ; } } if ( ! FoundBucket ) { Buckets . push_back ( Bucket ( SCEVLess ( SE ) ) ) ; Buckets [ Buckets . size ( ) - <NUM_LIT> ] . insert ( std :: make_pair ( LSCEV , MemI ) ) ; } } } if ( Buckets . empty ( ) || Buckets . size ( ) > MaxVars ) return MadeChange ; BasicBlock * LoopPredecessor = L -> getLoopPredecessor ( ) ; if ( ! LoopPredecessor || ! LoopPredecessor -> getTerminator ( ) -> getType ( ) -> isVoidTy ( ) ) { LoopPredecessor = InsertPreheaderForLoop ( L , this ) ; if ( LoopPredecessor ) MadeChange = true ; } if ( ! LoopPredecessor ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Buckets . size ( ) << <STR_LIT> ) ; SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( unsigned i = <NUM_LIT> , e = Buckets . size ( ) ; i != e ; ++ i ) { const SCEVAddRecExpr * BasePtrSCEV = cast < SCEVAddRecExpr > ( Buckets [ i ] . begin ( ) -> first ) ; if ( ! BasePtrSCEV -> isAffine ( ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * BasePtrSCEV << <STR_LIT> ) ; assert ( BasePtrSCEV -> getLoop ( ) == L && <STR_LIT> ) ; Instruction * MemI = Buckets [ i ] . begin ( ) -> second ; Value * BasePtr = GetPointerOperand ( MemI ) ; assert ( BasePtr


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo >


<s> if ( Subtarget -> has<ISA_LIT>32 ( ) && ! Subtarget -> has<ISA_LIT>32r6 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMADD ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op00 = Op0 . getOperand (


<s> return ( __m128d ) __builtin_ia32_vfmaddpd128_mask3 ( ( __v2df ) __A , ( __v2df )


<s> <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc (


<s> case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; ISDNo = <STR_LIT> ; OpTy = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; ISDNo = <STR_LIT> ; OpTy = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; ISDNo = <STR_LIT> ; OpTy = <STR_LIT> ; break ; } assert ( ISDNo && <STR_LIT> ) ; unsigned MaskVals = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < MaskSize ; ++ i ) { int EltIdx = SVOp -> getMaskElt ( i ) ; if ( EltIdx == i || EltIdx == - <NUM_LIT> ) MaskVals |= ( <NUM_LIT> << i ) ; else if ( EltIdx == ( i + MaskSize ) ) continue ; else return SDValue ( ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , OpTy , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , OpTy , V2 ) ; SDValue Ret = DAG . getNode ( ISDNo , dl , OpTy , V1 , V2 , DAG . getConstant ( MaskVals , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ret