<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA


<s> SDLoc DL ( N ) ; const SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( And . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftOpc = Shift . getOpcode ( ) ; if ( ( ShiftOpc != <STR_LIT> && ShiftOpc != <STR_LIT> ) ) return SDValue ( ) ; bool IsShiftRight = ShiftOpc == <STR_LIT> ; ConstantSDNode * C2node = dyn_cast < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ; if ( ! C2node ) return SDValue ( ) ; uint64_t C1 ; if ( ! isAllConstantBuildVector ( And . getOperand ( <NUM_LIT> ) , C1 ) ) return SDValue ( ) ; uint64_t C2 = C2node -> getZExtValue ( ) ; unsigned ElemSizeInBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( C2 > ElemSizeInBits ) return SDValue ( ) ; unsigned ElemMask = ( <NUM_LIT> << ElemSizeInBits ) - <NUM_LIT> ; if ( ( C1 & ElemMask ) != ( ~ C2 & ElemMask ) ) return SDValue ( ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; SDValue Y = Shift . getOperand ( <NUM_LIT> ) ; unsigned Intrin = IsShiftRight ? <STR_LIT> : <STR_LIT> ; SDValue ResultSLI = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Intrin , DL , <STR_LIT> ) , X , Y , Shift . getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) <<


<s> vec_uint4 mask ; neg_b = vec_splat ( ( vec_uint4 ) ( si_from_int ( - b ) ) , <NUM_LIT> ) ; mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> tokens . push_back ( std :: string ( ) ) ; std :: getline ( ss , tokens . back ( ) , ',' ) ; } if ( tokens . empty ( ) ) err_ret ( <STR_LIT> ) ; { for ( size_t i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) if ( tokens . front ( ) == model_names [ i ] ) { ret . type = ( <STR_LIT> ) i ; ret . name = model_names [ i ] ; ret . cdef_name = model_cdef_names [ i ] ; goto got_mode_name ; } err_ret ( <STR_LIT> , tokens . front ( ) . c_str ( ) ) ; got_mode_name : ; } for ( size_t i = <NUM_LIT> ; i < tokens . size ( ) ; ++ i ) { if ( tokens [ i ] == <STR_LIT> ) ret . strict = true ; else if ( tokens [ i ] . find ( <STR_LIT> ) == <NUM_LIT> ) { std :: string offset_str = tokens [ i ]


<s> return ( __m64 ) __builtin_ia32_pmulhuw ( ( __v4hi


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DestVT = N -> getValueType ( <NUM_LIT> ) ; assert ( DestVT . getSizeInBits ( ) > <NUM_LIT> && <STR_LIT> ) ; if ( SrcVT . getSizeInBits ( ) * <NUM_LIT> != DestVT . getSizeInBits ( ) && SrcVT . getSizeInBits ( ) * <NUM_LIT> != DestVT . getSizeInBits ( ) ) return SDValue ( ) ; SDLoc dl ( N ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned DestEltSize = DestVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; SDValue Mid , SplitLo , SplitHi , ExtLo , ExtHi ; EVT MidVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts ) ; EVT SplitVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts / <NUM_LIT> ) ; EVT ExtVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , DestEltSize ) , NumElts /


<s> static rtx gen_tls_get_addr ( void ) { if ( ! gen_tls_tga ) gen_tls_tga = init_one_libfunc ( <STR_LIT> ) ; return


<s> for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; MI . eraseFromParent


<s> assert ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; TrueOp = <NUM_LIT> ; FalseOp = <NUM_LIT> ; Cond . push_back ( MI -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MI -> getOperand ( <NUM_LIT> )


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Target & T , const StringRef & TT ) { Data16bitsDirective = <STR_LIT>


<s> OS << markup ( <STR_LIT> ) << getRegisterName ( RegNo ) << markup


<s> static bool hasUndefRegUpdate ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int ExtractIdx = ( int ) N -> getConstantOperandVal ( <NUM_LIT> ) ; int Scale = Mask . size ( ) / NumSrcElts ; int Lo = Scale * ExtractIdx ; int Hi = Scale * ( ExtractIdx + <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = ( int ) Mask . size ( ) ; i != e ; ++ i ) if ( i < Lo || Hi <= i ) Mask [ i ] = SM_SentinelUndef ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || (

SrcVT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) {


<s> OutOps . push_back ( Op ) ; return false ; default : break ; } return


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count % <NUM_LIT>


<s> case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; case ENCODING_IB : if ( sawRegImm ) { insn -> immediates [ insn -> numImmediatesConsumed ] = insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] & <NUM_LIT> ; ++ insn -> numImmediatesConsumed ; break ; } if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( insn -> spec -> operands [ index ] . type == TYPE_IMM3 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( insn -> spec -> operands [ index ] . type == TYPE_IMM5 && insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] > <NUM_LIT> ) return - <NUM_LIT> ; if ( insn -> spec -> operands [ index ] . type == TYPE_XMM128 || insn -> spec -> operands [ index ] . type == TYPE_XMM256 ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : if ( readImmediate ( insn , insn -> immediateSize ) ) return - <NUM_LIT> ; break ; case ENCODING_Ia : if ( readImmediate ( insn , insn -> addressSize ) ) return - <NUM_LIT> ; break ; case ENCODING_RB : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RW : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RD : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RO


<s> MBBInfos . resize ( MF -> size ( ) ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB ->


<s> static bool is_leaf_function ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; if ( fn -> cfg == NULL ) return


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = I64RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> i = mips16e_find_first_register ( * mask_ptr , regs , size ) ; for ( i ++ ; i < size ; i ++ ) if ( ! BITSET_P ( * mask_ptr , regs [ i ] ) ) { * num_regs_ptr += <NUM_LIT> ; * mask_ptr |= <NUM_LIT> << regs [ i


<s> return ( cost + set_src_cost ( XEXP ( x , <NUM_LIT> ) , GET_MODE ( x ) , speed ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , GET_MODE

( x ) , GET_CODE ( x ) , <NUM_LIT> , speed ) ) ;


<s> MachineInstr * FoldCmp = tryFoldIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( FoldCmp ) return { FoldCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; unsigned CmpOpc = <NUM_LIT> ; Register ZReg ; LLT CmpTy = MRI . getType ( LHS . getReg ( ) ) ; assert ( ( CmpTy . isScalar ( ) || CmpTy . isPointer ( ) ) && <STR_LIT> ) ; if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) || CmpTy . isPointer ( ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else { return { nullptr , CmpInst :: Predicate :: BAD_ICMP_PREDICATE } ; } MachineInstr * ImmedCmp = tryOptArithImmedIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( ImmedCmp ) return { ImmedCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; MachineInstr * ShiftedCmp = tryOptArithShiftedCompare ( LHS , RHS , MIRBuilder ) ; if ( ShiftedCmp ) return { ShiftedCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; auto CmpMI = MIRBuilder . buildInstr ( CmpOpc , { ZReg } , { LHS . getReg ( ) , RHS . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; return { & * CmpMI , ( CmpInst :: Predicate ) Predicate . getPredicate


<s> bool <ISA_LIT>FastISel :: SelectIntrinsicCall ( const IntrinsicInst & I ) { switch ( I . getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; const char * IntrMemName = isa < MemCpyInst > ( I ) ? <STR_LIT> : <STR_LIT> ; return SelectCall ( & I , IntrMemName ) ; } case <STR_LIT> : { const MemSetInst & MSI = cast <


<s> std :: vector < LiveRange * > getInterferingLiveRangesFor ( LiveRange * LR ) { std :: vector < LiveRange


<s> auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . hasMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError (

<STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ;


<s> bool enablePostRAScheduler ( ) const


<s> if ( TARGET_THUMB1 ) thumb1_reorg ( ) ; else if ( TARGET_THUMB2 ) thumb2_reorg ( ) ; if ( ! optimize ) split_all_insns_noflow ( ) ; minipool_fix_head = minipool_fix_tail = NULL ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; minipool_pad = <NUM_LIT> ; for ( insn = next_nonnote_insn ( insn ) ; insn ; insn = next_nonnote_insn ( insn ) ) { if ( BARRIER_P ( insn ) ) push_minipool_barrier ( insn , address ) ; else if ( INSN_P ( insn ) ) { rtx_jump_table_data * table ; note_invalid_constants ( insn , address , true ) ; address += get_attr_length ( insn ) ; if ( tablejump_p ( insn , NULL , & table ) ) { address += get_jump_table_size ( table ) ; insn = table ; } } else if ( LABEL_P ( insn ) ) address += get_label_padding ( insn ) ; } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix *


<s> if ( MO . isReg ( ) && <STR_LIT> . contains ( MO . getReg ( )


<s> return ( Op . isMem ( ) && ( Op . Mem . SegReg == <NUM_LIT> || Op . Mem . SegReg == <STR_LIT> ) && isa < MCConstantExpr > ( Op . Mem . Disp ) && cast < MCConstantExpr > ( Op . Mem . Disp ) -> getValue ( ) == <NUM_LIT> && Op . Mem . BaseReg == basereg


<s> if ( pool_size ) { fprintf ( asm_out_file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ; output_asm_insn ( <STR_LIT> , & p -> value ) ; } pool_size = <NUM_LIT>


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) , DL ( getSubtargetImpl ( ) -> isTarget64BitILP32 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo


<s> if ( MCDisableArithRelaxation ) return false ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; bool hasExp = false ; bool hasRIP = false ; for ( unsigned i = <NUM_LIT> ; i < Inst . getNumOperands ( ) ;


<s> } switch ( Ext ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ;


<s> SDLoc DL ( N ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( NewIID , DL , <STR_LIT> ) ; return DAG . getNode ( N -> getOpcode ( ) , DL ,


<s> MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; } else { MemVT = getContainerForFixedLengthVector ( DAG , MemVT ) ; IndexVT = MemVT . changeTypeToInteger ( ) ; } InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } if ( PassThru -> isUndef ( ) || isZerosVector ( PassThru . getNode ( ) ) ) PassThru = SDValue ( ) ; if ( VT . isFloatingPoint ( ) && ! IsFixedLength ) { if ( PassThru ) { EVT PassThruVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; PassThru = getSVESafeBitCast ( PassThruVT , PassThru , DAG ) ; } InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( IndexVT , <STR_LIT> ) ; if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getGatherVecOpcode ( IsScaled , IsSigned , IdxNeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , true , DAG ) ; if ( ExtTy == <STR_LIT> ) Opcode = getSignExtendedGatherOpcode ( Opcode ) ; if ( IsFixedLength ) { if ( Index . getSimpleValueType ( ) . isFixedLengthVector ( ) ) Index = convertToScalableVector ( DAG , IndexVT , Index ) ; if ( BasePtr . getSimpleValueType ( ) . isFixedLengthVector ( ) ) BasePtr = convertToScalableVector ( DAG , IndexVT , BasePtr ) ; Mask = convertFixedMaskToScalableVector ( Mask , DAG ) ; } SDValue Ops [ ] = { Chain , Mask , BasePtr , Index , InputVT } ; SDValue Result = DAG . getNode ( Opcode , DL , VTs , Ops ) ; Chain = Result . getValue ( <NUM_LIT> ) ; if ( IsFixedLength ) { Result = convertFromScalableVector ( DAG , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Result ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Result ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result ) ; if ( PassThru ) Result = DAG . getSelect ( DL , VT , MGT -> getMask ( ) , Result , PassThru ) ; } else { if ( PassThru ) Result = DAG . getSelect ( DL , IndexVT , Mask , Result , PassThru ) ; if ( VT . isFloatingPoint ( ) ) Result = getSVESafeBitCast ( VT , Result , DAG ) ; } return DAG . getMergeValues ( { Result , Chain }


<s> static Relocator :: DWord helper_thumb32_cond_branch_offset ( Relocator :: DWord pUpper16 , Relocator :: DWord pLower16 ) { uint32_t s = ( pUpper16 & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t j1 = ( pLower16 & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t j2 = ( pLower16 & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t lower = ( pLower16 & <NUM_LIT> ) ; uint32_t upper = ( s << <NUM_LIT> ) | ( j2 << <NUM_LIT>


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E )


<s> return DecodeGPRSeqPairsClassRegisterClass ( Inst , <STR_LIT> ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto * Regs = Subtarget -> getSpecialRegisters ( ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error (


<s> Inst . addOperand ( MCOperand :: CreateReg ( getFGR32Reg ( )


<s> bool useRegsForByval ( ) const { return CallConv != CallingConv ::


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( const Function & F , Type * Ty ) const { switch ( Ty -> getScalarType ( ) -> getTypeID ( ) ) { case Type :: FloatTyID : case Type ::


<s> PostGenericScheduler :: leaveMBB ( )


<s> f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_res = DECL_CHAIN ( f_fpr ) ; f_ovf = DECL_CHAIN ( f_res ) ; f_sav = DECL_CHAIN ( f_ovf ) ; valist = build_simple_mem_ref ( valist ) ; gpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , unshare_expr ( valist ) , f_fpr , NULL_TREE ) ; ovf = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , unshare_expr ( valist ) , f_ovf , NULL_TREE ) ; sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , unshare_expr ( valist ) , f_sav , NULL_TREE ) ; words = crtl -> args . info . words ; n_gpr = MIN ( crtl -> args . info . sysv_gregno - GP_ARG_MIN_REG , GP_ARG_NUM_REG ) ; n_fpr = MIN ( crtl -> args . info . fregno - FP_ARG_MIN_REG , FP_ARG_NUM_REG ) ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , words , n_gpr , n_fpr ) ; if ( cfun


<s> Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> , ShiftAmt ) } ) ; if ( CountThree ) return true ; for ( ShiftAmt += <NUM_LIT> ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> ,


<s> d . vmode = V2SFmode ; d . nelt = <NUM_LIT> ; d . one_operand_p = false ; d . testing_p = false ; which = INTVAL ( operands [ <NUM_LIT> ] ) ; gcc_assert ( which <= <NUM_LIT> ) ; d . perm [ <NUM_LIT> ] = <NUM_LIT>


<s> } unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; } SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDIMask ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDISMask ) ) , <NUM_LIT> ) ; SDValue TotalVal ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal = ANDIVal ; else TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; if ( ! Res ) Res = TotalVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , TotalVal ) , <NUM_LIT> ) ; for ( auto I = BitGroups . begin ( ) ; I != BitGroups . end (


<s> bool isTargetCygMing ( ) const { return TargetType == isMingw || TargetType


<s> if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( type != NULL_TREE ) ; if ( POINTER_TYPE_P ( type ) ) { gcc_assert ( TYPE_MODE ( type ) == Pmode ) ; if ( cfun -> machine -> func_type == TYPE_INTERRUPT ) arg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; else arg = arg_pointer_rtx ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( type ) == INTEGER_TYPE && TYPE_MODE ( type ) == word_mode ) ; arg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode ,

arg_pointer_rtx , - UNITS_PER_WORD ) ) ;


<s> const MachineOperand & MO = MI -> getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ; assert ( MO . isImm ( ) && <STR_LIT> ) ; O << <STR_LIT> << lsb <<


<s> EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( std :: move ( Cs ) ) ; } llvm :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front ( ) ) ; } ) ; int Parity = <NUM_LIT>


<s> bool FixupLEAPass :: runOnMachineFunction ( MachineFunction & Func ) { TM = & Func . getTarget ( ) ; const <ISA_LIT>Subtarget & ST = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM -> getInstrInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true


<s> static rtx crx_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED ,


<s> return ( int32x4_t ) __builtin_aarch64_sqnegv4si


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; unsigned BasePointerReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; unsigned ExtraCSSpill = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { const unsigned Reg = CSRegs [ i ] ; if ( Reg == BasePointerReg ) SavedRegs . set ( Reg ) ; bool RegUsed = SavedRegs . test ( Reg ) ; unsigned PairedReg = CSRegs [ i ^ <NUM_LIT> ] ; if ( ! RegUsed ) { if ( <STR_LIT> . contains ( Reg ) && ! RegInfo -> isReservedReg ( MF , Reg ) ) { UnspilledCSGPR = Reg ; UnspilledCSGPRPaired = PairedReg ; } continue ; } if ( produceCompactUnwindFrame ( MF ) && PairedReg != <STR_LIT> && ! SavedRegs . test ( PairedReg ) ) { SavedRegs . set ( PairedReg ) ; if ( <STR_LIT> . contains ( PairedReg ) && ! RegInfo -> isReservedReg ( MF , PairedReg ) ) ExtraCSSpill = PairedReg ; } } unsigned CSStackSize = <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo (


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo


<s> const MCOperand & ScaleOp = MI -> getOperand ( OpNum ) ; O << '#' << ( <NUM_LIT> -


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn (


<s> int k = <NUM_LIT> ; if ( align_words < GP_ARG_NUM_REG ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG || mode == BLKmode || ( TARGET_32BIT && TARGET_POWERPC64 ) ) { machine_mode rmode = TARGET_32BIT ? SImode : DImode ; int i = <NUM_LIT> ; if ( align_words + n_words > GP_ARG_NUM_REG ) { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } do { rtx r = gen_rtx_REG ( rmode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * GET_MODE_SIZE ( rmode ) ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_words != <NUM_LIT> ) ; } else { rtx r = gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , const0_rtx ) ; } } else { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } return k


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) transform ( Regs , Regs . begin


<s> if ( I . getOperand ( <NUM_LIT> ) . getReg ( ) != EntryReg ) return false ; if ( I . getOperand ( <NUM_LIT> ) . getReg ( )


<s> if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal ==


<s> } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation =


<s> if ( Group . empty ( ) ) { FirstCC = CC ; FirstOppCC = <STR_LIT> ( CC ) ; MemOpCC = <STR_LIT> ; FoundNonCMOVInst = false ; SkipGroup = false ; } Group . push_back ( & I ) ; if ( FoundNonCMOVInst || ( CC != FirstCC && CC != FirstOppCC ) ) SkipGroup = true ; if ( I . mayLoad ( ) ) { if ( MemOpCC == <STR_LIT> ) MemOpCC = CC ; else if ( CC != MemOpCC ) SkipGroup = true ; } if ( ! SkipGroup && llvm :: any_of ( MRI -> use_nodbg_instructions ( I . defs ( ) . begin ( ) -> getReg ( ) ) , [ & ] ( MachineInstr & UseI ) { return UseI . getOpcode ( ) == <STR_LIT> ; } ) ) SkipGroup = true ; continue ; } if ( Group . empty ( ) ) continue ; FoundNonCMOVInst = true ; if ( I . definesRegister ( <STR_LIT> ) ) { if ( ! SkipGroup ) CmovInstGroups . push_back ( Group ) ; else ++


<s> unsigned Register = FPR128DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base , Disp , Index


<s> if ( V . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * MaskCst = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = MaskCst -> getZExtValue ( ) ; return ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ; } return false ; } ; if ( ! Op . hasOneUse ( ) ) return <NUM_LIT> ; if ( isSupportedExtend ( Op ) ) return <NUM_LIT> ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) if ( ConstantSDNode * ShiftCst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { uint64_t Shift = ShiftCst -> getZExtValue ( ) ; if ( isSupportedExtend ( Op . getOperand ( <NUM_LIT> ) ) ) return ( Shift <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT VT = Op


<s> MVT PtrVT = Op . getValueType ( ) ; ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; Constant * C = CP -> getConstVal ( ) ; SDValue CPI = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi


<s> return ( int64x1_t ) __builtin_neon_vrshlsdi (


<s> static void or1k_save_reg ( int regno , HOST_WIDE_INT offset ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode ,


<s> static __inline qword si_from_uchar ( unsigned char c ) { union { qword q ; unsigned char c [ <NUM_LIT>


<s> } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = alignTo ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( TargetMBB ) { unsigned ReturnReg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( TargetMBB ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addMBB ( TargetMBB ) ; } TargetMBB -> setHasAddressTaken ( ) ; } if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes


<s> const int shiftl = ( __N & <NUM_LIT> ) * <NUM_LIT> ; const __m64 shiftD = ( const __m64 ) __D << shiftl ; const __m64 mask = <NUM_LIT> << shiftl ; __m64 result = ( __A & ( ~ mask ) ) | ( shiftD


<s> break ; case G_SELECT : { LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Ty2 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_ICMP : { LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty2 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_FCMP : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty1 ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Ty1 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Ty2 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_MERGE_VALUES : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) != <NUM_LIT> ) return getInvalidInstructionMapping ( ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_UNMERGE_VALUES : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) !=


<s> continue ; } if ( insn_defines_reg ( regno1 , INVALID_REGNUM , prev ) ) return true ; else if ( insn_defines_reg ( regno2 , INVALID_REGNUM , prev ) ) return false ; prev = PREV_INSN ( prev ) ; } return


<s> if ( current_function_calls_eh_return ) { gcc_assert ( ! final_sequence ) ; if ( ! flag_delayed_branch ) fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_V9 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; if ( flag_delayed_branch ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; } else if ( final_sequence ) { rtx delay , pat ; delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; pat = PATTERN


<s> SDNode * Elt = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! <STR_LIT> ( Elt ) || cast < LoadSDNode > ( Elt ) -> isVolatile ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( N ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; DCI . AddToWorklist ( V . getNode (


<s> Reached . insert ( MI ) ; if ( MI -> isPHI ( ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { Register Reg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) { continue ; } MachineInstr * NewMI = MRI -> getVRegDef ( Reg ) ; if ( ! NewMI ) continue ; Front . push_back ( NewMI ) ; } } else if ( MI -> isFullCopy ( ) ) { if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; MachineInstr * NewMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> unsigned rv = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MissingFeatures , matchingInlineAsm , VariantID ) ; if ( Code16GCC ) SwitchMode ( <STR_LIT> ) ; return rv


<s> case AARCH64_LS64_BUILTIN_LD64B : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; create_output_operand ( & ops [ <NUM_LIT> ] , target , V8DImode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , op0 , DImode ) ; expand_insn ( CODE_FOR_ld64b , <NUM_LIT> , ops ) ; return ops [ <NUM_LIT> ] . value ; } case AARCH64_LS64_BUILTIN_ST64B : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; create_output_operand ( & ops [ <NUM_LIT> ] , op0 , DImode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64b , <NUM_LIT> , ops ) ; return const0_rtx ; } case AARCH64_LS64_BUILTIN_ST64BV : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; create_output_operand ( & ops [ <NUM_LIT> ] , target , DImode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , op0 , DImode ) ; create_input_operand ( & ops [ <NUM_LIT> ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64bv , <NUM_LIT> , ops ) ; return ops [ <NUM_LIT> ] . value ; } case AARCH64_LS64_BUILTIN_ST64BV0 : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp


<s> cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; cfun -> machine -> uses_anonymous_args = <NUM_LIT> ; local_cum = * pcum ; csky_function_arg_advance ( local_cum_v , mode , type , true ) ; regs_to_push = CSKY_NPARM_REGS - local_cum ; if ( regs_to_push ) * pretend_size


<s> assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; Register RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) . addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , getCRFromCRBit ( DestReg ) ) . addReg ( RegO , RegState :: Kill ) . addReg ( getCRFromCRBit ( DestReg ) , RegState :: Implicit ) ; MBB . erase ( II


<s> get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg (

) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , false , MustPreserveCheriCapabilities , DstPtrInfo ,


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> return MIB . addReg ( GlobalBaseReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addConstantPoolIndex ( CPI )


<s> if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; } else if ( Base . getValueType ( ) != VT ) { assert ( VT == <STR_LIT> && Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Base ) ; SDValue Trunc = CurDAG -> getNode ( <STR_LIT> , DL , VT , Base ) ; insertDAGNode ( CurDAG , Base . getNode ( ) , Trunc ) ; Base = Trunc


<s> if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address , Address + imm + <NUM_LIT> , Decoder ) ; return


<s> if ( ! Subtarget -> is64Bit ( ) ) Entry . isSRet = true ; Entry . isReturned = false ; Args . push_back ( Entry ) ; RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTyABI , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( RetTyABI == RetTy ) return CallInfo . first ; assert ( RetTy -> isFP128Ty ( ) && <STR_LIT> ) ; Chain = CallInfo . second ; return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , Chain , RetPtr , MachinePointerInfo ( )


<s> if ( UsesWinAAPCS ) return invalidateWindowsRegisterPairing ( Reg1 , Reg2 , NeedsWinCFI , IsFirst ) ; if ( NeedsFrameRecord ) return


<s> unsigned <ISA_LIT>InstrInfo :: getMachineOutlinerMBBFlags ( MachineBasicBlock & MBB ) const { unsigned Flags = <NUM_LIT> ; if ( std :: any_of ( MBB . begin ( ) , MBB . end ( ) , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ; LiveRegUnits LRU ( getRegisterInfo ( )


<s> unsigned btihintop = MI -> getOperand ( OpNum ) . getImm ( ) ^ <NUM_LIT> ; auto BTI = <STR_LIT> ( btihintop ) ; if ( BTI ) O <<


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; MachineBasicBlock :: reverse_iterator FirstBr ; unsigned


<s> unsigned Rt2 = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm ( cop ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( opc1 ) ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) )


<s> break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , UseOffset , IndexReg ) ; bool IsVSSRC = isVSSRCRegClass ( RC ) ; bool IsVSFRC = isVSFRCRegClass ( RC ) ; bool Is32VSXStore = IsVSSRC && Opc == <STR_LIT> ; bool Is64VSXStore = IsVSFRC && Opc == <STR_LIT> ; if ( ( Is32VSXStore || Is64VSXStore ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXStore || Is64VSXStore ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlign ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXStore || Is64VSXStore ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc =


<s> if ( ! I -> isCall ( ) ) return false ; unsigned structSizeOpNum = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : return false ; } const MachineOperand & MO = I -> getOperand ( structSizeOpNum ) ; if ( ! MO . isImm ( ) ) return false ; StructSize = MO . getImm ( ) ; return


<s> return ( uint8x8_t ) __builtin_aarch64_sqrshrun_nv8hi ( __a ,


<s> rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == <NUM_LIT> ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , <NUM_LIT> ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( <NUM_LIT> , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } return true


<s> bool shouldKeepZExtForFP16Conv ( ) const


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Cond . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; const APInt & TrueVal = TrueC -> getAPIntValue ( ) ; const APInt & FalseVal = FalseC -> getAPIntValue ( ) ; bool OV ; APInt Diff = TrueVal . ssub_ov ( FalseVal , OV ) ; if ( OV ) return SDValue ( ) ; APInt AbsDiff = Diff . abs ( ) ; if ( AbsDiff . isPowerOf2 ( ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ( AbsDiff == <NUM_LIT> || AbsDiff == <NUM_LIT> || AbsDiff == <NUM_LIT> ) ) ) { if ( TrueVal . slt (


<s> Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else


<s> TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { MCInst Inst ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { default : break ; case Match_Success : ProcessInstruction ( Inst , Operands ) ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } llvm_unreachable ( <STR_LIT> )


<s> uint8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: csky > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( ST -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Tile } ; Builder . CreateIntrinsic ( <STR_LIT> , None


<s> bool isMemOpcodeFromGroup ( unsigned Opcode ) const { if ( ! MemOpcodes


<s> return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , vec_nor ( ( vec_uchar16 ) ( b ) , (


<s> bool isBDAddr32Disp20 ( ) const { return isMemDisp20 ( BDMem , GR32Reg


<s> return ( __m128i ) __builtin_ia32_loaddquhi128_mask ( ( const short * ) __P , ( __v8hi ) _mm_setzero_si128 (


<s> ReplaceNode ( Node , getGlobalBaseReg ( ) ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( ( Subtarget -> systemSupportsUnalignedAccess ( ) || cast < MemSDNode > ( Node ) -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> <= cast < MemSDNode > ( Node

) -> getAlignment ( ) ) && <STR_LIT> ) ;


<s> const std :: string & <ISA_LIT>LA25Stub :: name ( ) const { return m_Name


<s> bool SelectAddrModeIndexedU6S128 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeIndexedBitWidth ( N , false , <NUM_LIT> , <NUM_LIT>


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NumElts = MRI . getType ( Dst ) . getNumElements ( ) ; if ( ! isUZPMask ( ShuffleMask , NumElts , WhichResult ) ) return false ; unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register V1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register V2 = MI . getOperand ( <NUM_LIT> ) . getReg


<s> EVT VT = Op . getValueType ( ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; EVT NodeTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , None ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl ,


<s> <ISA_LIT>MachineFunctionInfo * AFI = Entry -> getParent (

) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> MachineInstrBuilder emitInstStore ( unsigned Opc , unsigned SrcReg , unsigned MemReg , int64_t MemOffset ) { return emitInst ( Opc ) . addReg ( SrcReg ) .

addReg ( MemReg ) . addImm ( MemOffset ) ;


<s> return GET_CODE ( x ) == MOD && GET_MODE ( x ) ==


<s> static bool isUncondBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc


<s> bool <ISA_LIT>PreTileConfig :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; MachineInstr * MI = getTileConfigPoint ( ) ; if ( ! MI ) return


<s> DebugLoc DL ; using RegAndKill = std :: pair < unsigned , bool > ; SmallVector < RegAndKill , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { Register Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( const RegAndKill & LHS , const RegAndKill & RHS ) { return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; }


<s> bool loongarch_eh_uses ( unsigned int regno ATTRIBUTE_UNUSED ) { return


<s> return __builtin_mve_vcvtq_m_to_f_sv8hf ( __inactive ,


<s> const DataLayout * DL = TM . getDataLayout ( ) ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; break ; case MachineOperand :: MO_BlockAddress


<s> EVT VecVT = V -> getValueType ( <NUM_LIT> ) ; bool RightType = VecVT == <STR_LIT> || VecVT == <STR_LIT> || ( HasDirectMove && ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) ) ; if ( ! RightType ) return false ; bool IsSplat = true ; bool IsLoad = false ; SDValue Op0 = V -> getOperand ( <NUM_LIT> ) ; if ( V -> isConstant ( ) ) return false ; for ( int i = <NUM_LIT> , e = V -> getNumOperands ( ) ;


<s> Allocas [ AI ] . DbgVariableIntrinsics . push_back ( DVI ) ; } continue ; } auto * II = dyn_cast < IntrinsicInst > ( I ) ; if ( II && ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ) { AllocaInst * AI = findAllocaForValue ( II -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! AI ) { UnrecognizedLifetimes . push_back ( I ) ; continue ; } if ( II -> getIntrinsicID ( ) == <STR_LIT> ) Allocas [ AI ] . LifetimeStart . push_back ( II ) ; else Allocas [ AI ] . LifetimeEnd . push_back ( II ) ; } if ( isa < ReturnInst > ( I ) || isa < ResumeInst > ( I ) || isa < CleanupReturnInst > ( I ) ) RetVec . push_back ( I ) ; } } if ( Allocas . empty ( ) ) return false ; int NextTag = <NUM_LIT> ; int NumInterestingAllocas = <NUM_LIT> ; for ( auto & I : Allocas ) { AllocaInfo & Info = I . second ; assert ( Info . AI ) ; if ( ! isInterestingAlloca ( * Info . AI ) ) { Info . Tag = - <NUM_LIT> ; continue ; } alignAndPadAlloca ( Info ) ; NumInterestingAllocas ++ ; Info . Tag = NextTag ; NextTag = ( NextTag + <NUM_LIT> ) % <NUM_LIT> ; } if ( NumInterestingAllocas == <NUM_LIT> ) return true ; std :: unique_ptr < DominatorTree > DeleteDT ; DominatorTree * DT = nullptr ; if ( auto * P = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ) DT = & P -> getDomTree ( ) ; if ( DT == nullptr && ( NumInterestingAllocas > <NUM_LIT> || ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) ) { DeleteDT = std :: make_unique < DominatorTree > ( * F ) ; DT = DeleteDT . get ( ) ; } std :: unique_ptr < PostDominatorTree > DeletePDT ; PostDominatorTree * PDT = nullptr ; if ( auto * P = getAnalysisIfAvailable < PostDominatorTreeWrapperPass > ( ) ) PDT = & P -> getPostDomTree ( ) ; if ( PDT == nullptr && ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) { DeletePDT = std :: make_unique < PostDominatorTree > ( * F ) ; PDT = DeletePDT . get ( ) ; } SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = insertBaseTaggedPointer ( Allocas , DT ) ; for ( auto & I


<s> return CurDAG -> getTargetConstant ( Imm ,


<s> void <ISA_LIT>InstPrinter :: printAbsAddrOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << ( int ) MI -> getOperand ( OpNo )


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; return X


<s> isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , StByValParamsPadding ( <NUM_LIT> ) , ArgRegsSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) ,

VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT>


<s> else ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , SDLoc ( N ) ) ; if ( Opcode == <STR_LIT> && ( ShiftVal + <NUM_LIT> ) == NumBitsPerElt && N0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( LogicalShift && ( ShiftVal . getZExtValue ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back ( <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , NonceMask , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned ShiftImm = ShiftVal . getZExtValue ( ) ; for ( APInt & Elt : EltBits ) { if ( <STR_LIT> == Opcode ) Elt = Elt . shl ( ShiftImm ) ; else if ( <STR_LIT> == Opcode ) Elt


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode (


<s> CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ return HasSVE ? <STR_LIT> ## n : <STR_LIT> ## n CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> )


<s> bool isCC = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( isCC ? <NUM_LIT> : <NUM_LIT> ) ; bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 . cloneMemRefs ( MI ) ; HI16 . cloneMemRefs ( MI ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc =


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitFEXT_CCRX16_ins ( unsigned SltOpc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX


<s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction


<s> return false ; case MachineOperand :: MO_Register : if ( MO . getReg ( ) == <STR_LIT> ) return false ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS ) ; return false ; case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Sym -> print ( OS , MAI ) ; return


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( M1 ( <NUM_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SubTmp , getKillRegState ( true ) ) ; MIB . getInstr ( ) -> addRegisterKilled ( TmpReg , TRI , true ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { const unsigned SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned int NumSubRegs = <NUM_LIT> ; copyPhysSubRegs ( MBB , I , DL , DestReg , SrcReg , KillSrc , get ( <STR_LIT> ) , NumSubRegs , SubRegIdx , & getRegisterInfo ( ) ) ; } else { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; dbgs ( ) << <STR_LIT> << printReg ( SrcReg , TRI ) <<

<STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> ;


<s> gcc_assert ( VECTOR_MODE_P ( p . mode ) && VECTOR_MODE_P ( prev . mode ) ) ; unsigned int nelems1 , nelems2 ; if ( prev . orig_mode == p . orig_mode && known_eq ( prev . offset + GET_MODE_SIZE ( prev . mode ) , p . offset ) && constant_multiple_p ( GET_MODE_NUNITS ( prev . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems1 ) && constant_multiple_p ( GET_MODE_NUNITS ( p . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems2 ) && targetm

. array_mode ( p . orig_mode , nelems1 + nelems2 ) . exists ( & prev . mode ) ) {


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= RC -> getSize ( ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( )

>= Alignment ) || RI . canRealignStack ( MF ) ;


<s> case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue =


<s> static unsigned sizeSIBByte ( ) { return <NUM_LIT>


<s> if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Add1 = DAG . getNode ( <STR_LIT> , DL , ValTy , N ->

getOperand ( <NUM_LIT> ) , Add . getOperand ( <NUM_LIT> ) ) ;


<s> default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> static int vax_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as

ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {


<s> -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = <STR_LIT> ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( I -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( & * I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] .


<s> if ( ! TARGET_TLS ) return false ; if ( GET_CODE ( x ) != SYMBOL_REF ) return


<s> words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = <NUM_LIT> ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = <NUM_LIT> ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum


<s> } else SetCC = SetCC . getOperand ( <NUM_LIT> ) ; } switch ( SetCC . getOpcode ( ) ) { case <STR_LIT> : if ( checkAgainstTrue && ! truncatedToBoolWithAnd ) break ; assert ( <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) ; if ( needOppositeCond ) CC = <STR_LIT> ( CC ) ; return SetCC . getOperand ( <NUM_LIT> ) ; case <STR_LIT> : { ConstantSDNode * FVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * TVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; if ( ! TVal ) return SDValue ( ) ; if ( ! FVal ) { SDValue Op = SetCC . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || Op . getResNo ( ) != <NUM_LIT> ) return SDValue ( ) ; } bool FValIsFalse = true ; if ( FVal && FVal -> getZExtValue ( ) != <NUM_LIT> ) { if ( FVal -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; needOppositeCond = ! needOppositeCond ; FValIsFalse =


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream &


<s> void pa_asm_output_aligned_bss ( FILE * stream , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { switch_to_section ( bss_section ) ; fprintf ( stream , <STR_LIT> , align / BITS_PER_UNIT ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name ,


<s> if ( C . Chain ) return ; auto * C1 = dyn_cast < ConstantFPSDNode > ( C . Op1 ) ; if ( C1 && C1 -> isZero ( ) ) { for ( auto I = C . Op0 -> use_begin ( ) , E = C . Op0 -> use_end ( ) ; I != E ; ++ I ) { SDNode * N = *


<s> return ( int16x8_t ) __builtin_neon_vmaxsv8hi ( __a ,


<s> static bool isSimpleShift ( SDValue N , unsigned & ShiftVal ) { ConstantSDNode * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Shift ) return


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; if ( ! ADDIMI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; Imm = ADDIMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true


<s> switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return MCSymbolRefExpr :: VK_None ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ; case <STR_LIT> : return MCSymbolRefExpr


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> opNum = MI -> getNumOperands ( ) - <NUM_LIT> ; break ; } printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O ) ; O << <STR_LIT>


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; } else while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && parseParenSuffix ( Name , Operands ) ) return true ; } } if ( getLexer ( ) . isNot (


<s> return & InstrInfo . getRegisterInfo


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val <


<s> virtual void EmitInstruction ( const


<s> changeFPCCToAND<ISA_LIT>CC ( CC , OutCC , ExtraCC ) ; if ( ExtraCC != <STR_LIT> ) { MachineInstr * ExtraCmp ; if ( ! CCOp ) ExtraCmp = emitFPCompare ( LHS , RHS , MIB , CC ) ; else ExtraCmp = emitConditionalComparison ( LHS , RHS , CC , Predicate , ExtraCC , MIB ) ; CCOp = ExtraCmp -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Predicate = ExtraCC ; } } if ( ! CCOp ) { auto Dst = MRI . cloneVirtualRegister ( LHS ) ; if ( isa < GICmp > ( Cmp ) ) return emitSUBS ( Dst , Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> getOperand ( <NUM_LIT> ) , MIB ) ; return emitFPCompare ( Cmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , Cmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ; } return emitConditionalComparison ( LHS , RHS , CC , Predicate , OutCC , MIB ) ; } assert ( MRI . hasOneNonDBGUse ( Val ) && <STR_LIT> ) ; bool IsOR = Opcode == TargetOpcode :: G_OR ; Register LHS = ValDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool CanNegateL ; bool MustBeFirstL ; bool ValidL = canEmitConjunction ( LHS , CanNegateL , MustBeFirstL , IsOR , MRI ) ; assert ( ValidL && <STR_LIT> ) ; ( void ) ValidL ; Register RHS = ValDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool CanNegateR ; bool MustBeFirstR ; bool ValidR = canEmitConjunction ( RHS , CanNegateR , MustBeFirstR , IsOR , MRI ) ; assert ( ValidR && <STR_LIT> ) ; ( void ) ValidR ; if ( MustBeFirstL ) { assert ( ! MustBeFirstR && <STR_LIT> ) ; std :: swap ( LHS , RHS ) ; std :: swap ( CanNegateL , CanNegateR ) ; std :: swap ( MustBeFirstL , MustBeFirstR ) ; } bool NegateR ; bool NegateAfterR ; bool NegateL ; bool NegateAfterAll ; if ( Opcode == TargetOpcode :: G_OR ) { if ( ! CanNegateL ) { assert ( CanNegateR && <STR_LIT> ) ; assert ( ! MustBeFirstR && <STR_LIT> ) ; assert ( ! Negate ) ; std :: swap ( LHS , RHS ) ; NegateR = false ; NegateAfterR = true ; } else { NegateR = CanNegateR ; NegateAfterR = ! CanNegateR ; } NegateL =


<s> static bool spillsVRSAVE ( const MachineFunction & MF ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return FuncInfo -> isVRSAVESpilled


<s> if ( Reg == <STR_LIT> ) OS << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) ; else printRegName ( OS ,


<s> } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( Immr ) . addImm ( Imms ) ; } } StoreI -> clearRegisterKills ( StRt , TRI ) ; ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( BitExtMI ) -> print


<s> if ( combineCCMask ( CCReg , CCValidVal , CCMaskVal ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getTargetConstant ( CCMaskVal , SDLoc ( N ) , <STR_LIT> ) , CCReg ) ; return SDValue (


<s> ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o ,


<s> if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getSimpleValueType ( ) ; int NumElems = ( int ) ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , false , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt == SM_SentinelUndef ) return DAG . getUNDEF ( ShufVT . getVectorElementType ( ) ) ; assert ( <NUM_LIT> <= Elt && Elt < ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue NewV = ( Elt < NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { V = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = V . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT . getVectorNumElements ( ) != NumElems ) return SDValue ( ) ; } if ( V . getOpcode ( ) == <STR_LIT> ) return ( Index == <NUM_LIT> ) ? V . getOperand ( <NUM_LIT> ) : DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; if ( V . getOpcode ( ) == <STR_LIT> ) return V . getOperand (


<s> initSubtargetFeatures ( CPU , FS ) ; return *


<s> MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ; IsSelfLoop = false ; } else if ( DefCPSR ) { CPSRDef = MI ; IsSelfLoop =


<s> set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , <STR_LIT> ) ; if ( DITF_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , <STR_LIT> ) ; } if ( SUN_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , <STR_LIT> ) ; } } if ( TARGET_ARCH64 ) { set_optab_libfunc ( smul_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( sdiv_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( udiv_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( smod_optab , SImode , <NUM_LIT> ) ; set_optab_libfunc ( umod_optab , SImode


<s> return ( __m512i ) __builtin_ia32_paddsw512_mask ( ( __v32hi ) __A , ( __v32hi )


<s> OpBegins . push_back ( OpBegins . back


<s> df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) if ( DF_REF_REG_DEF_P ( def ) && ! DF_REF_IS_ARTIFICIAL ( def ) && ( regno1 == DF_REF_REGNO ( def ) || regno2 == DF_REF_REGNO ( def ) ) ) return true ; return false


<s> std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString ( )


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef SymbolName = Tok . getIdentifier ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( SymbolName ) ; if ( ! Sym ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseEOL ( )


<s> bool NeedStub = false ; MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , RelocCST , <NUM_LIT> , NeedStub ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( <NUM_LIT> ) ; else MCE . emitWordLE


<s> NegateOperand = true ; case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; case <STR_LIT> : NegateOperand = true ; case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; } LoadSDNode * LoadNode = nullptr ; SDValue InputChain ; if ( ! isFusableLoadOpStorePattern ( StoreNode , StoredVal , CurDAG , LoadNode , InputChain ) ) return false ; SDValue Operand = StoredVal . getOperand ( <NUM_LIT> ) ; auto * OperandC = dyn_cast < ConstantSDNode > ( Operand ) ; if ( ! OperandC ) return false ; auto OperandV = OperandC -> getAPIntValue ( ) ; if ( NegateOperand ) OperandV = - OperandV ; if ( OperandV . getMinSignedBits ( ) > <NUM_LIT> ) return false ; Operand = CurDAG -> getTargetConstant ( OperandV , DL , MemVT ) ; SDValue Base , Disp ; if ( ! selectBDAddr20Only ( StoreNode -> getBasePtr ( ) , Base , Disp ) ) return false ; SDValue Ops [ ] = { Base , Disp , Operand , InputChain } ; MachineSDNode * Result = CurDAG -> getMachineNode ( NewOpc , DL , <STR_LIT> , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = StoreNode -> getMemOperand ( ) ; MemOp [ <NUM_LIT> ] = LoadNode -> getMemOperand ( ) ; Result -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( SDValue ( StoreNode , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( StoredVal . getNode ( ) , <NUM_LIT> ) , SDValue (


<s> for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int MaskElt = SVOp -> getMaskElt ( i ) ; if ( MaskElt < <NUM_LIT> ) continue ; MaskElt %= LaneSize ; unsigned Shamt = i ; if ( NumElts == <NUM_LIT> )


<s> static rtx vax_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED


<s> static bool BBHasFallthrough ( MachineBasicBlock * MBB ) { MachineFunction :: iterator MBBI = MBB ; if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = std :: next ( MBBI ) ; for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if ( *


<s> return Opc == <STR_LIT> || isT1i32Store ( Opc ) || isT2i32Store (


) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> static __inline void si_stqr ( qword a , unsigned


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; return SDValue ( )


<s> static DecodeStatus DecodeQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpacedAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT>

<< getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) !=


<s> if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMicro<ISA_LIT> ( ) { Micro<ISA_LIT>Enabled = false


<s> addPass ( createUnpackMachineBundles ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > (


<s> AsmTransCBE = x86_asm_table ; AssemblerDialect = AsmWriterFlavor ; bool is64Bit = Triple . getArch ( ) == Triple :: x86_64 ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT>


<s> SmallVector < Bucket , <NUM_LIT> > Buckets ; for ( const auto & BB : L -> blocks ( ) ) for ( auto & J : * BB ) { Value * PtrValue = nullptr ; Type * PointerElementType = nullptr ; PtrValue = getPointerOperandAndType ( & J , & PointerElementType ) ; if ( ! PtrValue ) continue ; if ( PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ) continue ; if ( L -> isLoopInvariant ( PtrValue


<s> const TargetFrameLowering * getFrameLowering (


<s> rtx_insn * load_insn = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; load_insn = DF_REF_INSN ( def_link -> ref ) ; break ; } gcc_assert ( load_insn ) ; insn_info = DF_INSN_INFO_GET ( load_insn ) ; rtx_insn * tocrel_insn = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; tocrel_insn = DF_REF_INSN ( def_link -> ref ) ; break ; } gcc_assert ( tocrel_insn ) ; rtx base , offset ; rtx tocrel_expr = SET_SRC ( PATTERN ( tocrel_insn ) ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) gcc_unreachable ( ) ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; rtx const_vector = get_pool_constant (


<s> case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_GPRel_4 : if ( isN64 ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_CALL16 ; case <STR_LIT>


<s> EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( BCVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , VT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast <


<s> bool isFixed = MFI -> isFixedObjectIndex ( FI ) ; FrameReg = <STR_LIT> ; Offset += SPAdj ; bool hasMovingSP = ! hasReservedCallFrame ( MF ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return


<s> if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return false ; return true


<s> Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE1 ( ) || Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind


<s> addPass ( create<ISA_LIT>ModuleISelDagPass ( ) ) ; addPass ( create<ISA_LIT>16ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( )


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( )


<s> SDValue Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , BoolCarry , DAG . getConstant ( <NUM_LIT> , DL


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : { unsigned Size = getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) )