<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , ( Subtarget . isSVR4ABI ( ) && CallConv == CallingConv :: Cold

) ? RetCC_<ISA_LIT>_Cold : RetCC_<ISA_LIT> ) ;


<s> static JumpKind classifySecond ( const MachineInstr & MI ) { <STR_LIT> CC = <STR_LIT> ( MI ) ; if ( CC == <STR_LIT> ) return JumpKind :: Invalid ; switch ( CC ) { default : return JumpKind :: Invalid ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return JumpKind :: ELG ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB , unsigned


<s> void <ISA_LIT>ATTInstPrinter :: printSTiRegOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & OS ) { const MCOperand & Op = MI


<s> return ( uint8x8_t ) __builtin_neon_vdup_nv8qi ( ( __builtin_neon_qi )


<s> static void mips_set_current_function ( tree fndecl


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo


<s> ret = gen_reg_rtx ( Pmode ) ; emit_library_call_value ( gen_tls_get_addr ( ) , ret , LCT_CONST


<s> case <STR_LIT> : return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ) return false ; break ; } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = nullptr ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) return true ; OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ; } else if ( OpNum ==


<s> Value * <ISA_LIT>IREmitter :: visitBFI ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> static inline bool save_global_or_fp_reg_p ( unsigned int regno , int leaf_function


<s> void addImm1_64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> bool isMemNoOffsetT2 ( bool alignOK = false , unsigned Alignment = <NUM_LIT> ) const { if ( ! isMem (


<s> const unsigned * <ISA_LIT>BaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction *


<s> const AsmToken & Tok = getLexer ( ) . getTok ( ) ; assert ( Tok . is ( AsmToken :: Register ) && <STR_LIT> ) ; unsigned RegNo ; assert ( Tok . getString ( ) . startswith (


<s> log_msg ( <STR_LIT> ) ; log_rtx ( other_comp ) ; log_return ( false , <STR_LIT> ) ; } if ( comp_insn == NULL_RTX ) { comp = other_comp ; comp_insn = i -> setcc . insn ; } else if ( ! can_combine_comparisons ( comp , other_comp ) ) return false ; if ( ! can_remove_cstore ( * i , trace ) || ! can_remove_comparison ( * i , trace ) ) return false ; } if ( ! REG_P ( XEXP ( comp , <NUM_LIT> ) ) ) { log_msg ( <STR_LIT> ) ; log_rtx ( XEXP ( comp , <NUM_LIT> ) ) ; log_return ( false , <STR_LIT> ) ; } rtx comp_op0 = gen_reg_rtx ( GET_MODE ( XEXP ( comp , <NUM_LIT> ) ) ) ; rtx comp_op1 = REG_P ( XEXP ( comp , <NUM_LIT> ) ) ? gen_reg_rtx ( GET_MODE ( XEXP ( comp , <NUM_LIT> ) ) ) : XEXP ( comp , <NUM_LIT> ) ; if ( inv_cstore_count != <NUM_LIT> && cstore_count != <NUM_LIT> ) { if ( make_not_reg_insn ( comp_op0 , comp_op0 ) == NULL_RTX ) log_return ( false , <STR_LIT> ) ; for ( std :: list < bb_entry > :: const_iterator i = trace . bb_entries . begin ( ) ; i != trace . bb_entries . end ( ) ; ++ i ) { if ( i -> setcc . empty ( ) || i -> cstore . empty ( ) ) continue ; if ( i -> cstore_type != dominating_cstore && ! is_cmp_eq_zero ( i -> comparison_rtx ( ) ) ) { log_msg ( <STR_LIT> ) ; log_insn ( i -> setcc . insn ) ; log_return ( false , <STR_LIT> ) ; } } } if ( dominating_cstore == cstore_normal && ! try_invert_branch_condition ( trace ) ) return false ; log_msg ( <STR_LIT> , trace . bb ( ) -> index ) ; rtx common_comp_pat = copy_rtx ( PATTERN ( comp_insn ) ) ; rtx common_comp = const_cast < rtx > ( set_of ( m_ccreg , common_comp_pat ) ) ; gcc_assert ( common_comp != NULL_RTX ) ; XEXP ( XEXP ( common_comp , <NUM_LIT> ) , <NUM_LIT>


<s> const MCSection * FindAssociatedSection ( ) const override { return getSubExpr ( ) -> FindAssociatedSection (


<s> const TargetRegisterClass * MandarinRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( regOpc ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( immOpc ) , t2 ) ; MIB . addReg ( t1 ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; unsigned t3 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( Invert ) { MIB = BuildMI ( newMBB , dl , TII -> get ( notOpc ) , t3 ) . addReg ( t2 ) ; } else t3 = t2 ; MIB = BuildMI ( newMBB , dl , TII -> get ( TargetOpcode :: COPY ) , EAXreg ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( CXchgOpc ) ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MIB . addReg ( t3 ) ; assert ( bInstr -> hasOneMemOperand ( ) && <STR_LIT> ) ; ( * MIB ) . setMemRefs ( bInstr -> memoperands_begin ( ) , bInstr -> memoperands_end ( ) ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( TargetOpcode :: COPY ) , destOper


<s> bool hasFPU ( ) const { return HasFPU


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent ( ) ; return EndMBB


<s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned IssueWidth = TSM . getIssueWidth ( ) ; for ( unsigned i = <NUM_LIT> , e = IssueWidth * NOOPsToAdd ; i != e ; ++ i ) BuildMI ( * MBB , MBBI , DL , TSM . getInstrInfo ( ) -> get


<s> } if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; if ( ! isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ) return false ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) return true ; auto AddendExpr = dyn_cast < MCConstantExpr > ( BE


<s> if ( fcode >= RS6000_OVLD_MAX ) return error_mark_node ; return rs6000_builtin_decls [


<s> SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } if ( ! Subtarget -> isLittle ( ) ) std


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget


<s> if ( const ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( CP -> getConstVal ( ) , CP -> getValueType ( <NUM_LIT> ) , CP -> getAlignment ( ) , CP -> getOffset ( ) , TF ) ; if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ; llvm_unreachable ( <STR_LIT>


<s> if ( ! TARGET_32BIT ) return false ; * p1 = CC_REGNUM ; * p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; MI . eraseFromParent (


<s> } else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BalTgtMBB -> rbegin ( ) -> bundleWithPred ( ) ; } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . has<ISA_LIT>64r6 ( ) ) BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BalTgtMBB -> rbegin ( ) -> bundleWithPred (


<s> auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair (


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) { Mask . push_back


<s> SDValue SetCC = Ext . getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) != <STR_LIT> || ! SetCC . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC = ( <STR_LIT> ) SetCC . getConstantOperandVal ( <NUM_LIT> ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = SetCC . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue CmpOp0 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue NewCmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CmpOp0 , DAG . getConstant ( <NUM_LIT> , CmpOp0 . getValueType ( ) ) ) ; SDValue OtherVal = N -> getOperand ( N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant (

- <NUM_LIT> , OtherVal . getValueType ( ) ) , NewCmp ) ;


<s> bool ia64_extra_constraint ( rtx value , char c ) { switch ( c ) { case 'Q' : return memory_operand ( value , VOIDmode ) && ! MEM_VOLATILE_P ( value ) ; case 'R' : return ( GET_CODE ( value ) == CONST_INT && INTVAL ( value ) >= <NUM_LIT> && INTVAL ( value ) <= <NUM_LIT> ) ; case 'S' : return ( GET_CODE ( value ) == MEM && GET_RTX_CLASS ( GET_CODE ( XEXP ( value , <NUM_LIT> ) ) ) != RTX_AUTOINC && ( reload_in_progress || memory_operand ( value , VOIDmode ) ) ) ; case 'T' : return small_addr_symbolic_operand ( value , VOIDmode ) ; case 'U' : return value == CONST0_RTX ( GET_MODE ( value ) ) ; case 'W' : if ( GET_CODE ( value ) == CONST_VECTOR && GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_VECTOR_INT ) { value = simplify_subreg ( DImode , value , GET_MODE ( value ) , <NUM_LIT> ) ; return ia64_const_ok_for_letter_p ( INTVAL ( value )


<s> void mmix_asm_output_internal_label ( FILE * stream , const


<s> bool <ISA_LIT>TargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , N . getValueType ( ) ) ; Index =


<s> BUILTIN_VDQF ( UNOP , abs , <NUM_LIT> , ALL ) return fold_build1 ( ABS_EXPR , type , args [ <NUM_LIT> ] ) ; VAR1 ( UNOP , floatv2si , <NUM_LIT> , ALL , v2sf ) VAR1 ( UNOP , floatv4si , <NUM_LIT> , ALL , v4sf ) VAR1 ( UNOP , floatv2di , <NUM_LIT> , ALL , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ <NUM_LIT> ] ) ; case AARCH64_SIMD_BUILTIN_LANE_CHECK : gcc_assert ( n_args == <NUM_LIT> ) ; if ( aarch64_fold_builtin_lane_check ( args [ <NUM_LIT> ] , args [ <NUM_LIT> ] , args [ <NUM_LIT>


<s> static const char * getRegisterName ( unsigned RegNo ) { return <ISA_LIT>InstPrinter :: getRegisterName (


<s> MVT InSVT = InVT . getScalarType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known ; DAG . computeKnownBits ( In , Known ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedSignBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT


<s> auto Token = Parser . getTok ( ) ; SMLoc S = Token . getLoc ( ) ; if ( Token . isNot ( AsmToken :: Dollar ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar ( Operands , S ) ; if ( ResTy


<s> CPU = select<ISA_LIT>CPU ( TT , CPU ) ; MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; if ( State . isVarArg ( ) ) { unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; for ( unsigned j = <NUM_LIT> ; j < ArgsParts [ i ] ; j ++ ) { if ( i == <NUM_LIT> && j == <NUM_LIT> ) State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( <NUM_LIT> ,


<s> static SDValue createStoreLR ( unsigned Opc , SelectionDAG & DAG , StoreSDNode * SD , SDValue Chain , unsigned Offset ) { SDValue Ptr = SD -> getBasePtr ( ) , Value = SD -> getValue ( ) ; EVT MemVT = SD -> getMemoryVT ( ) , BasePtrVT = Ptr . getValueType ( ) ; SDLoc DL ( SD ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> ) ; if ( Offset ) Ptr = DAG . getNode ( <STR_LIT> , DL , BasePtrVT , Ptr , DAG . getConstant ( Offset , DL , BasePtrVT ) ) ; SDValue Ops [ ] = { Chain ,


<s> if ( CIdx && ( CIdx -> getZExtValue ( ) <= <NUM_LIT> ) ) { SDValue CI = DAG . getTargetConstant ( CIdx -> getZExtValue ( ) , DL , <STR_LIT> ) ; SDNode * DUPQ = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , V , CI ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( DUPQ , <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SplatOne = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SDValue SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SV , SplatOne ) ; SDValue Idx64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Idx128 , Idx128 ) ; SDValue SplatIdx64 = DAG . getNode ( <STR_LIT> , DL


<s> } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } } return DecodeVMOVModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) )


<s> return & InstrInfo . getRegisterInfo (


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Size -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned <ISA_LIT>Reg = <STR_LIT> ; SDValue <ISA_LIT> = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>Reg , VT ) ; SDValue New<ISA_LIT> = DAG . getNode ( <STR_LIT> , dl , VT , <ISA_LIT> , Size ) ; Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; unsigned regSpillArea = Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; regSpillArea += Subtarget -> getStackPointerBias ( ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , VT , New<ISA_LIT> , DAG . getConstant ( regSpillArea , VT ) ) ; SDValue Ops [ <NUM_LIT> ] = { NewVal , Chain } ; return DAG . getMergeValues ( Ops


<s> const uint32_t * Mask ; const auto * TRI = Subtarget . getRegisterInfo ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( AssignFnFixed , AssignFnVarArg , Subtarget , false ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , false ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , OutArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; Mask = getMaskForArgs ( OutArgs , Info , * TRI , MF ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) constrainOperandRegClass ( MF , * TRI , MRI , * Subtarget . getInstrInfo ( ) , * Subtarget . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ) ; bool UsingReturnedArg = ! OutArgs . empty ( ) && OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . isReturned ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( RetAssignFn , RetAssignFn , Subtarget , false ) ; ReturnedArgCallReturnHandler ReturnedArgHandler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( UsingReturnedArg ? ReturnedArgHandler : Handler , Assigner , InArgs , MIRBuilder , Info . CallConv , Info . IsVarArg , UsingReturnedArg ? makeArrayRef ( OutArgs [ <NUM_LIT> ] . Regs ) : None ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } uint64_t CalleePopBytes = doesCalleeRestoreStack ( Info . CallConv , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ? alignTo ( Assigner . StackOffset , <NUM_LIT> ) : <NUM_LIT> ; CallSeqStart . addImm ( Assigner . StackOffset ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Assigner . StackOffset


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( fixed_regs [ regno ] ) { save_regs [ regno ] = <NUM_LIT> ; continue ; } if ( crx_interrupt_function_p ( ) ) { if ( ! current_function_is_leaf && call_used_regs [ regno ] ) save_regs [ regno ] = <NUM_LIT> ; else if ( regs_ever_live [ regno ] ) save_regs [ regno ] = <NUM_LIT> ; else save_regs [ regno ] = <NUM_LIT> ; } else { if ( regs_ever_live [ regno ] && ( ! call_used_regs [ regno ] || regno == RETURN_ADDRESS_REGNUM ) ) save_regs [ regno ] = <NUM_LIT> ; else save_regs [ regno ] = <NUM_LIT> ; } } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( save_regs [ regno ] == <NUM_LIT> ) { last_reg_to_save = regno ; sum_regs +=


<s> for ( MachineInstr & MI : MBB ) if ( MI . getOpcode ( ) == <STR_LIT> ) CFGs . push_back ( & MI ) ; for ( auto * MI : CFGs ) materializeTileCfg ( MI ) ; if ( ! CFGs . empty ( ) ) Changed = true ; } if ( Changed ) <ISA_LIT>FI ->


<s> DEBUG ( dbgs ( ) << <STR_LIT> << SU ->


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . BaseRegNum != <STR_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , <NUM_LIT> , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; addPass ( createMVETailPredicationPass (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = std :: next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; else BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - UPad - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand


<s> if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; } case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : if ( ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS :


<s> case <NUM_LIT> : return UNSPEC_REVH ; case <NUM_LIT> : return UNSPEC_REVW ; } gcc_unreachable (


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return


<s> return MCInstBuilder ( Opcode ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> )

. getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> void addThumbModImmNeg1_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Val = - CE -> getValue (


<s> if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && ! Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , A ) , DAG . getBitcast ( <STR_LIT> , B ) ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Aodds ) , DAG . getBitcast ( <STR_LIT> , Bodds ) ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; KnownBits AKnown , BKnown ; DAG . computeKnownBits ( A , AKnown ) ; DAG . computeKnownBits ( B , BKnown ) ; APInt LowerBitsMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool ALoIsZero = LowerBitsMask . isSubsetOf ( AKnown . Zero ) ; bool BLoIsZero = LowerBitsMask . isSubsetOf ( BKnown . Zero ) ; APInt UpperBitsMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool AHiIsZero = UpperBitsMask . isSubsetOf ( AKnown . Zero ) ; bool BHiIsZero = UpperBitsMask . isSubsetOf ( BKnown . Zero ) ; SDValue Zero = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue AloBlo = Zero ; if ( ! ALoIsZero && ! BLoIsZero ) AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = Zero ; if ( ! ALoIsZero && ! BHiIsZero ) { SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; } SDValue AhiBlo = Zero ; if ( ! AHiIsZero && ! BLoIsZero ) { SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> unsigned Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugInstr ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded


<s> rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) { * symbol_type = loongarch_classify_symbol ( x ) ; if ( * symbol_type == SYMBOL_TLS ) return true ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_TLS_IE : case SYMBOL_TLS_LE : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_PCREL : case SYMBOL_PCREL64 : return sext_hwi ( INTVAL ( offset ) , <NUM_LIT> ) == INTVAL ( offset ) ; case SYMBOL_GOT_DISP : case SYMBOL_TLS


<s> assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; MI . print ( DOUT ( llvm :: dbgs ( ) ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> << spOffset << <STR_LIT> ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> << stackSize << <STR_LIT> ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) . getImm ( ) ; DOUT ( llvm :: dbgs ( ) << <STR_LIT>


<s> EVT PtrVT = getPointerTy ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> )

, DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , unsigned nelt , rtx perm [ ] ) { machine_mode imode ; rtx x ; imode = vmode ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> ,


<s> return setInfoSVEStN < <NUM_LIT> > ( * this , DL , Info , I ) ; case <STR_LIT> : return setInfoSVEStN < <NUM_LIT> > ( * this , DL , Info , I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc =


<s> } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant (


<s> unsigned getDPRCalleeSavedGapSize ( ) const { return


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . get


<s> emitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue IID = N -> getOperand ( <NUM_LIT> ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; SDValue Vec = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Lane = Op1 . getOperand ( <NUM_LIT> ) ; EVT ResTy = N -> getValueType ( <NUM_LIT> ) ; EVT VecResTy


<s> unsigned FRINTXOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; if ( VT == <STR_LIT> ) { Variant = <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { Variant = <NUM_LIT> ; } else return nullptr ; unsigned FRINTXOpc = FRINTXOpcs [ Variant ] ; switch ( N -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : { unsigned FRINTPOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTPOpcs [ Variant ] ; break ; } case <STR_LIT> : { unsigned FRINTMOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTMOpcs [ Variant ] ; break ; } case <STR_LIT> : { unsigned FRINTZOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTZOpcs [ Variant ] ; break ; } case <STR_LIT> : { unsigned FRINTAOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTAOpcs


<s> assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Lo , Hi ; SDValue ArgValueLo , ArgValueHi ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( nullptr == InFlag ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValueLo = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValueHi = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; } else { ArgValueLo = DAG . getCopyFromReg ( Root , Dl , VA . getLocReg ( ) ,


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind )


<s> if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } if ( ! ! ( Flags & MachineMemOperand :: MONonTemporal ) && VT . isVector ( ) ) { if ( ! ! ( Flags & MachineMemOperand :: MOLoad ) ) return ( Alignment < <NUM_LIT> ||


<s> unsigned ExtReg = MRI . createGenericVirtualRegister ( LocTy ) ; MIRBuilder . buildSExt ( ExtReg , ValReg ) ; return ExtReg ; } case CCValAssign :: ZExt : { unsigned ExtReg = MRI . createGenericVirtualRegister ( LocTy ) ; MIRBuilder . buildZExt ( ExtReg , ValReg ) ; return ExtReg ; } case CCValAssign ::


<s> inline vector unsigned int vec_vmulouh ( vector unsigned


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSVEVectorWithOffset ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; const SMLoc S = getLoc ( ) ; StringRef Kind ; int RegNum = tryMatchSVEVectorRegister ( Parser . getTok ( ) , Kind , false ) ; if ( RegNum == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( Kind . empty ( ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: SVEVector , S , getLoc ( ) , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { return MatchOperand_Success ; } Parser . Lex ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) { return MatchOperand_NoMatch ; } StringRef value = TokE . getString ( ) ; const char * extTypeName =


<s> extern __inline float __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsbh_ss ( __bfloat16 __A ) { union { float a ; unsigned int b ; } __tmp ; __tmp . b = ( ( unsigned int ) ( __A ) ) << <NUM_LIT> ; return __tmp .


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , getContext ( ) ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_DTPREL , Expr , getContext (


<s> const StringRef & ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsl ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex ( ) ; if ( St == Rrx ) return false ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error


<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveKnownElts = true ) { EVT VT = Op . getValueType ( )


<s> if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 . cloneMemRefs ( MI ) ; HI16 . cloneMemRefs ( MI ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF


<s> unsigned <ISA_LIT>FrameLowering :: getEmergencySpillSlotSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = MFFrame -> getStackSize ( ) + <STR_LIT> * <NUM_LIT> ; return isUInt < <NUM_LIT> > ( MaxReach ) ?


<s> const <ISA_LIT>InstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) return true ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ <NUM_LIT> ) return true ; for ( unsigned i = <NUM_LIT> ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ; const TargetRegisterClass * RC = getMinimalPhysRegClass ( Reg ) ; unsigned Opcode = InstrInfo -> getStoreOpcodeForSpill ( RC ) ; if ( ! MFI . isFixedObjectIndex ( FrIdx ) ) { if ( offsetMinAlignForOpcode ( Opcode ) > <NUM_LIT> ) return true ; } if ( InstrInfo -> isXFormMemOp ( Opcode


<s> if ( isAsynchronousEHPersonality ( Personality ) ) return


<s> enum insn_path path ; enum dispatch_group insn_group ; bool insn_fits ; int num_insn ; int num_uops ; int window_num ; int insn_num_uops ; int sum ; if ( INSN_CODE ( insn ) < <NUM_LIT> ) return ; byte_len = min_insn_size ( insn ) ; window_list = dispatch_window_list ; next_list = window_list -> next ; path = get_insn_path ( insn ) ; insn_group = get_insn_group ( insn ) ; if ( next_list ) window_list = dispatch_window_list -> next ; if ( path == path_single ) insn_num_uops = <NUM_LIT> ; else if ( path == path_double ) insn_num_uops = <NUM_LIT> ; else insn_num_uops = ( int ) path ; num_insn = window_list -> num_insn ; num_uops = window_list -> num_uops ; window_num = window_list -> window_num ; insn_fits = fits_dispatch_window ( insn ) ; if ( num_insn >= MAX_INSN || num_uops + insn_num_uops > MAX_INSN || ! ( insn_fits ) ) { window_num = ~ window_num & <NUM_LIT> ; window_list = allocate_next_window ( window_num ) ; } if ( window_num == <NUM_LIT> ) { add_insn_window ( insn , window_list , insn_num_uops ) ; if ( window_list -> num_insn >= MAX_INSN && insn_group == disp_branch ) { process_end_window ( ) ; return ; } } else if ( window_num == <NUM_LIT> ) { window0_list = window_list -> prev ; sum = window0_list -> window_size + window_list -> window_size ; if ( sum == <NUM_LIT> || ( byte_len + sum ) >= <NUM_LIT> ) { process_end_window ( ) ; window_list = dispatch_window_list ; } add_insn_window ( insn , window_list , insn_num_uops ) ; } else gcc_unreachable ( ) ; if ( is_end_basic_block ( insn_group )


<s> OutStreamer . emitLabel ( StubLabel ) ; OutStreamer . emitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer

. emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> unsigned CPELogAlign = getCPELogAlign ( U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = Water ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockAlignment = NextBlock -> getAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPEEnd = CPEOffset + Size ; if ( CPEEnd > NextBlockOffset ) { Growth = CPEEnd - NextBlockOffset ; Growth += OffsetToAlignment ( CPEEnd , <NUM_LIT> << NextBlockAlignment ) ; if ( CPEOffset < UserOffset ) UserOffset += Growth + UnknownPadding

( MF -> getAlignment ( ) , CPELogAlign ) ;


<s> if ( MBBI == MBB -> getParent ( ) -> begin ( ) ) return nullptr ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * PrevBB = std :: prev ( MBBI ) ; for ( MachineBasicBlock * S : MBB -> predecessors ( ) ) if ( S == PrevBB && ! TII -> AnalyzeBranch ( * PrevBB , TBB

, FBB , Cond ) && ! TBB && ! FBB ) return S ;


<s> switch ( Inst . getOpcode ( ) ) { default : return true ; case <STR_LIT> : <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & >


<s> if ( LHS ) Mov = DAG . getNode ( NewOp , dl , MovTy , * LHS , DAG . getConstant ( Value , dl , <STR_LIT> ) , DAG . getConstant ( Shift , dl , <STR_LIT> ) ) ; else Mov = DAG . getNode ( NewOp , dl , MovTy , DAG . getConstant ( Value , dl , <STR_LIT> ) , DAG . getConstant ( Shift , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov


<s> bool <ISA_LIT>TargetLowering :: findOptimalMemOpLowering ( std :: vector < EVT > & MemOps , unsigned Limit , const MemOp & Op , unsigned DstAS , unsigned SrcAS , const AttributeList & FuncAttributes ) const { const int MVCFastLen = <NUM_LIT> ; if ( Op . isMemcpy ( ) && Op . allowOverlap ( ) && Op . size ( ) <= MVCFastLen ) return false ; if ( Op . isMemset ( ) && Op . size (

) - <NUM_LIT> <= MVCFastLen ) return false ;


<s> inline int getMemoryOperandNo ( uint64_t TSFlags , unsigned Opcode ) { switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : return - <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasEVEX = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasEVEX_K = HasEVEX && ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++


<s> StringRef getPassName ( ) const override { return


<s> unsigned getGlobalBaseReg ( ) const { return


<s> long int <ISA_LIT>ELFWriterInfo :: computeRelocation ( unsigned SymOffset , unsigned RelOffset , unsigned RelTy ) const { if ( RelTy == ELF :: R_<ISA_LIT>_64_PC32 || RelTy == ELF :: R_386_PC32 ) return SymOffset - ( RelOffset + <NUM_LIT> ) ; else assert ( <NUM_LIT>


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value ,

const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const {


<s> BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> return ( __m512i ) __builtin_ia32_pmovsxwd512_mask ( ( __v16hi ) __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16


<s> virtual void EmitCFIEndProcImpl ( MCDwarfFrameInfo & Frame ) { Frame . End = (


<s> assert ( MI . getOperand ( OpNo - <NUM_LIT> ) . isImm ( ) ) ; assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Position = getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) , Fixups , STI ) ; unsigned Size = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ,


<s> if ( Mnemonic -> getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { Error ( Parser . getTok ( ) . getLoc (


<s> void setPic ( bool Value ) override { Pic =


<s> enum rs6000_builtins fn = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; switch ( fn ) { case RS6000_BUILTIN_RSQRTF : if ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( V4SFmode ) && out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ ALTIVEC_BUILTIN_VRSQRTFP ] ; break ; case RS6000_BUILTIN_RSQRT : if ( VECTOR_UNIT_VSX_P ( V2DFmode ) && out_mode == DFmode && out_n == <NUM_LIT>

&& in_mode == DFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ;


<s> cvtLdWriteBackRegAddrMode3 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addAddrMode3Operands ( Inst , <NUM_LIT> ) ;


<s> SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = MI -> getOperand ( <NUM_LIT> ) . getImm


<s> const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s32 , v8s64 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v16s32


<s> void <ISA_LIT>CodeEmitter :: emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) { MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES


<s> return __builtin_aarch64_uqsubdi_uuu ( __a ,


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( )


<s> const unsigned AluCode = AluOp . getImm ( ) ; printMemoryImmediateOffset < <NUM_LIT> > ( MAI , OffsetOp , OS ) ; printMemoryBaseRegister ( OS , AluCode


<s> int regno ; HOST_WIDE_INT tsize ; int last_arg_is_vararg_marker = <NUM_LIT> ; tree fndecl = current_function_decl ; tree fntype = TREE_TYPE ( fndecl ) ; tree fnargs = DECL_ARGUMENTS ( fndecl ) ; rtx next_arg_reg ; int i ; tree next_arg ; tree cur_arg ; CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; int store_args_on_stack = ( iq2000_can_use_return_insn ( ) ) ; if ( aggregate_value_p ( DECL_RESULT ( fndecl ) , fndecl ) && ! cfun -> returns_pcc_struct && targetm . calls . struct_value_rtx ( TREE_TYPE ( fndecl ) , <NUM_LIT> ) == <NUM_LIT> ) { tree type = build_pointer_type ( fntype ) ; tree function_result_decl = build_decl ( BUILTINS_LOCATION , PARM_DECL , NULL_TREE , type ) ; DECL_ARG_TYPE ( function_result_decl ) = type ; DECL_CHAIN ( function_result_decl ) = fnargs ; fnargs = function_result_decl ; } INIT_CUMULATIVE_ARGS ( args_so_far_v , fntype , NULL_RTX , <NUM_LIT> , <NUM_LIT> ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; regno = GP_ARG_FIRST ; for ( cur_arg = fnargs ; cur_arg != <NUM_LIT> ; cur_arg = next_arg ) { tree passed_type = DECL_ARG_TYPE ( cur_arg ) ; machine_mode passed_mode = TYPE_MODE ( passed_type ) ; rtx entry_parm ; if ( TREE_ADDRESSABLE ( passed_type ) ) { passed_type = build_pointer_type ( passed_type ) ; passed_mode = Pmode ; } entry_parm = iq2000_function_arg ( args_so_far , passed_mode , passed_type , true ) ; iq2000_function_arg_advance ( args_so_far , passed_mode , passed_type , true ) ; next_arg = DECL_CHAIN ( cur_arg ) ; if ( entry_parm && store_args_on_stack ) { if ( next_arg == <NUM_LIT> && DECL_NAME ( cur_arg ) && ( ( <NUM_LIT> == strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) ) || ( <NUM_LIT> == strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) ) ) ) { last_arg_is_vararg_marker = <NUM_LIT> ; break ; } else { int words ; gcc_assert ( GET_CODE ( entry_parm ) == REG ) ; if ( GET_MODE ( entry_parm ) == BLKmode ) words = ( int_size_in_bytes ( passed_type ) + <NUM_LIT> ) / <NUM_LIT> ; else words = ( GET_MODE_SIZE ( GET_MODE ( entry_parm ) ) + <NUM_LIT> ) / <NUM_LIT> ; regno = REGNO ( entry_parm ) + words - <NUM_LIT> ; } } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = iq2000_function_arg ( args_so_far , VOIDmode , void_type_node , true ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; emit_insn ( pattern )


<s> bool loongarch_epilogue_uses ( unsigned


<s> return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA , E , false , Ctx ) ; case MCSymbolRefExpr


<s> bool hasV6KOps ( ) const { return HasV6KOps


<s> MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true ) ) ; MBB . erase ( PrevMBBI ) ; return true ; } else if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true ) ) ; MBB . erase ( PrevMBBI ) ; return true ; } } if ( MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = next ( MBBI ) ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } } } else { if ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) return false ; <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned Offset = <STR_LIT> ( MI -> getOperand (


<s> Value * <ISA_LIT>IREmitter :: visitSHUFP ( const SDNode *


<s> getRegisterByName ( const char * RegName , EVT VT , const MachineFunction & MF ) const { Register Reg = MatchRegisterName ( RegName ) ; if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) { const MCRegisterInfo * MRI = Subtarget -> getRegisterInfo ( ) ; unsigned DwarfRegNum = MRI -> getDwarfRegNum


<s> if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; unsigned ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; } else { ZeroReg = UseInfo -> RegClass == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI -> getOperand ( UseIdx ) . setReg (


<s> for ( unsigned int i = <NUM_LIT> ; i < <ISA_LIT>GOT0Num ; ++ i ) new <ISA_LIT>GOTEntry ( <NUM_LIT>


<s> static rtx strip_offset_and_salt ( rtx addr ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { if ( isNonFoldablePartialRegisterLoad ( LoadMI , MI , MF


<s> void emitLocalEntry ( MCSymbolELF * S , const MCExpr * LocalOffset ) override { llvm_unreachable ( <STR_LIT>


<s> virtual const TargetData * getTargetData


<s> <STR_LIT> ET = getShiftExtendType ( ) ; bool IsSigned = ET == <STR_LIT> || ET == <STR_LIT> ; Inst . addOperand ( MCOperand :: createImm ( IsSigned ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> static inline unsigned getImm4 ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> const char * getPassName ( ) const override


<s> const MachineOperand & MO = MI . getOperand ( Op ) ; const MachineOperand & MO1 = MI . getOperand ( Op + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { emitConstPoolAddress ( MO . getIndex ( ) ,


<s> return ( __m256d ) __builtin_ia32_fixupimmpd256_maskz ( ( __v4df ) __A , ( __v4df )


<s> static void InsertLDR_STR ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int OffImm , bool isDef , DebugLoc dl , unsigned NewOpc , unsigned Reg , bool RegDeadKill , bool RegUndef , unsigned BaseReg , bool BaseKill , bool BaseUndef , unsigned OffReg , bool OffKill , bool OffUndef , <STR_LIT> Pred , unsigned PredReg , const TargetInstrInfo * TII , bool isT2 ) { int Offset = OffImm ; if ( ! isT2 ) { if ( OffImm < <NUM_LIT> ) Offset = <STR_LIT> ( <STR_LIT> , -


<s> if ( MI . isCall ( ) ) RegDefs . set ( <STR_LIT> ) ; if ( MI . isBranch ( ) ) { checkRegDefsUses ( RegDefs , RegUses , MI , MI . getDesc ( ) . getNumOperands ( ) , MI . getNumOperands ( ) ) ; RegDefs . reset (


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { OS << <STR_LIT> <STR_LIT> <STR_LIT> ; OS << <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ; OS << <STR_LIT> ; for ( std :: vector < char > :: iterator


<s> mem2 = operands [ <NUM_LIT> ] ; } else { reg1 = operands [ <NUM_LIT> ] ; reg2 = operands [ <NUM_LIT> ] ; mem1 = operands [ <NUM_LIT> ] ; mem2 = operands [ <NUM_LIT> ] ; } if ( REGNO ( reg2 ) == REGNO ( reg1 ) + <NUM_LIT> ) { umips_output_load_store_pair_1 ( load_p , reg1 , mem1 ) ; return ; } gcc_assert ( REGNO ( reg1 ) == REGNO ( reg2 ) + <NUM_LIT> ) ; umips_output_load_store_pair_1 ( load_p , reg2 , mem2


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_IMPLICIT_DEF : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT>


<s> return ( uint16x8_t ) ( vabsq_f16 ( __a ) <= vabsq_f16 ( __b ) ) ; return ( uint16x8_t ) __builtin_neon_vcalev8hf ( __a


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; return <STR_LIT> ( MCE -> getValue


<s> assert ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) && <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT>


<s> Count += Space ; } else { while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; PrevReg = Reg ; ++ Count ; } } if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( Count > <NUM_LIT> ) return Error ( S , <STR_LIT> ) ; unsigned NumElements = <NUM_LIT> ; char ElementKind = <NUM_LIT> ; if ( ! Kind . empty ( ) ) parseValidVectorKind ( Kind , NumElements , ElementKind ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , NumElements , ElementKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken ::


<s> if ( SetCC . getOpcode ( ) == <STR_LIT> && SetCC . getOperand ( <NUM_LIT> ) == DAG . getCondCode ( <STR_LIT> ) ) { SDValue CmpLHS = SetCC . getOperand ( <NUM_LIT> ) ; EVT VT = CmpLHS . getValueType ( ) ; SDNode * CmpRHS = SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * SplatLHS = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * SplatRHS = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; APInt SplatLHSVal ; if ( CmpLHS . getValueType ( ) == N -> getOperand ( <NUM_LIT> ) . getValueType ( ) && VT . isSimple ( ) && is_contained ( makeArrayRef ( { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , VT . getSimpleVT ( ) . SimpleTy ) && <STR_LIT> ( SplatLHS , SplatLHSVal ) && SplatLHSVal . isOneValue ( ) && <STR_LIT> ( CmpRHS ) && <STR_LIT> ( SplatRHS ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumElts , DAG . getConstant ( VT . getScalarSizeInBits ( ) - <NUM_LIT> , SDLoc ( N ) , VT . getScalarType ( ) ) ) ; SDValue Val = DAG . getBuildVector ( VT , SDLoc ( N ) , Ops ) ; auto Shift = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , CmpLHS , Val ) ; auto Or = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shift , N -> getOperand ( <NUM_LIT> ) ) ; return Or ; } } if ( N0 . getOpcode ( ) != <STR_LIT> || CCVT . getVectorElementCount ( ) != ElementCount :: getFixed ( <NUM_LIT> ) || CCVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ResVT . getSizeInBits ( ) != CmpVT . getSizeInBits ( ) ) return SDValue ( ) ; SDValue IfTrue = N -> getOperand ( <NUM_LIT> ) ; SDValue IfFalse = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( SDLoc ( N ) , CmpVT . changeVectorElementTypeToInteger ( ) , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , cast < CondCodeSDNode >

( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ) ;


<s> void clearFeatureBits ( unsigned Feature , StringRef FeatureString ) { if ( STI . getFeatureBits ( ) & Feature ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString )


<s> SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Concat0Op1 . getOpcode ( ) != <STR_LIT> || Concat1Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts


<s> SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( Cond , DAG , <ISA_LIT>cc ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , SelectTrue , SelectFalse , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True


<s> void <ISA_LIT>AsmPrinter :: printMachineInstruction ( const MachineInstr * MI ) { ++


<s> int pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT

&& ! SMALL_INT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) return <NUM_LIT> ;


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; Destination = & MI . getOperand ( <NUM_LIT> ) ; Source = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder )


<s> case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB


<s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return

TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> unsigned Size = TRI -> getSpillSize ( <STR_LIT> ) ; Align Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( <STR_LIT> ) ; Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = <STR_LIT> ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) . addImm ( <NUM_LIT> ) ; unsigned Opc = <STR_LIT> ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) ) , TileSS ) . addReg ( SrcReg , getKillRegState ( SrcMO . isKill ( ) ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( GR64Cand ) ; MO . setIsKill ( true ) ; Opc = <STR_LIT> ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) , DstReg ) , TileSS ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) , StrideSS ) ; MI . eraseFromParent ( ) ; Changed =


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; } else if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get (


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! JUMP_P ( insn ) ) continue ; combine_bnp (


<s> if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc ,


<s> if ( ! CE ) return true ; uint64_t Value = CE ->


<s> unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned SrcLo = RegInfo . getSubReg ( Src , <STR_LIT> ) ; unsigned SrcHi = RegInfo . getSubReg ( Src , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , VR0 ) . addReg ( SrcLo , SrcKill ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY

) , DstLo ) . addReg ( VR0 , RegState :: Kill ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { return new <ISA_LIT>MCAsmInfo (


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT>


<s> if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ; else return CSR_<ISA_LIT>_AAPCS_SaveList


<s> long double __gcc_qsub ( double a , double b , double c , double d ) { return __gcc_qadd ( a , b , -


<s> MCSymbol * HandlerLabel = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; unsigned LoadOpcode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned LoadOperandsBeginIdx = <NUM_LIT> ; FM . recordFaultingOp ( FaultMaps :: FaultingLoad , HandlerLabel ) ; MCInst LoadMI ; LoadMI . setOpcode ( LoadOpcode ) ; LoadMI . addOperand ( MCOperand :: createReg ( LoadDefRegister ) ) ; for ( auto I = MI . operands_begin ( ) + LoadOperandsBeginIdx , E = MI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , * I ) ) LoadMI . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> EmitInstruction ( LoadMI , getSubtargetInfo ( )


<s> rtx addr_rtx ; if ( MEM_SIZE_KNOWN_P ( mem ) ) * size = MEM_SIZE ( mem ) ; else return false ; addr_rtx = ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; * offset = <NUM_LIT> ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , <NUM_LIT> ) ) ) { * offset += INTVAL ( XEXP


<s> case PLUS : if ( satisfies_constraint_I ( x ) ) * total = <NUM_LIT> ; else if ( satisfies_constraint_J ( x ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; default : if ( satisfies_constraint_K ( x ) || satisfies_constraint_L ( x ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case FMA : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( FLOAT_MODE_P ( mode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : case MINUS : if ( FLOAT_MODE_P ( mode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case DIV


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) && RelocM != Reloc :: Static ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDValue CPAddr


<s> if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( selectAddrFrameIndexOffset ( Addr , Base , Offset


<s> return new <ISA_LIT>ModuleDAGToDAGISel (


<s> if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type ==

GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ;


<s> SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( ! MRI . isReserved ( Reg1 ) ) MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { if ( ! MRI . isReserved ( Reg2 ) ) MBB . addLiveIn ( Reg2 ) ; MIB . addReg ( Reg2 , getPrologueDeath ( MF , Reg2 ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; } MIB . addReg ( Reg1 , getPrologueDeath ( MF , Reg1 ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx ) , MachineMemOperand :: MOStore , <NUM_LIT> ,


<s> unsigned Opc = Def -> getOpcode ( ) ; if ( Opc != TargetOpcode :: G_SHL && Opc != TargetOpcode :: G_ASHR && Opc != TargetOpcode :: G_LSHR ) return <NUM_LIT> ; auto MaybeShiftAmt = getConstantVRegValWithLookThrough ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! MaybeShiftAmt ) return <NUM_LIT> ; uint64_t ShiftAmt = MaybeShiftAmt -> Value . getZExtValue ( ) ; MachineInstr * ShiftLHS = getDefIgnoringCopies ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( IsSupportedExtend ( * ShiftLHS ) ) return ( ShiftAmt <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; LLT Ty = MRI . getType ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . isVector ( ) ) return <NUM_LIT> ; unsigned ShiftSize = Ty . getSizeInBits ( )


<s> } else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BalTgtMBB -> rbegin ( ) -> bundleWithPred ( ) ; } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . has<ISA_LIT>64r6 ( ) ) BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg (


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadDRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl ,


) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> <ISA_LIT>64Disassembler ( const MCSubtargetInfo & STI , MCContext &


<s> if ( GET_CODE ( x ) == PLUS && BASE_REGISTER_P ( XEXP ( x , <NUM_LIT> ) , strict ) && indirectable_constant_address_p ( XEXP

( x , <NUM_LIT> ) ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; O << <STR_LIT> (


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) vmlal_n_s16 ( int32x4_t a , int16x4_t b , int16_t c ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned regKind = <STR_LIT> ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok


<s> return __builtin_aarch64_sqdmull2_laneqv4si ( __a ,


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back (


<s> static int mt_function_arg_slotno ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming_p ATTRIBUTE_UNUSED , int * pregno ) { int regbase =


<s> void SLSBLRThunkInserter :: insertThunks ( MachineModuleInfo & MMI


<s> bool <ISA_LIT>SelectionDAGInfo :: generateFMAsInMachineCombiner ( CodeGenOpt :: Level OptLevel )


<s> SDValue SelectRotMask64 ( SDValue V , const SDLoc & dl , unsigned RLAmt , bool Repl32 , unsigned MaskStart , unsigned MaskEnd , unsigned * InstCnt = nullptr ) { unsigned InstMaskStart = <NUM_LIT> - MaskEnd - <NUM_LIT> , InstMaskEnd = <NUM_LIT> - MaskStart - <NUM_LIT> ; if ( InstCnt ) * InstCnt += <NUM_LIT> ; if ( Repl32 ) { assert ( InstMaskStart >= <NUM_LIT> && <STR_LIT> ) ; assert ( InstMaskEnd >= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart - <NUM_LIT> , dl ) , getI32Imm ( InstMaskEnd - <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskStart == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskEnd , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 = MaskStart ; unsigned RLAmt1 = ( <NUM_LIT> + RLAmt - RLAmt2 )


<s> void <ISA_LIT>SEInstrInfo :: ExpandRetRA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get (


<s> <ISA_LIT>ConstantPoolSymbol * <ISA_LIT>ConstantPoolSymbol :: Create ( LLVMContext & C , StringRef s


<s> int getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const override { return <ISA_LIT>GenInstrInfo :: getOperandLatency ( ItinData , DefNode , DefIdx


<s> __inline__ static void sh_media_PREFO ( void * mm , int s ) { __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char *


<s> case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return


<s> rtx op0 , op1 , ret ; op0 = ix86_compare_op0 ; op1 = ix86_compare_op1 ; if ( second_test ) * second_test = NULL_RTX ; if ( bypass_test ) * bypass_test = NULL_RTX ; if ( ix86_compare_emitted ) { ret = gen_rtx_fmt_ee ( code , VOIDmode , ix86_compare_emitted , const0_rtx ) ; ix86_compare_emitted = NULL_RTX ; } else if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_FLOAT ) ret = ix86_expand_fp_compare ( code , op0 ,


<s> void ix86_output_addr_diff_elt ( FILE * file , int value , int rel ) { if ( TARGET_64BIT ) fprintf ( file , <STR_LIT> ,

ASM_LONG , LPREFIX , value , LPREFIX , rel ) ;


<s> if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < <NUM_LIT> ) extra = <NUM_LIT> ; if ( GET_CODE ( addr ) == LO_SUM ) offset = sext_hwi ( offset ,


<s> int bs0 , bs1 , p , len ; if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; for ( bs0 = <NUM_LIT> ; bs0 < HOST_BITS_PER_WIDE_INT ; bs0 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> <<


<s> if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLd ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SDValue SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned Sub0 = ( is64BitVector ? <STR_LIT> : <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLd , <NUM_LIT> ) ) ; if ( isUpdating ) ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( VLd , <NUM_LIT> ) ) ; return


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( ( Op0 . getValueType ( ) == <STR_LIT> ) && isOneConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , NewCC ) ; } bool isFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , isFP , Op0


DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ;


<s> return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_RegMask ; return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue (


<s> case IES_RPAREN : if ( BracCount -- != <NUM_LIT> ) return true ; State = IES_RBRAC ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg =


<s> return ( __m512i ) __builtin_ia32_pabsb512_mask ( ( __v64qi ) __A , ( __v64qi ) _mm512_setzero_qi ( ) , ( __mmask64 )


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T ,


<s> return __builtin_ia32_vcvtdq2ph512_mask_round ( ( __v16si ) __A , _mm256_setzero_ph ( )

, ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;