<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT . isVector ( ) ) return LowerVSETCC ( Op , Subtarget , DAG ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } } bool isFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS = EmitCmp ( Op0 , Op1 , <ISA_LIT>CC , DAG ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,

DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) , EFLAGS ) ;


<s> if ( ! Loops ) return ; for ( unsigned i = <NUM_LIT> , e = Removed . size ( ) ; i != e ; ++ i ) Loops -> removeBlock


<s> return adjust_automodify_address ( pointer , GET_MODE ( pointer


<s> TargetAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const std :: string & TT ) { switch ( Triple ( TT ) . getOS ( ) ) { case Triple :: Darwin : return new Darwin<ISA_LIT>AsmBackend (


<s> for ( unsigned i = HalfBegin , e = HalfBegin + HalfSize ; i != e ; ++ i )

ShuffleMask . push_back ( ( HalfMask & <NUM_LIT> ) ? SM_SentinelZero : ( int ) i ) ;


<s> IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( GATHER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData ( SCATTER , <STR_LIT> , <NUM_LIT> ) ) ) ; IntrMap . insert ( std :: make_pair ( <STR_LIT> , IntrinsicData

( PREFETCH , <STR_LIT> , <STR_LIT> ) ) ) ;


<s> O << getAddrOpcStr ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printRegName ( O , MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs <<


<s> OperandMatchResultTy parseFP128 ( OperandVector


<s> rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return NULL_RTX ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return NULL_RTX ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2


<s> unsigned long n_bytes = INTVAL ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ; unsigned int n_insns = <NUM_LIT> ; if ( align > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) align = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; n_insns =


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; LLVM_FALLTHROUGH ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; default : return MCDisassembler :: Fail ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Mask = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! ( FeatureBits [ <STR_LIT> ] ) ) { if ( Mask != <NUM_LIT> ) S = MCDisassembler ::


<s> static DecodeStatus decodeDirectBrTarget ( MCInst & Inst , unsigned Imm , uint64_t , const MCDisassembler * ) { int32_t Offset = SignExtend32 < <NUM_LIT> > ( Imm ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler ::


<s> SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Value ) ) return false ; if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; getStreamer ( ) . EmitIntValue ( IntValue , Size ) ; }


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent


<s> int regno = cum -> regno ; if ( cum -> fastcall ) { if ( mode == BLKmode || mode == DImode || ( type && AGGREGATE_TYPE_P ( type ) ) ) break ; if ( regno == AX_REG ) regno = CX_REG ; } return gen_rtx_REG ( mode , regno ) ; } break ; case E_DFmode : if ( cum -> float_in_sse == - <NUM_LIT> ) error_p = true ; if ( cum -> float_in_sse < <NUM_LIT> ) break ; case E_SFmode : if ( cum -> float_in_sse == - <NUM_LIT> ) error_p = true ; if ( cum -> float_in_sse < <NUM_LIT> ) break ; case E_TImode : case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V8HFmode : case E_V8BFmode : case E_V4SFmode : case E_V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case E_OImode : case E_XImode : gcc_unreachable ( ) ; case E_V64QImode : case E_V32HImode : case E_V16SImode : case E_V8DImode : case E_V32HFmode : case E_V32BFmode : case E_V16SFmode : case E_V8DFmode : case E_V16HFmode : case E_V16BFmode : case E_V8SFmode : case E_V8SImode : case E_V32QImode : case E_V16HImode : case E_V4DFmode : case E_V4DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case E_V8QImode : case E_V4HImode : case E_V4HFmode : case E_V4BFmode : case E_V2SImode : case E_V2SFmode : case E_V1TImode : case E_V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> mmx_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> mmx_regno + FIRST_MMX_REG ) ; } break ; } if ( error_p ) { cum -> float_in_sse = <NUM_LIT> ; error ( <STR_LIT> <STR_LIT> , cum -> decl ) ; sorry ( <STR_LIT> <STR_LIT> ) ; } return NULL_RTX


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return


<s> if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( VldN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , VectorType :: get ( SV -> getType ( ) -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) ) ) ; SubVecs [ SV ] . push_back ( SubVec ) ; } } for ( ShuffleVectorInst * SVI : Shuffles ) { auto & SubVec = SubVecs [


<s> return DAG . getConstant ( <NUM_LIT> , Op .


<s> void <ISA_LIT>TargetStreamer :: emitConstantPools ( ) { if ( EXRLTargets2Sym . empty ( ) ) return ; const MCObjectFileInfo & OFI = * Streamer . getContext ( ) . getObjectFileInfo ( ) ; Streamer . SwitchSection ( OFI . getTextSection ( ) ) ; for ( auto & I : EXRLTargets2Sym ) { Streamer . emitLabel ( I . second ) ; const MCInstSTIPair & MCI_STI = I .


<s> bool <ISA_LIT>FastISel :: emitICmp_ri ( MVT RetVT , unsigned LHSReg , uint64_t Imm ) { return emitAddSub_ri ( false , RetVT , LHSReg , Imm ,


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM =


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> left . i [ <NUM_LIT> ] = count ; right . i [ <NUM_LIT> ] = <NUM_LIT> - count ; return ( ( qword ) ( vec_or ( vec_slo ( ( vec_uchar16 ) ( a ) , left . v ) , vec_sro ( ( vec_uchar16 )


<s> static DecodeStatus DecodeGPR32spRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR32DecoderTable [ RegNo ] ; if ( Register == <STR_LIT> ) Register = <STR_LIT> ; Inst . addOperand ( MCOperand ::


<s> if ( isMaskRegClass ( RC ) ) return getLoadStoreMaskRegOpcode ( RC , load ) ; if ( RC -> getSize ( ) == <NUM_LIT> && <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( RC -> getSize ( ) == <NUM_LIT> && <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; } bool HasAVX = STI . hasAVX ( ) ; switch ( RC -> getSize ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( STI . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> bool mustAddCurrentAddress ( ) const { return AddCurrentAddress


<s> } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = uint32_t ( * CI -> getValue ( ) . getRawData ( ) ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) -> isFloatTy ( ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt


<s> void addAlignedMemoryOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> MachineOperand GAOp = MI . getOperand ( <NUM_LIT> ) ; uint64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; auto Key = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned AddrDisc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t Disc = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand GAHiOp ( GAOp ) ; MachineOperand GALoOp ( GAOp ) ; GAHiOp . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; GALoOp . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( GAHiOp ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( GALoOp ) ; if ( Offset ) { if ( ! isUInt < <NUM_LIT> > ( Offset ) ) report_fatal_error ( <STR_LIT> ) ; for ( int BitPos = <NUM_LIT> ; BitPos < <NUM_LIT> && ( Offset >> BitPos ) ; BitPos += <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ( Offset >> BitPos ) & <NUM_LIT> ) . addImm ( <STR_LIT> ( <STR_LIT> , BitPos ) ) ; } } unsigned DiscReg = <STR_LIT> ; if ( Disc ) { DiscReg = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Disc ) . addImm ( <NUM_LIT> ) ; } else if ( AddrDisc != <STR_LIT> ) { assert ( Disc == <NUM_LIT> && <STR_LIT> ) ; DiscReg = AddrDisc ; } unsigned PACOpc = getPACOpcodeForKey ( Key , DiscReg == <STR_LIT> ) ; auto MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( PACOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( DiscReg != <STR_LIT> ) MIB . addReg ( DiscReg ) ; MI . eraseFromParent ( ) ; return


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS << <STR_LIT>


<s> if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] && ! ( MI . mayLoad ( ) && UsedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) && ! mayAlias ( MI , MemInsns , TII ) ) { Flags . setMergeForward ( false ) ; return MBBI ; } if ( ! ModifiedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] && ! ( MayLoad && UsedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] ) && ! mayAlias ( FirstMI , MemInsns , TII ) ) { Flags . setMergeForward ( true ) ; return MBBI ; } } } if ( MI . isCall ( ) ) return E ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ]


<s> unsigned TZ = countTrailingZeros ( Imm ) ; Shift = ( TZ / <NUM_LIT> ) * <NUM_LIT> ; LastShift = ( ( <NUM_LIT> - LZ ) / <NUM_LIT> ) * <NUM_LIT> ; } unsigned Imm16 = ( Imm >> Shift ) & Mask ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( FirstOpc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && Shift == LastShift ) ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , Shift ) ) ; if ( isNeg ) Imm = ~ Imm ; if ( Shift == LastShift ) { transferImpOps ( MI , MIB1 , MIB1 ) ; MI . eraseFromParent ( ) ; return true ; } MachineInstrBuilder MIB2 ; unsigned Opc = ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; while ( Shift < LastShift ) { Shift += <NUM_LIT> ; Imm16 = ( Imm >> Shift ) & Mask ; if ( Imm16 == ( isNeg ? Mask : <NUM_LIT> ) ) continue ; MIB2 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( DstReg , RegState :: Define |

getDeadRegState ( DstIsDead && Shift == LastShift ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , Shift ) ) ;


<s> CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = OutStreamer -> getContext ( ) . getXCOFFSection ( CurrentFnDescSym -> getName ( ) , XCOFF :: XMC_DS , XCOFF :: XTY_SD , XCOFF :: C_HIDEXT , SectionKind :: getData ( ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect ( FnDescSec ) ; return AsmPrinter :: SetupMachineFunction


<s> unsigned getArgRegsSaveSize ( ) const { return ArgRegsSaveSize


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: ParseOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , StringRef Mnemonic ) { OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; case AsmToken :: Identifier : { OperandMatchResultTy GotShift = ParseShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; uint32_t NumLanes = <NUM_LIT> ; OperandMatchResultTy GotReg = ParseRegister ( Operands , NumLanes ) ; assert ( GotReg != MatchOperand_ParseFail && <STR_LIT> ) ; if ( GotReg == MatchOperand_Success ) { if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) return ParseNEONLane ( Operands , NumLanes ) ; else return MatchOperand_Success ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : case AsmToken :: Dollar : case AsmToken :: Colon : { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; const MCExpr * ImmVal = <NUM_LIT> ; if ( ParseImmediate ( ImmVal ) != MatchOperand_Success ) return MatchOperand_ParseFail ; EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , StartLoc , EndLoc ) ) ; return MatchOperand_Success ; } case AsmToken :: Hash : { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; const MCExpr * ImmVal = <NUM_LIT> ; Parser . Lex ( ) ; if ( ParseImmediate ( ImmVal ) != MatchOperand_Success ) return MatchOperand_ParseFail ; EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , StartLoc , EndLoc ) ) ; return MatchOperand_Success ; } case AsmToken :: LBrac : { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Loc ) ) ; Parser . Lex ( ) ; return ParseOperand ( Operands


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_Ghc_RegMask ; if ( ! Is64Bit


<s> if ( size == <NUM_LIT> ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_frame_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7


<s> MCSymbol * <ISA_LIT>TargetLowering :: getPICBaseSymbol ( const MachineFunction * MF , MCContext & Ctx ) const { const MCAsmInfo & MAI = * getTargetMachine (


<s> if ( ! Subtarget -> is<ISA_LIT>64 ( ) && ( TM . getRelocationModel ( ) != Reloc :: PIC_ || MF -> getFunction ( ) -> getParent ( ) -> getPICLevel ( ) == PICLevel :: Small ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; if ( ! Subtarget -> is<ISA_LIT>64 ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> usesPICBase ( ) ) { MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym


<s> void <ISA_LIT>ExpandPseudo :: TransferImpOps ( MachineInstr & OldMI , MachineInstrBuilder & UseMI , MachineInstrBuilder & DefMI ) { const MCInstrDesc & Desc = OldMI . getDesc ( ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO .


<s> if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; SmallVector < unsigned , <NUM_LIT> > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = <NUM_LIT> ; return FoldMI ; } return nullptr


<s> static bool isSequentialOrUndefOrZeroInRange ( ArrayRef < int > Mask , unsigned Pos , unsigned Size ,


<s> if ( TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE ( valtype ) == DCmode ) { return gen_rtx_PARALLEL ( DCmode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; else mode = TYPE_MODE ( valtype


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperands ( const <ISA_LIT>AddressingMode & AM , EVT VT , SDValue & Base , SDValue & Disp , SDValue & Index ) const { getAddressOperands ( AM , VT , Base ,


<s> __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st3v4si ( ( __builtin_aarch64_simd_si *


<s> insn -> repeatPrefix = prefix ; break ; case <NUM_LIT> : if ( lookAtByte ( insn , & nextByte ) ) break ; if ( ! insn -> mandatoryPrefix && ( nextByte == <NUM_LIT> || isREX ( insn , nextByte ) ) ) insn


<s> Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx


<s> processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC ->


<s> const MCPhysReg * <ISA_LIT>TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { <STR_LIT> , <STR_LIT>


<s> unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { NumNoNeedForFrame ++ ; if ( UpdateMF ) MFI . setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize


<s> inline static unsigned makePostOp ( unsigned AluOp ) { assert ( ! isPreOp ( AluOp ) && <STR_LIT> ) ; return AluOp | <ISA_LIT>_POST_OP


<s> if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; NewShiftVal = NumBitsPerElt - <NUM_LIT> ; } return DAG . getNode ( Opcode , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; for ( APInt & Elt : EltBits ) { if ( <STR_LIT> == Opcode ) Elt <<= ShiftVal ; else if ( <STR_LIT> == Opcode ) Elt . ashrInPlace ( ShiftVal ) ; else Elt . lshrInPlace ( ShiftVal ) ; } return getConstVector ( EltBits , UndefElts , VT . getSimpleVT ( ) , DAG , SDLoc


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString


<s> CallingConv :: ID CallingConvention = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CallingConvention == CallingConv :: HiPE ) { if ( Is64Bit ) return Primary ? <STR_LIT> : <STR_LIT> ; else return Primary ? <STR_LIT> : <STR_LIT> ; } if ( Is64Bit ) { if ( IsLP64 ) return Primary ? <STR_LIT> : <STR_LIT> ; else return Primary ? <STR_LIT>


<s> if ( Bitcast -> user_empty ( ) ) { DeadInsts . push_back ( Bitcast ) ; continue ; } LoadInst * LD = dyn_cast < LoadInst > ( Src ) ; if ( ! LD ) { if ( transformBitcast ( Bitcast ) ) DeadInsts . push_back ( Bitcast ) ; continue ; } combineLoadBitcast ( LD , Bitcast ) ; DeadInsts . push_back ( Bitcast ) ; if ( LD -> hasOneUse ( ) ) DeadInsts . push_back ( LD ) ; } else if ( Src -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { if ( Bitcast -> user_empty ( ) ) { DeadInsts . push_back ( Bitcast ) ; continue ; } StoreInst * ST = nullptr ; for ( auto UI = Bitcast -> use_begin ( ) , UE = Bitcast -> use_end ( ) ; UI != UE ; ) { Value * I = ( UI ++ ) -> getUser ( ) ; ST = dyn_cast < StoreInst > ( I ) ; if ( ST ) break ; } if ( ! ST ) { if ( transformBitcast ( Bitcast ) ) DeadInsts . push_back ( Bitcast ) ; continue ; } combineBitcastStore ( Bitcast , ST ) ; DeadInsts . push_back ( ST ) ; DeadInsts . push_back ( Bitcast ) ; } } } bool C = ! DeadInsts . empty ( ) ; for ( auto * Inst : DeadInsts ) Inst -> eraseFromParent


<s> if ( ! MI -> isFullCopy ( ) ) return MI ; if ( ! TRI -> isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) )


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) { if ( TheTriple . getArchName ( ) == <STR_LIT> || TheTriple . getArchName ( ) == <STR_LIT> ) return new Darwin<ISA_LIT>AsmBackend ( T , TT , object


<s> O << <STR_LIT> ; printLeaMemReference ( MI , OpNo , O


<s> return DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF || ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF && Addend == <NUM_LIT> ) || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) .

hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue & Offset ) { return IsAddressingMode5 ( N , Base


<s> code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1


<s> if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( <STR_LIT> ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , <NUM_LIT>


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( useSVEForFixedLengthVectorVT ( VT ) ) return false ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned Cost = getPerfectShuffleCost ( M ) ; if ( Cost <= <NUM_LIT>


<s> GlobalAddressSDNode * GlobalAddr = cast < GlobalAddressSDNode > ( Op . getNode ( ) ) ; SDValue TargetAddr = DAG . getTargetGlobalAddress ( GlobalAddr -> getGlobal ( ) , Op , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , Op , VT , TargetAddr


<s> else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveNops ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_lower ( <STR_LIT> ) ) ) return parseDirectiveSEHPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_lower ( <STR_LIT> ) ) ) return parseDirectiveSEHSetFrame


<s> EVT VectorT1 = Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT VectorT2 = Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; uint64_t Size = VectorT1 . getFixedSizeInBits ( ) ; if ( VectorT1 != VectorT2 || ( Size != <NUM_LIT> && Size != <NUM_LIT> ) ) return SDValue ( ) ; EVT VT1 = VectorT1 . getVectorElementType ( ) ; if ( VT1 != <STR_LIT> && VT1 != <STR_LIT> && VT1 != <STR_LIT> ) return SDValue ( ) ; Op0 = Op0 .


<s> } if ( ! reg_dead_after_insn ( m_ccreg , e . cstore . insn ) && ! reg_unused_after_insn ( m_ccreg , e . cstore . insn ) ) { log_msg ( <STR_LIT> ) ; log_insn ( e . cstore . insn ) ; log_return ( false , <STR_LIT> ) ; } if ( multiple_sets ( e . setcc


<s> if ( CallMI . isCall ( ) && CallMI . getOperand ( <NUM_LIT> ) . isGlobal ( ) ) { const Function * CalleeFn = dyn_cast < Function > ( CallMI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ) ; if ( ! CalleeFn ) return false ; const IntegerType * IntTy = dyn_cast < IntegerType > ( CalleeFn -> getReturnType ( ) ) ; const AttributeSet & Attrs = CalleeFn -> getAttributes ( ) . getRetAttrs ( ) ; if ( IntTy && IntTy -> getBitWidth ( ) <= <NUM_LIT> ) return Attrs . hasAttribute ( SignExt ? Attribute :: SExt : Attribute :: ZExt ) ; } } } } if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { E = MI . getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( MI . getOperand ( I ) . isReg ( ) ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI == NULL || ! isSignOrZeroExtended ( * SrcMI , SignExt , Depth + <NUM_LIT> ) ) return false ; } else return false ; } return


<s> return ( __m128i ) __builtin_ia32_lddqu ( ( char const * )


<s> return gen_frame_set ( reg , frame_reg , offset


<s> case E_V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case E_V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ <NUM_LIT> ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ <NUM_LIT> ] , two31r , val , tmp [ <NUM_LIT> ] ) ) ; tmp [ <NUM_LIT> ] = expand_simple_binop ( mode , AND , tmp [ <NUM_LIT> ] , two31r , tmp [ <NUM_LIT> ] , <NUM_LIT> , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ <NUM_LIT>

] ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) { CPUName = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName ,


<s> switch ( ppFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( zFromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_EVEXKZ ; if ( bFromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_EVEXB ; if ( aaaFromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_EVEXK ; if ( lFromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_EVEXL ; if ( l2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_EVEXL2 ; } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( ppFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { switch ( ppFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( ppFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> mode != MODE_16BIT && isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_ADSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( insn -> rexPrefix & <NUM_LIT>


<s> rtx call [ <NUM_LIT> ] ; rtx insn ; int cookie_val = INTVAL ( cookie ) ; bool make_island = false ; if ( ( cookie_val & CALL_LONG ) != <NUM_LIT> && GET_CODE ( func_desc ) == SYMBOL_REF ) { if ( darwin_emit_branch_islands && TARGET_32BIT ) make_island = true ; else { func = rs6000_longcall_ref ( func_desc , NULL_RTX ) ; cookie_val &= ~ CALL_LONG ; } } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , GEN_INT ( cookie_val ) ) ; if ( sibcall ) call [ <NUM_LIT> ] = simple_return_rtx ; else call [ <NUM_LIT> ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v


<s> switch ( align ) { case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn


<s> static unsigned int loongarch_builtin_avail_default (


<s> const TargetMachine & TM = FuncInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget


<s> if ( HardenInterprocedurally ) { for ( MachineBasicBlock & MBB : MF ) { assert ( ! MBB . isEHScopeEntry ( ) && <STR_LIT> ) ; assert ( ! MBB . isEHFuncletEntry ( ) && <STR_LIT> ) ; assert ( ! MBB . isCleanupFuncletEntry ( ) && <STR_LIT> ) ; if ( ! MBB . isEHPad ( ) ) continue ; PS -> SSA . AddAvailableValue ( & MBB , extractPredStateFromSP ( MBB , MBB . SkipPHIsAndLabels ( MBB . begin ( ) ) , Loc ) ) ; } } if ( HardenIndirectCallsAndJumps ) { unfoldCallAndJumpLoads ( MF ) ; auto IndirectBrCMovs = tracePredStateThroughIndirectBranches ( MF ) ; CMovs . append ( IndirectBrCMovs . begin ( ) , IndirectBrCMovs . end ( ) ) ; } tracePredStateThroughBlocksAndHarden ( MF ) ; for ( MachineInstr * CMovI : CMovs ) for ( MachineOperand & Op : CMovI -> operands ( ) ) { if ( ! Op . isReg ( ) || Op . getReg ( ) != PS -> InitialReg ) continue ; PS -> SSA . RewriteUse ( Op ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ; dbgs ( ) << <STR_LIT> ; MF .


<s> static inline const MachineInstrBuilder & AddNoT1CC ( const MachineInstrBuilder & MIB ) { return MIB . addReg


<s> if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT>


<s> for ( end = loop -> end -> next ; end != <NUM_LIT> ; end = end -> next ) { rtx_insn * newjmp ; newjmp = emit_jump_insn_before ( gen_jump ( repeat_label ) , end -> insn ) ; JUMP_LABEL ( newjmp ) = repeat_label ; delete_insn ( end -> insn ) ; delete_insn ( end -> fallthrough ) ; } } else { for ( begin = loop -> begin ; begin != <NUM_LIT> ; begin = begin -> next ) { insn = gen_move_insn ( copy_rtx ( begin -> counter ) , copy_rtx ( begin -> loop_count ) ) ; emit_insn_before ( insn , begin -> insn ) ; delete_insn ( begin -> insn ) ; } for ( end = loop -> end ; end != <NUM_LIT> ; end = end -> next ) { rtx reg ; start_sequence ( ) ; reg = end -> counter ; if ( ! REG_P ( reg ) || REGNO ( reg ) > LAST_NONIO_GP_REGNUM ) { reg = end -> scratch ; emit_move_insn ( copy_rtx ( reg ) , copy_rtx ( end -> counter ) ) ; } emit_insn ( gen_add3_insn ( copy_rtx ( reg ) , copy_rtx ( reg ) , constm1_rtx ) ) ; if ( reg != end -> counter ) emit_move_insn ( copy_rtx ( end -> counter ) , copy_rtx ( reg ) ) ; insn = emit_jump_insn ( gen_cbranchsi4 ( gen_rtx_NE ( VOIDmode , reg , const0_rtx ) , reg , const0_rtx , end -> label ) ) ; JUMP_LABEL ( insn ) = end -> label ; LABEL_NUSES ( end -> label ) ++ ; insn = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( insn , end


<s> PM . add ( create<ISA_LIT>CodeEmitterPass ( * this , MCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT>


<s> if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= <NUM_LIT> || scale > <NUM_LIT> || ( scale & ( scale - <NUM_LIT> ) ) != <NUM_LIT> ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; default : return NULL_TREE ; } return ix86_builtins [ code


<s> bool <ISA_LIT>InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AA ) const { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) )

&& ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) return <NUM_LIT> ;


<s> OS << '%' << StringRef ( getRegisterName ( RegNo )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ( EVT . getSizeInBits ( ) == <NUM_LIT> || EVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc = ( EVT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast

< ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ;


<s> break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> )


<s> Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O'


<s> static DecodeStatus DecodeExtSize ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Size = ( int ) Insn + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 <


<s> return ( __m128i ) __builtin_ia32_vpcomleq ( ( __v2di ) __A ,


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false


<s> Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; return true ; case <STR_LIT> : if ( ! areOperandsOfVmullHighP64 ( II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ) return false ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 -> getOperand ( <NUM_LIT> ) , Ext2 -> getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands (


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { SDValue ResNode ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; const Constant * C = N -> getConstVal ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDValue CPHi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue CP = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , GOTFlag ) ; CP = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG ,


<s> const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; Register BaseReg = TRI -> getBaseRegister (


<s> tree type = arg . type ; machine_mode mode = arg . mode ; if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE

( mode ) > <NUM_LIT> || ( type && VECTOR_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) ;


<s> static DecodeStatus DecodeGPRnopcRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget . is64Bit ( ) ) { return Op ; } SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ) ; return BuildFILD ( Op , SrcVT , Chain ,


<s> ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop1MBB ) ; BB -> addSuccessor (


<s> bool <ISA_LIT>ParallelDSP :: InsertParallelMACs ( Reduction & Reduction ) { Instruction * Acc = Reduction . Phi ; Instruction * InsertAfter = Reduction . AccIntAdd ; for ( auto & Pair : Reduction . PMACPairs ) { BinOpChain * PMul0 = Pair . first ; BinOpChain * PMul1 = Pair . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; PMul0 -> Root -> dump ( ) ; dbgs ( ) << <STR_LIT> ; PMul1 -> Root -> dump ( ) ) ; Acc = CreateSMLADCall ( PMul0 -> VecLd , PMul1 -> VecLd , Acc , PMul1 -> Exchange , InsertAfter ) ; InsertAfter = Acc ; } if ( Acc != Reduction . Phi ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; Reduction . AccIntAdd -> replaceAllUsesWith (


<s> if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return <NUM_LIT> ; if ( MI -> isBundle ( ) ) { unsigned Latency = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , & * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) ) { * PredCost =


<s> auto Token = Parser . getTok ( ) ; SMLoc S = Token . getLoc ( ) ; if ( Token . isNot ( AsmToken :: Dollar ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar ( Operands , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( )


<s> Target & llvm :: getThe<ISA_LIT>_64Target


<s> MachineBasicBlock * BB = Fn . CreateMachineBasicBlock ( ) ; Fn . push_back ( BB ) ; const std :: vector < MachineConstantPoolEntry > & CPs = Fn . getConstantPool ( ) -> getConstants ( ) ; const TargetData & TD = * Fn . getTarget ( ) . getTargetData ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; NumCPEs ++ ; DOUT << <STR_LIT> << i << <STR_LIT> <<


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) ,


<s> if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( ZeroReg ) MIB . addReg ( <STR_LIT> ) ; if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState


<s> const TargetRegisterClass * RC ; if ( HasSPE ) RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; else RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; Register DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Alignment ) ; unsigned Opc ; if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Register TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { Register TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } return DestReg


<s> if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg ) && <STR_LIT> ) ; assert ( MI . definesRegister ( DReg , TRI )


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return Subtarget -> isTargetDarwin ( ) ? LowerGlobalAddressDarwin ( Op , DAG ) : LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerCALL ( Op , DAG ) ; case <STR_LIT> : return LowerRET ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex


<s> O << StringRef ( getRegisterName ( RegNo )


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired <


<s> assert ( Ty . isFatPointer ( ) ) ; assert ( ABI . IsCheriPureCap ( ) ) ; SDValue Off = getTargetNode ( N , <STR_LIT> , DAG , Flag ) ; SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , CapType

, getCapGlobalReg ( DAG , CapType ) , Off ) ;


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } fprintf ( file ,


<s> ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( Input . getOperand ( <NUM_LIT> ) ) ; SDValue OrigVector = Input . getOperand ( <NUM_LIT> ) ; if ( Idx && VT == OrigVector . getValueType ( ) ) { SmallVector < int , <NUM_LIT> > NewMask ( VT . getVectorNumElements ( ) , - <NUM_LIT> ) ; NewMask [ VT . getVectorNumElements ( ) / <NUM_LIT> ] = Idx -> getZExtValue


<s> static DecodeStatus DecodeVLDST3Instruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( align & <NUM_LIT> ) return MCDisassembler ::


<s> if ( IsATT ) O << '%' ; O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; } case MachineOperand :: MO_Immediate : if ( IsATT ) O << '$' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : { if ( IsATT ) O << '$' ; PrintSymbolOperand ( MO , O


<s> pool_node * p = & pool_vector [ i ] ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ; output_asm_insn ( <STR_LIT> , & p -> value


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> getDesc ( ) . hasDelaySlot ( ) ) { MachineBasicBlock :: iterator J


<s> SDValue LoA = CDAG . getUnpack ( <STR_LIT> , A , PackElem :: Lo , AVL ) ; SDValue HiA = CDAG . getUnpack ( <STR_LIT> , A , PackElem :: Hi , AVL ) ; SDValue LoB = CDAG . getUnpack ( <STR_LIT> , B , PackElem :: Lo , AVL ) ; SDValue HiB = CDAG . getUnpack ( <STR_LIT> , B , PackElem


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo


<s> unsigned int low , high ; low = mips_const_insns ( mips_subword ( x , false ) ) ; high = mips_const_insns ( mips_subword ( x , true ) ) ; gcc_assert ( low > <NUM_LIT> && high


<s> static SDValue PerformVDUPCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( Op . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; else if ( Op . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD

-> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ;


<s> if ( IsPCRel && RelocType == macho :: RIT_Vanilla ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && SD && ! Writer -> doesSymbolRequireExternRelocation ( SD ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation


<s> DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> <<

OffsetBits << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ;


<s> const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string jumpLabel = <STR_LIT> ; if ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) ) jumpLabel = MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) -> getName ( ) ; SExpr * call = ctx -> call ( ctx -> labelRef


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , ScalarEvolution * SE , const SCEV * Ptr ) { const unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE ) { if ( ! BaseT :: isStridedAccess ( Ptr ) ) return NumVectorInstToHideOverhead ; if ( ! BaseT :: getConstantStrideStep ( SE , Ptr ) ) return <NUM_LIT> ; } return BaseT :: getAddressComputationCost ( Ty ,


<s> MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( * MI ) ; ++ MI


<s> const MCExpr * E = MCSymbolRefExpr :: Create ( Get<ISA_LIT>GVSymbol ( GV , <STR_LIT> ) , ( Subtarget -> isTargetELF ( ) ? MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : MCSymbolRefExpr :: VK_None ) , OutContext ) ; OutStreamer . EmitValue ( E , Size


<s> bool isSP = FrameReg == <STR_LIT> ; bool HasCCOut = Opcode != <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( isSP ? <STR_LIT> : <STR_LIT> ) ) ; } else { MI . setDesc ( TII . get ( isSP ? <STR_LIT> : <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; Offset = <NUM_LIT> ; return true ; } if ( Offset < <NUM_LIT> && ( ! HasCCOut || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ) { unsigned NewOpc = isSP ? ( isSub ? <STR_LIT> : <STR_LIT> ) : ( isSub ? <STR_LIT> : <STR_LIT> ) ; MI . setDesc ( TII . get ( NewOpc ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; if ( HasCCOut ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = CountLeadingZeros_32 ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; if ( ! HasCCOut ) MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; } else { if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return false ; unsigned NewOpc = Opcode ; if ( AddrMode == <STR_LIT> ) { unsigned OffsetReg = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getReg ( ) ; if ( OffsetReg != <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; return Offset == <NUM_LIT> ; } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT>


<s> static SDValue lowerV32I16Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = vectorWidth / ElVT .


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU


<s> Inst . addOperand ( MCOperand :: CreateReg ( getGPRMM16Reg ( )


<s> } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB ,


<s> Inst . addOperand ( MCOperand :: CreateExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg


<s> return ( int32x2_t ) __builtin_neon_vreinterpretv2siv2sf (


<s> while ( FixCount -- ) { unsigned OldReg = getStackEntry ( FixCount ) ; unsigned Reg = FixStack [ FixCount ] ; if ( Reg == OldReg ) continue ; moveToTop ( Reg , I ) ; if ( FixCount > <NUM_LIT> ) moveToTop ( OldReg , I ) ; } LLVM_DEBUG ( dumpStack ( )


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BimmX16MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( isBBInRange ( MI , DestBB , BimmX16MaxDisp ) ) { Br . MaxDisp = BimmX16MaxDisp ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } else { DestBB -> setAlignment ( <NUM_LIT> ) ; Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB


<s> MI . getOperand ( <NUM_LIT> ) . setReg ( SrcHiReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , <STR_LIT> ) ; Register DestLoReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , II , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestHiReg ) ; Offset +=


<s> break ; } case 'u' : case 'e' : result = result * <NUM_LIT> + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * <NUM_LIT> + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * <NUM_LIT> + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = <NUM_LIT> ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * <NUM_LIT> + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result


<s> FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: getRealLinkageName ( ParentFunc -> getName ( ) ) , TheModule ) ; BasicBlock * EntryBB = BasicBlock :: Create ( Context , <STR_LIT> , Trampoline ) ; IRBuilder < > Builder ( EntryBB


<s> grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( groff ) , groff , build_int_cst ( TREE_TYPE ( groff


<s> BitVector <ISA_LIT>BaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; BitVector Reserved ( getNumRegs ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; } CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB )


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCSubtargetInfo


<s> vec_uchar16 v ; unsigned int i [ <NUM_LIT> ] ; } x ; unsigned int cnt ; vec_uchar16 mask ; x . v = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> )


<s> uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MachineLocation DstML0 ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation DstML1 ( MachineLocation :: VirtualFP


<s> if ( ST -> hasMVEFloatOps ( ) ) if ( SDValue NewLoad = PerformSplittingToWideningLoad ( N ,


<s> switch ( MO . getType ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; operand = <STR_LIT> + LowercaseString ( getRegisterName ( MO . getReg ( ) ) ) ; break ; } unsigned mfNum = MI -> getParent ( ) -> getParent ( ) -> getFunctionNumber ( ) ; unsigned bbNum = MI -> getParent ( ) -> getNumber ( ) ; O << '\n' << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> ; O << <STR_LIT> << mfNum << '_' << bbNum << '\n' ; O << <STR_LIT> << <STR_LIT> << mfNum << '_' << bbNum


<s> return ( __m512i ) __builtin_ia32_psllv8di_mask ( ( __v8di ) __X , ( __v8di ) __Y , (

__v8di ) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> gen_neg = gen_negsi2 ; break ; case DImode : gen_neg = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } e1 = gen_reg_rtx ( inmode ) ; e2 = gen_reg_rtx ( inmode ) ; res = gen_reg_rtx ( outmode ) ; half = CONST_DOUBLE_FROM_REAL_VALUE ( dconsthalf , inmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_UNSPEC ( HImode , gen_rtvec ( <NUM_LIT> , op1 ) , UNSPEC_FXAM ) ) ) ; emit_insn ( gen_abs ( e1 , op1 ) ) ; half = force_reg ( inmode , half ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_PLUS ( inmode , e1 , half ) ) ) ; if ( inmode != XFmode ) { tmp1 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp1 , gen_rtx_FLOAT_EXTEND ( XFmode , e2 ) ) ) ; } else tmp1 = e2 ; switch ( outmode ) { case SFmode : case DFmode : { rtx tmp0 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_frndintxf2_floor ( tmp0 , tmp1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( <NUM_LIT> , tmp0 ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; case XFmode : emit_insn ( gen_frndintxf2_floor ( res , tmp1 ) ) ; break ; case HImode


<s> Offset = DAG . getConstant ( - RHSC , RHS -> getValueType ( <NUM_LIT> ) ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; return true ; } } if ( Ptr -> getOpcode ( ) == <STR_LIT> ) { isInc = true ; <STR_LIT> ShOpcVal = <STR_LIT> ( Ptr -> getOperand ( <NUM_LIT> ) ) ; if ( ShOpcVal != <STR_LIT> ) { Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; } else { Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; } return true ; } isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT>


<s> if ( DisableBackwardSearch ) return false ; auto * Fn = MBB . getParent ( ) ; RegDefsUses RegDU ( * Fn -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MemDefsUses MemDU ( Fn -> getDataLayout ( ) , & Fn -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( Slot ) ; MachineBasicBlock :: iterator SlotI = Slot ; if ( ! searchRange ( MBB , ++ SlotI . getReverse ( ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( SlotI ) , & MBB , Filler . getReverse ( ) ) ; MIBundleBuilder ( MBB , SlotI , std :: next ( SlotI , <NUM_LIT> ) ) ; ++ UsefulSlots


<s> static MachineOperand & getBaseOperand (


<s> size_t uns_fcode = ( size_t ) fcode ; const struct builtin_description * d ; size_t i ; rtx ret ; bool success ; HOST_WIDE_INT mask = rs6000_builtin_info [ uns_fcode ] . mask ; bool func_valid_p = ( ( rs6000_builtin_mask & mask ) == mask ) ; enum insn_code icode = rs6000_builtin_info [ uns_fcode ] . icode ; if ( FLOAT128_IEEE_P ( TFmode ) ) switch ( icode ) { default : break ; case CODE_FOR_sqrtkf2_odd : icode = CODE_FOR_sqrttf2_odd ; break ; case CODE_FOR_trunckfdf2_odd : icode = CODE_FOR_trunctfdf2_odd ; break ; case CODE_FOR_addkf3_odd : icode = CODE_FOR_addtf3_odd ; break ; case CODE_FOR_subkf3_odd : icode = CODE_FOR_subtf3_odd ; break ; case CODE_FOR_mulkf3_odd : icode = CODE_FOR_multf3_odd ; break ; case CODE_FOR_divkf3_odd : icode = CODE_FOR_divtf3_odd ; break ; case CODE_FOR_fmakf4_odd : icode = CODE_FOR_fmatf4_odd ; break ; case CODE_FOR_xsxexpqp_kf : icode = CODE_FOR_xsxexpqp_tf ; break ; case CODE_FOR_xsxsigqp_kf : icode = CODE_FOR_xsxsigqp_tf ; break ; case CODE_FOR_xststdcnegqp_kf : icode = CODE_FOR_xststdcnegqp_tf ; break ; case CODE_FOR_xsiexpqp_kf : icode = CODE_FOR_xsiexpqp_tf ; break ; case CODE_FOR_xsiexpqpf_kf : icode = CODE_FOR_xsiexpqpf_tf ; break ; case CODE_FOR_xststdcqp_kf : icode = CODE_FOR_xststdcqp_tf ; break ; } if ( TARGET_DEBUG_BUILTIN ) { const char * name1 = rs6000_builtin_info [ uns_fcode ] . name ; const char * name2 = ( icode != CODE_FOR_nothing ) ? get_insn_name ( ( int ) icode ) : <STR_LIT> ; const char * name3 ; switch ( rs6000_builtin_info [ uns_fcode ] . attr & RS6000_BTC_TYPE_MASK ) { default : name3 = <STR_LIT> ; break ; case RS6000_BTC_SPECIAL : name3 = <STR_LIT> ; break ; case RS6000_BTC_UNARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_BINARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_TERNARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_PREDICATE : name3 = <STR_LIT> ; break ; case RS6000_BTC_ABS : name3 = <STR_LIT> ; break ; case RS6000_BTC_DST : name3 = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> , ( name1 ) ? name1 : <STR_LIT> , fcode , ( name2 ) ? name2 : <STR_LIT> , ( int ) icode , name3 , func_valid_p ? <STR_LIT> : <STR_LIT> ) ; } if ( ! func_valid_p ) { rs6000_invalid_builtin ( fcode ) ; return expand_call ( exp , target , ignore ) ; } switch ( fcode ) { case RS6000_BUILTIN_RECIP : return rs6000_expand_binop_builtin ( CODE_FOR_recipdf3 , exp , target ) ; case RS6000_BUILTIN_RECIPF : return rs6000_expand_binop_builtin ( CODE_FOR_recipsf3 , exp , target ) ; case RS6000_BUILTIN_RSQRTF : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtsf2 , exp , target ) ; case


<s> } if ( Op2 . getReg ( ) == <STR_LIT> ) return ; unsigned PairedReg = GPR . getRegister ( RtEncoding + <NUM_LIT> ) ; if ( ! PairedReg || PairedReg == <STR_LIT> || ( PairedReg == <STR_LIT> && ! hasV8Ops ( ) ) ) return ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , <ISA_LIT>Operand :: CreateReg ( PairedReg , Op2 .

getStartLoc ( ) , Op2 . getEndLoc ( ) ) ) ;


<s> switch ( Size ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( IsLittleEndian ) { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } break ; case <NUM_LIT> : if ( IsLittleEndian )


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_Q1 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_Q2 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_Q3 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_Q4 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL26 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL19 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_9BIT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_6BIT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_12BIT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_MOVRZ : OS << <STR_LIT> ; break ; default : { std :: string msg = <STR_LIT> + std :: to_string ( Kind ) + <STR_LIT> ; llvm_unreachable ( msg . c_str ( ) ) ; } } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << <ISA_LIT>_ez_int2hex


<s> emit_clobber ( gen_frame_mem ( BLKmode ,


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 ,


<s> unsigned int regno , count ; gcc_assert ( TARGET_HARD_FLOAT && ISA_HAS_8CC ) ; if ( mode == CCmode ) count = <NUM_LIT> ; else if ( mode == CCV2mode ) count = <NUM_LIT> ; else if ( mode == CCV4mode ) count = <NUM_LIT> ; else gcc_unreachable ( ) ; cfun -> machine -> next_fcc += - cfun -> machine ->


<s> static SDValue CommuteVectorShuffleMask ( SDValue Mask , SelectionDAG & DAG , DebugLoc dl ) { MVT MaskVT = Mask . getValueType ( ) ; MVT EltVT = MaskVT . getVectorElementType ( ) ; unsigned NumElems = Mask . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Arg = Mask . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { MaskVec . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val < NumElems ) MaskVec . push_back ( DAG . getConstant ( Val + NumElems , EltVT ) ) ; else MaskVec . push_back ( DAG . getConstant ( Val - NumElems , EltVT ) ) ; } return DAG . getNode ( <STR_LIT> , dl , MaskVT , &


<s> if ( assoc == <NUM_LIT> ) assoc = <NUM_LIT> ; else if ( assoc == <NUM_LIT> ) assoc = <NUM_LIT> ; else if ( assoc >= <NUM_LIT> && assoc <= <NUM_LIT> ) assoc = <NUM_LIT> + ( assoc - <NUM_LIT> ) * <NUM_LIT> ; else if ( assoc >= <NUM_LIT> && assoc <= <NUM_LIT> ) assoc = <NUM_LIT> + ( assoc - <NUM_LIT> ) * <NUM_LIT> ; level2 -> assoc


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedScatterBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Type * Ty = Input -> getType ( ) ; if ( ! ( Ty -> getVectorNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder


<s> return new <ISA_LIT>CTRLoopsVerify ( )


<s> intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += <NUM_LIT>


<s> SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; } SDValue VecCstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) , DL , VecFloatVT ) ; SDValue HighBitcast = DAG . getBitcast ( VecFloatVT , High ) ; SDValue LowBitcast = DAG . getBitcast ( VecFloatVT , Low ) ; if ( IsStrict ) { SDValue FHigh = DAG . getNode ( <STR_LIT> , DL , { VecFloatVT , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , HighBitcast , VecCstFAdd } ) ; return DAG . getNode ( <STR_LIT> , DL , { VecFloatVT , <STR_LIT> } , { FHigh . getValue ( <NUM_LIT> ) , LowBitcast , FHigh } ) ; } SDValue FHigh = DAG . getNode ( <STR_LIT> , DL , VecFloatVT , HighBitcast , VecCstFAdd ) ; return DAG . getNode ( <STR_LIT> , DL , VecFloatVT , LowBitcast ,


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand (


<s> if ( GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , x ) || reg_mentioned_p ( arg_pointer_rtx , x ) || reg_mentioned_p ( virtual_incoming_args_rtx , x ) || reg_mentioned_p ( virtual_outgoing_args_rtx , x ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , x ) || reg_mentioned_p ( virtual_stack_vars_rtx , x ) ) ) return <NUM_LIT> ; else if ( thumb1_base_register_rtx_p ( x , mode , strict_p ) ) return <NUM_LIT> ; else if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONSTANT_P ( x ) && GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! flag_pic ) return <NUM_LIT> ; else if ( ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> || mode == HFmode ) && reload_completed && ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( x ) == POST_INC && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && thumb1_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ) return <NUM_LIT> ; else if ( GET_CODE ( x ) == PLUS ) { if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && XEXP ( x , <NUM_LIT> ) != frame_pointer_rtx && XEXP ( x , <NUM_LIT> ) != frame_pointer_rtx && thumb1_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && ( thumb1_index_register_rtx_p

( XEXP ( x , <NUM_LIT> ) , strict_p ) || ( ! strict_p && will_be_in_index_register ( XEXP ( x , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ;


<s> virtual void markPhysRegUsed ( unsigned PhysReg ) override { MIB . addDef ( PhysReg , RegState


<s> void <ISA_LIT>TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MF . getFrameInfo ( ) . computeMaxCallFrameSize


<s> m_MultipartList [ m_CurrentGOTPart ] . consumeTLS ( pType ) ; return m_MultipartList [ m_CurrentGOTPart


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2


<s> if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNum ) && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNum ) ) IsVector = false ; if ( Layout . size ( ) == <NUM_LIT> )