<s> auto Cst = MIB . buildConstant ( MRI . cloneVirtualRegister ( RHS . getReg ( ) ) , MatchInfo . first ) ; Observer . changingInstr ( MI ) ; RHS . setReg ( Cst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( MatchInfo . second ) ; Observer . changedInstr ( MI ) ; return true


<s> void printi64mem ( const MCInst * MI , unsigned OpNo


<s> MachineInstr * MI = MBBI ; MachineInstr * NewMI ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( Dest ) . addOperand ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; MMO = LD -> getMemOperand ( ) ; if ( MMO -> getSize ( ) < <NUM_LIT> ) return SDValue ( ) ; break ; } case <STR_LIT> : { MemIntrinsicSDNode * Intrin = cast < MemIntrinsicSDNode > ( N ) ; Chain = Intrin -> getChain ( ) ; Base = Intrin -> getOperand ( <NUM_LIT> ) ; MMO = Intrin -> getMemOperand ( ) ; break ; } } MVT VecTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue LoadOps [ ] = { Chain , Base } ; SDValue Load = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VecTy , <STR_LIT> ) , LoadOps , VecTy , MMO ) ; DCI . AddToWorklist ( Load . getNode ( ) ) ; Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Swap = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VecTy , <STR_LIT> ) , Chain , Load ) ; DCI . AddToWorklist ( Swap . getNode ( )


<s> return ( __m64 ) __builtin_ia32_pminsw ( ( __v4hi )


<s> if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; const unsigned TlsOffset = <NUM_LIT> ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = <STR_LIT> (


<s> unsigned InOpcode = InVec . getOpcode ( ) ; if ( OpVT == <STR_LIT> && InVec . getValueType ( ) == <STR_LIT> ) { if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } } if ( ( InOpcode == <STR_LIT> || InOpcode == <STR_LIT> ) && OpVT . is128BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . is128BitVector ( ) ) { unsigned ExtOp = InOpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ExtOp , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } } return SDValue (


<s> case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_H44 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_M44 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_L44 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HH : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HM : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PC22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PC10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT13 : closeParen = false ; break ; case VK_<ISA_LIT>_13 : closeParen = false ; break ; case VK_<ISA_LIT>_WPLT30 : closeParen = false ; break ; case VK_Sparc_R_DI<ISA_LIT>32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_HIX22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_LOX10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LO10 : OS <<


<s> return ( __m128i ) __builtin_ia32_pmuludq128_mask ( ( __v4si ) __X , ( __v4si )


<s> } ) ; } ; auto CanBeUsedForAllClasses = [ & RequiredClasses , TRI ] ( MCPhysReg PR ) { return all_of ( RequiredClasses , [ PR , TRI ] ( const TargetRegisterClass * C ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ C , TRI ] ( MCPhysReg SubOrSuper ) { return C == TRI -> getMinimalPhysRegClass ( SubOrSuper ) ; } ) ; } ) ; } ; auto * RegClass = TRI -> getMinimalPhysRegClass ( Reg ) ; for ( const MCPhysReg & PR : * RegClass ) { if ( DefinedInBB . available ( PR ) && UsedInBetween . available ( PR ) && ! RegInfo . isReserved ( PR ) && ! AnySubOrSuperRegCalleePreserved ( PR ) && CanBeUsedForAllClasses ( PR ) ) { DefinedInBB . addReg ( PR ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( PR , TRI ) << <STR_LIT> ) ; return { PR }


<s> getThumbAddrModeRegRegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & , const MCSubtargetInfo & STI ) const { const MCOperand & MO1 = MI . getOperand ( OpIdx ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; unsigned Rm = CTX . getRegisterInfo ( ) ->


<s> static void EmitGuardLoadOrStoreTst ( const MCSubtargetInfo & STI , int I , MCInst Saved [ ] , MCStreamer & Out ) { assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( false ) ; EmitTST ( STI , Out , Reg ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ; Out . EmitBundleUnlock (


<s> switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( PostRA ) return false ; bool Changed = false ; unsigned DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Comparand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t SExtComparand = ( ( uint64_t ) Comparand & ~ <NUM_LIT> ) != <NUM_LIT> ? ( Comparand | <NUM_LIT> ) : Comparand ; for ( auto & CompareUseMI : MRI -> use_instructions ( DefReg ) ) { unsigned UseOpc = CompareUseMI . getOpcode ( ) ; if ( UseOpc != <STR_LIT> && UseOpc != <STR_LIT> ) continue ; unsigned CRSubReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned TrueReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegToCopy = selectReg ( SExtImm , SExtComparand , Opc , TrueReg , FalseReg , CRSubReg ) ; if ( RegToCopy == <STR_LIT> ) continue ; if ( RegToCopy == <STR_LIT> || RegToCopy == <STR_LIT> ) { CompareUseMI . setDesc ( get ( UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; CompareUseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ; MI . dump ( ) ; CompareUseMI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; CompareUseMI . setDesc ( get ( <STR_LIT> ) ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( RegToCopy == TrueReg ? <NUM_LIT> : <NUM_LIT> ) ; CmpIselsConverted ++ ; Changed = true ; LLVM_DEBUG ( CompareUseMI . dump ( ) ) ; } if ( Changed ) return true ; MissedConvertibleImmediateInstrs ++ ; return false ; } case <STR_LIT> : case <STR_LIT> : { int64_t Addend = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Addend + SExtImm ) ) { ReplaceWithLI = true ; Is64BitLI = Opc == <STR_LIT> ; NewImm = Addend + SExtImm ; break ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t SH = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t MB = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; APInt InVal ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , SExtImm , true ) ; InVal = InVal .


<s> unsigned <ISA_LIT>BranchRelaxation :: insertUnconditionalBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , const DebugLoc


<s> Instruction & Inst = * I ; if ( const ReturnInst * RI = dyn_cast < ReturnInst > ( I ) ) { Value * RVal = RI -> getReturnValue ( ) ; if ( ! RVal ) continue ; Type * T = RVal -> getType ( ) ; FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeSet A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , NULL ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { if ( Subtarget . getRelocationModel ( ) != Reloc :: PIC_ ) { Function * F_ = CI -> getCalledFunction ( ) ; if ( F_ && ! isIntrinsicInline ( F_ ) && needsFPHelperFromSig (


<s> parms . regbase = regbase ; parms . stack = <NUM_LIT> ; parms . nregs = <NUM_LIT> ; parms . intoffset = <NUM_LIT> ; function_arg_record_value_1 ( type , <NUM_LIT> , & parms , false ) ; if ( parms . intoffset != - <NUM_LIT> ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms . intoffset & - BITS_PER_WORD ; endbit = ( typesize * BITS_PER_UNIT + BITS_PER_WORD - <NUM_LIT> ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = slotno + parms . intoffset / BITS_PER_WORD ; if ( intslots > <NUM_LIT> && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( <NUM_LIT> , SPARC_INT_ARG_MAX - this_slotno ) ; parms . stack = <NUM_LIT> ; } parms . nregs += intslots ; } nregs = parms . nregs ; if ( nregs == <NUM_LIT> ) { if ( typesize <= <NUM_LIT> ) { return gen_rtx_REG ( mode , regbase ) ; } else { nregs = ( typesize + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; } if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs != <NUM_LIT> ) ; parms . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( parms . stack + nregs ) ) ; if ( parms . stack ) XVECEXP ( parms . ret , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; parms . nregs


<s> case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI . killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue


<s> if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget -> hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( AlignVT , Lo ) ; Hi = DAG . getBitcast ( AlignVT , Hi ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , AlignVT , Lo , Hi , DAG . getConstant ( Rotation * Scale , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - Rotation * Scale ; int HiByteShift = Rotation * Scale ; Lo = DAG . getBitcast ( <STR_LIT> ,


<s> _Unwind_VRS_Result _Unwind_VRS_Get ( _Unwind_Context * context , _Unwind_VRS_RegClass regclass , _uw regno , _Unwind_VRS_DataRepresentation representation , void * valuep ) { phase1_vrs * vrs = ( phase1_vrs * ) context ; switch ( regclass ) { case _UVRSC_CORE : if ( representation != _UVRSD_UINT32 || regno > <NUM_LIT> ) return _UVRSR_FAILED ; * ( _uw * ) valuep = vrs -> core . r [ regno ] ; return _UVRSR_OK ; case _UVRSC_VFP : case _UVRSC_FPA : case _UVRSC_WMMXD


<s> assert ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc ::

PIC_ && Subtarget -> isPICStyleGOT ( ) ) ;


<s> else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) emitGlobalAddressUnaligned ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , <NUM_LIT> ) ; else if ( MI . getOpcode ( ) == <STR_LIT> ) emitGlobalAddressUnaligned ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , <NUM_LIT> ) ; else emitGlobalAddress ( MO . getGlobal ( ) , getRelocation


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_EVENT_CALL ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( CurSled ) ; OutStreamer -> emitBinaryData ( <STR_LIT> ) ; const Register DestRegs [ ] = { <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( SrcRegs [ I ] != DestRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) )


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N


<s> const <ISA_LIT>GNULDBackend & getTarget ( ) const { return m_Target


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , DL , <STR_LIT> ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) ; if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) , V1 ) ; return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; } if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2

, Mask , Subtarget , DAG ) ) return Result ;


<s> } else if ( RegSpc == SingleHighTSpc ) { D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg


<s> target = gen_lowpart ( GET_MODE ( cmp_operands [ <NUM_LIT> ] ) , target ) ; if ( code == EQ || code == NE ) { rtx zie = mips_zero_if_equal ( cmp_operands [ <NUM_LIT> ] , cmp_operands [ <NUM_LIT> ] ) ; mips_emit_binary ( code , target , zie , const0_rtx ) ; } else mips_emit_int_relational ( code , <NUM_LIT> , target , cmp_operands [


<s> if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; if ( ! IsZExt ) { Op0 = emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; if ( ! Op0 ) return <NUM_LIT> ; SrcVT = RetVT ; SrcBits = SrcVT . getSizeInBits ( ) ; IsZExt = true ; } unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { Register TmpReg = MRI . createVirtualRegister (


<s> ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue = DAG . getLoad ( LocVT , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> ,


<s> HOST_WIDE_INT bitpos = INTVAL ( operands [ <NUM_LIT> ] ) ; rtx dst = operands [ <NUM_LIT> ] ; rtx src = operands [ <NUM_LIT> ] ; if ( MEM_P ( dst ) && width == <NUM_LIT> && ( bitpos % BITS_PER_UNIT ) == <NUM_LIT> && GET_MODE_BITSIZE ( GET_MODE ( src ) ) == width ) { rtx newmem = adjust_address ( dst , GET_MODE ( src ) , bitpos / BITS_PER_UNIT ) ; rtx base_addr = force_reg ( Pmode , XEXP ( newmem , <NUM_LIT> ) ) ; emit_insn ( gen_unaligned_storesi ( base_addr , src ) ) ; return EXPAND_DONE


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , <STR_LIT> , & rs6000_opt_masks

[ <NUM_LIT> ] , ARRAY_SIZE ( rs6000_opt_masks ) ) ;


<s> void onGT ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State =


<s> enum { N = <NUM_LIT> , Z = <NUM_LIT> , C = <NUM_LIT> , V = <NUM_LIT> } ; switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return Z ; case NE : return <NUM_LIT> ; case HS : return C ; case LO : return <NUM_LIT> ; case MI : return N ; case PL : return <NUM_LIT> ; case VS : return V ; case VC : return <NUM_LIT> ; case HI : return


<s> assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; assert ( Largest + <NUM_LIT> < <NUM_LIT> ) ; result . push_back ( { Largest + <NUM_LIT> , LegalizerInfo :: Unsupported } ) ; result . push_back ( { <NUM_LIT> ,


<s> SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) ) return false ; return


<s> const <ISA_LIT>ABIInfo & getABI ( ) const { return ABI


<s> length = pa_attr_length_millicode_call ( insn ) + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) length += compute_movmem_length ( insn ) - <NUM_LIT> ; else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ==

const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) length += compute_clrmem_length ( insn ) - <NUM_LIT> ;


<s> if ( ! UCB_FORCED_STOP_FN ( ucbp ) ) return __gnu_Unwind_RaiseException ( ucbp , entry_vrs ) ; entry_vrs -> core . r [ R_PC ] = entry_vrs -> core . r [ R_LR ] ; return unwind_phase2_forced ( ucbp ,


<s> } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode


<s> else if ( TARGET_DIVIDE_CALL_TABLE ) sh_divsi3_libfunc = <STR_LIT> ; else sh_divsi3_libfunc = <STR_LIT> ; if ( sh_branch_cost == - <NUM_LIT> ) { sh_branch_cost = <NUM_LIT> ; } if ( ! global_options_set . x_TARGET_ZDCBRANCH && TARGET_HARD_SH4 ) TARGET_ZDCBRANCH = <NUM_LIT> ; if ( TARGET_FDPIC && ! flag_pic ) flag_pic = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! VALID_REGISTER_P ( regno ) ) sh_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; for ( regno = <NUM_LIT> ; regno < ADDREGNAMES_SIZE ; regno ++ ) if ( ! VALID_REGISTER_P ( ADDREGNAMES_REGNO ( regno ) ) ) sh_additional_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; if ( flag_pic && ! TARGET_PREFERGOT ) flag_no_function_cse = <NUM_LIT> ; if ( targetm . small_register_classes_for_mode_p ( VOIDmode ) ) { if ( ! TARGET_HARD_SH4 || flag_pic ) flag_schedule_insns = <NUM_LIT> ; else if ( flag_exceptions ) { if ( flag_schedule_insns && global_options_set . x_flag_schedule_insns ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; flag_schedule_insns = <NUM_LIT> ; } else if ( flag_schedule_insns && ! global_options_set . x_flag_schedule_insns ) flag_schedule_insns = <NUM_LIT> ; } if ( ( flag_unwind_tables || flag_asynchronous_unwind_tables || flag_exceptions || flag_non_call_exceptions ) && flag_omit_frame_pointer && ! TARGET_ACCUMULATE_OUTGOING_ARGS ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; TARGET_ACCUMULATE_OUTGOING_ARGS = <NUM_LIT> ; } if ( flag_unsafe_math_optimizations )


<s> if ( MI -> getOperand ( <STR_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <STR_LIT> ) . getReg ( ) ; } return


<s> <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( * Def0 , * Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 . getOperand ( i ) ; const MachineOperand & MO1 = MI1 . getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; } return true


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , dl , MaskVT ) ; else { MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType ( ) . getSizeInBits ( ) ) ; MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , MaskInReg , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; return SDValue ( Res , <NUM_LIT> )


<s> scalar_int_mode libval_mode = smallest_int_mode_for_size ( <NUM_LIT> * GET_MODE_BITSIZE ( mode ) ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , op0 , mode , op1 , mode ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , <NUM_LIT> ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p =


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) { if ( RegInfo -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; if ( CSSize != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( IsLP64 ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; } else { unsigned Opc = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , IsLP64 , UseLEA , TII , * RegInfo ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { bool isMem = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; int MaxTCDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int Offset = <NUM_LIT> ; assert ( MaxTCDelta <= <NUM_LIT> && <STR_LIT> ) ; Offset = StackAdj - MaxTCDelta ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if ( Offset ) { Offset += mergeSPUpdates ( MBB , MBBI , StackPtr , true ) ; emitSPUpdate ( MBB , MBBI , StackPtr , Offset , Is64Bit , IsLP64


<s> } ; SDValue MulOp , OtherOp ; if ( UsePMADDWD ( Op0 ) ) { MulOp = Op0 ; OtherOp = Op1 ; } else if ( UsePMADDWD ( Op1 ) ) { MulOp = Op1 ; OtherOp = Op0 ; } else return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT OpVT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , OpVT , Ops ) ; } ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , Madd .


<s> } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; assert ( StoredVal . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal , DAG . getUNDEF ( <STR_LIT> ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( )

, St -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; bool CloseParen = false ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) O << <STR_LIT> << LowercaseString ( RI . get ( MO . getReg ( ) ) . AsmName ) ; else O << <STR_LIT> << MO . getReg ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( )


<s> const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitGPRel64Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( )


<s> if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT


<s> MCELFStreamer :: EmitValueImpl ( Value ,


<s> return ( __m256i ) __builtin_ia32_pbroadcastw256 ( (


<s> MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugInstr ( ) ) ++ NextMBBI ; if ( NextMBBI == EndMBBI ) return EndMBBI ; Offset = isIncrementOrDecrement ( * NextMBBI , Reg , Pred , PredReg ) ; return Offset == <NUM_LIT> ?


<s> if ( vmode != op_mode ) return false ; if ( ! TARGET_VIS2 ) return false ; if ( ! target ) return GET_MODE_SIZE ( vmode ) == <NUM_LIT> ; if ( vmode != V8QImode ) return false ; rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; op1 = force_reg ( vmode , op1 ) ; unsigned int i , mask


<s> if ( VT . getSizeInBits ( ) >= RegisterVT . getSizeInBits ( ) ) return CCValAssign :: LocInfo :: Full ; if ( Flags . isSExt ( ) ) return CCValAssign :: LocInfo :: SExt ; if ( Flags . isZExt ( ) ) return CCValAssign ::


<s> static bool isVINSERTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getScalarSizeInBits (


<s> return ( ( AM2Opc >> <NUM_LIT> ) & <NUM_LIT> ) ?


<s> for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = & <STR_LIT> ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F ->


<s> Value * <ISA_LIT>IREmitter :: visitVQSHRNs ( const SDNode * N


<s> int I = <NUM_LIT> ; while ( E > <NUM_LIT> ) { int ZI = <NUM_LIT> ; if ( E % <NUM_LIT> == <NUM_LIT> ) { ZI = <NUM_LIT> - ( E % <NUM_LIT> ) ; if ( ZI != <NUM_LIT> ) ++ NonzeroEntries ; } SignedDigit [ I ] = S * ZI ; if ( SignedDigit [ I ] == <NUM_LIT> ) HighestOne = I ; E = ( E - ZI ) / <NUM_LIT> ; ++ I ; } int32_t InstrRequired = <NUM_LIT> * NonzeroEntries - <NUM_LIT> ; if ( std :: abs ( MulAmt ) % <NUM_LIT> == <NUM_LIT> ) -- InstrRequired ; if ( InstrRequired > <ISA_LIT>LowerConstantMulThreshold ) return SDValue ( ) ; SDValue Res ; SDLoc DL ( Op ) ; SDValue V = Op -> getOperand ( <NUM_LIT> ) ; if ( HighestOne == - <NUM_LIT> ) Res = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; else { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( HighestOne , DL , <STR_LIT> ) ) ; SignedDigit [ HighestOne ] = <NUM_LIT> ; } for ( unsigned int I = <NUM_LIT> ; I < sizeof ( SignedDigit ) / sizeof ( SignedDigit [ <NUM_LIT> ] ) ; ++ I ) { if ( SignedDigit [ I ]


<s> return hasSSE1 ( ) || ( hasPRFCHW ( ) && ! hasThreeDNow ( ) )


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex


<s> void <ISA_LIT>GNUInfo :: setABIVersion ( uint8_t ver ) { m_ABIVersion =


<s> return __builtin_mve_vhcaddq_rot90_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __b ,


<s> uint32_t j2 = ( pOffset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t j1 = ( pOffset & <NUM_LIT> ) >>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> for ( const auto & BB : L -> blocks ( ) ) for ( auto & J : * BB ) { Value * PtrValue ; Type * PointerElementType ; if ( LoadInst * LMemI = dyn_cast < LoadInst > ( & J ) ) { PtrValue = LMemI -> getPointerOperand ( ) ; PointerElementType = LMemI -> getType ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( & J ) ) { PtrValue = SMemI -> getPointerOperand ( ) ; PointerElementType = SMemI -> getValueOperand ( ) -> getType ( ) ; } else if ( IntrinsicInst * IMemI = dyn_cast < IntrinsicInst > ( & J ) ) { PointerElementType = Type :: getInt8Ty ( J . getContext ( ) ) ; if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> || IMemI -> getIntrinsicID ( ) == <STR_LIT> ) { PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } else if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> ) { PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } else continue


<s> Int64Cmp = false ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { SignedCmp = true ; Int64Cmp = true ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { SignedCmp = false ; Int64Cmp =


<s> MachineInstr * PrevMI = nullptr ; for ( unsigned i = <NUM_LIT> , e = DstSize / EltSize + <NUM_LIT> ; i < e ; ++ i ) { PrevMI = & * emitLaneInsert ( None , DstVec , I . getOperand ( i ) . getReg ( ) , i - <NUM_LIT> , RB , MIRBuilder ) ; DstVec = PrevMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( DstSize < <NUM_LIT> ) { const TargetRegisterClass * RC = getMinClassForRegBank ( * RBI . getRegBank ( DstVec , MRI , TRI ) , DstSize ) ; if ( ! RC ) return false ; if ( RC != & <STR_LIT> && RC != & <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SubReg = <NUM_LIT> ; if ( ! getSubRegForClass ( RC , TRI , SubReg ) ) return false ; if ( SubReg != <STR_LIT> && SubReg != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << DstSize << <STR_LIT> ) ; return false ; } Register Reg = MRI . createVirtualRegister ( RC ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MIRBuilder . buildInstr ( TargetOpcode :: COPY , { DstReg } , { } ) . addReg ( DstVec , <NUM_LIT> , SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( Reg ) ; RBI . constrainGenericRegister ( DstReg , * RC


<s> HOST_WIDE_INT offset1 , offset2 ; if ( ! MEM_P ( mem1 ) || ! MEM_P ( mem2 ) ) return false ; mips_split_plus ( XEXP ( mem1 , <NUM_LIT> ) , & base1 , & offset1 ) ; mips_split_plus ( XEXP ( mem2 , <NUM_LIT> ) , & base2 , & offset2 ) ; if ( ! REG_P ( base1 ) || ! rtx_equal_p ( base1 , base2 ) ) return false ; if ( load_p && REGNO ( first_reg ) == REGNO ( base1 ) ) return false ; if ( load_p && swap_p && REGNO ( first_reg ) + <NUM_LIT> == REGNO ( base1 ) ) return false ; if ( offset2 != offset1 + <NUM_LIT> ) return false ; if ( ! UMIPS_12BIT_OFFSET_P ( offset1 )


<s> inline vector unsigned short vec_vavguh ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned short ) __builtin_altivec_vavguh ( ( vector signed short ) a1 ,


<s> PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; AbsoluteDebugSectionOffsets = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; if ( ! is64Bit ) ExceptionsType = ExceptionHandling :: Dwarf ; AbsoluteEHSectionOffsets = false ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : <NUM_LIT> ; HasLCOMMDirective = true ; AssemblerDialect = <NUM_LIT>


<s> return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv2di (


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsTbx = true ; Layout = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsTbx = false ; Layout = <STR_LIT>


<s> MachineOperand & StackOffsetOperand = getMemOpBaseRegImmOfsOffsetOperand ( MI ) ; assert ( StackOffsetOperand . isImm ( ) && <STR_LIT> ) ; getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ; assert ( Scale != <NUM_LIT> && <STR_LIT> ) ; int64_t NewImm = ( Offset + <NUM_LIT> ) / Scale ; StackOffsetOperand . setImm (


<s> unsigned Opcode = Node -> getOpcode ( ) ; DebugLoc DL = Node -> getDebugLoc ( ) ; EVT NodeTy = Node -> getValueType ( <NUM_LIT> ) ; unsigned MultOpc ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) , CmpLHS ; unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops , <NUM_LIT> ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; SDNode * Result = CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return std :: make_pair ( true , Result ) ; } case <STR_LIT>


<s> else if ( gasm * gs = dyn_cast < gasm * > ( stmt ) ) { unsigned ninputs = gimple_asm_ninputs ( gs ) ; for ( unsigned i = <NUM_LIT> ; i < ninputs ; i ++ ) { tree op = gimple_asm_input_op ( gs , i ) ; tree val = TREE_VALUE ( op ) ; tree type = TREE_TYPE ( val ) ; if ( check_and_error_invalid_use ( type ) ) return true ; } unsigned noutputs = gimple_asm_noutputs ( gs ) ; for ( unsigned i = <NUM_LIT> ; i < noutputs ; i ++ ) { tree op = gimple_asm_output_op ( gs , i ) ; tree val = TREE_VALUE ( op ) ; tree type = TREE_TYPE ( val ) ; if ( check_and_error_invalid_use ( type ) ) return true ; } } else if ( gcall * gc = dyn_cast < gcall * >


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


<s> if ( STI -> hasV8_1MMainlineOps ( ) ) CMSESaveClearFPRegsV81


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC


<s> bool <ISA_LIT>SEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func -> hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag


<s> case <ISA_LIT>MCExpr :: MEK_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_HI


<s> } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , dl , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> __rv . __o = __builtin_neon_vld3v16qi ( ( const __builtin_neon_qi * ) __a ) ; return __rv .


<s> bool isABI_N32 ( ) const { return STI . getFeatureBits ( ) &


<s> static DecodeStatus DecodeVST3LN ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = CLI . OutVals [ VA . getValNo ( ) ] ; MVT ArgVT = OutVTs [ VA . getValNo ( ) ] ; unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt


<s> const InstType & getRecordedTypeForInstr ( const MachineInstr * MI ) const { assert ( wasVisited ( MI ) && <STR_LIT>


<s> return ( __m64 ) __builtin_arm_wsllw ( ( __v2si )


<s> if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot


<s> PM -> add ( create<ISA_LIT>ISelDag (


<s> bool is64Bit = Triple . getArch ( ) == Triple :: x86_64 ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString =


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ) ; return ; } O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O <<


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { const Triple & TheTriple = STI


<s> bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != ( <NUM_LIT> << <NUM_LIT> ) ) return None ; else if ( isDSPControlWrite ) { return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI


<s> assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill (


<s> if ( vzeroupper_operation ( pat , VOIDmode ) || vzeroall_operation ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_reg256_found = false ; note_stores ( pat , ix86_check_avx256_stores , & avx_reg256_found ) ; return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return


<s> int Opc = MI -> getOpcode ( ) ; return Opc != getTransformOpcode ( Opc


<s> if ( prologue ) fputs ( <STR_LIT> , f ) ; else fputs ( <STR_LIT> ,


<s> static DecodeStatus DecodeVecShiftR16Imm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm ,


<s> bool LowOverheadLoop :: ValidateMVEInst ( MachineInstr * MI ) { if ( CannotTailPredicate ) return false ; if ( ! shouldInspect ( * MI ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return false ; } if ( isVCTP ( MI ) && ! AddVCTP ( MI ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; bool IsUse = false ; unsigned LastOpIdx = MI -> getNumOperands ( ) - <NUM_LIT> ; for ( auto & Op : enumerate ( reverse ( MCID . operands ( ) ) ) ) { const MachineOperand & MO = MI -> getOperand ( LastOpIdx - Op . index ( ) ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( <STR_LIT> ( Op . value ( ) . OperandType


<s> static inline DecodeStatus DecodeMVE_MEM_pre ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder , unsigned Rn , OperandDecoder RnDecoder , OperandDecoder AddrDecoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Qd = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) <<


<s> if ( Caller . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> ) return false ; if ( ! Outs . empty ( ) && Caller . hasStructRetAttr ( ) != Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ) return false ; for ( auto & Arg : Outs ) if ( Arg . Flags .


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_TAIL_CALL ( const


<s> bool aarch64_sve_cnt_immediate_p ( rtx x ) { poly_int64 value ; return poly_int_rtx_p ( x , & value ) && aarch64_sve_cnt_immediate_p ( value


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn >> <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( pending_data_specs >= <NUM_LIT> && ( TODO_SPEC ( insn ) & BEGIN_DATA ) ) return ready_index == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ; if ( ready_index == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ! reload_completed || ! safe_group_barrier_needed ( insn ) ) && ( ! mflag_sched_mem_insns_hard_limit || ! is_load_p ( insn ) || mem_ops_in_group [ current_cycle % <NUM_LIT>

] < ia64_max_memory_insns ) ) return <NUM_LIT> ;


<s> return ( ( qword ) ( vec_sll ( ( vec_uchar16


<s> SDValue VecIn2 ; SmallVector < unsigned , <NUM_LIT> > InsertIndices ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Opc = Op . getOperand ( i ) . getOpcode ( ) ; if ( Opc == <STR_LIT> ) continue ; if ( Opc != <STR_LIT> ) { if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; if ( VecIn1 . getNode ( ) == <NUM_LIT> ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( VecIn2 . getNode ( ) == <NUM_LIT> ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return


<s> Type * ScalarTy = SrcVTy -> getScalarType ( ) ; unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnes ( VF ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; InstructionCost MaskUnpackCost = <NUM_LIT> ; if ( VariableMask ) { auto * MaskTy = FixedVectorType :: get ( Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , VF ) ; MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; InstructionCost ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; InstructionCost BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } InstructionCost AddressUnpackCost = getScalarizationOverhead ( FixedVectorType :: get ( ScalarTy -> getPointerTo ( )

, VF ) , DemandedElts , false , true ) ;


<s> } break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ConstantPoolIndex


<s> LEAInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEAInst . addOperand ( MCOperand :: CreateExpr ( RetTargetExpr ) ) ; LEAInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Out . EmitInstruction ( LEAInst , STI ) ; MCInst PUSHInst ; PUSHInst . setOpcode ( <STR_LIT> ) ; PUSHInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Out . EmitInstruction ( PUSHInst , STI ) ; } else { MCInst


<s> Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG ,


<s> bool isSVEVectorIndexB ( ) const { return Kind == k_VectorIndex && VectorIndex .


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT>


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue CondRes = CreateFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand


<s> void LLVMInitialize<ISA_LIT>AsmLexer ( ) { RegisterAsmLexer < <ISA_LIT>AsmLexer > X ( The<ISA_LIT>Target ) ; RegisterAsmLexer < ThumbAsmLexer > Y


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; unsigned StackOffset = MI . getOperand ( <NUM_LIT> )


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } MFI -> setAdjustsStack ( true ) ; SDValue Flag = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , dl , ReturnReg , PtrVT ,


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; int D8SpillFI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) if ( CSI [ i ] . getReg ( ) == <STR_LIT> ) { D8SpillFI = CSI [ i ] . getFrameIdx ( ) ; break ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -=


<s> const BasicBlockInfo & BBI = BBInfo [ U . MI -> getParent ( ) -> getNumber ( ) ] ; unsigned KnownBits = BBI . internalKnownBits


<s> machine_mode mode = GET_MODE ( in ) ; int i ; if ( TARGET_SSE4_1 && mode == V8HImode && fn == gen_uminv8hi3 ) { emit_insn ( gen_sse4_1_phminposuw ( dest , in ) ) ; return ; } for ( i = GET_MODE_BITSIZE ( mode ) ; i > GET_MODE_UNIT_BITSIZE ( mode ) ; i >>= <NUM_LIT> ) { half = gen_reg_rtx ( mode ) ; emit_reduc_half ( half , vec , i ) ; if ( i == GET_MODE_UNIT_BITSIZE ( mode ) * <NUM_LIT> ) dst = dest ; else dst = gen_reg_rtx ( mode ) ; emit_insn ( fn ( dst , half , vec ) ) ; vec =


<s> case 'f' : switch_to_section ( farbss_section ) ; sec = <STR_LIT> ; break ; } if ( sec ) { const char * name2 ; int p2align = <NUM_LIT> ; while ( align > BITS_PER_UNIT ) { align /= <NUM_LIT> ; p2align ++ ; } name2 = targetm . strip_name_encoding ( name ) ; if ( global ) fprintf ( stream , <STR_LIT> , name2 ) ; fprintf ( stream , <STR_LIT> , p2align ) ; fprintf ( stream , <STR_LIT> , name2 ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; return ; } } if ( ! global ) { fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name


<s> SDLoc DL ( N ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ( ImmVal & <NUM_LIT> ) == <NUM_LIT> ) && ( ImmVal >= - <NUM_LIT> ) && ( ImmVal <= <NUM_LIT> ) ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( ImmVal / <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL ,


<s> static inline unsigned getMBit ( uint32_t insn ) { return ( insn >> <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else


<s> SDValue <ISA_LIT>TargetLowering :: LowerAsmOutputForConstraint ( SDValue & Chain , SDValue & Flag , SDLoc DL , const AsmOperandInfo & OpInfo , SelectionDAG & DAG ) const { <STR_LIT> Cond = parseConstraintCode ( OpInfo . ConstraintCode ) ; if ( Cond == <STR_LIT> ) return SDValue ( ) ; if ( OpInfo . ConstraintVT . isVector ( ) || ! OpInfo . ConstraintVT . isInteger ( ) || OpInfo . ConstraintVT . getSizeInBits ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Flag . getNode ( ) ) { Flag = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Flag ) ; Chain = Flag . getValue (


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( VT . is512BitVector ( ) || SVT . getVectorElementType ( ) == <STR_LIT> ) return LowerZERO_EXTEND_AVX512


<s> rtx_insn * c_insn = BB_HEAD ( bb ) ; if ( ! NONDEBUG_INSN_P ( c_insn ) ) c_insn = next_nonnote_nondebug_insn ( c_insn ) ; if ( c_insn && NONJUMP_INSN_P ( c_insn ) ) { rtx pat = PATTERN ( c_insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { rtx vec = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( vec ) == SET && XINT ( XEXP ( vec , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_SET_GOT && REGNO ( XEXP

( vec , <NUM_LIT> ) ) == REGNO ( reg ) ) delete_insn ( c_insn ) ;


<s> case IES_MINUS : case IES_NOT : case IES_INIT : case IES_LBRAC : MemExpr = true ; State = IES_INTEGER ; Sym = SymRef ; SymName = SymRefName ; IC . pushOperand ( IC_IMM ) ; if ( ParsingInlineAsm ) Info = IDInfo ; break ; } if ( HasSymbol )


<s> return ( TargetTriple . getEnvironment ( ) != Triple ::

ELF && TargetTriple . isOSBinFormatCOFF ( ) ) ;


<s> void addRegVSRpRCOperands ( MCInst & Inst


<s> } return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV8 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : case Match_AlignedMemoryRequires64 : case Match_DupAlignedMemoryRequires64 : case Match_AlignedMemoryRequires64or128 : case Match_DupAlignedMemoryRequires64or128 : case Match_AlignedMemoryRequires64or128or256 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getAlignmentLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; switch ( MatchResult ) { default : llvm_unreachable (


<s> Value * <ISA_LIT>IREmitter :: visitVLD2DUP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> static bool shouldGuaranteeTCO ( CallingConv :: ID CC , bool


<s> SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( VT

. getSizeInBits ( ) , DL , <STR_LIT> ) ) ;


<s> SmallVector < Instruction * , <NUM_LIT> > Users ; Instruction * InstTo = dyn_cast < Instruction > ( To ) ; for ( Use & U : From -> uses ( ) ) { auto * User = cast < Instruction > (


<s> SDLoc Loc ( Op ) ; RTLIB :: Libcall LC ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; for ( unsigned Sz = SrcSz ; Sz <= <NUM_LIT> && Sz < DstSz ; Sz *= <NUM_LIT> ) { bool Supported = ( Sz == <NUM_LIT> ? Subtarget -> hasFP16 ( ) : Subtarget -> hasFP64 ( ) ) ; MVT SrcVT = ( Sz == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT DstVT = ( Sz == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( Supported ) { if ( IsStrict ) { SrcVal = DAG . getNode ( <STR_LIT> , Loc , { DstVT , <STR_LIT> } , { Chain , SrcVal } ) ; Chain = SrcVal . getValue ( <NUM_LIT>


<s> if ( CPU . empty ( ) ) CPU = <STR_LIT> ; if ( TuneCPU . empty ( ) ) TuneCPU = <STR_LIT> ; std :: string FullFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple ) ; assert ( ! FullFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = Align ( <NUM_LIT> ) ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ; else if ( Prefer128Bit ) PreferVectorWidth = <NUM_LIT> ; else if ( Prefer256Bit )


<s> return new <ISA_LIT>64Disassembler ( STI , T . createMCRegInfo ( <STR_LIT> )


<s> for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) || ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_DELETED_LABEL ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label


<s> void printi8mem ( const MCInst * MI , unsigned OpNo ) { printMemReference ( MI ,


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes = false ; ExceptionsType = ExceptionHandling :: WinEH ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString =


<s> EVT Ty = Op . getValueType ( ) ; SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , GetGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Tgt , MachinePointerInfo ::

getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch ( access ) { case <STR_LIT>


<s> unsigned Val = <NUM_LIT> ; const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; else Val = MO . getImm ( ) >> <NUM_LIT> ; bool I = ( Val & <NUM_LIT> ) ; bool J1 = ( Val & <NUM_LIT> ) ; bool J2 = ( Val & <NUM_LIT> ) ; if ( I ^ J1 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; if ( I ^ J2 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; return


<s> const TargetRegisterClass * RC = & <STR_LIT> ; Register Result = MRI . createVirtualRegister ( RC ) ; if ( isPositionIndependent ( ) ) { if ( IsCall && ! IsLocal ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Result ) . addExternalSymbol ( <STR_LIT> ) ; } else if ( IsLocal ) { Register Tmp1 = MRI . createVirtualRegister ( RC ) ; Register Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp1 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addExternalSymbol ( Symbol . data ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_LO32 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp1 , getKillRegState ( true ) ) . addImm ( M0 ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Result ) . addReg ( <STR_LIT> ) . addReg ( Tmp2 , getKillRegState ( true ) ) . addExternalSymbol ( Symbol . data ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_HI32 ) ; } else { Register Tmp1 = MRI . createVirtualRegister ( RC ) ; Register Tmp2 = MRI . createVirtualRegister


<s> Pos = Lsb ; Size = Msbd + <NUM_LIT> + <NUM_LIT> ; break ; case <STR_LIT> : Pos = Lsb + <NUM_LIT> ; Size = Msbd + <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MI . setOpcode ( <STR_LIT> ) ; InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Pos ) ) ; MI . addOperand ( MCOperand :: createImm (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT = Op . getValueType ( ) ; assert ( all_of ( Op -> ops ( ) . drop_front ( <NUM_LIT> ) , [ VT ] ( const SDUse & Use ) { return Use . getValueType ( ) == VT ; } ) && <STR_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; if ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) CC = <STR_LIT> ; unsigned I = Op . getNumOperands ( ) - <NUM_LIT> , Cnt = I ; SDValue Res = Op . getOperand ( I ) ; for ( -- I ; Cnt != <NUM_LIT> ; -- Cnt , I = ( -- I == <NUM_LIT> ? ( Op . getNumOperands ( ) - <NUM_LIT> ) : I ) ) { Res = DAG . getSelectCC ( dl , Res , Op . getOperand ( I ) , Res , Op . getOperand ( I ) , CC ) ; } return Res ; } } int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true


<s> bool <ISA_LIT>TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { return


__v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) ==


<s> static SDValue getScalarMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { if ( auto * MaskConst = dyn_cast < ConstantSDNode > ( Mask ) ) if ( MaskConst -> getZExtValue ( ) & <NUM_LIT> ) return Op ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector (


<s> int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) { loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO ( stmt_info ) ; struct loop * loop = LOOP_VINFO_LOOP ( loop_info ) ; unsigned nest_level = loop_depth ( loop ) ; count *= nest_level ; } retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval


<s> SDValue <ISA_LIT>TargetLowering :: LowerSIGN_EXTEND_INREG ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { EVT ExtVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; if ( ExtVT != <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getValueType ( EVT :: getVectorVT ( * DAG . getContext ( ) , ExtVT . getVectorElementType ( )


<s> EVT VT = Op . getValueType ( ) ; if ( ( Subtarget -> hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX ( ) && VT == <STR_LIT> ) ) { RefinementSteps = <NUM_LIT>


<s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs


<s> Value * <ISA_LIT>IREmitter :: visitVSHL ( const SDNode


<s> x = plus_constant ( Pmode , frame_pointer_rtx , offset ) ; x = gen_rtx_MEM ( SImode , x ) ; x = gen_rtx_SET ( VOIDmode , x


<s> bool hasExtendLrw ( ) const { return HasExtendLrw


<s> bool <ISA_LIT>BaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB ,


<s> uint64_t HiMask = ( BlendMask >> <NUM_LIT> ) & <NUM_LIT> ; if ( LoMask == <NUM_LIT> || LoMask == <NUM_LIT> || HiMask == <NUM_LIT> || HiMask == <NUM_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( LoMask , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( HiMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( <STR_LIT> , DL , Lo , Hi , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT> : assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getSelect ( DL , BlendVT , DAG . getBuildVector ( BlendVT , DL , VSELECTMask ) , V1 , V2 ) ) ; } case


<s> unsigned FnSize = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII . getInstSizeInBytes (


<s> if ( ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isXRegisterReserved ( <NUM_LIT> ) ) ) Reg = <NUM_LIT> ; if ( Reg ) return


<s> assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm ) && <STR_LIT> ) ; return Mem .


<s> Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; } Offset = N ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , <NUM_LIT>


<s> static bool DisassembleVFPConv4Frm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRn ( insn , true ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return MCDisassembler


<s> return ( ! TARGET_EXPLICIT_RELOCS && TARGET_USE_GOT && GET_CODE ( x ) == SYMBOL_REF && mips_global_symbol_p ( x


<s> return ( uint32x4_t ) __builtin_aarch64_umaxpv4si ( ( int32x4_t ) a


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , Scale , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc (


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { unsigned Base = i + Imm ; if ( Base >= NumLaneElts ) Base += NumElts -


<s> FunctionPass * llvm :: create<ISA_LIT>LDCleanupPass (


<s> ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == SEG_DEFAULT ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( index && GET_CODE ( index ) == SUBREG ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += <NUM_LIT> ; if ( rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += <NUM_LIT> ; else len += <NUM_LIT> ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len


<s> if ( aarch64_emit_cfi_for_reg_p ( regno ) ) return VNx2DImode ; return VNx16QImode ; case ARM_PCS_TLSDESC : case ARM_PCS_UNKNOWN : break ; } if ( PR_REGNUM_P ( regno ) ) return VNx16BImode ; gcc_unreachable (


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X =


<s> unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . addOperand ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( * MBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ; MI . eraseFromParent ( )


<s> if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) && hasPartialRegUpdate ( MI -> getOpcode ( ) ) ) return <NUM_LIT> ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI -> getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI -> getObjectAlignment ( FrameIndex ) ; if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc =


<s> return ( __m128i ) __builtin_ia32_phaddd128 ( ( __v4si )


<s> static bool isEndChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == std :: numeric_limits < uint64_t > :: max ( ) ) return false ; return isMask_64 (


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg


<s> for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) CalleeSaveRegs . set ( CSRegs [ i ] ) ; BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ; for ( int AvailReg = Available . find_first ( ) ; AvailReg != - <NUM_LIT> ; AvailReg = Available . find_next ( AvailReg ) ) if ( ! CalleeSaveRegs . test ( AvailReg ) ) return AvailReg ; return <STR_LIT>


<s> return ( __m256 ) __builtin_ia32_vfmaddps256_mask ( ( __v8sf ) __A , ( __v8sf )


<s> if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 (

) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag ) ) return MatchOperand_NoMatch ; IFlags |= Flag ; } } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateProcIFlags ( (


<s> static const TargetRegisterClass * getRegClassFromGRPhysReg ( unsigned Reg ) { assert ( Register :: isPhysicalRegister ( Reg ) ) ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; llvm_unreachable ( <STR_LIT>


<s> if ( & vStream == & nulls ( ) ) loggerFn = <NUM_LIT> ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr ,


<s> struct expand_vec_perm_d d ; rtx t1 ; bool ok ; if ( elt != const0_rtx ) elt = force_reg ( GET_MODE_INNER ( vmode ) , elt ) ; if ( REG_P ( elt ) ) elt = gen_lowpart ( DImode , elt ) ; t1 = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case V8QImode


<s> bool isLegalMaskedGatherScatter ( Type * DataType ) const { if ( ! ST -> hasSVE ( ) ) return false ; auto * DataTypeFVTy = dyn_cast <


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> bool selectBDXAddr20Only ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue &


<s> inline vector unsigned char vec_vaddubs ( vector unsigned char a1


<s> void DecodeScalarMoveMask ( MVT VT , bool IsLoad , SmallVectorImpl < int > & Mask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; Mask . push_back


<s> case MCExpr :: SymbolRef : return ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) != MCSymbolRefExpr :: VK_None ) ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; if ( ! isEvaluated ( BE -> getLHS ( ) ) ) return false ; return isEvaluated ( BE -> getRHS ( ) ) ; } case MCExpr :: Unary : return isEvaluated ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) ) ; case MCExpr


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter =


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int StackSize = ( int ) MFI