<s> break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_A6 : dec = & THREEBYTEA6_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_A7 : dec = & THREEBYTEA7_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP8_MAP : dec = & XOP8_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOP9_MAP : dec = & XOP9_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case XOPA_MAP : dec = & XOPA_MAP_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : debug ( <STR_LIT> ) ; return <NUM_LIT> ; case MODRM_ONEENTRY : return modRMTable [ dec -> instructionIDs ] ; case MODRM_SPLITRM : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + <NUM_LIT> ] ; return modRMTable [ dec -> instructionIDs ] ; case MODRM_SPLITREG : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + ( ( modRM & <NUM_LIT> ) >> <NUM_LIT> ) + <NUM_LIT> ] ; return modRMTable [ dec -> instructionIDs + ( ( modRM & <NUM_LIT> ) >> <NUM_LIT> ) ] ; case MODRM_SPLITMISC : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + ( modRM & <NUM_LIT> ) + <NUM_LIT> ] ; return modRMTable [ dec -> instructionIDs + ( ( modRM & <NUM_LIT> ) >> <NUM_LIT> ) ] ; case MODRM_FULL


<s> Register Reg = BuildVecMI -> getOperand ( Lane + <NUM_LIT> ) . getReg ( ) ; MatchInfo = ShuffleVectorPseudo ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) .


<s> static SetOfMachineInstr & getSet ( BlockToSetOfInstrsPerColor & sets , const MachineBasicBlock & MBB , unsigned reg , unsigned nbRegs ) { SetOfMachineInstr * result ; BlockToSetOfInstrsPerColor :: iterator it = sets . find ( & MBB ) ; if ( it != sets . end ( ) ) result = it -> second ; else result = sets [ & MBB ] = new SetOfMachineInstr [ nbRegs ] ; return result [


<s> bool <ISA_LIT>BaseInstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode


<s> for ( RegDomain D : LegalDstDomainList )


<s> if ( IdVal == <STR_LIT> ) { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { if ( has<ISA_LIT>64r6 ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>0Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) { if ( inMicro<ISA_LIT>Mode ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature (


<s> bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP , PtrVT ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SaveSP = Op . getOperand (


) ) _mm_storer_pd ( double * __P , __m128d __A ) {


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseCmp ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseTest ; break ; } switch ( First -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size )


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , *


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = * ( MBB -> getParent ( ) ) ; bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF ) ; int NegFrameSize = -


<s> if ( DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) <= <NUM_LIT> ) return false ; if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_return_big_vectors = false ; if ( ! warned_for_return_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT>


<s> vst2_p64 ( poly64_t * __a , poly64x1x2_t val ) { __builtin_aarch64_simd_oi __o ; poly64x2x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p64 ( val . val [ <NUM_LIT> ] , vcreate_p64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p64 ( val . val [ <NUM_LIT> ] , vcreate_p64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di_ssps ( __o , ( poly64x2_t ) temp . val [ <NUM_LIT> ]


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( ! ST . hasLOB ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; MF . RenumberBlocks ( ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF . front ( ) ) ; bool Changed = false ; RevertedWhileLoops . clear ( ) ; for ( auto * ML : * MLI ) Changed |= processPostOrderLoops ( ML ) ; for ( auto * WlsInstr : RevertedWhileLoops ) Changed |= revertWhileToDoLoop ( WlsInstr ) ; return


<s> vpadal_u32 ( uint64x1_t a , uint32x2_t b ) { uint64x1_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; bool Ok = TII -> copyRegToReg ( FirstMBB , MBBI , GlobalBaseReg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; assert ( Ok && <STR_LIT> ) ; Ok =


<s> OS << MI -> getDebugVariable ( ) -> getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getDebugOperand ( <NUM_LIT> ) . isReg ( ) && MI -> isDebugOffsetImm ( ) ) ; OS <<


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF


<s> rtx rhs = SET_SRC ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; if ( GET_CODE ( rhs ) == UNSPEC && XINT ( rhs , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ; if ( GET_CODE ( rhs ) == MEM && GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> )


<s> return __builtin_mve_vcvtbq_m_f16_f32v8hf ( __a ,


<s> static bool isVINSERTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getVectorElementType (


<s> static void report_out_of_range ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT actual , HOST_WIDE_INT min , HOST_WIDE_INT max ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno


<s> if ( SrcReg == <STR_LIT> ) { Warning ( IDLoc , <STR_LIT> ) ; if ( loadImmediate ( <NUM_LIT> , DstReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; return false ; } unsigned Opc ; if ( ImmValue > - <NUM_LIT> && ImmValue < <NUM_LIT> ) { ImmValue = - ImmValue ; Opc = isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opc = <STR_LIT> ; } if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( Opc , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , IDLoc , Out , STI ) ) return true ; TOut . emitRRR ( <STR_LIT> , DstReg , SrcReg , ATReg , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false


<s> if ( mem != NULL_RTX && MEM_P ( mem ) && GET_CODE ( symbol = XEXP ( mem , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_FLAGS ( symbol ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) { const char * name2 ; int p2align = <NUM_LIT> ; switch_to_section ( bss100_section ) ; while ( align > <NUM_LIT> ) { align /= <NUM_LIT> ; p2align ++ ; } name2 = default_strip_name_encoding


<s> break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = V . getConstantOperandVal ( <NUM_LIT> ) ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( ( ( Mask >> i ) & <NUM_LIT> ) == <NUM_LIT> ) Bits [ i ] = ( * LHSBits ) [ i ] ; else { if ( ( * LHSBits ) [ i ] . isZero ( ) ) Bits [ i ] = ( * LHSBits ) [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; } return std :: make_pair ( Interesting , & Bits ) ; } break ; case <STR_LIT> : { const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; const auto & RHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; bool AllDisjoint = true ; SDValue LastVal = SDValue ( ) ; unsigned LastIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) { if ( LHSBits [ i ] . isZero ( ) && RHSBits [ i ] . isZero ( ) ) { if ( LHSBits [ i ] . hasValue ( ) && LHSBits [ i ] . getValue ( ) == LastVal && LHSBits [ i ] . getValueBitIndex ( ) == LastIdx + <NUM_LIT> ) Bits [ i ] = LHSBits [ i ] ; else if ( RHSBits [ i ] . hasValue ( ) && RHSBits [ i ] . getValue ( ) == LastVal && RHSBits [ i ] . getValueBitIndex ( ) == LastIdx + <NUM_LIT> ) Bits [ i ] = RHSBits [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; } else if ( LHSBits [ i ] . isZero ( ) ) Bits [ i ] = RHSBits [ i ] ; else if ( RHSBits [ i ] . isZero ( ) ) Bits [ i ] = LHSBits [ i ] ; else { AllDisjoint = false ; break ; } if ( Bits [ i ] . hasValue ( ) ) { LastVal = Bits [ i ] . getValue ( ) ; LastIdx = Bits [ i ] . getValueBitIndex ( ) ; } else { if ( LastVal ) LastVal =


<s> enum tls_model tls_kind = TLS_MODEL_NONE ; rtx sym , addend ; if ( GET_CODE ( addr ) == CONST ) { split_const ( addr , & sym , & addend ) ; if ( GET_CODE ( sym ) == SYMBOL_REF ) tls_kind =


<s> } assert ( ! VCTPs . empty ( ) && <STR_LIT> ) ; assert ( ML . getBlocks ( ) . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( DisableTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! VPTState :: isValid ( RDA ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! ValidateLiveOuts ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Register StartReg = isDo ( Start ) ? Start -> getOperand ( <NUM_LIT> ) . getReg ( ) : Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( StartInsertPt == Start && StartReg == <STR_LIT> ) { if ( auto * IterCount = RDA . getMIOperand ( Start , isDo ( Start ) ? <NUM_LIT> : <NUM_LIT> ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( IterCount , MCRegister :: from ( <STR_LIT> ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != Start && Use != Dec ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Use ) ; return false ; } } } } MachineInstr * VCTP = VCTPs . back ( ) ; if ( Start -> getOpcode ( ) == <STR_LIT> ) { TPNumElements = Start -> getOperand ( <NUM_LIT> ) ; StartInsertPt = Start ; StartInsertBB = Start -> getParent ( ) ; } else { TPNumElements = VCTP -> getOperand ( <NUM_LIT> ) ; MCRegister NumElements = TPNumElements . getReg ( ) . asMCReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StartInsertPt != StartInsertBB -> end ( ) && ! RDA . isReachingDefLiveOut ( & * StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( StartInsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , & * StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent


<s> static SDValue LowerMGATHER ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MaskedGatherSDNode * N = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Index = N -> getIndex ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue Src0 = N -> getValue ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { if ( NumElts == <NUM_LIT> ) { Index = DAG . getNode ( <STR_LIT> , dl ,


<s> return ( __m512h ) __builtin_ia32_vfmsubaddph512_maskz ( ( __v32hf ) __A , ( __v32hf ) __B , (


<s>
SmallVector
<
unsigned
,
<NUM_LIT>
>
UnspilledCSFPRs
;
if
(
hasFP
(
MF
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
if
(
RegInfo
->
hasBasePointer
(
MF
)
)
SavedRegs
.
set
(
RegInfo
->
getBaseRegister
(
)
)
;
if
(
RegInfo
->
needsStackRealignment
(
MF
)
&&
!
RegInfo
->
hasBasePointer
(
MF
)
)
SavedRegs
.
set
(
<STR_LIT>
)
;
unsigned
NumGPRSpilled
=
<NUM_LIT>
;
unsigned
NumFPRSpilled
=
<NUM_LIT>
;
bool
ExtraCSSpill
=
false
;
bool
CanEliminateFrame
=
true
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
i
+=
<NUM_LIT>
)
{
assert
(
CSRegs
[
i
+
<NUM_LIT>
]
&&
<STR_LIT>
)
;
const
unsigned
OddReg
=
CSRegs
[
i
]
;
const
unsigned
EvenReg
=
CSRegs
[
i
+
<NUM_LIT>
]
;
assert
(
(
<STR_LIT>
.
contains
(
OddReg
)
&&
<STR_LIT>
.
contains
(
EvenReg
)
)
^
(
<STR_LIT>
.
contains
(
OddReg
)
&&
<STR_LIT>
.
contains
(
EvenReg
)
)
&&
<STR_LIT>
)
;
const
bool
OddRegUsed
=
SavedRegs
.
test
(
OddReg
)
;
const
bool
EvenRegUsed
=
SavedRegs
.
test
(
EvenReg
)
;
if
(
!
OddRegUsed
&&
!
EvenRegUsed
)
{
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
UnspilledCSGPRs
.
push_back
(
OddReg
)
;
UnspilledCSGPRs
.
push_back
(
EvenReg
)
;
}
else
{
UnspilledCSFPRs
.
push_back
(
OddReg
)
;
UnspilledCSFPRs
.
push_back
(
EvenReg
)
;
}
continue
;
}
unsigned
Reg
=
<STR_LIT>
;
if
(
OddRegUsed
^
EvenRegUsed
)
{
Reg
=
OddRegUsed
EvenReg
:
OddReg
;
SavedRegs
.
set
(
Reg
)
;
}
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize =


<s> if ( best_class != ALL_REGS ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ?


<s> SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> )


<s> case VK_<ISA_LIT>_HA16 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_LO16 : OS << <STR_LIT> ; break ; } OS << '(' ; getSubExpr ( ) -> print ( OS ) ; OS << ')'


<s> if ( ! isDoubleSpacedVectorList ( ) ) return false ; return VectorList . Count ==


<s> TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |=


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getThumbBLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx


<s> return __builtin_loongson_pcmpeqb_s ( s , t


<s> function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE (


<s> MachineInstr * NewMI = nullptr ; WasCandidate = false ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) { if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) { NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; WasCandidate = true


<s> InsertPt = Revert ? nullptr : IsSafeToDefineLR ( RDA ) ; if ( ! InsertPt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; return ; } else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * InsertPt ) ; if ( ! IsTailPredicationLegal ( ) ) { LLVM_DEBUG ( if ( ! VCTP ) dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ) ; return ; } assert ( ML -> getBlocks ( ) . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CannotTailPredicate = ! ValidateTailPredicate ( InsertPt , RDA , MLI ) ; LLVM_DEBUG ( if ( CannotTailPredicate ) dbgs ( ) <<


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; case 'r' : RC = & <STR_LIT> ; break ; case 'v'


<s> RegNum = matchACRegisterName ( RegName ) ; break ; default : break ; } if ( RegNum < <NUM_LIT> ) return MatchOperand_NoMatch ; int RegVal = getReg ( regKindToRegClass ( Kind ) , RegNum ) ; if ( RegVal == - <NUM_LIT> ) return MatchOperand_NoMatch ; <ISA_LIT>Operand * Op = <STR_LIT> ( RegVal , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( Kind ) ; Operands . push_back ( Op ) ; hasConsumedDollar = false ; Parser . Lex ( ) ; return MatchOperand_Success ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; if ( Kind == <STR_LIT> ) { if ( RegNum != <NUM_LIT> ) return MatchOperand_NoMatch ; RegNum = <NUM_LIT> ; } int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( Kind ) ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser .


<s> if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return


<s> static MachineBasicBlock * emitCapFloatStore ( const <ISA_LIT>Subtarget & Subtarget , MachineInstr & MI , const llvm :: TargetRegisterClass & RC , MachineBasicBlock * BB ) { DebugLoc DL = MI . getDebugLoc ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; Register IntReg = RegInfo . createVirtualRegister ( &


<s> if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS


<s> case <ISA_LIT>MCExpr :: MEK_DTPREL : return getExprOpValue ( <ISA_LIT>Expr -> getSubExpr ( ) , Fixups , STI ) ; case <ISA_LIT>MCExpr :: MEK_CALL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_CALL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM


<s> if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidVectorKind ( Kind , MatchKind ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } Parser . Lex ( ) ; Reg =


<s> if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT>


<s> static void dump_tree_root_info ( fma_forest * forest , fma_root_node


<s> return ( __m128i ) __builtin_ia32_vpcomltd ( ( __v4si ) __A ,


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask ) ; O <<

',' << <ISA_LIT>FI -> getCPUTopSavedRegOff ( ) << '\n' ;


<s> sawStore = true ; if ( sawLoad ) return true ; } for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet (


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [


<s> return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg (

) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ; MIRBuilder . buildInstr ( <STR_LIT> ) .


<s> if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ! ( LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) && LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) == LPAC :: ADD ) ) return false ; switch ( LdSt . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; break ; } BaseReg = LdSt . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true


<s> int cur_pos ; cur_pos = <NUM_LIT> ; fprintf ( stream , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < len ; i ++ ) { int c ; c = ( unsigned char ) string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT>


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name , bool is64BitReg ) { int CC ; CC = matchCPURegisterName


<s> if ( NewOpc == Opc ) return false ; const MCInstrDesc & MCID = get ( NewOpc ) ; CmpInstr . setDesc ( MCID ) ; CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr ( & CmpInstr , SrcReg , SrcReg2 , MRI ) ; assert ( ( CmpValue == <NUM_LIT> || CmpValue == <NUM_LIT> ) && <STR_LIT> ) ; if ( SrcReg2 != <NUM_LIT> ) return


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) .


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT>


<s> return __builtin_ia32_rndscaleph128_mask ( __A , __B , _mm_setzero_ph ( ) , (


<s> if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; int FrameIndex = MFI -> CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd ; ++ Reg , ++ i ) { unsigned VReg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOps ) ; return FrameIndex


<s> SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Tgt , MachinePointerInfo

:: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( )


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { InFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InFlag ) ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( BytesCalleePops , true ) , InFlag ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue (


<s> if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { assert ( VT . getSizeInBits ( ) >= SrcSVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned OpCode = ( SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( OpCode , dl , <STR_LIT> , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; return DAG . getZExtOrTrunc ( ExtOp , dl ,


<s> } MachineInstrBuilder MI ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( getLEArOpcode ( Uses64BitFramePtr ) ) , StackPtr ) , StackPtr , false , Offset ) ; } else { bool IsSub = Offset < <NUM_LIT> ; uint64_t AbsOffset = IsSub ? - Offset : Offset ; const unsigned Opc = IsSub ? getSUBriOpcode ( Uses64BitFramePtr , AbsOffset ) : getADDriOpcode ( Uses64BitFramePtr , AbsOffset ) ; MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( AbsOffset ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } return MI


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > (


<s> SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue Low = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; SDValue High = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; Low = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , Low ) , Zeros ) ; High = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , High ) , Zeros ) ; MVT ShortVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ShortVecVT , Low ) , DAG . getBitcast ( ShortVecVT , High ) ) ; return DAG . getBitcast ( VT , V ) ; } assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Shifters ( NumElts , DAG

. getConstant ( <NUM_LIT> , DL , EltVT ) ) ;


<s> void <ISA_LIT>MCInstLower :: lowerLongBranchLUi ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode (


<s> break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) && ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > MemOps [

insertAfter ] . Position ) insertAfter = i ;


<s> if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! C || ! ( C . isPowerOf2 ( ) || ( - C ) . isPowerOf2 ( ) ) ) return selectBinaryOp ( I , <STR_LIT> ) ; unsigned Lg2 = C . countTrailingZeros ( ) ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; if ( cast < BinaryOperator > ( I ) -> isExact ( ) ) { unsigned ResultReg = emitASR_ri ( VT , VT , Src0Reg , Src0IsKill , Lg2 ) ; if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return true ; } int64_t Pow2MinusOne = ( <NUM_LIT> << Lg2 ) - <NUM_LIT> ; unsigned AddReg = emitAdd_ri_ ( VT , Src0Reg , false , Pow2MinusOne ) ; if ( ! AddReg ) return false ; if ( ! emitICmp_ri ( VT , Src0Reg , false , <NUM_LIT> ) ) return false ; unsigned SelectOpc


<s> assert ( MaxShift > <NUM_LIT> ) ; if ( ! N . hasOneUse ( ) ) return false ; ConstantSDNode * MulConst = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! MulConst ) return false ; if ( ! MulConst -> hasOneUse ( ) ) return false ; unsigned MulConstVal = MulConst -> getZExtValue


<s> const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM

. getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>32LETarget ( ) , & getThe<ISA_LIT>64Target ( ) , & getThe<ISA_LIT>64LETarget ( ) } ) { RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , Size ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; SDValue Ops [ <NUM_LIT> ] = { Result


<s> bool isFP64 ( ) const { return STI . getFeatureBits ( )


<s> static bool preferUnsignedComparison ( SelectionDAG & DAG , SDValue CmpOp0 , SDValue CmpOp1 , unsigned CCMask ) { if ( CCMask != <STR_LIT> && CCMask != <STR_LIT> ) return false ; if ( CmpOp1 . getOpcode ( ) == <STR_LIT> ) { uint64_t Value = cast < ConstantSDNode > ( CmpOp1 ) -> getSExtValue ( ) ; if ( CmpOp0 . hasOneUse ( ) && <STR_LIT> ( CmpOp0 . getNode ( ) ) && ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) ) return true ; if ( CmpOp0 . getValueType ( ) == <STR_LIT> && ( Value >> <NUM_LIT> ) == <NUM_LIT> ) return true ; return false ; } if ( CmpOp1 . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( CmpOp1 . getNode ( ) ) ) return true ; if ( CmpOp1 . getOpcode ( ) == <STR_LIT> && CmpOp1 . getValueType ( ) == <STR_LIT> ) { SDValue Mask = CmpOp1 . getOperand ( <NUM_LIT> ) ; if ( Mask . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode

> ( Mask ) -> getZExtValue ( ) == <NUM_LIT> ) return true ;


<s> SDValue PackedOp = Op . getOperand ( <NUM_LIT> ) ; EVT OutVT = Op . getValueType ( ) ; EVT InVT = PackedOp . getValueType ( ) ; unsigned ToBits = OutVT . getScalarSizeInBits (


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int InputIdx = Mask [ i ] >= Size ; if ( i < Size / <NUM_LIT> ) ++ NumLoInputs [ InputIdx ] ; else ++ NumHiInputs [ InputIdx ] ; if ( ( i % <NUM_LIT> ) ==

<NUM_LIT> ) ++ NumEvenInputs [ InputIdx ] ;


<s> static bool isZeroExtended ( Register R , MachineRegisterInfo & MRI ) { return MRI . getVRegDef ( R ) -> getOpcode


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I


<s> MachineIRBuilder & MIRBuilder = Helper . MIRBuilder ; if ( MI . getOpcode ( ) == TargetOpcode :: G_MEMSET ) { auto & Value = MI . getOperand


<s> if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MCSymbol * & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = GetGlobalValueSymbol ( * I ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { O << * Stubs [ i ] . first << <STR_LIT> ; O << <STR_LIT> << * Stubs [ i ] . second << '\n' ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; } } Stubs = MMIMacho .


<s> return inline_secondary_memory_needed ( mode , class1 ,


<s> if ( ! DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) || ! isConstantOrUndef (

N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ;


<s> unsigned Reg ; int64_t Offset ; L = getLoc ( ) ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma

( ) || parseImmExpr ( Offset ) ) return true ;


<s> return ( ( vec_double2 ) ( si_dfnma ( ( qword ) ( a ) , ( qword


<s> void x86_elf_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) { switch_to_section ( get_named_section ( decl , <STR_LIT> , <NUM_LIT> ) ) ; fputs ( LARGECOMM_SECTION_ASM_OP , file ) ; } else fputs ( COMMON_ASM_OP , file ) ; assemble_name ( file ,


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) ) return false ; CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT>


<s> static enum reg_class rs6000_debug_preferred_reload_class ( rtx x , enum reg_class rclass ) { enum reg_class ret = rs6000_preferred_reload_class ( x , rclass ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , reg_class_names [ ret ] , reg_class_names [ rclass

] , GET_MODE_NAME ( GET_MODE ( x ) ) ) ;


<s> static unsigned getStoreRegOpcode ( unsigned SrcReg , const TargetRegisterClass * RC , bool isStackAligned ,


<s> unsigned getStackEntry ( unsigned STi ) const { assert ( STi <


<s> case NE : case LTGT : case ORDERED : * code = reverse_condition_maybe_unordered ( * code ) ; return true ; default : return


<s> SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CSel , DAG . getConstant ( Lg2 , <STR_LIT> ) ) ; if ( Divisor . isNonNegative (


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned FrameReg = getFrameRegister (


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ,

DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; <ISA_LIT>InstPrinter :: printOperand ( MO , OS ) ; } return false


<s> return ; case <STR_LIT> : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( getSubtarget ( ) . isTargetNaCl ( ) ? <STR_LIT> : <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel ( PICBase ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand (


<s> if ( UNARY_P ( x ) ) return symbolic_expression_p ( XEXP ( x , <NUM_LIT> ) ) ; if ( ARITHMETIC_P ( x ) ) return ( symbolic_expression_p ( XEXP ( x , <NUM_LIT> ) ) ||

symbolic_expression_p ( XEXP ( x , <NUM_LIT> ) ) ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg ( )


<s> const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , & STI , Alignment ) ; else OS . emitValueToAlignment ( Alignment , <NUM_LIT> , <NUM_LIT> , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ <STR_LIT> ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; <ISA_LIT>ELFStreamer & MEF = static_cast < <ISA_LIT>ELFStreamer & > ( Streamer ) ; MEF . Emit<ISA_LIT>OptionRecords ( )


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( false ) ; EmitTST ( Out , Reg ) ; Out . EmitInstruction ( Saved


<s> DEBUG ( const MachineLoop * Loop = MLI -> getLoopFor ( MBB ) ; if ( Loop && Loop -> getHeader ( ) == MBB ) dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; ) ; MachineBasicBlock * SinglePredMBB = getSingleSchedPred ( MBB , MLI -> getLoopFor ( MBB ) ) ; if ( SinglePredMBB == nullptr || SchedStates . find ( SinglePredMBB ) == SchedStates . end ( ) ) return ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * SinglePredMBB ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; DEBUG ( HazardRec -> dumpState ( ) ; ) ; for ( MachineBasicBlock :: iterator I = SinglePredMBB -> getFirstTerminator ( ) ; I != SinglePredMBB -> end ( ) ; I ++ ) { DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; bool TakenBranch = ( I -> isBranch ( ) && ( TII -> getBranchInfo ( * I ) . Target -> isReg ( ) || TII -> getBranchInfo ( * I ) . Target -> getMBB ( ) == MBB ) ) ; HazardRec -> emitInstruction ( & * I ,


<s> return MIB . buildNot ( DstTy , FCmp ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS , RHS } ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS , RHS } ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS , RHS } ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { RHS , LHS


<s> SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; auto * IdxC = dyn_cast < ConstantSDNode > ( Idx ) ; MVT EltVT = Op . getSimpleValueType ( ) ; assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! IdxC ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; MVT ExtEltVT = ( NumElts <= <NUM_LIT> ) ? <STR_LIT> ( <NUM_LIT> / NumElts ) : <STR_LIT> ; MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl


<s> char pattern [ <NUM_LIT> ] ; char size ; rtx code = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; size = nds32_byte_to_size ( byte ) ; switch ( nds32_mem_format ( operands [ <NUM_LIT> ] ) ) { case ADDRESS_REG : operands [ <NUM_LIT> ] = code ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case ADDRESS_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_INC_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_FP_IMM7U : output_asm_insn ( <STR_LIT> ,


<s> DEBUG_FUNCTION void rs6000_debug_print_mode ( ssize_t m ) { ssize_t rc ; int spaces = <NUM_LIT> ; bool fuse_extra_p ; fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( m ) ) ; for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) fprintf ( stderr , <STR_LIT> , reload_reg_map [ rc ] . name , rs6000_debug_addr_mask ( reg_addr [ m ] . addr_mask [ rc ] , true ) ) ; if ( ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) || ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) ) fprintf ( stderr , <STR_LIT> , ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) ? 's' : '*' , ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) ? 'l' : '*' ) ; else spaces += sizeof ( <STR_LIT> ) - <NUM_LIT> ; if ( reg_addr [ m ] . scalar_in_vmx_p ) { fprintf ( stderr , <STR_LIT> , spaces , <STR_LIT> ) ; spaces = <NUM_LIT> ; } else spaces += sizeof ( <STR_LIT> ) - <NUM_LIT> ; fuse_extra_p = ( ( reg_addr [ m ] . fusion_gpr_ld != CODE_FOR_nothing ) || reg_addr [ m ] . fused_toc ) ; if ( ! fuse_extra_p ) { for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) { if ( rc != RELOAD_REG_ANY ) { if ( reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addi_st [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addis_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addis_st [ rc ] != CODE_FOR_nothing ) { fuse_extra_p = true ; break ; } } } } if ( fuse_extra_p ) { fprintf ( stderr , <STR_LIT> , spaces , <STR_LIT> ) ; spaces = <NUM_LIT> ; for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) { if ( rc != RELOAD_REG_ANY ) { char load , store ; if ( reg_addr [ m ] . fusion_addis_ld [ rc ] != CODE_FOR_nothing ) load = 'l' ; else if ( reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing ) load = 'L' ; else load = '-'


<s> return ( uint8x16_t ) __builtin_aarch64_raddhn2v8hi ( ( int8x8_t ) __a , ( int16x8_t ) __b , (


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseGPR64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( ! is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , ( int


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return & DefaultSubtarget


<s> emitFrameDirective ( ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask (


<s> if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> ) return false ; if ( Subtarget -> isLittle ( ) ) { if ( Fast ) * Fast = true ; return true ; } else { if ( Ty == <STR_LIT> || ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && Alignment >= <NUM_LIT> ) || ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && Alignment >= <NUM_LIT> ) ) { if ( Fast )


<s> case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : { unsigned NumOperands = MI . getNumOperands ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , false ) , <NUM_LIT> ) ; return getInstructionMapping ( DefaultMappingID , <NUM_LIT> , Mapping , NumOperands ) ; } default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_FPTOSI : { auto & Op0 = MI . getOperand ( <NUM_LIT> ) ; auto & Op1 = MI . getOperand ( <NUM_LIT> ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool FirstArgIsFP = Opc == TargetOpcode :: G_SITOFP ; bool SecondArgIsFP = Opc == TargetOpcode :: G_FPTOSI ; OpRegBankIdx [ <NUM_LIT> ] = getPartialMappingIdx ( Ty0 , FirstArgIsFP ) ; OpRegBankIdx [ <NUM_LIT> ] = getPartialMappingIdx ( Ty1 , SecondArgIsFP ) ; break ; } case TargetOpcode :: G_FCMP : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty1 . getSizeInBits ( ) == Ty2 . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Size = Ty1 . getSizeInBits ( ) ; ( void ) Size ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto FpRegBank = getPartialMappingIdx ( Ty1 , true ) ; OpRegBankIdx = { PMI_GPR8 , PMI_None , FpRegBank , FpRegBank } ; break ; } case TargetOpcode :: G_TRUNC : case TargetOpcode :: G_ANYEXT : { auto & Op0 = MI . getOperand ( <NUM_LIT> ) ; auto & Op1 = MI . getOperand ( <NUM_LIT> ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool isFPTrunc = ( Ty0 . getSizeInBits ( ) == <NUM_LIT> || Ty0 . getSizeInBits ( ) == <NUM_LIT> ) && Ty1 . getSizeInBits ( ) == <NUM_LIT> && Opc == TargetOpcode :: G_TRUNC ; bool isFPAnyExt = Ty0 . getSizeInBits ( ) == <NUM_LIT> && ( Ty1 . getSizeInBits ( ) == <NUM_LIT> || Ty1 . getSizeInBits ( ) == <NUM_LIT> ) && Opc == TargetOpcode :: G_ANYEXT ; getInstrPartialMappingIdxs ( MI , MRI , isFPTrunc || isFPAnyExt , OpRegBankIdx ) ; }


<s> LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; TM = & MF . getTarget ( ) ; ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; Is64Bit = TM -> getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; Module & M = const_cast < Module & > ( * MMI -> getModule ( ) ) ; if ( ! MF . getName ( ) . startswith ( ThunkNamePrefix ) ) { if ( InsertedThunks ) return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } if ( Subtarget . isDarwinABI ( ) ) return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv


<s> if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( hasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * Bin = static_cast < const MCBinaryExpr * > ( Expr ) ; if ( hasSecRelSymbolRef ( Bin -> getLHS ( ) ) || hasSecRelSymbolRef ( Bin -> getRHS ( ) ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } } if ( FixupKind == FK_PCRel_4 || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) { ImmOffset -= <NUM_LIT> ; if ( startsWithGlobalOffsetTable ( Expr ) != GOT_None ) FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( FixupKind == FK_PCRel_2 ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == FK_PCRel_1 ) ImmOffset -=


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( insn -> opcodeType == TWOBYTE ) { attrMask ^= ATTR_OPSIZE ; insn -> immediateSize = <NUM_LIT> ; insn -> displacementSize = <NUM_LIT> ; } break ; } } if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT && insn -> vectorExtensionType != TYPE_NO_VEX_XOP ) { if ( ( insn -> vectorExtensionType == TYPE_EVEX && wFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_VEX_3B && wFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_XOP && wFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) { uint16_t instructionIDWithREXW ; if ( getIDWithAttrMask ( & instructionIDWithREXW , insn , attrMask | ATTR_REXW ) ) { insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT> ; } const char * SpecName = GetInstrName ( instructionIDWithREXW , miiArg ) ; if ( ! is64Bit ( SpecName ) ) { insn -> instructionID = instructionIDWithREXW ; insn -> spec = specifierForUID ( instructionIDWithREXW ) ; return <NUM_LIT> ; } } } if ( insn -> opcodeType == ONEBYTE && ( ( insn -> opcode & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_ADSIZE ; if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_OPSIZE ; if ( insn -> mode == MODE_16BIT ) attrMask ^= ATTR_ADSIZE | ATTR_OPSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT> ; } if ( ( insn -> mode == MODE_16BIT || insn -> prefixPresent [ <NUM_LIT> ] ) && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const char * specName , * specWithOpSizeName ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specName = GetInstrName ( instructionID , miiArg ) ; specWithOpSizeName = GetInstrName ( instructionIDWithOpsize , miiArg


<s> if ( ! TheReg || ! TheReg -> hasRequiredFeatures ( FeatureBits ) ) return - <NUM_LIT> ; return ( int ) ( TheReg ->


<s> TRI = STI -> getRegisterInfo ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow ( MF ) ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB (


<s> fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f ,


<s> unsigned EltBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; EVT EltVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EltBits * <NUM_LIT> ) ; auto HalfEC = VT . getVectorElementCount ( ) / <NUM_LIT> ; return EVT :: getVectorVT ( * DAG . getContext ( )


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { PM -> add ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine (


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return


<s> if ( ! KindRes ) return true ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( Reg , RegKind :: NeonVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , S , getContext ( ) ) ) ; return tryParseVectorIndex ( Operands )


<s> gcc_assert ( VECTOR_MODE_P ( mode ) || mode == OImode ) ; rtx mem = gen_rtx_MEM ( mode , memory_address ( mode , addr )


<s> if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isX18Reserved ( ) ) Reg = <NUM_LIT> ; if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> )


<s> } ; static const SpillSlot Offsets64 [ ] = { { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> ,


<s> void addRegF8RCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( FRegs [ getReg (


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> void <ISA_LIT>PagerandoOptimizer :: changeToPCRelativeCall ( MachineInstr * MI , const Function * Callee ) { auto & MBB = * MI -> getParent ( ) ; auto & MF = * MBB . getParent ( ) ; auto & C = MF . getFunction ( ) . getContext ( ) ; auto & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; auto & TLI = * MF . getSubtarget ( ) . getTargetLowering ( ) ; auto & DL = MF . getDataLayout ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto isThumb = AFI . isThumbFunction ( ) ; auto Label = AFI . createPICLabelUId ( ) ; auto PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; auto * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( Callee , Label , <STR_LIT> , PCAdj , <STR_LIT> , false ) ; auto Alignment = DL . getPrefTypeAlignment ( Type :: getInt32PtrTy ( C ) ) ; auto Index = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Alignment ) ; auto Opc = AFI . isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ; auto OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TII . get ( Opc ) , OffsetReg ) . addConstantPoolIndex ( Index ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps (


<s> BitVector <ISA_LIT>BaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) )


<s> StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; assert ( StoredVal . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal , DAG . getUNDEF ( <STR_LIT> ) ) ; StoredVal = DAG . getBitcast (


<s> return ( __m128i ) __builtin_ia32_pmovqd256_mask ( ( __v4di ) __A ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> void DecodeMOVLHPSMask ( unsigned NElts , SmallVectorImpl < int > & ShuffleMask ) { for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ,


<s> return __builtin_mve_vandq_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a


<s> NaCl<ISA_LIT>_64AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>_64AsmBackend ( T , OSABI , CPU ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo (


<s> const Align Alignment = MBB . getAlignment ( ) ; if ( Alignment == Align :: None ( ) ) return <NUM_LIT> ; const Align ParentAlign = MBB . getParent ( ) -> getAlignment


<s> if ( ! MDT -> dominates ( L2 , L1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; <ISA_LIT>FI . addLOHDirective ( MCLOH_AdrpAdrp , { L2 , L1 } ) ; ++ NumADRPSimpleCandidate ; } else if ( Size == <NUM_LIT> ) ++ NumADRPComplexCandidate2 ; else if ( Size == <NUM_LIT> ) ++ NumADRPComplexCandidate3 ; else ++


<s> return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op ,


<s> unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( unsigned i = <NUM_LIT> , e = IB -> getNumSuccessors ( ) ; i != e ; ++ i ) FuncInfo

. MBB -> addSuccessor ( FuncInfo . MBBMap [ IB -> getSuccessor ( i ) ] ) ;


<s> MachineInstrBuilder buildLoad ( const DstOp & Res


<s> return loongarch_print_operand_punct [ code ]


<s> SDValue InGlue = DivRem ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , dl , LO , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( N -> hasAnyUseOfValue


<s> Parser . Lex ( ) ; int64_t ImmDisp = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { ImmDisp = Tok . getIntVal ( ) ; AsmToken ImmDispToken = Parser . Lex ( ) ; if ( isParsingInlineAsm ( ) ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , ImmDispToken . getLoc ( ) ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { const MCExpr * Disp = MCConstantExpr :: Create ( ImmDisp , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , ImmDispToken . getEndLoc ( ) , Size ) ; } } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers (


<s> edge_iterator ei ; edge e ; if ( ! crtl -> tail_call_emit ) return false ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <=


<s> NewBB -> getParent ( ) -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = llvm :: lower_bound ( WaterList , NewBB , CompareMBBNumbers


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm ( ) ; addExpr ( Inst , Expr


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } DEBUG ( dbgs ( ) << Parser . getTok ( ) . getKind ( ) <<


<s> tree decl = def_builtin2 ( mask , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = <NUM_LIT> ; else ix86_builtins_isa [ ( int ) code


<s> if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ! ByteOk && ! HalfWordOk ) continue ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; CPUser & User = CPUsers [ JumpTableUserIndices [ JTI ] ] ; unsigned DeadSize = <NUM_LIT> ; bool CanDeleteLEA = false ; bool BaseRegKill = false ; bool PreservedBaseReg = preserveBaseRegister ( MI , User . MI , DeadSize , CanDeleteLEA , BaseRegKill ) ; if ( ! jumpTableFollowsTB ( MI , User . CPEMI ) && ! PreservedBaseReg ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstr * CPEMI = User . CPEMI ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock :: iterator MI_JT = MI ; MachineInstr * NewJTMI = BuildMI ( * MBB , MI_JT , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( User . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getKillRegState ( BaseRegKill ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ; unsigned JTOpc = ByteOk ? <STR_LIT> : <STR_LIT> ; CPEMI -> setDesc ( TII -> get ( JTOpc ) ) ; if ( jumpTableFollowsTB ( MI , User . CPEMI ) ) { NewJTMI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; NewJTMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; if ( CanDeleteLEA ) { User . MI -> eraseFromParent ( ) ; DeadSize += <NUM_LIT> ; User . MI = NewJTMI ; User . MaxDisp = <NUM_LIT> ; User . NegOk = false ; User . IsSoImm = false ; User . KnownAlignment = false ; } else { int CPEntryIdx = JumpTableEntryIndices [ JTI ] ; auto & CPEs = CPEntries [ CPEntryIdx ] ; auto Entry = std :: find_if ( CPEs . begin ( ) , CPEs . end ( ) , [ & ] ( CPEntry & E ) { return E . CPEMI == User . CPEMI ; } ) ; ++ Entry -> RefCount ; CPUsers . emplace_back ( CPUser ( NewJTMI , User . CPEMI , <NUM_LIT> , false , false ) ) ; } } unsigned NewSize = TII -> GetInstSizeInBytes ( * NewJTMI ) ; unsigned OrigSize = TII -> GetInstSizeInBytes ( * MI ) ; MI -> eraseFromParent (


<s> if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffective<ISA_LIT>CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , IsJIT ( JIT ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; initAsmInfo (


<s> bool <ISA_LIT>InstructionSelector :: selectMergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF , CodeGenCoverage & CoverageInfo ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) && <STR_LIT> ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg0 ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned DefReg = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( DefReg , RegBank ) ; if ( ! emitInsertSubreg ( DefReg , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I , MRI , MF ) ) return false ; for ( unsigned Idx = <NUM_LIT> ; Idx < I . getNumOperands ( ) ; ++ Idx ) { unsigned Tmp = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst , CoverageInfo ) ) return false ; } MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ; if ( ! select ( CopyInst , CoverageInfo ) ) return false ; I . eraseFromParent (


<s> FunctionCallee FCache = M . getOrInsertFunction ( MASSVEntryName , Func . getFunctionType ( ) , Func . getAttributes ( ) ) ; CI -> setCalledFunction ( FCache ) ; return true


<s> SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; if ( is64BitVector ) { unsigned Opc = DOpcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) { SDValue D = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + Vec , dl , VT , SuperReg ) ; ReplaceUses ( SDValue ( N , Vec ) , D ) ; } ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLd , <NUM_LIT> ) ) ; return NULL ; } if ( NumVecs <= <NUM_LIT> ) { unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SuperReg = SDValue ( VLd , <NUM_LIT> ) ; Chain = SDValue ( VLd , <NUM_LIT> ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl ,


<s> for ( unsigned i = Desc . getNumOperands ( ) , e = OldMI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = OldMI . getOperand (


<s> for ( StringMap < const <ISA_LIT>CallEntry * > :: iterator I = ExternalCallEntries . begin ( ) , E = ExternalCallEntries . end ( ) ; I != E ; ++ I ) delete I ->


<s> virtual raw_ostream & GetCommentOS ( ) { if ( ! IsVerboseAsm ) return nulls ( ) ; return


<s> if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; unsigned RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( MulLHS ) ; return emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ShiftVal ) ; } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) if ( const auto * SI = dyn_cast < ShlOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) { uint64_t ShiftVal = C -> getZExtValue ( ) ; unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( SI -> getOperand ( <NUM_LIT> ) ) ; return emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ShiftVal ) ; } unsigned RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( RHS ) ; MVT VT = std :: max ( <STR_LIT> , RetVT . SimpleTy ) ; ResultReg = fastEmit_rr ( VT , VT , ISDOpc , LHSReg , LHSIsKill , RHSReg , RHSIsKill ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , true , Mask ) ; } return


<s> return ( __m256i ) __builtin_ia32_loaddqusi256_mask ( ( __v8si * ) __P , ( __v8si )


<s> if ( ( MEM_P ( operands [ <NUM_LIT> ] ) || MEM_P ( operands [ <NUM_LIT> ] ) ) && ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return false ; return true


<s> createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } const unsigned LogAlign = isThumb ? <NUM_LIT> : <NUM_LIT> ; if ( NewMBB -> getLogAlignment ( ) < LogAlign ) NewMBB -> setLogAlignment ( LogAlign ) ; if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . add ( CPEMI -> getOperand (


<s> InstructionCost Cost = <NUM_LIT> ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; for ( auto * I : Tys ) { if ( ! I -> isVectorTy ( ) ) continue ; if ( I -> getScalarSizeInBits ( ) * cast < FixedVectorType > ( I ) -> getNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) +

getMemoryOpCost ( Instruction :: Load , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) ;


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; } if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; if ( HasELFModifier ) ImmVal = <ISA_LIT>MCExpr :: Create ( ImmVal , RefKind , getContext (


<s> Pass * llvm :: createMVETailPredicationPass ( ) { return new MVETailPredication


<s> return CurDAG -> getTargetConstant ( ( uint64_t ) <STR_LIT> , dl


<s> EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; unsigned DestReg ; auto RC = MRI . getRegClass ( SrcReg ) ; if ( Subtarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( isVSFRCRegClass ( RC ) ) { DestReg = createResultReg (


<s> BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status

) . addReg ( newval ) . addReg ( ptr ) ;


<s> static bool isLDSTRO ( InsnType insn ) { return ( ( ( insn ) & <NUM_LIT> )


<s> switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : case TargetOpcode :: G_XOR : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getIConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! VRegAndVal ) { std :: swap ( ConstantReg , TestReg ) ; VRegAndVal = getIConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; } if ( VRegAndVal ) { if ( HasZext ) C = VRegAndVal -> Value . getZExtValue ( ) ; else C = VRegAndVal -> Value . getSExtValue ( ) ; } break ; } case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_SHL : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getIConstantVRegValWithLookThrough ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( VRegAndVal ) C = VRegAndVal -> Value . getSExtValue ( ) ; break ; } } if ( ! C || ! TestReg . isValid ( ) ) break ; Register NextReg ; unsigned TestRegSize = MRI . getType ( TestReg ) . getSizeInBits ( ) ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : if ( ( * C >> Bit ) & <NUM_LIT> ) NextReg = TestReg ; break ; case TargetOpcode :: G_SHL : if ( * C <= Bit && ( Bit - * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit - * C ; } break ; case TargetOpcode :: G_ASHR : NextReg = TestReg ; Bit = Bit + * C ; if ( Bit >= TestRegSize ) Bit = TestRegSize - <NUM_LIT> ; break ; case TargetOpcode :: G_LSHR : if ( ( Bit + * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit + * C ; } break ; case TargetOpcode :: G_XOR : if ( ( * C >> Bit ) & <NUM_LIT> ) Invert = ! Invert ; NextReg = TestReg ; break ; } if ( ! NextReg . isValid ( ) ) return Reg ; Reg = NextReg ; } return Reg