<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm )


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget -> isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Subtarget -> isABI_N32 (


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsi_u64 ( unsigned long long __X ) { return __blsi_u64 (


<s> return & InstrInfo . getRegisterInfo (


<s> return GET_CODE ( x ) == SYMBOL_REF || GET_CODE (


<s> if ( ( ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ElemSize == <NUM_LIT> ) ) && ElemSize / <NUM_LIT> <= Alignment ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false


<s> if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i

) ) . second ) assert ( false && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) + ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ; case


<s> } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer


<s> switch ( op_code ) { case LTU : case LEU : case GEU : case GTU : return aarch64_sve_cmp_immediate_p ( x , false ) ; case LT : case LE : case GE : case GT : case NE : case EQ : return aarch64_sve_cmp_immediate_p ( x , true ) ; default : gcc_unreachable (


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; const Triple & TT = STI . getTargetTriple ( ) ; bool is<ISA_LIT>64 = TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ; return CTX . getRegisterInfo ( ) -> getEncodingValue ( is<ISA_LIT>64


<s> if ( ! TLI . isOperationLegalOrCustom ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; unsigned NumElems = Op . getNumOperands ( ) ; SDValue VecIn1 ; SDValue VecIn2 ; SmallVector < unsigned , <NUM_LIT> > InsertIndices ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Opc = Op . getOperand ( i ) . getOpcode ( ) ; if ( Opc == <STR_LIT> ) continue ; if ( Opc != <STR_LIT> ) { if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; int Idx = getUnderlyingExtractedFromVec ( ExtractedFromVec , ExtIdx ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! VecIn1 . getNode ( ) ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( ! VecIn2 . getNode ( ) ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } if ( ExtractedFromVec == VecIn1 ) Mask [


<s> return ( ( optimize_size || arm_ld_sched ) ? <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( * MBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ; MI . eraseFromParent ( ) ; return


<s> const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstrAndDebugLoc ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isCortexA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> rtx_insn * last_label = <NUM_LIT> ; int insns_since_last_label = <NUM_LIT> ; init_insn_group_barriers ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) ) { if ( insns_since_last_label ) last_label = insn ; insns_since_last_label = <NUM_LIT> ; } else if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_BASIC_BLOCK ) { if ( insns_since_last_label ) last_label = insn ; insns_since_last_label = <NUM_LIT> ; } else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPECV_INSN_GROUP_BARRIER ) { init_insn_group_barriers ( ) ; last_label = <NUM_LIT> ; } else if ( NONDEBUG_INSN_P ( insn ) ) { insns_since_last_label = <NUM_LIT> ; if ( group_barrier_needed ( insn ) ) { if ( last_label ) { if ( dump ) fprintf ( dump , <STR_LIT> , INSN_UID ( last_label ) ) ; emit_insn_before ( gen_insn_group_barrier ( GEN_INT ( <NUM_LIT> ) ) , last_label ) ; insn = last_label ; init_insn_group_barriers (


<s> SmallVector < <STR_LIT> , <NUM_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false ; switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; case CallingConv :: <ISA_LIT>_INTR : report_fatal_error ( <STR_LIT> )


<s> std :: pair < <ISA_LIT>InstrInfo :: BranchType , MachineInstr * > P = getBranch ( Pred , Succ ) ; if ( P . first == <ISA_LIT>InstrInfo :: BT_None ) return false ; if ( ( P . first != <ISA_LIT>InstrInfo :: BT_Uncond ) && ( P . first != <ISA_LIT>InstrInfo :: BT_NoBranch ) ) { HasMultipleSuccs = true ; RegDU . addLiveOut ( Pred , Succ ) ; } BrMap [ & Pred ] = P . second ; return


<s> } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || ! Subtarget . hasFP64 ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT>


<s> return ( uint16x4_t ) __builtin_neon_vcgtv4hi ( __a ,


<s> return ( int16x4_t ) __builtin_aarch64_sqmovnv4si


<s> SDValue Val = isNEONModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VmovVT , VT . is128BitVector ( ) , VMOVModImm ) ; if ( Val . getNode ( ) ) { SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } uint64_t NegatedImm = ( SplatBits . getZExtValue ( ) ^ ( ( <NUM_LIT> << SplatBitSize ) - <NUM_LIT> ) ) ; Val = isNEONModifiedImm ( NegatedImm , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VmovVT , VT . is128BitVector ( ) , VMVNModImm ) ; if ( Val . getNode ( ) ) { SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool isConstant = true ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; if ( ! Value . getNode ( ) ) Value


<s> return false ; } if ( MaskNode . getOpcode ( ) == <STR_LIT> && MaskNode . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; unsigned ElementSplit = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; SDValue MaskOp = MaskNode . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskOp ) ) { SplitElementToMask ( CN -> getAPIntValue ( ) ) ; RawMask . append ( ( VT . getVectorNumElements ( ) - <NUM_LIT> ) * ElementSplit , <NUM_LIT> ) ; return true ; } return false ; } if ( MaskNode . getOpcode ( ) != <STR_LIT> ) return false ; if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; for ( SDValue Op : MaskNode -> ops


<s> unsigned LSB = ImmROp . getImm ( ) == <NUM_LIT> ? <NUM_LIT> : RegWidth - ImmROp .


<s> unsigned CalleeCC = TheCall -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { SDValue Callee = TheCall -> getCallee ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ || ! Subtarget -> isPICStyleGOT ( ) || ! Subtarget -> is64Bit ( )


<s> MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . add ( Reg0Op ) . add ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; assert ( TII -> get ( Opcode ) . getNumOperands ( ) == <NUM_LIT> && TII -> get ( NewOpc

) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> case TargetOpcode :: G_FFLOOR : case TargetOpcode :: G_FNEG : case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode :: G_FLOG2


<s> void fma_forest :: merge_forest ( fma_forest * other_forest ) { std :: list < fma_root_node * > * other_roots ; std :: list < fma_root_node * > :: iterator other_root_iter ; if ( this == other_forest )


<s> unsigned <ISA_LIT>AsmParser :: IdentifyIntelInlineAsmOperator ( StringRef Name ) { return StringSwitch < unsigned > ( Name ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_TYPE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_SIZE

) . Cases ( <STR_LIT> , <STR_LIT> , IOK_LENGTH ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_OFFSET ) . Default ( IOK_INVALID ) ;


<s> -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) ) ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size (


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; if ( ! isCmp ) TmpInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; TmpInst . addOperand ( Inst . getOperand


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; initialize ( MF


<s> MVT VT = Load -> getSimpleValueType ( <NUM_LIT> ) ; MVT EVT = VT . getVectorElementType ( ) ; SDValue Addr = Load -> getOperand ( <NUM_LIT> ) ; SDValue NewAddr = DAG . getNode ( <STR_LIT> , dl , Addr . getSimpleValueType ( ) , Addr , DAG . getConstant ( Index * EVT . getStoreSize ( ) , Addr . getSimpleValueType ( ) ) ) ; SDValue NewLoad = DAG . getLoad ( EVT , dl , Load -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Load -> getMemOperand ( ) , <NUM_LIT> , EVT . getStoreSize ( ) ) ) ; return NewLoad


<s> RegisterTarget < Triple :: cjg > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) ,


<s> if ( STI . isTargetLinux ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetDarwin ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; } else if ( STI . isTargetWin32 ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetFreeBSD ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; if ( STI . isTargetLinux ( ) || STI . isTargetWin32 ( ) || STI . isTargetWin64 ( ) ) { BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ; } else if ( STI . isTargetDarwin ( ) ) { unsigned ScratchReg2 ; bool SaveScratch2 ; if ( CompareStackPointer ) { ScratchReg2 = GetScratchRegister ( Is64Bit , MF , true ) ; SaveScratch2 = false ; } else { ScratchReg2 = GetScratchRegister ( Is64Bit , MF , false ) ; SaveScratch2 = MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) ; } assert ( ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) || SaveScratch2 ) && <STR_LIT> ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg2 , RegState :: Kill ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & prologueMBB ) ; if ( Is64Bit ) { if ( IsNested ) BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg


<s> void <ISA_LIT>_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRRI20 ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { <ISA_LIT>RRIAddressMode AM ; bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr


<s> __attribute__ ( ( vector_size ( <NUM_LIT> * sizeof ( float ) ) ) ) ; static __inline unsigned long long sh_media_MABS_L ( unsigned long long mm ) { typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_absv2si2 ( (


<s> if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg ,


<s> FunctionPass * llvm :: create<ISA_LIT>GlobalMergePass ( const TargetLowering *


<s> ShapeBBs . clear ( ) ; DefVisited . clear ( ) ; BBVisitedInfo . clear (


<s> MachineBasicBlock * jcc1MBB = nullptr ; if ( NextCMOV ) { jcc1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , jcc1MBB ) ; jcc1MBB -> addLiveIn ( <STR_LIT> ) ; } MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; MachineInstr * LastEFLAGSUser = NextCMOV ? NextCMOV : MI ; if ( ! LastEFLAGSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastEFLAGSUser , BB , TRI ) ) { copy0MBB -> addLiveIn ( <STR_LIT> ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; } sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; if ( NextCMOV ) { BB -> addSuccessor ( jcc1MBB ) ; jcc1MBB -> addSuccessor ( copy0MBB ) ; jcc1MBB -> addSuccessor ( sinkMBB ) ; } else { BB -> addSuccessor ( copy0MBB ) ; } BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; if (


<s> rtx op0 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx op1 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx op2 = nds32_read_argument ( exp , <NUM_LIT> ) ; int op0_num = return_p ? <NUM_LIT> : <NUM_LIT> ; int op1_num = return_p ? <NUM_LIT> : <NUM_LIT> ; int op2_num = return_p ? <NUM_LIT> : <NUM_LIT> ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op2_num , op2 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num ,


<s> if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; STI = TM -> getSubtargetImpl ( F ) ; TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID


<s> bool <ISA_LIT>LegalizerInfo :: legalizeBSwap ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_BSWAP ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) == MRI . getType ( ValReg ) ) ; const LLT v2s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s8 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; auto Undef = MIRBuilder . buildUndef (


<s> assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = true ; } else if ( I -> getOpcode ( ) == <STR_LIT> && MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . enableMachinePipeliner ( ) ) { if ( ! Cond . empty ( ) ) return true ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( I -> getOpcode ( ) ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify


<s> static htab_t htab ; unsigned int flags ; unsigned int * * slot ; if ( ! htab ) htab = htab_create ( <NUM_LIT> , htab_hash_pointer , htab_eq_pointer , NULL ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) flags = SECTION_CODE ; else if ( decl && decl_readonly_section ( decl , reloc ) ) flags = <NUM_LIT> ; else { flags = SECTION_WRITE ; if ( decl && TREE_CODE ( decl ) == VAR_DECL && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) flags |= SECTION_PE_SHARED ; } if ( decl && DECL_ONE_ONLY ( decl ) ) flags |= SECTION_LINKONCE ; slot = ( unsigned int * * ) htab_find_slot ( htab ,


<s> default : break ; case TargetOpcode :: COPY : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains


<s> assert ( Kind == Memory && <STR_LIT> ) ; return Mem . IndexReg >= LowR && Mem . IndexReg


<s> if ( ! Subtarget . isTargetLinux ( ) ) return false ; if ( Subtarget . is64Bit ( ) ) { Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT> ; } else


<s> static MachineBasicBlock :: iterator insertDoubleXchange ( MachineBasicBlock :: iterator I ) { MachineBasicBlock * MBB = I -> getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF -> getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned RBX = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned XchgOpc = STI . is64Bit ( )


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupSetCC


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp =


<s> aarch64_layout_frame ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) { if ( from == ARG_POINTER_REGNUM ) return cfun -> machine -> frame . hard_fp_offset ; if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . hard_fp_offset - cfun -> machine -> frame . locals_offset ; } if ( to == STACK_POINTER_REGNUM ) { if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . frame_size - cfun -> machine -> frame . locals_offset ; } return cfun -> machine -> frame


<s> static int getMemoryOpOffset ( const MachineInstr * MI ) { unsigned Opcode = MI -> getOpcode ( ) ; bool isAM3 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; unsigned NumOperands = MI -> getDesc ( ) . getNumOperands ( ) ; unsigned OffField = MI -> getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField * <NUM_LIT> ; int Offset = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> ( OffField ) * <NUM_LIT> ; <STR_LIT> Op = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> (


<s> if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc


<s> if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = static_cast < const MCSectionELF


<s> break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; O << * GetExternalSymbolSymbol ( MO . getSymbolName (


<s> CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if ( STI . isTargetWin64 ( ) || ! STI . isOSWindows ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( getSUBrrOpcode ( Is64Bit ) ) , SP ) . addReg ( SP ) . addReg ( AX ) ; } if (


<s> void addDupAlignedMemory16Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst ,


<s> OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) .


<s> CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF


<s> TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; RCI . runOnMachineFunction ( F ) ; for ( auto & MBB : F


<s> CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else { return false ; } MVT VT


<s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { Mang = new Mangler ( M , <STR_LIT>


<s> else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( LL ) , Dest )

. addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) ; unsigned int alignment = <NUM_LIT> ; unsigned int bitfield_alignment = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) { alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; if ( DECL_BIT_FIELD_TYPE ( field ) ) bitfield_alignment = std :: max ( bitfield_alignment , TYPE_ALIGN ( DECL_BIT_FIELD_TYPE ( field ) ) ) ; } if ( bitfield_alignment > alignment ) { * abi_break = true


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return nullptr


<s> bool <ISA_LIT>ConditionOptimizer :: adjustTo ( MachineInstr * CmpMI , <STR_LIT> Cmp , MachineInstr * To , int ToImm ) { CmpInfo Info = adjustCmp ( CmpMI , Cmp ) ; if ( std :: get < <NUM_LIT> > ( Info ) == ToImm && std :: get < <NUM_LIT> > ( Info ) == To -> getOpcode ( ) ) { modifyCmp ( CmpMI , Info ) ; return true


<s> bool llvm :: checkConvertToNonDenormSingle ( APFloat & ArgAPFloat ) { APFloat APFloatToConvert = ArgAPFloat ; bool LosesInfo = true ; APFloatToConvert . convert ( APFloat :: IEEEsingle ( )

, APFloat :: rmNearestTiesToEven , & LosesInfo ) ;


<s> static inline bool isIndirectBranchOpcode (


<s> tryParseRegisterOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , bool is64BitReg ) { SMLoc S = Parser . getTok (


<s> bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return


<s> bool <ISA_LIT>InstrInfo :: isStackSlotCopy ( const MachineInstr & MI , int & DestFrameIndex , int & SrcFrameIndex ) const { const MachineFrameInfo & MFI = MI . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI . getOpcode ( ) != <STR_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isFI ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isFI ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; int64_t Length = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FI1 = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( MFI . getObjectSize ( FI1 ) != Length || MFI . getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex = FI2 ; return


<s> bool mips_9bit_offset_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && MIPS_9BIT_OFFSET_P ( INTVAL


<s> if ( Cond == <STR_LIT> && isZerosVector ( RHS . getNode ( ) ) && LHS -> getOpcode ( ) == <STR_LIT> && LHS -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) && LHS -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && LHS -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) == Pred ) return LHS -> getOperand ( <NUM_LIT> ) ; return SDValue (


<s> return __builtin_aarch64_lfrintnhfdi (


<s> static int arm_get_strip_length ( int c ) { switch ( c


<s> else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) res = <NUM_LIT> ; else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) res = <NUM_LIT> ; else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) res = <NUM_LIT> ; else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand


<s> rtx pat = PATTERN ( insn ) ; return GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , <NUM_LIT> )


<s> return static_cast < <ISA_LIT>TargetMachine & > (


<s> return ! MFI . hasCalls ( ) && ! MRI . isPhysRegUsed ( <STR_LIT> ) && !

MRI . isPhysRegUsed ( <STR_LIT> ) && ! hasFP ( MF ) ;


<s> OriginalRetWasFloatVector . push_back ( originalEVTTypeIsVectorFloat ( ArgVT


<s> MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneUse ( CondDefReg ) ) { for ( auto UI = MRI . use_instr_begin ( CondDefReg ) , UE = MRI . use_instr_end ( ) ; UI != UE ; ++ UI ) { if ( CondDef == & * UI ) continue ; if ( UI -> getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { CondCode = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( ! emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; unsigned CmpOpc = selectFCMPOpc ( * CondDef ,


<s> const char * load_string ; int r ; if ( GET_CODE ( mem ) == FLOAT_EXTEND || GET_CODE ( mem ) == ZERO_EXTEND ) { mem = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; } if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == <NUM_LIT> ) ; reg = SUBREG_REG ( reg ) ; } if ( ! REG_P ( reg ) ) fatal_insn ( <STR_LIT> , reg ) ; r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_DFORM_SCALAR ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : load_string = <STR_LIT> ; break ; case E_HImode : load_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode : load_string = <STR_LIT>


<s> if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles


<s> case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_LO ) ; return true ; case <STR_LIT> : unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_HI ) ; else if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_LO ) ; else report_fatal_error ( <STR_LIT> ) ; return true


<s> if ( IsIndirect ) assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return BuildMI ( * MBB , MBB -> erase ( & MI ) , DL , TII -> get ( TargetOpcode :: DBG_VALUE ) , IsIndirect , VReg


<s> case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMUL_LOHI ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRotate ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , Subtarget , DAG ) ; case


<s> static bool ix86_libgcc_floating_mode_supported_p ( scalar_float_mode mode ) { return ( ( ( mode == HFmode || mode == BFmode )


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ! VT . isFloatingPoint ( ) && VT . getSimpleVT ( ) != <STR_LIT> && VT . getSimpleVT ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned )


<s> } if ( PointerType * Ty = dyn_cast < PointerType > ( V -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: Alloca : { const AllocaInst * A = cast < AllocaInst > ( V ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) { AM . Disp = (


<s> virtual const TargetData * getTargetData ( ) const { return &


<s> bool <ISA_LIT>ShortenInst :: runOnMachineFunction ( MachineFunction & F ) { const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB


<s> unsigned UseIdx ; for ( UseIdx = <NUM_LIT> ; UseIdx < UseMI -> getNumOperands ( ) ; ++ UseIdx ) if ( UseMI -> getOperand ( UseIdx ) . isReg ( ) && UseMI -> getOperand ( UseIdx ) . getReg ( ) == Reg ) break ; assert ( UseIdx < UseMI -> getNumOperands ( ) && <STR_LIT> ) ; assert ( UseIdx < UseMCID . getNumOperands ( ) && <STR_LIT> ) ; const MCOperandInfo * UseInfo = & UseMCID . OpInfo [ UseIdx ] ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else


<s> SET_TYPE_MODE ( float128t_type_node , TYPE_MODE ( float128_type_node ) ) ; } ( * lang_hooks . types . register_builtin_type ) ( float128t_type_node , <STR_LIT> ) ; ftype = build_function_type_list ( float128t_type_node , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_INFQ , BUILT_IN_MD , NULL , NULL_TREE ) ; ia64_builtins [ IA64_BUILTIN_INFQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_HUGE_VALQ , BUILT_IN_MD , NULL , NULL_TREE ) ; ia64_builtins [ IA64_BUILTIN_HUGE_VALQ ] = decl ; ftype = build_function_type_list ( float128t_type_node , const_string_type , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_NANQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ia64_builtins [ IA64_BUILTIN_NANQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_NANSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ia64_builtins [ IA64_BUILTIN_NANSQ ] = decl ; ftype = build_function_type_list ( float128t_type_node , float128t_type_node , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_FABSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ia64_builtins [ IA64_BUILTIN_FABSQ ] = decl ; ftype = build_function_type_list ( float128t_type_node , float128t_type_node , float128t_type_node , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_COPYSIGNQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ia64_builtins [ IA64_BUILTIN_COPYSIGNQ ] = decl ; } else ( * lang_hooks . types . register_builtin_type ) ( long_double_type_node , <STR_LIT> ) ; vms_patch_builtins ( ) ; add_builtin_function ( ( name ) , ( type ) , ( code ) , BUILT_IN_MD , \ NULL , NULL_TREE ) decl = def_builtin ( <STR_LIT> , build_function_type_list ( ptr_type_node , NULL_TREE ) , IA64_BUILTIN_BSP ) ; ia64_builtins [ IA64_BUILTIN_BSP ] = decl ; decl = def_builtin ( <STR_LIT> , build_function_type_list ( void_type_node , NULL_TREE ) , IA64_BUILTIN_FLUSHRS ) ; ia64_builtins [ IA64_BUILTIN_FLUSHRS ] = decl ; if ( TARGET_HPUX ) { if ( ( decl = builtin_decl_explicit ( BUILT_IN_FINITE ) ) != NULL_TREE ) set_user_assembler_name (


<s> unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg ) ; if ( ResultReg == <NUM_LIT> ) return false ; UpdateValueMap ( I , ResultReg ) ; return true ; } return


<s> MachineIRBuilder MIB ( I ) ; Register TargetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto JumpTableInst = MIB . buildInstr ( <STR_LIT> , { TargetReg , ScratchReg } , { JTAddr , Index } ) . addJumpTableIndex ( JTI ) ; MIB . buildInstr ( <STR_LIT> , { } , { TargetReg } ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * JumpTableInst , TII


<s> } else { rtx const_reg ; rtx insn ; int temp = epilogue_p ? <NUM_LIT> : <NUM_LIT> ; int i ; if ( epilogue_p < <NUM_LIT> || current_function_interrupt || ! call_really_used_regs [ temp ] || fixed_regs [ temp ] ) temp = - <NUM_LIT> ; if ( temp < <NUM_LIT> && ! current_function_interrupt && epilogue_p >= <NUM_LIT> ) { HARD_REG_SET temps ; COPY_HARD_REG_SET ( temps , call_used_reg_set ) ; AND_COMPL_HARD_REG_SET ( temps , call_fixed_reg_set ) ; if ( epilogue_p > <NUM_LIT> ) { int nreg = <NUM_LIT> ; if ( crtl -> return_rtx ) { machine_mode mode ; mode = GET_MODE ( crtl -> return_rtx ) ; if ( BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) nreg = HARD_REGNO_NREGS ( FIRST_RET_REG , mode ) ; } for ( i = <NUM_LIT> ; i < nreg ; i ++ ) CLEAR_HARD_REG_BIT ( temps , FIRST_RET_REG + i ) ; if ( crtl -> calls_eh_return ) { CLEAR_HARD_REG_BIT ( temps , EH_RETURN_STACKADJ_REGNO ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) CLEAR_HARD_REG_BIT ( temps , EH_RETURN_DATA_REGNO ( i ) ) ; } } if ( epilogue_p <= <NUM_LIT> ) { for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) { HARD_REG_SET temps ; COPY_HARD_REG_SET ( temps , * live_regs_mask ) ; CLEAR_HARD_REG_BIT ( temps , REGNO ( reg ) ) ; temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> ) { rtx adj_reg , tmp_reg , mem ; gcc_assert ( epilogue_p ) ; gcc_assert ( ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] ) ; adj_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; tmp_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; emit_move_insn ( gen_tmp_stack_mem ( Pmode , reg ) , adj_reg ) ; emit_insn ( GEN_MOV ( adj_reg , GEN_INT ( size ) ) ) ; emit_insn ( GEN_ADD3 ( adj_reg , adj_reg , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg


<s> aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; if ( USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p


<s> int eligible_for_sibcall_delay ( rtx trial ) { rtx pat ; if ( GET_CODE ( trial ) != INSN || GET_CODE ( PATTERN ( trial ) ) != SET ) return <NUM_LIT> ; if ( get_attr_length ( trial ) != <NUM_LIT> ) return <NUM_LIT> ; pat = PATTERN ( trial ) ; if ( sparc_leaf_function_p ) { if ( LEAF_SIBCALL_SLOT_RESERVED_P ) return <NUM_LIT> ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , pat ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= <NUM_LIT> && REGNO ( SET_DEST ( pat ) ) < <NUM_LIT> ) || REGNO ( SET_DEST ( pat ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , <NUM_LIT> ) ,


<s> const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; if ( MCID . getOpcode ( ) == <STR_LIT> ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDead ( true ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID .


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; bool IsEHFuncletEpilogue = MBBI == MBB . end ( ) ? false : isFuncletReturnInstr ( * MBBI ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int FIOffset ; unsigned BasePtr ; if ( MI . isReturn ( ) ) { assert ( ( ! needsStackRealignment ( MF ) || MF . getFrameInfo ( ) . isFixedObjectIndex ( FrameIndex ) ) && <STR_LIT> ) ; FIOffset = TFI -> getFrameIndexReferenceSP ( MF , FrameIndex , BasePtr , <NUM_LIT> ) ; } else if ( TFI -> Is64Bit && ( MBB . isEHFuncletEntry ( ) || IsEHFuncletEpilogue ) ) { FIOffset = TFI -> getWin64EHFrameIndexRef ( MF , FrameIndex , BasePtr ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) ; } unsigned Opc = MI . getOpcode ( ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( FIOffset ) ; return ; } unsigned MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP ||


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel (


<s> const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( )


<s> MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } else { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else { MI . setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) ; } if ( setLR ) MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT>

, RegState :: Implicit ) . addReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegState :: ImplicitDefine ) ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo (


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv2di ( ( int64x2_t )


<s> return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSUBCombine ( N , DAG , DCI , Subtarget


<s> unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { tree default_decl ; gimple ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = <NUM_LIT> ; unsigned int actual_versions = <NUM_LIT> ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= <NUM_LIT> ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - <NUM_LIT> ) ) ; default_decl = ( * fndecls ) [ <NUM_LIT> ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = <NUM_LIT> ; fndecls -> iterate ( ix


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } } ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend


<s> static bool matchRegisterNameHelper ( MCRegister & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; return RegNo ==


) _xsaves64 ( void * __P , long long __M ) {


<s> bool <ISA_LIT>TargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { APInt MulC ; if ( ! <STR_LIT> ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; if ( isOperationLegal ( <STR_LIT> , VT )


<s> if ( ( TREE_CODE ( decl_op1 ) == VAR_DECL || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( TREE_CODE ( decl_op0 ) == VAR_DECL || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; } return true


<s> gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return


<s> auto SetOffset = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; auto PCC = DAG . getNode ( <STR_LIT> , DL , CapType , GetPCC ) ; return DAG . getNode ( <STR_LIT> , DL , CapType


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList


<s> bool haveFeatures ( FeatureBitset ActiveFeatures ) const { return ( FeaturesRequired & ActiveFeatures )


<s> switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm

( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ;


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT>


<s> static DecodeStatus DecodeShiftLeftImm16 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val > <NUM_LIT> ) return MCDisassembler


<s> const <STR_LIT> InvCC = changeICMPPredTo<ISA_LIT>CC ( CmpInst :: getInversePredicate ( ( CmpInst :: Predicate ) Pred ) ) ; auto I = MIRBuilder . buildInstr ( <STR_LIT> , { DefReg } , { Register ( <STR_LIT> ) , Register ( <STR_LIT> ) } ) . addImm ( InvCC ) ; constrainSelectedInstRegOperands ( * I , TII


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI ,

const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return


<s> if ( ! Mul ) { Mul = Op0L -> getOperand ( <NUM_LIT> ) ; if ( Mul -> getOpcode ( ) != <STR_LIT> || Mul . getValueType ( ) . getVectorNumElements ( ) != <NUM_LIT> * e ) return SDValue ( ) ; } if ( Mul != Op0L -> getOperand ( <NUM_LIT> ) || Mul != Op1L -> getOperand ( <NUM_LIT> ) || Mul != Op0H -> getOperand ( <NUM_LIT> ) || Mul != Op1H -> getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } ShrinkMode Mode ; if ( ! canReduceVMulWidth ( Mul . getNode ( ) , DAG , Mode ) || Mode == MULU16 ) return SDValue ( ) ; auto PMADDBuilder = [ ] ( SelectionDAG & DAG , SDLoc DL , SDValue Op0 , SDValue Op1 ) { EVT InVT = Op0 . getValueType ( ) ; assert ( InVT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( InVT == Op1 . getValueType ( ) && <STR_LIT> ) ; EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) / <NUM_LIT> ) ; EVT TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , DAG . getNode ( <STR_LIT> , DL , TruncVT , Op0 ) , DAG . getNode ( <STR_LIT> , DL , TruncVT , Op1 ) ) ; } ; return SplitBinaryOpsAndApply ( DAG , Subtarget , DL , VT , Mul . getOperand ( <NUM_LIT>

) , Mul . getOperand ( <NUM_LIT> ) , PMADDBuilder ) ;


<s> gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? <NUM_LIT> :


<s> static const unsigned EhDataReg64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return IsN64 ( ) ? EhDataReg64 [ I ] : EhDataReg [


<s> if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset , PtrVT ) ) ; } MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else CalculateTailCallArgDest ( DAG , MF , is<ISA_LIT>64 , Arg , SPDiff , ArgOffset ,


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed =


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; if ( const auto * Entry = CostTableLookup ( CostTbl , ISDOpcode , LT . second ) ) return LT . first * Entry -> Cost ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( LT . second == <STR_LIT> && Op2Info == TargetTransformInfo :: OK_UniformConstantValue ) Cost += <NUM_LIT> ; return Cost ; } auto LooksLikeAFreeShift = [ & ]


<s> set_optab_libfunc ( smin_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( smax_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( sqrt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( abs_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode ,


<s> if ( TII . isPredicable ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , &


<s> case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; } return true


<s> ValueToEmit = ( ValueToEmit << <NUM_LIT> ) | ValueBuffer [ i ] ; } ValueToEmit <<= ( CurrentAlignmentToValue - ValueBuffer . size ( ) ) * <NUM_LIT> ; EmitValueWithAlignment ( MCConstantExpr :: create ( ValueToEmit , getContext ( ) ) , CurrentAlignmentToValue ) ; ValueBuffer . clear


<s> return ( uint8x8_t ) __builtin_neon_vqshrnu_nv8hi ( ( int16x8_t


<s> int getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx ,


<s> if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors ( ) ) return false ; return isLegalElementTypeForSVE ( DataType -> getScalarType ( )


<s> Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; if ( VT == <STR_LIT> ) Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; unsigned AssignedReg = FuncInfo . ValueMap [


<s> static void mips_promote_ready ( rtx_insn * * ready , int lower , int higher ) { rtx_insn * new_head ; int i


<s> SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; if ( V1 -> getOpcode ( ) != <STR_LIT> || V2 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand (

<NUM_LIT> ) != LHS ) ) return SDValue ( ) ;


<s> if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 && DstVT != <STR_LIT> ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; Align SlotAlign ( <NUM_LIT> ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MPI , SlotAlign ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , SlotAlign ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( DstVT , <STR_LIT> , dl , Store2 , StackSlot , MPI , SlotAlign , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , SlotAlign ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MPI , SlotAlign , MachineMemOperand :: MOLoad ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; APInt FF ( <NUM_LIT>


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> uint64_t Disp = Imm & <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp << <NUM_LIT> ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler


<s> TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo


<s> unsigned ResultReg ; if ( I -> getOpcode ( ) == Instruction :: Add ) ResultReg = emitAdd ( VT , I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ; else if ( I -> getOpcode ( ) == Instruction :: Sub ) ResultReg = emitSub ( VT , I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ; else llvm_unreachable (


<s> } else if ( DEFAULT_ABI == ABI_V4 ) { if ( abi_v4_pass_in_fpr ( mode , named ) ) { if ( mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; if ( cum -> fregno + ( FLOAT128_2REG_P ( mode ) ? <NUM_LIT> : <NUM_LIT> ) <= FP_ARG_V4_MAX_REG ) cum -> fregno += ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) >> <NUM_LIT> ; else { cum -> fregno = FP_ARG_V4_MAX_REG + <NUM_LIT> ; if ( mode == DFmode || FLOAT128_IBM_P ( mode ) || mode == DDmode || mode == TDmode ) cum -> words += cum -> words & <NUM_LIT> ; cum -> words += rs6000_arg_size ( mode , type ) ; } } else { int n_words = rs6000_arg_size ( mode , type ) ; int gregno = cum -> sysv_gregno ; if ( n_words == <NUM_LIT> ) gregno += ( <NUM_LIT> - gregno ) & <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> > GP_ARG_MAX_REG ) { if ( n_words == <NUM_LIT> ) cum -> words += cum -> words & <NUM_LIT> ; cum -> words += n_words ; } cum -> sysv_gregno = gregno + n_words ; } if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cum -> words , cum -> fregno ) ; fprintf ( stderr , <STR_LIT> , cum -> sysv_gregno , cum -> nargs_prototype , cum -> prototype ) ; fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( mode ) , named ) ; } } else { int n_words = rs6000_arg_size ( mode , type ) ; int start_words = cum -> words ; int align_words = rs6000_parm_start ( mode , type , start_words ) ; cum -> words = align_words + n_words ; if ( SCALAR_FLOAT_MODE_P ( elt_mode ) && TARGET_HARD_FLOAT ) { if ( elt_mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; cum -> fregno += n_elts * ( ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ) ; } if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cum -> words ,


<s> setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv1 , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed


<s> rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_mentioned_p ( x , * pinsn


<s> if ( cfun -> machine -> sdmode_stack_slot != NULL_RTX

) instantiate_decl_rtl ( cfun -> machine -> sdmode_stack_slot ) ;


<s> TPNumElements = VCTP -> getOperand ( <NUM_LIT> ) ; MCRegister NumElements = TPNumElements . getReg ( ) . asMCReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StartInsertPt != StartInsertBB -> end ( ) && ! RDA . isReachingDefLiveOut ( & * StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( StartInsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , & * StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; StartInsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , & * StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { MachineOperand Operand = ElemDef -> getOperand ( <NUM_LIT> ) ; if ( isMovRegOpcode ( ElemDef -> getOpcode ( ) ) && RDA . getUniqueReachingMIDef ( ElemDef , Operand . getReg ( ) . asMCReg ( ) ) == RDA . getUniqueReachingMIDef ( & * StartInsertPt , Operand . getReg ( ) . asMCReg ( ) ) ) { TPNumElements = Operand ; NumElements = TPNumElements . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , MCRegister NumElements ) { if ( MBB -> empty ( ) ) return false ; if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> bool <ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return


<s> MVT VT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; ( void ) VT ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Result = Op ; if ( false ) { } else { SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue PackedElt = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { Vec , HalfIdx } ) , <NUM_LIT> ) ; SDValue AndIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { AndIdx , Const1 } ) ; SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Shift } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; SDValue SubI32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Result = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , PackedElt , SubI32 ) , <NUM_LIT> ) ; if ( Op . getSimpleValueType ( ) == <STR_LIT> ) { Result = DAG . getBitcast ( <STR_LIT> , Result ) ; }


<s> if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMSUB ( N ,

& DAG ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> else { MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , CSI [ CSIIndex ] . getFrameIdx ( ) ) ) ; RestoreOp = <STR_LIT> ; MoveReg = <STR_LIT> ; } if ( CR2Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR3Spilled && ! CR4Spilled ) ) ) ; if ( CR3Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR4Spilled ) ) ) ; if ( CR4Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg (

MoveReg , getKillRegState ( true ) ) ) ;


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MBB -> erase


<s> APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op1 , Op1 . getScalarValueSizeInBits ( ) , UndefElts , EltBits , false , false ) ) if ( llvm :: all_of ( EltBits , [ ] ( APInt & I ) { return I . isSignMask ( ) ; } ) ) return peekThroughBitcasts ( Op . getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> const MCExpr * getImm ( ) const { assert ( Kind == Immediate && <STR_LIT> ) ; return Imm . Val


<s> static DecodeStatus DecodeGRH32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const


<s> if ( mode == CImode ) return ( aarch64_offset_7bit_signed_scaled_p ( TImode , offset ) && ( offset_9bit_signed_unscaled_p ( V16QImode , offset + <NUM_LIT> ) || offset_12bit_unsigned_scaled_p ( V16QImode , offset + <NUM_LIT> ) ) ) ; if ( mode == XImode ) return ( aarch64_offset_7bit_signed_scaled_p ( TImode , offset ) && aarch64_offset_7bit_signed_scaled_p ( TImode , offset + <NUM_LIT> ) ) ; if ( load_store_pair_p ) return ( ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) && aarch64_offset_7bit_signed_scaled_p ( mode , offset ) ) ; else return ( offset_9bit_signed_unscaled_p ( mode , offset ) || offset_12bit_unsigned_scaled_p ( mode , offset ) ) ; } if ( allow_reg_index_p ) { if ( aarch64_base_register_rtx_p ( op0 , strict_p ) && aarch64_classify_index ( info , op1 , mode , strict_p ) ) { info -> base = op0 ; return true ; } if ( aarch64_base_register_rtx_p ( op1 , strict_p ) && aarch64_classify_index ( info , op0 , mode , strict_p ) ) { info -> base = op1 ; return true ; } } return false ; case POST_INC : case POST_DEC : case PRE_INC : case PRE_DEC : info -> type = ADDRESS_REG_WB ; info -> base = XEXP ( x , <NUM_LIT> ) ; info -> offset = NULL_RTX ; return aarch64_base_register_rtx_p ( info -> base , strict_p ) ; case POST_MODIFY : case PRE_MODIFY : info -> type = ADDRESS_REG_WB ; info -> base = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , info -> base ) && aarch64_base_register_rtx_p ( info -> base , strict_p ) ) { HOST_WIDE_INT offset ; info -> offset = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; offset = INTVAL ( info -> offset ) ; if ( mode == TImode || mode == TFmode ) return ( aarch64_offset_7bit_signed_scaled_p ( mode , offset ) && offset_9bit_signed_unscaled_p ( mode , offset ) ) ; if ( load_store_pair_p ) return ( ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) && aarch64_offset_7bit_signed_scaled_p ( mode , offset ) ) ; else return offset_9bit_signed_unscaled_p ( mode , offset ) ; } return false ; case CONST : case SYMBOL_REF : case LABEL_REF : info -> type = ADDRESS_SYMBOLIC ; if ( ! load_store_pair_p && GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) { rtx sym , addend ; split_const ( x , & sym , & addend ) ; return ( ( GET_CODE ( sym ) == LABEL_REF || ( GET_CODE ( sym ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( sym ) && ! aarch64_nopcrelative_literal_loads ) ) ) ; } return false ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> base = XEXP (


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: AddOptionalDefs ( const MachineInstrBuilder & MIB ) { MachineInstr * MI = & * MIB ; if ( TII . isPredicable ( MI ) || is<ISA_LIT>NEONPred ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR ) AddDefaultT1CC ( MIB ) ; else AddDefaultCC ( MIB ) ; } return MIB


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) { SDValue ResNode ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; Constant * C = N -> getConstVal ( ) ; SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; ResNode = DAG . getNode ( <STR_LIT> ,


<s> else if ( mips_abi == ABI_64 ) d_add_builtin_version ( <STR_LIT> ) ; else if ( mips_abi == ABI_O64 ) d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT_ABI ) { d_add_builtin_version ( <STR_LIT> ) ; d_add_builtin_version ( <STR_LIT> ) ; } else if ( TARGET_SOFT_FLOAT_ABI ) { d_add_builtin_version ( <STR_LIT> ) ; d_add_builtin_version ( <STR_LIT>


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= RC -> getSize ( ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) )

, FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> return __builtin_neon_vbfcvtsf ( __a )


<s> Y = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; Y = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X , Y ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , X ) ; return X


<s> } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl ) ; cfun -> is_thunk = true ; first_function_block_is_cold = false ; final_start_function ( emit_barrier ( ) , asm_out_file , <NUM_LIT> ) ; if ( TARGET_PAD_SHORT_FUNCTION ) { int i = <NUM_LIT> ; while ( i -- ) fputs ( <STR_LIT> , asm_out_file ) ; } xops [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , regno ) ; xops [ <NUM_LIT> ] = gen_rtx_MEM ( Pmode , stack_pointer_rtx ) ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file ) ; final_end_function ( ) ; init_insn_lengths ( ) ; free_after_compilation ( cfun ) ; set_cfun ( NULL


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getReg (


<s> static const char * ix86_mangle_fundamental_type ( tree type ) { switch ( TYPE_MODE ( type ) ) { case TFmode : return <STR_LIT> ; case XFmode : return <STR_LIT> ; default : return NULL


<s> assert ( Cond . empty ( ) && ! FBB && TBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT>


<s> SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { assert ( Subtarget -> hasSSE2 ( ) && ! Subtarget -> hasSSE41 ( ) && <STR_LIT> ) ; const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getNode ( <STR_LIT> , dl , VT , Evens ) ; Odds = DAG . getNode ( <STR_LIT> , dl , VT , Odds ) ; const int ShufMask [ ] = { <NUM_LIT>


<s> MIB = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addUse ( ArgsAddrReg ) . addUse ( ListReg ) . addImm ( <NUM_LIT> ) . addMemOperand ( * I . memoperands_begin ( ) ) ; constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> } if ( isOverflowIntrOpRes ( LHS ) && isOneConstant ( RHS ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , LHS . getValue ( <NUM_LIT> ) , DAG ) ; if ( CC == <STR_LIT> ) OFCC = getInvertedCondCode ( OFCC ) ; SDValue CCVal = DAG . getConstant ( OFCC , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , CCVal , Overflow ) ; } if ( LHS . getValueType ( ) . isInteger ( ) ) { assert ( ( LHS . getValueType ( ) == RHS . getValueType ( ) ) && ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ) ; const ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> && ProduceNonFlagSettingCondBr ) { if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode (


<s> rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; num_use_regs = Re - Rb + <NUM_LIT> + <NUM_LIT> ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + <NUM_LIT> ) ) ; par_index = <NUM_LIT> ; offset = - ( num_use_regs * <NUM_LIT> ) ; for ( regno = Rb ; regno <= Re ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index )


<s> auto & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; auto Opc = toDirectCall ( MI -> getOpcode ( ) ) ; auto MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TII . get ( Opc ) ) . addGlobalAddress ( Callee ) ; auto RemainingOps = make_range ( MI -> operands_begin ( ) + <NUM_LIT> , MI -> operands_end ( ) ) ; for ( auto & Op : RemainingOps ) MIB . add (