<s> assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( &


<s> HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PostRAScheduler = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG =


<s> b = ( __vector unsigned short ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t


<s> SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = TLI . getDataLayout ( ) -> getABITypeAlignment ( EltVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( NewAlign > Align || ! TLI . isOperationLegalOrCustom ( <STR_LIT> , EltVT ) ) return SDValue ( ) ; SDLoc dl (


<s> case 'Y' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasFp256 ( ) ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt >


<s> static void AnalyzeReturnValues ( CCState & State , SmallVectorImpl < CCValAssign >

& RVLocs , const SmallVectorImpl < ArgT > & Args ) {


<s> ShuffleVectorSDNode * Shuffle = cast < ShuffleVectorSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; EVT SrcType = Shuffle -> getValueType ( <NUM_LIT> ) ; if ( ! Shuffle -> getOperand ( <NUM_LIT> ) -> isUndef ( ) ) return SDValue ( ) ; unsigned SrcSize = SrcType . getScalarSizeInBits ( ) ; unsigned NumElems = SrcType . getVectorNumElements ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Vector -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) ) return SDValue ( ) ; unsigned ResSize = N1 . getValueType ( ) . getScalarSizeInBits ( ) ; if ( SplatBitSize > ResSize || ( SplatValue + <NUM_LIT> ) . exactLogBase2 ( ) != ( int ) SrcSize ) return SDValue ( ) ; if ( SrcSize >= ResSize || ResSize % SrcSize ) return SDValue ( ) ; unsigned ZextRatio = ResSize / SrcSize ; bool IsZext = true ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( i % ZextRatio ) { if ( Shuffle -> getMaskElt ( i ) > <NUM_LIT> ) { IsZext = false ; break ; } } else


<s> int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: cpu0 , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> bool Indirect = gvNeedsNonLazyPtr ( RelocOp -> getGlobal ( ) ) ; emitGlobalAddress ( RelocOp -> getGlobal ( ) , rt , RelocOp -> getOffset ( ) , PCAdj , NeedStub , Indirect ) ; } else if ( RelocOp -> isCPI ( ) ) { unsigned rt = Is64BitMode ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( RelocOp -> getIndex ( ) , rt , RelocOp -> getOffset ( ) , PCAdj ) ; } else if ( RelocOp -> isJTI ( ) ) { unsigned rt = Is64BitMode ? <STR_LIT> : <STR_LIT> ; emitJumpTableAddress ( RelocOp -> getIndex ( ) ,


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - <NUM_LIT> ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } if ( ! hasD32 ( ) && RegNum >= <STR_LIT> && RegNum


<s> if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ExtType = <STR_LIT> ; else if ( LoadNode -> getExtensionType ( ) == <STR_LIT> || LoadNode -> getExtensionType ( ) == <STR_LIT> ) ExtType = <STR_LIT> ; else return SDValue ( ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , DL , LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) , MachinePointerInfo ( ) ) ; SDValue Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , DL


<s> } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeT2AddrModeImm8 ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> for ( auto & Val : SupportedValues ) if ( Val == Query .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem


<s> bool AffectsGrouping = ( SC -> isValid ( ) && ( SC ->


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case


<s> MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get (

<STR_LIT> ) ) , UnwindHelpFI ) . addImm ( - <NUM_LIT> ) ;


<s> SmallString < <NUM_LIT> > Name ; StringRef Prefix = <STR_LIT> ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else { TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first . first , TM ) ) ; } OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first . first , I . first . second ) ; } for ( const auto * GV : TOCDataGlobalVars


<s> Parms = <STR_LIT> ; break ; case FDSig : Parms = <STR_LIT> ; break ; case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer . AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer . PushSection ( ) ; const MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer . SwitchSection ( M , nullptr ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbol * Stub = OutContext . GetOrCreateSymbol ( StringRef ( x ) ) ; TS . emitDirectiveEnt (


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x

, <NUM_LIT> ) ) == UNSPEC ) return true ;


<s> StringRef getSymName ( ) { return SymName


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i64gather_ps ( float const * base , __m128i index , const int scale ) { __v4sf src =


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg ==


<s> OS << <STR_LIT> << Attribute << <STR_LIT> << Twine (


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; return


<s> mi -> getOperand ( <NUM_LIT> ) . setIsUndef ( mi -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; mi -> RemoveOperand ( <NUM_LIT> ) ; mi -> setDesc ( TII -> get ( TargetOpcode :: COPY ) ) ; ( -- getIterForMI ( MI ) ) -> eraseFromParent ( ) ; goto reloop ; } } outs ( ) << <STR_LIT> ; outs ( ) << MBB << <STR_LIT> ; outs ( ) . flush ( ) ; } spilledRegisters . clear ( ) ; BEGINNING : for ( LiveRange * LR : interferenceGraph ) { delete LR ; } interferenceGraph . clear ( ) ; interferenceGraphRetrieval . clear ( ) ; livenessInformation . clear ( ) ; phiNodes . clear ( ) ; calcGlobalLivenessInfo ( MF , regInfo ) ; if ( interferenceGraph . size ( ) > <NUM_LIT> && color ( MF , regInfo ) == EXIT_STATUS_T :: SPILLED ) { goto BEGINNING ; } for ( MachineInstr * MI : getPhiNodes ( ) ) { MI -> eraseFromParent ( ) ; } MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: NoPHIs ) ; MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ; outs ( ) << <STR_LIT> ; for ( auto & MBB : MF ) { outs ( ) << <STR_LIT> ; outs ( ) <<


<s> SMShadowTracker . emitShadowPadding ( OutStreamer , getSubtargetInfo ( )


<s> case V2DFmode : return gen_aarch64_rsqrte_v2df2 ; case V2SFmode : return gen_aarch64_rsqrte_v2sf2 ; case V4SFmode : return gen_aarch64_rsqrte_v4sf2 ; default : gcc_unreachable (


<s> LEONMachineFunctionPass ( char & ID ) ; int GetRegIndexForOperand ( MachineInstr & MI , int OperandIndex ) ; void clearUsedRegisterList ( ) ; void markRegisterUsed (


<s> tree result = fold_convert ( type , expr ) ; bool maybe_const =


<s> mp -> value = fix -> value ; mp -> refcount = <NUM_LIT> ; mp -> min_address = - <NUM_LIT> ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head =


<s> bits = vec_sl ( vec_and ( ( vec_uchar16 ) ( a ) , vec_splat_u8 ( <NUM_LIT> ) ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> Value * <ISA_LIT>IREmitter :: visitPCMPEQ ( const SDNode


<s> EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue SrcBC = peekThroughBitcasts ( Src ) ; if ( <STR_LIT> == SrcBC . getOpcode ( ) ) { SDValue SrcOp = SrcBC . getOperand ( <NUM_LIT> ) ; if ( SrcOp . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , SrcOp ) ; } if ( SrcBC . getOpcode ( ) == <STR_LIT> && SrcBC . hasOneUse ( ) ) { auto * MemIntr = cast < MemIntrinsicSDNode > ( SrcBC ) ; unsigned SrcBCWidth = SrcBC . getScalarValueSizeInBits ( ) ; if ( MemIntr -> getMemoryVT ( ) . getSizeInBits ( ) == SrcBCWidth && VT . getSizeInBits ( ) == SrcBCWidth ) { SDValue Load = DAG . getLoad ( VT , dl , MemIntr -> getChain ( ) , MemIntr -> getBasePtr ( ) , MemIntr -> getPointerInfo ( ) , MemIntr -> getAlignment ( ) , MemIntr -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( MemIntr , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } if ( <STR_LIT> == Src . getOpcode ( ) && SrcVT . is128BitVector ( ) && isNullConstant ( Idx ) ) { Src = extract128BitVector ( Src . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , dl ) ; Src = DAG . getBitcast ( SrcVT , Src ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , VT , Src , Idx ) ; } SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( ! getTargetShuffleInputs ( SrcBC , Ops , Mask , DAG )


<s> static rtx legitimize_tls_address ( rtx addr ) { rtx ret , tmp , t1 , t2 , tp ; rtx_insn * insn ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return addr ; switch ( SYMBOL_REF_TLS_MODEL ( addr ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_reg_rtx ( Pmode ) ; if ( flag_pic ) emit_insn ( gen_tgd_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tgd_load ( tmp , addr ) ) ; ret = hppa_tls_call ( tmp ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : ret = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( Pmode ) ; start_sequence ( ) ; if ( flag_pic ) emit_insn ( gen_tld_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tld_load ( tmp , addr ) ) ; t1 = hppa_tls_call ( tmp ) ; insn = get_insns ( ) ; end_sequence (


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { AttrEmitter = new AsmAttributeEmitter ( OutStreamer ) ; emitFPU = true ; } else { MCObjectStreamer & O = static_cast < MCObjectStreamer & > ( OutStreamer ) ; AttrEmitter = new ObjectAttributeEmitter ( O ) ; } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> ,


<s> assert ( false && <STR_LIT> ) ; return


<s> } if ( ( flag_pic == <NUM_LIT> && rs1 == pic_offset_table_rtx && ! REG_P ( rs2 ) && GET_CODE ( rs2 ) != SUBREG && GET_CODE ( rs2 ) != LO_SUM && GET_CODE ( rs2 ) != MEM && ! SPARC_SYMBOL_REF_TLS_P ( rs2 ) && ( ! symbolic_operand ( rs2 , VOIDmode ) || mode == Pmode ) && ( GET_CODE ( rs2 ) != CONST_INT || SMALL_INT ( rs2 ) ) ) || ( ( REG_P ( rs1 ) || GET_CODE ( rs1 ) == SUBREG ) && RTX_OK_FOR_OFFSET_P ( rs2 ) ) ) { imm1 = rs2 ; rs2 = NULL ; } else if ( ( REG_P ( rs1 ) || GET_CODE ( rs1 ) == SUBREG ) && ( REG_P ( rs2 ) || GET_CODE ( rs2 ) == SUBREG ) ) { if ( mode == TFmode && ! ( TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || SPARC_SYMBOL_REF_TLS_P ( rs1 ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || SPARC_SYMBOL_REF_TLS_P ( rs1 ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ; else return <NUM_LIT> ; if ( GET_CODE ( rs1 ) == SUBREG ) rs1 = SUBREG_REG ( rs1 ) ; if ( ! REG_P ( rs1 ) ) return <NUM_LIT> ; if ( rs2 ) { if ( GET_CODE ( rs2 ) == SUBREG ) rs2 = SUBREG_REG ( rs2 ) ; if ( ! REG_P ( rs2 ) ) return


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp , InVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( NumElts / <NUM_LIT> + <NUM_LIT> ) ) ; } else { InVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; SDValue VecOp2 = DAG . getNode ( <STR_LIT>


<s> MCAsmBackend * llvm :: create<ISA_LIT>_64AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX ( ) && ! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new NaCl<ISA_LIT>_64AsmBackend ( T , OSABI , CPU ) ; return new ELF<ISA_LIT>_64AsmBackend ( T ,


<s> assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI . getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI . killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , ScratchFPReg , I ) ; }


<s> assert ( ! DAG . getTarget ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , <STR_LIT> ) , DAG . getConstant ( ArgMode , <STR_LIT> ) , DAG . getConstant ( Align , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue (


<s> static inline bool isMatchingDecrement ( MachineInstr * MI , unsigned Base , unsigned Bytes , unsigned Limit , <STR_LIT> Pred , unsigned PredReg ) { unsigned MyPredReg = <NUM_LIT> ; if ( ! MI ) return false ; if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) )


<s> MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP , CloserWater ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } const unsigned Align = isThumb ? <NUM_LIT> : <NUM_LIT> ; if ( NewMBB -> getAlignment ( ) < Align ) NewMBB -> setAlignment ( Align ) ; if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . add ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex ( ID ) ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << ID << <STR_LIT> << CPI << format ( <STR_LIT> , BBInfo [ NewIsland -> getNumber ( ) ] . Offset ) ) ; return true


<s> struct simd_immediate_info info = { NULL_RTX , <NUM_LIT> , <NUM_LIT> , false , false } ; is_valid = aarch64_simd_valid_immediate ( const_vector , mode , false , & info ) ; gcc_assert ( is_valid ) ; element_char = sizetochar ( info . element_width ) ; lane_count = width / info . element_width ; mode = GET_MODE_INNER ( mode ) ; if ( mode == SFmode || mode == DFmode ) { gcc_assert ( info . shift == <NUM_LIT> && ! info . mvn ) ; if ( aarch64_float_const_zero_rtx_p ( info . value ) ) info . value = GEN_INT ( <NUM_LIT> ) ; else { REAL_VALUE_TYPE r ; REAL_VALUE_FROM_CONST_DOUBLE ( r , info . value ) ; char float_buf [ buf_size ] = { '\0' } ; real_to_decimal_for_mode ( float_buf , & r , buf_size , buf_size , <NUM_LIT> , mode ) ; if ( lane_count == <NUM_LIT> ) snprintf ( templ , sizeof ( templ )


<s> __builtin_ia32_storedqusi128_mask ( ( __v4si * ) __P , (


<s> if ( ForceExapnd ) return true ; MachineInstr * DefMI = getAccDefMI ( MI ) ; if ( TII -> isFpMLxInstruction ( DefMI -> getOpcode ( ) ) ) { IgnoreStall . insert ( DefMI ) ; return true ; } if ( IgnoreStall . count ( MI ) ) return false ; unsigned Limit1 = isA9 ? <NUM_LIT> : <NUM_LIT> ; unsigned Limit2 = isA9 ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) { int Idx = ( ( int ) MIIdx - i + <NUM_LIT> ) % <NUM_LIT> ; MachineInstr * NextMI = LastMIs [ Idx ] ; if ( ! NextMI ) continue ; if ( TII -> canCauseFpMLxStall ( NextMI -> getOpcode ( )


<s> if ( ! cum -> warn_empty ) return ; if ( ! TYPE_EMPTY_P ( type ) ) return ; const_tree ctx = get_ultimate_context ( cum -> decl ) ; if ( ctx != NULL_TREE && ! TRANSLATION_UNIT_WARN_EMPTY_P


<s> break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = ( Value & ~ <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> ,


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printOperand ( MI , OpNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNum ,


<s> return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG


<s> return ( int32x2x2_t ) { vtrn1_s32 ( a , b ) , vtrn2_s32


) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit ,


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize (

) ) && ! MFI -> hasVarSizedObjects ( ) ;


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : case CCValAssign :: ZExt : case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg


<s> rtx gen_df_reg ( rtx reg , int low ) { int regno = REGNO (


<s> bool UseSplitPush = STI . splitFramePushPop ( ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) .


<s> class LLVM_LIBRARY_VISIBILITY <ISA_LIT>MCInstLower { MCContext & Ctx ; AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym


<s> if ( aarch64_madd_needs_nop ( insn ) ) fprintf ( asm_out_file


<s> void sh_optimize_sett_clrt :: update_ccreg_mode ( machine_mode m ) { if ( GET_MODE ( m_ccreg ) == m ) return ; PUT_MODE ( m_ccreg , m ) ; log_msg ( <STR_LIT> ) ; log_rtx ( m_ccreg ) ; log_msg ( <STR_LIT>


<s> const <ISA_LIT>InstrInfo * getInstrInfo


<s> while ( ( q = strtok ( argstr , <STR_LIT> ) ) != NULL ) { while ( ISSPACE ( * q ) ) ++ q ; argstr = NULL ; if ( ! strncmp ( q , <STR_LIT> , <NUM_LIT> ) ) opts -> x_target_flags |= MASK_THUMB ; else if ( ! strncmp ( q , <STR_LIT> , <NUM_LIT> ) ) opts -> x_target_flags &= ~ MASK_THUMB ; else if ( ! strncmp ( q , <STR_LIT> , <NUM_LIT> ) ) { int fpu_index ; if ( ! opt_enum_arg_to_value ( OPT_mfpu_ , q + <NUM_LIT> , & fpu_index ,


<s> return __aarch64_vget_lane_any ( __a ,


<s> if ( isPopOpcode ( MI -> getOpcode ( ) ) ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true


<s> const char * asmname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P


<s> if ( num_suffix == <NUM_LIT> ) sprintf ( buffer , <STR_LIT> , funcname , modename ) ; else sprintf ( buffer , <STR_LIT> , funcname , modename


<s> if ( ! STI . isTargetMachO ( ) ) return false ; MachineFunction & MF = * I . getParent ( ) -> getParent ( ) ; MF . getFrameInfo ( ) . setAdjustsStack ( true ) ; const GlobalValue & GV = * I . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; MachineIRBuilder MIB ( I ) ; auto LoadGOT = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { } ) . addGlobalAddress ( & GV , <NUM_LIT> , <STR_LIT> ) ; auto Load = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { LoadGOT . getReg ( <NUM_LIT> ) } ) . addImm ( <NUM_LIT> ) ; MIB . buildCopy ( Register ( <STR_LIT> ) , LoadGOT . getReg ( <NUM_LIT> ) ) ; MIB . buildInstr ( getBLRCallOpcode ( MF ) , { } , { Load } ) . addUse ( <STR_LIT> , RegState :: Implicit ) . addDef ( <STR_LIT> , RegState :: Implicit ) . addRegMask ( TRI . getTLSCallPreservedMask ( ) ) ; MIB . buildCopy ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , Register ( <STR_LIT> ) ) ; RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> ,


<s> rtx loc , a0 ; rtx_insn * insn ; rtx tmp = gen_reg_rtx ( Pmode ) ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! loongarch_tls_symbol ) loongarch_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = loongarch_unspec_address ( sym , type ) ; start_sequence ( ) ; if ( TARGET_EXPLICIT_RELOCS ) { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( loc ) ) ; high = loongarch_force_temporary ( tmp , high ) ; if ( TARGET_CMODEL_EXTREME ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; rtx tmp1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_low ( Pmode , tmp1 , gen_rtx_REG ( Pmode , <NUM_LIT> ) , loc ) ) ; emit_insn ( gen_lui_h_lo20 ( tmp1 , tmp1 , loc ) ) ; emit_insn ( gen_lui_h_hi12 ( tmp1 , tmp1 , loc ) ) ; emit_move_insn ( a0 , gen_rtx_PLUS ( Pmode , high , tmp1 ) ) ; } else emit_insn ( gen_tls_low ( Pmode , a0 , high , loc ) ) ; } else { if ( type == SYMBOL_TLSLDM ) emit_insn ( loongarch_got_load_tls_ld ( a0 , loc ) ) ; else if ( type == SYMBOL_TLSGD ) emit_insn ( loongarch_got_load_tls_gd ( a0 , loc ) ) ; else gcc_unreachable ( ) ; } if ( flag_plt ) { switch ( la_opt_cmodel ) { case CMODEL_NORMAL : insn = emit_call_insn ( gen_call_value_internal ( v0 , loongarch_tls_symbol , const0_rtx ) ) ; break ; case CMODEL_MEDIUM : { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_EXPLICIT_RELOCS ) { emit_insn ( gen_pcalau12i ( Pmode , reg , loongarch_tls_symbol ) ) ; rtx call = gen_call_value_internal_1 ( Pmode , v0 , reg , loongarch_tls_symbol , const0_rtx ) ; insn = emit_call_insn ( call ) ; } else { emit_move_insn ( reg , loongarch_tls_symbol ) ; insn = emit_call_insn ( gen_call_value_internal ( v0 , reg , const0_rtx ) ) ; } break ; } case CMODEL_EXTREME : case CMODEL_LARGE : case CMODEL_TINY : case CMODEL_TINY_STATIC : default : gcc_unreachable ( ) ; } } else { rtx dest = gen_reg_rtx ( Pmode ) ; switch ( la_opt_cmodel ) { case CMODEL_NORMAL : case CMODEL_MEDIUM : { if ( TARGET_EXPLICIT_RELOCS ) { rtx high = gen_reg_rtx ( Pmode ) ; loongarch_emit_move ( high , gen_rtx_HIGH ( Pmode , loongarch_tls_symbol ) ) ; emit_insn ( gen_ld_from_got ( Pmode , dest , high , loongarch_tls_symbol ) ) ; } else loongarch_emit_move ( dest , loongarch_tls_symbol ) ; break ; } case CMODEL_EXTREME : { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; rtx tmp1 = gen_reg_rtx ( Pmode ) ; rtx high = gen_reg_rtx ( Pmode ) ; loongarch_emit_move ( high , gen_rtx_HIGH ( Pmode , loongarch_tls_symbol ) ) ; loongarch_emit_move ( tmp1 , gen_rtx_LO_SUM ( Pmode , gen_rtx_REG

( Pmode , <NUM_LIT> ) , loongarch_tls_symbol ) ) ;


<s> static void mergeSPUpdatesDown ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , uint64_t * NumBytes = NULL ) { return ; if ( MBBI == MBB . end ( ) ) return ; MachineBasicBlock :: iterator NI = llvm :: next ( MBBI ) ; if ( NI == MBB . end ( ) ) return ; unsigned Opc = NI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes -= NI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( NI ) ; MBBI =


<s> SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues (


<s> bool targetHandlesStackFrameRounding ( ) const


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp , ArrayRef < Value * > Args ) { InstructionCost CostFactor = vectorCostAdjustmentFactor ( Instruction ::


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasShiftedReg ( * FirstMI ) ) ; } } return false


<s> bool isThumbFunction ( ) const { return isThumb


<s> if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) ,


<s> bool isVK1Pair ( ) const { return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> if ( <STR_LIT> . hasSubClassEq ( RC )


<s> return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ; case <STR_LIT> :: <ISA_LIT>V4T : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ; case <STR_LIT> :: <ISA_LIT>V5T : case <STR_LIT> :: <ISA_LIT>V5TE : case <STR_LIT> :: <ISA_LIT>V5TEJ : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V5 ; case <STR_LIT> :: <ISA_LIT>V6 : case <STR_LIT> :: <ISA_LIT>V6K : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ; case <STR_LIT> :: <ISA_LIT>V7A : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ; case <STR_LIT> :: <ISA_LIT>V7S : return MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ; case <STR_LIT> ::


<s> static SDValue getPXOnesVector ( EVT VT , SDNodeTreeBuilder b ) { SDValue Vec ; if ( VT . isSimple ( ) && VT . getSimpleVT ( ) . is32BitVector ( ) ) { Vec = b . Constant ( - <NUM_LIT> , <STR_LIT> ) ; } else if ( VT . isSimple ( ) && VT . getSimpleVT ( ) . is64BitVector ( ) ) { Vec = b . Constant ( - <NUM_LIT> , <STR_LIT> ) ; } else if ( VT . isSimple ( ) && VT . getSimpleVT ( ) . is128BitVector ( ) ) { Vec = b . ConstantVector ( <STR_LIT> ,


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinus1 , CTLZ ) ; } SDValue Bits ; if ( ElemTy == <STR_LIT> ) { SDValue FF = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , FF ) ; } else { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB


<s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal ==


<s> if ( MO . isReg ( ) && ( ( MO . getReg ( ) == <STR_LIT> )


<s> SDValue getAddrGlobal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const MachinePointerInfo & PtrInfo , bool IsForTls ) const { assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty .


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : ( void ) RetFastCC_<ISA_LIT>_APCS ; ( void ) FastCC_<ISA_LIT>_APCS ; case CallingConv :: C : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS


<s> void addMRSSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> rtx src = operands [ <NUM_LIT> ] ; unsigned int size = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned int pos = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( GET_CODE ( dst ) == SUBREG ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; switch ( GET_MODE ( dst ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx


<s> if ( Offset % Size != <NUM_LIT> ) return None ; auto GV = Adrp . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) return None ; auto & MF = * RootDef . getParent ( ) -> getParent ( ) ; if ( GV -> getPointerAlignment ( MF . getDataLayout ( ) ) < Size ) return None ; unsigned OpFlags = STI . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) ; MachineIRBuilder MIRBuilder ( RootDef ) ; Register AdrpReg = Adrp . getOperand ( <NUM_LIT> ) . getReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( AdrpReg )

; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> if ( CI -> isTailCall ( ) ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CC = CS . getCallingConv ( ) ; FunctionType * FTy = CS . getFunctionType ( ) ; bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CS . arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: SwiftSelf ) || CS . paramHasAttr ( AttrInd , Attribute :: SwiftError ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i )


<s> } if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) { report_fatal_error ( <STR_LIT> ) ; } X -> InitMCCodeGenInfo ( RM


<s> return false ; case SIGN_EXTEND : case ZERO_EXTEND : * total = COSTS_N_INSNS ( CSKY_NUM_REGS ( mode ) ) ; return false ; case SIGN_EXTRACT : case ZERO_EXTRACT : if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) % <NUM_LIT> == <NUM_LIT> ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } * total = COSTS_N_INSNS ( CSKY_NUM_REGS ( mode ) ) ; return false ; case CONST_INT : { unsigned HOST_WIDE_INT t = ( unsigned HOST_WIDE_INT ) ( INTVAL ( x ) ) ; if ( outer_code == COMPARE ) { if ( t < <NUM_LIT> ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == AND || outer_code == IOR || outer_code == XOR ) { if ( t < <NUM_LIT> ) { if ( outer_code == AND && ( t == <NUM_LIT> || t == <NUM_LIT> ) ) { * total = <NUM_LIT> ; return true ; } * total = <NUM_LIT> ; } else if ( t < <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( t < <NUM_LIT> ) * total = <NUM_LIT> ; else if ( t < <NUM_LIT> ) * total = <NUM_LIT> ; else if ( t < <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == ROTATE || outer_code == ROTATERT || outer_code == LSHIFTRT || outer_code == ASHIFTRT || outer_code == ASHIFT ) { if ( t < <NUM_LIT> ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else { if ( t < <NUM_LIT> ) if ( outer_code == SET && t < <NUM_LIT> ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } } return true ; case CONST


<s> insertTrackingCode ( * SplitEdgeTBB , CondCode , DL ) ; insertTrackingCode ( * SplitEdgeFBB , InvCondCode , DL ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplitEdgeTBB << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplitEdgeFBB << <STR_LIT> ) ; Modified = true ; } SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > ReturnInstructions ; SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > CallInstructions ; bool TmpRegisterNotAvailableEverywhere = false ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; I ++ ) { MachineInstr & MI = * I ; if ( ! MI . isReturn ( ) && ! MI . isCall ( ) ) continue ; if ( I != MBB . begin ( ) ) RS . forward ( std :: prev ( I ) ) ; unsigned TmpReg = RS . FindUnusedReg ( & <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ( TmpReg == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( TmpReg != <NUM_LIT> ) dbgs ( ) << printReg ( TmpReg , TRI ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MI ) ; if ( TmpReg == <NUM_LIT> ) TmpRegisterNotAvailableEverywhere = true ; if ( MI . isReturn ( ) ) ReturnInstructions . push_back ( { & MI , TmpReg } ) ; else if ( MI . isCall ( ) ) CallInstructions . push_back ( { & MI , TmpReg } ) ; } if ( TmpRegisterNotAvailableEverywhere ) { insertFullSpeculationBarrier ( MBB , MBB . begin ( ) , ( MBB . begin ( ) ) -> getDebugLoc ( ) ) ; UsesFullSpeculationBarrier = true ; Modified = true ; } else { for ( auto MI_Reg :


<s> void expand_sf_binop ( rtx ( * fun ) ( rtx , rtx , rtx , rtx ) , rtx * operands ) { emit_sf_insn ( ( * fun ) ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , get_fpscr_rtx (


<s> unsigned CC = StringSwitch < unsigned > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex (


<s> int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ; } return Offset


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT> ) ; return Tok


<s> case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP


<s> break ; } case G_FCONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_FCMP : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , FPRValueMapping , FPRValueMapping } ) ; break ; } case G_FPEXT : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_FPTRUNC : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT>


<s> static bool isSVEVectorOrPredicateRegister ( std :: string Name


<s> if ( MRI . hasOneNonDBGUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasOptSize ( ) ) return true ; if ( ! STI . hasLSLFast ( ) ) return


<s> CurrGroupSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++

i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ;


<s> if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false


<s> bool UseFastISel = false ; UseFastISel |= STI . isTargetMachO ( ) && ! STI . isThumb1Only ( ) ; UseFastISel |= STI . isTargetLinux ( ) && ! STI . isThumb ( ) ; UseFastISel |= STI . isTargetNaCl ( ) && ! STI . isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new <ISA_LIT>FastISel ( funcInfo , libInfo ) ; } return nullptr


<s> return ( __m256i ) __builtin_ia32_pternlogd256_mask ( ( __v8si ) __A , ( __v8si ) __B , ( __v8si ) __C , ( unsigned


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N0 = DAG . getNode ( <STR_LIT> ,


<s> if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> ; if ( UseCycle < <NUM_LIT> ) UseCycle = <NUM_LIT> ; UseCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { UseCycle = ( RegNo / <NUM_LIT>


<s> for ( i = <NUM_LIT> ; i < len ; i ++ ) { int c = p [ i ] ; if ( len_so_far >= MAX_ASCII_LEN ) { fputs ( <STR_LIT> , stream ) ; len_so_far = <NUM_LIT> ; } if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; len_so_far ++ ; } putc ( c , stream


<s> void addImm1_32Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr >


<s> unsigned ScalarBits = ValTy -> getScalarSizeInBits ( ) ; if ( I != nullptr && ScalarBits >= <NUM_LIT> ) if ( LoadInst * Ld = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( const ConstantInt * C = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( ! Ld -> hasOneUse ( ) && Ld -> getParent ( ) == I -> getParent ( ) && C -> getZExtValue ( ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += ( I != nullptr ? getOperandsExtensionCost ( I ) : <NUM_LIT> ) ; return Cost ; } case Instruction :: Select : if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return


<s> static SDValue getUnpackl ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements (


<s> EVT FPTy = EVT :: getFloatingPointVT ( Op . getValueSizeInBits ( ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , FPTy , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( )


<s> auto MMO = * MI -> memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI -> getMF ( ) -> getSubtarget ( ) ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( ) && MMO ->

getSize ( ) > MMO -> getAlignment ( ) ) ) return true ;


<s> df_note_add_problem ( ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; regrename_init ( true ) ; regrename_analyze ( NULL ) ; auto_vec < du_head_p > cands ; for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) continue ; extract_insn ( insn ) ; int opno0 , opno1 ; int modrm = ix86_get_modrm_for_rop ( insn , recog_data . operand , recog_data . n_operands , & opno0 , & opno1 ) ; if ( ! ix86_rop_should_change_byte_p ( modrm ) ) continue ; insn_rr_info * info = & insn_rr [ INSN_UID ( insn ) ] ; if ( ! info -> op_info ) continue ; if ( info -> op_info [ opno0 ] . n_chains != <NUM_LIT> ) { gcc_assert ( info -> op_info [ opno0 ] . n_chains == <NUM_LIT> ) ; du_head_p op0c ; op0c = regrename_chain_from_id ( info -> op_info [ opno0 ] . heads [ <NUM_LIT> ] -> id ) ; if ( op0c -> target_data_1 + op0c -> target_data_2 == <NUM_LIT> && ! op0c -> cannot_rename ) cands . safe_push ( op0c ) ; op0c -> target_data_1 ++ ; } if ( info -> op_info [ opno1 ] . n_chains != <NUM_LIT> ) { gcc_assert ( info -> op_info [ opno1 ] . n_chains == <NUM_LIT> ) ; du_head_p op1c ; op1c = regrename_chain_from_id ( info -> op_info [ opno1 ] . heads [ <NUM_LIT> ] -> id ) ; if ( op1c -> target_data_1 + op1c -> target_data_2 == <NUM_LIT> && ! op1c -> cannot_rename ) cands . safe_push ( op1c ) ; op1c -> target_data_2 ++ ; } } int i ; du_head_p head ; FOR_EACH_VEC_ELT ( cands , i , head ) { int old_reg , best_reg ; HARD_REG_SET unavailable ; CLEAR_HARD_REG_SET ( unavailable ) ; if ( head -> target_data_1 ) IOR_HARD_REG_SET ( unavailable , output_risky ) ; if ( head -> target_data_2 ) IOR_HARD_REG_SET ( unavailable , input_risky ) ; int n_uses ; reg_class superclass = regrename_find_superclass ( head , & n_uses , & unavailable ) ; old_reg = head -> regno ; best_reg = find_rename_reg ( head , superclass , & unavailable , old_reg , false ) ; bool ok = regrename_do_replace ( head , best_reg ) ; gcc_assert ( ok ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , head -> id , reg_names [ best_reg ] , reg_class_names [ superclass ] ) ; } regrename_finish ( ) ; df_analyze ( ) ; basic_block bb ; regset_head live ; INIT_REG_SET ( & live ) ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; COPY_REG_SET ( & live , DF_LR_OUT ( bb ) ) ; df_simulate_initialize_backwards ( bb , & live ) ; FOR_BB_INSNS_REVERSE ( bb ,


<s> return __builtin_aarch64_reduc_smin_scal_v4sf (


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( ShAmtOp ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; SDValue ValOp = N -> getOperand ( <NUM_LIT> ) ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; break ; case <STR_LIT> : if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; break ; case <STR_LIT> : if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT>


<s> bool Swap = false ; unsigned LittleEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned BigEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = N -> getMask ( ) ; int OriginalOrder [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; bool FoundCandidate = false ; unsigned VINSERTBSrcElem = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <


<s> return ( uint32x2_t ) __builtin_neon_vsubhnv2di ( ( int64x2_t )


<s> dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return <NUM_LIT> ; return dest_uid


<s> if ( MBBI == B || Offset != <NUM_LIT> ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , Offset ) ) return MBBI ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits


<s> bool doInitialization ( Module & M ) override { SMShadowTracker . reset ( <NUM_LIT>


<s> } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; return ; } if ( TT . isOSBinFormatCOFF ( ) ) { emitStackMaps ( SM ) ; return ; } if ( TT . isOSBinFormatELF (


<s> if ( getLexer ( ) . getKind ( ) != AsmToken :: LBrac ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; if ( getLexer ( ) . getKind ( ) != AsmToken :: RBrac ) return MatchOperand_NoMatch ; getLexer ( ) . Lex (


<s> static bool pru_nongeneric_pointer_addrspace ( tree typ ) { while ( ARRAY_TYPE == TREE_CODE ( typ ) ) typ = TREE_TYPE ( typ ) ; if ( POINTER_TYPE_P ( typ )


<s> if ( process_root ) process_root ( * forest_iter , * root_iter ) ; to_process . safe_push ( * root_iter ) ; } while ( ! to_process . is_empty ( ) ) { fma_node * node ; std :: list < fma_node * > :: iterator child_iter ; node = to_process . pop ( ) ; if ( process_node ) process_node ( * forest_iter , node ) ; if ( node -> get_children ( ) -> empty ( ) ) continue ; for ( child_iter = node -> get_children ( ) -> begin ( ) ; child_iter != node -> get_children ( ) -> end ( ) ; child_iter ++ ) to_process . safe_push


<s> static MachineBasicBlock :: iterator skipAlignedDPRCS2Spills ( MachineBasicBlock :: iterator MI , unsigned NumAlignedDPRCS2Regs ) { ++ MI ; ++ MI ; ++ MI ; assert ( MI -> mayStore ( ) && <STR_LIT> ) ; switch ( NumAlignedDPRCS2Regs ) { case <NUM_LIT> : ++ MI ; assert ( MI -> mayStore ( ) && <STR_LIT> ) ; default : ++


<s> MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL = Cmp . getDebugLoc ( ) ; MachineInstr * Loop = findLoopInstr ( PreHeader ) ; if ( ! Loop ) return <NUM_LIT> ; Register LoopCountReg = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; if ( ! LoopCount ) return <NUM_LIT> ; if ( LoopCount -> getOpcode ( ) == <STR_LIT> || LoopCount -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = LoopCount -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) { LoopCount -> eraseFromParent ( ) ; Loop -> eraseFromParent ( ) ; return


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != <NUM_LIT> || Align <= <NUM_LIT> ||

Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ;


<s> static bool isValidNEONi32vmovImm ( int64_t Value ) { return ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( ( Value & <NUM_LIT> ) == <NUM_LIT> )

|| ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( <NUM_LIT> ) ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , Align ( <NUM_LIT> ) ) ; const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; Function :: const_arg_iterator FuncArg = Func . arg_begin ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) && ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_FixedArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , CCInfo . getInRegsParamsCount ( ) > <NUM_LIT> ) ; unsigned CurArgIdx = <NUM_LIT> ; CCInfo . rewindByValRegsInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . isOrigArg ( ) ) { std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ i ] . getOrigArgIndex ( ) ; } EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Ins [ i ] . isOrigArg ( ) && <STR_LIT> ) ; unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , FirstByValReg , LastByValReg , VA , CCInfo ) ; CCInfo . nextInRegsParam ( ) ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; Register ArgReg = VA . getLocReg (


<s> <STR_LIT> CC = getITInstrPredicate ( * MI , PredReg ) ; if ( CC == <STR_LIT> ) { ++ MBBI ; continue ; } Defs . clear ( ) ; Uses . clear ( ) ; TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugInstr ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; Register NPredReg ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( ( NCC ^ CC ) & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; MIB . addImm ( Mask )


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return <NUM_LIT> ; if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( ST -> hasNEON ( ) && Src -> isVectorTy ( ) && ( Alignment && * Alignment != Align ( <NUM_LIT> ) ) && cast < VectorType > ( Src ) -> getElementType ( ) -> isDoubleTy ( ) ) { return LT . first * <NUM_LIT> ; } int BaseCost = ST -> hasMVEIntegerOps ( ) && Src -> isVectorTy

( ) ? ST -> getMVEVectorCostFactor ( ) : <NUM_LIT> ;


<s> tree arg0 = TREE_VALUE ( arglist ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate )

( target , tmode ) ) target = gen_reg_rtx ( tmode ) ;


<s> case VK_<ISA_LIT>_M44 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_L44 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_HH : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_HM : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_PC22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_PC10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT13 : return false ; case VK_<ISA_LIT>_13 : return false ; case VK_Sparc_WDI<ISA_LIT>30 : return false ; case VK_<ISA_LIT>_WPLT30 : return false ; case VK_Sparc_R_DI<ISA_LIT>32 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_ADD : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_CALL : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_ADD : OS << <STR_LIT> ; return


<s> if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C

) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , IsVarArg , MF , TM , RetLocs , * DAG . getContext ( ) ) ; RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA ,


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCTargetStreamer * TargetStreamer , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TargetStreamer , TAB

, OS , Emitter ) , IsThumb ( IsThumb ) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) {


<s> insn = emit_insn ( ( * move_fn ) ( mem , reg , GEN_INT ( cfa_off ) ) ) ; spill_fill_data . prev_insn [ iter ] = insn ; if ( frame_reg ) { rtx base ; HOST_WIDE_INT off ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( frame_pointer_needed ) { base = hard_frame_pointer_rtx ; off = - cfa_off ; } else { base = stack_pointer_rtx ; off = current_frame_info . total_size - cfa_off ; } add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( gen_rtx_MEM ( GET_MODE ( reg ) , plus_constant ( Pmode ,


<s> <STR_LIT> llvm :: getITInstrPredicate ( const MachineInstr & MI , Register & PredReg ) { unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT>


<s> return ( __m64 ) __builtin_ia32_pavgusb ( ( __v8qi ) __A , (


<s> return ( unsigned long long ) __builtin_sh_media_MEXTR6 ( ( v8qi ) mm , (


<s> } else { s_level = nds32_isr_secure_level ; } if ( intr != NULL_TREE && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( intr ) ) ) == STRING_CST ) { tree string_arg = TREE_VALUE ( TREE_VALUE ( intr ) ) ; nds32_interrupt_attribute_parse_string ( TREE_STRING_POINTER ( string_arg ) , func_name , s_level ) ; return ; } if ( excp != NULL_TREE && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( excp ) ) ) == STRING_CST ) { tree string_arg = TREE_VALUE ( TREE_VALUE ( excp ) ) ; nds32_exception_attribute_parse_string ( TREE_STRING_POINTER ( string_arg ) , func_name , s_level ) ; return ; } if ( reset != NULL_TREE && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( reset ) ) ) == STRING_CST ) { tree string_arg = TREE_VALUE ( TREE_VALUE ( reset ) ) ; nds32_reset_attribute_parse_string ( TREE_STRING_POINTER ( string_arg ) , func_name ) ; return ; } if ( intr || excp ) { tree id_list ; id_list = ( intr ) ? ( TREE_VALUE ( intr ) ) : ( TREE_VALUE ( excp ) ) ; while ( id_list ) { tree id ; int vector_id ; unsigned int vector_number_offset ; vector_number_offset = ( intr ) ? ( <NUM_LIT> ) : ( <NUM_LIT> ) ; id = TREE_VALUE ( id_list ) ; vector_id = TREE_INT_CST_LOW ( id ) + vector_number_offset ; nds32_isr_vectors [ vector_id ] . security_level = s_level ; nds32_isr_vectors [ vector_id ] . category = ( intr ) ? ( NDS32_ISR_INTERRUPT ) : ( NDS32_ISR_EXCEPTION ) ; strcpy ( nds32_isr_vectors [ vector_id ] . func_name , func_name ) ; if ( save_all ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_SAVE_ALL ; else if ( partial_save ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_PARTIAL_SAVE ; if ( nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED ; else if ( not_nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NOT_NESTED ; else if ( nested_ready ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED_READY ; else if ( critical ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_CRITICAL ; id_list = TREE_CHAIN ( id_list ) ; } } else { tree id_list ; tree id ; tree nmi , warm ; nds32_isr_vectors [ <NUM_LIT> ] . category = NDS32_ISR_RESET ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors = TREE_INT_CST_LOW ( id


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , LoSmallShift , LoBigShift , <ISA_LIT>cc , CCR , CmpLo ) ; SDValue HiSmallShift = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue HiBigShift = Opc == <STR_LIT> ? DAG . getNode ( Opc , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , dl , VT ) ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue CmpHi = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , HiSmallShift , HiBigShift , <ISA_LIT>cc , CCR , CmpHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues (


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; OpLHS = DAG . getNode ( <STR_LIT> , DL , VT , OpLHS ) ; unsigned ExtractNum = ( VT == <STR_LIT> ) ? <NUM_LIT> :


<s> case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ; case <STR_LIT> : return Imm >= <NUM_LIT> && Imm < ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) ; case <STR_LIT> : return Imm < <NUM_LIT> && - Imm < ( ( <NUM_LIT> << <NUM_LIT> )


<s> const MCExpr * Value = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; if ( Size == <NUM_LIT> ) { if ( MF -> getFunction ( ) . isPagerando ( ) ) report_fatal_error ( <STR_LIT> ) ; const TargetLowering * TLI = MF -> getSubtarget


<s> void <ISA_LIT>IntelInstPrinter :: printAVXCC ( const MCInst * MI , unsigned Op ,


<s> assert ( ! Is64Bit ) ; MCInst ADDInst ; unsigned ADDReg = <STR_LIT> ; ADDInst . setOpcode ( <STR_LIT> ) ; ADDInst . addOperand ( MCOperand :: CreateReg ( ADDReg ) ) ; ADDInst . addOperand ( MCOperand :: CreateReg ( ADDReg ) ) ; ADDInst . addOperand ( * AmtOp ) ; Out . EmitInstruction ( ADDInst , STI ) ; } EmitIndirectBranch ( STI , MCOperand :: CreateReg ( RegTarget ) , Is64Bit


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame . laid_out ) ; if ( crtl -> calls_eh_return )


<s> if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return <NUM_LIT> ; if ( TARGET_P8_VECTOR && ( mode == SImode ) ) return <NUM_LIT> ; if ( TARGET_P9_VECTOR && ( mode == QImode || mode == HImode ) ) return <NUM_LIT> ; } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode


<s> static DecodeStatus DecodeDSPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPR32RegisterClass ( Inst , RegNo , Address , Decoder


<s> computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> return ( uint32x2_t ) __builtin_neon_vpminuv2si ( ( int32x2_t ) __a ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> SDValue Op0 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , Op0 , Op1 , CC , dl , Op0 , Op1 , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! Op1 . getNode ( ) ) { assert ( Op0 . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; if ( IsStrict ) return DAG . getMergeValues ( { Op0 , Chain } , dl ) ; return Op0 ; } } if ( Op0 . getSimpleValueType ( ) . isInteger ( ) ) { SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT>CC , EFLAGS ) ; return IsStrict ? DAG . getMergeValues ( { Res , Chain } , dl ) : Res ; } <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , true , Op0 , Op1 , DAG ) ; if ( CondCode == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS ; if ( IsStrict )


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT>


<s> int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = <NUM_LIT> ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case


<s> bool <ISA_LIT>MCTargetExpr :: EvaluateAsRelocatableImpl ( MCValue & Res ) const { if ( Sym -> isVariable ( ) ) return Sym -> getValue ( ) -> EvaluateAsRelocatable ( Res ) ; Res = MCValue :: get ( Sym , <NUM_LIT> , <NUM_LIT> ) ; return true


<s> void <ISA_LIT>AsmPrinter :: emitInlineAsmStart ( const MCSubtargetInfo & StartInfo ) const { <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush (


<s> if ( ! FuncInfo . CanLowerReturn ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } unsigned RetOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( RetOpc ) ) ; AddOptionalDefs ( MIB ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs


) ) , preferred_alignment ) ) return false ;


<s> void emitARM64WinCFISaveNext ( ) override { OS <<


<s> switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>MCAsmInfoDarwin ( ) ; default : return new <ISA_LIT>ELFMCAsmInfo (


<s> if ( reg && ix86_check_avx_upper_register ( reg ) ) return AVX_U128_DIRTY ; return ix86_avx_u128_mode_entry (


<s> return ( __m256d ) __builtin_ia32_haddpd256 ( ( __v4df


<s> getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return


<s> for ( MachineInstr * Op : llvm :: reverse ( Ops ) ) { unsigned LSMOpcode = getLoadStoreMultipleOpcode ( Op -> getOpcode ( ) , <STR_LIT> ) ; if ( LastOpcode && LSMOpcode != LastOpcode ) break ; int Offset = getMemoryOpOffset ( * Op ) ; unsigned Bytes = getLSMultipleTransferSize ( Op ) ; if ( LastBytes ) { if ( Bytes != LastBytes || Offset != ( LastOffset + ( int ) Bytes ) ) break ; } if ( NumMove == InstReorderLimit ) break ; ++ NumMove ; LastOffset = Offset ; LastBytes = Bytes ; LastOpcode = LSMOpcode ; unsigned Loc = MI2LocMap [ Op ] ; if ( Loc <= FirstLoc ) { FirstLoc = Loc ; FirstOp = Op ; } if ( Loc >= LastLoc ) { LastLoc = Loc ; LastOp = Op ; } } if ( NumMove <= <NUM_LIT> ) Ops . pop_back ( ) ; else { SmallPtrSet < MachineInstr * , <NUM_LIT> > MemOps ; SmallSet < unsigned , <NUM_LIT> > MemRegs ; for ( size_t i = Ops . size ( ) - NumMove , e = Ops . size ( ) ; i != e ; ++ i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI , AA ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( & * InsertPos ) || InsertPos -> isDebugInstr ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; Register FirstReg , SecondReg ; Register BaseReg , PredReg ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , FirstReg , SecondReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( FirstReg , TRC ) ; MRI -> constrainRegClass ( SecondReg , TRC ) ; if ( isLd


<s> void mep_reinit_regs ( void ) { reinit_regs ( )


<s> context -> bsp = context -> regstk_top = ( unsigned long ) bsp ; context -> psp = ( unsigned long ) psp ; context -> rp = ( unsigned long ) rp ; asm ( <STR_LIT> : <STR_LIT> ( context -> sp ) ) ; asm ( <STR_LIT> : <STR_LIT> ( context -> pr ) ) ; context -> pri_unat_loc = & context -> initial_unat ; if ( uw_frame_state_for ( context , & fs ) !=


<s> if ( Narrow ) transform ( Regs , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( St ) , { MemOp } ) ; ReplaceNode ( N , St


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , TM . getPointerSizeInBits ( <NUM_LIT> ) ) ; const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; LegacyInfo . setAction ( { G_IMPLICIT_DEF , s64 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_IMPLICIT_DEF , s128 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_PHI , s64 } , LegacyLegalizeActions :: Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) LegacyInfo . setAction ( { BinOp , s64 } , LegacyLegalizeActions :: Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) LegacyInfo . setAction ( { MemOp , s64 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_PTR_ADD , <NUM_LIT> , s64 } , LegacyLegalizeActions :: Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; LegacyInfo . setAction ( { TargetOpcode :: G_CONSTANT , s64 } , LegacyLegalizeActions :: Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { LegacyInfo . setAction ( { extOp , s64 } , LegacyLegalizeActions :: Legal ) ; } getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) .


<s> static int ia64_function_arg_offset ( const CUMULATIVE_ARGS * cum , const_tree type , int words ) { if ( TARGET_ABI_OPEN_VMS || ( cum -> words & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; if ( type && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return TYPE_ALIGN


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> x . v = ( vec_uchar16 ) ( count ) ; x . i [ <NUM_LIT> ] = cnt = <NUM_LIT> - ( x . i [ <NUM_LIT> ] & ~ <NUM_LIT> ) ; x . v = vec_splat ( x . v , <NUM_LIT> ) ; mask = ( cnt & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ; return ( ( qword ) ( vec_and ( vec_sro ( ( vec_uchar16 ) ( a


<s> return :: isUNPCKHMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT>


<s> else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Scatters . push_back ( II ) ; } } bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; if ( isa < GetElementPtrInst > ( I -> getArgOperand ( <NUM_LIT> ) ) ) optimiseOffsets ( cast < Instruction > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) , I -> getParent ( ) , & LI ) ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = <NUM_LIT> ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; if ( isa < GetElementPtrInst > ( I -> getArgOperand ( <NUM_LIT> ) ) ) optimiseOffsets ( cast < Instruction > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) , I -> getParent ( ) , & LI ) ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed =


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( TRI -> hasBasePointer ( MF ) ) FrameReg = TRI -> getBaseRegister ( ) ; else if ( TRI -> needsStackRealignment ( MF ) ) FrameReg = TRI -> getStackRegister ( ) ; else FrameReg = TRI -> getFrameRegister ( MF ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; bool HasFP = hasFP ( MF ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int64_t FPDelta = <NUM_LIT> ; if ( IsWin64Prologue ) { assert ( ! MFI -> hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI -> hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! HasFP ) return Offset


<s> if ( FP_REGNUM_P ( regno ) && abi_id != ARM_PCS_SVE ) { poly_int64 per_register_size = GET_MODE_SIZE ( mode ) ; unsigned int nregs = hard_regno_nregs ( regno , mode ) ; if ( nregs > <NUM_LIT> ) per_register_size = exact_div ( per_register_size , nregs ) ; if ( abi_id == ARM_PCS_SIMD || abi_id == ARM_PCS_TLSDESC ) return maybe_gt ( per_register_size


<s> if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; if ( Offset != <NUM_LIT> || ! tryOptimizeLEAtoMOV ( II ) ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else


<s> if ( ( Form == <STR_LIT> || Form == <STR_LIT> ) && MI . isBranch ( ) ) return <STR_LIT> ; if ( Form == <STR_LIT> && MI . getOpcode (


<s> Parser . Lex ( ) ; if ( invertCondCode ) CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; const MCExpr * CCExpr = MCConstantExpr :: Create ( CC , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( CCExpr , S , getLoc


<s> EhDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC


<s> unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegD ) ; RegD = II -> getRegisterInfo ( ) . getEncodingValue ( RegD ) ; if ( ! isSPVFP ) { Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegD & <NUM_LIT>


<s> assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = IsN64 ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( RA


<s> return __builtin_mve_vldrbq_sv4si ( ( __builtin_neon_qi * ) __base


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) )


<s> return gen_rtx_REG ( mode , BASE_RETURN_VALUE_REG (