<s> assert ( N . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( N ) ; SmallVector < SDValue , <NUM_LIT> > Chain ; SDValue V = N . getOperand ( <NUM_LIT> ) ; for ( ; V . hasOneUse ( ) ; V = V . getOperand ( <NUM_LIT> ) ) { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : continue ; case <STR_LIT> : break ; case <STR_LIT> : if ( Mask [ <NUM_LIT> ] != <NUM_LIT> || Mask [ <NUM_LIT> ] != <NUM_LIT> || ! ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return SDValue ( ) ; Chain . push_back ( V ) ; continue ; case <STR_LIT> : if ( Mask [ <NUM_LIT> ] != <NUM_LIT> || Mask [ <NUM_LIT> ] != <NUM_LIT> || ! ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return SDValue ( ) ; Chain . push_back ( V ) ; continue ; case <STR_LIT> : case <STR_LIT> : if ( V . getSimpleValueType ( ) . getScalarType ( ) != <STR_LIT> && V . getSimpleValueType ( ) . getScalarType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned CombineOp = V . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( V . getOperand ( <NUM_LIT> ) != V . getOperand ( <NUM_LIT> ) || ! V -> isOnlyUserOf ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; Chain . push_back ( V ) ; V = V . getOperand ( <NUM_LIT> ) ; do { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( )


<s> std :: string CPUName = select<ISA_LIT>CPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName


<s> FrameReg = TRI -> getStackRegister ( ) ; return StackOffset :: getFixed ( MFI . getObjectOffset ( FI )

- getOffsetOfLocalArea ( ) + Adjustment ) ;


<s> return __builtin_mve_vaddq_m_n_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a


<s> Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( ! FloatDomain ) return false ; if ( SrcVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) ) { if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( SrcVT . is256BitVector ( ) ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( SrcVT . is512BitVector ( ) ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return


<s> rtx newv = gen_reg_rtx ( SImode ) ; rtx oldvalue = gen_reg_rtx ( SImode ) ; rtx newvalue = gen_reg_rtx ( SImode ) ; rtx res = gen_reg_rtx ( SImode ) ; rtx resv = gen_reg_rtx ( SImode ) ; rtx memsi , val , mask , cc ; emit_insn ( gen_rtx_SET ( VOIDmode , addr , gen_rtx_AND ( Pmode , addr1 , GEN_INT ( - <NUM_LIT> ) ) ) ) ; if ( Pmode != SImode ) addr1 = gen_lowpart ( SImode , addr1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , off , gen_rtx_AND ( SImode , addr1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; memsi = gen_rtx_MEM ( SImode , addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; val = copy_to_reg ( memsi ) ; emit_insn ( gen_rtx_SET ( VOIDmode , off , gen_rtx_XOR ( SImode , off , GEN_INT ( GET_MODE ( mem ) == QImode ? <NUM_LIT> : <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , off , gen_rtx_ASHIFT ( SImode , off , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( GET_MODE ( mem ) == QImode ) mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; else mask = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_ASHIFT ( SImode , mask , off ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , val , gen_rtx_AND ( SImode ,

gen_rtx_NOT ( SImode , mask ) , val ) ) ) ;


<s> bool allowMixed16_32 ( ) const { return in<ISA_LIT>16ModeDefault ( ) | AllowMixed16_32


<s> const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget >


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OS << '+' << MI -> getOperand ( <NUM_LIT> ) . getImm


<s> Reserved . set ( getBaseRegister ( ) ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { static const uint16_t GPR64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( MCRegAliasIterator AI ( GPR64 [ n ] , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved


<s> MachineInstr & MI = * I ; unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ; bool KillsSrc = MI . killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) { moveToTop ( Reg , I ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; -- StackTop ; pushReg ( getFPReg ( MI .


<s> static void arm_pre_atomic_barrier ( enum


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; int Size = <NUM_LIT> ; EmitInstruction ( Binary ,


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , { O0 , O1 } ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes || TrueRes . isUndef ( ) ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes || FalseRes . isUndef ( ) ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType ( <NUM_LIT> ) , Cond , TrueRes , FalseRes ) ; N = User ; ConstTrue = TrueRes


<s> OutStreamer -> emitDataRegion ( OffsetWidth == <NUM_LIT> ? MCDR_DataRegionJT8 : MCDR_DataRegionJT16 ) ; for ( auto MBB : JTBBs ) { const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; MCSymbol * TBInstPC = GetCPISymbol ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; const MCExpr * Expr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( TBInstPC , OutContext ) , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; Expr = MCBinaryExpr :: createSub ( MBBSymbolExpr , Expr , OutContext ) ; Expr = MCBinaryExpr :: createDiv ( Expr , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( Expr , OffsetWidth ) ; } OutStreamer -> emitDataRegion ( MCDR_DataRegionEnd


<s> return new <ISA_LIT>64Disassembler ( STI , Ctx


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false , <NUM_LIT> ) ; nextOffset += FrameOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr


<s> assert ( VA . getValVT ( ) . isVector ( ) ) ; Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value ) ; return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; case CCValAssign


<s> if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) thiz = <STR_LIT> ; if ( delta != <NUM_LIT> ) { if ( delta > maxoff || delta < - maxoff ) { fprintf ( file , <STR_LIT> , reg0 , ( long ) delta ) ; fprintf ( file , <STR_LIT> , thiz , thiz , reg0 ) ; } else fprintf ( file , <STR_LIT> , ( delta > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , thiz , thiz , ( long ) ( delta > <NUM_LIT> ? delta : - delta ) ) ; } if ( vcall_offset != <NUM_LIT> ) { fprintf ( file , <STR_LIT> , reg0 , thiz ) ; if ( vcall_offset > maxoff || vcall_offset < - maxoff ) { fprintf ( file , <STR_LIT> , reg1 , ( long ) vcall_offset ) ; fprintf ( file , <STR_LIT> , reg0 , reg0 , reg1 ) ; } else fprintf ( file , <STR_LIT> , ( vcall_offset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , reg0 , reg0 , ( long ) ( vcall_offset > <NUM_LIT> ? vcall_offset : - vcall_offset ) ) ; fprintf ( file , <STR_LIT> , reg0 , reg0 ) ; fprintf ( file , <STR_LIT> , thiz , thiz , reg0 ) ; } if ( CSKY_TARGET_ARCH ( CK801 ) ) { if ( vcall_offset > maxoff || vcall_offset < - maxoff ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else if ( delta > maxoff || delta < - maxoff ) { fprintf ( file ,


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned GPRSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; unsigned NumRegs = LastReg - FirstReg ; unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) , ABI . StackAddrSpace ( ) ) ; int FI = MFI . CreateFixedObject ( FrameObjSize , FrameObjOffset , false ,


_mm_setzero_ps ( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> Instrumentation -> InstrumentInstruction ( Inst , Operands


<s> else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) vvvv = vvvvFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) vvvv &= <NUM_LIT> ; insn -> vvvv = static_cast <


<s> if ( Writer -> is64Bit ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else Record<ISA_LIT>Relocation ( Writer , Asm , Layout , Fragment , Fixup ,


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; const char * Prefix = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegs ; i ++ ) { O <<


<s> goto constant_arg ; case SIMD_ARG_LANE_PAIR_INDEX : gcc_assert ( opc > <NUM_LIT> ) ; if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; unsigned int nunits = GET_MODE_NUNITS ( vmode ) . to_constant ( ) ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , nunits / <NUM_LIT> , exp ) ; int lane = INTVAL ( op [ opc ] ) ; op [ opc ] = gen_int_mode ( ENDIAN_LANE_N ( nunits / <NUM_LIT> , lane ) , SImode ) ; } goto constant_arg ; case SIMD_ARG_LANE_QUADTUP_INDEX : gcc_assert ( opc > <NUM_LIT> ) ; if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; unsigned int nunits = GET_MODE_NUNITS ( vmode ) . to_constant ( ) ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , nunits / <NUM_LIT> , exp ) ; int lane = INTVAL ( op [ opc ] ) ; op [ opc ] = gen_int_mode ( ENDIAN_LANE_N ( nunits / <NUM_LIT> , lane ) , SImode ) ; } goto constant_arg ; case SIMD_ARG_CONSTANT : constant_arg : if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> , opc + <NUM_LIT> - have_retval ) ; return const0_rtx ; } break ; case SIMD_ARG_STOP : gcc_unreachable ( ) ; } opc ++ ; } } switch ( opc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI ->


<s> } Parser . Lex ( ) ; unsigned Mcpu = <STR_LIT> ( CPU ) ; if ( check ( Mcpu == <STR_LIT> , L , <STR_LIT> ) ) return addErrorSuffix ( <STR_LIT> ) ; if ( ForceCPUSubTypeAll ) { parseToken ( AsmToken :: EndOfStatement ) ; return false ; } bool OSX_OK = Mcpu == <STR_LIT> || Mcpu == <STR_LIT> || ( Mcpu >= <STR_LIT> && Mcpu <= <STR_LIT> ) ; if ( check ( ! OSX_OK , L , <STR_LIT> ) || check ( is<ISA_LIT>64 ( ) && ( Mcpu != <STR_LIT> ) , L , <STR_LIT> ) || check ( ! is<ISA_LIT>64 ( ) && ( Mcpu == <STR_LIT> ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer (


<s> const <ISA_LIT>RegisterInfo * TRI = getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getNoPreservedMask ( ) ) ; BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB , <NUM_LIT> ) ; thisMBB -> addSuccessor ( sinkMBB , <NUM_LIT> ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) , LabelReg ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , mainDstReg ) . addImm ( <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( mainDstReg ) . addMBB ( mainMBB ) .

addReg ( restoreDstReg ) . addMBB ( thisMBB ) ;


<s> if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; EVT ElementType = InputVector . getValueType ( ) . getVectorElementType ( ) ; unsigned EltSize = ElementType . getSizeInBits


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) { initAsmInfo ( ) ; if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString


<s> bool hasSlowVGETLNi32 ( ) const { return


<s> unsigned Op1 = getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg (


<s> ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; break ; case <STR_LIT> : Opc = ( IsZExt ? ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) : ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( ( Addr . Offset & <NUM_LIT> ) != <NUM_LIT> ) ) UseOffset = false ; break ; case <STR_LIT> : Opc = <STR_LIT> ; assert ( UseRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = FP64LoadOpc ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Addr .


<s> static unsigned getMinSizeForRegBank ( const RegisterBank & RB ) { switch ( RB . getID


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function &


<s> case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { bool Changed = false ; Changed |= Helper . tryCombineExtendingLoads ( MI ) ; Changed |= Helper . tryCombineIndexedLoadStore ( MI ) ; return Changed ; } case TargetOpcode :: G_STORE : return Helper . tryCombineIndexedLoadStore ( MI ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID (


<s> bool <ISA_LIT>WinCOFFObjectWriter :: recordRelocation ( const MCFixup & Fixup ) const { return true


<s> CommentString = <STR_LIT> ; SupportsDebugInformation = true ; UseDataRegionDirectives = MarkedJTDataRegions ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( T . isMacOSX ( ) && T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ; DwarfFDESymbolsUseAbsDiff = T . isMacOSX ( ) && ! T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; UseIntegratedAssembler = true


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned Mask = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT> ; Mask |= Elt << ( i * <NUM_LIT> ) ; } } return Mask


<s> char buf [ <NUM_LIT> ] ; section * s ; if ( priority == DEFAULT_INIT_PRIORITY ) snprintf ( buf , sizeof ( buf ) , <STR_LIT> ) ; else { snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; } s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_aligned_integer ( INIT_ARRAY_ENTRY_BYTES , symbol


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedScatterBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; auto * Ty = cast < VectorType > ( Input -> getType ( ) ) ; if ( ! ( Ty -> getNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } Value * Mask = I -> getArgOperand (


<s> const <ISA_LIT>MCExpr * A64E = cast < <ISA_LIT>MCExpr > ( UImm16MO . getExpr ( ) ) ; switch ( A64E -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 : case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 : case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G2 : case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G2 : case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1


<s> __builtin_ia32_pmovqb512mem_mask ( ( __v16qi * ) __P , (


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( Op0 . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; SDValue NotOp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; SDValue NotOp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT>


<s> mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = <NUM_LIT> ; } else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = <NUM_LIT> ; if ( nregs <= <NUM_LIT> ) return false ; } * pnregs = nregs ; * pmode = mode


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> unsigned BranchOffset = Insn & <NUM_LIT> ; BranchOffset = SignExtend32 < <NUM_LIT> > ( BranchOffset << <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm


<s> RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z ( TheARM64Target ) ; initializeGlobalISel ( * PassRegistry :: getPassRegistry (


<s> bool hasMSA ( ) const { return STI . getFeatureBits (


<s> static SDValue LowerZERO_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( SVT . getVectorElementType ( ) == <STR_LIT> ) return LowerZERO_EXTEND_Mask ( Op , Subtarget , DAG ) ; assert ( Subtarget . hasFp256 ( ) && <STR_LIT> ) ; return LowerAVXExtend ( Op , DAG


<s> CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation =


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) || N -> getConstantOperandVal ( FirstOp ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast <


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT>


<s> if ( MI -> isCopy ( ) ) CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) { SwapVector [ VecIdx ] . MentionsPhysVR = <NUM_LIT> ; return


<s> Type * Ty = IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( NumElements , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( cast < Instruction > ( Predicate ) ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VecTy -> getNumElements ( ) ) ; <STR_LIT> VCTPID ; switch ( VecTy -> getNumElements ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; } Function * VCTP = <STR_LIT> ( M , VCTPID ) ; Value * TailPredicate = Builder . CreateCall ( VCTP , Processed ) ; Predicate -> replaceAllUsesWith ( TailPredicate ) ; NewPredicates [ Predicate ] = cast < Instruction > ( TailPredicate


<s> Function * ThreadPointerFunc = <STR_LIT> ( M , <STR_LIT> ) ; return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , Offset ) , Type :: getInt8PtrTy

( IRB . getContext ( ) ) -> getPointerTo ( <NUM_LIT> ) ) ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= ( - <NUM_LIT> << Scale ) && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , dl , <STR_LIT> ) ; return true ; } } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return


<s> return __builtin_mve_vcmpneq_v16qi ( __a ,


<s> else if ( Inst -> isFullCopy ( ) ) NextReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( NextReg == SrcReg || ! Register :: isVirtualRegister ( NextReg ) ) break ; SrcReg = NextReg


<s> if ( VTy == <STR_LIT> ) return true ; if ( TLI -> isOperationLegalOrCustom ( Opcode , VTy ) ) continue ; else if ( VTy . isVector ( ) && TLI -> isOperationLegalOrCustom ( Opcode , VTy . getScalarType ( ) ) ) continue ; return true ; } } return true ; } else if ( isa < BinaryOperator > ( J ) && J -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) { return true ; } else if ( isa < UIToFPInst > ( J ) || isa < SIToFPInst > ( J ) || isa < FPToUIInst > ( J ) || isa < FPToSIInst > ( J ) ) { CastInst * CI = cast < CastInst > ( J ) ; if ( CI -> getSrcTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || CI -> getDestTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || isLargeIntegerTy ( TT . isArch32Bit ( ) , CI -> getSrcTy ( ) -> getScalarType ( ) ) || isLargeIntegerTy ( TT . isArch32Bit ( ) , CI -> getDestTy ( ) -> getScalarType ( ) ) ) return true ; } else if ( isLargeIntegerTy ( TT . isArch32Bit ( ) , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: UDiv || J -> getOpcode ( ) == Instruction :: SDiv || J -> getOpcode ( ) == Instruction :: URem || J -> getOpcode ( ) == Instruction :: SRem ) ) { return true ; } else if ( TT . isArch32Bit ( ) && isLargeIntegerTy ( false , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: Shl || J -> getOpcode ( ) == Instruction :: AShr || J -> getOpcode ( ) == Instruction :: LShr ) ) { return true ; } else if ( isa < IndirectBrInst > ( J ) || isa < InvokeInst > ( J ) ) { return true


<s> COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl )


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CSI [ I ] .


<s> AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( TwoRepStos ) { InFlag = Chain . getValue ( <NUM_LIT> ) ; Count = Size ; EVT CVT = Count . getValueType ( ) ; SDValue Left = DAG . getNode ( <STR_LIT> , dl , CVT , Count , DAG . getConstant ( ( AVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , CVT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , ( CVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> , Left , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT>


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT>


<s> } else { Offset = N . getOperand ( <NUM_LIT> ) ; SignExtend = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; } unsigned LegalShiftVal = Log2_32 ( Size ) ; unsigned ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal != <NUM_LIT> && ShiftVal != LegalShiftVal ) return false ; if ( isWorthFolding ( N ) ) return true ; return


<s> if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result

= combineSelectAndUse ( N , N0 , N1 , DCI ) ) return Result ;


<s> subRegIdx = DFP_FP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( Subtarget . isV9 ( ) ) { if ( Subtarget . hasHardQuad ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { subRegIdx = QFP_DFP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else { subRegIdx = QFP_FP_SubRegsIdx ; numSubRegs = <NUM_LIT> ; movOpc = <STR_LIT> ; } } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( numSubRegs == <NUM_LIT> || subRegIdx == nullptr || movOpc == <NUM_LIT> ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * MovMI = nullptr ; for ( unsigned i = <NUM_LIT> ; i != numSubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , subRegIdx [ i ] ) ; unsigned Src = TRI -> getSubReg ( SrcReg , subRegIdx [ i ] ) ; assert ( Dst && Src && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( movOpc ) , Dst ) ; if ( ExtraG0 ) MIB . addReg ( <STR_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ! ConstExpr


<s> case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Or : case Instruction :: Xor : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize <= <NUM_LIT> ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( ~ Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> )


<s> if ( __builtin_expect ( __builtin_tbegin ( <NUM_LIT> ) , <NUM_LIT> ) ) return _HTM_TBEGIN_STARTED ; * _TEXASR_PTR ( TM_buff ) = __builtin_get_texasr ( ) ; * _TEXASRU_PTR ( TM_buff ) = __builtin_get_texasru ( ) ; * _TEXASRL_PTR ( TM_buff ) =


<s> return ( __m128 ) __builtin_ia32_sqrtss ( ( __v4sf


<s> FunctionPass * llvm :: createSgxMCPass ( ) { return new SgxMCPasses (


<s> assert ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_<ISA_LIT>NT && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; switch ( static_cast < unsigned > ( Fixup . getKind ( ) ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF


<s> if ( PREV_INSN ( insn ) == NULL ) return <NUM_LIT> ; seq = NEXT_INSN ( PREV_INSN ( insn ) ) ; if ( GET_CODE ( PATTERN ( seq ) ) == SEQUENCE ) return <NUM_LIT> ; return


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; auto UniqueRS = make_unique < RegScavenger > ( ) ; RS = UniqueRS . get ( ) ; bool Modified = false


<s> MachineInstrBuilder CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; if ( Callee . isReg ( ) ) return false ; MachineInstrBuilder MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIB . add ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } CallSeqStart . addImm ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) ) . addImm ( <NUM_LIT> ) ; MIRBuilder . insertInstr ( MIB ) ; if ( OrigRet . Reg ) { ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > OrigRetIndices ; splitToValueTypes ( OrigRet , <NUM_LIT> , ArgInfos , OrigRetIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigRetIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( )


<s> Register Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ,


<s> SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( GV -> isDeclaration ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset ,


<s> fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; gcc_assert ( fcode < ARRAY_SIZE ( mips_builtins ) ) ; d = & mips_builtins [ fcode ] ; avail = d -> avail ( ) ; gcc_assert ( avail != <NUM_LIT> ) ; if ( TARGET_MIPS16 && ! ( avail & BUILTIN_AVAIL_MIPS16 ) ) { error ( <STR_LIT> , DECL_NAME ( fndecl ) ) ; return ignore ? const0_rtx : CONST0_RTX ( mode ) ; } switch ( d -> builtin_type ) { case MIPS_BUILTIN_DIRECT : return mips_expand_builtin_direct ( d -> icode , target , exp , true ) ; case MIPS_BUILTIN_DIRECT_NO_TARGET : return mips_expand_builtin_direct ( d -> icode , target , exp , false ) ; case MIPS_BUILTIN_MOVT : case MIPS_BUILTIN_MOVF : return mips_expand_builtin_movtf ( d -> builtin_type , d -> icode , d -> cond , target , exp ) ; case MIPS_BUILTIN_CMP_ANY : case MIPS_BUILTIN_CMP_ALL : case


<s> if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef ( ) ) { if ( SDValue Rotate = lowerShuffleAsBitRotate ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , RepeatedMask , Subtarget , DAG ) ; } } if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue PSHUFB = lowerShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable , Subtarget , DAG ) )


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , - StackSize ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; unsigned S1 = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( AFI -> isGPRCalleeSavedArea1Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea1Offset ( ) ; else if ( AFI -> isGPRCalleeSavedArea2Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea2Offset ( ) ; else if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl <


<s> return ( __m512i ) __builtin_ia32_loaddqusi512_mask ( ( const int * ) __P , ( __v16si ) _mm512_setzero_si512 ( )


<s> if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue Op = lowerShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Op ; if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget


<s> Op1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , N1 , DAG . getConstant ( <NUM_LIT> , DL , VecIdxTy ) ) ; Op2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , N1 , DAG . getConstant ( SplitNumElts , DL , VecIdxTy ) ) ; } else { Op1 = SrcSize == <NUM_LIT> ? N1 : widenVec ( DAG , N1 , DL ) ; Op2 = DAG . getUNDEF ( WideVT ) ; } unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ; SmallVector < int , <NUM_LIT> > ShuffV ; if ( Subtarget . isLittleEndian ( ) ) for ( unsigned i = <NUM_LIT> ; i < TrgNumElts ; ++ i ) ShuffV . push_back ( i * SizeMult ) ; else for ( unsigned i = <NUM_LIT> ; i <= TrgNumElts ; ++ i ) ShuffV .

push_back ( i * SizeMult - <NUM_LIT> ) ;


<s> static void compile_for_target ( struct obstack * argv_obstack ) { switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( argv_obstack , NULL ) ; char * * argv = XOBFINISH ( argv_obstack , char * * ) ; const char * epath = getenv ( <STR_LIT> ) ; const char * cpath = getenv ( <STR_LIT> ) ; const char * lpath = getenv ( <STR_LIT> ) ; const char * rpath = getenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT>


<s> virtual bool hasRelocationAddend ( ) const { return is64Bit ? true :


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF

, const MCAsmLayout & Layout ) const override {


<s> if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType


<s> if ( CallTarget ) { assert ( ( CallTarget & <NUM_LIT> ) == CallTarget && <STR_LIT> ) ; unsigned ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> * <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm (


<s> if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; return nullptr ; } if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; if ( ! Value ) return false ; if ( Inv ) Value = ~ Value ; uint64_t Mask = ( <NUM_LIT> << Width ) - <NUM_LIT> ; uint64_t Elem = Value & Mask ; if ( ! AllowMinusOne && Elem == Mask ) return false ; if ( Width == <NUM_LIT> && ( Elem & <NUM_LIT> ) != <NUM_LIT> && ( Elem & <NUM_LIT> ) != <NUM_LIT> ) return false ; if ( Width == <NUM_LIT> && ! isValidNEONi32vmovImm ( Elem ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { Value >>= Width ; if ( ( Value & Mask ) != Elem ) return false ; } return true


<s> SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; EVT CarryVT = Carry . getValueType ( ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getAllOnesConstant ( DL , CarryVT ) ) ; bool IsAdd = Opc == <STR_LIT> || Opc == <STR_LIT> ; SDValue Sum = DAG . getNode ( IsAdd ? <STR_LIT> : <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ; bool IsSigned = Opc == <STR_LIT> || Opc


<s> case AtomicRMWInst :: Xchg : return Inc ; case AtomicRMWInst :: Add : return Builder . CreateAdd ( Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: Sub : return Builder . CreateSub ( Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: And : return Builder . CreateAnd ( Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: Nand : return Builder . CreateNot ( Builder . CreateAnd ( Loaded , Inc ) , <STR_LIT> ) ; case AtomicRMWInst :: Or : return Builder . CreateOr ( Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: Xor : return Builder . CreateXor ( Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: Max : NewVal = Builder . CreateICmpSGT ( Loaded , Inc ) ; return Builder . CreateSelect ( NewVal , Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: Min : NewVal = Builder . CreateICmpSLE ( Loaded , Inc ) ; return Builder . CreateSelect ( NewVal , Loaded , Inc , <STR_LIT> ) ; case AtomicRMWInst :: UMax : NewVal = Builder . CreateICmpUGT ( Loaded ,


<s> AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * FixupExpression = MCBinaryExpr :: createAdd ( MO . getExpr ( )

, MCConstantExpr :: create ( - <NUM_LIT> , Ctx ) , Ctx ) ;


<s> if ( MI == MBB . end ( ) ) continue ; unsigned JTOpcode ; switch ( MI -> getOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB


<s> for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) , Size = <NUM_LIT> ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) continue ; if ( Size == <NUM_LIT> ) { unsigned Align = TRI -> getSpillAlignment ( <STR_LIT> ) ; int Remainder = SpillSlotOffset % Align ; if ( Remainder < <NUM_LIT> ) SpillSlotOffset -= Align + Remainder ; else SpillSlotOffset -= Remainder ; MFI . ensureMaxAlignment (


<s> SmallVector < int , <NUM_LIT> > Mask ( NumElems ) ; for ( unsigned i = <NUM_LIT> , Half = NumElems / <NUM_LIT> ; i != Half ; ++ i ) { Mask [ i * <NUM_LIT> ] = i + Half ; Mask [ i * <NUM_LIT> + <NUM_LIT> ]


<s> if ( ST -> getNumElements ( ) != NumElts ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { if ( Inst -> getArgOperand ( i ) -> getType ( ) != ST -> getElementType ( i ) ) return nullptr ; } Value * Res = UndefValue :: get ( ExpectedType ) ; IRBuilder < > Builder ( Inst ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { Value * L = Inst -> getArgOperand ( i ) ; Res = Builder . CreateInsertValue ( Res , L , i ) ; } return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst -> getType ( ) ==


<s> I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; OutStreamer . EmitInstruction ( I ,


<s> static unsigned calculateMaxStackAlignment ( const MachineFrameInfo * FFI ) { unsigned MaxAlign = <NUM_LIT> ; for ( int i = FFI -> getObjectIndexBegin ( ) , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; unsigned Align = FFI -> getObjectAlignment ( i ) ; MaxAlign = std :: max ( MaxAlign , Align ) ; } return MaxAlign


<s> if ( cfun -> is_thunk ) return <NUM_LIT> ; if ( cfun -> machine -> lr_save_state ) return cfun -> machine -> lr_save_state - <NUM_LIT> ; push_topmost_sequence ( ) ; top = get_insns ( ) ; pop_topmost_sequence ( ) ; reg = gen_rtx_REG ( Pmode , LR_REGNO ) ; for ( insn = NEXT_INSN ( top ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) { if ( ! SIBLING_CALL_P ( insn


<s> <ISA_LIT>leTargetMachine :: <ISA_LIT>leTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM ,

CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL (


<s> return __builtin_ia32_subph128_mask ( __B , __C , _mm_setzero_ph ( ) ,


<s> return ( __m512 ) __builtin_ia32_broadcastf32x4_512 ( ( __v4sf ) __A ,


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L ==


<s> O << ( MO2 . getImm ( ) ? <STR_LIT> : <STR_LIT> ) << getRegisterName ( MO1


<s> case E_DImode : return gen_loadwb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case E_DFmode : return gen_loadwb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( adjustment


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF .

getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> void <ISA_LIT>ELFStreamer :: EmitPad ( int64_t Offset ) { SPOffset -=


<s> if ( Subtarget -> hasFPAO ( ) ) return AM . Scale < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> ; } return -


<s> label = gen_label_rtx ( ) ; rtx tmp = gen_rtx_fmt_ee ( UNORDERED , VOIDmode , flag , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; } if ( GET_MODE ( set_dst ) != mode ) { gcc_assert ( mode == CCAmode || mode == CCCmode || mode == CCOmode || mode == CCPmode || mode == CCSmode || mode == CCZmode ) ; set_dst = gen_rtx_REG ( mode , FLAGS_REG


<s> if ( VT . isVector ( ) ) return LowerVSETCC ( Op , Subtarget , DAG ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Op0 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , Op0 , Op1 , CC , dl , Op0 , Op1 , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! Op1 . getNode ( ) ) { assert ( Op0 . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; if ( IsStrict ) return DAG . getMergeValues ( { Op0 , Chain } , dl ) ; return Op0 ; } } SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! EFLAGS ) return SDValue ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT>CC , EFLAGS ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res ,


<s> static rtx altivec_expand_dst_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , <NUM_LIT> ) , <NUM_LIT> ) ; tree arglist = TREE_OPERAND ( exp , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 , arg2 ; enum machine_mode mode0 , mode1 , mode2 ; rtx pat , op0 , op1 , op2 ; struct builtin_description * d ; size_t i ; * expandedp = false ; d = ( struct builtin_description * ) bdesc_dst ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_dst ) ; i ++ , d ++ ) if ( d -> code == fcode ) { arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; op2 = expand_expr ( arg2 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode2 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; * expandedp = true ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> , d -> name ) ; return const0_rtx ; } if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( Pmode , op0 ) ; if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1


<s> bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const override { return false


<s> static bool mips_get_unaligned_mem ( rtx * op , unsigned int width , int bitpos , rtx * left , rtx * right ) { rtx first , last ; if ( ! MEM_P ( * op ) ) return false ; if ( width != <NUM_LIT> && ( ! TARGET_64BIT || width != <NUM_LIT> ) ) return false ; if ( bitpos % BITS_PER_UNIT != <NUM_LIT> ) return false ; if ( MEM_ALIGN ( * op ) >= width ) return false ; * op = adjust_address ( * op , BLKmode , <NUM_LIT> ) ; set_mem_size ( * op , GEN_INT ( width / BITS_PER_UNIT


<s> if ( CCValid != <STR_LIT> ) return false ; if ( CCMask == <STR_LIT> ) Invert = ! Invert ; else if ( CCMask != <STR_LIT> ) return false ; SDNode * ICmp = Glue . getNode ( ) ; if ( ICmp -> getOpcode ( ) != <STR_LIT> ) return false ; SDNode * Select = ICmp -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Select -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! Select -> hasOneUse ( ) ) return false ; auto * CompareVal = dyn_cast < ConstantSDNode > ( ICmp -> getOperand ( <NUM_LIT> ) ) ; if ( ! CompareVal ) return false ; auto * TrueVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal ) return false ; auto * FalseVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! FalseVal ) return false ; if ( CompareVal -> getZExtValue ( ) == FalseVal -> getZExtValue ( ) ) Invert = ! Invert ; else if ( CompareVal -> getZExtValue ( ) != TrueVal -> getZExtValue ( ) ) return false ; auto * NewCCValid = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * NewCCMask = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! NewCCValid || ! NewCCMask ) return false ; CCValid = NewCCValid -> getZExtValue ( ) ; CCMask = NewCCMask -> getZExtValue ( ) ; if ( Invert ) CCMask ^= CCValid ; Glue = Select -> getOperand


<s> Negative = false ; OffsetRegShifted = false ; OffsetIsReg = false ; OffsetRegNum = - <NUM_LIT> ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . is ( AsmToken :: Plus ) ) Parser . Lex ( ) ; else if ( NextTok . is ( AsmToken :: Minus ) ) { Negative = true ; Parser . Lex ( ) ; } const AsmToken & OffsetRegTok = Parser . getTok ( ) ; if ( OffsetRegTok . is ( AsmToken :: Identifier ) ) { OffsetIsReg = ! MaybeParseRegister ( Op , false ) ; if ( OffsetIsReg ) OffsetRegNum = Op . getReg ( ) ; } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; OffsetRegShifted =


<s> UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE


<s> unsigned AddrReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) )


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_cvtusepi32_storeu_epi16 ( void *


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = false ; WeakRefDirective = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler = true ; HasIdentDirective = true


<s> void addBankedRegOperands ( MCInst & Inst , unsigned


<s> void emitRX ( unsigned Opcode , unsigned DstReg , MCOperand Imm , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { MCInst tmpInst ; tmpInst . setOpcode ( Opcode ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; tmpInst . addOperand ( Imm


<s> unsigned <ISA_LIT>TTI :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( SrcBytes && Alignment && Alignment < SrcBytes ) Cost *= ( SrcBytes / Alignment ) ; return Cost


<s> TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; SDValue TP = lowerThreadPointer ( DL , DAG ) ; SDValue Offset ; switch ( model ) { case TLSModel :: GeneralDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; break ; } case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec


<s> if ( new_align < DECL_ALIGN ( decl ) ) SET_DECL_ALIGN ( decl ,


<s> __inline__ static unsigned long long sh_media_MSHFHI_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> if ( Vec . getOpcode ( ) == <STR_LIT> ) return Result ; EVT VT = Vec . getValueType ( ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec


<s> bool <ISA_LIT>16TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags ,


<s> ABI = & P . getABI ( ) ; ABIFlagsSection . setAllFromPredicates ( P


<s> static <ISA_LIT>Operand * CreateExpr ( const MCExpr * Val , SMLoc S , SMLoc E , bool Is<ISA_LIT>64 ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand (


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT>


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; const uint32_t * Mask ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const auto * TRI = Subtarget . getRegisterInfo ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( AssignFnFixed , AssignFnVarArg , Subtarget , false ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , false ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , OutArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; Mask = getMaskForArgs ( OutArgs , Info , * TRI , MF ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) constrainOperandRegClass ( MF , * TRI , MRI , * Subtarget . getInstrInfo ( ) , * Subtarget . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn (


<s> unsigned Directive = Subtarget . getDarwinDirective ( ) ; if ( Subtarget . isGigaProcessor ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> << CPUDirectives [ Directive ] << '\n' ; bool Result = AsmPrinter :: doInitialization ( M ) ; assert ( MMI ) ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer . SwitchSection ( TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection (


<s> void emitPair ( IRBuilder < > & IRB , uint64_t Offset , Value * A , Value * B ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset <<

<STR_LIT> << Offset + <NUM_LIT> << <STR_LIT> ) ;


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { Register Reg = Register :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) ) continue ; Closure C ( ClosureID ++ , { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back ( std :: move ( C ) ) ; } for ( Closure & C : Closures ) { LLVM_DEBUG ( C . dump ( MRI ) ) ; if ( isReassignmentProfitable ( C , MaskDomain ) ) { reassign ( C , MaskDomain ) ; ++ NumClosuresConverted ; Changed =


<s> auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; InEpilogCFI = false ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , nullptr , - <NUM_LIT> , <NUM_LIT> ) ; CurFrame -> EpilogMap [ CurrentEpilog ] . Instructions . push_back ( Inst ) ; CurrentEpilog = nullptr


<s> RBegin = RBeginIdx == <NUM_LIT> ? ( unsigned ) <STR_LIT> : GPRArgRegs [ RBeginIdx ] ; REnd = <STR_LIT> ; } if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int FrameIndex = MFI -> CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg


<s> void <ISA_LIT>TargetStreamer :: emitInst ( uint32_t Inst , char Suffix ) { llvm_unreachable (


<s> int i , used = <NUM_LIT> ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( x ) + is_dest ) ) ; return <NUM_LIT> ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return <NUM_LIT> ; } case SET : return regs_used ( SET_SRC ( x ) , <NUM_LIT> ) | regs_used ( SET_DEST ( x ) , <NUM_LIT> ) ; case RETURN : return <NUM_LIT> ; case CLOBBER : is_dest =


<s> for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) if (

bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSCallEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo + <NUM_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO .

getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> V = DAG . getBitcast ( <STR_LIT> , V ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } V = DAG . getBitcast ( <STR_LIT> , V ) ; } else { V = DAG . getAnyExtOrTrunc ( V , DL , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; } ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( Splat ) { if ( Splat . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; Splat = CreateMMXElement ( Splat ) ; if ( Subtarget . hasSSE1 ( ) ) { if ( NumElts == <NUM_LIT> ) Splat = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Splat , Splat ) ; unsigned ShufMask = ( NumElts > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , Splat , DAG . getTargetConstant ( ShufMask , DL , <STR_LIT> ) ) ; } Ops . append ( NumElts , Splat ) ; } else { for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Ops . push_back ( CreateMMXElement ( BV -> getOperand ( i ) ) ) ; } while ( Ops . size ( ) > <NUM_LIT> ) { unsigned NumOps = Ops . size ( ) ; unsigned IntrinOp = ( NumOps == <NUM_LIT> ? <STR_LIT> : ( NumOps == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; SDValue Intrin = DAG . getConstant ( IntrinOp , DL , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; i += <NUM_LIT> ) Ops [ i / <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Intrin , Ops [ i ] , Ops [ i + <NUM_LIT> ] ) ; Ops . resize ( NumOps / <NUM_LIT>


<s> MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBSizes [ MI -> getParent ( ) -> getNumber ( ) ] -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; AdjustBBOffsetsAfter ( MBB ,


<s> if ( ! NewMul ) { assert ( MulAmt != <NUM_LIT> && MulAmt != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; int64_t SignMulAmt = C -> getSExtValue ( ) ; if ( ( SignMulAmt != INT64_MIN ) && ( SignMulAmt != INT64_MAX ) && ( SignMulAmt != - INT64_MAX ) ) { int NumSign = SignMulAmt > <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; bool IsPowerOf2_64PlusOne = isPowerOf2_64 ( NumSign * SignMulAmt - <NUM_LIT> ) ; bool IsPowerOf2_64MinusOne = isPowerOf2_64 ( NumSign * SignMulAmt + <NUM_LIT> ) ; if ( IsPowerOf2_64PlusOne ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( NumSign * SignMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( IsPowerOf2_64MinusOne ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( NumSign * SignMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) ) ; } if ( ( IsPowerOf2_64PlusOne || IsPowerOf2_64MinusOne ) && NumSign == - <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } } if ( NewMul ) DCI . CombineTo ( N , NewMul , false ) ; return SDValue ( )


<s> return getParser ( ) . Error ( L , Msg , Range


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ; return SDValue (


<s> unsigned Opcode = I . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opcode ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands (


<s> } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , false , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) ,


<s> const <ISA_LIT>MCExpr * <ISA_LIT>AsmParser :: adjustPICRelocation ( <ISA_LIT>MCExpr :: VariantKind VK , const MCExpr * subExpr ) { if ( getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) { switch ( VK


<s> assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } } return


<s> Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg5 = MRI -> createVirtualRegister


<s> else FrameObjOffset = ByVal . Address ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = CC . intArgRegs ( ) [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , DL , DAG . getRegister ( VReg , RegTy ) , StorePtr , MachinePointerInfo

( FuncArg , Offset ) , false , false , <NUM_LIT> ) ;


<s> if ( ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) ) return false ; if ( LocVT == <STR_LIT> && ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State )


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , I . getFrameIdx ( ) , RC ,


<s> REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; ix86_sse_copysign_to_positive ( adj , adj , force_reg ( mode , op1 ) , NULL_RTX ) ; adj = expand_simple_binop ( mode , PLUS , adj , op1 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; expand_fix ( op0 , adj


<s> for ( auto * L : Labels ) { auto * Label = cast < MCSymbolELF > ( L ) ; getAssembler ( ) . registerSymbol ( * Label ) ; Label -> setOther ( ELF


<s> MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( )


<s> void addTLSRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; if ( STI . in<ISA_LIT>16Mode (


<s> StringRef Format2 = Name . slice ( Next , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format2 , NameLoc ) ) ; setFpFormat ( Format1 ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; setFpFormat ( Format2 ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> gpr_size = ( gpr_reg_num * reg_size + <NUM_LIT> ) & ~ <NUM_LIT> ; } else if ( fpr_size ) offset = - ( int ) ( next_cum . fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD - ( int ) ( GP_ARG_NUM_REG * reg_size ) ; if ( gpr_size + fpr_size ) { rtx reg_save_area = assign_stack_local ( BLKmode , gpr_size + fpr_size , <NUM_LIT> ) ; gcc_assert ( MEM_P ( reg_save_area ) ) ; reg_save_area = XEXP ( reg_save_area , <NUM_LIT> ) ; if ( GET_CODE ( reg_save_area ) == PLUS ) { gcc_assert ( XEXP ( reg_save_area , <NUM_LIT> ) == virtual_stack_vars_rtx ) ; gcc_assert ( CONST_INT_P ( XEXP ( reg_save_area , <NUM_LIT> ) ) ) ; offset += INTVAL ( XEXP ( reg_save_area , <NUM_LIT> ) ) ; } else gcc_assert ( reg_save_area == virtual_stack_vars_rtx ) ; } cfun -> machine -> varargs_save_offset = offset ; save_area = plus_constant ( Pmode , virtual_stack_vars_rtx , offset ) ; } } else { first_reg_offset = next_cum . words ; save_area = crtl -> args . internal_arg_pointer ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && targetm . calls . must_pass_in_stack ( arg ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( arg . type ) , arg . type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area , first_reg_offset * reg_size ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; rs6000_move_block_from_reg ( GP_ARG_MIN_REG + first_reg_offset , mem , nregs ) ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_HARD_FLOAT && ! no_rtl && next_cum . fregno <= FP_ARG_V4_MAX_REG && cfun -> va_list_fpr_size ) { int fregno = next_cum . fregno , nregs ; rtx cr1 = gen_rtx_REG ( CCmode , CR1_REGNO ) ; rtx lab = gen_label_rtx ( ) ; int off = ( GP_ARG_NUM_REG * reg_size ) + ( ( fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , cr1 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , lab ) , pc_rtx ) ) ) ; for ( nregs = <NUM_LIT> ; fregno <= FP_ARG_V4_MAX_REG && nregs < cfun -> va_list_fpr_size ; fregno ++ , off += UNITS_PER_FP_WORD , nregs ++ ) { mem = gen_rtx_MEM ( TARGET_HARD_FLOAT ? DFmode : SFmode , plus_constant ( Pmode , save_area , off ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; ( void ) SPAdj ; ( void ) RS ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned Reg = Subtarget . isDarwinABI ( ) ? ( LP64 ? <STR_LIT> : <STR_LIT> ) : ( LP64 ? <STR_LIT> : <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) { unsigned ShiftBits = get<ISA_LIT>RegisterNumbering ( DestReg ) * <NUM_LIT> ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg ) . addImm ( <NUM_LIT> - ShiftBits ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT>


<s> const MachineOperand & Src = SrcR1 == DstR ? Index : Base ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( Opcode , Offset ) ) ; const MachineOperand & SrcR = SrcR1 == DstR ? Base : Index ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , ADDri , DstR ) . add ( SrcR ) . addImm ( Offset . getImm ( ) ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } if ( NewMI ) { MBB . getParent ( ) -> substituteDebugValuesForInst ( * I , * NewMI , <NUM_LIT> ) ; MBB . erase ( I ) ; I =


<s> do { const MachineInstr * MI = MemOps [ SIndex ] . MI ; int Offset = MemOps [ SIndex ] . Offset ; const MachineOperand & PMO = getLoadStoreRegOp ( * MI ) ; Register PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? std :: numeric_limits < unsigned > :: max ( ) : TRI -> getEncodingValue ( PReg ) ; unsigned Latest = SIndex ; unsigned Earliest = SIndex ; unsigned Count = <NUM_LIT> ; bool CanMergeToLSDouble = STI -> isThumb2 ( ) && isNotVFP && isValidLSDoubleOffset ( Offset ) ; if ( STI -> isCortexM3 ( ) && isi32Load ( Opcode ) && PReg == getLoadStoreBaseOp ( * MI ) . getReg ( ) ) CanMergeToLSDouble = false ; bool CanMergeToLSMulti = true ; if ( STI -> hasSlowOddRegister ( ) && ! isNotVFP && ( PRegNum % <NUM_LIT> ) == <NUM_LIT> ) CanMergeToLSMulti = false ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) CanMergeToLSMulti = CanMergeToLSDouble = false ; if ( AssumeMisalignedLoadStores && ! mayCombineMisaligned ( * STI , * MI ) ) CanMergeToLSMulti = CanMergeToLSDouble = false ; unsigned Limit ; switch ( Opcode ) { default : Limit = UINT_MAX ; break ; case <STR_LIT> : case <STR_LIT> : Limit = <NUM_LIT> ; break ; } for ( unsigned I = SIndex + <NUM_LIT> ; I < EIndex ; ++ I , ++ Count ) { int NewOffset = MemOps [ I ] . Offset ; if ( NewOffset != Offset + ( int ) Size ) break ; const MachineOperand & MO = getLoadStoreRegOp ( * MemOps [ I ]


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock ::


<s> if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ; unsigned Flags = MI -> getFlags ( ) ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( ! ( TSFlags & <STR_LIT> ) && Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT> ; printPCRelImm ( MI , <NUM_LIT> , OS ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { MCInst Data32MI ( * MI


<s> case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor =