<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op1 = U -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( U -> getOpcode ( ) == <STR_LIT> && Imm -> getAPIntValue ( ) . getBitWidth ( ) == <NUM_LIT> && Imm -> getAPIntValue ( ) . isIntN ( <NUM_LIT> ) ) return false ; if ( U -> getOpcode ( ) == <STR_LIT> && ( Imm -> getAPIntValue ( ) == UINT8_MAX || Imm -> getAPIntValue ( ) == UINT16_MAX || Imm -> getAPIntValue ( ) == UINT32_MAX ) ) return false ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) && ( - Imm -> getAPIntValue ( ) ) . isSignedIntN ( <NUM_LIT> ) ) return false ; } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) { if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> ) { SDValue U0 = U -> getOperand ( <NUM_LIT> ) ; SDValue U1 = U -> getOperand ( <NUM_LIT> ) ; if ( U0 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U0 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } if ( U1 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U1 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return false ; break ; } } if ( Root -> getOpcode ( ) == <STR_LIT> && isNullConstant ( Root -> getOperand ( <NUM_LIT> ) ) && ( Root -> getOperand ( <NUM_LIT> ) . isUndef ( ) || <STR_LIT> ( Root -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) return false ; return true


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~ <NUM_LIT> ; if ( MCELFStreamer * MES = dyn_cast < MCELFStreamer > ( & Parser . getStreamer ( ) ) )

MES -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;


<s> void addRegCRRCOperands ( MCInst & Inst ,


<s> if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask (


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ; return Success


<s> __vector float __vf1 ; __vs8 = ( __vector signed short ) ( __vector unsigned long long ) { __A , __A } ; __vi4 = vec_vupklsh ( __vs8 ) ; __vf1 = ( __vector float )


<s> unsigned Register = VectorDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg (


<s> case <STR_LIT> : Binary |= ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; break ; case <STR_LIT> : Binary |= ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; break ; } Binary |= getMachineOpValue ( MI , <NUM_LIT>


<s> if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return createMachOStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ; if ( TheTriple . isOSWindows ( ) ) return createWinCOFFStreamer ( Ctx


<s> printVisibility ( name , GVar -> getVisibility ( ) ) ; Constant * C = GVar -> getInitializer ( ) ; const Type * Type = C -> getType ( ) ; unsigned Size = TD -> getTypeAllocSize ( Type ) ; unsigned Align = TD -> getPreferredAlignmentLog ( GVar ) ; const MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GVar , Mang , TM ) ; OutStreamer . SwitchSection ( TheSection ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> hasExternalLinkage ( ) || GVar -> isWeakForLinker ( ) ) && ! TheSection -> getKind ( ) . isMergeableCString ( ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasExternalLinkage ( ) ) { O << <STR_LIT> << name << '\n' ; O << <STR_LIT> << name << <STR_LIT> << Size << <STR_LIT> << Align ; } else if ( GVar -> hasLocalLinkage ( ) ) { O << TAI -> getLCOMMDirective ( ) << name << ',' << Size << ',' << Align ; } else if ( ! GVar -> hasCommonLinkage ( ) ) { O << <STR_LIT> << name << '\n' << TAI -> getWeakDefDirective ( ) << name << '\n' ; EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; WriteAsOperand ( O , GVar , false , GVar -> getParent ( ) ) ; } O << '\n' ; EmitGlobalConstant ( C ) ; return ; } else { O << <STR_LIT> << name << ',' << Size ; if ( Subtarget . isDarwin9 ( ) ) O << ',' << Align ; } if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; WriteAsOperand ( O , GVar , false , GVar -> getParent ( ) ) ; O << <STR_LIT> ; } O << '\n' ; return ; } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: CommonLinkage : O << <STR_LIT> << name << '\n' << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage


<s> bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8


<s> BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> AnalyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MIB ) ; MIB . addMBB ( NextBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( * MI ) ; MI -> eraseFromParent (


<s> MCInst tmpInst ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; tmpInst . setLoc ( IDLoc ) ; if ( <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= -


<s> gcc_assert ( nops != <NUM_LIT> || pred != PRED_m ) ; nargs = nops + <NUM_LIT> ; if ( ! check_num_arguments ( nargs ) || ! require_vector_type ( i , VECTOR_TYPE_svbool_t ) ) return false ; i += <NUM_LIT> ; } else { nargs = nops ; if ( ! check_num_arguments ( nargs ) ) return false ; } return true


<s> if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) PrevAddc = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) PrevAddc = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( PrevAddc == nullptr ) return AddCombineTo64bitMLAL ( AddcNode , DCI , Subtarget ) ; SDValue MLAL = AddCombineTo64bitMLAL ( PrevAddc , DCI , Subtarget ) ; if ( MLAL != SDValue ( PrevAddc , <NUM_LIT> ) ) return AddCombineTo64bitMLAL ( AddcNode , DCI , Subtarget ) ; SDNode * UmlalNode = nullptr ; SDValue AddHi ; if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else if ( AddcNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { UmlalNode = AddcNode -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AddHi = AddcNode -> getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } auto * Zero = dyn_cast < ConstantSDNode > ( UmlalNode -> getOperand ( <NUM_LIT> ) ) ; if ( ! Zero || Zero -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( AddcNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( ! AddeNode ) return SDValue ( ) ; if ( ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == Zero && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == UmlalNode ) || ( AddeNode -> getOperand (

<NUM_LIT> ) . getNode ( ) == UmlalNode && AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == Zero ) ) {


<s> auto * HalfTy = HalfV -> getType ( ) ; return FullTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) == <NUM_LIT> * HalfTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) ; } ; auto extractHalf = [ ] ( Value * FullV , Value * HalfV ) { auto * FullVT = cast < FixedVectorType > ( FullV -> getType ( ) ) ; auto * HalfVT = cast < FixedVectorType > ( HalfV -> getType ( ) ) ; return FullVT -> getNumElements ( ) == <NUM_LIT> * HalfVT -> getNumElements ( ) ; } ; ArrayRef < int > M1 , M2 ; Value * S1Op1 , * S2Op1 ; if ( ! match ( Op1 , m_Shuffle ( m_Value ( S1Op1 ) , m_Undef ( ) , m_Mask ( M1 ) ) ) || ! match ( Op2 , m_Shuffle ( m_Value ( S2Op1 ) , m_Undef ( ) , m_Mask ( M2 ) ) ) ) return false ; if ( ! areTypesHalfed ( S1Op1 , Op1 ) || ! areTypesHalfed ( S2Op1 , Op2 ) || ! extractHalf ( S1Op1 , Op1 ) || ! extractHalf ( S2Op1 , Op2 ) ) return false ; int M1Start = -


<s> return ( uint16x4_t ) __builtin_neon_vcgeuv4hi ( ( int16x4_t )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( NumIssued == <NUM_LIT> ) return Hazard ; break ; case <STR_LIT> : if ( NumIssued >= <NUM_LIT> ) return Hazard ; break ; case <STR_LIT> : break ; } if ( HasCTRSet && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) return NoopHazard ; if ( isLoad && NumStores ) { unsigned LoadSize ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT>


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; Op2 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill *


<s> rtx op2 = XEXP ( src , <NUM_LIT> ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , <NUM_LIT> ) ; op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != <NUM_LIT> || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != <NUM_LIT> || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG (


<s> SDValue GlobalAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT>


<s> vld3q_dup_u16 ( const uint16_t * __a ) { uint16x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi


<s> int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , &

num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_RegList , Parser ) ; Op -> RegList . List = new SmallVector < unsigned , <NUM_LIT> > ( Regs . begin ( ) , Regs


<s> unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; if ( Opc == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } if ( Opc == <STR_LIT> && ! hasV8Ops ( ) ) { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresV8 ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return Match_RequiresV8 ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT>


<s> bool enableEarlyIfConversion ( ) const override { return true


<s> break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm


<s> return N -> getOpcode ( ) == Opc && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ,


<s> SysAliasReg ( const char * N , uint16_t E , bool R , FeatureBitset F ) :

SysAlias ( N , E , F ) , NeedsReg ( R ) { }


<s> SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } if ( F . hasStructRetAttr ( ) && ( Subtarget -> is64Bit ( ) || Subtarget -> isTargetKnownWindowsMSVC ( ) ) ) { unsigned Reg = <ISA_LIT>MFInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; unsigned CopyTo = Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CopyTo ) . addReg ( Reg ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] ,


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; Parser . Lex ( ) ; const MCExpr * Val = nullptr ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , true , End ) ) return <NUM_LIT> ; if ( ! Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Error ( Start , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Var . Length ; break ; case IOK_SIZE : CVal = Info . Var . Size ; break ; case IOK_TYPE : CVal = Info . Var .


<s> if ( ! User -> isMachineOpcode ( ) ) return false ; if ( User -> getMachineOpcode ( ) != <STR_LIT> && User -> getMachineOpcode ( ) != <STR_LIT> ) return false ; SDNode * Op2 = User -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ! Op2 -> isMachineOpcode ( ) ) return false ; if ( Op2 -> getMachineOpcode ( ) != <STR_LIT> && Op2 -> getMachineOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op2 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; if ( ! C -> isNullValue ( ) ) return false ; } return true


<s> emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; MI . tieOperands ( <NUM_LIT> ,


<s> const SubOperator * Sub = dyn_cast < SubOperator > ( CE ) ; if ( ! Sub ) return nullptr ; const PtrToIntOperator * SubLHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; const PtrToIntOperator * SubRHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! SubLHS || ! SubRHS ) return nullptr ; if ( SubLHS -> getPointerAddressSpace ( ) != <NUM_LIT> || SubRHS -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; const GlobalVariable * GVLHS = dyn_cast < GlobalVariable > ( SubLHS -> getPointerOperand ( ) ) ; const GlobalVariable * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ; if ( ! GVLHS || ! GVRHS ) return nullptr ; if ( GVRHS -> isThreadLocal ( ) || GVRHS -> getName ( ) != <STR_LIT> || ! GVRHS -> hasExternalLinkage ( ) || GVRHS -> hasInitializer ( ) || GVRHS -> hasSection ( ) ) return nullptr ; if ( GVLHS -> isThreadLocal ( ) ) return nullptr ; return MCSymbolRefExpr :: Create ( TM . getSymbol ( GVLHS , Mang ) , MCSymbolRefExpr ::


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT>


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode ,


<s> unsigned int live_regs_mask = <NUM_LIT> ; * count = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < CSKY_NGPR_REGS ; reg ++ ) { bool save = false ; if ( CSKY_TARGET_ARCH ( CK801 ) && reg > <NUM_LIT> && reg < <NUM_LIT> ) continue ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > <NUM_LIT> ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && reg == CSKY_LR_REGNUM && ( ! crtl -> is_leaf

|| csky_far_jump_used_p ( ) ) ) save = true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool needsTwoConstNR ( ) const { return


<s> const MCOperand & BaseReg = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] .

contains ( IndexReg . getReg ( ) ) ) ) return true ;


<s> return ( isGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind


<s> cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != <NUM_LIT> ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; label2 = pc_rtx


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { IsResolved = true ; ( void ) adjustFixupValue ( Fixup , Value , & Asm . getContext


<s> rtx xops [ <NUM_LIT> ] ; int regno ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; ++ regno ) { char name [ <NUM_LIT> ] ; if ( ! ( ( pic_labels_used >> regno ) & <NUM_LIT> ) ) continue ; get_pc_thunk_name ( name , regno ) ; if ( USE_HIDDEN_LINKONCE ) { tree decl ; decl = build_decl ( FUNCTION_DECL , get_identifier ( name ) , error_mark_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_ONE_ONLY ( decl ) = <NUM_LIT> ; ( * targetm . asm_out . unique_section ) ( decl , <NUM_LIT> ) ; named_section ( decl , NULL , <NUM_LIT> ) ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputc ( '\n' , asm_out_file


<s> static SDValue lowerMSASplatZExt ( SDValue Op , unsigned OpNr , SelectionDAG & DAG ) { EVT ResVecTy = Op -> getValueType ( <NUM_LIT> ) ; EVT ViaVecTy = ResVecTy ; SDLoc DL ( Op ) ; SDValue LaneA ; SDValue LaneB = Op -> getOperand ( <NUM_LIT> ) ; if ( ResVecTy == <STR_LIT>


<s> if ( ! HasEVEX || CD8_Scale == <NUM_LIT> ) return isInt < <NUM_LIT> > ( Value ) ; assert ( isPowerOf2_32 ( CD8_Scale ) && <STR_LIT> ) ; if ( Value & ( CD8_Scale - <NUM_LIT> ) ) return false ; int CDisp8 = Value / CD8_Scale ; if ( ! isInt < <NUM_LIT> > ( CDisp8 ) ) return false ; ImmOffset = CDisp8 -


<s> if ( ST -> hasSlowLoadDSubregister ( ) && Opcode == Instruction :: InsertElement && ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { if ( ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; if ( ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return std :: max (

BaseT :: getVectorInstrCost ( Opcode , ValTy , Index ) , <NUM_LIT> ) ;


<s> MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange =


<s> if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val > - <NUM_LIT> &&


<s> return getSTI ( ) . getFeatureBits ( )


<s> unsigned GetFrameReg ( const MCContext & Ctx , MCStreamer & Out ) { unsigned FrameReg = GetFrameRegGeneric ( Ctx


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinCFISaveSP ( unsigned


<s> const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Register BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> && Subtarget . isSVR4ABI ( ) ) { setUsesTOCBasePtr ( * MBB -> getParent ( )


<s> MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; SDValue VMask = getMaskNode ( MaskNode , <STR_LIT> ( <STR_LIT> , NumElts ) , Subtarget ,


<s> return Is64Bit && ( ! TargetTriple . isX32 ( )


<s> } if ( src_aligned ) emit_move_insn ( reg0 , src ) ; else { emit_insn ( gen_unaligned_loadsi ( low_reg , src ) ) ; src = next_consecutive_mem ( src ) ; emit_insn ( gen_unaligned_loadsi ( hi_reg , src ) ) ; } if ( dst_aligned ) emit_move_insn ( dst , reg0 ) ; else { emit_insn ( gen_unaligned_storesi ( dst , low_reg ) ) ; dst = next_consecutive_mem ( dst ) ; emit_insn ( gen_unaligned_storesi ( dst , hi_reg ) ) ; } src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; } gcc_assert ( len < <NUM_LIT> ) ; if ( len >= <NUM_LIT> ) { reg0 = gen_reg_rtx ( SImode ) ; src = adjust_address ( src , SImode , <NUM_LIT> ) ; dst = adjust_address ( dst , SImode , <NUM_LIT> ) ; if ( src_aligned ) emit_move_insn ( reg0 , src ) ; else emit_insn ( gen_unaligned_loadsi ( reg0 , src ) ) ; if ( dst_aligned ) emit_move_insn ( dst , reg0 ) ; else emit_insn ( gen_unaligned_storesi ( dst , reg0 ) ) ; src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; len -= <NUM_LIT> ; } if ( len == <NUM_LIT> ) return true ; if ( len >= <NUM_LIT> ) { dst = adjust_address ( dst , HImode , <NUM_LIT> ) ; src = adjust_address ( src , HImode , <NUM_LIT> ) ; reg0 = gen_reg_rtx ( SImode ) ; if ( src_aligned ) emit_insn ( gen_zero_extendhisi2 ( reg0 , src ) ) ; else emit_insn ( gen_unaligned_loadhiu ( reg0 , src ) ) ; if ( dst_aligned ) emit_insn ( gen_movhi ( dst , gen_lowpart ( HImode , reg0 ) ) ) ; else emit_insn ( gen_unaligned_storehi ( dst , gen_lowpart ( HImode , reg0 ) ) ) ; src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; if ( len == <NUM_LIT> ) return true ; } dst = adjust_address ( dst , QImode , <NUM_LIT> ) ; src = adjust_address ( src , QImode , <NUM_LIT>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand


<s> void <ISA_LIT>InstPrinter :: printU10ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned short Value = MI -> getOperand ( OpNo


<s> const SDValue LHS = V . getOperand ( <NUM_LIT> ) ; const SDValue RHS = V . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( LHS ) ) return true ; if ( RHS . getOpcode ( ) == <STR_LIT> && isWorthFoldingSHL ( RHS ) ) return true ; } return


<s> static inline unsigned char getAM3Offset ( unsigned AM3Opc ) { return AM3Opc


<s> EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; if ( SrcVT == <STR_LIT> ) { unsigned ResultReg = createResultReg


<s> if ( ! reload_in_progress && ! reload_completed && ! ia64_move_ok ( op0 , op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ( mode == Pmode || mode == ptr_mode ) && symbolic_operand ( op1 , VOIDmode ) ) { HOST_WIDE_INT addend = <NUM_LIT> ; enum tls_model tls_kind ; rtx sym = op1 ; if ( GET_CODE ( op1 ) == CONST && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { addend = INTVAL ( XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ) ; sym = XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ; } tls_kind = tls_symbolic_operand_type ( sym ) ; if ( tls_kind ) return ia64_expand_tls_address ( tls_kind , op0 , sym , op1 , addend ) ; if ( any_offset_symbol_operand ( sym , mode ) ) addend = <NUM_LIT> ; else if ( aligned_offset_symbol_operand ( sym , mode ) ) { HOST_WIDE_INT addend_lo ,


<s> void startImplicitITBlock ( ) { assert ( ! inITBlock ( ) ) ; ITState . Cond =


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( ~ MCE -> getValue ( ) , <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> static SDValue PerformFPExtendCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST


<s> Inst . addOperand ( MCOperand :: createReg ( QFRegs [ getReg (


<s> enum ix86_builtin_func_type ftype ; const struct builtin_description * d ; size_t i ; tree decl ; tree attrs_load , attrs_type_load , attrs_store , attrs_type_store ; tree attrs_log , attrs_type_log ; if ( ! flag_tm ) return ; if ( ! builtin_decl_explicit_p ( BUILT_IN_TM_LOAD_1 ) ) return ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOAD_1 ) ; attrs_load = DECL_ATTRIBUTES ( decl ) ; attrs_type_load = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ; attrs_log = DECL_ATTRIBUTES


<s> temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ]


<s> int sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED ,


<s> VectorType * VTy = cast < VectorType > ( I -> getType ( ) ) ; auto * DupXIntrI = dyn_cast < IntrinsicInst > ( OpIndices ) ; if ( ! DupXIntrI || DupXIntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; auto * SplatValue = dyn_cast < ConstantInt > ( DupXIntrI -> getOperand ( <NUM_LIT> ) ) ; if ( ! SplatValue || SplatValue -> getValue ( ) . uge ( VTy -> getElementCount ( ) . getKnownMinValue ( ) ) ) return false ; LLVMContext & Ctx = I -> getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint


<s> EVT IntPtr = getPointerTy ( ) ; EVT SPTy = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr


<s> static bool mep_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( reload_in_progress || reload_completed ) ) { char e = mep_section_tag ( x ) ; return ( e != 't' && e != 'b'


<s> const char * <ISA_LIT>DarwinTargetAsmInfo :: getEHGlobalPrefix ( ) const { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> getDarwinVers ( ) > <NUM_LIT> )


<s> int offset ; if ( to == STACK_POINTER_REGNUM ) offset = sparc_compute_frame_size ( get_frame_size ( ) , crtl -> is_leaf ) ; else offset = <NUM_LIT> ; offset += SPARC_STACK_BIAS ; return offset


<s> MEM_COPY_ATTRIBUTES ( mem , orig_addr ) ; set_mem_size ( mem , GET_MODE_SIZE ( mode ) ) ; do_load_for_compare ( dest , mem , mode


<s> __malloc_ptr = malloc ( __size + __align ) ; if ( ! __malloc_ptr ) return ( ( void * ) <NUM_LIT> ) ; __aligned_ptr = ( void * ) ( ( ( size_t ) __malloc_ptr + __align ) & ~ ( ( size_t ) ( __align ) - <NUM_LIT> ) ) ; ( ( void * * ) __aligned_ptr ) [


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> auto BundleStart = BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addDisp ( Target , - <NUM_LIT> , <STR_LIT> ) . getInstr ( ) ; BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( ScratchReg , RegState :: Kill ) . addDisp ( Target , - <NUM_LIT> , <STR_LIT> ) ; auto BundleEnd = BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addReg ( ScratchReg , RegState :: Kill


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , false

) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ;


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , offset )


<s> static __inline unsigned long long sh_media_LDHI_L ( void * p , int


<s> if ( ! IsMemcpySmall ( Len ) ) return false ; bool i64Legal = Subtarget -> is64Bit ( ) ; while ( Len ) { MVT VT ; if ( Len >= <NUM_LIT> && i64Legal ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Len == <NUM_LIT> ) ; VT = <STR_LIT> ; } unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , nullptr , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , true , DestAM ) ; assert ( RV && <STR_LIT> ) ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -=


<s> return ( poly8x16_t ) __builtin_neon_vmulpv16qi ( ( int8x16_t ) __a , (


<s> unsigned short mode ; unsigned short n


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; const TargetMachine & TM = DAG . getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel (


<s> bool <ISA_LIT>WinCOFFTargetStreamer :: emitFPOProc ( const MCSymbol * ProcSym , unsigned ParamsSize , SMLoc L ) { if ( haveOpenFPOData ( ) ) { getContext ( ) . reportError ( L , <STR_LIT> ) ; return true ; } CurFPOData = llvm :: make_unique <


<s> assert ( ! BytesAdded && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count


<s> return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> assert ( <STR_LIT> . contains ( DestReg , SrcReg ) && <STR_LIT> ) ; if ( st . hasV6Ops ( ) || <STR_LIT> . contains ( SrcReg ) || ! <STR_LIT> . contains ( DestReg ) ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> )

, DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;


<s> LLVM_DEBUG ( const MachineLoop * Loop = MLI -> getLoopFor ( MBB ) ; if ( Loop && Loop -> getHeader ( ) == MBB ) dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; ) ; MachineBasicBlock * SinglePredMBB = getSingleSchedPred ( MBB , MLI -> getLoopFor ( MBB ) ) ; if ( SinglePredMBB == nullptr || SchedStates . find ( SinglePredMBB ) == SchedStates . end ( ) ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * SinglePredMBB ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; LLVM_DEBUG ( HazardRec -> dumpState ( ) ; ) ; for ( MachineInstr & MI : SinglePredMBB -> terminators ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; bool TakenBranch = ( MI . isBranch ( ) && ( TII -> getBranchInfo ( MI ) . isIndirect ( ) || TII -> getBranchInfo ( MI ) . getMBBTarget ( ) == MBB ) ) ; HazardRec -> emitInstruction ( &


<s> return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv2di ( (


<s> return ( uint64x1_t ) ( __a [ <NUM_LIT> ] > __b [ <NUM_LIT> ] ?


<s> return ( __m128i ) __builtin_ia32_psllqi128 ( ( __v2di


<s> unsigned encoding ; const MCOperand op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( op1 . isReg ( ) && <STR_LIT> ) ; encoding = ( get<ISA_LIT>RegisterNumbering ( op1 . getReg ( )


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU )


<s> MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MF -> push_back ( restoreMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( XII -> getGlobalBaseReg ( MF ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB , Subtarget -> ClassifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } } else PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> (


<s> case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , <NUM_LIT> ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return


<s> uint64_t ObjSize = cast < ConstantSDNode > ( Size ) -> getZExtValue ( ) ; assert ( ObjSize % <NUM_LIT> == <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * BaseMemOperand = MF . getMachineMemOperand ( DstPtrInfo , MachineMemOperand :: MOStore , ObjSize , <NUM_LIT> ) ; bool UseSetTagRangeLoop = kSetTagLoopThreshold >= <NUM_LIT> && ( int ) ObjSize >= kSetTagLoopThreshold ; if ( ! UseSetTagRangeLoop ) return EmitUnrolledSetTag ( DAG , dl , Chain , Addr , ObjSize , BaseMemOperand , ZeroData ) ; if ( ObjSize % <NUM_LIT> != <NUM_LIT> ) { SDNode * St1 = DAG . getMachineNode ( ZeroData ? <STR_LIT> : <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Addr , Addr , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Chain } ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( St1 ) , { BaseMemOperand } ) ; ObjSize -= <NUM_LIT> ; Addr = SDValue ( St1 , <NUM_LIT> ) ; Chain = SDValue ( St1 , <NUM_LIT> ) ; } const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SDValue Ops [ ] = { DAG . getConstant ( ObjSize , dl ,


<s> if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = get<ISA_LIT>SubSuperRegister ( RegNo


<s> unsigned RBegin , REnd ; CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; NumGPRs = REnd - RBegin ; } else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced ) : <NUM_LIT> ; } unsigned Align = MF . getTarget ( ) . getSubtargetImpl

( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ;


_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( Mst -> isTruncatingStore ( ) ) return SDValue ( ) ; if ( SDValue ScalarStore = reduceMaskedStoreToScalarStore ( Mst , DAG , Subtarget ) ) return ScalarStore ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { APInt DemandedBits ( APInt :: getSignMask ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedBits , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewMask = TLI . SimplifyMultipleUseDemandedBits ( Mask , DemandedBits , DAG ) ) return DAG . getMaskedStore ( Mst -> getChain ( ) , SDLoc ( N ) , Mst -> getValue ( ) , Mst -> getBasePtr ( ) , Mst -> getOffset ( ) , NewMask , Mst -> getMemoryVT ( ) , Mst -> getMemOperand ( ) , Mst -> getAddressingMode ( ) ) ; } SDValue Value = Mst ->


<s> getParser ( ) . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Off ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement


<s> MCELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer (


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST (

TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) {


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> unsigned VectorWidth = cast < FixedVectorType > ( ActiveLaneMask -> getType ( ) ) -> getNumElements ( ) ; Builder . SetInsertPoint ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( ActiveLaneMask -> getOperand ( <NUM_LIT> ) , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( ActiveLaneMask ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , VectorWidth ) ; <STR_LIT> VCTPID


<s> unsigned R ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! ( R = MO . getReg ( ) ) ) continue ; const MachineFunction & MF = * MBB . getParent (


<s> for ( Use & U : llvm :: make_early_inc_range ( TileZero -> uses ( ) ) ) { Instruction * I = cast < Instruction > ( U . getUser ( ) ) ; Value * Vec ; if ( match ( I , m_BitCast ( m_Value ( Vec ) ) ) ) { I -> replaceAllUsesWith ( VecZero ) ; I -> eraseFromParent ( ) ; } } TileZero -> eraseFromParent (


<s> SectMap :: const_iterator it = m_SectToExData . find ( & pSect ) ; if ( it == m_SectToExData . end ( ) ) { return


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_SysReg , Ctx ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . FeatureBits = FeatureBits ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> static std :: pair < bool , bool > GetSignReturnAddress ( const Function & F ) { if ( ! F . hasFnAttribute ( <STR_LIT> ) ) { const Module & M = * F . getParent ( ) ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( <STR_LIT> ) ) ) { if ( Sign -> getZExtValue ( ) ) { if ( const auto * All = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( <STR_LIT> ) ) ) return { true , All -> getZExtValue ( ) } ; return { true , false } ; } } return { false , false } ; } StringRef Scope = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) return { false , false } ; if ( Scope . equals ( <STR_LIT> ) ) return { true , true } ; assert ( Scope . equals


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Op = <STR_LIT> ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Op = <STR_LIT> ; bool writeback = ( P == <NUM_LIT> ) || ( W == <NUM_LIT> ) ; unsigned idx_mode = <NUM_LIT> ; if ( P && writeback ) idx_mode = <STR_LIT> ; else if ( ! P && writeback ) idx_mode = <STR_LIT> ; if ( writeback && ( Rn == <NUM_LIT> || Rn == Rt ) ) S = MCDisassembler :: SoftFail ; if ( reg ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Opc = <STR_LIT>


<s> if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc

:: PIC_ ) addPass ( create<ISA_LIT>TLSDynamicCallPass ( ) ) ;


<s> return Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( Tok . getString ( ) . lower ( ) ) ; if ( isParsingInlineAsm ( ) && isParsingIntelSyntax ( ) && RegNo == <STR_LIT> ) RegNo = <NUM_LIT> ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) return Error ( StartLoc , <STR_LIT> + Tok . getString ( ) + <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } else if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { if ( <STR_LIT> ( RegNo ) ) return Error ( StartLoc , <STR_LIT> + Tok . getString ( ) + <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; } if ( RegNo == <NUM_LIT> && ( Tok . getString ( ) == <STR_LIT> || Tok . getString ( ) == <STR_LIT> ) ) { RegNo = <STR_LIT> ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Parser . getTok ( )


<s> SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) ? <NUM_LIT>


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI ,


<s> unsigned <ISA_LIT>AsmParser :: getATReg ( SMLoc Loc ) { unsigned ATIndex = AssemblerOptions . back ( ) -> getATRegIndex ( ) ; if ( ATIndex == <NUM_LIT> ) { reportParseError ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned AT = getReg ( ( isGP64bit ( ) ) ? <STR_LIT> : <STR_LIT> ,


<s> __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT>


<s> bool isPackedVectorType ( EVT SomeVT ) { if ( ! SomeVT . isVector ( ) ) return false ; return SomeVT . getVectorNumElements ( ) >


<s> for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isImplicit ( ) ) continue ; RegList . push_back ( MO . getReg ( ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != -


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElems * <NUM_LIT> ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskVec ( NumElems * <NUM_LIT> , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) MaskVec [ i ] = i * <NUM_LIT> ; SDValue V = DAG . getVectorShuffle ( NVT , DL , DAG . getNode ( <STR_LIT> , DL , NVT , In ) , DAG . getUNDEF ( NVT ) , & MaskVec [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getIntPtrConstant (


<s> ASM_OUTPUT_ALIGN ( asm_out_file , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; } for ( i = <NUM_LIT> ; i < n_deferred_plabels ; i ++ ) { targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( deferred_plabels [ i ]


<s> static int rs6000_tls_symbol_ref_1 ( rtx * x , void *


<s> bool hasRecipPrec ( ) const { return HasRecipPrec


<s> bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; if ( ConstSplatVal && ( Subtarget -> hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget -> hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; if ( ! IsLoad && Subtarget -> hasInt256 ( ) && ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( ! IsLoad ) return SDValue ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( Subtarget -> hasVLX ( ) && ScalarSize == <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT>


<s> LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal , <NUM_LIT>


<s> return getBoundedStrlen ( DAG , DL , Chain , Src ,

DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc


<s> MVT ExtVT = VT ; MVT EltVT = VT . getVectorElementType ( ) ; int V2Index = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , [ & Mask ] ( int M ) { return M >= ( int ) Mask . size ( ) ; } ) - Mask . begin ( ) ; bool IsV1Zeroable = true ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( i != V2Index && ! Zeroable [ i ] ) { IsV1Zeroable = false ; break ; } if ( SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ) { V2S = DAG . getNode ( <STR_LIT> , DL , EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getNode ( <STR_LIT> , DL , VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ]


<s> Vm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( ! SelectAddr ( Node , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return NULL ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray (


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val


<s> assert ( ( vectorWidth == <NUM_LIT> || vectorWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( Vec . isUndef ( ) ) return Result ; EVT VT = Vec . getValueType ( ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ; SDValue VecIdx = DAG . getIntPtrConstant ( IdxVal


<s> MCTargetStreamer * create<ISA_LIT>ObjectTargetELFStreamer ( MCStreamer


<s> assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto MSRMapper = <STR_LIT> ( ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto PStateMapper = <STR_LIT> ( ) ; uint32_t PStateField = PStateMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateField , getContext ( ) ) ) ; Parser . Lex ( ) ; return


<s> unsigned <ISA_LIT>Subtarget :: getSpecialAddressLatency ( ) const { return <NUM_LIT>


<s> return true ; } case FusionFeature :: FK_SldiAdd : return ( matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ) || ( matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ) ; case FusionFeature :: FK_RotateLeftXor : return matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_RotateRightXor : return matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_LoadCmp1 : case FusionFeature :: FK_LoadCmp2 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; if ( SecondMI . getOpcode ( ) == <STR_LIT> && matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ) return true ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_LoadCmp3 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_ZeroMoveCTR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_ZeroMoveLR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature ::


<s> return __builtin_mve_vcreateq_sv4si ( __a ,


<s> } else if ( STI . isTargetDarwin ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; } else if ( STI . isTargetWin32 ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetDragonFly ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetFreeBSD ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; if ( STI . isTargetLinux ( ) || STI . isTargetWin32 ( ) || STI . isTargetWin64 ( ) || STI . isTargetDragonFly ( ) ) { BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ; } else if ( STI . isTargetDarwin ( ) ) { unsigned ScratchReg2 ; bool SaveScratch2 ; if ( CompareStackPointer ) { ScratchReg2 = GetScratchRegister ( Is64Bit , IsLP64 , MF , true ) ; SaveScratch2 = false ; } else { ScratchReg2 = GetScratchRegister ( Is64Bit , IsLP64 , MF , false ) ; SaveScratch2 = MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) ; } assert ( ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) || SaveScratch2 ) && <STR_LIT> ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg2 , RegState :: Kill ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & PrologueMBB ) ; if ( Is64Bit ) { const unsigned RegAX = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg10 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg11 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVrr = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVri = IsLP64 ?


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; auto * ShiftC = dyn_cast < ConstantSDNode > ( N1 ) ; auto * AndC = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftC || ! AndC ) return SDValue ( ) ; APInt MaskVal = AndC -> getAPIntValue ( ) ; APInt NewMaskVal = MaskVal . lshr ( ShiftC -> getAPIntValue ( ) ) ; unsigned OldMaskSize = MaskVal . getMinSignedBits ( ) ; unsigned NewMaskSize = NewMaskVal . getMinSignedBits ( ) ; if ( ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) || ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) ) { SDLoc DL ( N ) ; SDValue NewMask = DAG . getConstant ( NewMaskVal , DL , VT ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewShift ,


<s> const SmallVectorImpl < MachineBasicBlock * > & getOrder ( ) const { return


<s> static <ISA_LIT>ABIInfo Unknown ( ) { return <ISA_LIT>ABIInfo ( <STR_LIT>


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - TFI . getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( ) )

Offset -= TFI . getOffsetOfLocalArea ( ) ;


<s> static bool rs6000_hard_regno_mode_ok ( unsigned int regno , machine_mode


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> int <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * SrcVTy , Value * Ptr , bool VariableMask , unsigned Alignment ) { assert ( SrcVTy -> isVectorTy ( ) && <STR_LIT> ) ; unsigned VF = SrcVTy -> getVectorNumElements ( ) ; PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) -> getVectorElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ; if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy , VariableMask , Alignment ,


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) { initAsmInfo ( )


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>MCInstrAnalysis ( Info


<s> if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } } else { SymToPrint = getSymbol ( GV


<s> for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : MemoryFoldTable3 ) addTableEntry ( Entry , TB_INDEX_3 | TB_FOLDED_LOAD ) ; for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : MemoryFoldTable4 ) addTableEntry ( Entry , TB_INDEX_4 | TB_FOLDED_LOAD ) ; for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : BroadcastFoldTable2 ) addTableEntry ( Entry , TB_INDEX_2 | TB_FOLDED_LOAD | TB_FOLDED_BCAST ) ; for ( const <ISA_LIT>MemoryFoldTableEntry & Entry : BroadcastFoldTable3 ) addTableEntry ( Entry ,


<s> vmlal_n_u16 ( uint32x4_t a , uint16x4_t b , uint16_t c ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && ! cast < LoadSDNode > ( N0 ) -> isVolatile ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , SDLoc ( N ) , VT , Load ) ; } return SDValue (


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : { SDValue Lo = DAG . getConstant ( INTVal . trunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue Hi = DAG . getConstant ( INTVal . lshr ( <NUM_LIT> ) . trunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; if ( ! ST -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( INTVal , DL , <STR_LIT> ) ) ; } } if ( ! ST -> hasVFP3 ( ) ) return SDValue ( ) ; if ( IsDouble && Subtarget -> isFPOnlySP ( ) ) return SDValue ( ) ; int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL


<s> switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return opcode ; default : llvm_unreachable (


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG ,


<s> static __inline unsigned long long sh_media_MSHFHI_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MSHFHI_W ( ( v4hi )


<s> SDLoc DL ( MS ) ; SDValue Value = MS -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; EVT CastVT = VT . changeVectorElementType ( EltVT ) ; Value = DAG . getBitcast ( CastVT , Value ) ; } SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , Value , VecIndex ) ; return DAG . getStore ( MS -> getChain ( ) , DL , Extract , Addr , MS -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment ,

MS -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr (


<s> setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) { assert ( OrigArg . Regs . size ( ) == <NUM_LIT> && MRI . getType ( OrigArg . Regs [ <NUM_LIT> ] ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! OrigArg . Flags [ <NUM_LIT> ] . isZExt ( ) ) { Register OrigReg = OrigArg . Regs [ <NUM_LIT> ] ; Register WideReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; OrigArg . Regs [ <NUM_LIT> ] = WideReg ; BoolArgs . push_back ( { OrigReg , WideReg } ) ; } } if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; <ISA_LIT>IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; if ( ! BoolArgs . empty ( ) ) { for ( auto & KV : BoolArgs ) { Register OrigReg = KV . first ; Register WideReg = KV . second ; LLT WideTy = MRI . getType ( WideReg ) ; assert ( MRI . getType ( OrigReg ) . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildTrunc ( OrigReg , MIRBuilder . buildAssertZExt ( WideTy , WideReg , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ) ; } } <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( )


<s> const MCSymbolData & A_SD = Asm . getSymbolData ( * A ) ; const MCSymbolData * A_Base = Asm . getAtom ( & A_SD ) ; const MCSymbol * B = & Target . getSymB ( ) -> getSymbol ( ) ; if ( B -> isTemporary ( ) ) B = & Writer -> findAliasedSymbol ( * B ) ; const MCSymbolData & B_SD = Asm . getSymbolData ( * B ) ; const MCSymbolData * B_Base = Asm . getAtom ( & B_SD ) ; if ( Target . getSymA ( ) -> getKind ( ) != MCSymbolRefExpr :: VK_None || Target . getSymB ( ) -> getKind ( ) != MCSymbolRefExpr :: VK_None ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsPCRel ) report_fatal_error ( <STR_LIT> , false ) ; if ( A_Base == B_Base && A_Base ) report_fatal_error ( <STR_LIT> , false ) ; if ( A -> isUndefined ( ) || B -> isUndefined ( ) ) { StringRef Name = A -> isUndefined ( ) ? A -> getName ( ) : B -> getName ( ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> ) ; } Value += Writer -> getSymbolAddress ( & A_SD , Layout ) - ( ! A_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( A_Base , Layout ) ) ; Value -= Writer -> getSymbolAddress ( & B_SD , Layout ) - ( ! B_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( B_Base , Layout ) ) ; if ( ! A_Base ) Index = A_SD . getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_UNSIGNED ; MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; Writer -> addRelocation ( A_Base , Fragment -> getParent ( ) , MRE ) ; if ( B_Base ) RelSymbol = B_Base ; else Index = B_SD . getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_SUBTRACTOR ; } else { const MCSymbol * Symbol = & Target . getSymA ( ) -> getSymbol ( ) ; if ( Symbol -> isTemporary ( ) && Value ) { const MCSection & Sec = Symbol -> getSection ( ) ; if ( ! Asm . getContext ( ) . getAsmInfo ( ) -> isSectionAtomizableBySymbols ( Sec ) ) Asm . addLocalUsedInReloc ( * Symbol ) ; } const MCSymbolData & SD = Asm . getSymbolData ( * Symbol ) ; RelSymbol = Asm . getAtom ( & SD ) ; if ( Symbol -> isInSection


<s> unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; while ( ! OrigBB -> succ_empty ( ) ) { MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || ! Succ -> begin ( ) -> isPHI ( ) ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( llvm :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; unsigned OrigBBI = OrigBB -> getNumber ( ) ; unsigned NewBBI = NewBB -> getNumber ( ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; unsigned OrigBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = OrigBB -> begin ( ) , E = OrigBB -> end ( ) ; I != E ; ++ I ) OrigBBSize += TII -> GetInstSizeInBytes ( I ) ; BBSizes [ OrigBBI ] = OrigBBSize ; BBOffsets [ NewBBI ] = BBOffsets [ OrigBBI ] + BBSizes [ OrigBBI ] ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E = NewBB -> end ( ) ; I != E ; ++ I ) NewBBSize += TII -> GetInstSizeInBytes ( I ) ; BBSizes [ NewBBI ] = NewBBSize ; MachineInstr * ThumbJTMI = prior ( NewBB -> end ( ) ) ; if ( ThumbJTMI -> getOpcode ( ) == <STR_LIT> ) { unsigned OrigOffset = BBOffsets [ OrigBBI ] + BBSizes [ OrigBBI


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_ShiftedImmediate ) ; Op -> RegShiftedImm . ShiftTy = ShTy ; Op -> RegShiftedImm . SrcReg = SrcReg ; Op -> RegShiftedImm . ShiftImm =


<s> case Function :: ExternalLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; break ; case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; O << <STR_LIT> << CurrentFnName << '\n' ; break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; EmitAlignment ( MF . getAlignment ( ) , F ) ; O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O <<


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | <NUM_LIT> ; else if ( Value > <NUM_LIT> && Value <= <NUM_LIT> ) Value =


<s> WriteGraph ( OS , G , false , <STR_LIT> + MF .


<s> emitDataProcessingInstruction ( MI , <STR_LIT> ) ; unsigned JTIndex = ( MCID . Opcode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getIndex ( ) : MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; emitInlineJumpTable ( JTIndex ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { emitLoadStoreInstruction ( MI , <STR_LIT> ) ; emitInlineJumpTable ( MI . getOperand ( <NUM_LIT> )


<s> assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? Register ( TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs (


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoDsp ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNoDsp (


<s> AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , <STR_LIT> ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT (


<s> } unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; } AddOptionalDefs ( MIB ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; else MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) .


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; const TargetMachine & TM = mf . getTarget ( ) ; MRI = & mf . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator I = mf . begin ( ) , E = mf . end ( ) ; I != E ; ++ I ) if ( processMachineBasicBlock ( I ) ) Changed = true ; return Changed


<s> rtx_code_label * true_label , * done_label ; rtx cmp_result ; true_label = gen_label_rtx ( ) ; done_label = gen_label_rtx ( ) ; create_input_operand ( & ops [ <NUM_LIT> ] , true_label , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; mips_prepare_builtin_arg ( & ops [ <NUM_LIT> ] , exp , <NUM_LIT> ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , const0_rtx ) ; if ( GET_CODE ( ops [ <NUM_LIT> ] . value ) != REG ) ops [ <NUM_LIT> ] . value = force_reg ( ops [ <NUM_LIT> ] . mode , ops [ <NUM_LIT> ] . value ) ; if ( ( cbranch = maybe_gen_insn ( icode , <NUM_LIT> , ops ) ) == NULL_RTX ) error ( <STR_LIT> ) ; cmp_result = gen_reg_rtx