<s> DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; TLI = TLIP ? & TLIP -> getTLI ( * L -> getHeader ( ) -> getParent ( ) ) : nullptr ; DL = & L -> getHeader ( ) -> getModule ( ) -> getDataLayout ( ) ; this -> L = L ; ActiveLaneMask = nullptr ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( ) ) return false ; Setup = FindLoopIterations ( Preheader ->


<s> break ; case AttributeType :: Numeric : Result += getULEB128Size ( item . Tag ) ; Result += getULEB128Size ( item . IntValue ) ; break ; case AttributeType :: Text : Result += getULEB128Size ( item . Tag ) ; Result += item . StringValue . size ( ) + <NUM_LIT> ; break ; case AttributeType :: NumericAndText : Result += getULEB128Size ( item . Tag ) ; Result += getULEB128Size ( item . IntValue ) ; Result += item . StringValue . size (


<s> unsigned char value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( value <= <NUM_LIT> &&


<s> TargetLowering :: LegalizeAction <ISA_LIT>TargetLowering :: getCustomOperationAction ( SDNode & Op ) const { if ( isPackingSupportOpcode ( Op . getOpcode ( ) )


<s> uint64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t UImm = Imm << ( <NUM_LIT> - BitSize ) >> (


<s> Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand ( <NUM_LIT> ) ; BasicBlock * BB = TileDef -> getParent ( ) ; BasicBlock :: iterator Iter = TileDef -> getIterator ( ) ; IRBuilder < > Builder ( BB , ++ Iter ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , Ptr , Stride , TileDef } ; Instruction * TileStore = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; return TileStore


<s> YMMUsed = true ; break ; } } } if ( ! YMMUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) processBasicBlock ( * I ) ; if ( FnHasLiveInYmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear ( )


<s> uint8_t getISARevisionValue ( ) { return ( uint8_t )


<s> unsigned HOST_WIDE_INT const1 ; unsigned HOST_WIDE_INT const2 = <NUM_LIT> ; if ( ! CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) ) return false ; const1 = UINTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( op1 , <NUM_LIT> ) ) || ~ UINTVAL ( XEXP ( op1 , <NUM_LIT> ) ) != const1 ) return false ; if ( GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ) { const2 = UINTVAL ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ; * sub0 = XEXP ( XEXP ( op0


<s> static MachineBasicBlock :: const_iterator PrevCrossBBInst ( MachineBasicBlock :: const_iterator MBBI ) { const MachineBasicBlock * MBB = MBBI -> getParent ( ) ; while ( MBBI == MBB -> begin ( ) ) { if ( MBB == & MBB -> getParent ( ) -> front ( ) ) return nullptr ; MBB = MBB ->


<s> return __builtin_ia32_vcvtudq2ph256_mask ( ( __v8si ) __A , _mm_setzero_ph ( ) , (


<s> ConstantPool & AssemblerConstantPools :: getOrCreateConstantPool ( const MCSection * Section ) { return ConstantPools [ Section


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; GlobalDirective = <STR_LIT> ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HasSingleParameterDotFile = false


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ,


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits

, TLI . getShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


<s> static bool sparc_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( decl && flag_delayed_branch && ( TARGET_ARCH64 ||


<s> void printxmmwordmem ( const MCInst * MI , unsigned OpNo ,


<s> SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( TLI . getVarArgsFrameOffset ( ) , <STR_LIT> ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op

. getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> void <ISA_LIT>InstPrinter :: printModImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { MCOperand Op = MI -> getOperand ( OpNum ) ; if ( Op . isExpr ( ) ) return printOperand ( MI , OpNum , STI , O ) ; unsigned Bits = Op . getImm ( ) & <NUM_LIT> ; unsigned Rot = ( Op . getImm ( ) & <NUM_LIT> ) >> <NUM_LIT> ; bool PrintUnsigned =


<s> SDValue VecCstHighBitcast = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getNode ( <STR_LIT> , DL , VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { SDValue CstMask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue VecCstMask = DAG . getNode ( <STR_LIT> , DL , VecIntVT , CstMask , CstMask , CstMask , CstMask ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; } SDValue CstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> ) ) , <STR_LIT> ) ; SDValue CstFAddArray [ ] = { CstFAdd , CstFAdd , CstFAdd , CstFAdd , CstFAdd , CstFAdd , CstFAdd , CstFAdd } ; SDValue VecCstFAdd = DAG . getNode ( <STR_LIT> , DL , VecFloatVT , makeArrayRef ( & CstFAddArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue HighBitcast = DAG . getNode ( <STR_LIT> , DL , VecFloatVT , High ) ; SDValue FHigh = DAG . getNode ( <STR_LIT> , DL , VecFloatVT , HighBitcast , VecCstFAdd ) ; SDValue LowBitcast = DAG . getNode ( <STR_LIT> , DL , VecFloatVT


<s> StringRef <ISA_LIT>InstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName (


<s> SDValue Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . getAlignment ( ) , Nd . getMemOperand ( ) -> getFlags ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) , Nd . getMemOperand ( ) -> getFlags ( ) ) ; if ( ! Subtarget . isLittle ( ) ) std ::


<s> return addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( Opc ) ) , FrameIdx , Offset ) . addImm


<s> void <ISA_LIT>AsmPrinter :: printJTBlockOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { assert ( ! Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; O << * JTISymbol << <STR_LIT> ; const char * JTEntryDirective = MAI -> getData32bitsDirective ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool UseSet = MAI -> hasSetDirective ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > JTSets ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; bool isNew = JTSets . insert ( MBB ) ; if ( UseSet && isNew ) { O << <STR_LIT> << * Get<ISA_LIT>SetPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) , MBB ) << ',' << * MBB -> getSymbol ( )


<s> assert ( Code . size ( ) < <NUM_LIT> && <STR_LIT> ) ; unsigned ExistingPrefixSize = Code . size ( ) ; unsigned TargetPrefixMax


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( poly8x8_t ) __builtin_aarch64_qtbx3v8qi ( ( int8x8_t ) r , __o , ( int8x8_t


<s> auto RemMemOp = MF . getMachineMemOperand ( MMOBase , P2HalfMemSize , RemMemSize ) ; if ( MI . getOpcode ( ) == G_STORE ) { if ( Size < <NUM_LIT> ) Val = MIRBuilder . buildAnyExt ( s32 , Val ) . getReg ( <NUM_LIT> ) ; if ( Size > <NUM_LIT> && Size < <NUM_LIT> ) Val = MIRBuilder . buildAnyExt ( s64 , Val ) . getReg ( <NUM_LIT> ) ; auto C_P2HalfMemSize = MIRBuilder . buildConstant ( s32 , P2HalfMemSize ) ; auto Addr = MIRBuilder . buildPtrAdd ( PtrTy , BaseAddr , C_P2HalfMemSize ) ; if ( MI . getOpcode ( ) == G_STORE && MemSize <= <NUM_LIT> ) { MIRBuilder . buildStore ( Val , BaseAddr , * P2HalfMemOp ) ; auto C_P2Half_InBits = MIRBuilder . buildConstant ( s32 , P2HalfMemSize * <NUM_LIT> ) ; auto Shift = MIRBuilder . buildLShr ( s32 , Val , C_P2Half_InBits ) ; MIRBuilder . buildStore ( Shift , Addr , * RemMemOp ) ; } else { auto Unmerge = MIRBuilder . buildUnmerge ( s32 , Val ) ; MIRBuilder . buildStore ( Unmerge . getReg ( <NUM_LIT> ) , BaseAddr , * P2HalfMemOp ) ; MIRBuilder . buildStore ( Unmerge . getReg ( <NUM_LIT> ) , Addr , * RemMemOp ) ; } } if ( MI . getOpcode ( ) == G_LOAD ) { if ( MemSize <= <NUM_LIT> ) { auto * Load4MMO = MF . getMachineMemOperand ( MMOBase , <NUM_LIT> , <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) MIRBuilder . buildLoad ( Val , BaseAddr , * Load4MMO ) ; else { auto Load = MIRBuilder . buildLoad ( s32 , BaseAddr , * Load4MMO ) ; MIRBuilder . buildTrunc ( Val , Load . getReg ( <NUM_LIT> ) ) ; } } else { auto C_P2HalfMemSize = MIRBuilder . buildConstant ( s32 , P2HalfMemSize ) ; auto Addr = MIRBuilder . buildPtrAdd (


<s> static SDValue LowerToTLSGeneralDynamicModel32 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const MVT PtrVT ) { SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG .

getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , InFlag ) ;


<s> static unsigned EnsureStackAlignment ( const <ISA_LIT>FrameLowering * Lowering , unsigned NumBytes ) { return alignTo ( NumBytes , Lowering -> getStackAlign (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo (


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT> && (


<s> SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL

) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( computeDataLayout ( Subtarget ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> static void CalculateTailCallArgDest ( SelectionDAG & DAG , MachineFunction & MF , bool is<ISA_LIT>64 , SDValue Arg , int SPDiff , unsigned ArgOffset , SmallVectorImpl < TailCallArgumentInfo > & TailCallArguments ) { int Offset = ArgOffset + SPDiff ; uint32_t OpSize = ( Arg . getValueType ( ) . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( OpSize , Offset , true ) ; EVT VT = is<ISA_LIT>64


<s> unsigned getNumFixupKinds ( ) const override { return <NUM_LIT>


<s> bool nds32_n13_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; return n13_consumed_by_e2_dep_p ( consumer , def_reg


<s> if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P


<s> SmallVector < MachineOperand * , <NUM_LIT> > Uses ; MachineInstr & MI = * I ; for ( auto & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) - <STR_LIT> ; if ( Reg >= <NUM_LIT> ) continue ; if ( MO . isDef ( ) ) { Defs . set ( Reg ) ; if ( ! LPR . contains ( MO . getReg ( ) ) ) MO . setIsDead ( ) ; } else Uses . push_back ( & MO ) ; } for ( auto * MO : Uses ) if ( Defs . test ( getFPReg ( * MO ) ) || ! LPR . contains ( MO -> getReg ( ) ) ) MO -> setIsKill ( ) ; LPR . stepBackward


<s> static SDValue getOnesVector ( EVT VT , SelectionDAG & DAG , const SDLoc & dl ) { assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; APInt Ones = APInt :: getAllOnesValue (


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: arm , true > X ( getThe<ISA_LIT>LETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT


<s> assert ( ( ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT>

) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ;


<s> else { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_LOAD || type

== TYPE_STORE ) mips_last_74k_agen_insn = type ;


<s> return ; } if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; return ; } if ( Disp . isImm ( ) ) { if ( ! HasEVEX && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } int CDisp8 = <NUM_LIT> ; if ( HasEVEX && isCDisp8 ( TSFlags , Disp . getImm ( ) , CDisp8 ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups , CDisp8 - Disp . getImm ( ) ) ; return ; } } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , MCFixupKind ( <STR_LIT> ) , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; int CDisp8 = <NUM_LIT> ; int ImmOffset = <NUM_LIT> ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } else if ( ! HasEVEX && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp8 = true ; } else if ( HasEVEX && isCDisp8 ( TSFlags , Disp . getImm ( ) , CDisp8 ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; assert ( MO . getReg ( ) > <STR_LIT> && MO . getReg ( ) < <STR_LIT> && <STR_LIT> ) ; OutMO = MCOperand :: createReg ( MO . getReg ( ) ) ; return true ; case MachineOperand :: MO_Immediate : OutMO = MCOperand :: createImm ( MO . getImm ( ) ) ; return true ; case MachineOperand :: MO_MachineBasicBlock : OutMO = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; return true ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_BlockAddress : OutMO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_MCSymbol : OutMO = GetSymbolRef ( MO , MO . getMCSymbol ( ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_RegisterMask


<s> bool isJITCodeModel ( ) const { return


<s> return ( __m128 ) __builtin_ia32_vfmaddss3 ( ( __v4sf ) __A , -


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode


<s> DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; const TargetRegisterClass * RC = is64bit ? & <STR_LIT> : & <STR_LIT> ; unsigned PtrReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Shift1Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Incr2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg (


<s> emitFPCompare ( FCmp . getOperand ( <NUM_LIT> ) . getReg ( ) , FCmp . getOperand ( <NUM_LIT> ) . getReg ( ) , MIB , Pred ) ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( static_cast < CmpInst :: Predicate > ( Pred ) , CC1 , CC2 ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm


<s> return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt =


<s> return new <ISA_LIT>CodeEmitter ( TM ,


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return


<s> if ( Op . isImm ( ) ) O << formatImm ( Op . getImm ( ) ) ; else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << formatHex ( ( uint64_t ) Address ) ; } else { O << * Op . getExpr


<s> assert ( Kind == k_ShiftExtend && <STR_LIT> ) ; return ShiftExtend .


<s> aarch64_init_simd_builtin_types ( ) ; aarch64_init_simd_builtin_scalar_types ( ) ; tree lane_check_fpr = build_function_type_list ( void_type_node , size_type_node , size_type_node , intSI_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , AARCH64_SIMD_BUILTIN_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_simd_builtin_data ) ; i ++ , fcode ++ ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { <NUM_LIT> } ; aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ i ] ; char namebuf [ <NUM_LIT> ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers


<s> static DecodeStatus DecodeHWRegs64RegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Address , const void * Decoder ) {


<s> case E_QImode : gen = gen_aarch64_atomic_casqi ; break ; case E_HImode : gen = gen_aarch64_atomic_cashi ; break ; case E_SImode : gen = gen_aarch64_atomic_cassi ; break ; case E_DImode : gen = gen_aarch64_atomic_casdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( rval , expected ) ) ; emit_insn ( gen ( rval , mem


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo &


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv8qi (


<s> DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ; concatSubVector ( Vec , InVec , VecElems , Builder ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , UndefValue :: get ( Vec [ <NUM_LIT> ] -> getType ( ) ) , VPShuf ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) TempVector [ i ] = Builder . CreateShuffleVector ( Vec [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , Vec [ i ] , VPAlign [ <NUM_LIT> ] ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( TempVector [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , TempVector [ i ] , VPAlign [ <NUM_LIT> ] ) ; Value * TempVec = Builder . CreateShuffleVector ( Vec [ <NUM_LIT> ] , UndefValue :: get ( Vec [ <NUM_LIT> ] -> getType ( ) ) , VPAlign3 ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ <NUM_LIT> ] , UndefValue :: get (

Vec [ <NUM_LIT> ] -> getType ( ) ) , VPAlign2 ) ;


<s> mips_prepare_builtin_arg ( & ops [ <NUM_LIT> ] , exp , <NUM_LIT> ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , const0_rtx ) ; if ( GET_CODE ( ops [ <NUM_LIT> ] . value ) != REG ) ops [ <NUM_LIT> ] . value = force_reg ( ops [ <NUM_LIT> ] . mode , ops [ <NUM_LIT> ] . value ) ; if ( ( cbranch = maybe_gen_insn ( icode , <NUM_LIT> , ops ) ) == NULL_RTX ) error ( <STR_LIT> ) ; cmp_result = gen_reg_rtx ( SImode ) ; mips_emit_move ( cmp_result , const0_rtx ) ; emit_jump_insn ( cbranch ) ; emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label (


<s> unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS .


<s> return ( int32x4_t ) __builtin_neon_vcvts_nv4sf (


<s> uint64_t NumBytes = StackSize - TFI . getOffsetOfLocalArea ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitSPUpdate ( MBB , MBBI , - ( int64_t ) NumBytes , TII ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin (


<s> return __builtin_mve_vshlq_m_sv4si ( __arm_vuninitializedq_s32 ( ) ,


<s> rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER


<s> SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , RegSeq -> getValueType ( <NUM_LIT> ) , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Narrow ? NarrowVector ( SuperReg , * CurDAG ) : SuperReg ) ; } else { EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static const unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i


<s> uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset )


<s> void WinEHStatePass :: insertStateNumberStore ( Value * ParentRegNode , Instruction * IP , int State ) { IRBuilder < > Builder ( IP )


<s> SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getIntPtrConstant ( PointerSize ) ) ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , getPointerTy ( ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , RSFIN , FIN , MachinePointerInfo ( SV , <NUM_LIT> + PointerSize ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOps [ <NUM_LIT> ] ,


<s> DecodeGPR32RegisterClass ( Inst , Rd , Address , Decoder ) ; if ( Opc == BFM ) DecodeGPR32RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rn , Address , Decoder ) ; } assert ( ! ( ImmS == <NUM_LIT> && ! SF && Opc != BFM ) && <STR_LIT> ) ; assert ( ! ( ImmS == <NUM_LIT> && SF && Opc != BFM ) && <STR_LIT> ) ; if ( Opc == SBFM && ImmR == <NUM_LIT> ) { assert ( ( ImmS != <NUM_LIT> && ImmS != <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( ImmS != <NUM_LIT> || SF == <NUM_LIT> ) && <STR_LIT> ) ; } else if ( Opc == UBFM && ImmR == <NUM_LIT> ) { assert ( ( SF != <NUM_LIT> || ( ImmS != <NUM_LIT> && ImmS != <NUM_LIT> ) ) && <STR_LIT> ) ; } if ( Opc == UBFM ) { if ( SF && ( ImmS + <NUM_LIT> ) % <NUM_LIT> == ImmR ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - ImmS ) ) ; return MCDisassembler :: Success ; } else if ( ! SF && ( ImmS + <NUM_LIT> ) % <NUM_LIT> == ImmR ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - ImmS ) ) ; return MCDisassembler :: Success ; } } unsigned ExtractOp , InsertOp ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case SBFM : ExtractOp = SF ? <STR_LIT> : <STR_LIT> ; InsertOp = SF ? <STR_LIT> : <STR_LIT> ; break ; case BFM : ExtractOp = SF ? <STR_LIT> : <STR_LIT> ; InsertOp = SF ? <STR_LIT> : <STR_LIT> ; break ; case UBFM : ExtractOp = SF ? <STR_LIT> : <STR_LIT> ; InsertOp = SF ? <STR_LIT> :


<s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT>


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT>


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; return false ; } if ( RegNo == <NUM_LIT> && Tok . getString ( ) . size ( ) == <NUM_LIT> && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { switch ( Tok . getString ( ) [ <NUM_LIT> ] ) { case '0' : RegNo = <STR_LIT> ; break ; case '1' : RegNo = <STR_LIT> ; break ; case '2' : RegNo = <STR_LIT> ; break ; case '3' : RegNo = <STR_LIT> ; break ; case '4' : RegNo = <STR_LIT> ; break ; case '5' : RegNo = <STR_LIT> ; break ; case '6' : RegNo = <STR_LIT> ; break ; case '7' : RegNo = <STR_LIT> ; break ; } if ( RegNo != <NUM_LIT> ) { EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; return false ; } } if ( RegNo ==


<s> void <ISA_LIT>SEInstrInfo :: expandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , bool FP64 ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg (


<s> if ( <STR_LIT> . contains ( Reg ) ) { MachineLocation DstML0 ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation DstML1 ( MachineLocation :: VirtualFP , Offset + <NUM_LIT> ) ; MachineLocation SrcML0 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; MachineLocation SrcML1 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; if ( ! STI . isLittle ( ) ) std :: swap ( SrcML0 , SrcML1 ) ; Moves . push_back ( MachineMove ( CSLabel , DstML0 , SrcML0 ) ) ; Moves . push_back ( MachineMove ( CSLabel , DstML1 , SrcML1 ) ) ; } else { DstML = MachineLocation ( MachineLocation :: VirtualFP , Offset ) ; SrcML = MachineLocation ( Reg ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; } } } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { if ( ! MBB . isLiveIn ( ehDataReg ( I ) ) ) MBB . addLiveIn ( ehDataReg ( I ) ) ; TII . storeRegToStackSlot ( MBB , MBBI , ehDataReg ( I ) , false , <ISA_LIT>FI -> getEhDataRegFI ( I ) , RC , RegInfo ) ; } MCSymbol * CSLabel2 = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel2 ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( <ISA_LIT>FI -> getEhDataRegFI ( I ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , Offset ) ; SrcML = MachineLocation ( ehDataReg ( I ) ) ; Moves . push_back ( MachineMove ( CSLabel2 , DstML , SrcML ) ) ; } } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( ADDu ) , FP ) . addReg ( SP ) . addReg ( ZERO ) ; MCSymbol * SetFPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( SetFPLabel ) ; DstML = MachineLocation ( FP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP ) ; Moves . push_back ( MachineMove ( SetFPLabel , DstML ,


<s> unsigned try = <NUM_LIT> , used ; int jump_left = flag_expensive_optimizations + <NUM_LIT> ; for ( scan = jump ; ( scan = PREV_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( INSN_DELETED_P ( scan ) ) continue ; code = GET_CODE ( scan ) ; if ( code == CODE_LABEL || code == JUMP_INSN ) break ; if ( code == INSN && GET_CODE ( PATTERN ( scan ) ) != USE && GET_CODE ( PATTERN ( scan ) ) != CLOBBER && get_attr_in_delay_slot ( scan ) == IN_DELAY_SLOT_YES ) { try &= ~ regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; break ; } } for ( used = dead = <NUM_LIT> , scan = JUMP_LABEL ( jump ) ; ( scan = NEXT_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( INSN_DELETED_P ( scan ) ) continue ; code = GET_CODE ( scan ) ; if ( INSN_P ( scan ) ) { used |= regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; if ( code == CALL_INSN ) used |= regs_used ( CALL_INSN_FUNCTION_USAGE ( scan ) , <NUM_LIT> ) ; dead |= ( used >> <NUM_LIT> )


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t ArgumentPopSize = <NUM_LIT> ; if ( IsTailCallReturn ) { MachineOperand & StackAdjust = MBBI ->


<s> MachineBasicBlock * UserBB = U . MI -> getParent ( ) ; unsigned MinNoSplitDisp = BBInfo [ UserBB -> getNumber ( ) ] . postOffset ( getCPELogAlign ( U . CPEMI ) ) ; if ( CloserWater && MinNoSplitDisp > U . getMaxDisp ( ) / <NUM_LIT> ) return false ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI -> getParent ( ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * WaterBB ) << <STR_LIT> << Growth << '\n' ) ; if ( CloserWater && WaterBB == U . MI -> getParent ( ) ) return true ; if ( ! CloserWater && BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B


<s> RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode >


<s> unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( <STR_LIT>


<s> int <ISA_LIT>ConstantIslands :: findInRangeCPEntry ( CPUser & U , unsigned UserOffset ) { MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getMaxDisp ( ) , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [


<s> unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ idx ] . getFrameIdx ( ) << <STR_LIT> << CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ; const int Offset = ( i == <NUM_LIT> ) ? - Count :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = getFMA3Group ( MI . getOpcode ( ) , MI . getDesc ( ) . TSFlags ) ; if ( FMA3Group ) return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , FMA3Group -> isIntrinsic ( ) ) ; if ( <STR_LIT> ( Desc . TSFlags ) ) { unsigned CommutableOpIdx1 = Desc . getNumDefs ( ) + <NUM_LIT> ; unsigned CommutableOpIdx2 = Desc . getNumDefs ( ) + <NUM_LIT> ; if ( ( MI . getDesc ( ) . getOperandConstraint ( Desc . getNumDefs ( ) , MCOI :: TIED_TO ) != -


<s> if ( ( index = do_reorder_for_imul ( ready , n_ready ) ) >= <NUM_LIT> ) { if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , INSN_UID ( ready [ index ] ) ) ; insn = ready [ index ] ; for ( i = index ; i < n_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ n_ready - <NUM_LIT> ] = insn ; return issue_rate ; } if ( clock_var != <NUM_LIT> && ! sel_sched_p ( ) && swap_top_of_ready_list ( ready , n_ready ) ) { if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , INSN_UID ( ready [ n_ready - <NUM_LIT> ] ) , INSN_UID ( ready [ n_ready - <NUM_LIT> ] ) ) ; insn = ready [ n_ready - <NUM_LIT> ] ; ready [ n_ready - <NUM_LIT> ] = ready [ n_ready - <NUM_LIT> ] ; ready [ n_ready - <NUM_LIT> ] =


<s> } func_type = arm_current_func_type ( ) ; if ( ! IS_VOLATILE ( func_type ) && TARGET_VFP_BASE ) saved += arm_get_vfp_saved_size ( ) ; if ( TARGET_HAVE_FPCXT_CMSE && IS_CMSE_ENTRY ( func_type ) ) saved += <NUM_LIT> ; } else { offsets -> saved_regs_mask = thumb1_compute_save_core_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * <NUM_LIT> ; saved = core_saved ; if ( TARGET_BACKTRACE ) saved += <NUM_LIT> ; } offsets -> saved_regs = offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + saved ; offsets -> soft_frame = offsets -> saved_regs + CALLER_INTERWORKING_SLOT_SIZE ; if ( crtl -> is_leaf && frame_size == <NUM_LIT> && ! cfun -> calls_alloca ) { offsets -> outgoing_args = offsets -> soft_frame ; offsets -> locals_base = offsets -> soft_frame ; return ; } if ( ARM_DOUBLEWORD_ALIGN && ( offsets -> soft_frame & <NUM_LIT> ) ) { offsets -> soft_frame += <NUM_LIT> ; if ( frame_size + crtl -> outgoing_args_size == <NUM_LIT> ) { int reg = - <NUM_LIT> ; bool prefer_callee_reg_p = false ; if ( ! any_sibcall_could_use_r3 ( ) && arm_size_return_regs ( ) <= <NUM_LIT> && ( offsets -> saved_regs_mask & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> && ( TARGET_THUMB2 || ! ( TARGET_LDRD && current_tune -> prefer_ldrd_strd ) ) ) { reg = <NUM_LIT> ; if ( ! TARGET_THUMB2 ) prefer_callee_reg_p


<s> if ( I -> mayStore ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) { DebugLoc DL3 = MBB -> findDebugLoc ( I ) ; int storeOpcode = I -> getOpcode ( ) ; int loadOpcode = <NUM_LIT> ; int cmpOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } default : { I -> dump ( ) ; errs ( ) << <STR_LIT> ; check = false ; } } if ( check ) { assert ( loadOpcode != <NUM_LIT> ) ; assert ( cmpOpcode != <NUM_LIT> ) ; MachineInstr * MIload = BuildMI ( MF , DL3 , TII -> get ( loadOpcode ) ) ; MIload -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { MIload -> addOperand ( MF , I -> getOperand ( opcount ) ) ; } MIload -> getOperand ( <NUM_LIT> ) . setReg


<s> TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; PCSymbol = <STR_LIT> ; SupportsDebugInformation = true ; DwarfUsesInlineInfoSection = true ; ExceptionsType = ExceptionHandling :: Dwarf ; AbsoluteEHSectionOffsets =


<s> case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType


<s> DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; BuildMI ( MBB , I , dl , Mfc1Tdd


<s> bool isImm1_8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE


<s> Streamer . SwitchSection ( AttributeSection ) ; Streamer . emitInt8 ( ELFAttrs :: Format_Version ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ; Streamer . emitBytes ( CurrentVendor ) ; Streamer . emitInt8 ( <NUM_LIT> ) ; Streamer . emitInt8 ( ELFAttrs :: File ) ; Streamer . emitInt32 ( TagHeaderSize + ContentsSize ) ; for ( AttributeItem item : Contents ) { Streamer . emitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeType :: Numeric : Streamer . emitULEB128IntValue ( item


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> )

, DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; NumElts = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Op0 = Op .


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeFP ( const ConstantFP * CFP , MVT VT ) { const APFloat Val = CFP -> getValueAPF ( ) ; bool is64bit = VT == <STR_LIT> ; if ( TLI . isFPImmLegal ( Val , VT ) ) { int Imm ; unsigned Opc ; if ( is64bit ) { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } else { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } Register DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP )


<s> if ( ( RegNo & <NUM_LIT> ) || RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBinaryData ( <STR_LIT> ) ; unsigned DestRegs [ ] = { <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false } ; unsigned SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = Op -> getReg ( ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return false


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU ) { assert ( TheTriple . isOSBinFormatELF


<s> if ( VT . getSizeInBits ( ) >= <NUM_LIT> ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForSize ( ) ; if ( ConstSplatVal && ( Subtarget . hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget . hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; if ( ! IsLoad && Subtarget . hasInt256 ( ) && ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( ! IsLoad ) return SDValue ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( Subtarget . hasVLX ( ) && ScalarSize

== <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ;


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC != CallingConv :: C && CC != CallingConv :: Fast && CC != CallingConv :: <ISA_LIT>_FastCall ) return false ; if ( Subtarget -> isTargetWin64 ( ) ) return false ; if ( FuncInfo . MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) != <NUM_LIT> ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) . getRetAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt (


<s> bool ret ; if ( ! TARGET_QUAD_MEMORY ) ret = false ; else if ( REG_P ( op0 ) && MEM_P ( op1 ) ) ret = ( quad_int_reg_operand ( op0 , GET_MODE ( op0 ) ) && quad_memory_operand ( op1 , GET_MODE ( op1 ) ) && ! reg_overlap_mentioned_p ( op0 , op1 ) ) ; else if ( MEM_P ( op0 ) && REG_P ( op1 ) ) ret = ( quad_memory_operand ( op0 , GET_MODE ( op0 ) ) && quad_int_reg_operand ( op1 , GET_MODE ( op1 ) ) ) ; else ret =


<s> else I = SetRegister ( I , & TLSBaseAddrReg ) ; Changed = true ; break ; default : break ; } } for ( auto I = Node -> begin ( ) , E = Node -> end ( ) ; I != E ; ++ I ) Changed |= VisitNode ( * I , TLSBaseAddrReg ) ; return Changed


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerNaClTpTlsOffset ( Op , DAG ) ; case <STR_LIT> : return LowerNaClTpTdbOffset ( Op , DAG ) ; case <STR_LIT> : return LowerNaClTargetArch ( Op , DAG


<s> if ( Val != <NUM_LIT> ) return false ; } bool HasHi = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val != <NUM_LIT> )


<s> if ( VT . isScalableVector ( ) ) return SDValue ( ) ; if ( ! InVT . isVector ( ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst ) return SDValue ( ) ; unsigned Val = Cst ->


<s> if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitCmp ( CondReg , CI ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addMBB ( TBB ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } return


<s> void <ISA_LIT>BranchFixup :: verify ( ) { for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , E = MF -> end ( ) ; MBBI != E ; ++ MBBI


<s> edge e ; if ( ! crtl -> tail_call_emit ) return false ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) if ( e -> flags & EDGE_SIBCALL ) { rtx_insn * call = BB_END ( e -> src ) ; if ( ! CALL_P ( call ) ) call = prev_nonnote_nondebug_insn ( call ) ; gcc_assert ( CALL_P ( call ) && SIBLING_CALL_P ( call ) ) ; if ( find_regno_fusage ( call , USE , <NUM_LIT> ) || is_indirect_tailcall_p ( call ) ) return true ; } return false


<s> assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT> ) ; return


<s> Inst . addOperand ( MCOperand :: createImm ( Value == <NUM_LIT> ? <NUM_LIT> : Value ) ) ; return MCDisassembler ::


<s> object :: mach :: CPUSubtype<ISA_LIT> CS = StringSwitch < object :: mach :: CPUSubtype<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7F ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , object :: mach :: CS<ISA_LIT>_V7S ) . Default ( object :: mach :: CS<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ; } if ( TheTriple . isOSWindows ( )


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) . getVectorElementType


<s> encoding = ( get<ISA_LIT>RegisterNumbering ( op1 . getReg ( ) ) << <NUM_LIT> ) ; MCOperand op2 = MI . getOperand ( <NUM_LIT> ) ; assert ( op2 . isImm (


<s> MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >=


<s> assert ( ( CurrentPredicates . size ( ) || MI -> getParent ( ) -> isLiveIn ( <STR_LIT> ) ) && <STR_LIT> ) ; Blocks . emplace_back ( MI ) ; PredicatedInsts . emplace ( MI , std :: make_unique < PredicatedMI >


<s> gcc_assert ( GET_CODE ( unspec_rtx ) == UNSPEC ) ; operand_ra = XVECEXP ( unspec_rtx , <NUM_LIT> , <NUM_LIT> ) ; operand_rb = XVECEXP ( unspec_rtx , <NUM_LIT> , <NUM_LIT> ) ; if ( rtx_equal_p ( def_reg , operand_ra ) || rtx_equal_p ( def_reg , operand_rb ) ) return true ; return false


<s> void startVisit ( const MachineInstr * MI ) { Types . try_emplace ( MI , InstType :: NotDetermined ) ; WaitingQueues . try_emplace


<s> Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; auto * Ty = cast < VectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( regno ) ) return false ; return


<s> return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , Flavour , Flavour ) ; return


<s> MachineInstr * getVPST ( ) const { return VPST ->


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) &&


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa . mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset


<s> tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; tree arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; rtx op2 = expand_expr ( arg2 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vsldoi_v4sf || icode == CODE_FOR_altivec_vsldoi_v4si || icode == CODE_FOR_altivec_vsldoi_v8hi || icode == CODE_FOR_altivec_vsldoi_v16qi ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 ,


<s> return ( ( vec_int4 ) ( si_andi ( ( qword


<s> RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addLeaAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI .


<s> llvm :: cast < <ISA_LIT>GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin ( ) ) ) . setValue


<s> Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 , TheTriple ) ; else MAI = new <ISA_LIT>LinuxMCAsmInfo ( is<ISA_LIT>64 ,


<s> unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Idx = <NUM_LIT> ; const TargetRegisterClass * RC32 = TLI . getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; bool is32Bit = TLI . getValueType ( I -> getType ( ) ) == <STR_LIT> ; const TargetRegisterClass * RC = is32Bit ? RC32 : RC64 ; unsigned SrcReg = is32Bit ? GPR32ArgRegs [ Idx ] : GPR64ArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; UpdateValueMap ( I , ResultReg


<s> return ( __mmask16 ) __builtin_ia32_fpclassps512_mask ( ( __v16sf ) __A ,


<s> if ( ! LoadedType . isSimple ( ) || ( ! LoadedType . isInteger ( ) && ! LoadedType . isFloatingPoint ( ) ) ) return false ; RequiredAligment = <NUM_LIT> ; unsigned NumBits = LoadedType . getSizeInBits ( ) ; return NumBits == <NUM_LIT> || NumBits


<s> unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; shift_mask <<= INTVAL (


<s> Imm = MI -> getOperand ( Op ) . getImm ( ) ; return true


<s> rtx temp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp4 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ <NUM_LIT> ) != <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( VOIDmode , temp3 , gen_safe_OR64 ( temp2 , ( low_bits & <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( <NUM_LIT> - <NUM_LIT> ) ) & <NUM_LIT> ) ; rtx low2 = GEN_INT ( ( low_bits >> ( <NUM_LIT> - <NUM_LIT>


<s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( Operands ) != MatchOperand_NoMatch ) return false ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E , * this ) ) ; return false ; } default : { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression (


<s> State . AllocateReg ( <NUM_LIT> ) ; return true ; } else if ( ValNo == <NUM_LIT> && State . isAllocated ( <NUM_LIT> ) ) { assert ( ValVT == <STR_LIT> && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , <NUM_LIT> , LocVT , LocInfo ) ) ; return true


<s> if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) x = XEXP ( x , <NUM_LIT> ) ; if ( MEM_P ( x ) )


<s> for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , U . NegOk ) ) { DEBUG ( errs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs


<s> { <STR_LIT> , AARCH64_LS64_BUILTIN_LD64B , build_function_type_list ( ls64_arm_data_t , const_ptr_type_node , NULL_TREE ) } , { <STR_LIT> , AARCH64_LS64_BUILTIN_ST64B , build_function_type_list ( void_type_node , ptr_type_node , ls64_arm_data_t , NULL_TREE ) } , { <STR_LIT> , AARCH64_LS64_BUILTIN_ST64BV , build_function_type_list ( uint64_type_node , ptr_type_node , ls64_arm_data_t , NULL_TREE ) } , { <STR_LIT> , AARCH64_LS64_BUILTIN_ST64BV0 , build_function_type_list ( uint64_type_node , ptr_type_node , ls64_arm_data_t , NULL_TREE ) } , } ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( data ) ; ++ i ) aarch64_builtin_decls [ data [ i ] . code ] = aarch64_general_add_builtin (

data [ i ] . name , data [ i ] . type , data [ i ] . code ) ;


<s> ( * lang_hooks . types . register_builtin_type ) ( intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( aarch64_fp16_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type


<s> Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ; SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue CosVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDVTList Tys = DAG . getVTList ( ArgVT , ArgVT ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> Inst . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> bool isCheri64 ( ) const { return IsCheri64


<s> bool IsVSSReg ( unsigned Reg , MachineRegisterInfo & MRI


<s> return __builtin_mve_vsubq_fv4sf ( __a ,


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return getSETCC ( CCode , Op0 . getOperand ( <NUM_LIT> ) , dl , DAG ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; <STR_LIT> <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , IsFP , Op0


<s> case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , <STR_LIT> ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , <STR_LIT> ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , <STR_LIT> ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction


<s> else { HOST_WIDE_INT rounded_size ; rtx r13 = LARCH_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = LARCH_PROLOGUE_TEMP2 ( Pmode ) ; rtx r14 = LARCH_PROLOGUE_TEMP3 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; if ( first != <NUM_LIT> ) { emit_move_insn ( r14 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( r13 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_move_insn ( r13 , stack_pointer_rtx ) ; emit_move_insn ( r14 , GEN_INT ( PROBE_INTERVAL ) ) ; if ( rounded_size == <NUM_LIT> ) emit_move_insn ( r12 , r13 ) ; else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r13 , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , r13 , r13 , r12 , r14 ) ) ; } if ( size != rounded_size ) { if ( TARGET_64BIT ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; else { HOST_WIDE_INT i ; for ( i = <NUM_LIT> ; i < ( size - rounded_size ) ; i += <NUM_LIT> ) { emit_stack_probe ( plus_constant ( Pmode , r12 , - i ) ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r12 , - <NUM_LIT> ) ) ) ; } rtx r1 = plus_constant ( Pmode , r12 , - ( size - rounded_size


<s> static void rs6000_emit_msub ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx dst ; if ( optab_handler ( fms_optab , mode ) != CODE_FOR_nothing ) dst = expand_ternary_op ( mode , fms_optab , m1 , m2 , a , target , <NUM_LIT> ) ; else { a = expand_unop ( mode , neg_optab , a , NULL_RTX ,


<s> return needsCmpXchgNb ( PTy -> getElementType ( ) )

? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isRegMask ( ) ) { bool ClobbersFP0 = Op . clobbersPhysReg ( <STR_LIT> ) ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) assert ( Op . clobbersPhysReg ( <STR_LIT> + i ) == ClobbersFP0 && <STR_LIT> ) ; if ( ClobbersFP0 ) ClobbersFPStack = true ; } if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isImplicit ( ) && <STR_LIT> ) ; if ( Op . isDef ( ) ) STReturns |= <NUM_LIT> << getFPReg ( Op ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } assert ( ( ClobbersFPStack || STReturns == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! ClobbersFPStack ) return ; unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) &&


<s> if ( ST -> isCortexA15 ( ) || ST -> isSwift ( ) )


<s> bool <ISA_LIT>FastISel :: TargetSelectInstruction ( const Instruction * I ) { return I &&


<s> unsigned long long res ; __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( k ) ) ; return res


<s> unsigned i ; if ( ! TARGET_AVX || d -> vmode != V8SFmode || ! d -> one_operand_p ) return false ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( i < <NUM_LIT> ? e >= <NUM_LIT> : e < <NUM_LIT> ) return false ; } if ( d -> testing_p ) return true ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e >= <NUM_LIT> + <NUM_LIT> ) e -= <NUM_LIT> ; else if ( e >= <NUM_LIT> ) e -= <NUM_LIT> ; rperm [ i ] = GEN_INT


<s> void addAccessRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( Kind == KindAccessReg && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( AccessReg


<s> return SYSmvalue ; } int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasThumb2DSP ( ) ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasThumb2DSP ( ) && ( Mask &


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( TT . isOSDarwin ( ) ) return CSR_<ISA_LIT>_TLS_Darwin_RegMask ; assert ( TT . isOSBinFormatELF (


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT ) const { using namespace <ISA_LIT> ; switch ( RC . getID ( ) ) { case GPRRegClassID : case GPRwithAPSRRegClassID : case GPRnoipRegClassID : case GPRnopcRegClassID : case GPRnoip_and_GPRnopcRegClassID : case rGPRRegClassID : case GPRspRegClassID : case GPRnoip_and_tcGPRRegClassID : case tcGPRRegClassID : case


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg , Mask ) ; Register ResultReg = fastEmitInst_rr ( Opc , RC , Op0Reg , Op1Reg ) ; if ( NeedTrunc ) ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ; return


<s> unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ; OpIdx +=


<s> if ( AssemblerDialect == AD_ATT ) return MCAsmInfo :: isAcceptableChar


<s> if ( Reg == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , RegKind :: Scalar , S , getLoc ( ) , getContext


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) . isVector ( ) ) return lowerUINT_TO_FP_vec ( Op , DAG ) ; if ( DAG . SignBitIsZero ( N0 ) ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , N0 ) ; MVT SrcVT = N0 . getSimpleValueType ( ) ; MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG ) ; if ( Subtarget -> is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType


<s> if ( RegVT . getVectorElementType ( ) == <STR_LIT> ) { assert ( EVT ( RegVT ) == Ld -> getMemoryVT ( ) && <STR_LIT> ) ; assert ( RegVT . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; SDValue NewLd = DAG . getLoad ( <STR_LIT> , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; assert ( NewLd -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewLd ) ; Val = DAG . getNode ( <STR_LIT> , dl , RegVT , DAG . getBitcast ( <STR_LIT> , Val ) , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> return Kind == k_VectorIndex && VectorIndex .


<s> if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = INTVAL ( XEXP ( shift , <NUM_LIT> ) ) ; if ( sh < <NUM_LIT> || sh >= n ) return false ; rtx_code code = GET_CODE ( shift ) ; if ( sh == <NUM_LIT> ) code = ROTATE ; if ( code == ROTATE && sh >= <NUM_LIT> && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= <NUM_LIT> && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < <NUM_LIT> && ne < <NUM_LIT> && sh < <NUM_LIT> ) ; if ( ne > nb ) return false ; if ( code == ASHIFT && ne


<s> uint64_t StartSrcReg = forceReg ( MI , SrcBase , TII ) ; uint64_t StartDestReg = ( HaveSingleBase ? StartSrcReg : forceReg ( MI , DestBase , TII ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t ThisSrcReg = MRI . createVirtualRegister ( RC ) ; uint64_t ThisDestReg = ( HaveSingleBase ? ThisSrcReg : MRI . createVirtualRegister ( RC ) ) ; uint64_t NextSrcReg = MRI . createVirtualRegister ( RC ) ; uint64_t NextDestReg = ( HaveSingleBase ? NextSrcReg : MRI . createVirtualRegister ( RC ) ) ; RC = & <STR_LIT> ; uint64_t ThisCountReg = MRI . createVirtualRegister ( RC ) ; uint64_t NextCountReg = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * NextMBB = ( EndMBB ? emitBlockAfter ( LoopMBB ) : LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisDestReg ) . addReg ( StartDestReg ) . addMBB ( StartMBB ) . addReg ( NextDestReg ) . addMBB ( NextMBB ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisSrcReg ) . addReg ( StartSrcReg ) . addMBB ( StartMBB ) . addReg ( NextSrcReg ) . addMBB ( NextMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisCountReg ) . addReg ( StartCountReg ) . addMBB ( StartMBB ) . addReg ( NextCountReg ) . addMBB ( NextMBB ) ; if ( Opcode == <STR_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( ThisDestReg ) . addImm ( DestDisp + <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( ThisDestReg ) . addImm ( DestDisp ) . addImm ( <NUM_LIT> ) . addReg ( ThisSrcReg ) . addImm ( SrcDisp ) ; if ( EndMBB ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; MBB -> addSuccessor ( NextMBB ) ; } MBB = NextMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextDestReg ) . addReg (

ThisDestReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> return ( unaligned_access ? ( align >= BITS_PER_WORD && ( offset & <NUM_LIT> ) == <NUM_LIT> ) : (

align >= <NUM_LIT> * BITS_PER_WORD && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> if ( Subtarget -> isFlavorIntel ( ) ) { return new <ISA_LIT>IntelAsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) ,


<s> Mfix * fix ; minipool_fix_head = minipool_fix_tail = NULL ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_nonnote_insn ( insn ) ; insn ; insn = next_nonnote_insn ( insn ) ) { if ( BARRIER_P ( insn ) ) push_csky_minipool_barrier ( insn , address ) ; else if ( INSN_P ( insn ) ) { rtx_jump_table_data * table ; note_csky_invalid_constants ( insn , address , true ) ; address += get_attr_length ( insn ) ; if ( tablejump_p ( insn , NULL , & table ) ) { address += get_csky_jump_table_size ( table ) ; insn = table ; } } } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; Mnode * mp ; bool has_pending_const = false ; for ( mp = minipool_vector_head ; mp ; mp = mp -> next ) if ( mp -> refcount > <NUM_LIT> ) { has_pending_const = true ; break ; } if ( has_pending_const == false ) { while ( fix && BARRIER_P ( fix -> insn ) ) fix = fix -> next ; if ( fix == NULL ) break ; } last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( BARRIER_P ( ftmp -> insn ) ) { if ( minipool_vector_head && ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else { ftmp -> minipool = add_csky_minipool_forward_ref ( ftmp ) ; if ( ftmp -> minipool == NULL ) break ; } last_added_fix = ftmp


<s> assert ( ( Idx + Len ) <= NumElts && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ShuffleMask . push_back ( i ) ; for ( unsigned i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask [


<s> return <NUM_LIT> - MI . getOperand ( Op )