<s> if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SFmode ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false


<s> return ( __m256i ) __builtin_ia32_expandloadhi256_mask ( ( const __v16hi * ) __C ,


<s> return ( int64x1_t ) { vcvtmd_s64_f64 (


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Disp , SDValue & Index ) { if ( <STR_LIT> ( N . getNode ( ) ) && IsLegalToFold ( N , P , P , OptLevel ) ) return SelectAddrRRI20 ( P , N . getOperand ( <NUM_LIT> ) , Base , Disp , Index ) ; return false


<s> SDValue MinPos = Src ; while ( SrcVT . getSizeInBits ( ) > <NUM_LIT> ) { unsigned NumElts = SrcVT . getVectorNumElements ( ) ; unsigned NumSubElts = NumElts / <NUM_LIT> ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcSVT , NumSubElts ) ; unsigned SubSizeInBits = SrcVT . getSizeInBits ( ) ; SDValue Lo = extractSubVector ( MinPos , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( MinPos , NumSubElts , DAG , DL , SubSizeInBits ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , getZeroVector ( <STR_LIT> , Subtarget , DAG , DL ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos ,


<s> ParseRegister ( unsigned & RegNo , SMLoc & StartLoc


<s> rtx untagged_base = expand_simple_binop ( Pmode , AND , tagged_pointer , tag_mask , target , true , OPTAB_DIRECT ) ; gcc_assert (


<s> int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveReg ( Reg , Offset ) ; return false


<s> machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; rtx op0 = force_reg ( d -> mode , expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ) ; rtx op1 = force_reg ( d -> mode , expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ) ; rtx op2 = force_reg ( quadmode , expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ) ; tree tmp = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx lane_idx = expand_expr ( tmp , NULL_RTX , VOIDmode , EXPAND_INITIALIZER ) ; if ( ! CONST_INT_P ( lane_idx ) ) { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> , <NUM_LIT> ) ; return const0_rtx ; } int nunits = GET_MODE_NUNITS ( quadmode ) . to_constant ( ) ; aarch64_simd_lane_bounds ( lane_idx , <NUM_LIT> , nunits / <NUM_LIT> , exp ) ; int lane = INTVAL ( lane_idx ) ; if ( lane < nunits / <NUM_LIT> ) op2 = simplify_gen_subreg ( d -> mode , op2 , quadmode , subreg_lowpart_offset ( d -> mode , quadmode ) ) ; else { rtx temp1 = gen_reg_rtx ( d -> mode ) ; rtx temp2 = gen_reg_rtx ( DImode ) ; temp1 = simplify_gen_subreg ( d -> mode , op2 , quadmode , subreg_lowpart_offset ( d -> mode , quadmode ) ) ; temp1 = simplify_gen_subreg ( V2DImode , temp1 , d -> mode , <NUM_LIT> ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_aarch64_get_lanev2di ( temp2 , temp1 , const0_rtx ) ) ; else emit_insn ( gen_aarch64_get_lanev2di ( temp2 ,


<s> std :: pair < uint8_t , uint8_t > <ISA_LIT>XCOFFObjectWriter :: getRelocTypeAndSignSize ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { const MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; const uint8_t EncodedSignednessIndicator = IsPCRel ? SignBitMask : <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : { const uint8_t SignAndSizeForHalf16 = EncodedSignednessIndicator | <NUM_LIT> ; switch ( Modifier ) { default : report_fatal_error ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return { XCOFF :: RelocationType :: R_TOC , SignAndSizeForHalf16 } ; case MCSymbolRefExpr :: VK_<ISA_LIT>_U : return { XCOFF :: RelocationType :: R_TOCU , SignAndSizeForHalf16 } ; case MCSymbolRefExpr :: VK_<ISA_LIT>_L : return { XCOFF :: RelocationType :: R_TOCL , SignAndSizeForHalf16 } ; } } break ; case <STR_LIT> : case <STR_LIT> : { if ( IsPCRel ) report_fatal_error ( <STR_LIT> ) ; switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! isN64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG ,


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_LOAD_OP ( SDValue Op , SelectionDAG & DAG , unsigned Opcode ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; EVT NarrowVT = Node -> getMemoryVT ( ) ; EVT WideVT = <STR_LIT> ; if ( NarrowVT == WideVT ) return Op ; int64_t BitSize = NarrowVT . getSizeInBits ( ) ; SDValue ChainIn = Node -> getChain ( ) ; SDValue Addr = Node -> getBasePtr ( ) ; SDValue Src2 = Node -> getVal ( ) ; MachineMemOperand * MMO = Node -> getMemOperand ( ) ; SDLoc DL ( Node ) ; EVT PtrVT = Addr . getValueType ( ) ; if ( Opcode == <STR_LIT> ) if ( auto * Const = dyn_cast < ConstantSDNode > ( Src2 ) ) { Opcode = <STR_LIT> ; Src2 = DAG . getConstant ( - Const -> getSExtValue ( ) , Src2 . getValueType ( ) ) ; } SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG .


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF

:: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> Value * <ISA_LIT>TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr ,


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) ; return true ; } if ( ( Subtarget . isABI_FPXX ( ) && ! Subtarget . hasMTHC1 ( ) ) || ( FP64 && ! Subtarget . useOddSPReg ( ) ) ) { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Op1 . getReg ( ) ; unsigned N = Op2 . getImm ( ) ; int64_t Offset = <NUM_LIT> * ( Subtarget . isLittle ( ) ? N : ( <NUM_LIT> - N ) ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = FP64 ? & <STR_LIT> : & <STR_LIT> ; const TargetRegisterClass * RC2 = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC ) ; TII . storeRegToStack ( MBB , I , SrcReg , Op1 . isKill ( ) , FI , RC ,


<s> if ( intrinsic == mep_cmov ) { for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mep_cmov_insns ) ; i ++ ) if ( mep_get_intrinsic_insn ( mep_cmov_insns [ i ]


<s> StringRef CPU , ExtensionString ; std :: tie ( CPU , ExtensionString ) = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) . split ( '+' ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( CurLoc , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , CPU , <STR_LIT> ) ; CurLoc = incrementLoc ( CurLoc , CPU . size ( ) ) ; ExpandCryptoAEK ( llvm :: <STR_LIT> ( CPU ) , RequestedExtensions ) ; for ( auto Name : RequestedExtensions ) { CurLoc = incrementLoc ( CurLoc , <NUM_LIT> ) ; bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } bool FoundExtension = false ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; FeatureBitset ToggleFeatures = EnableFeature ? STI . SetFeatureBitsTransitively ( ~ Features & Extension . Features ) : STI . ToggleFeature ( Features & Extension . Features ) ; setAvailableFeatures ( ComputeAvailableFeatures ( ToggleFeatures ) ) ; FoundExtension = true ; break ; } if ( ! FoundExtension ) Error ( CurLoc


<s> OperandMatchResultTy parseGR64 ( SmallVectorImpl < MCParsedAsmOperand *


<s> SDValue getGatherScatterIndex ( SDValue Op ) { if ( auto * N = dyn_cast < MaskedGatherScatterSDNode > ( Op . getNode ( ) ) ) return N -> getIndex ( ) ; if ( auto * N = dyn_cast < VPGatherScatterSDNode > ( Op . getNode ( ) ) ) return N -> getIndex ( ) ; return SDValue


<s> bool hasFuseLiterals ( ) const { return HasFuseLiterals


<s> if ( UseMI . getOpcode ( ) == TargetOpcode :: COPY ) { COPYUses . push_back ( & UseMI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; UseMI . dump ( ) ; ) ; } } for ( MachineInstr * UseMI : COPYUses ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; UseMI -> dump ( ) ) ; MachineBasicBlock * MBB = UseMI -> getParent ( ) ; auto TargetReg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister ( TargetReg ) ) { if ( ! MRI -> getRegClass ( TargetReg ) -> hasSuperClassEq ( & <STR_LIT> ) ) { errs ( ) << <STR_LIT> ; UseMI -> dump ( ) ; errs ( ) << <STR_LIT> ; GetNullMI . dump ( ) ; errs ( ) << <STR_LIT> << MRI -> getRegClassOrNull ( TargetReg ) -> getID ( ) ; errs ( ) << <STR_LIT> << <STR_LIT> . getID ( ) ; errs ( ) << <STR_LIT> ; } assert ( MRI -> getRegClass ( TargetReg ) -> hasSuperClassEq ( & <STR_LIT> ) ) ; } else { if ( ! <STR_LIT> . contains ( TargetReg ) ) { errs ( ) << <STR_LIT> << ( int ) TargetReg << <STR_LIT> ; errs ( ) << <STR_LIT> ; UseMI -> dump ( ) ; errs ( ) << <STR_LIT> ; UseMI -> dump ( ) ; UseMI -> getParent ( ) -> dump ( ) ; llvm_unreachable ( <STR_LIT>


<s> case NotAtomic : case Unordered : llvm_unreachable ( <STR_LIT> ) ; case Monotonic : case Acquire : return ; case SequentiallyConsistent : if ( ! IsStore ) return ; case


<s> return new <ISA_LIT>ELFObjectWriter ( true , OSType , ELF :: EM_<ISA_LIT>_64 ,


<s> AsmPrinter :: runOnMachineFunction ( MF ) ; return


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; OffBits >>= ShiftAmount


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> isIndirectBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear


<s> return __builtin_mve_vrshlq_sv4si ( __a ,


<s> Res = DAG . getNode ( <STR_LIT> , dl , FullVT , Mask , TransN0 ) ; } } else { SDValue NotV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getNOT ( dl , N1 , <STR_LIT> ) ) ; SDValue Zext = DAG . getNode ( <STR_LIT> , dl , FullVT , NotV ) ; SDValue Mask = DAG . getNOT ( dl , DAG . getNode ( <STR_LIT> , dl , FullVT , Zext , N2 ) , FullVT ) ; Res = DAG . getNode ( <STR_LIT> , dl , FullVT , Mask , TransN0 ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } else { assert ( VT . getVectorElementType ( ) . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; N2 = getTruncateOrZeroExtend ( N2 , DAG , <STR_LIT> ) ; int I16VecNumElts = RegisterWidth / <NUM_LIT> ; MVT I16VecType = <STR_LIT> ( <STR_LIT> , I16VecNumElts ) ; int lowbitsMask = ( <NUM_LIT> << FieldWidth ) - <NUM_LIT> ; SDValue IdxVec = b . UDIV ( N2 , b . Constant ( NumElts / I16VecNumElts , <STR_LIT> ) ) ; SDValue IdxInside = b . UREM ( N2 , b . Constant ( NumElts / I16VecNumElts , <STR_LIT> ) ) ; SDValue TransVal = b . BITCAST ( N0 , I16VecType ) ; SDValue ExtVal = b . EXTRACT_VECTOR_ELT ( TransVal , IdxVec ) ; SDValue NewElt = b . SHL ( b . ZERO_EXTEND ( b . AND ( N1 , b . Constant ( lowbitsMask , <STR_LIT> ) ) , <STR_LIT> ) , b . MUL ( IdxInside , b . Constant ( FieldWidth , <STR_LIT> ) ) ) ; SDValue Mask = b . SHL ( b . Constant ( lowbitsMask , <STR_LIT> ) , b . MUL ( IdxInside , b . Constant ( FieldWidth , <STR_LIT> ) ) ) ; ExtVal = b . OR ( b . AND ( ExtVal , b . NOT ( Mask ) ) , NewElt ) ; MVT IdxValueType = <STR_LIT> ; if ( Subtarget -> is64Bit ( ) ) IdxValueType = <STR_LIT> ; return b . BITCAST ( b . INSERT_VECTOR_ELT ( TransVal , ExtVal , b

. ZERO_EXTEND ( IdxVec , IdxValueType ) ) , VT ) ;


<s> if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } } Relocator :: DWord X = S + A ; X >>= <NUM_LIT> ; if ( helper_check_signed_overflow ( X , <NUM_LIT> ) ) return Relocator :: Overflow ; val = helper_insert_val_thumb_movw_movt_inst ( val , X ) ; * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) = val >> <NUM_LIT> ; * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) = val & <NUM_LIT> ; return Relocator


<s> if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n'


<s> SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ; if ( EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) OpLHS = WidenVector ( OpLHS , DAG ) ; SDValue Lane = DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ; return DAG . getNode ( Opcode , dl , VT , OpLHS , Lane ) ; } case


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return isPALIGNRMask ( M ,

VT , Subtarget -> hasSSSE3 ( ) || Subtarget -> hasAVX ( ) ) ;


<s> static bool checkBoolTestAndOrSetCCCombine ( SDValue Cond , <STR_LIT> & CC0 , <STR_LIT> & CC1 , SDValue & Flags , bool & isAnd ) { if ( Cond -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CondOp1C = dyn_cast < ConstantSDNode > ( Cond -> getOperand ( <NUM_LIT> ) ) ; if ( ! CondOp1C || ! CondOp1C -> isNullValue ( ) ) return false ; Cond = Cond -> getOperand ( <NUM_LIT>


<s> bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Info . Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Info . Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : Info . OrigArgs ) { if ( OrigArg . Flags . isByVal ( ) ) return false ; if ( OrigArg . Regs . size ( ) > <NUM_LIT> ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Regs [ <NUM_LIT> ] ) ; } ) ) return false ; } OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = Info . OrigArgs . empty ( ) ? true : Info . OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( Info . CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Handler . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState


<s> else if ( SecondOpcode == <STR_LIT> ) { if ( ! FirstMI ) return true ; if ( FirstMI -> definesRegister ( <STR_LIT> ) ) switch ( FirstMI -> getOpcode ( ) ) { case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasShiftedReg ( * FirstMI ) ) ; case <STR_LIT> : case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasExtendedReg ( * FirstMI ) ) ; case


<s> MachineBasicBlock * Filler :: selectSuccBB ( MachineBasicBlock & B ) const { if ( B . succ_empty ( ) ) return nullptr ; auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end ( ) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) { return Prob . getEdgeWeight ( & B , Dst0 ) < Prob . getEdgeWeight ( & B , Dst1 ) ; } )


<s> unsigned int res = <NUM_LIT> ; while ( * str != '\0' ) { if ( * str == c


<s> static bool isPostIncrementForm ( const MCInst * MI , int


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( Op1 . isReg ( ) && Op2 . isReg ( ) && Register :: isVirtualRegister ( Op1 . getReg ( ) ) && Register :: isVirtualRegister ( Op2 . getReg ( ) ) ) { MachineInstr * Op1Def = MRI -> getVRegDef ( Op1 . getReg ( ) ) ; MachineInstr * Op2Def = MRI -> getVRegDef ( Op2 . getReg ( ) ) ; if ( TII -> produceSameValue ( * Op1Def , * Op2Def , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Op1Def << <STR_LIT> << * Op2Def << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> case VK_ABS_G0_NC : return <STR_LIT> ; case VK_PREL_G3 : return <STR_LIT> ; case VK_PREL_G2 : return <STR_LIT> ; case VK_PREL_G2_NC : return <STR_LIT> ; case VK_PREL_G1 : return <STR_LIT> ; case VK_PREL_G1_NC : return <STR_LIT> ; case VK_PREL_G0 : return <STR_LIT> ; case VK_PREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 : return <STR_LIT> ; case VK_DTPREL_LO12 : return <STR_LIT> ; case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 :


, int __LX , __m128i __Y , int __LY , const int __M ) {


<s> if ( ! CI -> isTailCall ( ) ) return false ; CallingConv :: ID CalleeCC = CI -> getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return


<s> static SDValue PXLowerADD ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { return GENLowerADD ( Op , DAG ) ; } else if ( VT == <STR_LIT> ) { std :: string mask = <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask += <STR_LIT> ; SDValue Mask = b . Constant (


<s> MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ; return static_cast < <ISA_LIT>TargetStreamer & > ( TS


<s> f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = AARCH64_ROUND_UP ( gr_save_area_size


<s> return ( ! csky_cannot_force_const_mem ( mode , x ) && CONSTANT_P (


<s> std :: unique_ptr < ScheduleDAGMutation > create<ISA_LIT>MacroFusionDAGMutation ( ) { return createBranchMacroFusionDAGMutation ( shouldScheduleAdjacent


<s> case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ; if ( ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( GET_CODE ( src ) != NEG && GET_CODE ( src ) != NOT && GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) ) return false ; return


<s> MCAsmParserExtension :: Initialize ( parser ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn =


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) .


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; auto TRI = STI . getRegisterInfo ( ) ; if ( ! STI . isTargetLinux ( ) || ! ( CallConv == CallingConv :: C || CallConv == CallingConv :: <ISA_LIT>_64_SysV ) ) return false ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : OrigArgs ) { if ( OrigArg . Flags . isByVal ( ) ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Reg ) ; } ) ) return false ; } OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = OrigArgs . empty ( ) ? true : OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Handler . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < unsigned ,


<s> unsigned RegNo ; switch ( CCReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ; break ; case <STR_LIT> : RegNo = <NUM_LIT> ;


<s> static void initiate_bundle_state_table (


<s> if ( ! SelectAddr ( Op , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return load ? <STR_LIT> :


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , reg_class_names [ ret ] , reg_class_names [ rclass ] , GET_MODE_NAME ( mode ) ) ; debug_rtx ( in )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u16 ( unsigned short


<s> const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM , <NUM_LIT> ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && STI . hasSym32 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) || STI . useSoftFloat ( ) ) TS . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) TS . emitDirectiveModuleOddSPReg ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection


<s> SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const TargetMachine & TM = getTargetMachine ( ) ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Result .


<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else


<s> return ; } if ( code == SMAX || code == SMIN ) c = GE ; else c = GEU ; if ( code == SMAX || code == UMAX ) target = emit_conditional_move ( dest , { c , op0 , op1 , mode } , op0 , op1 , mode , <NUM_LIT> ) ; else target = emit_conditional_move ( dest , { c , op0 , op1 , mode } , op1 , op0 , mode , <NUM_LIT> ) ; gcc_assert ( target ) ; if ( target != dest ) emit_move_insn ( dest


<s> for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT>


<s> if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; return nullptr ; } if ( RB . getID ( ) == <STR_LIT> ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; } return nullptr


<s> SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiv4si (


<s> static DecodeStatus DecodeAR32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> unsigned getRotImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ) const { switch ( MI . getOperand ( Op ) . getImm ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> :


<s> mips_expand_vi_constant ( V4HImode , <NUM_LIT> , target , vals ) ; emit_insn ( gen_vec_setv4hi ( target , target , XVECEXP ( vals , <NUM_LIT> , one_var ) , GEN_INT ( one_var


<s> <ISA_LIT>MCTargetExpr * <ISA_LIT>MCTargetExpr :: Create ( const MCSymbol * Sym , VariantKind K , MCContext


<s> VT = <STR_LIT> ; } } else { if ( Len >= <NUM_LIT> && Alignment == <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Alignment == <NUM_LIT> && <STR_LIT> ) ; VT = <STR_LIT> ; } } bool RV ; unsigned ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV == true && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ; assert ( RV == true && <STR_LIT> ) ; ( void ) RV ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; Dest . Offset += Size ; Src . Offset += Size


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name , bool is64BitReg ) { int CC ; CC = matchCPURegisterName ( Name ) ; if ( CC != - <NUM_LIT> ) return matchRegisterByNumber ( CC


<s> __inline__ static void sh_media_PREFI ( void * mm , int s ) { __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; const bool IsPurecap = TT . getEnvironment ( ) == Triple :: CheriPurecap || Options . ABIName == <STR_LIT> ; Init<ISA_LIT>MCRegisterInfo ( X , IsPurecap ?


<s> static bool canGuaranteeTCO ( CallingConv :: ID


<s> } } if ( NeedsRotate ) Res = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , InstCnt ) ; else Res = VRI . V ; if ( Res ) eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt && BG . Repl32 == VRI . Repl32 ; } ) ; } if ( ! Res ) for ( auto I = BitGroups . begin ( ) , IE = BitGroups . end ( ) ; I != IE ; ++ I ) { if ( SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , false ) < SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , true ) ) { if ( I != BitGroups . begin ( ) ) { BitGroup BG = * I ; BitGroups . erase ( I ) ; BitGroups . insert ( BitGroups . begin ( ) , BG ) ; } break ; } } for ( auto & BG : BitGroups ) { if ( ! Res ) Res = SelectRotMask64 ( BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; else Res = SelectRotMaskIns64 ( Res , BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; } if ( LateMask ) { uint64_t Mask = getZerosMask ( ) ; bool Use32BitInsts = isUInt <


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case


<s> InChain = FprIndex . getValue ( <NUM_LIT> ) ; SDValue RegSaveAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = OverflowArea . getValue ( <NUM_LIT> ) ; SDValue RegSaveArea = DAG . getLoad ( <STR_LIT> , dl , InChain , RegSaveAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = RegSaveArea . getValue ( <NUM_LIT> ) ; SDValue CC = DAG . getSetCC ( dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue RegConstant = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT . isInteger ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , RegSaveArea , RegConstant ) ; if ( VT . isFloatingPoint ( ) ) OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , OurReg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue IndexPlus1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ,


<s> switch ( CC ) { default : changeFPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; break ; case <STR_LIT> : Invert = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 =


<s> <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction


<s> for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) CLEAR_HARD_REG_BIT ( temps , EH_RETURN_DATA_REGNO ( i ) ) ; } } if ( TARGET_SHMEDIA && epilogue_p < <NUM_LIT> ) for ( i = FIRST_TARGET_REG ; i <= LAST_TARGET_REG ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( epilogue_p <= <NUM_LIT> ) { for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) { HARD_REG_SET temps ; COPY_HARD_REG_SET ( temps , * live_regs_mask ) ; CLEAR_HARD_REG_BIT ( temps , REGNO ( reg ) ) ; temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> ) { rtx adj_reg , tmp_reg , mem ; gcc_assert ( ! TARGET_SHMEDIA && epilogue_p ) ; gcc_assert ( ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] ) ; adj_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; tmp_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; emit_move_insn ( gen_tmp_stack_mem ( Pmode , reg ) , adj_reg ) ; emit_insn ( GEN_MOV ( adj_reg , GEN_INT ( size ) ) ) ; emit_insn ( GEN_ADD3 ( adj_reg , adj_reg , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg ) ; emit_move_insn ( tmp_reg , gen_tmp_stack_mem ( Pmode , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg ) ; emit_move_insn ( reg , adj_reg ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_POST_INC ( Pmode , reg ) ) ; emit_move_insn ( adj_reg , mem ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_POST_INC ( Pmode , reg ) ) ; emit_move_insn ( tmp_reg , mem ) ; emit_use ( tmp_reg ) ; emit_use ( adj_reg ) ; return ; } const_reg = gen_rtx_REG ( GET_MODE ( reg ) ,


<s> if ( get_attr_type ( insn ) != TYPE_STORE ) return false ; if ( INSN_CODE ( insn ) == CODE_FOR_move_di || INSN_CODE (

insn ) == CODE_FOR_move_df ) return false ;


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) CC = CallingConv :: <ISA_LIT>_INTR ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return CSR_NoRegs_SaveList ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit


<s> EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; if ( auto * Gather = dyn_cast < MaskedGatherSDNode > ( GorS ) ) { SDValue Ops [ ] = { Chain , Gather -> getPassThru ( ) , Mask , Base , Index , Scale } ; return DAG . getMaskedGather ( Gather -> getVTList ( ) , Gather -> getMemoryVT ( ) , DL , Ops , Gather -> getMemOperand ( ) , Gather -> getIndexType ( ) ) ; } auto * Scatter = cast < MaskedScatterSDNode > ( GorS ) ; SDValue Ops [ ] = { Chain , Scatter -> getValue ( ) , Mask , Base , Index , Scale } ; return DAG . getMaskedScatter ( Scatter -> getVTList ( ) , Scatter -> getMemoryVT ( ) , DL , Ops , Scatter -> getMemOperand ( ) , Scatter -> getIndexType ( ) ) ; } } if ( ( Index . getOpcode ( ) == <STR_LIT> || Index . getOpcode ( ) == <STR_LIT> ) && IndexWidth > <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; if ( auto * Gather = dyn_cast < MaskedGatherSDNode > ( GorS ) ) { SDValue Ops [ ] = { Chain , Gather -> getPassThru ( ) , Mask , Base , Index , Scale } ; return DAG . getMaskedGather ( Gather -> getVTList ( ) , Gather -> getMemoryVT ( ) , DL , Ops , Gather -> getMemOperand ( ) , Gather -> getIndexType ( ) ) ; } auto * Scatter = cast < MaskedScatterSDNode > ( GorS ) ; SDValue Ops [ ] = { Chain , Scatter -> getValue ( ) , Mask , Base , Index , Scale } ; return DAG . getMaskedScatter ( Scatter -> getVTList ( ) , Scatter -> getMemoryVT ( ) , DL , Ops , Scatter -> getMemOperand ( ) , Scatter -> getIndexType ( ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) { unsigned IndexWidth = Index . getScalarValueSizeInBits (


<s> return __builtin_mve_vcreateq_sv16qi ( __a ,


<s> if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address


<s> Vec = concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } else { Vec = DAG . getConstant ( Ones , dl , <STR_LIT> ( <STR_LIT> , NumElts ) ) ; } return DAG . getBitcast (


<s> case ABI_BASE_LP64F : case ABI_BASE_LP64S : if ( abi . ext ==


<s> int xstormy16_mode_dependent_address_p ( rtx x ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return <NUM_LIT> ; return <NUM_LIT>


<s> return ( __m512i ) __builtin_ia32_cvttps2dq512_mask ( ( __v16sf ) __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16


<s> void DecodeMOVDDUPMask ( unsigned NumElts , SmallVectorImpl < int > & ShuffleMask ) { const unsigned NumLaneElts = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) for ( unsigned i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) ShuffleMask


<s> unsigned <ISA_LIT>AsmBackend :: getMaximumNopSize ( const MCSubtargetInfo & STI ) const { if ( STI . hasFeature ( <STR_LIT> ) ) return <NUM_LIT> ; if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature


<s> if ( is64Bit ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT>


<s> errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) == Type :: getFloatTy ( CFP -> getContext ( ) ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) == Type :: getDoubleTy ( CFP -> getContext ( ) ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { llvm_unreachable ( <STR_LIT> )


<s> CCValAssign & VA = RVLocs [ i ] ; EVT VT = VA . getValVT ( ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VT , InFlag ) . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain .


<s> const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & SelectionDAGISel :: ID , nullptr , false , false ) ; Registry . registerPass ( *


<s> ElemSize esize = Opcode == <STR_LIT> ? ESize8 : ( Opcode == <STR_LIT> ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn


<s> } ncrn = pcum -> aapcs_ncrn ; nregs = size / UNITS_PER_WORD ; if ( allocate_ncrn && ( ncrn + nregs <= NUM_ARG_REGS ) ) { unsigned int alignment = aarch64_function_arg_alignment ( mode , type ) ; gcc_assert ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || nregs == <NUM_LIT> ) ; if ( nregs == <NUM_LIT> && alignment == <NUM_LIT> * BITS_PER_UNIT && ncrn % <NUM_LIT> ) { ++ ncrn ; gcc_assert ( ncrn + nregs <= NUM_ARG_REGS ) ; } if ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || GET_MODE_CLASS ( mode ) == MODE_INT ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , R0_REGNUM + ncrn ) ; } else { rtx par ; int i ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tmp = gen_rtx_REG ( word_mode , R0_REGNUM


<s> OperandMatchResultTy parseFP64 ( SmallVectorImpl < MCParsedAsmOperand *


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_CCOut ) ; Op -> Reg . RegNum =


<s> unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> ) return false ; if ( VecTy -> getNumElements ( ) < <NUM_LIT> ) return


<s> if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ; return


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , ZeroVal ) ; Ops [ <NUM_LIT> ] = Mask ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } SDValue WideLd = DAG . getMaskedLoad ( WideVecVT , dl , Mld -> getChain ( ) , Mld -> getBasePtr ( ) , NewMask , WidePassThru , Mld -> getMemoryVT ( ) , Mld -> getMemOperand ( ) , <STR_LIT> ) ; SDValue SlicedVec = DAG . getBitcast ( WideVecVT , WideLd ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i


<s> Inst . addOperand ( MCOperand :: CreateImm ( OptionHiS ) ) ; return MCDisassembler


<s> bool isMEMri ( ) const { return Kind


<s> static bool mips_lwxs_address_p ( rtx addr ) { if ( ISA_HAS_LWXS && GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) { rtx offset = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( offset ) == MULT && REG_P ( XEXP ( offset , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( offset , <NUM_LIT> ) ) && INTVAL ( XEXP ( offset , <NUM_LIT> ) ) == <NUM_LIT> ) return true ; } return false


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt

( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; Inst . addOperand ( MCOperand :: createImm ( ( cmode & <NUM_LIT> ) << <NUM_LIT> ) ) ; return Success


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( )


<s> if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ; if ( RegWidth == <NUM_LIT> ) Value &= <NUM_LIT> ; if ( Value == <NUM_LIT> && Shift != <NUM_LIT> ) return false ; return ( Value & ~ ( <NUM_LIT>


<s> const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST .


<s> __builtin_aarch64_simd_ci __o ; float32x4x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ]


<s> if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( strncmp ( name , LTO_SECTION_NAME_PREFIX , strlen ( LTO_SECTION_NAME_PREFIX


<s> auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT> , I * <NUM_LIT> * <NUM_LIT> ) ; SExpr * SP_times_8 = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , SP ) ,

ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ;


<s> virtual const <ISA_LIT>ELFWriterInfo * getELFWriterInfo ( )


<s> case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op ,


<s> MI -> getParent ( ) -> push_back ( NOP2 ) ; for ( auto & Reg : functionCallArgs ) { MachineInstr * checkArgM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( getSlaveReg2 ( Reg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * checkArgD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( Reg ) ) . addReg ( getSlaveReg2 ( Reg ) ) . addImm ( <NUM_LIT> ) ; diagnosisBB -> push_back ( checkArgM ) ; diagnosisBB -> push_back ( checkArgD ) ; } MachineInstr * jumpBack = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getParent ( ) ) ; diagnosisBB -> push_back ( jumpBack ) ; MachineInstr * NOP = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; diagnosisBB -> push_back ( NOP ) ; diagnosisBB -> addSuccessor ( MI -> getParent ( ) ) ; MachineBasicBlock * diagnosisBB1 = MF . CreateMachineBasicBlock ( ) ; It = ( MF . end ( ) ) -> getIterator ( ) ; MF . insert ( It , diagnosisBB1 ) ; MI -> getParent ( ) -> addSuccessor ( diagnosisBB1 ) ; MIcmp = NULL ; MItest = NULL ; for ( auto & Reg : functionCallArgs ) { MIcmp = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( getSlaveReg2 ( Reg ) ) ; MI -> getParent ( ) -> insert ( MI , MIcmp ) ; MItest = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( diagnosisBB1 ) ; MI -> getParent ( ) -> insert ( MI , MItest ) ; } NOP1 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MI -> getParent ( ) -> insert ( MI , NOP1 ) ; NOP2 = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MI -> getParent ( ) -> push_back ( NOP2 ) ; for ( auto & Reg : functionCallArgs


<s> return REGNO_REG_SET_P ( ENTRY_BLOCK_PTR -> il . rtl


<s> if ( ! op0_preserve_value && GET_CODE ( * op0 ) == FLOAT && MEM_P ( XEXP ( * op0 , <NUM_LIT> ) ) && REG_P ( * op1 ) ) { enum rtx_code scode = swap_condition ( ( enum rtx_code )


<s> if ( ! cast < ConstantInt > ( DupQLane -> getArgOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return None ; auto * VecIns = dyn_cast < IntrinsicInst > ( DupQLane -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! VecIns || VecIns -> getIntrinsicID ( ) != <STR_LIT> ) return None ; if ( ! isa < UndefValue > ( VecIns -> getArgOperand ( <NUM_LIT> ) ) ) return None ; if ( ! cast < ConstantInt > ( VecIns -> getArgOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return None ; auto * ConstVec = dyn_cast < Constant > ( VecIns -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! ConstVec ) return None ; auto * VecTy = dyn_cast < FixedVectorType > ( ConstVec -> getType ( ) ) ; auto * OutTy = dyn_cast < ScalableVectorType > ( II . getType ( ) ) ; if ( ! VecTy || ! OutTy || VecTy -> getNumElements ( ) != OutTy -> getMinNumElements ( ) ) return None ; unsigned NumElts = VecTy -> getNumElements ( ) ; unsigned PredicateBits = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { auto * Arg = dyn_cast < ConstantInt > ( ConstVec -> getAggregateElement ( I ) ) ; if ( ! Arg ) return None ; if ( ! Arg -> isZero ( ) ) PredicateBits |= <NUM_LIT> << ( I * ( <NUM_LIT> / NumElts ) ) ; } if ( PredicateBits == <NUM_LIT> ) { auto * PFalse = Constant :: getNullValue ( II . getType ( ) ) ; PFalse -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , PFalse ) ; } unsigned Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) if ( ( PredicateBits & ( <NUM_LIT> << I ) ) != <NUM_LIT> ) Mask |= ( I % <NUM_LIT> ) ; unsigned PredSize = Mask & - Mask ; auto * PredType = ScalableVectorType :: get ( Type :: getInt1Ty ( Ctx ) , <STR_LIT> / ( PredSize * <NUM_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += PredSize ) if ( ( PredicateBits & ( <NUM_LIT> << I ) ) == <NUM_LIT> ) return None ; auto * PTruePat = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , <STR_LIT> ) ; auto * PTrue = Builder . CreateIntrinsic ( <STR_LIT> , { PredType } , { PTruePat } ) ; auto * ConvertToSVBool = Builder . CreateIntrinsic ( <STR_LIT> , { PredType } , { PTrue } ) ; auto * ConvertFromSVBool = Builder . CreateIntrinsic ( <STR_LIT> , { II . getType ( ) }


<s> } StringRef Arch = Parser . getTok ( ) . getString ( ) ; SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; unsigned ID = StringSwitch < unsigned > ( Arch ) . Case ( NAME , <STR_LIT> ) . Case ( NAME , <STR_LIT> )


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> return new <ISA_LIT>DeadRegisterDefinitions ( )


<s> if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . NOT ( A2 ) ; SDValue TmpAns = b . OR ( b . AND ( A1 , Tmp ) , b . AND ( b . SHL < <NUM_LIT> > ( b . AND ( b . NOT ( A1 ) , A2 ) ) , b . OR ( A1 , Tmp ) ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , TmpAns , b . SRL < <NUM_LIT> > (


<s> MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; if ( isFPCmp ) BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; else BuildMI ( BB , dl , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB =


<s> Inst . addOperand ( MCOperand :: createReg ( VSRpRegs [ RegNo >> <NUM_LIT> ] ) ) ; return MCDisassembler :: Success


<s> machine_mode dmode = GET_MODE ( op0 ) ; machine_mode smode = GET_MODE ( op1 ) ; machine_mode inner_dmode = GET_MODE_INNER ( dmode ) ; machine_mode inner_smode = GET_MODE_INNER ( smode ) ; int nunits = <NUM_LIT> / GET_MODE_SIZE ( inner_dmode ) ; machine_mode sse_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits ) . require ( ) ; machine_mode sse_half_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits / <NUM_LIT> ) . require ( ) ; nunits = <NUM_LIT> / GET_MODE_SIZE ( inner_smode ) ; machine_mode sse_smode = mode_for_vector ( GET_MODE_INNER ( smode ) , nunits ) . require ( ) ; rtx dest = lowpart_subreg ( sse_dmode , op0 , GET_MODE ( op0 ) ) ; op1 = lowpart_subreg ( sse_smode , op1 , GET_MODE ( op1 ) ) ; op2 = lowpart_subreg ( sse_smode , op2


<s> for ( i = <NUM_LIT> ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; if ( d -> vec_flags == VEC_SVE_DATA ) { machine_mode int_mode = aarch64_sve_int_mode ( pred_mode ) ; rtx target = gen_reg_rtx ( int_mode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_aarch64_sve_reinterpret ( int_mode , target , d -> op0 ) ) ; else { int unspec = aarch64_sve_rev_unspec ( d -> vmode ) ; rtx pred = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_pred ( unspec , int_mode , target , pred , gen_lowpart ( int_mode , d -> op0 ) ) ) ; } emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , target ) ) ; return true ; } rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d -> op0 ) , unspec ) ; emit_set_insn ( d -> target , src ) ; return true


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static inline unsigned encodeNEONi16splat ( unsigned Value ) { assert ( isNEONi16splat ( Value ) && <STR_LIT> ) ; if ( Value >= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | <NUM_LIT> ; else Value


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumGPRs = array_lengthof ( GPR ) ; const unsigned NumFPRs = <NUM_LIT> ; const unsigned NumVRs = array_lengthof ( VR ) ; const unsigned ParamAreaSize = NumGPRs * PtrByteSize ; unsigned NumBytes = LinkageSize ; unsigned AvailableFPRs = NumFPRs ; unsigned AvailableVRs = NumVRs ; for ( const <STR_LIT> & Param :


<s> case E_V16QImode : if ( ! BYTES_BIG_ENDIAN ) { if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_ld_elemrev_v16qi_internal ( reg , mem ) ) ; else { rtx reg_v2di = simplify_gen_subreg ( V2DImode , reg , V16QImode , <NUM_LIT> ) ; gcc_assert ( MEM_P ( mem ) ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; rtx mem_v2di = gen_rtx_MEM ( V2DImode , addr ) ; MEM_COPY_ATTRIBUTES ( mem_v2di , mem ) ; set_mem_size ( mem , GET_MODE_SIZE ( V2DImode ) ) ; emit_insn ( gen_vsx_ld_elemrev_v2di ( reg_v2di , mem_v2di ) ) ; } } else emit_insn ( gen_vsx_movv2di_64bit ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable (


<s> FunctionPass * llvm :: createMVEVPTOptimisationsPass


<s> if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ; default : return


<s> } } else if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill ) , FrameIndex ) ; } else { unsigned OutReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( OutReg , true , false , false , isDead ) , FrameIndex ) ; } } else if ( Opc == <STR_LIT> ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill ) , FrameIndex ) ; } else { unsigned OutReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( OutReg , true , false , false , isDead ) , FrameIndex ) ; } } else if ( Opc == <STR_LIT> ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill


<s> } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> )


<s> NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV


<s> } else if ( DstReg != MI . getOperand ( DOPIdx ) . getReg ( ) && DstReg != MI . getOperand ( SrcIdx ) . getReg ( ) ) { PRFX = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( DOPIdx ) ) ; DOPIdx = <NUM_LIT> ; } unsigned Opnds [ ] = { PredIdx , DOPIdx , SrcIdx } ; if ( Info . DType == Unary ) std :: swap ( Opnds [ <NUM_LIT> ] , Opnds [ <NUM_LIT> ] ) ; DOP = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Info . InstrOpcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addOperand ( MI . getOperand ( Opnds [ <NUM_LIT> ] ) ) . addOperand ( MI . getOperand ( Opnds [ <NUM_LIT> ] ) ) . addOperand ( MI . getOperand ( Opnds [ <NUM_LIT> ] ) ) ; if ( PRFX ) { finalizeBundle ( MBB , PRFX -> getIterator ( ) , MBBI -> getIterator ( ) ) ; transferImpOps ( MI , PRFX


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { unsigned int targetReg = <STR_LIT> ; if ( I -> getOpcode ( ) == <STR_LIT> ) targetReg = <STR_LIT> ; else { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; targetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( targetReg == <STR_LIT> ) continue ; MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( targetReg ) . addReg ( getSlaveReg1 ( targetReg ) ) ; MBB -> insert ( I , cmpInst ) ; MachineInstr * MImfspr = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) .

addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( GET_CODE ( reg1 ) != REG ) return <NUM_LIT> ; regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ; regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return <NUM_LIT> ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) &&

SPARC_INT_REG_P ( regno2 ) ) ) return <NUM_LIT> ;


<s> tree_code code = gimple_assign_rhs_code ( assign ) ; if ( code != PLUS_EXPR && code != MINUS_EXPR ) return false ; if ( CONSTANT_CLASS_P ( gimple_assign_rhs1 ( assign ) ) || CONSTANT_CLASS_P ( gimple_assign_rhs2 ( assign ) ) ) return false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { tree rhs = gimple_op ( assign , i ) ; if ( TREE_CODE ( rhs )


<s> return ( __m256 ) __builtin_ia32_cvtpd2ps512_mask ( ( __v8df ) __A , ( __v8sf ) _mm256_undefined_ps ( )


<s> static DecodeStatus DecodeShiftRight16Imm ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


<s> if ( VT == <STR_LIT> ) { assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Index . getValueType ( ) == <STR_LIT> && Subtarget . hasVLX ( ) ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index , Scale } ; SDValue NewScatter = DAG . getTargetMemSDNode < <ISA_LIT>MaskedScatterSDNode > ( VTs , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; return SDValue ( NewScatter . getNode ( ) , <NUM_LIT> ) ; } return SDValue ( ) ; } if ( VT == <STR_LIT> ) { assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ; if ( Index . getValueType ( ) == <STR_LIT> && Subtarget . hasVLX ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index , Scale } ; SDValue NewScatter = DAG . getTargetMemSDNode < <ISA_LIT>MaskedScatterSDNode > ( VTs , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; return SDValue ( NewScatter . getNode ( ) , <NUM_LIT> ) ; } EVT NewIndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , Index . getValueType ( ) . getVectorElementType ( ) , <NUM_LIT> ) ; Index = DAG . getNode ( <STR_LIT> , dl , NewIndexVT , Index , DAG . getUNDEF ( Index . getValueType ( ) ) ) ; Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant (


<s> enum reg_class mmix_preferred_output_reload_class ( rtx x ATTRIBUTE_UNUSED , enum reg_class class ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << ShAmt ; } O <<


<s> unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag , GV ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , DL , GA ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN ->


<s> unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , Subtarget -> is64Bit ( ) ? <STR_LIT>


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back (


, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> SDLoc DL ( Op ) ; bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue V = Op -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; MVT VecIntVT = V . getSimpleValueType ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget . hasAVX512 ( ) ) { assert ( ! Subtarget . hasVLX ( ) && <STR_LIT> ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return Op ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; MVT WideVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MVT WideIntVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Tmp = IsStrict ? DAG . getConstant ( <NUM_LIT> , DL , WideIntVT ) : DAG . getUNDEF ( WideIntVT ) ; V = DAG . getNode ( <STR_LIT> , DL , WideIntVT , Tmp , V , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , DL , { WideVT , <STR_LIT> } , { Op -> getOperand ( <NUM_LIT> ) , V } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , WideVT , V ) ; } Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , DL ) ; return Res ; } if ( Subtarget . hasAVX ( ) && VecIntVT == <STR_LIT> && Op -> getSimpleValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue ZExtIn = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V ) ; Constant * Bias = ConstantFP :: get ( * DAG . getContext ( ) , APFloat ( APFloat ::

IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ;


<s> SDLoc DL ( Op ) ; bool HasAddrDiversity = ! isNullConstant ( AddrDiscriminator ) ; uint64_t PtrOffsetC = <NUM_LIT> ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { PtrOffsetC = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } GlobalAddressSDNode * PtrN = cast < GlobalAddressSDNode > ( Ptr . getNode ( ) ) ; SDValue TPtr = DAG . getTargetGlobalAddress ( PtrN -> getGlobal ( ) , DL , VT , <NUM_LIT> , <NUM_LIT> ) ; PtrOffsetC += PtrN -> getOffset ( ) ; assert ( PtrN -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Ld = LowerPtrAuthGlobalAddressViaGOT ( Wrapper , ( <STR_LIT> ) KeyC , HasAddrDiversity , PtrN , DAG ) ) return Ld ; if ( HasAddrDiversity ) { SDValue BlendIntID = DAG . getTargetConstant ( <STR_LIT> ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMem ( unsigned ModeSize , unsigned SegReg , const MCExpr * Disp , unsigned BaseReg , unsigned IndexReg , unsigned Scale , SMLoc StartLoc , SMLoc EndLoc , unsigned Size = <NUM_LIT> , unsigned DefaultBaseReg = <STR_LIT> , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr , unsigned FrontendSize = <NUM_LIT> ) { assert ( ( SegReg || BaseReg || IndexReg || DefaultBaseReg ) && <STR_LIT> ) ; assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; auto Res = std :: make_unique < <ISA_LIT>Operand > ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( Subtarget -> hasBMI ( ) ) { if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isZero ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isZero ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue ( ) ; if ( isMask_64 ( Mask ) ) { uint64_t MaskSize = CountPopulation_64 ( Mask ) ; if ( Shift + MaskSize <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Shift | ( MaskSize << <NUM_LIT> ) , VT ) ) ; } } } } if ( Subtarget -> hasBMI2 ( ) ) { if ( N0 . getOpcode ( ) == <STR_LIT> && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode (


<s> if ( isOneConstant ( Other ) && isOverflowIntrOpRes ( Sel ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Sel -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand (


<s> nVT <= <STR_LIT> ; ++ nVT ) { EVT SVT = ( <STR_LIT> ) nVT ; if ( isTypeLegal ( SVT ) && SVT . getVectorElementType ( ) == EltVT && SVT . getVectorNumElements ( ) > NElts ) return SVT ; } return


<s> Optional < RegOrConstant > <ISA_LIT>GISelUtils :: get<ISA_LIT>VectorSplat ( const MachineInstr & MI , const MachineRegisterInfo & MRI ) { if ( auto Splat = getVectorSplat ( MI , MRI ) ) return Splat ; if ( MI . getOpcode ( ) != <STR_LIT> ) return None ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return RegOrConstant ( ValAndVReg -> Value . getSExtValue ( ) ) ; return RegOrConstant (


<s> static void init_vselect_insn ( void ) { unsigned i ; rtx x ; x = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( MAX_VECT_LEN ) ) ; for ( i = <NUM_LIT> ; i < MAX_VECT_LEN ; ++ i

) XVECEXP ( x , <NUM_LIT> , i ) = const0_rtx ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( )


<s> bool TailCallOpt = getTargetMachine ( ) . Options . GuaranteedTailCallOpt ; if ( DisableSCO && ! TailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CallerCC != CalleeCC ) return false ; if ( CalleeCC != CallingConv :: Fast && CalleeCC != CallingConv :: C ) return false ; if ( std :: any_of ( Ins . begin ( ) , Ins . end ( ) , [ ] ( const <STR_LIT> & IA ) { return IA . Flags . isByVal ( ) ; } ) ) return false ; if ( any_of ( Outs , [ ] ( const <STR_LIT> & OA ) {

return OA . Flags . isByVal ( ) ; } ) ) return false ;


<s> static DecodeStatus decodePredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { if ( Val >= LPCC :: UNKNOWN ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success


<s> unsigned getRegisterBitWidthUpperBound ( bool Vector ) { if ( Vector && ST -> hasSVE ( ) )


<s> } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false ,


<s> default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + strlen ( <STR_LIT> ) ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = <NUM_LIT> ; DECL_EXTERNAL ( new_fndecl ) = <NUM_LIT> ; DECL_IS_NOVOPS ( new_fndecl ) = <NUM_LIT> ; TREE_READONLY ( new_fndecl ) = <NUM_LIT> ; return new_fndecl


<s> break ; } case CodeModel :: Large : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , RegO7 , OutContext , STI ) ; EmitADD ( * OutStreamer , MCRegOP , RegO7 , MCRegOP , STI ) ; } } return ; } MCSymbol * StartLabel = OutContext . createTempSymbol ( ) ; MCSymbol * EndLabel = OutContext . createTempSymbol ( ) ; MCSymbol * SethiLabel = OutContext . createTempSymbol ( ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; OutStreamer -> EmitLabel ( StartLabel ) ; MCOperand Callee = createPCXCallOP ( EndLabel , OutContext ) ; EmitCall ( * OutStreamer , Callee , STI ) ; OutStreamer -> EmitLabel ( SethiLabel ) ; MCOperand hiImm = createPCXRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 , GOTLabel , StartLabel , SethiLabel , OutContext ) ; EmitSETHI ( * OutStreamer , hiImm , MCRegOP


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PrevInstr << <STR_LIT> << * CurrInstr << <STR_LIT> << isFirstInstructionInSequence ( PrevInstr ) << <STR_LIT> << <STR_LIT> << isSecondInstructionInSequence ( CurrInstr ) << <STR_LIT> ) ; if ( isFirstInstructionInSequence ( PrevInstr ) && isSecondInstructionInSequence ( CurrInstr ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Idx << <STR_LIT> ) ; ( void ) Idx ; Sequences . push_back ( CurrInstr ) ; } } if ( ! CurrInstr -> isPseudo ( ) ) PrevInstr = CurrInstr ; ++ Idx ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Sequences . size ( ) << <STR_LIT> ) ; for ( auto & MI : Sequences ) { Changed =


<s> Value * <ISA_LIT>IREmitter :: visitANDNP (


<s> for ( unsigned int i = <NUM_LIT> ; i < nelts ; ++ i ) if ( INTVAL ( builder . elt ( i ) ) != <NUM_LIT> ) { if ( i & <NUM_LIT> ) return <NUM_LIT> ; mask |= i


<s> op [ <NUM_LIT> ] = copy_to_mode_reg ( Pmode , op [ <NUM_LIT> ] ) ; addr = gen_rtx_MEM ( smode , gen_rtx_PLUS ( Pmode , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ) ; } pat = GEN_FCN ( icode ) ( target , addr


<s> if ( ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> ) return SDValue ( ) ; for ( <STR_LIT> Op : { <STR_LIT> , <STR_LIT> } ) { SDValue Match = matchBinOpReduction ( Extract , Op ) ; if ( ! Match ) continue ; if ( Match . getScalarValueSizeInBits ( ) != BitWidth ) continue ; unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && ( ( Subtarget . hasAVX ( ) && BitWidth >= <NUM_LIT> ) || Subtarget . hasAVX2 ( ) ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( Op == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext ( ) ,


<s> if ( GET_CODE ( x ) == ZERO_EXTRACT || GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) x = XEXP ( x , <NUM_LIT> ) ; if ( MEM_P ( x ) ) continue ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == PRE_INC

|| GET_CODE ( x ) == PRE_DEC ) return true ;


<s> EVT EltVT = VecVT . getVectorElementType ( ) ; Op = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , EltVT , Op . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , EltVT , Op ) ; if ( EltVT != N -> getValueType ( <NUM_LIT> ) ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op ) ; } return Op ; } if ( auto * IndexN = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VecVT = Op0 . getValueType ( ) ; return combineExtract ( SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , VecVT , Op0 , IndexN -> getZExtValue ( ) , DCI , false ) ; } return SDValue (


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) ||


<s> else if ( b == <NUM_LIT> && st == ST_INRANGE ) st = ST_TRAILING_ZEROS ; else if ( b == <NUM_LIT> && st == ST_FFS ) { st = ST_INRANGE ; r . start = i ; r . nbytes = <NUM_LIT> ; } else if ( b == <NUM_LIT> && st == ST_INRANGE ) r . nbytes ++ ; else return invalid_range ; } if ( st != ST_TRAILING_ZEROS && st != ST_INRANGE )


<s> switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT>


) _mm256_broadcast_ps ( __m128 const * __X ) {


<s> return true ; } } if ( ( N1 . isUndef ( ) || DAG . ComputeNumSignBits ( VV1 ) > BitSize ) && ( N2 . isUndef ( ) || DAG . ComputeNumSignBits ( VV2 ) > BitSize ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } return false ; } ; SmallVector < int , <NUM_LIT> > BinaryMask ; createPackShuffleMask ( VT , BinaryMask , false ) ; if ( isTargetShuffleEquivalent ( TargetMask , BinaryMask ) ) if ( MatchPACK ( V1 , V2 ) ) return true ; SmallVector < int , <NUM_LIT> > UnaryMask ; createPackShuffleMask ( VT , UnaryMask , true ) ; if ( isTargetShuffleEquivalent ( TargetMask , UnaryMask ) ) if


<s> const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return <NUM_LIT> - CurrGroupSize ; return - <NUM_LIT> ; } if ( SC


<s> Size = getPointerWidth ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ) ; } return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Info . OpDecl ) ; } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef )