<s> static void emit_constant_insn ( rtx cond , rtx pattern ) { if ( cond ) pattern = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFPOStackAlign ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; int64_t Offset ; if ( Parser . parseIntToken ( Offset , <STR_LIT> ) || Parser . parseEOL ( <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_26_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC16_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_CALL16 ; break ; case <STR_LIT> : Type = ELF ::


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> case IES_AND : case IES_EQ : case IES_NE : case IES_LT : case IES_LE : case IES_GT : case IES_GE : case IES_LSHIFT : case IES_RSHIFT : case IES_DIVIDE : case IES_MOD : case IES_MULTIPLY : case IES_LPAREN : case IES_INIT : case IES_LBRAC : State = IES_INTEGER ; if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { if ( IndexReg ) return regsUseUpError ( ErrMsg ) ; IndexReg = TmpReg ; Scale = TmpInt ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . popOperator ( ) ; } else { IC . pushOperand ( IC_IMM , TmpInt ) ; } break ; } PrevState =


<s> unsigned IndexReg = Inst -> getOperand ( IndexOpPosition ) . getReg ( ) ; if ( FlagUseZeroBasedSandbox


<s> uint64_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; AM . Disp += Val ; return false ; } case <STR_LIT> : if ( ! MatchWrapper ( N , AM ) ) return false ; break ; case <STR_LIT> : if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . BaseType = <ISA_LIT>ISelAddressMode :: FrameIndexBase ; AM . Base . FrameIndex = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; return false ; } break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup


<s> if ( GV -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI ,


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( )


<s> SmallVectorImpl < PredicatedMI > & getInsts ( ) { return


<s> if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; if ( Reg == FPReg )


<s> tree function_resolver :: resolve ( ) { return shape -> resolve (


<s> return __builtin_aarch64_floatdihf (


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_MSRMask ) ; Op -> MMask . Val = MMask ; Op -> StartLoc = S ; Op -> EndLoc =


<s> assert ( getT2SOImmVal ( Imm ) != - <NUM_LIT> && <STR_LIT>


<s> EVT VT16Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Bitcast = DAG . getNode ( <STR_LIT> , DL , VT16Bit , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Counts16 = lowerCTPOP16BitElements ( Bitcast . getNode ( ) , DAG ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , Counts16 , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT16Bit , N1 , N1 ) ; if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N2 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>

, Extended , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; RC = updatedRC ( RC ) ; StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO


<s> inline bool isImmUnsignedi4Value ( uint64_t Value ) { return isUInt < <NUM_LIT> >


<s> if ( SimplifyDemandedBits ( Op0 , DemandedMask , OriginalDemandedElts , Known , TLO , Depth + <NUM_LIT> ) ) return true ; assert ( ! Known . hasConflict ( ) && <STR_LIT> ) ; Known . Zero . lshrInPlace ( ShAmt ) ; Known . One . lshrInPlace ( ShAmt ) ; if ( Known . Zero [ BitWidth - ShAmt - <NUM_LIT> ] || OriginalDemandedBits . countLeadingZeros ( ) >= ShAmt ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op0 , Op1 ) ) ; if ( Known . One [ BitWidth - ShAmt - <NUM_LIT> ] ) Known . One . setHighBits ( ShAmt ) ; } break ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; unsigned SrcBits = SrcVT . getScalarSizeInBits ( ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; if ( OriginalDemandedBits . countTrailingZeros ( ) >= NumElts ) return TLO . CombineTo ( Op , TLO . DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , VT ) ) ; APInt KnownUndef , KnownZero ; APInt DemandedElts = OriginalDemandedBits . zextOrTrunc ( NumElts ) ; if ( SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , TLO , Depth + <NUM_LIT> ) ) return true ; Known . Zero = KnownZero . zextOrSelf ( BitWidth ) ; Known . Zero . setHighBits ( BitWidth - NumElts ) ; KnownBits KnownSrc ; if ( SimplifyDemandedBits ( Src , APInt :: getSignMask ( SrcBits ) , DemandedElts ,

KnownSrc , TLO , Depth + <NUM_LIT> ) ) return true ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDRAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum +


<s> O << '#' << MI -> getOperand ( OpNum )


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ST -> getValue ( ) , DAG . getTargetConstant ( DAG . getDataLayout ( ) . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , { ST -> getChain ( ) , Lo , Hi , ST -> getBasePtr ( ) } , MemVT , ST -> getMemOperand ( ) ) ; } else if ( Subtarget -> hasMVEIntegerOps ( ) && ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT ==


<s> assert ( ! convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) && <STR_LIT> ) ; return ; } const MCInstrDesc * MCID = & MI -> getDesc ( ) ; unsigned NewOpc = convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; if (


<s> if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVector < MBBInfo , <NUM_LIT> > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setEmitNOAT ( ) ; uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address


<s> return isMem ( MemKind , RegKind ) && inRange ( Mem . Disp , <NUM_LIT>


<s> return CurDAG -> getTargetConstant ( ( uint64_t ) <STR_LIT> , dl , <STR_LIT>


<s> SDNode * Lo = <NUM_LIT> , * Hi = <NUM_LIT> ; SDNode * Mul = CurDAG -> getMachineNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , Ty , InFlag ) ; return std :: make_pair ( Lo


<s> return Error ( ErrorLoc , <STR_LIT> ) ; } } if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( Result ) { default : break ; case Match_RequiresMsbNotLessThanLsb : { SMLoc ErrorStart = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; return Error ( ErrorStart , <STR_LIT> , SMRange ( ErrorStart , Operands [ <NUM_LIT> ] -> getEndLoc ( ) ) ) ; } case Match_RequiresOpnd2NotR0R1 : return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; case Match_InvalidUImm2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm2plus1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) ) ; case Match_InvalidUImm3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm15 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> <<


<s> if ( SVT . getVectorElementType ( ) == <STR_LIT> ) return LowerZERO_EXTEND_Mask ( Op , Subtarget , DAG ) ; if ( Subtarget . hasFp256 ( ) ) if ( SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ) return Res ; assert ( ! Op . getSimpleValueType ( ) . is256BitVector ( ) || ! SVT . is128BitVector ( )

|| Op . getSimpleValueType ( ) . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) ;


<s> if ( ! altivec_indexed_or_indirect_operand ( x , GET_MODE ( x ) ) ) { rtx addr = XEXP ( x , <NUM_LIT> ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indexed_address_p ( addr , strict_p ) && ! legitimate_indirect_address_p ( addr , strict_p ) ) addr = copy_to_mode_reg ( Pmode , addr ) ; addr = gen_rtx_AND ( Pmode , addr , GEN_INT ( - <NUM_LIT> ) ) ; x = change_address ( x , GET_MODE ( x ) , addr ) ; } return x


<s> if ( ! MO1 . isReg ( ) || MO1 . getReg ( ) != <STR_LIT> || ! MO2 . isImm ( ) ) return None ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; return Addr +


<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op .


<s>
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
' '
<<
StackOffsetBeforeAlign
<<
<STR_LIT>
<<
StackAlign
<<
<STR_LIT>
;
}
}
else
{
FuncOS
<<
CFAVar
<<
<STR_LIT>
;
}
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
<STR_LIT>
;
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
<STR_LIT>
;
for
(
RegSaveOffset
RO
:
RegSaveOffsets
)
FuncOS
<<
printFPOReg
(
MRI
,
RO
.
Reg
)
<<
' '
<<
CFAVar
<<
' '
<<
RO
.
Offset
<<
<STR_LIT>
;
CodeViewContext
&
CVCtx
=
OS
.
getContext
(
)
.
getCVContext
(
)
;
unsigned
FrameFuncStrTabOff
=
CVCtx
.
addToStringTable
(
FuncOS
.
str
(
)
)
.
second
;
unsigned
MaxStackSize
=
<NUM_LIT>
;
OS
.
emitAbsoluteSymbolDiff
(
Label
,
FPO
->
Begin
,
<NUM_LIT>
)
;
OS
.
emitAbsoluteSymbolDiff
(
FPO
->
End
,
Label
,
<NUM_LIT>
)
;
OS
.
EmitIntValue
(
LocalSize
,
<NUM_LIT>
)
;
OS
.
EmitIntValue
(
FPO
->
ParamsSize
,
<NUM_LIT>
)
;
OS
.
EmitIntValue
(
MaxStackSize
,
<NUM_LIT>
)
;
OS
.
EmitIntValue
(
FrameFuncStrTabOff
,
<NUM_LIT>
)
;
OS
.
emitAbsoluteSymbolDiff
(
FPO
->
PrologueEnd
,
Label
,
<NUM_LIT>
)
;
OS
.
EmitIntValue
(
SavedRegSize


<s> unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; return SignExtend32 < <NUM_LIT> > ( Imm25


<s> static DecodeStatus DecodeGPRMM16RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo


<s> SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; if ( NumElts >= OpsVT . getVectorNumElements ( ) ) { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) { switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = true ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) { switch ( IntrinsicID ) { case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) CompareOpc = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc = <NUM_LIT>


<s> if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder )


<s> unsigned Opc = Op . getOpcode ( ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExtendInVecOpc = getOpcode_EXTEND_VECTOR_INREG ( Opc ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( ExtendInVecOpc , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue OpLo = DAG . getNode ( ExtendInVecOpc , dl , HalfVT , In ) ; if ( auto * Shuf = dyn_cast < ShuffleVectorSDNode > ( In ) ) if ( hasIdenticalHalvesShuffleMask ( Shuf -> getMask ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpLo ) ; SDValue ZeroVec = DAG . getConstant ( <NUM_LIT> , dl , InVT ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Opc == <STR_LIT> ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; OpHi = DAG . getBitcast


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasInt256 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero && ! V2IsAllZero ) { CommuteVectorShuffleMask ( MaskVals , <NUM_LIT> ) ; V1 = V2 ; } SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i ++ ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> || EltIdx >= <NUM_LIT> ) EltIdx = <NUM_LIT> ; else { if ( ( EltIdx >= <NUM_LIT> && i < <NUM_LIT> ) || ( EltIdx < <NUM_LIT> && i >= <NUM_LIT> ) ) return SDValue


<s> void printPostIncOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printPostIncOperand ( MI , OpNo , Amount ,


<s> static rtx xstormy16_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM


<s> inline int getFP32FP16Imm ( const APFloat & FPImm ) { return getFP32FP16Imm ( FPImm . bitcastToAPInt ( )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _subborrow_u32 ( unsigned char __CF , unsigned int __X , unsigned int __Y , unsigned int * __P ) { return __builtin_ia32_sbb_u32 ( __CF , __Y ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > (


<s> EVT MemVT = LdNode -> getMemoryVT ( ) ; if ( MemVT == <STR_LIT> ) return LowerF128Load ( Op ,


<s> if ( ( Index == <NUM_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || Op0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( Index ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Index , DL , <STR_LIT> ) ) ; } GeneralShuffle GS ( VT ) ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { int Elt = VSN -> getMaskElt (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> SDValue Cond = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) return


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass


<s> switch ( GET_CODE ( x ) ) { case NE : str = <STR_LIT> ; break ; case UNORDERED : str = <STR_LIT> ; break ; case ORDERED : str = <STR_LIT> ; break ; case UNLT : str = <STR_LIT> ; break ; case UNLE : str = <STR_LIT> ; break ; case UNGT : str = <STR_LIT> ; break ; case UNGE : str = <STR_LIT> ; break ; case UNEQ : case LTGT : gcc_unreachable ( ) ; default : str = GET_RTX_NAME ( GET_CODE ( x ) ) ; break ; } fputs ( str , file ) ; return ; case 'E' : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , <NUM_LIT> - INTVAL ( x ) ) ; return ; case 'e' : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , <NUM_LIT> - INTVAL ( x ) ) ; return ; case 'F' : if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) str = reg_names [ FR_REG ( <NUM_LIT> ) ] ; else if ( x == CONST1_RTX ( GET_MODE ( x ) ) ) str = reg_names [ FR_REG ( <NUM_LIT> ) ] ; else { gcc_assert ( GET_CODE ( x ) == REG ) ; str = reg_names [ REGNO ( x ) ] ; } fputs ( str , file ) ; return ; case 'G' : { long val [ <NUM_LIT> ] ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; real_to_target ( val , & rv , GET_MODE ( x ) ) ; if ( GET_MODE ( x ) == SFmode ) fprintf ( file , <STR_LIT> , val [ <NUM_LIT> ] & <NUM_LIT> ) ; else if ( GET_MODE ( x ) == DFmode ) fprintf ( file , <STR_LIT> , ( WORDS_BIG_ENDIAN ? val [ <NUM_LIT> ] : val [ <NUM_LIT> ] ) & <NUM_LIT> , ( WORDS_BIG_ENDIAN ? val [ <NUM_LIT> ] : val [ <NUM_LIT> ] ) & <NUM_LIT> ) ; else output_operand_lossage ( <STR_LIT> ) ; } return ; case 'I' : fputs ( reg_names [ REGNO ( x ) + <NUM_LIT> ] , file ) ; return ; case 'J' : case 'j' : { unsigned int regno = REGNO ( XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == EQ ) regno += <NUM_LIT> ; if ( code == 'j' ) regno ^= <NUM_LIT> ; fputs ( reg_names [ regno ] , file ) ; } return ; case 'O' : if ( MEM_VOLATILE_P ( x ) ) fputs ( <STR_LIT> , file ) ; return ; case


<s> return ( __m128i ) __builtin_ia32_pmovdw256_mask ( ( __v8si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) ,


<s> if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d ->


<s> case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align =


<s> <ISA_LIT>TargetAsmStreamer * S = new <ISA_LIT>TargetAsmStreamer ( ) ; return llvm :: createAsmStreamer ( Ctx , S , OS , isVerboseAsm , useLoc , useCFI ,

useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> : nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateGPRReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E ,


<s> Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) .


<s> TargetRegistry :: RegisterMCDisassembler ( TheThumbLETarget , createThumbDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( TheThumbBETarget ,


<s> if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor (


<s> bool <ISA_LIT>FrameLowering :: isFPCloseToIncomingSP ( )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; MVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { JTI


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT>


<s> return decodeRegisterClass ( Inst , RegNo


<s> FuseTest , FuseCmp , FuseInc } FuseKind ; switch ( Second -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseInc ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseCmp ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseTest ; break ; } switch ( First -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> case <STR_LIT> : case <STR_LIT> : return legalizeInternalLoadStoreOp ( Op , CDAG ) ; } EVT IdiomVT = Op . getValueType ( ) ; if ( isPackedVectorType ( IdiomVT ) && ! supportsPackedMode ( Op . getOpcode ( ) , IdiomVT ) ) return splitVectorOp ( Op , CDAG ) ; return legalizePackedAVL ( Op , CDAG )


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_SJLJ_SETUP_DISPATCH ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL ,

<STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Changed = false ; Changed |= peepholeOpt ( MF ) ; return Changed


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE ->


<s> unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm


<s> if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H :


<s> output_asm_insn ( <STR_LIT> , operands ) ; } else if ( regno_use_in ( LR_REGNUM , operands [ <NUM_LIT> ] ) ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( arm_arch4t ) output_asm_insn ( <STR_LIT> , operands


<s> case <STR_LIT> : case <STR_LIT> : if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx =


<s> virtual const MandarinRegisterInfo *


<s> for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = Mask [ i + l ] ; unsigned RngStart = l + ( ( Commuted == ( i < HalfLaneElems ) ) ? NumElems : <NUM_LIT> ) ; if ( ! isUndefOrInRange ( Idx , RngStart , RngStart + NumLaneElems ) ) return false ; if ( NumElems != <NUM_LIT> || l == <NUM_LIT> || Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Idx , Mask [ i ] +


<s> bool DoMerge = false ; <STR_LIT> Mode = <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; } Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } else if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { if ( NextMBBI ==


<s> static DecodeStatus DecodeBranchTargetMM ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > (


<s> static bool isDispSafeForFrameIndex ( int64_t Val ) { return isInt < <NUM_LIT> > (


<s> void <ISA_LIT>CodeEmitter :: emitConstPoolAddress ( unsigned CPI ,


<s> vpaddq_u16 ( uint16x8_t a , uint16x8_t b ) { uint16x8_t result


<s> static bool isNaturalMemoryOperand ( SDValue Op , unsigned ICmpType ) { auto * Load = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( Load ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return false ; switch ( Load -> getExtensionType ( ) ) { case <STR_LIT> : return true ; case <STR_LIT> : return ICmpType != <STR_LIT> ; case <STR_LIT> : return ICmpType !=


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget


<s> bool arm_output_addr_const_extra ( FILE * fp , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return arm_emit_tls_decoration ( fp , x ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_LABEL ) { char label [ <NUM_LIT> ] ; int labelno = INTVAL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; ASM_GENERATE_INTERNAL_LABEL ( label , <STR_LIT> , labelno ) ; assemble_name_raw ( fp , label ) ; return TRUE


<s> default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) == <STR_LIT> ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: Integer : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! CE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return


<s> return ( int64x2_t ) __builtin_neon_vpadalsv4si (


<s> return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; return vectorCostAdjustment ( Cost , Opcode , Ty


<s> if ( MI . getOpcode ( ) == FrameSetupOpcode ) { if ( TII -> getFrameSize ( MI ) >= StackProbeSize && UseStackProbe ) return false ; if ( InsideFrameSequence ) return false ; InsideFrameSequence = true ; } else if ( MI . getOpcode ( ) == FrameDestroyOpcode ) { if ( ! InsideFrameSequence ) return false ; InsideFrameSequence = false ; } } if ( InsideFrameSequence ) return false ; } return true


<s> const TargetRegisterClass * RC = nullptr ; switch ( RetVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned ResultReg = fastEmitInst_r ( Opc , RC ,


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return <NUM_LIT> ; switch ( rs6000_tune ) { case PROCESSOR_RS64A : case PROCESSOR_PPC601 : case PROCESSOR_PPC7450 : return <NUM_LIT> ; case PROCESSOR_PPC440 : case PROCESSOR_PPC603 : case PROCESSOR_PPC750 : case PROCESSOR_PPC7400 : case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : case PROCESSOR_CELL : case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case


<s> static char buf [ <NUM_LIT> ] ; bool useskip ; int nullify = INSN_ANNULLED_BRANCH_P ( insn ) ; int length = get_attr_length ( insn ) ; int xdelay ; if ( branch_to_delay_slot_p ( insn ) ) return <STR_LIT> ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> ) ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; useskip = ( length == <NUM_LIT> && nullify ) ? use_skip_p ( insn ) : FALSE ; switch ( length ) { case <NUM_LIT> : if ( useskip ) strcpy ( buf , <STR_LIT> ) ; else strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( useskip ) strcat ( buf , <STR_LIT> ) ; else if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else strcat ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p ( insn ) && nullify ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat (


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT>


<s> break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc

) , ResultReg ) . addReg ( Op1 ) . addReg ( Op2 ) ) ;


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , MRI ) ; assert ( TheTriple . isOSBinFormatELF (


<s> rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) ,


<s> ds [ i ] . vmode = V32HImode ; ds [ i ] . nelt = <NUM_LIT> ; ds [ i ] . target = gen_reg_rtx ( V32HImode ) ; ds [ i ] . op0 = gen_lowpart ( V32HImode , d -> op0 ) ; ds [ i ] . op1 = gen_lowpart ( V32HImode , d -> op1 ) ; } for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { ds [ i & <NUM_LIT> ] . perm [ i / <NUM_LIT> ] = d -> perm [ i ] / <NUM_LIT> ; if ( i & <NUM_LIT> ) { rperm [ i ] = constm1_rtx ; rperm [ i + <NUM_LIT> ] = GEN_INT ( ( i & <NUM_LIT> ) + ( d -> perm [ i ] & <NUM_LIT> ) ) ; } else { rperm [ i ] = GEN_INT ( ( i & <NUM_LIT> ) + ( d -> perm [ i ] & <NUM_LIT> ) ) ; rperm [ i + <NUM_LIT> ] = constm1_rtx ; } } bool ok = expand_vec_perm_1 ( & ds [ <NUM_LIT> ] ) ; gcc_assert ( ok ) ; ds [ <NUM_LIT> ] . target = gen_lowpart ( V64QImode , ds [ <NUM_LIT> ] . target ) ; ok = expand_vec_perm_1 ( & ds [ <NUM_LIT> ] ) ; gcc_assert ( ok ) ; ds [ <NUM_LIT> ] . target = gen_lowpart ( V64QImode ,


<s> else if ( CCMask != <STR_LIT> ) return false ; auto * TrueVal = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal ) return false ; auto * FalseVal = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! FalseVal ) return false ; if ( CompareRHS -> getZExtValue ( ) == FalseVal -> getZExtValue ( ) ) Invert = ! Invert ; else if ( CompareRHS -> getZExtValue ( ) != TrueVal -> getZExtValue ( ) ) return false ; auto * NewCCValid = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; auto * NewCCMask = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! NewCCValid || ! NewCCMask ) return false ; CCValid = NewCCValid -> getZExtValue ( ) ; CCMask = NewCCMask -> getZExtValue ( ) ; if ( Invert ) CCMask ^= CCValid ; CCReg = CompareLHS -> getOperand ( <NUM_LIT> ) ; return true ; } if ( CompareLHS -> getOpcode ( ) == <STR_LIT> ) { auto * SRACount = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! SRACount || SRACount -> getZExtValue ( ) != <NUM_LIT> ) return false ; auto * SHL = CompareLHS -> getOperand ( <NUM_LIT> )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS , bool is64Bit ) : PICStyle ( PICStyles :: None ) , <ISA_LIT>SSELevel ( NoMMXSSE ) , <ISA_LIT>3DNowLevel ( NoThreeDNow ) , Has<ISA_LIT>_64 ( false ) , HasSSE4A ( false ) , HasAVX ( false ) , HasFMA3 ( false ) , HasFMA4 ( false ) , IsBTMemSlow ( false ) , DarwinVers ( <NUM_LIT> ) , IsLinux ( false ) , stackAlignment ( <NUM_LIT> ) , MaxInlineSizeThreshold ( <NUM_LIT> ) , Is64Bit ( is64Bit ) , TargetType ( isELF ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Hard ; if ( ! FS . empty ( ) ) { std :: string CPU = GetCurrent<ISA_LIT>CPU ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; } else { AutoDetectSubtargetFeatures ( ) ; if ( Is64Bit && <ISA_LIT>SSELevel < SSE2 ) <ISA_LIT>SSELevel = SSE2 ; } if ( Is64Bit ) Has<ISA_LIT>_64 = true ; DEBUG ( errs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! Is64Bit || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( TT . length ( ) > <NUM_LIT> ) { size_t Pos ; if ( ( Pos = TT . find ( <STR_LIT> ) ) != std :: string :: npos ) { TargetType = isDarwin ; if ( isdigit ( TT [ Pos + <NUM_LIT> ] ) ) DarwinVers = atoi ( & TT [ Pos + <NUM_LIT> ] ) ; else DarwinVers = <NUM_LIT> ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isELF ; IsLinux = true ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isCygwin ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isMingw


<s> static bool MorphToI32Reg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx > <NUM_LIT> ) return


<s> <ISA_LIT>LinuxMCAsmInfo :: <ISA_LIT>LinuxMCAsmInfo ( bool is64Bit ) { AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; if ( ! is64Bit ) ExceptionsType = ExceptionHandling :: Dwarf ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : <NUM_LIT> ; HasLCOMMDirective = true


<s> } unsigned NumArgs = CLI . OutVals . size ( ) ; if ( NumArgs > <NUM_LIT> ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( NumArgs ) ; ArgRegs . reserve ( NumArgs ) ; ArgVTs . reserve ( NumArgs ) ; ArgFlags . reserve ( NumArgs ) ; for ( unsigned i = <NUM_LIT> , ie = NumArgs ; i != ie ; ++ i ) { <STR_LIT> Flags = CLI . OutFlags [ i ] ; if ( Flags . isInReg ( ) || Flags . isSRet ( ) || Flags . isNest ( ) || Flags . isByVal ( ) ) return false ; Value * ArgValue = CLI . OutVals [ i ] ; Type * ArgTy = ArgValue -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) ) return false ; unsigned Arg = getRegForValue ( ArgValue ) ; if ( Arg == <NUM_LIT> ) return false ; Args . push_back ( ArgValue ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; MachineInstrBuilder MIB ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) { if ( CLI . IsPatchPoint ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; else return false ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; } for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB . addReg ( RegArgs [ II ] , RegState :: Implicit ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( *


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * BBI << <STR_LIT> ) ; } for ( auto AfterBBI = std :: next ( BBI ) ; AfterBBI != MBB . instr_end ( ) ; ++ AfterBBI ) { int KillIdx = AfterBBI -> findRegisterUseOperandIdx ( Reg , true , TRI ) ; if ( KillIdx != - <NUM_LIT> ) { assert ( ! DeadOrKillToUnset && <STR_LIT> ) ; DeadOrKillToUnset = & AfterBBI -> getOperand ( KillIdx ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; } if ( ! AfterBBI -> modifiesRegister ( Reg , TRI ) ) continue ; assert ( DeadOrKillToUnset && <STR_LIT> ) ; if ( AfterBBI -> getOpcode ( ) != Opc ) break ; assert ( AfterBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( ! AfterBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) || AfterBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != Imm ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> <<

* DeadOrKillToUnset -> getParent ( ) ) ;


<s> if ( Reg . Num == <NUM_LIT> && IsAddress ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Regs ) Reg . Num = Regs [ Reg . Num ] ; return false


<s> void MVETailPredication :: InsertVCTPIntrinsic ( TripCountPattern & TCP , DenseMap < Instruction * , Instruction * > & NewPredicates ) { IRBuilder < > Builder ( L -> getHeader ( ) -> getFirstNonPHI ( ) ) ; Module * M = L -> getHeader ( ) -> getModule ( ) ; Type * Ty = IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) ; PHINode * Processed = Builder . CreatePHI ( Ty , <NUM_LIT> ) ; Processed -> addIncoming ( TCP . NumElements , L -> getLoopPreheader ( ) ) ; Builder . SetInsertPoint ( cast < Instruction > ( TCP . Predicate ) ) ; ConstantInt * Factor = ConstantInt :: get ( cast < IntegerType > ( Ty ) , TCP . VecTy -> getNumElements ( ) ) ; <STR_LIT> VCTPID ; switch ( TCP . VecTy -> getNumElements ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; case <NUM_LIT> : VCTPID = <STR_LIT> ; break ; } Function * VCTP = <STR_LIT> ( M , VCTPID ) ; Value * TailPredicate = Builder . CreateCall ( VCTP , Processed ) ; TCP . Predicate -> replaceAllUsesWith


<s> for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) emit_insn ( gen_rtx_SET ( st_reg , CONST0_RTX ( XFmode ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) { rtx insn ; insn = emit_insn ( gen_rtx_SET ( st_reg , st_reg ) ) ; add_reg_note ( insn , REG_DEAD , st_reg ) ; } return


<s> if ( IsFalseBlockRequired ) { FalseBlock = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , FalseBlock ) ; } if ( IsTrueBlockRequired ) { TrueBlock = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBlock ) ; } if ( NewSuccessor ) { MF -> insert ( It , NewSuccessor ) ; NewSuccessor -> splice ( NewSuccessor -> end ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( BIL . back ( ) ) ) , MBB -> end ( ) ) ; NewSuccessor -> transferSuccessorsAndUpdatePHIs ( MBB ) ; for ( auto & LI : MBB -> liveins ( ) ) NewSuccessor -> addLiveIn ( LI ) ; LivePhysRegs LPR ( * MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( MachineInstr & MI : * MBB ) LPR . stepForward ( MI , Clobbers ) ; for ( auto & LI : LPR ) NewSuccessor -> addLiveIn ( LI ) ; } else { MBB -> removeSuccessor ( Successor ) ; } MBB -> addSuccessor ( IsTrueBlockRequired ? TrueBlock : Successor ) ; MBB -> addSuccessor ( IsFalseBlockRequired ? FalseBlock : Successor ) ; if ( IsTrueBlockRequired ) { TrueBlockI = TrueBlock -> begin ( ) ; TrueBlock -> addSuccessor ( Successor ) ; } if ( IsFalseBlockRequired ) { FalseBlockI = FalseBlock ->


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( ) . hasStackAlignmentAttr ( ) ) ; if ( ForceStackAlign ) return canRealignStack ( MF ) ; return requiresRealignment && canRealignStack ( MF


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT ,


<s> uint8_t <STR_LIT> ( ) { if ( FpABI == FpABIKind :: XX )


<s> default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> initializeCookieSetterPass ( * PassRegistry :: getPassRegistry (


<s> return __builtin_loongson_pmovmskb_s (


<s> NEQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } unsigned Opc = <NUM_LIT> , EQOpc = <NUM_LIT> , GTOpc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = EQOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; Invert = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; FlipSigns = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; FlipSigns = true ; Invert = true ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( FlipSigns )


<s> TargetLoweringObjectFile * getObjFileLowering (


<s> if ( ImmMask != <NUM_LIT> && ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false


<s> return SelectAddrModeIndexed7S ( N , <NUM_LIT>


<s> gimple * fold_type ( gimple_folder & f ) const { T arg0 , arg1 ; if ( ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg0 ) || ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg1 ) ) return NULL ; if ( m_eq_p ? known_gt ( arg0 , arg1 ) : known_ge ( arg0 , arg1 ) ) return f . fold_to_pfalse ( ) ; if ( m_eq_p ? maybe_gt ( arg0 , arg1 ) : maybe_ge ( arg0 , arg1 ) ) return NULL ; poly_uint64 diff = arg1 - arg0 ; poly_uint64 nelts = GET_MODE_NUNITS ( f . vector_mode ( <NUM_LIT> ) ) ; if ( m_eq_p )


<s> bool <ISA_LIT>TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SelectionDAG & DAG ) const { if ( ! getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG .


<s> SDValue Const1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Const31 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Res ; SDValue X = ( TyX == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; SDValue Y = ( TyY == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) { SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , Const31 , Const1 , X ) ; } else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; SDValue SrlX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; SDValue SrlY = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 ) ; SDValue SllY = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SrlY ,


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>leTarget ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y


<s> return MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA : return MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGH : return MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHA : return MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA : return MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER : return MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; case <ISA_LIT>MCExpr ::


<s> bool <ISA_LIT>BaseInstrInfo :: isAddrMode3OpMinusReg ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & Offset = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; assert ( Opc . isImm ( ) ) ; assert ( Offset . isReg ( ) ) ; int64_t OpcImm = Opc . getImm ( ) ; bool isSub = <STR_LIT> ( OpcImm ) == <STR_LIT> ; return ( isSub && Offset . getReg ( )


<s> for ( Value * V : Defs ) if ( ! isa < PHINode > ( V ) && ! isa < Constant > ( V ) && ! isa < Argument > ( V ) && ! isa < CallInst > ( V ) ) return false ; for ( Value * V : Defs ) if ( const PHINode * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { User * First = dyn_cast < User > ( Pair .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getMGatherNode ( Opc , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getScatterNode ( Opc , Op , DAG , Src , Base , Index , Scale , Chain ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> if ( Ty -> isVectorTy ( ) && AM . BaseOffs != <NUM_LIT> && ! Subtarget . hasP9Vector ( ) ) return false ; if ( AM . BaseOffs <= - ( <NUM_LIT> << <NUM_LIT> ) || AM . BaseOffs >= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return false ; if ( AM . BaseGV ) return false ; switch ( AM .


<s> assert ( NOps == <NUM_LIT> ) ; O << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; O << V . getName ( ) ; O << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this , Subtarget . isDarwin (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> rs6000_function_arg_advance_1 ( get_cumulative_args ( cum ) , mode , type , named


<s> return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) !=

<STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> else { assert ( ! isPatchPoint && <STR_LIT> ) ; if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { const MCRegister StackPtrReg = Subtarget . getStackPointerRegister ( ) ; SDValue StackPtr = DAG . getRegister ( StackPtrReg , RegVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , StackPtr , TOCOff ) ; Ops . push_back ( AddTOC ) ; } if ( Subtarget . usesFunctionDescriptors ( ) && ! hasNest ) Ops . push_back ( DAG . getRegister ( Subtarget . getEnvironmentPointerRegister ( ) , RegVT ) ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ,


<s> if ( I -> isDebugInstr ( ) || MemOps . count ( & * I ) ) continue ; if ( I -> isCall ( ) || I -> isTerminator ( ) || I -> hasUnmodeledSideEffects ( ) ) return false ; if ( I -> mayStore ( ) || ( ! isLd && I -> mayLoad ( ) ) ) for ( MachineInstr * MemOp : MemOps ) if ( I -> mayAlias ( AA , * MemOp , false ) ) return false ; for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ; if ( Reg != Base && ! MemRegs . count ( Reg ) ) AddedRegPressure . insert ( Reg ) ; } } if ( MemRegs . size ( )


<s> if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op , DAG ) ; if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op , DAG ) ; llvm_unreachable ( <STR_LIT> )


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeList Attrs = MF . getFunction ( )


<s> return MBB . isEHPad ( ) || MBB . hasAddressTaken ( ) || & MBB == & MBB . getParent ( )


<s> unsigned OpMaskSizeLog2 = countTrailingZeros ( OpMask . size ( ) ) ; unsigned MaskWidth = std :: max < unsigned > ( OpMask . size ( ) , RootMask . size ( ) ) ; unsigned RootRatio = std :: max < unsigned > ( <NUM_LIT> , OpMask . size ( ) >> RootMaskSizeLog2 ) ; unsigned OpRatio = std :: max < unsigned > ( <NUM_LIT> , RootMask . size ( ) >> OpMaskSizeLog2 ) ; assert ( ( RootRatio == <NUM_LIT> || OpRatio == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( MaskWidth ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootRatio ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpRatio ) && <STR_LIT> ) ; unsigned RootRatioLog2 = countTrailingZeros ( RootRatio ) ; unsigned OpRatioLog2 = countTrailingZeros ( OpRatio ) ; SmallVector < int , <NUM_LIT> > Mask ( MaskWidth , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i < MaskWidth ; ++ i ) { unsigned RootIdx = i >> RootRatioLog2 ; if ( RootMask [ RootIdx ] < <NUM_LIT> ) { Mask [ i ] = RootMask [ RootIdx ] ; continue ; } unsigned RootMaskedIdx = RootRatio == <NUM_LIT> ? RootMask [ RootIdx ] : ( RootMask [ RootIdx ] << RootRatioLog2 ) + ( i & ( RootRatio - <NUM_LIT> ) ) ; if ( ( RootMaskedIdx < ( SrcOpIndex * MaskWidth ) ) || ( ( ( SrcOpIndex + <NUM_LIT> ) * MaskWidth ) <= RootMaskedIdx ) ) { Mask [ i ] = RootMaskedIdx ; continue ; } RootMaskedIdx = RootMaskedIdx & ( MaskWidth - <NUM_LIT> ) ; unsigned OpIdx = RootMaskedIdx >> OpRatioLog2 ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) { Mask [ i ] = OpMask [ OpIdx ] ; continue ; } unsigned OpMaskedIdx = OpRatio == <NUM_LIT> ? OpMask [ OpIdx ] : ( OpMask [ OpIdx ] << OpRatioLog2 ) + ( RootMaskedIdx & ( OpRatio - <NUM_LIT> ) ) ; OpMaskedIdx = OpMaskedIdx & ( MaskWidth - <NUM_LIT> ) ; int InputIdx = OpMask [ OpIdx ] / ( int ) OpMask . size ( ) ; assert ( <NUM_LIT> <= OpInputIdx [ InputIdx ] && <STR_LIT> ) ; OpMaskedIdx += OpInputIdx [ InputIdx ] * MaskWidth ; Mask [ i ]


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp ) { InstructionCost CostFactor = vectorCostAdjustmentFactor ( Instruction :: ShuffleVector , Tp , nullptr ) ; if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; return LT . first


<s> if ( ! Register :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr & DefMI = * MRI -> getVRegDef ( Reg


<s> if ( GET_CODE ( pattern ) == PARALLEL ) pattern = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; switch ( GET_CODE ( pattern ) ) { case SET : if ( GET_CODE ( SET_SRC ( pattern ) ) != CALL && get_attr_type ( insn ) != TYPE_SFUNC ) { targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( note , <NUM_LIT> ) ) ) ; break ; } case CALL : asm_fprintf ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( note , <NUM_LIT> ) ) ) ; break ; default : gcc_unreachable ( )


<s> static bool hasNonRISpills ( const MachineFunction & MF ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return FuncInfo ->


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> void buildLoad ( unsigned Val , const CCValAssign & VA ) { MachineMemOperand * MMO ; unsigned Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr , *


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X


<s> if ( ! Subtarget . isUsingPCRelativeCalls ( ) ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) std :: swap ( LHS , RHS ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; GlobalAddressSDNode * GSDN = dyn_cast < GlobalAddressSDNode > ( LHS . getOperand (


<s> fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } if ( ! TARGET_SVE ) for ( i = P0_REGNUM ; i <= P15_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } CLEAR_HARD_REG_BIT ( operand_reg_set ,


<s> int <ISA_LIT>ConstantPoolMBB :: getExistingMachineCPValue ( MachineConstantPool *


<s> return <STR_LIT> ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= <NUM_LIT> && !

Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) {


<s> return ( Candidate . isTerminator ( ) || Candidate . isCall ( ) || Candidate . isPosition ( ) || Candidate . isInlineAsm ( ) ||

Candidate . hasUnmodeledSideEffects ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printCPInstOperand ( const MCInst * MI , unsigned OpNum , const


<s> if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; bool IsWinEH = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int Offset ; if ( IsWinEH ) Offset = TFI -> getFrameIndexOffsetFromSP ( MF , FrameIndex ) ; else Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc


<s> bool isTargetDragonFly ( ) const { return TargetTriple . isOSDragonFly (


<s> else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ; if ( TheTriple . isOSDarwin ( ) ) RM = Reloc :: PIC_ ; else if ( RM == Reloc :: Default || RM == Reloc :: DynamicNoPIC ) RM = Reloc :: Static ; MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCondCode ( <STR_LIT> Code , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_CondCode ) ; Op -> CondCode . Code = Code ; Op -> StartLoc = S ; Op -> EndLoc


<s> assert ( Fixup . getOffset ( ) + Size <= DataSize && <STR_LIT> ) ; assert ( isIntN ( Size * <NUM_LIT> + <NUM_LIT> ,


<s> return true ; } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == nullptr && Subtarget -> isTargetLinux ( ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) { case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ; case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ; } return true


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < <STR_LIT> , <NUM_LIT> > & Outs = CLI . Outs ; SmallVector < SDValue , <NUM_LIT> > & OutVals = CLI . OutVals ; SmallVector < <STR_LIT> , <NUM_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false ; switch (


<s> R2MTable [ RegOp ] = std :: make_pair ( MemOp , Flags ) ; } if ( ( Flags & TB_NO_REVERSE ) == <NUM_LIT> ) { assert ( ! M2RTable . count ( MemOp ) && <STR_LIT>


<s> bool hasVFP3Base ( ) const { return hasVFPv3D16SP (


<s> TrapInfo TI = cast < GlobalAddressSDNode > ( Op ) -> getTrapInfo ( ) ; return LowerGlobalAddress ( GV , SDLoc ( Op ) , Offset , TI ,


<s> for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = Use -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Defs . count ( Reg ) ) return


<s> bool <ISA_LIT>NaClRewritePass :: ApplyStackSFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { TraceLog ( <STR_LIT> , MBB , MBBI ) ; assert ( Is64Bit ) ; MachineInstr & MI = * MBBI ; if ( ! IsStackChange ( MI , TRI ) ) return false ; if ( IsPushPop ( MI ) ) return false ; if ( MI . getDesc ( ) . isCall ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> || DestReg == <STR_LIT> ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; } assert ( Opc != <STR_LIT> &&


<s> if ( ! Subtarget . has<ISA_LIT>64 ( ) ) PM

. add ( create<ISA_LIT>EmitGPRestorePass ( * this ) ) ;


<s> const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; if ( ! IsZExt ) { Op0 = emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; if ( ! Op0 ) return <NUM_LIT> ; Op0IsKill = true ; SrcVT = RetVT ; SrcBits = SrcVT . getSizeInBits ( ) ; IsZExt = true ; } unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> ,


<s> if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) -


<s> emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } if ( NumBytes ) { const bool NeedsRealignment = RegInfo -> needsStackRealignment ( MF ) ; unsigned scratchSPReg = <STR_LIT> ; if ( NeedsRealignment ) { scratchSPReg = findScratchNonCalleeSaveRegister ( & MBB ) ; assert ( scratchSPReg != <STR_LIT> ) ; } if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , scratchSPReg , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; if ( NeedsRealignment ) { const unsigned Alignment = MFI . getMaxAlignment ( ) ; const unsigned NrBitsToZero = countTrailingZeros ( Alignment ) ; assert ( NrBitsToZero > <NUM_LIT> ) ; assert ( scratchSPReg != <STR_LIT> ) ; uint32_t andMaskEncoded = ( <NUM_LIT> << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero ) << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero - <NUM_LIT> ) << <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( scratchSPReg , RegState :: Kill ) . addImm ( andMaskEncoded ) ; AFI -> setStackRealigned ( true ) ; } } if ( RegInfo -> hasBasePointer ( MF ) ) { TII -> copyPhysReg ( MBB , MBBI , DL , RegInfo -> getBaseRegister ( ) , <STR_LIT> , false ) ; } if ( needsFrameMoves ) { const DataLayout & TD = MF . getDataLayout ( ) ; const int StackGrowth = - TD . getPointerSize ( <NUM_LIT> ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( HasFP ) { unsigned Reg = RegInfo -> getDwarfRegNum ( FramePtr


<s> if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) { PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> * RepeatedMask [ i ] ; PSHUFDMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * RepeatedMask [ i ] + <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DAG ) ) ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; } if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> ,

DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName


int __A , int __B , int __C , int __D ) {


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; int64_t Imm ; if ( ( VT != <STR_LIT> ) && CI -> isNegative (


<s> if ( Reg . Group != RegV && Reg . Group != RegFP ) { Error ( Reg . StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } break ; } } else if ( Parser . getTok ( ) . is ( AsmToken :: Integer ) ) { if ( parseIntegerRegister ( Reg , Group ) ) return MatchOperand_ParseFail ; } else return MatchOperand_NoMatch ; const unsigned * Regs ; switch ( Kind ) { case GR32Reg : Regs = <STR_LIT> ; break ; case GRH32Reg : Regs = <STR_LIT> ; break ; case GR64Reg : Regs = <STR_LIT> ; break ; case GR128Reg : Regs = <STR_LIT> ; break ; case FP32Reg : Regs = <STR_LIT> ; break ; case FP64Reg : Regs = <STR_LIT>


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB (


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperandsRI ( const <ISA_LIT>RRIAddressMode & AM , SDValue & Base , SDValue & Disp ) { if ( AM . BaseType == <STR_LIT> ) Base


<s> const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( <NUM_LIT>


<s> if ( target == NULL_RTX ) return NULL_RTX ; if ( ! REG_P ( target ) ) target = force_reg ( SImode , target ) ; emit_insn ( gen_mvfc ( target , arg ) ) ; return target


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++


<s> gcc_assert ( REG_P ( last_def_reg ) || GET_CODE ( last_def_reg ) == SUBREG ) ; return e8_consumed_by_addr_in_p ( consumer , last_def_reg


<s> static bool is<ISA_LIT>_64ExtendedReg ( const MachineOperand & MO ) { if ( ! MO . isReg


<s> if ( Op . getValueSizeInBits ( ) > <NUM_LIT> && Subtarget . isSingleFloat ( ) ) return SDValue ( ) ; EVT FPTy = EVT :: getFloatingPointVT ( Op . getValueSizeInBits (


<s> const MDNodeSDNode * MD = dyn_cast < MDNodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const MDString * RegString = dyn_cast < MDString > ( MD -> getMD ( ) -> getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; int Reg = getIntOperandFromRegisterString ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } <STR_LIT> PMapper ; bool IsValidSpecialReg ; Reg = PMapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) { assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; uint64_t Immed = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned State ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } else { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } ReplaceNode ( N , CurDAG -> getMachineNode ( State , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( Immed , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } <STR_LIT> Mapper ; Reg = Mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg


<s> MachineInstrBuilder MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; ++ NumCopiesInserted


<s> if ( ! SubIdx ) return MIB . addReg ( Reg , State ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return MIB . addReg (

TRI -> getSubReg ( Reg , SubIdx ) , State ) ;


<s> case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI .


<s> if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ; return SDValue (


<s> SDLoc DL ( SplatValue ) ; if ( VecTy == <STR_LIT> ) { ViaVecTy = <STR_LIT> ; SplatValueA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatValue , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SplatValueB = DAG . getNode ( <STR_LIT> , DL


<s> SDLoc dl ( Op ) ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue ARMcc ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , dl , DAG ) ; SDValue CCVal = DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue FalseValLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueValLo = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , TrueValLo , FalseValLo , CCVal , Cmp ) ; SDValue FalseValHi = DAG . getNode ( Opc , dl


<s> return __builtin_ia32_aesdec128kl_u8 ( ( __v2di * ) __A , ( __v2di


<s> static SDValue LowerDIV ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT != <STR_LIT> ) && ( VT != <STR_LIT> ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; bool isSigned = Op . getOpcode ( ) == <STR_LIT> ; unsigned ExtHiOpc = isSigned ? <STR_LIT> : <STR_LIT> ; unsigned ExtLoOpc = isSigned ? <STR_LIT> : <STR_LIT> ; unsigned MaxFactor = VT . getVectorNumElements ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Res ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op0 ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op1 ( MaxFactor ) ; unsigned Factors = <NUM_LIT> ; Op0 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; Op1 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; for ( ; Factors < MaxFactor ; Factors *= <NUM_LIT> ) { VT = getDoubleWidthHalfCountVectorVT ( DAG , VT ) ; for ( unsigned i = Factors ; i > <NUM_LIT> ; -- i ) { Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtLoOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op1 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op1 [


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isImm ( ) ) return addImmOperands ( Inst , N ) ; Inst . addOperand ( MCOperand :: createImm ( ModImm . Bits | ( ModImm .


<s> MCObjectWriter * llvm :: create<ISA_LIT>WinCOFFObjectWriter ( raw_ostream & OS , bool Is64Bit ) { MCWinCOFFObjectTargetWriter * MOTW = new


<s> if ( ! Mask ) Mask = CDAG . getConstantMask ( Packing , true ) ; assert ( LegalVecVT . isSimple ( ) ) ; if ( isVVPUnaryOp ( VVPOpcode ) ) return CDAG . getNode ( VVPOpcode , LegalVecVT , { Op -> getOperand ( <NUM_LIT> ) , Mask , AVL } ) ; if ( isVVPBinaryOp ( VVPOpcode ) ) return CDAG . getNode ( VVPOpcode , LegalVecVT , { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Mask , AVL } ) ; if ( isVVPReductionOp ( VVPOpcode ) ) { auto SrcHasStart = hasReductionStartParam ( Op -> getOpcode ( ) ) ; SDValue StartV = SrcHasStart ? Op -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue VectorV = Op -> getOperand ( SrcHasStart ? <NUM_LIT> : <NUM_LIT> ) ; return CDAG . getLegalReductionOpVVP ( VVPOpcode , Op . getValueType ( ) , StartV , VectorV , Mask , AVL , Op -> getFlags ( ) ) ; } switch ( VVPOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { auto X = Op -> getOperand ( <NUM_LIT> ) ; auto Y = Op -> getOperand ( <NUM_LIT> ) ; auto Z = Op -> getOperand ( <NUM_LIT> ) ; return CDAG . getNode ( VVPOpcode , LegalVecVT , { X , Y , Z , Mask , AVL } ) ; } case <STR_LIT> : { auto Mask = Op -> getOperand ( <NUM_LIT> ) ; auto OnTrue = Op -> getOperand ( <NUM_LIT> ) ; auto OnFalse = Op -> getOperand ( <NUM_LIT> ) ; return CDAG . getNode ( VVPOpcode , LegalVecVT , { OnTrue , OnFalse , Mask


<s> if ( <NUM_LIT> ) { } else { SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue PackedElt = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { Vec , HalfIdx } ) , <NUM_LIT> ) ; SDValue AndIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { AndIdx , Const1 } ) ; SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Mask , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Val ,


<s> return ( uint16x8_t ) __builtin_aarch64_uhaddv8hi ( ( int16x8_t ) __a , ( int16x8_t )