<s> if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( isUnsupportedFloatingType ( VT ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHClearUnwoundToCall ( SMLoc L


<s> return ( uint32x4_t ) __builtin_neon_vclzv4si ( (


<s> case GTU : fputs ( <STR_LIT> , file ) ; break ; case GEU : fputs ( <STR_LIT> , file ) ; break ; case LTU : fputs ( <STR_LIT> , file ) ; break ; case LEU : fputs ( <STR_LIT> , file ) ; break ; default : abort_with_insn ( op , <STR_LIT> ) ; } else if ( letter == 'F' ) switch ( code ) { case EQ : fputs ( <STR_LIT> , file ) ; break ; case NE : fputs ( <STR_LIT> , file ) ; break ; default : abort_with_insn ( op , <STR_LIT> ) ; } else if ( letter == 'W' ) switch ( code ) { case EQ : fputs ( <STR_LIT> , file ) ; break ; case NE : fputs ( <STR_LIT> , file ) ; break ; default : abort_with_insn ( op , <STR_LIT> ) ; } else if ( letter == 'A' ) fputs ( code == LABEL_REF ? <STR_LIT> : <STR_LIT> , file ) ; else if ( letter == 'P' ) { if ( code == LABEL_REF ) output_addr_const ( file , op ) ; else if ( code != PC ) output_operand_lossage ( <STR_LIT> ) ; } else if ( letter == 'p' ) { int value ; if ( code != CONST_INT || ( value = exact_log2 ( INTVAL ( op ) ) ) < <NUM_LIT> ) output_operand_lossage ( <STR_LIT> ) ; else fprintf ( file , <STR_LIT> , value ) ; } else if ( letter == 'Z' ) { gcc_unreachable ( ) ; } else if ( code == REG || code == SUBREG ) { int regnum ; if ( code == REG ) regnum = REGNO ( op ) ; else regnum = true_regnum ( op ) ; if ( ( letter == 'M' && ! WORDS_BIG_ENDIAN ) || ( letter == 'L' && WORDS_BIG_ENDIAN ) || letter == 'D' ) regnum ++ ; fprintf ( file , <STR_LIT> , reg_names [ regnum ] ) ; } else if ( code == MEM ) { if ( letter == 'D' ) output_address ( plus_constant ( Pmode , XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; else output_address ( XEXP ( op , <NUM_LIT> ) ) ; } else if ( code == CONST_DOUBLE && GET_MODE_CLASS ( GET_MODE ( op ) ) == MODE_FLOAT ) { char s [


<s> void mips_output_aligned_decl_common ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ( DECL_INITIAL ( decl ) == <NUM_LIT> || DECL_INITIAL ( decl ) == error_mark_node ) ) { if ( TREE_PUBLIC ( decl ) && DECL_NAME ( decl ) ) targetm . asm_out . globalize_label ( stream , name ) ; switch_to_section (


<s> bool ExpandPseudo :: expandCopy ( MachineBasicBlock & MBB , Iter I ) { Register Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; std :: pair < unsigned , unsigned >


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> is<ISA_LIT>64 ( ) && Subtarget -> isSVR4ABI ( ) ) return new <ISA_LIT>FastISel ( FuncInfo , LibInfo ) ; return <NUM_LIT>


<s> SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue Flags ; Flags = checkBoolTestSetCCCombine ( EFLAGS , CC ) ; if ( Flags . getNode ( ) ) { SDValue Cond = DAG . getConstant ( CC , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Chain , Dest , Cond , Flags ) ; } return SDValue


<s> return ( __m256i ) __builtin_ia32_pmovqd512_mask ( ( __v8di ) __A , ( __v8si )


<s> llvm :: FunctionPass * llvm :: create<ISA_LIT>ModuleISelDagPass ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>ModuleDAGToDAGISel


<s> <ISA_LIT>Relocator :: Result tls ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { return Relocator :: Unsupported


<s> if ( ! PSB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePSBHint ( PSB -> Encoding , Tok . getString ( ) , S


<s> bool hasByvalArg ( ) const { return HasByvalArg


<s> if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( Index == <NUM_LIT> )


<s> getTargetStreamer ( ) . EmitARM64WinCFINop ( )


<s> return has_func_attr ( decl , <STR_LIT>


<s> return ( unsigned int ) __builtin_ia32_kmovw ( ( __mmask16 ) __A


<s> Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str .


<s> if ( TREE_CODE ( arg . type ) == VECTOR_TYPE && int_size_in_bytes ( arg . type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_pass_big_vectors = false ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; if ( ! warned_for_pass_big_vectors ) { warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> <STR_LIT> ) ; warned_for_pass_big_vectors = true ; } return <NUM_LIT>


<s> if ( * CM != CodeModel :: Small && * CM != CodeModel :: Tiny && * CM != CodeModel :: Large ) { if ( ! TT . isOSFuchsia ( ) ) report_fatal_error ( <STR_LIT> ) ; else if ( * CM != CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else if ( * CM == CodeModel :: Tiny && ! TT . isOSBinFormatELF ( ) ) report_fatal_error ( <STR_LIT> ) ; return * CM ; } if ( JIT ) return CodeModel :: Large ; return CodeModel ::


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand

( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> return isRegIdx ( ) && RegIdx . Kind & RegKind_CheriHWRegs &&


<s> if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ; return hasMVEIntegerOps (


<s> return __builtin_mve_vldrhq_z_sv4si ( ( __builtin_neon_hi *


<s> void printi128mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo ,


<s> for ( ; i != MBB -> end ( ) ; ++ i ) { if ( MI . isIdenticalTo ( * i ) ) break ; } return


<s> scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ; verify ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << '\n' ;


<s> return ( __m128d ) __builtin_ia32_vfmaddsd3_maskz ( ( __v2df ) __W , ( __v2df ) __A , - (


<s> static tree get_prev_label ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return NULL_TREE


<s> <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) MBB


<s> SDValue <ISA_LIT>TargetLowering :: getReturnAddressFrameIndex ( SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ,


<s> bool <ISA_LIT>TargetLowering :: lowerInterleavedLoad ( LoadInst * LI , ArrayRef < ShuffleVectorInst * > Shuffles , ArrayRef < unsigned > Indices , unsigned Factor ) const { assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * EltTy = VecTy -> getVectorElementType ( ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; unsigned VecSize = DL . getTypeAllocSizeInBits ( VecTy ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( VecSize != <NUM_LIT> && VecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; IRBuilder < > Builder ( LI ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( LI -> getPointerOperand ( ) , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [


<s> virtual MVT getScalarShiftAmountTy ( EVT


<s> return ( __m64 ) ( ( __v2du ) vec_abs


<s> SDLoc DL ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue Symbol = withTargetFlags ( Op , callTF ,


<s> extern __inline __m256 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i32gather_ps ( __m256 src , float const * base , __m256i index , __m256 mask , const int scale ) { return ( __m256 ) __builtin_ia32_gathersiv8sf ( ( __v8sf ) src , base ,

( __v8si ) index , ( __v8sf ) mask , scale ) ;


<s> if ( fndecl != NULL_TREE && TREE_CODE ( fndecl ) == FUNCTION_DECL ) call_abi = ix86_function_abi ( fndecl ) ; else call_abi = ix86_function_type_abi ( fndecl ) ; if ( TARGET_64BIT && call_abi == MS_ABI


<s> assert ( StartIdx == StartIdx2 && <STR_LIT> ) ; } unsigned ScratchIdx = StartIdx , e = MI . getNumOperands ( ) ; while ( ScratchIdx < e && ! ( MI . getOperand ( ScratchIdx ) . isReg ( ) && MI . getOperand ( ScratchIdx ) . isDef ( ) && MI . getOperand ( ScratchIdx ) . isImplicit ( ) && MI . getOperand ( ScratchIdx ) . isEarlyClobber ( ) ) ) ++ ScratchIdx ; assert ( ScratchIdx != e && <STR_LIT> ) ; int64_t ID = MI . getOperand ( StartIdx ) . getImm ( ) ; assert ( ( int32_t ) ID == ID && <STR_LIT> ) ; bool isAnyRegCC = MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) == CallingConv :: AnyReg ; assert ( ( ( hasDef && isAnyRegCC ) || ! hasDef ) && <STR_LIT> ) ; int64_t StackMapIdx = isAnyRegCC ? StartIdx + <NUM_LIT> : StartIdx + <NUM_LIT> + MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) ; assert ( StackMapIdx <= MI . getNumOperands ( ) && <STR_LIT> ) ; SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , StackMapIdx ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end ( ) ) , isAnyRegCC && hasDef ) ; unsigned EncodedBytes = <NUM_LIT> ; int64_t CallTarget = MI . getOperand ( StartIdx


<s> static bool WindowsRequiresStackProbe ( const MachineFunction & MF , size_t StackSizeInBytes ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackProbeSize = ( MFI -> getStackProtectorIndex ( ) > <NUM_LIT> ) ?


<s> static tree mep_validate_interrupt ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add ) { tree function_type ; if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( <NUM_LIT> , <STR_LIT> , name ) ; * no_add = true ; return NULL_TREE ; } if ( DECL_DECLARED_INLINE_P ( * node ) ) error ( <STR_LIT> , DECL_NAME ( * node ) ) ; DECL_UNINLINABLE ( * node ) = <NUM_LIT> ; function_type = TREE_TYPE ( * node ) ; if ( TREE_TYPE ( function_type ) != void_type_node ) error ( <STR_LIT> ) ; if ( prototype_p ( function_type ) && ( TREE_VALUE ( TYPE_ARG_TYPES ( function_type ) ) != void_type_node || TREE_CHAIN ( TYPE_ARG_TYPES ( function_type ) ) != NULL_TREE ) ) error ( <STR_LIT> ) ; return NULL_TREE


<s> int16_t i [ <NUM_LIT> ] ; } u ; u . v = a


<s> int32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> MCCFIInstruction llvm :: createDefCFA ( const TargetRegisterInfo & TRI , unsigned FrameReg , unsigned Reg , const StackOffset & Offset , bool LastAdjustmentWasScalable ) { if ( Offset . getScalable ( ) ) return createDefCFAExpression ( TRI , Reg , Offset ) ; if ( FrameReg == Reg && ! LastAdjustmentWasScalable ) return MCCFIInstruction :: cfiDefCfaOffset ( nullptr , int ( Offset . getFixed ( ) ) ) ; unsigned DwarfReg = TRI . getDwarfRegNum ( Reg


<s> static const char * getIndirectThunkSymbol ( const <ISA_LIT>Subtarget & Subtarget , unsigned Reg ) { if ( Subtarget . useRetpolineExternalThunk ( ) ) { switch ( Reg ) { case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex


<s> MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator It = ++ MBB -> getIterator ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IfTrueReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IfFalseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool NZCVKilled = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB


<s> const BitVector & getSpilledCSRegisters (


<s> void AnalyzeReturn ( const SmallVectorImpl < <STR_LIT> > & Outs


<s> addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( )


<s> LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , dl , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getSrcValue ( ) , LDBase -> getSrcValueOffset ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , dl , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getSrcValue ( ) , LDBase -> getSrcValueOffset ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ResNode ) ; } return SDValue


<s> SDValue <ISA_LIT>cc ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl ,


<s> if ( REG_P ( def_reg ) ) { return rtx_equal_p ( def_reg , use_rtx ) ; } else if ( GET_CODE ( def_reg ) == SUBREG && GET_MODE ( def_reg ) == SImode && rtx_equal_p ( SUBREG_REG ( def_reg ) , use_rtx ) ) { if ( TARGET_BIG_ENDIAN && SUBREG_BYTE ( def_reg ) ==


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( ( CE -> getValue (


<s> } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XVECEXP

( tocrel_base_oac , <NUM_LIT> , <NUM_LIT> ) ) ] ) ;


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; bool IsNakedFunction = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; TS . emitDirectiveSetNoReorder (


<s> DebugLoc DL = MBB . findDebugLoc ( MBB . begin ( ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; MBB . removeLiveIn ( <STR_LIT>


<s> SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Alignment , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; Ptr = DAG . getMemBasePlusOffset ( Ptr , <NUM_LIT> , dl ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , MinAlign ( Alignment , <NUM_LIT> ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , RegVT , Load1 , Load2 ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ; } if ( Ext == <STR_LIT> && ! Subtarget . hasAVX512 ( ) && RegVT . isVector ( ) && RegVT . getScalarType

( ) == <STR_LIT> && DCI . isBeforeLegalize ( ) ) {


<s> if ( ! DECL_NAME ( decl ) ) return ! base_is_mips16 ; if ( ! mflip_mips16_htab ) mflip_mips16_htab = hash_map < nofree_string_hash , bool > :: create_ggc ( <NUM_LIT> ) ; name = IDENTIFIER_POINTER ( DECL_NAME


<s> static <ISA_LIT>Operand * CreateProcIFlags ( <STR_LIT> IFlags , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ProcIFlags ) ; Op -> IFlags . Val = IFlags ; Op -> StartLoc = S ; Op -> EndLoc


<s> if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) ) return arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) || ( TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p (


<s> break ; } unsigned SrcReg = Cond [ <NUM_LIT> ] . getReg ( ) ; if ( Is64Bit ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } else { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } break ; } case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } assert ( RC && <STR_LIT> ) ; if ( TryFold ) { unsigned NewVReg = <NUM_LIT> ; unsigned FoldedOpc = canFoldIntoCSel ( MRI , TrueReg , & NewVReg ) ; if ( FoldedOpc ) { CC = <STR_LIT> ( CC ) ; TrueReg = FalseReg ; } else FoldedOpc = canFoldIntoCSel ( MRI , FalseReg , & NewVReg


<s> static LegalizerInfo :: SizeAndActionsVec widen_1_8 ( const LegalizerInfo :: SizeAndActionsVec & v ) { assert ( v . size ( ) >= <NUM_LIT> ) ; assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result .


<s> d . perm [ i ] = ei ; perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) { d . one_operand_p = false ; break ; } for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d . perm [ i ] >= nelt ) d . perm [ i ] -= nelt ; case <NUM_LIT> : d . op1 = d . op0 ; d . one_operand_p = true ; break ; case <NUM_LIT> : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . op0 = d . op1 ; d . one_operand_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; if ( ! d . one_operand_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; start_sequence ( ) ; bool ret = ia64_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } if ( ia64_expand_vec_perm_const_1 ( & d ) ) return true ; if ( which == <NUM_LIT> && d . one_operand_p ) { memcpy ( d . perm , perm ,


<s> Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT>


<s> unsigned <ISA_LIT>FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { unsigned Offset = <NUM_LIT> ; Offset +=


<s> bool hasSMEI64 ( ) const { return HasSMEI64


<s> const char * getPassName ( ) const override { return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static bool isEXTMask ( ArrayRef < int > M , EVT VT , bool & ReverseEXT , unsigned & Imm ) { const int * FirstRealElt = find_if ( M , [ ] ( int Elt ) { return Elt >= <NUM_LIT> ; } ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned MaskBits = APInt ( <NUM_LIT> , NumElts * <NUM_LIT> ) . logBase2 ( ) ; APInt ExpectedElt = APInt ( MaskBits , * FirstRealElt + <NUM_LIT> ) ; const int * FirstWrongElt = std :: find_if ( FirstRealElt + <NUM_LIT> , M . end ( ) , [ & ] ( int Elt ) { return Elt != ExpectedElt ++ && Elt != - <NUM_LIT> ; } ) ; if ( FirstWrongElt != M . end ( ) ) return false ; Imm = ExpectedElt . getZExtValue ( ) ; if ( Imm < NumElts ) ReverseEXT = true ; else Imm -= NumElts ; return


<s> } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand &


<s> bool <ISA_LIT>TTIImpl :: expandMemCmp ( Instruction * I , unsigned & MaxLoadSize ) { MaxLoadSize = <NUM_LIT>


<s> LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( III . ZeroIsSpecialNew ) { unsigned RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegToModify ) ) { const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify , NewRC ) ; } } } if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill ( DefMI ,


<s> } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && IndexReg != <STR_LIT> ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && IndexReg != <STR_LIT> && IndexReg != <STR_LIT> ) || ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && IndexReg != <STR_LIT> && IndexReg != <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return


, ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case (

<STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; uint64_t SlotSize = TD -> getPointerSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset &


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) addExpr ( Inst , getImm ( ) ) ; else Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( )


<s> else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION


<s> if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; bool IsNegPow2 = Divisor . isNegatedPowerOf2 ( ) ; unsigned Lg2 = ( IsNegPow2 ? - Divisor : Divisor ) . countTrailingZeros ( ) ; SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VT , N0 , ShiftAmt ) ; Created . push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( <STR_LIT> , DL , VT , DAG

. getConstant ( <NUM_LIT> , DL , VT ) , Op ) ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { PM . add ( create<ISA_LIT>BranchSelectionPass ( ) )


<s> if ( GET_CODE ( dst ) != REG || ! ( FP_REGNO_P ( REGNO ( dst ) ) && FP_REGNO_P ( REGNO ( dst ) + <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( GET_CODE ( src ) != MEM || MEM_VOLATILE_P ( src ) ) return <NUM_LIT> ; switch ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) ) { case REG : case POST_INC : break ; case POST_DEC : return <NUM_LIT> ; case POST_MODIFY : { rtx adjust = XEXP ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( adjust ) != CONST_INT || INTVAL ( adjust ) != GET_MODE_SIZE

( GET_MODE ( src ) ) ) return <NUM_LIT> ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate ) ; Op -> Imm . Val =


<s> inline Predicate getPredicate ( unsigned Condition , unsigned Hint ) { return ( Predicate ) ( ( Condition & ~ BR_HINT_MASK ) |


<s> return isSimpleMove ( MI , FrameIndex , <STR_LIT>


<s> return __builtin_ia32_addsh_mask ( __B , __C , _mm_setzero_ph ( ) ,


<s> CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ; if ( ! IsExact || ! IntVal . isPowerOf2 ( ) ) return false ; unsigned FBits = IntVal . logBase2 (


<s> SmallVector < SDNode * , <NUM_LIT> > Queue ( <NUM_LIT> , Chain . getNode ( ) ) ; SmallSet < SDNode * , <NUM_LIT> > Visited ; while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) ) continue ; if ( LoadSDNode * ChainLD = dyn_cast < LoadSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear ( ) ; Queue . clear ( ) ; for ( SmallSet < SDNode * , <NUM_LIT> > :: iterator I = LoadRoots . begin ( ) , IE = LoadRoots . end ( ) ; I != IE ; ++ I ) { Queue . push_back ( * I ) ; while ( ! Queue . empty ( ) ) { SDNode * LoadRoot = Queue .


<s> LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc


<s> if ( arg . type && TREE_CODE ( arg . type ) == VECTOR_TYPE ) mode = type_natural_mode ( arg . type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) reg = function_arg_ms_64 ( cum , mode , arg . mode , arg . named , arg . type , bytes ) ; else reg = function_arg_64 ( cum , mode , arg . mode , arg . type , arg . named ) ; } else reg = function_arg_32 ( cum , mode , arg . mode , arg . type , bytes , words ) ; if ( reg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return


<s> assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasVSX ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : { Register TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) { MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( SrcReg ) ) { NumStoreSPILLVSRRCAsVec ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; return expandPostRAPseudo ( MI ) ; } else { NumStoreSPILLVSRRCAsGpr ++ ; MI . setDesc ( get ( <STR_LIT> ) ) ; } return true ; } case <STR_LIT> : { Register TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( TargetReg ) ) MI . setDesc ( get ( <STR_LIT> ) ) ; else MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT>


<s> return ( int16x8x2_t ) { vtrn1q_s16 ( a , b ) , vtrn2q_s16


<s> void <ISA_LIT>TargetLowering :: markLibCallAttributes ( MachineFunction * MF , unsigned CC , ArgListTy & Args ) const { if ( Subtarget . is64Bit ( ) ) return ; if ( CC != CallingConv :: C && CC != CallingConv :: <ISA_LIT>_StdCall ) return ; unsigned ParamRegs = <NUM_LIT> ; if ( auto * M = MF -> getFunction ( ) . getParent ( ) ) ParamRegs = M


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles

, const BranchProbability & Probability ) const {


<s> bool isMM16AsmReg ( ) const { if ( ! ( isRegIdx ( ) && RegIdx . Kind ) ) return false ; return ( ( RegIdx . Index >= <NUM_LIT> && RegIdx . Index <= <NUM_LIT> ) || RegIdx . Index == <NUM_LIT> || RegIdx . Index


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; } if ( Subtarget . is<ISA_LIT>64 ( )


<s> case <STR_LIT> : switch ( MI . getOperand ( <NUM_LIT> ) . getType ( ) ) { default : return false ; case MachineOperand :: MO_GlobalAddress : return MI . getOperand ( <NUM_LIT> ) .


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedSVERestores ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { emitCalleeSavedRestores ( MBB ,


<s> return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI ->


<s> unsigned Size = getInstSizeInBytes ( MI ) ; if ( Subtarget . isThumb2 ( ) ) Size /=


<s> bool hasSlowLoadDSubregister ( ) const { return


<s> rtx last_2_bit = gen_reg_rtx ( SImode ) ; rtx byte_loop_base = gen_reg_rtx ( SImode ) ; rtx byte_loop_size = gen_reg_rtx ( SImode ) ; rtx remain_size = gen_reg_rtx ( SImode ) ; rtx new_base_reg ; rtx value4byte , value4word ; rtx byte_mode_size ; rtx last_byte_loop_label = gen_label_rtx ( ) ; size = force_reg ( SImode , size ) ; value4word = nds32_gen_dup_4_byte_to_word_value ( value ) ; value4byte = simplify_gen_subreg ( QImode , value4word , SImode , <NUM_LIT> ) ; emit_move_insn ( byte_loop_size , size ) ; emit_move_insn ( byte_loop_base , base_reg ) ; emit_cmp_and_jump_insns ( size , gen_int_mode ( <NUM_LIT> , SImode ) , LE , NULL , SImode , <NUM_LIT> , last_byte_loop_label ) ; emit_insn ( gen_andsi3 ( last_2_bit , base_reg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_insn ( gen_subsi3 ( need_align_bytes , gen_int_mode ( <NUM_LIT> , SImode ) , last_2_bit ) ) ; new_base_reg = emit_setmem_byte_loop ( base_reg , need_align_bytes , value4byte , true ) ; emit_insn ( gen_subsi3 ( remain_size , size , need_align_bytes ) ) ; byte_mode_size = emit_setmem_word_loop ( new_base_reg , remain_size , value4word ) ; emit_move_insn ( byte_loop_base , new_base_reg ) ; emit_move_insn ( byte_loop_size , byte_mode_size ) ; emit_label ( last_byte_loop_label


<s> void <ISA_LIT>InstPrinter :: printU3ImmOperand ( const MCInst * MI , unsigned OpNo

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> static void rs6000_destroy_cost_data ( void


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget


<s> bool hasVDSP2E60F ( ) const { return


<s> } else if ( TM . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm (

<NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;


<s> unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addImm ( <NUM_LIT> ) .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= <NUM_LIT> * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( sr . reg , GEN_INT (


<s> SDValue HiShift = DAG . getConstant ( EltSizeInBits , DL , Amt . getValueType ( ) ) ; Op0 = DAG . getAnyExtOrTrunc ( Op0 , DL , <STR_LIT> ) ; Op1 = DAG . getZExtOrTrunc ( Op1 , DL , <STR_LIT> ) ; Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , Mask ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , HiShift ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Op1 ) ; if ( IsFSHR ) { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , HiShift ) ; } return DAG . getZExtOrTrunc ( Res , DL , VT ) ; } if ( VT == <STR_LIT> || ExpandFunnel ) return SDValue ( ) ; if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned FSHOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( FSHOp , DL , VT ,


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveLRPair ( unsigned Reg , int Offset ) { emitARM64WinUnwindCode ( Win64EH :: UOP_SaveLRPair , Reg ,


<s> if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; return ; } if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML -> getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; return ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert =


<s> __v16qu a , b ; __v16qu vmin , vmax , vabsdiff ; __v4si vsum ; const __v4su zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4si result ; a = ( __v16qu ) __A ; b = ( __v16qu ) __B ; vmin = vec_min ( a , b ) ; vmax = vec_max ( a , b ) ; vabsdiff = vec_sub ( vmax , vmin ) ; vsum = ( __vector signed int ) vec_sum4s ( vabsdiff , zero ) ; result = vec_sum2s ( vsum , ( __vector signed int ) zero ) ; result = vec_sld ( result ,


<s> } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index % NumElts ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) { assert ( ( LT . second . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubVecs = LT . second . getSizeInBits ( ) / <NUM_LIT> ; SubNumElts = NumElts / NumSubVecs ; if ( SubNumElts <= Index ) { RegisterFileMoveCost += ( Opcode == Instruction :: InsertElement ? <NUM_LIT> : <NUM_LIT> ) ; Index %= SubNumElts ; } } if ( Index == <NUM_LIT> ) { if ( ScalarType -> isFloatingPointTy ( ) ) return RegisterFileMoveCost ; if ( ScalarType -> isIntegerTy ( ) && Opcode == Instruction :: ExtractElement ) return <NUM_LIT> + RegisterFileMoveCost ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ST -> useSLMArithCosts ( ) ) if ( auto * Entry = CostTableLookup ( SLMCostTbl , ISD , MScalarTy ) ) return Entry -> Cost + RegisterFileMoveCost ; if ( ( MScalarTy == <STR_LIT> && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) ) return <NUM_LIT> + RegisterFileMoveCost ; if ( MScalarTy == <STR_LIT> && ST -> hasSSE41 ( ) && Opcode

== Instruction :: InsertElement ) return <NUM_LIT> + RegisterFileMoveCost ;


<s> rtx r2 = ( ( const struct toc_hash_struct * ) h2 ) -> key ; if ( ( ( const struct toc_hash_struct * ) h1 ) -> key_mode != ( ( const struct toc_hash_struct * )


<s> break ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! ResNode ) ResNode = tryRISBGZero ( Node ) ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; Node = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; } break ; } } if ( ! ResNode ) ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ; if ( ResNode == nullptr || ResNode == Node ) Node -> dump ( CurDAG ) ; else ResNode -> dump (


<s> assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: Create ( Mang -> getSymbol ( GV ) , ( Subtarget -> isTargetDarwin ( ) ? MCSymbolRefExpr :: VK_None : MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 ) , OutContext ) ; OutStreamer . EmitValue (


<s> bool isS16ImmX4 ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm ( ) ) && ( getImm ( ) &


<s> return DAG . getNode ( <STR_LIT> , dl , VT , X , Y ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getNOT ( dl , Y , VT ) ) ; } } if ( VT . is128BitVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetCCResultType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDLoc DL ( Op ) ; if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Add , <STR_LIT> ) ; return DAG . getSelect ( DL , VT , Cmp , DAG . getAllOnesConstant ( DL , VT ) , Add ) ; } if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT>


<s> Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) ->


<s> gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , & padding_bits_to_clear [ <NUM_LIT> ] ) ; if ( to_clear_args_mask ) { for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_args_mask & ( <NUM_LIT> << regno )

) bitmap_clear_bit ( to_clear_bitmap , regno ) ;


<s> machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int i , parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( inner ) ; rtx tmpsum = op1 ; for ( i = parts / <NUM_LIT> ; i >= <NUM_LIT> ; i /= <NUM_LIT> ) { rtx dest = ( i == <NUM_LIT> ) ?


<s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> if ( A . getSimpleValueType ( ) != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue V = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> )


<s> else if ( GET_CODE ( src ) == PLUS || GET_CODE ( src ) == MINUS || GET_CODE ( src ) == IOR || GET_CODE ( src ) == XOR || GET_CODE ( src ) == AND ) { gain += ix86_cost -> add ; if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == NOT && ! TARGET_BMI ) gain += <NUM_LIT> * ix86_cost -> add ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; } else if ( GET_CODE ( src ) == NEG || GET_CODE ( src ) == NOT ) gain += ix86_cost -> add - COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_CODE ( src ) == COMPARE ) { } else if ( CONST_INT_P ( src ) ) { if ( REG_P ( dst ) ) gain += COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( MEM_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_store [


<s> case LO : return <STR_LIT> ; case MI : return <STR_LIT> ; case PL : return <STR_LIT> ; case VS : return <STR_LIT> ; case VC : return <STR_LIT> ; case HI : return <STR_LIT> ; case LS : return <STR_LIT> ; case GE : return <STR_LIT> ; case LT : return <STR_LIT> ; case GT : return <STR_LIT> ; case LE : return <STR_LIT> ; case AL : return


<s> bool isTargetAndroid ( ) const { return TargetTriple . isAndroid (


<s> unsigned CCValid = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > Selects ; SmallVector < MachineInstr * , <NUM_LIT> > DbgValues ; Selects . push_back ( & MI ) ; unsigned Count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator NextMIIt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; NextMIIt != MBB -> end ( ) ; ++ NextMIIt ) { if ( isSelectPseudo ( * NextMIIt ) ) { assert ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCValid && <STR_LIT> ) ; if ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCMask || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) { Selects . push_back ( & * NextMIIt ) ; continue ; } break ; } if ( NextMIIt -> definesRegister ( <STR_LIT> ) || NextMIIt -> usesCustomInsertionHook ( ) ) break ; bool User = false ; for ( auto SelMI : Selects ) if ( NextMIIt -> readsVirtualRegister ( SelMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { User = true ; break ; } if ( NextMIIt -> isDebugInstr ( ) ) { if ( User ) { assert ( NextMIIt -> isDebugValue ( ) && <STR_LIT> ) ; DbgValues . push_back ( & * NextMIIt ) ; } } else if ( User || ++ Count > <NUM_LIT> ) break ; } MachineInstr * LastMI = Selects . back (


<s> reachedUsesToDefs ( ADRPToReachingDefs , ColorOpToReachedUses , RegToId , true ) ; computeADRP ( ADRPToReachingDefs , * <ISA_LIT>FI , MDT ) ; delete [ ] ColorOpToReachedUses ; ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , false , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs UsesToReachingDefs ; reachedUsesToDefs ( UsesToReachingDefs , ColorOpToReachedUses , RegToId , false ) ; computeOthers ( UsesToReachingDefs , ColorOpToReachedUses , * <ISA_LIT>FI , RegToId , MDT ) ; delete [ ] ColorOpToReachedUses ; if ( BasicBlockScopeOnly ) MF . DeleteMachineInstr ( DummyOp ) ; return Modified


<s> assert ( MCValOp . isImm ( ) || MCValOp . isExpr ( ) ) ; bool IsImm = Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ; uint64_t ImmValue = IsImm ? MCValOp . getImm ( ) : <NUM_LIT> ; const MCExpr * ValExpr ; if ( IsImm ) ValExpr = MCConstantExpr :: create ( ImmValue , getContext ( ) ) ; else ValExpr = MCValOp . getExpr ( ) ; MCOperand PrevReg = MCOperand :: createReg ( <STR_LIT> ) ; if ( ! IsImm || ( ImmValue & ~ <NUM_LIT> ) ) { MCInst TmpInst ; const MCExpr * Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , ValExpr , getContext ( ) ) ; TmpInst . setLoc ( IDLoc ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCRegOp ) ; TmpInst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; Instructions . push_back ( TmpInst ) ; PrevReg = MCRegOp ; } if ( ! IsImm || ( ( ImmValue & <NUM_LIT> ) != <NUM_LIT> || ImmValue == <NUM_LIT> ) ) { MCInst TmpInst ; const MCExpr * Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , ValExpr , getContext ( ) ) ; TmpInst . setLoc ( IDLoc ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCRegOp ) ; TmpInst . addOperand ( PrevReg ) ; TmpInst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; Instructions . push_back ( TmpInst


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) { return getAddrLarge ( JT , DAG ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel ::


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee ) const { <STR_LIT> SpecialCallingConv = <STR_LIT> ; return


<s> rtx_insn * insn = DF_INSN_UID_GET ( id ) -> insn ; df_ref ref ; FOR_EACH_INSN_DEF ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && GET_MODE ( DF_REF_REG ( ref ) ) == TImode ) timode_check_non_convertible_regs ( candidates , regs , DF_REF_REGNO ( ref ) ) ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && GET_MODE ( DF_REF_REG ( ref ) ) == TImode ) timode_check_non_convertible_regs ( candidates , regs , DF_REF_REGNO ( ref ) ) ; } EXECUTE_IF_SET_IN_BITMAP ( regs , <NUM_LIT> , id , bi ) { for ( df_ref def = DF_REG_DEF_CHAIN ( id ) ; def ; def = DF_REF_NEXT_REG ( def ) ) if ( bitmap_bit_p ( candidates , DF_REF_INSN_UID ( def ) ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , DF_REF_INSN_UID ( def ) ) ; bitmap_clear_bit ( candidates , DF_REF_INSN_UID ( def )


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> raw_string_ostream OS ( Buf ) ; OS << <STR_LIT> << * BaseGVB << <STR_LIT> ; BaseGV -> getContext ( ) . emitError ( OS . str ( ) ) ; } const MCExpr * Sym = MCSymbolRefExpr :: create ( getSymbol ( BaseGVB ) , Ctx ) ; if ( Offset . sgt ( <NUM_LIT> ) ) Sym = MCBinaryExpr :: createAdd ( Sym , MCConstantExpr :: create ( Offset . getSExtValue ( ) , Ctx ) , Ctx ) ; else if ( Offset . slt ( <NUM_LIT> ) ) Sym = MCBinaryExpr :: createSub ( Sym , MCConstantExpr :: create ( ( - Offset ) . getSExtValue ( ) , Ctx ) , Ctx ) ; auto * Disc = PAI . getDiscriminator (


<s> InstructionCost <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands , TTI :: TargetCostKind CostKind ) { if ( isMMAType ( U -> getType ( ) ) ) return InstructionCost :: getMax ( ) ; if ( isa < CastInst > ( U ) || isa < LoadInst > ( U ) || isa < StoreInst > ( U ) ) return

BaseT :: getUserCost ( U , Operands , CostKind ) ;


<s> unsigned TailOpcode ; if ( Call -> getOpcode ( ) == <STR_LIT> ) { TailOpcode = <STR_LIT> ; } else { assert ( Call -> getOpcode ( ) == <STR_LIT> ) ; TailOpcode = <STR_LIT> ; } MachineInstr * TC = BuildMI ( MF , DebugLoc ( ) , get ( TailOpcode ) ) . add ( Call -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB . insert ( MBB . end ( ) , TC ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { assert ( OF . FrameConstructionID != MachineOutlinerDefault && <STR_LIT> ) ; fixupPostOutline ( MBB ) ; MBB . addLiveIn ( <STR_LIT> ) ; MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction ::

createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG ,


<s> return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; } if ( Kind == TTI :: SK_Alternate ) { static const CostTblEntry < <STR_LIT> > NEONAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONAltShuffleTbl , <STR_LIT> , LT .

second ) ) return LT . first * Entry -> Cost ;


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; machine_mode cc_mode = CCmode ; rtx mask ; rtx cond2 ; rtx tmp ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return <NUM_LIT> ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case


<s> return ( uint16x8_t ) __builtin_neon_vreinterpretv8hiti ( ( __builtin_neon_ti )


<s> uint32_t imm = Val & <NUM_LIT> ; uint32_t rot = ( Val & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t rot_imm = ( imm >> rot ) | ( imm << ( ( <NUM_LIT> - rot ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( rot_imm ) ) ; return MCDisassembler :: Success


<s> insn -> sibIndexBase = SIB_INDEX_EAX ; sibBaseBase = SIB_BASE_EAX ; break ; case <NUM_LIT> : insn -> sibIndexBase = SIB_INDEX_RAX ; sibBaseBase = SIB_BASE_RAX ; break ; } if ( consume ( insn , insn -> sib ) ) return - <NUM_LIT> ; index = indexFromSIB ( insn -> sib ) | ( xFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; if ( index == <NUM_LIT> ) { insn -> sibIndex = SIB_INDEX_NONE ; } else { insn -> sibIndex = ( SIBIndex ) ( insn -> sibIndexBase + index ) ; } insn -> sibScale = <NUM_LIT> << scaleFromSIB ( insn -> sib ) ; base = baseFromSIB ( insn -> sib ) | ( bFromREX (


<s> static SDValue CreateStoreLR ( unsigned Opc , SelectionDAG & DAG , StoreSDNode * SD , SDValue Chain , unsigned Offset ) { SDValue Ptr = SD -> getBasePtr ( ) , Value = SD -> getValue ( ) ; EVT MemVT = SD -> getMemoryVT ( ) , BasePtrVT = Ptr . getValueType ( ) ; DebugLoc DL = SD -> getDebugLoc ( ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> ) ; if ( Offset ) Ptr = DAG . getNode ( <STR_LIT> , DL , BasePtrVT , Ptr , DAG . getConstant ( Offset , BasePtrVT ) ) ; SDValue Ops [ ] = { Chain , Value , Ptr } ; return DAG . getMemIntrinsicNode ( Opc , DL , VTList , Ops , <NUM_LIT> ,


<s> SDValue <ISA_LIT>TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT>

&& Subtarget . hasVSX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) ) {


<s> insn = emit_call_insn ( pattern ) ; if ( TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p ( orig_addr ) ) { reg = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn_before ( gen_move_insn ( reg , addr ) , insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , reg ) ; } if ( lazy_p ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; if ( TARGET_USE_GOT ) { use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , GOT_VERSION_REGNUM ) ) ; emit_insn ( gen_update_got_version ( ) ) ; } if ( TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS


<s> return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ]


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { auto * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> static const int INSTR_DISTANCE_THRESHOLD = <NUM_LIT> ; CurInst = I ; bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I != CurInst ) { if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD


<s> if ( SelectShifterOperandReg ( N , TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1


<s> switch ( Opcode ) { case <STR_LIT> : \ return <STR_LIT> ; case <STR_LIT> : \ case <STR_LIT>


<s> void setRegKind ( RegisterKind RegKind ) { assert ( ( Kind == k_Register || Kind == k_PtrReg ) && <STR_LIT> ) ; Reg . Kind


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; if ( ForceStackAlign ) return


<s> if ( LiveRegs [ rx ] -> Refs == <NUM_LIT> && ! LiveRegs [ rx ] -> isCollapsed (

) ) Collapse ( LiveRegs [ rx ] , LiveRegs [ rx ] -> getFirstDomain ( ) ) ;


<s> unsigned <ISA_LIT>FastISel :: emitSMULL_rr ( MVT RetVT , unsigned Op0 , bool Op0IsKill , unsigned Op1


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG ) ) return DivRem8 ; return SDValue


<s> unsigned <ISA_LIT>MCCodeEmitter :: get<ISA_LIT>RegNum ( const MCOperand & MO ) const { return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) )


<s> static rtx mmix_function_incoming_arg ( cumulative_args_t argsp , const function_arg_info & arg ) { return mmix_function_arg_1 ( argsp , arg ,


<s> return canCombine ( MBB , MO , MulOpc ,


<s> SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( NewReturnAddrFI ) , false ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createDRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl ,


<s> Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isTargetCygMing ( ) || ST . isTargetKnownWindowsMSVC ( ) || ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) ; else if ( ST . is64Bit ( ) || ST . isTargetDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? <NUM_LIT> : <NUM_LIT> ; if ( flag_mlow_precision_div ) iterations -- ; rtx xtmp = gen_reg_rtx ( mode ) ; while ( iterations -- ) { emit_insn ( gen_aarch64_frecps ( mode , xtmp , xrcp , den ) ) ; if ( iterations > <NUM_LIT> ) emit_set_insn ( xrcp , gen_rtx_MULT


<s> if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } bool is64BitVector = VT . is64BitVector ( ) ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) SrcReg = V0 ; else { SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = is64BitVector ? SDValue ( createDPairNode ( V0 , V1 ) , <NUM_LIT> ) : SDValue ( createQPairNode ( V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = is64BitVector ? SDValue ( createDTripleNode ( V0 , V1 , V2 ) , <NUM_LIT> ) : SDValue ( createQTripleNode ( V0 , V1 , V2 ) , <NUM_LIT> ) ; else { SDValue V3 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = is64BitVector ? SDValue ( createDQuadNode ( V0 , V1 , V2 , V3 ) , <NUM_LIT> )

: SDValue ( createQQuadNode ( V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ;


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Value = CE -> getValue ( ) ; if ( Inv ) Value = ~ Value ; unsigned B = Value & <NUM_LIT> ; B |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm


<s> return ( __mmask8 ) __builtin_ia32_ucmpq128_mask ( ( __v2di ) __X , (


<s> tree t_excp ; tree t_reset ; tree attrs ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; attrs = DECL_ATTRIBUTES ( func ) ; t_intr = lookup_attribute ( <STR_LIT> , attrs


<s> return __builtin_mve_vmovntq_uv4si ( __a ,


<s> first_v = node_v ; while ( first_v -> prev != NULL ) first_v = first_v -> prev ; default_version_info = first_v ; while ( default_version_info != NULL ) { const tree decl2 = default_version_info -> this_node -> decl ; if ( is_function_default_version ( decl2 ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; error_at ( DECL_SOURCE_LOCATION ( default_node -> decl ) , <STR_LIT> <STR_LIT> ) ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ; struct cgraph_node * dispatcher_node


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > (


<s> MCAsmParser & Parser = getParser ( ) ; const auto Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; if ( IsMachO ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: EndOfStatement ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken :: String ) ) { Error ( L , <STR_LIT>


<s> static inline hashval_t hash ( tree_map * m ) { return m ->


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; } assert ( Opc && <STR_LIT> ) ; const MachineInstrBuilder & MI = BuildMI ( MBB , MBBI , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) .


<s> AM . Disp += G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast


<s> if ( cum -> decl && ! TREE_PUBLIC ( cum -> decl ) ) return ; const_tree ctx = get_ultimate_context ( cum -> decl ) ; if ( ctx != NULL_TREE && ! TRANSLATION_UNIT_WARN_EMPTY_P ( ctx ) ) return ; if ( int_size_in_bytes ( type ) ==


<s> bool <ISA_LIT>Subtarget :: isXRaySupported ( )


<s> fprintf ( asm_out_file , <STR_LIT> ) ; recurse = <NUM_LIT> ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , <NUM_LIT> ) [ <NUM_LIT> ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , <NUM_LIT> ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , <STR_LIT> , name ) ; return true


<s> IAH . Out ( <STR_LIT> ) ; if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; } swapFPIntParams ( PV , M , IAH , LE , false ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( LocalName + <STR_LIT> + Name ) ; new UnreachableInst ( FStub -> getContext (


<s> if ( VecElems == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < Stride ; i ++ ) TransposedMatrix [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , UndefValue :: get ( Vec [ i ] -> getType ( ) ) , VPShuf ) ; return ; } SmallVector < int , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( ) ; } if ( VecElems == <NUM_LIT> ) { std :: copy ( Temp , Temp + Stride , TransposedMatrix . begin ( ) ) ; return ; } else for ( unsigned i = <NUM_LIT> ; i < Stride ; i ++ ) TransposedMatrix [ i ] = Builder . CreateShuffleVector ( Temp [

<NUM_LIT> * i ] , Temp [ <NUM_LIT> * i + <NUM_LIT> ] , Concat ) ;


<s> if ( const MCSymbolXCOFF * XSym = dyn_cast < MCSymbolXCOFF > ( & S ) ) { MCSymbolXCOFF * TCSym = cast < MCSymbolXCOFF > ( Streamer . getContext ( ) . getOrCreateSymbol ( XSym -> getSymbolTableName ( ) + <STR_LIT> ) ) ; if ( TCSym -> hasRename ( ) ) Streamer . emitXCOFFRenameDirective ( TCSym ,


<s> for ( unsigned i = <NUM_LIT> ; i != nelt ; i ++ ) d -> perm [ i ] = ( d -> perm [ i


<s> static bool ia64_struct_retval_addr_is_first_parm_p ( tree fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; return ( abi_version_at_least ( <NUM_LIT> ) && ret_type && TYPE_MODE ( ret_type ) == BLKmode && TREE_ADDRESSABLE ( ret_type


<s> if ( HaveReg1 && Reg1 . Group != RegGR && Reg1 . Group != RegV && parseAddressRegister ( Reg1 ) ) return true ; if ( HaveReg2 && parseAddressRegister ( Reg2 ) ) return true ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( HaveReg1 || HaveReg2 || Length ) Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; return false


<s> if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead


<s> rtl_opt_pass * make_pass_tag_collision_avoidance ( gcc :: context * ctxt ) { return new pass_tag_collision_avoidance (


<s> Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; UseDataRegionDirectives = true ; SupportsDebugInformation = true ; ExceptionsType = TheTriple . isWatchOS ( ) ? ExceptionHandling :: DwarfCFI : ExceptionHandling :: SjLj ; UseIntegratedAssembler =


<s> elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , offset + i ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , offset + n_elts + i ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g ,


<s> if ( MI . isDebugValue ( ) ) continue ; assert ( MI . isEHLabel ( ) && <STR_LIT> ) ; Sym = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; } if ( ! MMI -> hasCallSiteLandingPad ( Sym ) ) continue ; for ( unsigned CSI : MMI -> getCallSiteLandingPad ( Sym ) ) { CallSiteNumToLPad [ CSI ] . push_back ( & MBB ) ; MaxCSNum = std :: max ( MaxCSNum , CSI ) ; } } std :: vector < MachineBasicBlock * > LPadList ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > InvokeBBs ; LPadList . reserve ( CallSiteNumToLPad . size ( ) ) ; for ( unsigned CSI = <NUM_LIT> ; CSI <= MaxCSNum ; ++ CSI ) { for ( auto & LP : CallSiteNumToLPad [ CSI ] ) { LPadList . push_back ( LP ) ; InvokeBBs . insert ( LP -> pred_begin ( ) , LP -> pred_end ( ) ) ; } } assert ( ! LPadList . empty ( ) && <STR_LIT> ) ; MachineBasicBlock * DispatchBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> setIsEHPad ( true ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) ; DispatchBB -> addSuccessor ( TrapBB ) ; MachineBasicBlock * DispContBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> addSuccessor ( DispContBB ) ; MF -> push_back ( DispatchBB ) ; MF -> push_back ( DispContBB ) ; MF -> push_back ( TrapBB ) ; SetupEntryBlockForSjLj ( MI , BB , DispatchBB , FI ) ; MachineJumpTableInfo * JTI = MF -> getOrCreateJumpTableInfo ( getJumpTableEncoding ( ) ) ; unsigned MJTI = JTI -> createJumpTableIndex ( LPadList ) ; const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; const <ISA_LIT>RegisterInfo & RI = XII -> getRegisterInfo ( ) ; if ( RI . hasBasePointer ( * MF ) ) { const bool FPIs64Bit = Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setRestoreBasePointer ( MF ) ; unsigned FP = RI . getFrameRegister ( * MF ) ; unsigned BP = RI . getBaseRegister ( ) ; unsigned Op = FPIs64Bit ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( DispatchBB , DL , TII -> get ( Op ) , BP ) , FP , true , MFI -> getRestoreBasePointerOffset ( ) ) . addRegMask ( RI . getNoPreservedMask ( ) ) ; } else { BuildMI ( DispatchBB , DL , TII -> get ( <STR_LIT> ) ) . addRegMask ( RI . getNoPreservedMask ( ) ) ; } unsigned IReg = MRI -> createVirtualRegister (


<s> int d ; if ( TARGET_SHMEDIA || ( TARGET_SHCOMPACT && ( crtl -> args . info . call_cookie & CALL_COOKIE_RET_TRAMP ( <NUM_LIT> ) ) ) ) return false ; if ( ! reload_completed || frame_pointer_needed )


<s> case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { auto MMO = * MI . memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = MI . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! isPowerOf2_64 ( MMO -> getSize (


<s> static bool BUILD_VECTORtoBlendMask ( BuildVectorSDNode * BuildVector , unsigned & MaskValue ) { MaskValue = <NUM_LIT> ; unsigned NumElems = BuildVector -> getNumOperands ( ) ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; if ( NumLanes > <NUM_LIT> ) return false ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { SDValue EltCond = BuildVector -> getOperand ( i ) ; SDValue SndLaneEltCond = ( NumLanes == <NUM_LIT> ) ? BuildVector -> getOperand ( i + NumElemsInLane ) : EltCond ; int Lane1Cond = - <NUM_LIT> , Lane2Cond = - <NUM_LIT> ; if ( isa < ConstantSDNode > ( EltCond ) ) Lane1Cond = ! isNullConstant ( EltCond ) ; if ( isa < ConstantSDNode > ( SndLaneEltCond ) ) Lane2Cond = ! isNullConstant ( SndLaneEltCond ) ; unsigned LaneMask = <NUM_LIT> ; if ( Lane1Cond == Lane2Cond || Lane2Cond < <NUM_LIT> ) LaneMask = ! Lane1Cond << i ; else if ( Lane1Cond < <NUM_LIT> ) LaneMask = ! Lane2Cond << i ; else return false ; MaskValue |= LaneMask ; if ( NumLanes == <NUM_LIT> ) MaskValue |= LaneMask << NumElemsInLane ; } return


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && isGlobalInSmallSection ( GO , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isData ( ) && isGlobalInSmallSection ( GO , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM


<s> CFARegisterOffset = Inst . getOffset ( ) ; CFARegister = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; break ; case MCCFIInstruction :: OpDefCfaOffset : CFARegisterOffset = Inst . getOffset ( ) ; break ; case MCCFIInstruction :: OpDefCfaRegister : CFARegister = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; break ; case MCCFIInstruction :: OpOffset : Reg = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) RegOffsets [ Reg ] = Inst . getOffset ( ) ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { RegOffsets [ Reg ] = Inst . getOffset ( ) ; ++ FloatRegCount ; } else { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << Inst . getRegister ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } break ; case MCCFIInstruction :: OpRelOffset : break ; default : DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> <STR_LIT> << Inst . getOperation ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; break ; } } if ( ( CFARegister == <STR_LIT> ) && ( CFARegisterOffset == <NUM_LIT> ) ) return <NUM_LIT> ; if ( CFARegister != <STR_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << CFARegister << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } int StackAdjust = CFARegisterOffset - <NUM_LIT> ; if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> << CFARegisterOffset << <STR_LIT> << RegOffsets [ <NUM_LIT> ] << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } uint32_t CompactUnwindEncoding = CU :: UNWIND_<ISA_LIT>_MODE_FRAME ; switch ( StackAdjust ) { case <NUM_LIT> : break ; case <NUM_LIT>


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { default : MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return EmitF128CSEL ( MI , BB ) ; case TargetOpcode :: STACKMAP : case TargetOpcode :: PATCHPOINT : return emitPatchPoint ( MI , BB ) ; case <STR_LIT> : return EmitLoweredCatchRet ( MI , BB ) ; case <STR_LIT> : return EmitLoweredCatchPad ( MI ,


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false


<s> break ; case SUBREG : if ( ! REG_P ( SUBREG_REG ( op ) ) ) return <NUM_LIT> ; case REG : if ( ! base ) base = op ; else if ( ! index ) index = op ; else return <NUM_LIT> ; break ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : if ( disp ) return <NUM_LIT> ; disp = op ; break ; default : return <NUM_LIT> ; } } } else if ( GET_CODE ( addr ) == MULT ) { index = XEXP ( addr , <NUM_LIT> ) ; scale_rtx = XEXP ( addr , <NUM_LIT> ) ; } else if ( GET_CODE ( addr ) == ASHIFT ) { index = XEXP ( addr , <NUM_LIT> ) ; tmp = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONST_INT_P ( tmp ) ) return <NUM_LIT> ; scale = INTVAL ( tmp ) ; if ( ( unsigned HOST_WIDE_INT ) scale > <NUM_LIT> ) return <NUM_LIT> ; scale = <NUM_LIT> << scale ; retval = - <NUM_LIT> ; } else disp = addr ; if ( index ) { if ( REG_P ( index ) ) ; else if ( GET_CODE ( index ) == SUBREG && REG_P ( SUBREG_REG ( index ) ) ) ; else return <NUM_LIT> ; } if ( scale_rtx ) { if ( ! CONST_INT_P ( scale_rtx ) ) return <NUM_LIT> ; scale = INTVAL ( scale_rtx ) ; } base_reg = base && GET_CODE ( base ) == SUBREG ? SUBREG_REG ( base ) : base ; index_reg = index && GET_CODE ( index ) == SUBREG ? SUBREG_REG ( index ) : index ; if ( disp == const0_rtx && ( base || index ) ) disp = NULL_RTX ; if ( base_reg && index_reg && scale == <NUM_LIT> && ( index_reg == arg_pointer_rtx || index_reg == frame_pointer_rtx || ( REG_P ( index_reg ) && REGNO ( index_reg ) == STACK_POINTER_REGNUM ) ) ) { std :: swap ( base , index ) ; std :: swap ( base_reg , index_reg ) ; } if ( ! disp && base_reg && ( base_reg == hard_frame_pointer_rtx || base_reg == frame_pointer_rtx || base_reg == arg_pointer_rtx || ( REG_P ( base_reg ) && ( REGNO ( base_reg ) == HARD_FRAME_POINTER_REGNUM || REGNO ( base_reg ) == R13_REG ) ) ) ) disp = const0_rtx ; if ( TARGET_K6 && cfun && optimize_function_for_speed_p ( cfun ) && base_reg && ! index_reg && ! disp && REG_P ( base_reg ) && REGNO ( base_reg ) == SI_REG ) disp = const0_rtx ; if ( ! base && index && scale == <NUM_LIT> ) base = index , base_reg = index_reg , scale = <NUM_LIT> ; if ( ! base && ! disp && index && scale != <NUM_LIT> ) disp = const0_rtx ; out -> base = base ; out -> index = index ; out -> disp


<s> if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( CModel == CodeModel :: Large || ( GV -> getType ( ) -> getElementType ( ) -> isFunctionTy ( ) && ! GV -> isStrongDefinitionForLinker ( ) ) || GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; } return DestReg


<s> MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm (

<STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG .

getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 , Op1 ) ;