<s> MachineInstr * NewMI = postRAConvertToLEA ( MBB , MBI ) ; if ( NewMI ) { ++ NumLEAs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MBI -> dump ( ) ; ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ; ) ; MBB . getParent ( ) -> substituteDebugValuesForInst ( * MBI , * NewMI , <NUM_LIT> ) ; MBB . erase ( MBI ) ; MachineBasicBlock :: iterator J = static_cast < MachineBasicBlock :: iterator > ( NewMI


<s> if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> )


<s> if ( Res == <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || ! isNullConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue CSINC = N -> getOperand ( <NUM_LIT> ) ; if ( CSINC . getOpcode ( ) != <STR_LIT> || ! CSINC . hasOneUse ( ) ) return SDValue ( ) ; ConstantSDNode * X = dyn_cast < ConstantSDNode > ( CSINC


<s> static unsigned parse_field ( const std :: string & field ) { const char * rest = strchr ( field . c_str ( ) , ':' ) ; if ( rest == NULL ) return - <NUM_LIT> ; char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ; if ( after == rest + <NUM_LIT> ) return -


<s> default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( <STR_LIT> , file )


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return


<s> MachineInstrBuilder MIM = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) . addReg ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MachineInstr * MIO = BuildMI ( * BB , ( MachineInstr * ) MIM , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) . addReg ( MSrc )


<s> } if ( candidate -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse


<s> if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return combineAddOrSubToADCOrSBB ( N ,


<s> Inst . addOperand ( MCOperand :: CreateImm ( getShifter ( )


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data


<s> const char * getPassName ( ) const override { return


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned InsertPSMask ; if ( ! matchShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask ,


<s> BuildMI ( StackExtMBB , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( StackExtMBB ) ; NextMBB = <STR_LIT> ( StackAllocMI , & MBB ) ; MBB . addSuccessor ( NextMBB ) ; MBB . addSuccessor ( StackExtMBB


<s> O << markup ( <STR_LIT> ) << '$' << formatImm ( MI -> getOperand ( Op ) . getImm (

) & <NUM_LIT> ) << markup ( <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { this -> MF = & MF ; SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; O << <STR_LIT> ; emitFunctionStart ( MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II ) ; ++ EmittedInsts ; } O <<


_mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI


<s> unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder )


<s> else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; } else { AutoDetectSubtargetFeatures ( ) ; if ( In64BitMode ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; HasCMov = true ; ToggleFeature ( <STR_LIT> ) ; if ( ! HasAVX && <ISA_LIT>SSELevel < SSE2 ) { <ISA_LIT>SSELevel = SSE2 ; ToggleFeature ( <STR_LIT> ) ; ToggleFeature ( <STR_LIT> ) ; } } } if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; if ( HasAVX ) <ISA_LIT>SSELevel = NoMMXSSE ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( EnableSegmentedStacks && ! isTargetELF (


<s> MachineIRBuilder MIRBuilder ( I ) ; switch ( IntrinID ) { default : return false ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) | ( 'U' << <NUM_LIT> ) ) ; break ; } I . eraseFromParent ( ) ; return


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Res = ExpandBIT_CONVERT ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerShift ( N , DAG , Subtarget ) ; break ; } if ( Res . getNode ( ) ) Results .


<s> TARGET_CBRANCHDI4 = <NUM_LIT> ; flag_dwarf2_cfi_asm = <NUM_LIT> ; } } else { targetm . asm_out . aligned_op . di = NULL ; targetm . asm_out . unaligned_op . di = NULL ; } if ( ! ( TARGET_SH3 || TARGET_SH5 ) && TARGET_USERMODE ) TARGET_USERMODE = false ; if ( TARGET_SH1 ) { if ( ! strcmp ( sh_div_str , <STR_LIT> ) ) sh_div_strategy = SH_DIV_CALL_DIV1 ; else if ( ! strcmp ( sh_div_str , <STR_LIT> ) && ( TARGET_FPU_DOUBLE || TARGET_FPU_SINGLE_ONLY || ( TARGET_SHCOMPACT && TARGET_FPU_ANY ) ) ) sh_div_strategy = SH_DIV_CALL_FP ; else if ( ! strcmp ( sh_div_str , <STR_LIT> ) && TARGET_DYNSHIFT ) sh_div_strategy = SH_DIV_CALL_TABLE ; else if ( TARGET_HARD_SH4 ) sh_div_strategy = SH_DIV_CALL_TABLE ; else if ( TARGET_SH2A ) sh_div_strategy = SH_DIV_INTRINSIC ; else if ( TARGET_SHCOMPACT && TARGET_FPU_ANY ) sh_div_strategy = SH_DIV_CALL_FP ; else sh_div_strategy = SH_DIV_CALL_DIV1 ; } if ( ! TARGET_SH1 ) TARGET_PRETEND_CMOVE = <NUM_LIT> ; if ( sh_divsi3_libfunc [ <NUM_LIT> ] ) ; else if ( TARGET_DIVIDE_CALL_FP ) sh_divsi3_libfunc = <STR_LIT> ; else if ( TARGET_DIVIDE_CALL_TABLE ) sh_divsi3_libfunc = <STR_LIT> ; else if ( TARGET_SH5 ) sh_divsi3_libfunc = <STR_LIT> ; else sh_divsi3_libfunc = <STR_LIT> ; if ( sh_branch_cost == - <NUM_LIT> ) { sh_branch_cost = <NUM_LIT> ; } if ( ! global_options_set . x_TARGET_ZDCBRANCH && TARGET_HARD_SH4 ) TARGET_ZDCBRANCH = <NUM_LIT> ; if ( TARGET_FDPIC && ! flag_pic ) flag_pic = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! VALID_REGISTER_P ( regno ) ) sh_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; for ( regno = <NUM_LIT> ; regno < ADDREGNAMES_SIZE ; regno ++ ) if ( ! VALID_REGISTER_P ( ADDREGNAMES_REGNO ( regno ) ) ) sh_additional_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; if ( ( flag_pic && ! TARGET_PREFERGOT ) || ( TARGET_SHMEDIA && ! TARGET_PT_FIXED ) ) flag_no_function_cse = <NUM_LIT> ; if ( targetm . small_register_classes_for_mode_p ( VOIDmode ) ) { if ( ! TARGET_HARD_SH4 || flag_pic ) flag_schedule_insns = <NUM_LIT> ; else if ( flag_exceptions ) { if ( flag_schedule_insns && global_options_set . x_flag_schedule_insns ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; flag_schedule_insns = <NUM_LIT> ; } else if ( flag_schedule_insns && ! global_options_set . x_flag_schedule_insns ) flag_schedule_insns = <NUM_LIT> ; } if ( ( flag_unwind_tables || flag_asynchronous_unwind_tables || flag_exceptions || flag_non_call_exceptions ) && flag_omit_frame_pointer && ! TARGET_ACCUMULATE_OUTGOING_ARGS ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; TARGET_ACCUMULATE_OUTGOING_ARGS = <NUM_LIT> ; } if ( flag_unsafe_math_optimizations ) { if ( global_options_set . x_TARGET_FSCA == <NUM_LIT> && TARGET_SH4A_FP ) TARGET_FSCA = <NUM_LIT> ; if ( global_options_set . x_TARGET_FSRRA == <NUM_LIT> && TARGET_SH4A_FP ) TARGET_FSRRA = <NUM_LIT> ; } TARGET_FSRRA = TARGET_FSRRA && flag_unsafe_math_optimizations && flag_finite_math_only ; if ( ! global_options_set . x_TARGET_IEEE ) TARGET_IEEE = ! flag_finite_math_only ; if ( sh_fixed_range_str ) sh_fix_range ( sh_fixed_range_str ) ; if ( flag_strict_volatile_bitfields < <NUM_LIT> && abi_version_at_least ( <NUM_LIT>

) ) flag_strict_volatile_bitfields = <NUM_LIT> ;


<s> return ( uint16x4_t ) __builtin_neon_vcgev4hi (


<s> if ( ! N -> isExpandingLoad ( ) && VT . getVectorNumElements ( ) <= <NUM_LIT> ) return Op ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; SDValue Src0 = N -> getSrc0 ( ) ; Src0 = ExtendToType ( Src0 , WideDataVT , DAG ) ; MVT MaskEltTy = Mask . getSimpleValueType ( ) . getScalarType


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; bool NeedsStackRealignment = RegInfo . needsStackRealignment ( MF ) ; if ( ! NeedsStackRealignment && MFI . getMaxAlign ( ) > getStackAlign ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT>


<s> } int Base = i < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( M & ( <NUM_LIT> << <NUM_LIT> ) ) ShuffleMask . push_back ( SM_SentinelZero ) ; else { int Index = Base + (


<s> __arm_vldrbq_u16 ( uint8_t const * __base ) { return __builtin_mve_vldrbq_uv8hi ( ( __builtin_neon_qi *


<s> if ( ! isInt < <NUM_LIT> > ( ShiftedImm ) ) return ; Seq [ <NUM_LIT> ] . Opc = LUi ; Seq [ <NUM_LIT> ] . ImmOpnd = ( unsigned ) ( ShiftedImm & <NUM_LIT> ) ; Seq . erase ( Seq . begin (


<s> } else roundup = NULL ; t = build2 ( PLUS_EXPR , TREE_TYPE ( off ) , off , build_int_cst ( TREE_TYPE ( off ) , rsize ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( f_off ) , unshare_expr ( f_off ) , t ) ; if ( roundup ) t = build2 ( COMPOUND_EXPR , TREE_TYPE ( t ) , roundup , t ) ; u = build2 ( GT_EXPR , boolean_type_node , unshare_expr ( f_off ) , build_int_cst ( TREE_TYPE ( f_off ) , <NUM_LIT> ) ) ; cond2 = build3 ( COND_EXPR , ptr_type_node , u , NULL_TREE , NULL_TREE ) ; t = build2 ( COMPOUND_EXPR , TREE_TYPE ( cond2 ) , t , cond2 ) ; COND_EXPR_ELSE ( cond1 ) = t ; arg = get_initialized_tmp_var ( stack , pre_p , NULL ) ; if ( align > <NUM_LIT> ) { t = fold_build_pointer_plus_hwi ( arg , <NUM_LIT> ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - <NUM_LIT> ) ) ; roundup = build2 ( MODIFY_EXPR , TREE_TYPE ( arg ) , arg , t ) ; } else roundup = NULL ; t = fold_build_pointer_plus_hwi ( arg , size + <NUM_LIT> ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( TREE_TYPE ( t ) , - <NUM_LIT> ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , unshare_expr ( stack ) , t ) ; if ( roundup ) t = build2 ( COMPOUND_EXPR , TREE_TYPE ( t ) , roundup , t ) ; on_stack = build2 ( COMPOUND_EXPR , TREE_TYPE ( arg ) , t , arg ) ; if ( BLOCK_REG_PADDING ( mode , type , <NUM_LIT> ) == PAD_DOWNWARD && size < UNITS_PER_WORD ) { t = build2 ( POINTER_PLUS_EXPR , TREE_TYPE ( arg ) , arg , size_int ( UNITS_PER_WORD - size ) ) ; on_stack = build2 ( COMPOUND_EXPR , TREE_TYPE ( arg ) , on_stack , t ) ; } COND_EXPR_THEN ( cond1 ) = unshare_expr ( on_stack ) ; COND_EXPR_THEN ( cond2 ) = unshare_expr ( on_stack ) ; t = off ; if ( adjust ) t = build2 ( PREINCREMENT_EXPR , TREE_TYPE ( off ) , off , build_int_cst ( TREE_TYPE ( off ) , adjust ) ) ; t = fold_convert ( sizetype , t ) ; t = build2 ( POINTER_PLUS_EXPR , TREE_TYPE ( f_top ) , f_top , t ) ; if ( is_ha ) { int i ; tree tmp_ha , field_t , field_ptr_t ; tmp_ha = create_tmp_var_raw ( type , <STR_LIT> ) ; gimple_add_tmp_var ( tmp_ha ) ; switch ( ag_mode


<s> rtx addr = XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) ; if ( modified_in_p ( addr , set_insn ) != <NUM_LIT> ) { rtx set = single_set ( set_insn ) ; if ( set && ( push_operand ( SET_DEST ( set ) , GET_MODE ( SET_DEST ( set ) ) ) || pop_operand ( SET_SRC ( set ) , GET_MODE ( SET_SRC ( set ) ) ) ) ) { struct ix86_address parts ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx && ( parts . index == NULL_RTX || MEM_P ( SET_DEST ( set ) ) || ! modified_in_p ( parts . index , set_insn ) ) ) return false ; } return true ; } return false ; } return


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm


<s> LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; TTypeEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel |


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTTZ ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; assert ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT , Subtarget -> useSVEForFixedLengthVectors ( ) ) ) ; SDLoc DL ( Op ) ; SDValue RBIT = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> return __ev_mwsmian ( t , ( ( __ev64_s32__ ) { <NUM_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) MIB . addOperand ( MI . getOperand ( i ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Rt ) ; MI . eraseFromParent ( ) ; return BB


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMoveWideImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & UImm16MO = MI . getOperand ( OpIdx ) ; const MCOperand & ShiftMO = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Result = static_cast < unsigned > ( ShiftMO . getImm ( ) ) << <NUM_LIT> ; if ( UImm16MO . isImm ( ) ) { Result |= UImm16MO . getImm ( ) ; return Result ; } const <ISA_LIT>MCExpr * A64E = cast < <ISA_LIT>MCExpr > ( UImm16MO . getExpr ( ) ) ; <STR_LIT> requestedFixup ; switch ( A64E -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G0_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G1_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G3 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0 : requestedFixup = <STR_LIT> ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , false , false , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses (


<s> SDValue InVec1 = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExpectedOpcode = <STR_LIT> ; unsigned NextExpectedOpcode = <STR_LIT> ; bool AddFound = false ; bool SubFound = false ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue ( ) ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . getOpcode ( ) == <STR_LIT> ) InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getOpcode ( ) == <STR_LIT> ) InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) { if ( ExpectedOpcode == <STR_LIT> ) return SDValue ( ) ; std :: swap ( Op0 , Op1 ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } if ( InVec1 != Op1 . getOperand ( <NUM_LIT> ) )


<s> return ; if ( MBBI == MBB . end ( ) ) return ; MachineBasicBlock :: iterator NI = std :: next ( MBBI ) ; if ( NI == MBB . end ( ) ) return ; unsigned Opc = NI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes -= NI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( NI ) ; MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>


<s> RegNo = <NUM_LIT> ; const AsmToken & TokPercent = Parser . getTok ( ) ; assert ( TokPercent . is ( AsmToken :: Percent ) && <STR_LIT> ) ; StartLoc = TokPercent . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> && Tok . getString ( ) == <STR_LIT> ) { RegNo = <STR_LIT> ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; return false ; } if ( RegNo == <NUM_LIT> ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; EndLoc = Tok . getLoc


<s> MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd (


<s> if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < <NUM_LIT> ) { save_mask |= ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; if ( low == <NUM_LIT> ) low = <NUM_LIT> ; if ( high == <NUM_LIT> || low == high ) high = low + <NUM_LIT> ; } pushed_mask = ( - <NUM_LIT> << low ) & ~ ( - <NUM_LIT> << ( high + <NUM_LIT> ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = <NUM_LIT> ; * highest = <NUM_LIT> ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask


<s> return convReg ( BusyRegs [ REG_OFFSET_ADDRESS ]


<s> static SDValue combineLoopMAddPattern ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue MulOp = N -> getOperand ( <NUM_LIT> ) ; SDValue Phi = N -> getOperand ( <NUM_LIT> ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) std :: swap ( MulOp , Phi ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ShrinkMode Mode ; if ( ! canReduceVMulWidth ( MulOp . getNode ( ) , DAG , Mode ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL


<s> unsigned int regno ; unsigned int i ; chunks = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) / UNITS_PER_WORD ; if ( chunks + * arg_words + bias > ( unsigned ) MAX_ARGS_IN_REGISTERS ) chunks = MAX_ARGS_IN_REGISTERS - * arg_words - bias ; ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( chunks ) ) ; bitpos = <NUM_LIT> ; regno = regbase + * arg_words + bias ; field = TYPE_FIELDS ( type ) ; for ( i = <NUM_LIT> ; i < chunks ; i ++ ) { rtx reg ; for ( ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL && int_bit_position ( field ) >= bitpos ) break ; if ( field && int_bit_position ( field ) == bitpos && TREE_CODE ( TREE_TYPE ( field ) ) == REAL_TYPE && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD ) reg = gen_rtx_REG ( DFmode , regno ++ ) ; else reg = gen_rtx_REG ( word_mode , regno ) ; XVECEXP ( ret , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; bitpos += <NUM_LIT> ; regno ++ ; } } } if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> , reg_names [ regbase + * arg_words + bias ] , struct_p ? <STR_LIT> : <STR_LIT> ) ; } if ( mode == VOIDmode


<s> MaxLength = DAG . getZExtOrTrunc ( MaxLength , DL , PtrVT ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src ,


<s> while ( * loc ) loc = & XEXP ( * loc , <NUM_LIT> ) ; * loc = cfa_restores ; RTX_FRAME_RELATED_P ( insn )


<s> if ( ( static_cast < uint8_t > ( data [ <NUM_LIT> ] ) == <ISA_LIT>ELFAttributeData :: Tag_CPU_arch ) && ( ( data [ <NUM_LIT> ] == <ISA_LIT>ELFAttributeData :: CPU_Arch_<ISA_LIT>_V4T ) || ( data [ <NUM_LIT> ] == <ISA_LIT>ELFAttributeData :: CPU_Arch_<ISA_LIT>_V6_M ) ) ) return static_cast < uint32_t > ( data [ <NUM_LIT> ] ) ; return - <NUM_LIT>


<s> return & InstrInfo . getRegisterInfo


<s> SIBBase sibBaseBase = <NUM_LIT> ; uint8_t index , base ; dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> consumedSIB ) return <NUM_LIT> ; insn -> consumedSIB = TRUE ; switch ( insn -> addressSize ) { case <NUM_LIT> : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; break ; case <NUM_LIT> : sibIndexBase = SIB_INDEX_EAX ; sibBaseBase = SIB_BASE_EAX ; break ; case <NUM_LIT> : sibIndexBase = SIB_INDEX_RAX ; sibBaseBase = SIB_BASE_RAX ; break ; } if ( consumeByte ( insn , & insn -> sib ) ) return - <NUM_LIT> ; index = indexFromSIB ( insn -> sib ) | ( xFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( index ) { case <NUM_LIT> : insn -> sibIndex = SIB_INDEX_NONE ; break ; default : insn -> sibIndex = ( SIBIndex ) ( sibIndexBase + index ) ; if ( insn -> sibIndex == SIB_INDEX_sib || insn -> sibIndex == SIB_INDEX_sib64 ) insn -> sibIndex = SIB_INDEX_NONE ; break ; } switch ( scaleFromSIB ( insn -> sib ) ) { case


<s> MCE . addRelocation ( MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue * > ( GV )


<s> unsigned NOps = MI -> getNumOperands ( ) ; assert ( NOps == <NUM_LIT> ) ; OS << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; OS << cast < MDLocalVariable > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) -> getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << '+' ; printOperand ( MI , <NUM_LIT> , OS ) ; OS <<


<s> uint32_t Enc = <STR_LIT> ( - CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand ::


<s> else if ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Latency -= <NUM_LIT> ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isLikeA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ++ Latency ; break ; } return


<s> bool isMEMrr ( ) const { return Kind == k_MemoryReg


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) << markup


<s> unsigned EltSize = Ty . getVectorElementType ( ) . getSizeInBits ( ) ; BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget -> isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue


<s> void <ISA_LIT>FrameLowering :: emitPrologueInsns ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , int NumBytes , bool RequireFPUpdate ) const { DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm (

<NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions >


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode


<s> if ( ! TARGET_32BIT ) return false ; * p1 =


<s> llvm :: FastISel * <STR_LIT> ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! Disable<ISA_LIT>FastISel )

return new <ISA_LIT>FastISel ( funcInfo ) ;


<s> MaxValue = APInt :: getSignedMaxValue ( DstScalarSizeInBits ) . sext ( SrcScalarSizeInBits ) ; } else { MinValue = APInt :: getNullValue ( SrcScalarSizeInBits ) ; MaxValue = APInt :: getLowBitsSet ( SrcScalarSizeInBits , DstScalarSizeInBits ) ; } auto * MinC = Constant :: getIntegerValue ( ArgTy , MinValue ) ; auto * MaxC = Constant :: getIntegerValue ( ArgTy , MaxValue ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg0 , MinC ) , MinC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg1 , MinC ) , MinC , Arg1 ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg0 , MaxC ) , MaxC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg1 , MaxC ) , MaxC , Arg1 ) ; SmallVector < int , <NUM_LIT> > PackMask ; for ( unsigned Lane = <NUM_LIT> ; Lane


<s> return ( __m512 ) __builtin_ia32_loadups512_mask ( ( const __v16sf * ) __P , ( __v16sf


<s> named_section_real ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ; named_section_flags ( rname , SECTION_WRITE


<s> return ( int32x2_t ) __builtin_neon_vreinterpretv2siv4hi (


<s> Use64BitRegs = false ; UseCRBits = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx =


<s> return ( __m128d ) __builtin_ia32_extractf64x2_512_mask ( ( __v8df ) __A , __imm , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 )


<s> if ( ! I ) return false ; if ( I -> getSrcTy ( ) -> getIntegerBitWidth ( ) != BitWidth ) return false ; return isa < LoadInst > ( I -> getOperand


<s> void Emitter :: emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) { intptr_t RelocCST = ( Reloc == <STR_LIT> ) ? PICBaseOffset : <NUM_LIT> ; MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc


<s> if ( BinOp && isa < OverflowingBinaryOperator > ( BinOp ) && ( BinOp -> hasNoUnsignedWrap ( ) || BinOp -> hasNoSignedWrap ( ) ) ) return true ; if ( isa < TruncInst > ( Inst ) && isa <

SExtInst > ( Inst -> getOperand ( <NUM_LIT> ) ) ) {


<s> if ( ! isUndefHI && ! V1 -> isUndef ( ) ) HI = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V1_LO , V1_HI ) ; } else { if ( ! isUndefLO && ( ! V0_LO -> isUndef ( ) || ! V1_LO -> isUndef ( ) ) ) LO = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_LO , V1_LO ) ; if ( ! isUndefHI && ( ! V0_HI -> isUndef ( ) || ! V1_HI -> isUndef ( ) ) ) HI = DAG . getNode

( <ISA_LIT>Opcode , DL , NewVT , V0_HI , V1_HI ) ;


<s> if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> bool mep_allow_clip ( rtx ux , rtx lx , int s ) { HOST_WIDE_INT u = INTVAL ( ux ) ; HOST_WIDE_INT l = INTVAL ( lx ) ; int i ; if ( ! TARGET_OPT_CLIP ) return false ; if ( s ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( u == ( ( HOST_WIDE_INT ) <NUM_LIT> << i ) - <NUM_LIT> ) && ( l == - ( ( HOST_WIDE_INT ) <NUM_LIT> << i ) ) ) return true ; } else { if ( l != <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( u == ( ( HOST_WIDE_INT ) <NUM_LIT> << i ) - <NUM_LIT> ) ) return true ; } return false


<s> if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment


<s> return ( __m64 ) __builtin_arm_wmaxsw ( ( __v2si ) __A , ( __v2si )


<s> void <ISA_LIT>PassConfig :: addPreSched2 (


<s> SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; unsigned Align = Node -> getConstantOperandVal ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Node ) ; unsigned ArgSlotSizeInBytes = ( Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue VAListLoad = DAG . getLoad ( getPointerTy ( ) , DL , Chain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ; SDValue VAList =


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT> , Base


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { return ( memory_operand ( op1 , mode ) ? and_load_operand ( op2

, mode ) : and_reg_operand ( op2 , mode ) ) ;


<s> static inline bool isAdvSIMDModImmType7 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm & <NUM_LIT>


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg +=


<s> struct stat st ; if ( stat ( name , & st ) < <NUM_LIT>

|| S_ISDIR ( st . st_mode ) ) return - <NUM_LIT> ;


<s> for ( auto * I : Incomings ) { User * Store = createTileStore ( I , I8Ptr ) ; for ( Use & U : I -> uses ( ) ) { User * V = U . getUser ( ) ; if ( isa < PHINode > ( V ) || V == Store ) continue ; replaceWithTileLoad ( U ,


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = <NUM_LIT> ; unsigned int offset = <NUM_LIT> ; if ( ! TARGET_64BIT ) return <NUM_LIT> ; if ( pa_function_arg_size ( arg . mode , arg . type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset


<s> if ( TARGET_MULTIPLE && ! TARGET_POWERPC64 && ! ( TARGET_SPE_ABI && info -> spe_64bit_regs_used ) && info -> first_gp_reg_save < <NUM_LIT> && ! global_regs_p ( info -> first_gp_reg_save , <NUM_LIT> ) ) strategy |= SAVRES_MULTIPLE ; if ( crtl -> calls_eh_return || cfun -> machine -> ra_need_lr ) strategy |= ( SAVE_INLINE_FPRS | REST_INLINE_FPRS | SAVE_INLINE_GPRS | REST_INLINE_GPRS | SAVE_INLINE_VRS | REST_INLINE_VRS ) ; if ( info -> first_fp_reg_save == <NUM_LIT> || ( TARGET_HARD_FLOAT && ! TARGET_DOUBLE_FLOAT ) || global_regs_p ( info -> first_fp_reg_save , <NUM_LIT> ) ) strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS ; if ( info -> first_gp_reg_save == <NUM_LIT> || ( ! ( strategy & SAVRES_MULTIPLE ) && global_regs_p ( info -> first_gp_reg_save , <NUM_LIT> ) ) ) strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS ; if ( info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + <NUM_LIT> || global_regs_p ( info -> first_altivec_reg_save , LAST_ALTIVEC_REGNO + <NUM_LIT> ) ) strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS ; if ( DEFAULT_ABI == ABI_V4 || TARGET_ELF ) { if ( ! optimize_size ) { strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS ; strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS ; strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS ; } else { if ( info -> first_fp_reg_save > <NUM_LIT> ) strategy |= SAVE_INLINE_FPRS ; if ( info -> first_gp_reg_save > <NUM_LIT> ) { if ( info -> first_fp_reg_save == <NUM_LIT> ) strategy |= SAVE_INLINE_GPRS ; else strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS ; } if ( info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO ) strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS ; } } else if ( DEFAULT_ABI == ABI_DARWIN


<s> if ( is<ISA_LIT>64 ( ) ) return getReg ( <STR_LIT> , Reg ) ; return getReg ( <STR_LIT> ,


<s> case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEVectorMul ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorFAdd ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorBinOp ( IC , II ) ; case <STR_LIT> : return instCombineSVETBL ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEUnpack ( IC , II ) ; case <STR_LIT> : return instCombineSVETupleGet ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEZip ( IC , II ) ; case <STR_LIT> : return instCombineLD1GatherIndex ( IC , II ) ; case <STR_LIT> : return instCombineST1ScatterIndex ( IC


<s> rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP (


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineFunction & MF , MCSymbol * Label , unsigned FramePtr ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = TM .


<s> static void reset ( ) { Blocks . clear ( ) ; PredicatedInsts . clear ( ) ; CurrentPredicates . clear ( )


<s> else if ( MASK_REGNO_P ( regno ) ) return HImode ; else if ( MMX_REGNO_P ( regno ) )


<s> if ( TYPE_MODE ( fromtype ) == RFmode && TYPE_MODE ( totype ) != RFmode && TYPE_MODE ( totype ) != VOIDmode ) return N_ ( <STR_LIT> ) ; if ( TYPE_MODE ( totype ) == RFmode && TYPE_MODE ( fromtype ) != RFmode ) return N_ ( <STR_LIT> ) ; return NULL


<s> if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; if ( ! Subtarget . isThumb ( ) && ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> +

Subtarget . getCPUString ( ) + <STR_LIT> <STR_LIT> ) ;


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc )


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb ( ) ? <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: isADDIInstrEligibleForFolding ( MachineInstr & ADDIMI , int64_t & Imm ) const { unsigned Opc = ADDIMI . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> )


<s> decl = NULL ; } if ( ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align <


<s> const uint64_t ChunkVal = Chunk -> first ; const unsigned Count = Chunk -> second ; uint64_t Encoding = <NUM_LIT> ; if ( ( Count != <NUM_LIT> && Count != <NUM_LIT> ) || ! canUseOrr ( ChunkVal , Encoding ) ) continue ; const bool CountThree = Count == <NUM_LIT> ; Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt +=


<s> ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( Op ) -> getMask ( ) ; if ( VT . getVectorElementType ( ) != V0 . getValueType ( ) . getVectorElementType ( ) || VT . getVectorElementType ( ) != V1 . getValueType ( ) . getVectorElementType ( ) ) return SDValue ( ) ; bool SplitV0 = V0 . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ; if ( ! isConcatMask ( Mask , VT , SplitV0 ) ) return SDValue ( ) ; EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / <NUM_LIT> ) ; if ( SplitV0 ) { V0 = DAG . getNode ( <STR_LIT> , DL , CastVT , V0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( V1 . getValueType ( ) . getSizeInBits ( ) ==


<s> setCondCodeAction ( <STR_LIT> , VT , Expand ) ; setCondCodeAction ( <STR_LIT> , VT , Expand ) ; setCondCodeAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom )


<s> PM . add ( create<ISA_LIT>BranchSelectionPass ( ) ) ; return false


<s> rtx tmp = gen_frame_mem ( Pmode , plus_constant ( Pmode , hard_frame_pointer_rtx , UNITS_PER_WORD


<s> void <ISA_LIT>ConstantIslands :: verify ( MachineFunction & MF ) { assert ( BBOffsets . size ( ) == BBSizes . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = BBOffsets . size ( ) ; i != e ; ++ i ) assert ( BBOffsets [ i - <NUM_LIT> ] + BBSizes [ i - <NUM_LIT> ] == BBOffsets [ i ] ) ; if ( ! isThumb ) return ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , E = MF . end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB =


<s> static int arm_barrier_cost ( rtx insn ) { int base_cost = <NUM_LIT> ; rtx next = next_nonnote_insn ( insn ) ; if ( next != NULL && LABEL_P ( next ) ) base_cost -= <NUM_LIT> ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return <NUM_LIT> ; case INSN


<s> bool mmix_frame_pointer_required ( void ) { return ( cfun -> has_nonlocal_label )


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> )


<s> if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores


<s> maxoff = <NUM_LIT> ; if ( vcall_offset > maxoff || vcall_offset < - maxoff ) fprintf ( file , <STR_LIT> ) ; else if ( delta > maxoff || delta < - maxoff ) fprintf ( file , <STR_LIT> ) ; } if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) thiz = <STR_LIT> ; if ( delta != <NUM_LIT> ) { if ( delta > maxoff || delta < - maxoff ) { fprintf ( file , <STR_LIT> , reg0 , ( long ) delta ) ; fprintf ( file , <STR_LIT> , thiz , thiz , reg0 ) ; } else fprintf ( file , <STR_LIT> , ( delta > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , thiz , thiz , ( long ) ( delta > <NUM_LIT> ? delta : - delta ) ) ; } if ( vcall_offset != <NUM_LIT> ) { fprintf ( file , <STR_LIT> , reg0 , thiz ) ; if ( vcall_offset > maxoff || vcall_offset < - maxoff ) { fprintf ( file , <STR_LIT> , reg1 , ( long ) vcall_offset ) ; fprintf ( file , <STR_LIT> , reg0 , reg0 , reg1 ) ; } else fprintf ( file , <STR_LIT> , ( vcall_offset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , reg0 , reg0 , ( long ) ( vcall_offset > <NUM_LIT> ? vcall_offset : - vcall_offset ) ) ; fprintf ( file , <STR_LIT> , reg0 , reg0


<s> assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = ! isPredicated ( I ) ; } else { return true ; } if ( ! isPredicated ( I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . end


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm (


<s> } MVT WideVT = ExtVT ; if ( ! ExtVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { NumElts *= <NUM_LIT> / ExtVT . getSizeInBits ( ) ; InVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; In = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getUNDEF ( InVT ) , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; WideVT = <STR_LIT> ( ExtVT . getVectorElementType ( ) , NumElts ) ; } SDValue V ; MVT WideEltVT = WideVT . getVectorElementType ( ) ; if ( ( Subtarget . hasDQI ( ) && WideEltVT . getSizeInBits ( ) >= <NUM_LIT> ) || ( Subtarget . hasBWI ( ) && WideEltVT . getSizeInBits ( ) <= <NUM_LIT> ) ) { V = DAG . getNode ( <STR_LIT> , dl , WideVT , In ) ; } else { SDValue NegOne = getOnesVector ( WideVT , DAG ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateShiftExtend ( <STR_LIT> ShOp , unsigned Val , bool HasExplicitAmount , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ShiftExtend , Ctx ) ; Op -> ShiftExtend . Type = ShOp ; Op -> ShiftExtend . Amount = Val ; Op -> ShiftExtend . HasExplicitAmount = HasExplicitAmount ; Op -> StartLoc = S ; Op -> EndLoc =


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { <ISA_LIT>AddressMode AM


<s> vtrn_s16 ( int16x4_t a , int16x4_t b ) { return ( int16x4x2_t ) { vtrn1_s16 ( a , b ) , vtrn2_s16


<s> case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail : Out = In ; return false ; } llvm_unreachable ( <STR_LIT> )


<s> if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP


<s> return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpStore ( Node , DataN , DataN . getOperand ( <NUM_LIT> ) , DataN . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpStore ( Node , DataN , DataN . getOperand ( <NUM_LIT> ) , DataN . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; } if ( SDNode * ResNode = SelectIndexedStore ( Node ) ) return ResNode ; } break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> MCTargetStreamer & TS = * getParser ( ) . getStreamer


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlignment ( * RC ) ) ; FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx


<s> tmpInst . addOperand ( MCOperand :: createExpr ( HighestExpr ) ) ; Instructions . push_back ( tmpInst ) ; createLShiftOri < <NUM_LIT> > ( MCOperand :: createExpr ( HigherExpr ) , TmpReg , SMLoc ( ) , Instructions ) ; createLShiftOri < <NUM_LIT> > ( MCOperand :: createExpr ( HiExpr ) , TmpReg , SMLoc ( ) , Instructions ) ; createLShiftOri < <NUM_LIT> > ( MCOperand :: createExpr ( LoExpr ) , TmpReg , SMLoc ( ) , Instructions ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( TmpReg ) ) ; tmpInst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; Instructions . push_back ( tmpInst ) ; emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , SMLoc ( ) , Instructions ) ; } if ( UseSrcReg ) createAddu ( DstReg , TmpReg , SrcReg , ! Is32BitSym , Instructions ) ; return


<s> bool runOnFunction ( Function & F ) override { this -> F = & F ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo (


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ; return false


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NumElts = MRI . getType ( Dst ) . getNumElements ( ) ; if ( ! isZipMask ( ShuffleMask , NumElts , WhichResult ) ) return false ; unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register V1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register V2 = MI . getOperand ( <NUM_LIT>


<s> EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getSetCC ( DL , CCVT , Op , FPZero ,


<s> return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } load = REG_P ( recog_data . operand [ <NUM_LIT> ] ) ; reg = recog_data . operand [ ! load ] ; mem = recog_data . operand [ load ] ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( reg ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == LABEL_REF || GET_CODE ( addr ) == PLUS ) { int insns = HARD_REGNO_NREGS ( REGNO ( reg ) , mode ) / <NUM_LIT> ; return insns * <NUM_LIT> ; } else return <NUM_LIT>


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( )


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue (


<s> MachineBasicBlock * LoopExit = getWhileLoopStartTargetBB ( * WlsInstr ) ; if ( ! LoopExit -> getPrevNode ( ) ) return false ; if ( blockIsBefore ( Predecessor , LoopExit ) ) return false ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << Predecessor -> getFullName ( ) << <STR_LIT> << LoopExit -> getFullName ( ) << <STR_LIT> ) ; for ( auto It = ++ LoopExit -> getIterator ( ) ; It != Predecessor -> getIterator ( ) ; ++ It ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( ! isWhileLoopStart ( Terminator ) ) continue ; MachineBasicBlock * WLSTarget = getWhileLoopStartTargetBB ( Terminator ) ; if ( WLSTarget == Predecessor ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> <STR_LIT> ) ; return revertWhileToDo ( WlsInstr


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCoprocReg ( unsigned CopVal , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > (


<s> static bool MorphToQuadReg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; unsigned regIdx = <NUM_LIT> ; switch ( Op . Reg . Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case rk_FloatReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; case rk_DoubleReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; } Op . Reg . RegNum = Reg ; Op . Reg .


<s> return DecodeVecShiftLImm ( Inst , Imm ,


<s> SDValue Index = N -> getIndex ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( IndexVT == <STR_LIT> ) return SDValue ( ) ; MVT OrigVT = VT ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! IndexVT . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; PassThru = ExtendToType ( PassThru , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N -> getScale ( ) } ; SDValue NewGather = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , OrigVT ,

NewGather , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> if ( Code16GCC ) SwitchMode ( <STR_LIT> ) ; unsigned rv = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MissingFeatures , matchingInlineAsm , VariantID ) ; if ( Code16GCC ) SwitchMode ( <STR_LIT> ) ; return rv


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasNEON ( ) || ! Op . getValueType ( ) . isVector ( ) || Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; uint64_t C ; SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , <STR_LIT> ) ,

N0 , DAG . getConstant ( Log2_64 ( C ) , <STR_LIT> ) ) ;


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3


( <STR_LIT> , DL , <STR_LIT> , V2 ) , Mask ) ) ;


<s> isLarge = true ; } ( Inst . getOperand ( <NUM_LIT> ) ) . setImm ( Shift ) ; if ( isLarge ) switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT>


<s> if ( SrcReg != <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else { NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { if ( ( Enable<ISA_LIT>32RS && ! TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ) || ( Enable<ISA_LIT>64RS && TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else { NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned ShiftBits = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ; NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ShiftBits ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { unsigned Reg = <NUM_LIT> ; if ( SrcReg >= <STR_LIT> || SrcReg <= <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg >= <STR_LIT> || SrcReg <= <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg >= <STR_LIT> || SrcReg


<s> <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry XOPCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry X64CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry <ISA_LIT>CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; unsigned ISD = <STR_LIT> ; switch ( IID ) { default : break ; case <STR_LIT> : ISD = <STR_LIT> ; if ( Args [ <NUM_LIT> ] == Args [ <NUM_LIT> ] )


<s> uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto PStateMapper = <STR_LIT> ( ) ; uint32_t PStateField = PStateMapper . fromString ( Tok . getString ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> )


<s> if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , <NUM_LIT> ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - <NUM_LIT> ) ; return TargetLowering :: getSafeStackPointerLocation


<s> static unsigned int arm_elf_section_type_flags ( tree decl , const char *


<s> if ( SrcVT == <STR_LIT> ) return Op ; if ( SrcVT == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) { SDNodeFlags Flags ; Flags . setNoFPExcept ( Op -> getFlags ( ) . hasNoFPExcept ( ) ) ; if ( IsSigned ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Op . getOperand ( <NUM_LIT> ) , Lo , Hi } , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Res . getValue ( <NUM_LIT> ) , Res } , Flags ) ; } else { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } } else { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Cst = DAG . getConstantFP ( APF , dl , SrcVT ) ; SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , DstVT ) ; if ( IsStrict


<s> unsigned getNumFixupKinds ( ) const { return <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = <STR_LIT> ; Cost = <NUM_LIT> ; break ; } return std :: make_pair ( RRC ,


<s> SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , VT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; if ( HasShuffleIntoBitcast ) { unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = TLI . getDataLayout ( ) -> getABITypeAlignment ( VT . getTypeForEVT (


<s> machine_mode mode = TYPE_MODE ( TREE_TYPE ( fndecl ) ) ; if ( ! use_rsqrt_p ( mode ) ) return NULL_TREE ; return aarch64_builtin_rsqrt ( DECL_FUNCTION_CODE (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , usingPBQP ( false ) { initAsmInfo ( ) ; if ( EnablePBQP && Subtarget . isCortexA57 ( ) && OL != CodeGenOpt :: None ) { usingPBQP =


<s> using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Type * Ty = Input -> getType ( ) ; if ( ! ( Ty -> getVectorNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , {

Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input } ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage


<s> switch ( I -> Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I ->


<s> const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypePaddedSize ( GV -> getType ( ) -> getElementType ( ) ) ; unsigned Threshold = Subtarget -> getSSectionThreshold ( ) ; if ( Size > <NUM_LIT> && Size <= Threshold ) { if ( K == SectionKind :: BSS ) return SectionKind :: SmallBSS ; else return SectionKind ::


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand ::


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { if ( STI . hasE2 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( DestReg < <STR_LIT> ) ; assert ( DestReg < <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define ) . addReg ( SrcReg , RegState :: Define ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SrcReg << <STR_LIT> << DestReg ) ; LLVM_DEBUG ( I -> dump ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , I , DL , get ( Opcode ) , DestReg ) . addReg (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI


<s> } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; if ( ! MI . killsRegister ( <STR_LIT> ) && ! checkCCKill ( MI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: tracePredStateThroughCall ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; auto InsertPt = MI . getIterator ( ) ; DebugLoc Loc = MI . getDebugLoc ( ) ; unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn


<s> case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; default : llvm_unreachable ( <STR_LIT> )


<s> return TFI -> hasFP ( MF ) ? ( <STR_LIT> ) : ( <STR_LIT>


<s> bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , <STR_LIT> ) == <NUM_LIT> ) return true ; tree old_optimize = build_optimization_node ( & global_options ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes = false ; PrivateGlobalPrefix =


<s> int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( M > HalfSize ) return SDValue ( ) ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ; } return SDValue ( ) ; } if ( Idx < <NUM_LIT> ) return SDValue ( ) ; assert ( ( Idx + Len ) <= HalfSize && <STR_LIT> ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue


<s> if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ; if ( to_type == from_type && IS_STD_REG_TYPE ( to_type


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isRegMask ( ) ) { const uint32_t * RegMask = MO . getRegMask ( ) ; for ( MCPhysReg Reg : <STR_LIT> ) handleRegMaskClobber ( RegMask , Reg , LOHInfos ) ; for ( MCPhysReg Reg : <STR_LIT> ) handleRegMaskClobber ( RegMask , Reg , LOHInfos ) ; continue ; } if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; int Idx = mapRegToGPRIndex ( MO . getReg ( ) ) ; if ( Idx < <NUM_LIT> ) continue ; handleClobber ( LOHInfos [ Idx ] ) ; } SmallSet < int , <NUM_LIT> > UsesSeen ; for ( const MachineOperand & MO : MI . uses


<s> unsigned ResultReg ; if ( I -> getOpcode ( ) == Instruction :: Add ) ResultReg = emitAdd ( VT , I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ; else if ( I -> getOpcode ( ) == Instruction :: Sub ) ResultReg = emitSub ( VT , I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; assert ( ResultReg && <STR_LIT>


<s> <ISA_LIT>_64GNULDBackend & ld_backend = pParent . getTarget ( ) ; assert ( pParent . getSymGOTMap ( ) . lookUp ( * rsym ) == NULL ) ; <ISA_LIT>_64GOTEntry * got_entry = ld_backend . getGOT ( ) . create ( ) ; pParent . getSymGOTMap ( ) . record ( * rsym , * got_entry ) ; if ( ! pHasRel ) { got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; } else { if ( helper_use_relative_reloc ( * rsym , pParent ) ) { Relocation & rel_entry = helper_DynRel_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_<ISA_LIT>_64_RELATIVE , pParent ) ; rel_entry . setAddend ( <ISA_LIT>Relocator :: SymVal


<s> if ( ! Node -> isMachineOpcode ( ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return <NUM_LIT> ; unsigned Opcode = Node -> getMachineOpcode ( ) ; switch ( Opcode ) { default : return ItinData -> getStageLatency ( get ( Opcode ) . getSchedClass ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned FP = RegInfo -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( Subtarget -> isR9Reserved ( ) ?


<s> case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS8 ; break ; } break ; case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS16 ; break ; } break ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_SBREL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ : Type = ELF :: R_<ISA_LIT>_TLS_DESCSEQ ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case


<s> if ( VT . isScalableVector ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI


<s> expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , true ) ; break ; case <STR_LIT>


<s> ~ <ISA_LIT>AsmBackend ( ) override { delete STI


<s> default : gcc_unreachable ( ) ; } break ; case LTU : if ( mode == CCmode || mode == CCGZmode ) suffix = <STR_LIT> ; else if ( mode == CCCmode ) suffix = fp ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; break ; case GE : switch ( mode ) { case E_CCNOmode : case E_CCGOCmode : suffix = <STR_LIT> ; break ; case E_CCmode : case E_CCGCmode : case E_CCGZmode : suffix = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case GEU : if ( mode == CCmode || mode == CCGZmode ) suffix = <STR_LIT> ; else if ( mode == CCCmode ) suffix = fp ? <STR_LIT> : <STR_LIT> ; else gcc_unreachable ( ) ; break ; case LE : gcc_assert ( mode == CCmode || mode == CCGCmode || mode == CCNOmode ) ; suffix = <STR_LIT> ; break ; case LEU : if ( mode == CCmode ) suffix = <STR_LIT> ; else gcc_unreachable ( ) ; break ; case UNORDERED : suffix = fp ? <STR_LIT> : <STR_LIT> ; break ; case ORDERED : suffix = fp ? <STR_LIT> : <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } fputs ( suffix


<s> assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( ) ) ; assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: Create ( getSymbol ( GV ) , ( Subtarget -> isTargetDarwin

( ) ? MCSymbolRefExpr :: VK_None : MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 ) , OutContext ) ;


<s> MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~


<s> MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( M -> getPICLevel ( ) == PICLevel :: Small ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF


<s> FrameEscape = <STR_LIT> ( TheModule , <STR_LIT> ) ; FrameRecover = <STR_LIT> ( TheModule , <STR_LIT> ) ; FrameAddress = <STR_LIT> ( TheModule , <STR_LIT> ) ; RestoreFrame = <STR_LIT> ( TheModule , <STR_LIT> ) ; return


<s> int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT>


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , S , E ) ) ; return MatchOperand_Success ; } bool haveEaten = false ; bool isAdd = true ; if ( Tok . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; haveEaten = true ; } else if ( Tok . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; isAdd = false ; haveEaten = true ; } Tok = Parser . getTok ( ) ; int Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { if ( ! haveEaten ) return MatchOperand_NoMatch ; Error ( Tok . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_1 : case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 : case


<s> if ( ! call_insn_operand ( fn , VOIDmode ) )


<s> if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! VecIn1 . getNode ( ) ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( ! VecIn2 . getNode ( ) ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; } if ( ! VecIn1 . getNode ( ) ) return SDValue ( ) ; VecIn2 = VecIn2 . getNode ( ) ? VecIn2 : DAG . getUNDEF ( VT ) ; SDValue NV = DAG . getVectorShuffle ( VT , DL , VecIn1 , VecIn2 , & Mask [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> , e = InsertIndices . size ( ) ; i != e ; ++ i ) { unsigned Idx = InsertIndices [ i ] ; NV = DAG . getNode ( <STR_LIT> , DL , VT , NV ,

Op . getOperand ( Idx ) , DAG . getIntPtrConstant ( Idx ) ) ;


<s> emit_insn ( gen_rtx_SET ( gen_rtx_REG ( BImode , SR_F_REGNUM ) , gen_rtx_fmt_ee ( code ,


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) )


<s> return hasSSE1 ( ) || ( hasPRFCHW ( ) &&

! has3DNow ( ) ) || hasPREFETCHWT1 ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } TypeSize ScaleValue ( <NUM_LIT> , false ) ; unsigned Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = ScaleValue . isScalable ( ) ; unsigned Scale = ScaleValue . getKnownMinSize ( ) ; int64_t Offset = IsMulVL ? SOffset . getScalable ( ) : SOffset . getFixed ( ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; Scale = ScaleValue . getKnownMinSize ( ) ; assert ( IsMulVL == ScaleValue . isScalable (


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; return lower<ISA_LIT>FPLogicOp ( N , DAG , Subtarget


<s> bool isNEONmovReplicate ( ) const { checkNeonReplicateArgs ( FromW , ToW ) ; bool AllowMinusOne = ToW


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; else { reportParseError ( <STR_LIT> ) ; return false ; } TmpReg . clear ( ) ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & ReturnRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! ReturnRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( ReturnRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitFrame ( StackReg , FrameSizeVal , ReturnRegOpnd . getGPR32Reg ( ) ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { const MCExpr * BitMask ; int64_t BitMaskVal ; if ( Parser . parseExpression ( BitMask ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! BitMask -> EvaluateAsAbsolute ( BitMaskVal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; else { reportParseError ( <STR_LIT> ) ; return false ; } const MCExpr * FrameOffset ; int64_t FrameOffsetVal ; if ( Parser . parseExpression ( FrameOffset ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! FrameOffset -> EvaluateAsAbsolute ( FrameOffsetVal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( IDVal == <STR_LIT> ) getTargetStreamer ( ) . emitMask ( BitMaskVal , FrameOffsetVal ) ; else getTargetStreamer ( ) . emitFMask ( BitMaskVal , FrameOffsetVal ) ; return false ; } if ( IDVal == <STR_LIT> ) return parseDirectiveNaN ( ) ; if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpDWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDataDirective ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; if ( IDVal == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveAbiCalls


<s> if ( ( dyn_rel != NULL ) && ( <ISA_LIT>Relocator :: SymVal == dyn_rel -> addend ( ) ) ) { dyn_rel -> setAddend ( S ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( pParent . getTarget ( ) . symbolNeedsDynRel ( * rsym , ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) , false ) ) { return Relocator :: Overflow ; } } pReloc . target ( ) = S + A - P ; return Relocator ::