<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] =


<s> } if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> unsigned OffField = MI -> getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField ; int Offset = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> ( OffField ) * <NUM_LIT> ; if (


<s> SDValue StoredVal = Store -> getValue ( ) ; assert ( StoredVal . getValueType ( ) . is256BitVector ( ) && <STR_LIT> ) ; if ( Store -> isVolatile ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; SDLoc DL ( Store ) ; SDValue Value0 = extract128BitVector ( StoredVal , <NUM_LIT> , DAG , DL ) ; SDValue Value1 = extract128BitVector ( StoredVal , NumElems / <NUM_LIT> , DAG , DL ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , <NUM_LIT> , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , MinAlign ( Alignment , <NUM_LIT> ) , Store -> getMemOperand ( )


<s> case TYPE_DPACK : case TYPE_DINSB : case TYPE_DCMP : case TYPE_DCLIP : case TYPE_DALUROUND : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : case TYPE_DMAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , <NUM_LIT> ) ) ; else use_rtx = SET_SRC ( PATTERN


<s> unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { unsigned Align = getStackAlignment ( ) ; int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount = alignTo ( Amount , Align ) ; if ( ! IsDestroy ) Amount = - Amount ; if ( CalleePopAmount == <NUM_LIT> ) { assert ( Amount > - <NUM_LIT> && Amount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , Amount , TII ) ; } } else if ( CalleePopAmount != <NUM_LIT> ) { assert ( CalleePopAmount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , - CalleePopAmount , TII ) ; } return MBB . erase (


<s> void <ISA_LIT>InstPrinter :: printMatrixIndex ( const MCInst * MI , unsigned OpNum

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> unsigned Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) . addImm ( ( unsigned ) Pred ) .

addReg ( PredReg ) . addReg ( <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; EVT DstTy = Op . getValueType ( ) ; SDValue Value = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT TheVT = Value . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return SDValue ( ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> ; if ( ! IsSigned && DstTy != <STR_LIT> ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; if ( IsStrict ) Chain = Op . getOperand ( <NUM_LIT> ) ; else Chain = DAG . getEntryNode ( ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext

( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ;


<s> if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; unsigned ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( cast < VectorType > ( VecTy ) -> getElementType ( ) , cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ) ; unsigned NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; unsigned NumOfMoves


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , false , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ,


<s> bool IsStrict = N -> isStrictFPOpcode ( ) || N -> isTargetStrictFPOpcode ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue B = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue C = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDNodeFlags Flags = N -> getFlags ( ) ; if ( ! IsStrict && Flags . hasAllowReassociation ( ) && TLI . isOperationExpand ( <STR_LIT> , VT ) ) { SDValue Fmul = DAG . getNode ( <STR_LIT> , dl , VT , A , B , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fmul , C , Flags ) ; } EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; auto invertIfNegative = [ & DAG , & TLI , & DCI ] ( SDValue & V ) { bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( V , DAG , LegalOperations , CodeSize ) ) { V = NegV ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( Vec , DAG , LegalOperations , CodeSize ) ) { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegV , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , NegA != NegB , NegC , false ) ; if ( IsStrict ) { assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( NewOpcode , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , A , B , C } ) ; } else { if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT

, A , B , C , N -> getOperand ( <NUM_LIT> ) ) ;


<s> return JumpTableEntryInfo . find ( Idx )


<s> case 'A' : if ( ! printSymbolicAddress ( MI -> getOperand ( OpNum ) , false , <STR_LIT> , O ) ) return false ; break ; case 'L' : if ( ! printSymbolicAddress ( MI -> getOperand ( OpNum ) , true , <STR_LIT> , O ) ) return false ; break ; case 'G' : if ( ! printSymbolicAddress ( MI -> getOperand ( OpNum ) , true , <STR_LIT> , O ) ) return false ; break ; case 'a' : return PrintAsmMemoryOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; } const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( printModifiedFPRAsmOperand ( MO , TRI , 'v' , O ) ) O <<

<ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ;


<s> if ( XVECLEN ( pattern , <NUM_LIT> ) != <NUM_LIT> ) return false ; rtx set = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( set ) != SET ) return false ; rtx clobber = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( clobber ) != CLOBBER ) return false ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; rtx scratch = SET_DEST ( clobber ) ; if ( GET_CODE ( src ) != UNSPEC ) return false ; if ( XINT ( src , <NUM_LIT> ) == UNSPEC_SI_FROM_SF && GET_CODE ( dest ) == MEM && GET_MODE ( dest ) == SImode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == V4SFmode ) return true ; if ( XINT ( src , <NUM_LIT> ) == UNSPEC_SF_FROM_SI && GET_CODE ( dest ) == REG && GET_MODE ( dest ) == SFmode && GET_CODE ( scratch ) == SCRATCH &&

GET_MODE ( scratch ) == DImode ) return true ;


<s> CALL_ONCE_INITIALIZATION ( initializePassOnce


<s> unsigned TargetAlign = Target . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask


<s> return parseAddress ( Operands , BDMem , <STR_LIT> ,


<s> return ( __m128i ) __builtin_ia32_broadcasti32x2_128_mask ( ( __v4si ) __A , (


<s> setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; setAttributeItem ( <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : case <STR_LIT>


<s> NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> &&


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; EVT SVT = N0 . getValueType ( ) ; SDLoc dl ( Op ) ; assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl ,


<s> static int sh_address_cost ( rtx x , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return <NUM_LIT> ; if ( REG_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == GBR_REG && gbr_displacement ( XEXP ( x , <NUM_LIT> ) , mode ) ) return <NUM_LIT> ; const HOST_WIDE_INT offset = INTVAL ( XEXP (


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode ,


<s> if ( Reg == <STR_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> pshufh_u ( uint16x4_t dest , uint16x4_t s , uint8_t order ) { return __builtin_loongson_pshufh_u ( s , order


<s> bool isU16Imm ( ) const { return isExtImm < <NUM_LIT> > ( false ,


<s> } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetArchDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFpDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPopDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPushDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>0Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature (


<s> return ( float32x2_t ) __builtin_neon_vld1_dupv2sf ( ( const __builtin_neon_sf


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) ,


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT>


<s> static DecodeStatus DecodeTAddrModeImm7 ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm , Address , Decoder ) )


<s> ConstantSDNode * ConstOpOrElement = isConstOrConstSplat ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ConstOpOrElement ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) && isOperationLegal ( <STR_LIT> , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto IsProfitable = [ this ] ( bool IsNeg , bool IsAddOne , EVT VT ) -> bool { switch ( this -> Subtarget . getCPUDirective ( ) ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , false , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs + <NUM_LIT> ) .


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_resume ( void ) { __builtin_tresume (


<s> void <ISA_LIT>FrameLowering :: emitStackProbeInlineGeneric ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { MachineInstr & AllocWithProbe = * MBBI ; uint64_t Offset = AllocWithProbe . getOperand ( <NUM_LIT> ) . getImm ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; assert ( ! ( STI . is64Bit ( ) && STI . isTargetWindowsCoreCLR ( ) ) && <STR_LIT> ) ; const uint64_t StackProbeSize = TLI . getStackProbeSize ( MF ) ; uint64_t ProbeChunk = StackProbeSize * <NUM_LIT> ; uint64_t MaxAlign = TRI -> hasStackRealignment ( MF ) ? calculateMaxStackAlign ( MF ) : <NUM_LIT> ; if ( Offset > ProbeChunk ) { emitStackProbeInlineGenericLoop ( MF , MBB , MBBI , DL , Offset , MaxAlign % StackProbeSize ) ; } else { emitStackProbeInlineGenericBlock ( MF , MBB , MBBI , DL


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , Subtarget -> is64Bit ( )


<s> temp = ( __v4si ) vec_splats ( __A ) ; tmp2 = ( __v2di ) vec_unpackl ( temp ) ; result = vec_ctf ( ( __vector signed long


<s> result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , <NUM_LIT> ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result .


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg ,


<s> computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> bool useFPVFMx64 ( ) const { return useFPVFMx ( ) && hasFP64 (


<s> return xmalloc ( sizeof ( rs6000_sched_context_def


<s> unsigned CmpVal = MRI . createVirtualRegister ( RC ) ; unsigned SwapVal = MRI . createVirtualRegister ( RC ) ; unsigned StoreVal = MRI . createVirtualRegister ( RC ) ; unsigned RetryOldVal = MRI . createVirtualRegister ( RC ) ; unsigned RetryCmpVal = MRI . createVirtualRegister ( RC ) ; unsigned RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * SetMBB = emitBlockAfter ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB -> addSuccessor ( SetMBB ) ; MBB = SetMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetrySwapVal ) . addReg ( SwapVal ) . addReg


<s> if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDValue In64 ; if ( Subtarget . hasHighWord ( ) ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; } else { In64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; In64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; } if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDValue In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable


<s> MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor (


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( The<ISA_LIT>64Target ) ; RegisterAsmInfoFn C ( The<ISA_LIT>32Target , createMCAsmInfo


<s> if ( shift == <NUM_LIT> && Memory . ShiftType != <STR_LIT> ) return false ; if ( shift > <NUM_LIT> && ( Memory . ShiftType != <STR_LIT> || Memory . ShiftImm != shift ) ) return false ; return true


<s> SDValue getAddrLocal ( NodeTy * N , EVT Ty , SelectionDAG & DAG , bool IsN32OrN64 ) const { SDLoc DL ( N ) ; unsigned GOTFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; const RegisterBank & DstRB = * RBI . getRegBank ( Dst , MRI , TRI ) ; if ( EltRB != DstRB ) return false ; if ( any_of ( make_range ( I . operands_begin ( ) + <NUM_LIT> , I . operands_end ( ) ) , [ & MRI ] ( const MachineOperand & Op ) { return ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , Op . getReg ( ) , MRI ) ; } ) ) return false ; unsigned SubReg ; const TargetRegisterClass * EltRC = getRegClassForTypeOnBank ( EltTy , EltRB ) ; if ( ! EltRC


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_ADDR : case VK_<ISA_LIT>_PCREL : case VK_<ISA_LIT>_GOT


<s> JTI = ( ( <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getInstrInfo ( ) ; TD = ( ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getDataLayout ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF


<s> static DecodeStatus DecodeLO32DSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler ::


<s> const uint32_t * <ISA_LIT>CA53ErratumStub ::


<s> <STR_LIT> getFixupKind ( ) const { return getFixupKind ( Kind )


<s> if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; } return Res


<s> ExceptionsType = ExceptionHandling :: Dwarf ; if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch ( ) == Triple


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O )


<s> AlignmentIsInBytes = false ; COMMDirectiveTakesAlignment = true ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = NULL


<s> inline bool CC_<ISA_LIT>_AnyReg_Error ( unsigned & , MVT & , MVT & , CCValAssign :: LocInfo & , <STR_LIT> & , CCState & ) { llvm_unreachable ( <STR_LIT> \ <STR_LIT> ) ; return


<s> case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op ,


<s> return DAG . getConstant ( APInt ( Op -> getValueType ( <NUM_LIT> ) . getScalarType ( ) . getSizeInBits ( ) , Op -> getConstantOperandVal ( ImmOp ) ,

IsSigned ) , SDLoc ( Op ) , Op -> getValueType ( <NUM_LIT> ) ) ;


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i )

<STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , Endian ) ;


<s> if ( ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) { if ( VT == <STR_LIT> ) return <NUM_LIT> ; if ( VT == <STR_LIT> ) return <NUM_LIT> ; } return TargetLowering :: getNumRegistersForCallingConv ( Context


<s> } else if ( offset < <NUM_LIT> && offset > - <NUM_LIT> ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , <NUM_LIT> ) , SImode ) && ! s_register_operand ( XEXP ( x , <NUM_LIT> ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , <NUM_LIT> ) ) ; } if (


<s> DecodeUNPCKHMask ( VT , Mask ) ; break ; case <STR_LIT> : DecodeUNPCKLMask ( VT , Mask ) ; break ; case <STR_LIT> : DecodeMOVHLPSMask ( NumElems , Mask ) ; break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeVPERMMask ( cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : case <STR_LIT>


<s> Register RegDstMI2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegSrcMI2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! IsMovepSrcRegister ( RegSrcMI2 ) ) return false ; bool ConsecutiveForward ; if ( IsMovepDestinationRegPair ( RegDstMI1 , RegDstMI2 ) ) { ConsecutiveForward = true ; } else if ( IsMovepDestinationRegPair ( RegDstMI2 , RegDstMI1 ) ) { ConsecutiveForward = false ; } else return false


<s> tree decl ; indirect_thunk_name ( name , regno , need_prefix , ret_p ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ picbase_thunk_section ] ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node (


<s> case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back (


<s> unsigned AccessSize = <NUM_LIT> ; unsigned long OpIx = Operands . size ( ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx =


<s> bool IsSmallMemset = IsMemset && Size < <NUM_LIT> ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , <NUM_LIT> , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT>


<s> static bool arm_function_value_regno_p ( const unsigned int regno ) { if ( regno == ARG_REGISTER ( <NUM_LIT> ) || ( TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_HARD_FLOAT && regno == FIRST_VFP_REGNUM )

|| ( TARGET_IWMMXT_ABI && regno == FIRST_IWMMXT_REGNUM ) ) return true ;


<s> warning ( OPT_Wattributes , <STR_LIT> ) ; * no_add_attrs = true ; } else if ( args == NULL_TREE && TREE_CODE ( * node ) == VAR_DECL ) { if ( ! ( TREE_PUBLIC ( * node ) ||


<s> unsigned Code ; switch ( Val & <NUM_LIT> ) { case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: createImm ( Code ) ) ; return MCDisassembler


<s> if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; auto & DL = State . getMachineFunction ( ) . getDataLayout ( ) ; unsigned StackAlign = DL . getStackAlignment ( ) . value ( ) ; unsigned Align = std :: min ( PendingMembers [ <NUM_LIT> ] . getExtraInfo ( ) , StackAlign ) ; ArrayRef < MCPhysReg > RegList ; switch ( LocVT . SimpleTy ) { case <STR_LIT> : { RegList = RRegList ; unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; unsigned RegAlign = alignTo ( Align , <NUM_LIT> ) / <NUM_LIT> ; while ( RegIdx % RegAlign != <NUM_LIT> && RegIdx < RegList . size ( ) ) State . AllocateReg ( RegList [ RegIdx ++ ] ) ; break ; } case <STR_LIT> : case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg


<s> if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; getParser ( ) . Lex ( ) ; return ParseMemOperand ( RegNo , Start ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; Parser . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . ParseExpression ( Val , End ) ) return <NUM_LIT> ; return <STR_LIT> ( Val ,


<s> return __extension__ ( __m256d ) { <NUM_LIT> ,


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering (


<s> int rx_initial_elimination_offset ( int from , int to ) { unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int mask ; rx_get_stack_layout ( & low , & high , & mask , & frame_size , & stack_size ) ; if ( from == ARG_POINTER_REGNUM ) { if ( low ) frame_size += ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ; else frame_size += bit_count ( mask ) * UNITS_PER_WORD ; frame_size += <NUM_LIT> * UNITS_PER_WORD ; if ( to == FRAME_POINTER_REGNUM ) return frame_size ; gcc_assert ( to == STACK_POINTER_REGNUM


<s> needsTOCRestore = true ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { CallOpc = <STR_LIT> ; } } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( needsTOCRestore ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( BytesCalleePops , true ) , InFlag , dl ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; if ( VT == <STR_LIT> || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isSEXTLoad ) ) { Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } } isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return true


<s> Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt = false ; Entry . IsSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_F64 : RTLIB :: SINCOS_F32 ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CC , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( ShouldUseSRet ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; if ( ! ShouldUseSRet ) return CallResult . first ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) , dl ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> )


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT>


<s> SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue VIdx = Node -> getOperand ( <NUM_LIT> ) ; SDValue VMask = Node -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Scale = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! Scale ) return nullptr ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDLoc DL ( Node ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: useSoftFloat ( )


<s> if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( VMask . getNode ( ) ) )

Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ;


<s> bool MatchEvenMask = true ; bool MatchOddMask = true ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeEven [ i ] ) ) MatchEvenMask = false ; if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeOdd [ i ] ) ) MatchOddMask = false ; } if ( ! MatchEvenMask && ! MatchOddMask ) return SDValue ( ) ; SDValue UndefNode = DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Op0 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = SVOp -> getOperand ( <NUM_LIT> ) ; if ( MatchEvenMask ) { static const int ShiftRightMask [ ] = { - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> } ; Op1 = DAG . getVectorShuffle ( VT , dl , Op1 , UndefNode , ShiftRightMask ) ; } else { static const int ShiftLeftMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; Op0 = DAG . getVectorShuffle ( VT ,

dl , Op0 , UndefNode , ShiftLeftMask ) ;


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; SDValue Part0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Part1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part0 , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , DL , VA


<s> if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( ! CCMatch && CallerCC == CallingConv :: <ISA_LIT>_StdCall ) return false ; if ( isVarArg && ! Outs . empty ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; SmallVector < CCValAssign ,


<s> bool isNeonUImm64Mask ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , Value >>= <NUM_LIT> ) if ( ( Value & <NUM_LIT> ) != <NUM_LIT> && ( Value & <NUM_LIT> ) !=


<s> if ( <STR_LIT> ( N ) ) return true ; if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; auto Opnd0 = N -> getOperand ( <NUM_LIT> ) ; auto * CINT = dyn_cast < ConstantSDNode > ( Opnd0 ) ; auto * CFP = dyn_cast < ConstantFPSDNode


<s> SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , <STR_LIT> ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG .

getConstant ( <NUM_LIT> , DL , VT ) , SRA ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64


<s> <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } unsigned LowGPR = ZFI -> getLowSavedGPR ( ) ; unsigned HighGPR = ZFI ->


<s> break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M'


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned I = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ I ] , Arg , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F .


<s> rtx or1k_initial_frame_addr ( ) { crtl -> accesses_prior_frames =


<s> return __builtin_ia32_vcvtuw2ph512_mask_round ( ( __v32hi ) __A , _mm512_setzero_ph ( ) , ( __mmask32 ) - <NUM_LIT> ,


<s> switch ( GET_CODE ( addr ) ) { case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) { unsigned HOST_WIDE_INT val = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ; return val + <NUM_LIT>


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value


<s> bool <ISA_LIT>TargetLowering :: combineRepeatedFPDivisors (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = N -> getOperand ( <NUM_LIT> ) ; SDValue TrueVal = N -> getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>cc = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == <STR_LIT> && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , TrueVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , Cmp ) ; } else if ( CC == <STR_LIT> && TrueVal == RHS ) { SDValue <ISA_LIT>cc ; SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ,


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) KnownZero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break


<s> auto * BCTy = cast < VectorType > ( BitCast -> getType ( ) ) ; auto * BCSrcTy = cast < VectorType > ( BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( BCTy -> getNumElements ( ) == BCSrcTy -> getNumElements ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Ptr = BitCast -> getOperand (


<s> auto * Load = cast < LoadSDNode > ( Store -> getValue ( ) ) ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; if ( Size > <NUM_LIT> && Size <= <NUM_LIT> ) { if ( <STR_LIT> ( Load -> getBasePtr ( ) . getOpcode ( ) ) ) return false ; if ( <STR_LIT> ( Store -> getBasePtr ( ) . getOpcode ( ) ) )


<s> if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , <NUM_LIT> ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , <NUM_LIT> ) ; } const_rtx tocrel_base = op ; const_rtx tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , <NUM_LIT> ) ; tocrel_offset = XEXP ( op , <NUM_LIT> ) ; } if ( tocrel_base_ret ) * tocrel_base_ret


<s> return ( uint32x4_t ) __builtin_mve_vcaddq_rot270v4si ( ( int32x4_t )


<s> assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) .


<s> static SDValue lowerShuffleAsLanePermuteAndPermute ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { int NumElts = VT . getVectorNumElements ( ) ; int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; int NumEltsPerLane = NumElts / NumLanes ; SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ]


<s> DebugLoc DL ; assert ( & ( * MF . begin ( ) ) == & PrologueMBB && <STR_LIT> ) ; NamedMDNode * HiPELiteralsMD = MF . getMMI ( ) . getModule ( ) -> getNamedMetadata ( <STR_LIT> ) ; if ( ! HiPELiteralsMD ) report_fatal_error ( <STR_LIT> ) ; const unsigned HipeLeafWords = getHiPELiteral ( HiPELiteralsMD , Is64Bit ? <STR_LIT> : <STR_LIT> ) ; const unsigned CCRegisteredArgs = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; const unsigned Guaranteed = HipeLeafWords * SlotSize ; unsigned CallerStkArity = MF . getFunction ( ) -> arg_size ( ) > CCRegisteredArgs ? MF . getFunction ( ) -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; unsigned MaxStack = MFI . getStackSize ( ) + CallerStkArity * SlotSize + SlotSize ; assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI . hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( ! MI . isCall ( ) ) continue ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( const auto & LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn ( LI ) ; incStackMBB -> addLiveIn ( LI ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; SPLimitOffset = getHiPELiteral ( HiPELiteralsMD ,


<s> if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag ) ) return MatchOperand_NoMatch ; IFlags |= Flag ; } } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateProcIFlags (


, ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static void emitAuthenticatedPointer ( MCStreamer & OutStreamer , MCSymbol * StubLabel , const MachineModuleInfoMachO :: AuthStubInfo & StubInfo ) { OutStreamer . emitLabel ( StubLabel ) ; OutStreamer . emitValue ( StubInfo . Pointer


<s> } else { sve_nunits = ordered_min ( sve_nunits , GET_MODE_SIZE ( vector_mode ) ) ; if ( aarch64_sve_data_mode ( element_mode , sve_nunits ) . exists ( & sve_mode ) ) return sve_mode ; } } if ( ( vec_flags & VEC_ADVSIMD ) && known_eq ( nunits , <NUM_LIT> ) && known_eq ( GET_MODE_BITSIZE ( vector_mode ) , <NUM_LIT> ) && maybe_ge ( GET_MODE_BITSIZE ( element_mode )

* GET_MODE_NUNITS ( vector_mode ) , <NUM_LIT> ) ) {


<s> else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) return <NUM_LIT> ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { int local_regparm , globals = <NUM_LIT> , regno ; for ( local_regparm = <NUM_LIT> ; local_regparm < REGPARM_MAX ; local_regparm ++ ) if ( fixed_regs [ local_regparm ] ) break ; if ( local_regparm == <NUM_LIT> && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = <NUM_LIT> ; if ( local_regparm == <NUM_LIT> && flag_split_stack ) local_regparm = <NUM_LIT> ; for ( regno = AX_REG ; regno <= DI_REG ; regno ++ ) if (


<s> if ( ST -> hasNEON ( ) ) return TypeSize :: getFixed ( <NUM_LIT> ) ; if ( ST -> hasMVEIntegerOps ( ) ) return TypeSize :: getFixed ( <NUM_LIT> ) ; return TypeSize :: getFixed ( <NUM_LIT> ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable (


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Op . getNumOperands ( ) ; i ++ ) if ( ! <STR_LIT> ( Op . getOperand ( i ) . getNode ( ) ) ) return false ; return


<s> bool HasRs = false ; bool HasRt = false ; if ( Rt == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs == <NUM_LIT> ) { MI . setOpcode ( <STR_LIT> ) ; HasRt = true ; } else if ( Rs == Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; HasRt = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; if ( HasRt ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( VT . is128BitVector ( ) && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = Cond -> use_begin ( ) , UE = Cond -> use_end ( ) ; UI != UE ; ++ UI ) if ( ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) || UI . getOperandNo ( ) != <NUM_LIT> ) return SDValue ( ) ; APInt DemandedMask ( APInt :: getSignMask ( BitWidth ) ) ; KnownBits Known ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; if ( ! TLI . SimplifyDemandedBits ( Cond , DemandedMask , Known , TLO , <NUM_LIT> , true ) ) return SDValue ( ) ; for ( SDNode * U : Cond -> uses ( ) ) { if ( U -> getOpcode ( ) == <STR_LIT> ) continue ; SDValue SB = DAG . getNode ( <STR_LIT> , SDLoc ( U ) , U -> getValueType ( <NUM_LIT> ) , Cond , U -> getOperand ( <NUM_LIT> ) , U -> getOperand


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back (


<s> static bool isValidVectorKind ( StringRef Suffix , RegKind VectorKind ) { return parseVectorKind ( Suffix , VectorKind


<s> } else { LL = <STR_LIT> ; SC = <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB =


<s> case E_TImode : fn = gen_store_conditionalti ; break ; default : gcc_unreachable ( ) ; } if ( PPC405_ERRATUM77 ) emit_insn ( gen_hwsync ( ) ) ; emit_insn ( fn ( res , mem , val )


<s> case <STR_LIT> : { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int64_t Offset = MO . getImm ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { if ( ! isInt < <NUM_LIT> > ( Offset ) ) { EmitInstrWithMacroNoAT ( MI ) ; return ; } }


<s> if ( Alignment == Align :: None ( ) ) return <NUM_LIT> ; const Align ParentAlign = MBB . getParent ( ) -> getAlignment ( ) ; if ( Alignment <= ParentAlign ) return offsetToAlignment ( Offset , Alignment ) ; if ( FirstImpreciseBlock < <NUM_LIT> ) FirstImpreciseBlock = MBB . getNumber ( ) ; return Alignment . value ( ) + offsetToAlignment ( Offset , Alignment


<s> enum calling_abi ix86_function_type_abi ( const_tree fntype ) { enum calling_abi abi = ix86_abi ; if ( fntype == NULL_TREE || TYPE_ATTRIBUTES ( fntype ) == NULL_TREE ) return abi ; if ( abi == SYSV_ABI && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { static int warned ; if ( TARGET_X32 && ! warned ) { error ( <STR_LIT> ) ; warned = <NUM_LIT> ; } abi = MS_ABI ; } else if ( abi == MS_ABI && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) abi = SYSV_ABI ; return abi


<s> if ( pSym . isDyn ( ) || pSym . isUndef ( ) || pFactory . getTarget ( ) . isSymbolPreemptible ( pSym ) ) return false ; return true


<s> CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= ( Value & Mask ) << TargetOffset ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT>


<s> MCValue Val ; if ( ! E -> EvaluateAsRelocatable ( Val , nullptr , nullptr ) ) return false ; if ( ! Val . getSymA ( ) || Val . getSymA ( ) ->

getSymbol ( ) . isUndefined ( ) ) return false ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAddressWithFixup ( const MCOperand & MO , unsigned FixupKind , SmallVectorImpl < MCFixup > & Fixups ) const { if ( ! MO . isExpr ( ) ) { assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm


<s> if ( VT == <STR_LIT> ) { if ( Subtarget . hasBWI ( ) ) { SDValue ExA = DAG . getNode ( ExAVX , dl , <STR_LIT> , A ) ; SDValue ExB = DAG . getNode ( ExAVX , dl , <STR_LIT> , B ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExA , ExB ) ; Mul = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mul ) ; } SDValue ALo = extract128BitVector ( A , <NUM_LIT> , DAG , dl ) ; SDValue BLo = extract128BitVector ( B , <NUM_LIT> , DAG , dl ) ; SDValue AHi = extract128BitVector ( A , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue BHi = extract128BitVector ( B , NumElems / <NUM_LIT> , DAG , dl ) ; ALo = DAG . getNode ( ExAVX , dl , <STR_LIT> , ALo ) ; BLo = DAG . getNode ( ExAVX , dl , <STR_LIT> , BLo ) ; AHi = DAG . getNode ( ExAVX , dl , <STR_LIT> , AHi ) ; BHi = DAG . getNode ( ExAVX , dl , <STR_LIT> , BHi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ALo , BLo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AHi , BHi ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; const int LoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int HiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( <STR_LIT> , dl , Lo , Hi , LoMask ) , DAG . getVectorShuffle ( <STR_LIT> , dl , Lo , Hi , HiMask ) ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue ExA = DAG . getNode ( ExAVX , dl , <STR_LIT> , A ) ; SDValue ExB = DAG . getNode ( ExAVX , dl , <STR_LIT> , B ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> MCSubtargetInfo & STI = copySTI ( ) ; std :: vector < std :: string > ArchFeatures ( <ISA_LIT>Features . begin ( ) , <ISA_LIT>Features . end ( ) ) ; STI . setDefaultFeatures ( <STR_LIT> , join ( ArchFeatures . begin ( ) , ArchFeatures . end ( ) , <STR_LIT> ) ) ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; ExpandCryptoAEK ( ID , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { UP . Threshold = <NUM_LIT> ; UP . PartialThreshold = <NUM_LIT> ; UP . Count


<s> if ( Op2Info == TargetTransformInfo :: OK_UniformConstantValue && ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup < MVT > ( SSE2UniformConstCostTable , array_lengthof ( SSE2UniformConstCostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2UniformConstCostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > SSE2CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , } ; if ( ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup < MVT > ( SSE2CostTable , array_lengthof ( SSE2CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2CostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > AVX1CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) && ! ST -> hasAVX2 ( ) ) { int Idx = CostTableLookup < MVT > ( AVX1CostTable , array_lengthof ( AVX1CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > CustomLowered [


<s> } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset ,


<s> <ISA_LIT>_64ATTAsmParser ( const Target & T , MCAsmParser & Parser , TargetMachine & TM ) : <ISA_LIT>ATTAsmParser (


<s> return ( __m128 ) __builtin_ia32_vpermilvarps_mask ( ( __v4sf ) __A , ( __v4si )


<s> if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isiOS ( ) ) { unsigned Major , Minor , Micro ; TargetTriple . getiOSVersion ( Major , Minor , Micro ) ; return Major >= <NUM_LIT> ; } return


<s> return __builtin_mve_vshllbq_m_n_sv16qi ( __arm_vuninitializedq_s16 ( ) , __a , __imm ,


<s> void addMovePRegPairOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; for ( auto RegNo : getRegList ( ) ) Inst . addOperand ( MCOperand :: createReg (


<s> bool hasCONTEXTIDREL2 ( ) const { return HasCONTEXTIDREL2


<s> EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue OutOps [ ] =


<s> set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode ,


<s> static bool nds32_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno > FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == <NUM_LIT> || !


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; N1 = peekThroughBitcasts ( N1 ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; BuildVectorSDNode * Vector = cast < BuildVectorSDNode > ( N1 ) ; ShuffleVectorSDNode * Shuffle = cast < ShuffleVectorSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; EVT SrcType = Shuffle -> getValueType ( <NUM_LIT> ) ; if ( ! Shuffle -> getOperand ( <NUM_LIT> ) -> isUndef ( ) ) return SDValue ( ) ; unsigned SrcSize = SrcType . getScalarSizeInBits ( ) ; unsigned NumElems = SrcType . getVectorNumElements (


<s> void loongarch_split_move_insn ( rtx dest , rtx src ,


<s> sorry ( <STR_LIT> , <STR_LIT> ) ; return ; } calculate_dominance_info ( CDI_DOMINATORS ) ; protected_bbs = sbitmap_alloc ( last_basic_block_for_fn ( cfun ) ) ; bitmap_clear ( protected_bbs ) ; rev_post_order = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n = pre_and_rev_post_order_compute ( NULL , rev_post_order , false ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , rev_post_order [ i ] ) ; if ( r10k_protected_bb_p ( bb , protected_bbs ) ) unprotected_region = NULL_RTX ; else unprotected_region = pc_rtx ; end = NEXT_INSN ( BB_END ( bb ) ) ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn


<s> static SDValue lowerV4F32Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( ! Subtarget . hasSSE2 ( ) ) { if ( isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL


<s> static __inline qword si_from_ullong ( unsigned long long l ) { union { qword q ; unsigned long long l [ <NUM_LIT> ] ; } x ; x . l [ <NUM_LIT> ] =


<s> MVT OpVT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool IsI1Vector = OpVT . getVectorElementType ( ) == <STR_LIT> ; SDLoc dl ( N ) ; SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = N -> getOperand ( <NUM_LIT> ) ; uint64_t IdxVal = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( Vec . isUndef ( ) && SubVec . isUndef ( ) ) return DAG . getUNDEF ( OpVT ) ; if ( ( Vec . isUndef ( ) || <STR_LIT> ( Vec . getNode ( ) ) ) && ( SubVec . isUndef ( ) || <STR_LIT> ( SubVec . getNode ( ) ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , dl ) ; if ( <STR_LIT> ( Vec . getNode ( ) ) ) { if ( SubVec . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SubVec . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { uint64_t Idx2Val = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( IdxVal + Idx2Val , dl ) ) ; } if ( SubVec . getOpcode ( ) == <STR_LIT> && IdxVal == <NUM_LIT> && isNullConstant ( SubVec . getOperand ( <NUM_LIT> ) ) && SubVec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Ins = SubVec . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Ins . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( Ins . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Ins . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) . getFixedSize ( ) <= SubVecVT . getFixedSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , Ins . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( IsI1Vector ) return SDValue (


<s> return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && FUNCTION_ARG_PADDING ( TYPE_MODE (


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { Offset += getExtraSlotsForProtection ( MF ) ; return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { Offset += getExtraSlotsForProtection ( MF ) ; return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset + StackSize ; Offset += getExtraSlotsForProtection ( MF ) ; Offset += RegInfo -> getSlotSize ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT>


<s> if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( V2 . isUndef ( ) && ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { SDValue VPermMask = getConstVector ( Mask , <STR_LIT> , DAG , DL , true ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , VPermMask ) ; } if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG ,


<s> Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ; return MCDisassembler


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> use_sibcall_p = const_call_insn_operand ( fnaddr , Pmode ) ; temp1 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; temp2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! IMM12_OPERAND ( delta ) ) { loongarch_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; loongarch_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = loongarch_add_offset ( temp2 , temp1 , vcall_offset


<s> return __builtin_ia32_movmskps ( ( __v4sf )


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter >


<s> bool <ISA_LIT>FrameLowering :: adjustStackWithPops ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , int Offset ) const { if ( Offset <= <NUM_LIT> ) return false ; if ( Offset % SlotSize ) return false ; int NumPops = Offset / SlotSize ; if ( NumPops != <NUM_LIT> && NumPops != <NUM_LIT> ) return false ; if ( MBBI == MBB . begin ( ) ) return false ; MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; auto RegMask = Prev -> getOperand


<s> case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : ++ NumVLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : ++ NumVSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return gen_rtx_REG ( mode , NDS32_GPR_RET_FIRST_REGNUM


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmpgt ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A , c


<s> if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Inst . getOpcode ( ) == <STR_LIT> && Val == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; if ( Val == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; return MCDisassembler ::


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return <NUM_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : const Function * F = MF .


<s> if ( IsPCRel && RelocType == MachO :: <ISA_LIT>_RELOC_VANILLA ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && A && ! Writer -> doesSymbolRequireExternRelocation ( * A ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , RelocType , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; const MCSymbol * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( A -> isVariable ( ) ) { int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , * A , FixedValue ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue & <NUM_LIT> ; break ; } MachO :: any_relocation_info MREPair ; MREPair . r_word0 = Value ; MREPair . r_word1 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) ) ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MREPair ) ; } Writer -> addRelocation ( RelSymbol , Fragment -> getParent ( ) ,


<s> warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; } return NULL_TREE


<s> unsigned <ISA_LIT>SEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> )


<s> unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems / <NUM_LIT> , dl , <STR_LIT> ) ; if ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; SDValue Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec2 , ShiftBits ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , Vec2 ) ; } if ( IdxVal == <NUM_LIT> ) { SDValue Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec2 , ShiftBits ) ; Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec2 , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec


<s> if ( TARGET_HITACHI && ! TARGET_NOMACSAVE ) { call_used_regs [ MACH_REG ] = <NUM_LIT> ; call_used_regs [ MACL_REG ] = <NUM_LIT> ; } for ( int regno = FIRST_GENERAL_REG ; regno <= LAST_GENERAL_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; call_used_regs [ FPSCR_MODES_REG ] = <NUM_LIT> ; call_used_regs [ FPSCR_STAT_REG


<s> case <STR_LIT> : case <STR_LIT> : { int64_t SH = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t MB = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; APInt InVal ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , SExtImm , true ) ; InVal = InVal . rotl ( SH ) ; uint64_t Mask = ( <NUM_LIT> << ( <NUM_LIT> - MB + <NUM_LIT> ) ) - <NUM_LIT> ; InVal &= Mask ; if ( isUInt < <NUM_LIT> > ( InVal . getSExtValue ( ) ) || ( Opc == <STR_LIT> && isUInt < <NUM_LIT> > ( InVal . getSExtValue ( ) ) ) ) { ReplaceWithLI = true ; Is64BitLI = Opc != <STR_LIT> ; NewImm = InVal . getSExtValue ( ) ; SetCR = Opc == <STR_LIT> ; break ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t SH = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t MB = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t ME = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; APInt InVal ( <NUM_LIT> , SExtImm , true ) ; InVal = InVal . rotl ( SH ) ; uint64_t Mask = ( ( <NUM_LIT> << ( <NUM_LIT> - MB ) ) - <NUM_LIT> ) & ~ ( ( <NUM_LIT> << ( <NUM_LIT> - ME ) ) - <NUM_LIT> ) ; InVal &= Mask ; bool ValueFits = isUInt < <NUM_LIT> > ( InVal . getSExtValue ( ) ) ; ValueFits |= ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && isUInt < <NUM_LIT> > ( InVal . getSExtValue ( ) ) ) ; if ( ValueFits ) { ReplaceWithLI = true ; Is64BitLI = Opc == <STR_LIT> || Opc == <STR_LIT> ; NewImm = InVal . getSExtValue ( ) ; SetCR = Opc == <STR_LIT> || Opc == <STR_LIT> ; break ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t LogicalImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Result = <NUM_LIT> ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Result = LogicalImm | SExtImm ; else Result = LogicalImm ^ SExtImm ; if ( isInt < <NUM_LIT> > ( Result ) ) { ReplaceWithLI = true ; Is64BitLI = Opc == <STR_LIT> || Opc == <STR_LIT> ; NewImm = Result ; break ; } return false ; } } if ( ReplaceWithLI ) { if ( SetCR ) { bool ImmChanged = ( SExtImm & NewImm ) != NewImm ; if ( PostRA && ImmChanged )


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> current_function_uses_pic_offset_table = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( ! no_new_pseudos ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( ! arm_legitimate_index_p ( mode , offset , SET , <NUM_LIT> ) ) { gcc_assert ( ! no_new_pseudos ) ; offset = force_reg ( Pmode , offset ) ; } if ( GET_CODE ( offset ) == CONST_INT ) return plus_constant ( base , INTVAL ( offset ) ) ; } if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ( GET_MODE_CLASS ( mode ) == MODE_INT || TARGET_SOFT_FLOAT ) ) { emit_insn ( gen_addsi3 ( reg , base , offset ) ) ; return reg ; } return gen_rtx_PLUS ( Pmode , base ,


<s> int64_t Align = <NUM_LIT> << scale ; int64_t Max = Align * ( ( <NUM_LIT> << ( width - <NUM_LIT> ) ) - <NUM_LIT> ) ; int64_t Min = - Align * ( <NUM_LIT> << ( width


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return ; <ISA_LIT>FunctionInfo * PFI = Entry -> getParent ( ) -> getInfo <


<s> return ( __m128i ) __builtin_ia32_pmovusqb128_mask ( ( __v2di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 )


<s> bool <ISA_LIT>DagToDagISel :: SelectAddr ( SDNode * Parent , SDValue Addr , SDValue & Base , SDValue & Offset ) { return


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectFPTrunc ( const Instruction * I ) { if ( Subtarget -> hasSSE2 ( ) ) { if ( I -> getType ( ) -> isFloatTy ( ) ) { const Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isDoubleTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } } } return


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( e < <NUM_LIT> || ! hasSSSE3OrAVX ) return false ; for ( i = <NUM_LIT> ; i != e ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) break ; if ( i == e ) return false ; if ( Mask [ i ] <= i


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymB ( ) ) report_fatal_error (


<s> ret = __popcount_tab [ x & <NUM_LIT> ] ; ret += __popcount_tab [ ( x >> <NUM_LIT> ) &