<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GAHi , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst ) return


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex , SPAdj , RS ) ; return ; } } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TFI -> hasFP ( MF ) ? ( is64Bit ? <STR_LIT> : <STR_LIT> ) : ( is64Bit ? <STR_LIT> : <STR_LIT> ) , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( requiresRegisterScavenging ( MF ) ) { const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; SReg = findScratchRegister ( II , RS , is64Bit ? G8RC : GPRC , SPAdj ) ; } else SReg = is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) &&


<s> void Thumb1InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getTarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP


<s> MVT <ISA_LIT>TargetLowering :: getTypeForExtArgOrReturn ( MVT VT , <STR_LIT> ExtendKind ) const { MVT ReturnMVT ; if ( Subtarget -> is64Bit ( ) && VT == <STR_LIT> && ExtendKind == <STR_LIT> ) ReturnMVT = <STR_LIT> ; else ReturnMVT = <STR_LIT> ; MVT MinVT = getRegisterType ( ReturnMVT ) ; return VT . bitsLT ( MinVT )


<s> static void pa_asm_out_destructor ( rtx symbol , int priority ) { if ( ! function_label_operand ( symbol , VOIDmode ) ) hppa_encode_label ( symbol ) ; default_dtor_section_asm_out_destructor ( symbol


<s> static const MCPhysReg IntRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg F32Regs [ ] = { <STR_LIT> , <STR_LIT> } ; if ( ArgFlags . isByVal ( ) ) return true ; if ( ArgFlags . isInReg ( ) && ! Subtarget . isLittle ( ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ,


_mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return Opcode ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ! TARGET_INTER_UNIT_MOVES && ! optimize_size ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; if ( mode == SFmode || mode ==


<s> Inst . addOperand ( MCOperand :: CreateReg ( Mem . Base ) ) ; addExpr ( Inst , Mem . Disp


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [


<s> aarch64_layout_frame ( ) ; return cfun -> machine -> frame . frame_size ==


<s> ITState . Cond = <STR_LIT> ( ITState . Cond ) ; } else { ITState . Mask ^= <NUM_LIT> << ( <NUM_LIT> -


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) && Value


<s> unsigned oldval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned newval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned scratch = MRI . createVirtualRegister ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; if ( isThumb2 ) { MRI . constrainRegClass ( dest , <STR_LIT> ) ; MRI . constrainRegClass ( oldval , <STR_LIT> ) ; MRI . constrainRegClass ( newval , <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB


<s> if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > <NUM_LIT> && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > <NUM_LIT> && ! FLOAT128_2REG_P ( mode ) ) return true ; return false


<s> unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * UseMI = & * MRI -> use_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB ) return Reg ; while ( UseMI -> isCopy ( ) ||


<s> static bool matchingImmOps ( const MachineInstr & MI , int MIOpIndex , int64_t Expect , unsigned ExtendFrom = <NUM_LIT> ) { const MachineOperand & Op = MI . getOperand ( MIOpIndex ) ; if ( ! Op . isImm ( ) ) return


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getNOT ( dl , Op . getOperand ( <NUM_LIT> ) , VT ) ) ; } } assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType (


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DCI . DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , <STR_LIT> , LN0 -> getMemOperand ( ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; DCI . DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> void <ISA_LIT>TargetELFStreamer :: switchVendor ( StringRef Vendor ) { assert ( ! Vendor . empty (


<s> NewOpc = <STR_LIT> ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else { return false ; } if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function & Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func . getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( * Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } FirstReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SecondReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstReg == SecondReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT>


<s> if ( len >= <NUM_LIT> ) { emit_insn ( gen_movmem8b ( out , in , out , in ) ) ; len -= <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= <NUM_LIT> ; offset += <NUM_LIT> ; } if ( len >= <NUM_LIT> ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( in


<s> bool wasInITBlock = inITBlock ( ) ; while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) ) flushPendingInstructions ( Out ) ; } else { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; case Match_NearMisses : ReportNearMisses ( NearMisses , IDLoc , Operands ) ; return true ; case Match_MnemonicFail


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const

MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> assert ( ITState . CurPosition == <NUM_LIT> ) ; ITState . CurPosition = ~ <NUM_LIT>


<s> return ( __m256i ) __builtin_ia32_pbroadcastb256 ( (


<s> static uint32_t read_cpucfg_word ( int wordno ) { ( void ) wordno ; uint32_t ret =


<s> bool <ISA_LIT>FastISel :: SelectCmp ( const Instruction * I ) { const CmpInst * CI = cast < CmpInst > ( I ) ; <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CI -> isEquality ( ) ) ) return false ; unsigned MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; updateValueMap ( I , DestReg ) ; return


<s> bool hasDef = MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isDef ( ) && ! MI -> getOperand ( <NUM_LIT> ) . isImplicit ( ) ; unsigned StartIdx = hasDef ? <NUM_LIT> : <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { case TargetOpcode :: STACKMAP : StartIdx += <NUM_LIT> ; break ; case TargetOpcode :: PATCHPOINT : StartIdx += MI -> getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( SmallVectorImpl < unsigned > :: const_iterator I = Ops . begin ( ) , E = Ops . end ( ) ; I != E ; ++ I ) { if ( * I < StartIdx ) return <NUM_LIT> ; } MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( MI -> getOpcode ( ) ) , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; for ( unsigned i = <NUM_LIT> ; i < StartIdx ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; for ( unsigned i = StartIdx ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( std :: find ( Ops . begin ( ) , Ops . end ( ) , i ) != Ops . end ( ) ) { assert ( MO . getReg ( ) && <STR_LIT> ) ; const TargetRegisterClass * RC = MF . getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) ; unsigned SpillSize ; unsigned SpillOffset ; bool Valid = TII . getStackSlotRange ( RC , MO . getSubReg ( ) , SpillSize , SpillOffset ,


<s> assert ( LHS . getValueType ( ) . is64BitVector ( ) && RHS . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; if ( isEssentiallyExtractHighSubvector ( LHS ) ) { RHS = tryExtendDUPToExtractHigh ( RHS , DAG ) ; if ( ! RHS . getNode ( ) ) return SDValue ( ) ; } else if ( isEssentiallyExtractHighSubvector ( RHS ) ) { LHS = tryExtendDUPToExtractHigh ( LHS , DAG ) ; if ( ! LHS . getNode ( ) ) return SDValue


<s> unsigned R1 = RegList . List -> back ( ) ; if ( ! ( ( R0 == <STR_LIT> && R1 == <STR_LIT> ) || ( R0 == <STR_LIT> && R1 == <STR_LIT> ) ) ) return false ; int PrevReg = * RegList . List -> begin ( ) ; for ( int i = <NUM_LIT> ; i < Size - <NUM_LIT> ; i ++ ) { int Reg = ( * ( RegList . List ) ) [ i ] ; if ( Reg != PrevReg + <NUM_LIT> ) return false ; PrevReg = Reg ; } return true


<s> if ( parseRegister ( Reg ) ) return true ; if ( Reg . Group != Group ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Regs && Regs [ Reg . Num ] == <NUM_LIT> ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Reg . Num == <NUM_LIT> && IsAddress ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Regs ) Reg . Num = Regs [ Reg . Num ] ; return false


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [ i ] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ; return


<s> const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isGVInGOT ( GV ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI ,


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; unsigned Width ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return


<s> std :: string ( <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , Subtarget ) { if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString ( ) + <STR_LIT>


<s> EVT NodeTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG

. getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return AllowsUnaligned ; case <STR_LIT> : case <STR_LIT> : return Subtarget -> hasNEON ( ) && ( AllowsUnaligned


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N00 , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! crtl -> is_leaf ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= <NUM_LIT> ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += <NUM_LIT> *


<s> unsigned NumOfElm = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out . push_back ( Mask [ i ] + LowOffset ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++

) Out . push_back ( Mask [ i ] + HighOffset + NumOfElm ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) )


<s> case <NUM_LIT> : case 'c' : case 'C' : case <NUM_LIT> : case 'z' : case 'Z' : case <NUM_LIT> : case 's' : case 'S' : case <NUM_LIT> : case 'o' : case 'O' : case <NUM_LIT> : case


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule ->


<s> RegisterTarget < Triple :: x86 , true > X ( getThe<ISA_LIT>_32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: x86_64 , true > Y ( getThe<ISA_LIT>_64Target


<s> case E_DFmode : index = <NUM_LIT> ; break ; case E_XFmode : index = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> fp_load [ index ] , ix86_cost -> fp_store [ index ] ) ; return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( regclass ) ) { int index = sse_store_index ( mode ) ; if ( index == - <NUM_LIT> ) return <NUM_LIT> ; if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> sse_load [ index ] , ix86_cost -> sse_store [ index ] ) ; return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( regclass ) ) { int index ; switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : index = <NUM_LIT> ; break ; case <NUM_LIT> : index =


<s> getAddrMode2OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI .


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : { const MachineOperand & LastMO = MI -> getOperand ( opNum - <NUM_LIT> ) ; bool LastMOIsGP = LastMO . getType ( ) == MachineOperand :: MO_Register && LastMO . getReg ( ) == <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> || LastMOIsGP ) O << <STR_LIT> ; else O << <STR_LIT> ; break ; } case <STR_LIT> : if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand ::


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel (


<s> return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) || Val == std :: numeric_limits <


<s> ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT>


<s> if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . shouldOptForSize ( ) ; bool ExpandFunnel = ! OptForSize && Subtarget . isSHLDSlow ( ) ; if ( ( VT == <STR_LIT> || ( ExpandFunnel && VT == <STR_LIT> ) ) && ! isa < ConstantSDNode > ( Amt ) ) { unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue Mask = DAG . getConstant ( EltSizeInBits - <NUM_LIT> , DL , Amt . getValueType ( ) ) ; SDValue HiShift = DAG . getConstant ( EltSizeInBits , DL , Amt . getValueType ( ) ) ; Op0 = DAG . getAnyExtOrTrunc ( Op0 , DL , <STR_LIT> ) ; Op1 = DAG . getZExtOrTrunc ( Op1 , DL , <STR_LIT> ) ; Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , Mask ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , HiShift ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Op1 ) ; if ( IsFSHR ) { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ,


<s> MCSubtargetInfo * <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT ,


<s> return ( RealignStack && ( MFI -> getMaxAlignment ( ) > StackAlign && ! MFI


<s> resetSubtargetFeatures ( CPU , FS ) ; return *


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; SDValue SelectOp , Phi ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SelectOp = Op0 ; Phi = Op1 ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SelectOp = Op1


<s> case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return nullptr ; if ( RegNo == <STR_LIT> || RegNo == <STR_LIT> ) { Error ( Start , <STR_LIT> , SMRange ( Start , End ) ) ; return nullptr ; } if ( RegNo == <STR_LIT> ) { Error ( Start , <STR_LIT> , SMRange ( Start , End ) ) ; return nullptr ; } if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return ErrorOperand


<s> return __builtin_aarch64_lroundhfdi (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo &


<s> case CallingConv :: <ISA_LIT>_APCS : case CallingConv :: Swift : break ; } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= <NUM_LIT> ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case


<s> unsigned getSlot ( unsigned RegNo ) const { assert ( RegNo < NumFPRegs && <STR_LIT>


<s> if ( TARGET_SSP_TLS_GUARD ) { tree type_node = lang_hooks . types . type_for_mode ( ptr_mode , <NUM_LIT> ) ; int qual = ENCODE_QUAL_ADDR_SPACE ( ix86_stack_protector_guard_reg ) ; tree type = build_qualified_type ( type_node , qual ) ; tree t ; if ( OPTION_SET_P ( ix86_stack_protector_guard_symbol_str ) ) { t = ix86_tls_stack_chk_guard_decl ; if ( t == NULL ) { rtx x ; t = build_decl ( UNKNOWN_LOCATION , VAR_DECL ,

get_identifier ( ix86_stack_protector_guard_symbol_str ) , type ) ;


<s> SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . OR ( b . AND ( A1 , b . NOT ( A2 ) ) , b . AND ( b . SRL < <NUM_LIT> > ( A1 ) , A2 ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . AND ( A1 , b . NOT ( b . SHL < <NUM_LIT> > ( A2 ) ) ) , Tmp ) ; } llvm_unreachable ( <STR_LIT>


<s> void DecodeInsertElementMask ( MVT VT , unsigned Idx , unsigned Len , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT .


<s> ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) ) ; else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg )

. addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ;


<s> const TargetRegisterClass * ThumbRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only

( ) ) return <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ;


<s> return addOffset ( MIB . addReg ( Reg , getKillRegState ( isKill ) )


<s> return ( __m256d ) __builtin_ia32_minpd256 ( ( __v4df )


<s> assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in )

. addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef ( ) ) if ( SDValue Rotate = lowerShuffleAsBitRotate ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue PSHUFB = lowerShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable , Subtarget , DAG ) ) return PSHUFB ; if ( Subtarget . hasVBMI ( ) ) return lowerShuffleWithPERMV ( DL


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo


<s> if ( SHFIndices [ i ] == - <NUM_LIT> ) SHFIndices [ i ] = Idx ; if ( ! ( Idx == - <NUM_LIT> || Idx == SHFIndices [ i ] ) ) return SDValue ( ) ; } } APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { int Idx = SHFIndices [ i ] ; if ( Idx == - <NUM_LIT> ) Idx = <NUM_LIT> ; Imm <<= <NUM_LIT> ; Imm |= Idx


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetPop ( ) { OS <<


<s> bool <ISA_LIT>BaseRegisterInfo :: shouldRewriteCopySrc ( const TargetRegisterClass * DefRC , unsigned DefSubReg , const TargetRegisterClass


<s> void addInst ( MachineBasicBlock :: iterator I , unsigned SPAdjust , bool BeforeFPSet = false ) { InstInfo Info = { I , SPAdjust ,


<s> Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) { Constant * NewConst = ConstantExpr :: getZExt ( Const , ExtTy ) ; I -> setOperand ( i , NewConst ) ; } else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : Visited ) { auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) continue ; if ( Sources . count ( I ) || Sinks . count ( I ) ) continue ; if ( ! shouldPromote ( I ) || SafeToPromote . count (

I ) || NewInsts . count ( I ) ) continue ;


<s> if ( NumElts < <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ConcatMask ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ConcatMask [ i ] = i ; for ( unsigned i = NumElts ; i != <NUM_LIT> ; ++ i ) ConcatMask [ i ] = ( i % NumElts ) + NumElts ; Value * Zero = Constant :: getNullValue ( Op0 -> getType ( ) ) ; Op0 = Builder . CreateShuffleVector ( Op0 , Zero , ConcatMask ) ; Op1 = Builder . CreateShuffleVector ( Op1 , Zero , ConcatMask ) ; NumElts = <NUM_LIT> ; } Type * I32Ty = VectorType :: get ( Builder . getInt32Ty ( ) , IntrinsicNumElts / <NUM_LIT> ) ; assert ( NumElts % IntrinsicNumElts == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSplits = NumElts / IntrinsicNumElts ; SmallVector < Value * , <NUM_LIT> > Ops ( NumSplits ) ; for ( unsigned i = <NUM_LIT> ; i != NumSplits ; ++ i ) { SmallVector < int , <NUM_LIT> > ExtractMask ( IntrinsicNumElts ) ; std :: iota ( ExtractMask . begin ( ) , ExtractMask . end ( ) , i * IntrinsicNumElts ) ; Value * ExtractOp0 = Builder . CreateShuffleVector ( Op0 , Op0 , ExtractMask ) ; Value * ExtractOp1 = Builder . CreateShuffleVector ( Op1 , Op0 , ExtractMask ) ; Ops [ i ] = Builder . CreateCall ( PSADBWFn , { ExtractOp0 , ExtractOp1 } ) ; Ops [ i ] = Builder . CreateBitCast ( Ops [ i ] , I32Ty ) ; } assert ( isPowerOf2_32 ( NumSplits ) && <STR_LIT> ) ; unsigned Stages = Log2_32 ( NumSplits ) ; for ( unsigned s = Stages ; s > <NUM_LIT> ; -- s ) { unsigned NumConcatElts = cast < VectorType > ( Ops [ <NUM_LIT> ] -> getType ( ) ) -> getNumElements ( ) * <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> << ( s - <NUM_LIT> ) ; ++ i ) { SmallVector < int , <NUM_LIT> > ConcatMask ( NumConcatElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end ( ) , <NUM_LIT> ) ; Ops [ i ] = Builder . CreateShuffleVector ( Ops [ i * <NUM_LIT> ] , Ops [ i * <NUM_LIT> + <NUM_LIT> ] , ConcatMask ) ; } } NumElts = cast < VectorType > ( OpTy ) -> getNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { Ops [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , ArrayRef < int > { <NUM_LIT> , <NUM_LIT> } ) ; } else if ( NumElts >= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> >


<s> if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI . getOperand ( PIdx +


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasThumb2DSP ( ) && ( FlagsVal & <NUM_LIT> ) ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success


<s> static SDValue combineSetCCEFLAGS ( SDValue EFLAGS , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; if ( SDValue R = combinePTESTCC ( EFLAGS , CC , DAG )


<s> if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ; return false


<s> if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL (

XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>ELFStreamer :: Reset ( ) { ExTab = nullptr ; FnStart = nullptr ; Personality = nullptr ; PersonalityIndex = <STR_LIT> :: NUM_PERSONALITY_INDEX ; FPReg = <STR_LIT> ; FPOffset = <NUM_LIT> ; SPOffset = <NUM_LIT> ; PendingOffset = <NUM_LIT> ; UsedFP =


<s> MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) { ++ NumPreFolded ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { ++ NumPostFolded ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } DEBUG ( dbgs ( ) <<


<s> Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> ) ; else Disp = CurDAG -> getTargetConstant ( AM .


<s> if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr ,


<s> bool Changed = false ; TII = STI . getInstrInfo ( ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock ( MBB


<s> int dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest )


<s> uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; if ( ( pstate_field == <STR_LIT> || pstate_field == <STR_LIT> ) && crm > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; bool


<s> return SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return <NUM_LIT> ; return - ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT>


<s> if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; rtx mask = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; if ( GET_CODE ( mask ) == CONST_INT ) { if ( INTVAL ( mask ) == - <NUM_LIT> ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return <NUM_LIT> ; } if ( ! REG_P ( mask ) ) return <NUM_LIT> ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return <NUM_LIT> ; rtx_insn * const_insn = DF_REF_INSN ( def_link -> ref ) ; rtx const_body = PATTERN ( const_insn ) ; if ( GET_CODE ( const_body ) != SET ) return <NUM_LIT> ; real_mask = SET_SRC ( const_body ) ; if ( GET_CODE ( real_mask ) != CONST_INT || INTVAL ( real_mask ) != - <NUM_LIT> ) return <NUM_LIT> ; } if ( real_mask == <NUM_LIT> ) return <NUM_LIT> ; return alignment_with_canonical_addr ( SET_SRC ( body )


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) .


<s> FalkorMarkStridedAccessesLegacy ( ) : FunctionPass


<s> unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && TREE_CODE ( decl ) ==


<s> unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = IsLittleEndian ? i


<s> char * str = ( char * ) xmalloc ( strlen ( const_str ) ) ; enum aarch_parse_opt_result res = aarch_parse_branch_protection ( const_str , & str ) ; if ( res == AARCH_PARSE_INVALID_ARG ) error


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab


<s> MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo )


__vector __int128 ) result , <NUM_LIT> ) ) ;


<s> if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? <NUM_LIT> : <NUM_LIT> , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property


<s> } else { BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; PACI = Subtarget . hasPAuth ( ) ? <STR_LIT> : <STR_LIT> ; } auto MI = BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( PACI ) ) ; if ( Subtarget . hasPAuth ( ) ) MI . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: InternalRead ) ; MI . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> needsDwarfUnwindInfo ( ) ) { unsigned CFIIndex = MF . addFrameInst (

MCCFIInstruction :: createNegateRAState ( nullptr ) ) ;


<s> EncodeAddrModeOpValues ( const MCInst & MI , unsigned OpIdx , unsigned & Reg , unsigned & Imm , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg (


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( )


<s> unsigned Cycles = ReturnBB . second ; bool OptForSize = llvm :: shouldOptimizeForSize ( MBB , PSI , MBFI ) ; if ( OptForSize ) continue ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugInstr ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++


<s> if ( X . getOpcode ( ) == <STR_LIT> ) { SDValue A = emitOrXorXorTree ( Op0 , DL , DAG , VecVT , CmpVT , HasPT , SToV ) ; SDValue B = emitOrXorXorTree ( Op1 , DL , DAG , VecVT , CmpVT , HasPT , SToV ) ; if ( VecVT != CmpVT ) return DAG . getNode ( <STR_LIT> , DL , CmpVT , A , B ) ; if ( HasPT ) return DAG . getNode ( <STR_LIT> , DL , VecVT , A , B ) ; return DAG . getNode ( <STR_LIT> , DL , CmpVT , A , B ) ; } else if ( X . getOpcode ( ) == <STR_LIT> ) { SDValue A = SToV


<s> Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal ,


<s> SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) -> hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( )


<s> DebugLoc dl = N -> getDebugLoc ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; int NumElems = VT . getVectorNumElements ( ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( int i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; SDValue Zeros = getZeroVector ( VT , true , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleHigh128VectorInsertLow ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , V , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleLow128VectorInsertHigh ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , V , DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } return SDValue ( )


<s> void _Unwind_DeleteException ( _Unwind_Exception * exc ) { if ( exc -> exception_cleanup ) ( * exc -> exception_cleanup

) ( _URC_FOREIGN_EXCEPTION_CAUGHT , exc ) ;


<s> return ( ( qword ) ( vec_mulo ( ( vec_ushort8 ) ( a ) , (


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI

. getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) vmull_n_s16 ( int16x4_t a , int16_t b ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> void <ISA_LIT>InstPrinter :: printBranchOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; O << <STR_LIT> ; printAbsAddrOperand ( MI , OpNo


<s> SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> , <STR_LIT>


<s> return ( vector signed char ) __builtin_altivec_vxor ( ( vector signed int ) a1 , ( vector


<s> void <ISA_LIT>InstPrinter :: printUImm ( const MCInst * MI , int opNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isImm ( ) ) { uint64_t Imm = MO . getImm ( ) ; Imm -= Offset ; Imm &= ( <NUM_LIT> << Bits ) - <NUM_LIT> ; Imm += Offset


) _mm_undefined_si128 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> else ATS . emitFPU ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , STI . hasV8_1aOps ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? ( STI . isFPOnlySP ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? ( STI . isFPOnlySP ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasVFP3 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? ( STI . isFPOnlySP ( ) ? ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) ) : ( STI . hasFP16 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( isPositionIndependent ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . isRWPI ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( isPositionIndependent ( ) || STI . isROPI ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( isPositionIndependent ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( ! STI . hasVFP2 ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . allowsUnalignedMem ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT>


<s> unsigned Size = Subtarget . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned LUi = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ATReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Offset , Size , true ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , TII . get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - <NUM_LIT> ; ++ Inst ) BuildMI ( MBB , II , DL , TII . get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDu ) , ATReg ) . addReg ( FrameReg ) . addReg ( ATReg ) ; FrameReg = ATReg


<s> bool <ISA_LIT>BaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) )


<s> case TargetOpcode :: G_INSERT_VECTOR_ELT : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_BUILD_VECTOR_TRUNC : return true ; default : break ; } return hasFPConstraints ( MI , MRI , TRI ,


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << markup ( <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i )

if ( N -> getOperand ( i ) != SplatValue ) return false ;


<s> case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto * Arg0 = dyn_cast < CastInst > ( Args [ <NUM_LIT> ] ) ; if ( Opcode == Instruction :: Mul && ( ! Arg0 || Arg0 -> getOpcode ( ) != Extend -> getOpcode ( ) || Arg0 -> getOperand ( <NUM_LIT> ) -> getType ( ) != Extend -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return false ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; auto * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy ->


<s> bool SVEAddressingModes :: runOnLoop ( Loop * L ) { bool LoopOptimized = false ; for ( auto BB = L -> block_begin ( ) , BE = L -> block_end ( ) ; BB != BE ; ++ BB ) LoopOptimized |= OptimizeBlock ( * BB ) ; ++ NumVisited ; if ( LoopOptimized ) ++ NumOptimized ; return


<s> return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> static __inline__ void _mm_free ( void *


<s> mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 =


<s> static rtx ia64_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , ( ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && ( mode

) != TFmode ) ? FR_RET_FIRST : GR_RET_FIRST ) ) ;


<s> bool canMergeStoresTo ( EVT MemVT ) const


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { <ISA_LIT>Operand * RegOp ; SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( <STR_LIT> ) ) ; if ( Reg == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegOp = <STR_LIT> ( Reg , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { int RegNum = - <NUM_LIT> ; std :: string RegName = Parser . getTok ( ) . getString ( ) . lower ( ) ; RegNum = matchCPURegisterName ( RegName ) ; if ( RegNum == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegNum = getReg ( regKindToRegClass ( <STR_LIT> ) , RegNum ) ; RegOp = <STR_LIT> ( RegNum , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else return MatchOperand_ParseFail ; RegOp -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( RegOp ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * expr = dyn_cast <


<s> const unsigned Imm16 = getChunk ( UImm , ChunkIdx ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ; transferImpOps ( MI , MIB , MIB1 ) ; MI . eraseFromParent (


<s> dbgs ( ) << <STR_LIT> ; VecLd1 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; CreateLoadIns ( Builder , Acc , &


<s> EVT VT = Op . getValueType ( ) ; SDValue ff1 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ff1 , DAG . getConstant (


<s> bool isShiftAmtImm6 ( ) const { if ( ! isImm (


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( isThumb && <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; NumUBrFixed ++ ; DOUT << <STR_LIT> << * MI ; return true


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * getSubExpr


<s> SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; return DAG . getBitcast ( OrigVT , NewNode ) ; } unsigned NewOpcode = <NUM_LIT> ; if ( Arg . hasOneUse ( ) && Subtarget . hasAnyFMA ( ) ) { switch ( Arg . getOpcode ( ) ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } if ( NewOpcode ) return DAG . getBitcast ( OrigVT , DAG . getNode ( NewOpcode , DL , VT , Arg . getNode ( ) -> ops ( ) ) ) ; return SDValue (


<s> if ( FirstInput . getOpcode ( ) != <STR_LIT> && FirstInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) return SDValue ( ) ; SDValue Ext1 = FirstInput . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT>


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return


<s> union { int64_t Whole ; T Parts [ sizeof ( int64_t ) / sizeof (


<s> Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt = false ; Entry . IsSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_STRET_F64 : RTLIB :: SINCOS_STRET_F32 ; const char * LibcallName = getLibcallName ( LC ) ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CC , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( ShouldUseSRet ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; if ( ! ShouldUseSRet ) return CallResult . first ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) , dl ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) ) ; SDVTList Tys = DAG . getVTList ( ArgVT , ArgVT ) ; return DAG . getNode ( <STR_LIT> , dl , Tys , LoadSin . getValue ( <NUM_LIT> ) , LoadCos . getValue


<s> qword q ; float f [ <NUM_LIT> ] ; } x ; x . f [ <NUM_LIT> ] = f ; return ( x .


<s> unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == <NUM_LIT> && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == <NUM_LIT> ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return size >


<s> Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , VecTy ) ; IRBuilder < > Builder ( LI ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( LI -> getPointerOperand ( ) , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i ] ; unsigned Index = Indices [ i


<s> switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } SET_OPTION_IF_UNSET ( opts , & global_options_set , param_sched_autopref_queue_depth , queue_depth ) ; if ( aarch64_autovec_preference == <NUM_LIT> ) SET_OPTION_IF_UNSET ( opts , & global_options_set , aarch64_sve_compare_costs , <NUM_LIT> ) ; if ( aarch64_tune_params . prefetch -> num_slots > <NUM_LIT> ) SET_OPTION_IF_UNSET ( opts , & global_options_set , param_simultaneous_prefetches , aarch64_tune_params . prefetch -> num_slots ) ; if ( aarch64_tune_params . prefetch -> l1_cache_size >= <NUM_LIT> ) SET_OPTION_IF_UNSET ( opts , & global_options_set , param_l1_cache_size , aarch64_tune_params . prefetch -> l1_cache_size ) ; if ( aarch64_tune_params . prefetch -> l1_cache_line_size >= <NUM_LIT> ) SET_OPTION_IF_UNSET ( opts , & global_options_set , param_l1_cache_line_size , aarch64_tune_params . prefetch -> l1_cache_line_size ) ; if ( aarch64_tune_params . prefetch -> l2_cache_size >= <NUM_LIT> ) SET_OPTION_IF_UNSET ( opts , & global_options_set , param_l2_cache_size , aarch64_tune_params . prefetch -> l2_cache_size ) ; if ( ! aarch64_tune_params . prefetch -> prefetch_dynamic_strides ) SET_OPTION_IF_UNSET ( opts , & global_options_set , param_prefetch_dynamic_strides , <NUM_LIT> ) ; if ( aarch64_tune_params . prefetch -> minimum_stride >= <NUM_LIT> ) SET_OPTION_IF_UNSET ( opts , & global_options_set , param_prefetch_minimum_stride , aarch64_tune_params . prefetch -> minimum_stride ) ; SET_OPTION_IF_UNSET ( opts , & global_options_set , param_sched_pressure_algorithm , SCHED_PRESSURE_MODEL ) ; int guard_size =


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isV9 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setMinFunctionAlignment ( <NUM_LIT>


<s> return isMem64 ( ) && isMemIndexReg ( <STR_LIT>


<s> if ( epilogue_p < <NUM_LIT> || current_function_interrupt || ! call_used_regs [ temp ] || fixed_regs [ temp ] ) temp = - <NUM_LIT> ; if ( temp < <NUM_LIT> && ! current_function_interrupt && epilogue_p >= <NUM_LIT> ) { HARD_REG_SET temps = ( regs_invalidated_by_call & ~ fixed_reg_set & savable_regs ) ; if ( epilogue_p > <NUM_LIT> ) { int nreg = <NUM_LIT> ; if ( crtl -> return_rtx ) { machine_mode mode ; mode = GET_MODE ( crtl -> return_rtx ) ; if ( BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) nreg = hard_regno_nregs ( FIRST_RET_REG , mode ) ; } for ( i = <NUM_LIT> ; i < nreg ; i ++ ) CLEAR_HARD_REG_BIT ( temps , FIRST_RET_REG + i ) ; if ( crtl -> calls_eh_return ) { CLEAR_HARD_REG_BIT ( temps , EH_RETURN_STACKADJ_REGNO ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) CLEAR_HARD_REG_BIT ( temps , EH_RETURN_DATA_REGNO ( i ) ) ; } } if ( epilogue_p <= <NUM_LIT> ) { for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) { HARD_REG_SET temps ; temps = * live_regs_mask ; CLEAR_HARD_REG_BIT ( temps , REGNO ( reg ) ) ; temp = scavenge_reg ( & temps )


<s> const Align MaxAlign = MCP -> getConstantPoolAlign ( ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : Align ( <NUM_LIT> ) ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( Log2 ( MaxAlign ) + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; Align Alignment = CPs [ i ] . getAlign ( ) ; assert ( isAligned ( Alignment , Size ) && <STR_LIT> ) ; unsigned LogAlign = Log2 ( Alignment ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= Log2 ( MaxAlign ) ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Alignment . value ( ) << '\n' ) ; } LLVM_DEBUG ( BB -> dump


<s> std :: swap ( V1 , V2 ) ; Swap = true ; } bool IsUndefOrZero = V2 . isUndef ( ) || isZerosVector ( V2 . getNode ( ) ) ; MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SmallVector < SDValue , <NUM_LIT> > TBLMask ; for ( int Val : ShuffleMask ) { for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; if ( Swap ) Offset = Offset < IndexLen ? Offset + IndexLen : Offset - IndexLen ; if ( IsUndefOrZero && Offset >= IndexLen ) Offset = <NUM_LIT> ; TBLMask . push_back ( DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; } } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( IsUndefOrZero ) { if ( IndexLen == <NUM_LIT> ) V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V1Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst , DAG . getBuildVector ( IndexVT , DL , makeArrayRef ( TBLMask . data ( ) , IndexLen ) ) ) ; } else


<s> case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , <STR_LIT> ) ; break ; } if ( Subtarget -> isPICStyleGOT ( ) || Subtarget ->


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > <NUM_LIT> && ML -> getSubLoops ( ) . empty ( ) ) return Align ( <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > <NUM_LIT> ) break ; } if ( LoopSize > <NUM_LIT> && LoopSize <= <NUM_LIT> ) return Align ( <NUM_LIT> ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML


<s> void printanymem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo


<s> dbgs ( ) << Msg . c_str ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Bytes . size ( ) ; i ++ ) dbgs (


<s> void <ISA_LIT>InstPrinter :: printInstSyncBOption ( const MCInst * MI , unsigned OpNum , raw_ostream


<s> SDNode * <ISA_LIT>DAGToDAGISel :: QuadSRegs ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> if ( ! isa < ConstantDataArray > ( Init ) || ! Ty -> getArrayElementType ( ) -> isIntegerTy ( ) || Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) != VT . getSizeInBits ( ) || Ty -> getArrayNumElements ( ) > Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) ) continue ; uint64_t ArrayElementCount = Init -> getType ( ) -> getArrayNumElements ( ) ; bool ConstantsMatch = true ; for ( uint64_t j = <NUM_LIT> ; j < ArrayElementCount ; j ++ ) { ConstantInt * Elem = dyn_cast < ConstantInt > ( Init -> getAggregateElement ( j ) ) ; if ( Elem -> getZExtValue ( ) != ( ( ( uint64_t ) <NUM_LIT> << j ) - <NUM_LIT> ) ) { ConstantsMatch = false ; break ; } } if ( ! ConstantsMatch ) continue ; SDValue Inp = ( i == <NUM_LIT> ) ? Node -> getOperand ( <NUM_LIT> ) : Node -> getOperand ( <NUM_LIT> ) ; SDValue SizeC = DAG . getConstant ( VT . getSizeInBits ( ) , dl , VT ) ; SDValue Index = getIndexFromUnindexedLoad ( Ld ) ; if ( ! Index ) return SDValue


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < <NUM_LIT> ) { rtx_insn *


<s> } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == AtomicOrdering :: Release ) { Domain = <STR_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case CEK_CALL_HI16 : case


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index ==


<s> const TargetFrameLowering * getFrameLowering ( ) const override


<s> MCELFStreamer * llvm :: create<ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler


<s> I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return std :: min ( Size /


<s> static MCSymbol * getBFLabel ( StringRef Prefix , unsigned FunctionNumber , unsigned LabelId , MCContext & Ctx ) { MCSymbol * Label = Ctx . getOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> +

Twine ( FunctionNumber ) + <STR_LIT> + Twine ( LabelId ) ) ;


<s> SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . isFPOnlySP ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; assert ( ! DstRegs . count ( Src ) && <STR_LIT> ) ; DstRegs . insert ( Dst ) ; Mov = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) ; if ( Opc == <STR_LIT> ) Mov . addReg ( Src ) ; Mov = AddDefaultPred ( Mov ) ; if ( Opc == <STR_LIT> ) Mov = AddDefaultCC (


<s> rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != <NUM_LIT> && info -> first_gp_reg_save != <NUM_LIT> ) ) return emit_insn (


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) Val = <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return


<s> return DAG . getRegister ( FI -> getGlobalBaseReg ( )


<s> MachineBasicBlock * MBB = & PrologMBB ; MachineBasicBlock :: iterator MBBI = StackAllocMI ; const DebugLoc DL = StackAllocMI -> getDebugLoc ( ) ; auto allocateAndProbe = [ & ] ( MachineBasicBlock & InsMBB , MachineBasicBlock :: iterator InsPt , unsigned Size , bool EmitCFI ) -> void { emitIncrement ( InsMBB , InsPt , DL , <STR_LIT> , - int64_t ( Size ) , ZII ) ; if ( EmitCFI ) { SPOffsetFromCFA -= Size ; buildCFAOffs ( InsMBB , InsPt , DL , SPOffsetFromCFA , ZII ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( InsMBB , InsPt , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( Size - <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } ; bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; MachineBasicBlock * DoneMBB = nullptr ; MachineBasicBlock * LoopMBB = nullptr ; if ( NumFullBlocks < <NUM_LIT> ) { for ( unsigned int i = <NUM_LIT> ; i < NumFullBlocks ; i ++ ) allocateAndProbe ( * MBB , MBBI , ProbeSize , true ) ; } else { uint64_t LoopAlloc = ProbeSize * NumFullBlocks ; SPOffsetFromCFA -= LoopAlloc ; BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; buildDefCFAReg ( * MBB , MBBI , DL , <STR_LIT> , ZII ) ; emitIncrement ( * MBB , MBBI , DL , <STR_LIT> , - int64_t ( LoopAlloc ) , ZII ) ; buildCFAOffs ( * MBB , MBBI , DL , - int64_t ( <STR_LIT> + LoopAlloc ) , ZII ) ; DoneMBB = <STR_LIT> ( MBBI , MBB ) ; LoopMBB = <STR_LIT> ( MBB ) ; MBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; MBB = LoopMBB ; allocateAndProbe ( * MBB , MBB -> end ( ) , ProbeSize , false ) ; BuildMI ( * MBB , MBB -> end ( ) , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * MBB , MBB -> end ( ) , DL , ZII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm (


<s> int loongarch_const_insns ( rtx x ) { enum loongarch_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! loongarch_symbolic_constant_p ( XEXP ( x , <NUM_LIT> ) , & symbol_type ) || ! loongarch_split_symbol_type ( symbol_type ) ) return <NUM_LIT> ; return <NUM_LIT> ; case CONST_INT : return loongarch_integer_cost ( INTVAL ( x ) ) ; case CONST_VECTOR : case CONST_DOUBLE : return x == CONST0_RTX ( GET_MODE ( x ) ) ? <NUM_LIT> : <NUM_LIT> ; case CONST : if ( loongarch_symbolic_constant_p ( x , & symbol_type ) ) return loongarch_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != <NUM_LIT> ) { int n = loongarch_const_insns ( x ) ; if ( n


<s> * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( MEM_ALIGN ( mem ) , length * BITS_PER_UNIT


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsSHL ( uint64_t Imm , unsigned RemSize ,


<s> SDValue Ops [ ] = { Chain , StackSlot } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MPI , <NUM_LIT> , MachineMemOperand :: MOStore ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MPI , <NUM_LIT> ) ; Chain = CWD . getValue ( <NUM_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; SDValue LUT = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,

LUT , Shift ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( Val & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && Val % <NUM_LIT> == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( Val >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true


<s> return getGOT ( GN , DAG , OpFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , OpFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { Result = getAddrTiny ( GN , DAG , OpFlags ) ; } else { Result = getAddr ( GN , DAG , OpFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ; if ( OpFlags & ( <STR_LIT> | <STR_LIT> ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode (

) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubNoDynamic ( ) ) { OpFlag = <STR_LIT> ; } auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT (

) , false , false , false , <NUM_LIT> ) ;


<s> if ( ! OpVT . is128BitVector ( ) ) { unsigned SizeFactor = OpVT . getSizeInBits ( ) / <NUM_LIT> ; MVT VT128 = <STR_LIT> ( OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / SizeFactor ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } assert ( OpVT . is128BitVector (


<s> if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { printOperand ( MI , OpNum , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNum + <NUM_LIT> , STI , O ) ; return ; } if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { } else { printOperand ( MI , OpNum + <NUM_LIT> , STI , O ) ; } if ( MI -> getOperand ( OpNum ) . isImm ( ) && MI -> getOperand ( OpNum ) . getImm ( ) == <NUM_LIT> ) { if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; } else


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget ( ) ) , TII ( * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) , TLI ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) { MFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; Context = & funcInfo . Fn -> getContext (


<s> } else { SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue PackedElt = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { Vec , HalfIdx } ) , <NUM_LIT> ) ; SDValue AndIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { AndIdx , Const1 } ) ; SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Mask , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Val , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> case UNSPEC_PCREL_OPT_ST_ADDR : orig_x = XVECEXP ( orig_x , <NUM_LIT> , <NUM_LIT> ) ; break ; default : break ; } orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , <NUM_LIT> ) ) ) { offset = XEXP ( y , <NUM_LIT> ) ; y = XEXP ( y , <NUM_LIT> ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_XCOFF && SYMBOL_REF_P ( y ) && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode


<s> if ( L && ! L -> isLoopInvariant ( MI ) ) return false ; MachineInstr * MovMI = MRI -> getUniqueVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SubregToRegMI = nullptr ; if ( MovMI -> getOpcode ( ) == TargetOpcode :: SUBREG_TO_REG ) { SubregToRegMI = MovMI ; MovMI = MRI -> getUniqueVRegDef ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MovMI -> getOpcode ( ) != <STR_LIT> && MovMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneUse ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( SubregToRegMI && ! MRI -> hasOneUse ( SubregToRegMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; T UImm = static_cast < T > ( MovMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( SubregToRegMI ) UImm &= <NUM_LIT> ; T Imm1Enc ; T Imm2Enc ; if ( ! splitBitmaskImm ( UImm , RegSize , Imm1Enc , Imm2Enc ) ) return false ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetRegisterClass * ANDImmRC = ( RegSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg (


<s> if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) )


<s> return ( unsigned ) ( ( imm >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT>


<s> bool isMachineBasicBlock ( ) const { return Kind ==