<s> if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; for ( const SDNode * U : N -> uses ( ) ) if ( U -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; auto OpSize = N -> getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; unsigned Size = DAG . getDataLayout ( ) . getLargestLegalIntTypeSizeInBits ( ) ; if ( OpSize < Size ) { switch ( CC ) { default : break ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , false , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , true , true , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , false , true , DL , DAG ) ; case <STR_LIT> : return generateEquivalentSub ( N , Size , true , false , DL , DAG ) ; } } return SDValue (


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || CurSlots == <NUM_LIT> ) { CurGroup . clear ( ) ; CurSlots = CurBranches = <NUM_LIT> ; } else


<s> void <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ,


<s> Inst . addOperand ( MCOperand :: createReg ( PRRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed =


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return


<s> SDValue FprPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue FprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , false , <NUM_LIT> ) ; InChain = FprIndex . getValue ( <NUM_LIT> ) ; SDValue RegSaveAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = OverflowArea . getValue ( <NUM_LIT> ) ; SDValue RegSaveArea = DAG . getLoad ( <STR_LIT> , dl , InChain , RegSaveAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = RegSaveArea . getValue ( <NUM_LIT> ) ; SDValue CC = DAG . getSetCC ( dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue RegConstant = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT . isInteger ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , RegSaveArea , RegConstant ) ; if ( VT . isFloatingPoint ( ) ) OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , OurReg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue IndexPlus1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; InChain = DAG . getTruncStore ( InChain , dl , IndexPlus1 , VT . isInteger ( ) ? VAListPtr : FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , CC , OurReg , OverflowArea ) ; SDValue OverflowAreaPlusN = DAG . getNode ( <STR_LIT> , dl , PtrVT , OverflowArea , DAG . getConstant ( VT


<s> Register LastVReg = Last . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineOperand & MO : llvm :: make_early_inc_range ( MRI -> use_operands ( LastVReg ) ) ) { MachineInstr & MI = * MO . getParent ( ) ; if ( MI . isDebugValue ( ) ) { replaceDebugValue ( MI , LastVReg , FirstVReg , AddrDispShift ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; MO . setReg ( FirstVReg ) ; MachineOperand & Op = MI . getOperand ( MemOpNo + <STR_LIT> ) ; if ( Op . isImm ( ) ) Op . setImm ( Op . getImm ( ) + AddrDispShift ) ; else if ( ! Op . isJTI ( ) ) Op . setOffset ( Op . getOffset ( ) + AddrDispShift ) ; } MRI -> clearKillFlags ( FirstVReg ) ; ++ NumRedundantLEAs


<s> bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < <NUM_LIT> ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , <NUM_LIT> , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT>


<s> if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ <NUM_LIT> ] , count = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == <NUM_LIT> ) { rtvec p = rtvec_alloc ( <NUM_LIT> ) ; rtvec r = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( r , <NUM_LIT> ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [


<s> return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , <STR_LIT> ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } } MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , <STR_LIT> ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Start , Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( LRDef ) ; InsertBB = LRDef -> getParent ( ) ; return true ; } } if ( ! RDA . isSafeToDefRegAt ( Start , <STR_LIT> ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } ; auto TryAdjustInsertionPoint = [ ] ( MachineBasicBlock :: iterator & InsertPt , MachineInstr * Start , ReachingDefAnalysis & RDA ) { MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MachineBasicBlock :: iterator FirstNonTerminator = MBB -> getFirstTerminator ( ) ; unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstNonTerminator == MBB -> end ( ) ) { if ( RDA . isReachingDefLiveOut ( Start , CountReg ) && RDA . isReachingDefLiveOut ( Start , <STR_LIT> ) )


<s> return iterator_range < promoted_iterator > ( GVars . begin


<s> unsigned Reg = F128RegDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> if ( ST -> hasMVEIntegerOps ( ) && ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { return std :: max ( BaseT :: getVectorInstrCost ( Opcode , ValTy , Index ) , ST -> getMVEVectorCostFactor ( ) ) * cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) / <NUM_LIT> ; } return BaseT :: getVectorInstrCost ( Opcode


<s> case <STR_LIT> : if ( auto * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getZExtValue ( ) >= <NUM_LIT> ) return DAG . getStore ( N -> getOperand ( <NUM_LIT> ) , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) ) ; break ; } return SDValue


<s> SDValue getAddrGlobalLargeGOT ( NodeTy * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned HiFlag , unsigned LoFlag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi ,


<s> if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> || LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> || LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> )


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( isIntrinsic ) { VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && ( ! CInc || CInc -> getZExtValue ( ) != NumBytes ) ) { continue ; } EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment ( ) ; if ( isa < LSBaseSDNode > ( N ) ) { if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; if ( Alignment < VecTy . getScalarSizeInBits ( ) / <NUM_LIT> ) { MVT EltTy = <STR_LIT> ( Alignment * <NUM_LIT> ) ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; assert ( ! isLaneOp && <STR_LIT> ) ; unsigned NumElts = NumBytes / ( EltTy . getSizeInBits ( ) / <NUM_LIT> ) ; AlignedVecTy = <STR_LIT> ( EltTy , NumElts ) ; } Alignment = <NUM_LIT> ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoadOp ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = AlignedVecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumResultVecs + <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; Ops . push_back ( Inc ) ; if ( StoreSDNode * StN = dyn_cast < StoreSDNode > ( N ) ) { Ops . push_back ( StN -> getValue ( ) ) ; }


<s> static SDValue performABSCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SDValue AbsOp1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op0 , Op1 ; if ( AbsOp1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Op0 = AbsOp1 . getOperand ( <NUM_LIT> ) ; Op1 = AbsOp1 . getOperand ( <NUM_LIT> ) ; unsigned Opc0 = Op0 . getOpcode ( ) ; if ( Opc0 != Op1 . getOpcode ( ) || ( Opc0 != <STR_LIT> && Opc0 != <STR_LIT> ) ) return SDValue ( ) ; EVT VectorT1 = Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT VectorT2 = Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; uint64_t Size = VectorT1 . getFixedSizeInBits ( ) ; if ( VectorT1 != VectorT2 || ( Size != <NUM_LIT> && Size != <NUM_LIT> ) ) return SDValue ( ) ; EVT VT1 = VectorT1 . getVectorElementType ( ) ; if ( VT1 != <STR_LIT> && VT1 != <STR_LIT> && VT1 != <STR_LIT> ) return SDValue ( ) ; Op0 = Op0 . getOperand


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , DL . getPointerSizeInBits ( <NUM_LIT> ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( VecVT == <STR_LIT> ) return HasVSX ? <STR_LIT> : <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; default : break ; } llvm_unreachable ( <STR_LIT> ) ; } else { switch ( CC ) { case <STR_LIT> : CC = <STR_LIT> ; Swap = true ; break ; case <STR_LIT> : CC = <STR_LIT> ; Swap = true ; break ; case <STR_LIT> : CC = <STR_LIT> ; Swap = true ; break ; case <STR_LIT> : CC = <STR_LIT> ; Swap = true ; break ; default : break ; } switch ( CC ) { case <STR_LIT> : CC = <STR_LIT> ; Negate = true ; break ; case <STR_LIT> : CC = <STR_LIT> ; Negate = true ; break ; case <STR_LIT> : CC = <STR_LIT> ; Negate = true ; break ; case <STR_LIT> : CC = <STR_LIT> ; Negate = true ; break ; default : break ; } switch ( CC ) { case <STR_LIT> : case <STR_LIT> : if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; case <STR_LIT> : if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; case <STR_LIT> : if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; default : break ; } llvm_unreachable ( <STR_LIT> )


<s> unsigned <STR_LIT> ( ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) const { if ( Kind != SK_Reverse && Kind != SK_Alternate ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; if ( Kind == SK_Reverse ) { static const CostTblEntry < <STR_LIT> > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup ( NEONShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONShuffleTbl [ Idx ]


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value <<= Info . TargetOffset ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup . getOffset (


<s> SDValue <ISA_LIT>TargetLowering :: get<ISA_LIT>Cmp ( SDValue LHS , SDValue RHS , <STR_LIT> CC , SDValue & <ISA_LIT>cc , SelectionDAG & DAG , const SDLoc & dl ) const { if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS . getNode ( ) ) ) { unsigned C = RHSC -> getZExtValue ( ) ; if ( ! isLegalICmpImmediate ( ( int32_t ) C ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; } } } else if ( ( <STR_LIT> ( LHS . getOpcode ( ) ) != <STR_LIT> ) && ( <STR_LIT> ( RHS . getOpcode ( ) ) == <STR_LIT> ) ) { CC = <STR_LIT> ( CC


<s> break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create


<s> static bool isMOVDDUPYMask ( ArrayRef < int > Mask , MVT VT , bool HasFp256 ) { if ( ! HasFp256 || ! VT . is256BitVector ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElts / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Mask [


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; emitNops ( NoopsInSledCount ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups , STI ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT>

, MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> rtx insn ; if ( val == NULL_RTX || INTVAL ( val ) == <NUM_LIT> ) { gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_CONST ) ) ; insn = emit_insn ( gen_addsi3 ( dest , src


<s> static inline Relocator :: Address helper_get_page_address (


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Ra , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) )


<s> if ( F -> hasDLLExportLinkage ( ) ) DLLExportedFns . insert ( Mang -> makeNameProper ( F -> getName ( ) , <STR_LIT> ) ) ; emitFunctionHeader ( MF ) ; if ( TAI -> doesSupportDebugInformation ( ) || TAI -> doesSupportExceptionHandling ( ) ) DW -> BeginFunction ( & MF ) ; bool hasAnyRealCode = false ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! VerboseAsm && ( I -> pred_empty ( ) || I -> isOnlyReachableByFallthrough ( ) ) ) { } else { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , IE = I -> end ( ) ; II != IE ; ++ II ) { if ( ! II -> isLabel ( ) ) hasAnyRealCode = true ; printMachineInstruction ( II ) ; } } if ( Subtarget -> isTargetDarwin ( ) && ! hasAnyRealCode ) { O << <STR_LIT> ; } if ( TAI -> hasDotTypeDotSizeDirective ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << '\n' ; if ( TAI -> doesSupportDebugInformation ( ) ) DW -> EndFunction ( & MF ) ; EmitJumpTableInfo ( MF . getJumpTableInfo


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> vqtbx2q_u8 ( uint8x16_t r , uint8x16x2_t tab , uint8x16_t idx ) { __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( uint8x16_t ) __builtin_aarch64_tbx4v16qi ( ( int8x16_t ) r , __o , ( int8x16_t )


<s> DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) Mask . push_back ( Builder . getInt32 ( Start + i ) ) ; return ConstantVector :: get


<s> return __builtin_mve_vdwdupq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a ,


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( )


<s> WidenedLoad ( SmallVectorImpl < LoadInst * > & Lds , LoadInst * Wide ) : NewLd ( Wide ) { append_range ( Loads ,


<s> bool useAA ( ) const override { return isCortexA53 ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> epilogue_completed = <NUM_LIT> ; no_new_pseudos = <NUM_LIT> ; reset_block_changes ( ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else this = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; emit_insn ( TARGET_32BIT ? gen_addsi3 ( this , this , delta_rtx ) : gen_adddi3 ( this , this , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this ) ) ; if ( ( ( unsigned HOST_WIDE_INT ) vcall_offset ) + <NUM_LIT> >= <NUM_LIT> ) { emit_insn ( TARGET_32BIT ? gen_addsi3 ( tmp , tmp , vcall_offset_rtx ) : gen_adddi3 ( tmp , tmp , vcall_offset_rtx ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; } else { rtx loc = gen_rtx_PLUS ( Pmode , tmp , vcall_offset_rtx ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( TARGET_32BIT ? gen_addsi3 ( this , this , tmp ) : gen_adddi3 ( this , this , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE


<s> if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT> ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; for ( unsigned i = <NUM_LIT> ; i < SplitEVTs . size ( ) ; ++ i ) { ArgInfo CurArgInfo ( VRegs [ i ] , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) ) ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( CurArgInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder .


<s> Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isPhysicalRegister ( Reg ) ) return nullptr ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( Reg ) ; while ( true ) { if ( DefMI -> getParent ( ) != MBB ) break ; if ( DefMI -> isCopyLike ( ) ) { Reg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister


<s> void printi64mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . i [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) >> <NUM_LIT> ) & <NUM_LIT>


<s> if ( CVal == <NUM_LIT> ) break ; return ; } Result = DAG . getTargetConstant ( CVal , Op . getValueType ( ) ) ; break ; } case 'S' : { if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) { Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Op ) , GA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) { Result = DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , BA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) { Result = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) ) ; } else return ; break ; } case 'Y' : if ( const ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { if ( CFP -> isExactlyValue ( <NUM_LIT> ) ) { Result = DAG . getTargetConstantFP ( <NUM_LIT> , CFP -> getValueType ( <NUM_LIT> ) ) ; break ; } } return ; } if ( Result . getNode (


<s> return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , T , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { T , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) , Op . getValue ( <NUM_LIT> ) ) ; case <STR_LIT> : { Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , Op ) , <NUM_LIT> ) ; SDNode * AD = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> ) ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( AD , <NUM_LIT> ) , Op , SDValue ( AD , <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) ; SDValue AN = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , AD , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { AN , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT>


<s> bool hasVAES ( ) const { return HasVAES


<s> static unsigned getANDriOpcode ( bool IsLP64 , int64_t Imm ) { if ( IsLP64 ) { if ( isInt < <NUM_LIT> > ( Imm ) )


<s> bool hasVMLxHazards ( ) const { return HasVMLxHazards


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = <NUM_LIT> ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = <NUM_LIT> ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes ,


<s> if ( ST -> isAtom ( ) ) return <NUM_LIT> ; if ( ST -> hasAVX ( )


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizePICCallPass ( <ISA_LIT>TargetMachine & TM ) { return new OptimizePICCall (


<s> ret_type = void_type_node ; for ( i = <NUM_LIT> ; s16builtins [ i ] . name ; i ++ ) { args = void_list_node ; for ( a = strlen ( s16builtins [ i ] . arg_types ) - <NUM_LIT> ; a >= <NUM_LIT> ; a -- ) { switch ( s16builtins [ i ] . arg_types [ a


<s> return Opcode ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) >= <NUM_LIT> ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool OptForSize = F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; if ( ConstSplatVal && ( Subtarget -> hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget -> hasAVX2 ( ) ) ) ) { const Constant * C = nullptr


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ( Value & <NUM_LIT> ) != <NUM_LIT> && ( Value & <NUM_LIT> ) != <NUM_LIT> ) return false ; return true


<s> return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex


<s> } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; case <STR_LIT> : CastOpc =


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT>


<s> unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else { Expr = getImm ( ) ; } <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { return DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF || ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF && Addend == <NUM_LIT> ) || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ||

ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ;


<s> uint32_t Bits = Mapper . fromString ( getSysReg ( ) , Valid ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> if ( old_tree != target_option_current_node ) new_tree = target_option_current_node ; else new_tree = NULL_TREE ; } else { new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; } if ( TARGET_DEBUG_TARGET ) { if ( new_tree ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( new_tree ) ; } if ( old_tree ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( old_tree ) ; } if ( old_tree != NULL_TREE || new_tree != NULL_TREE


<s> HOST_WIDE_INT offset = <NUM_LIT> ; Mnode * mp ; minipool_barrier = barrier ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { mp -> offset


<s> static bool isValidCopy ( const MachineInstr & I , const RegisterBank & DstBank , const MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI ,


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT>


<s> setArgFlags ( OrigArg , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ Idx ] , Regs , Offsets ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_<ISA_LIT> , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB (


<s> return ; } ( void ) Opc ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % <NUM_LIT> ==


<s> } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getStoreSize ( ) ; Align Alignment ( Size ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , Alignment ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( VT , SrcVT , dl , Chain , StackSlot , MPI , Alignment , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first


<s> case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } if ( RegBank


<s> machine_mode new_mode = VOIDmode ; if ( type ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> && ag_count <= <NUM_LIT> ) * count = ag_count ; else return false ; } else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) { * count = <NUM_LIT> ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { * count = <NUM_LIT> ; new_mode = ( mode == DCmode ? DFmode : SFmode ) ; } else return false


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else


<s> return ( __m256i ) __builtin_ia32_cvtmask2q256


<s> return ia64_function_arg_1 ( cum , mode , type , named


<s> Out . emitInstruction ( Inst , getSTI ( ) ) ; if ( LVIInlineAsmHardening ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && applyLVICFIMitigation ( Inst ) ) return ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) applyLVILoadHardeningMitigation ( Inst ,


<s> return false ; case <STR_LIT> : ExpandBuildPairF64 ( MBB , MI ) ; break ; case <STR_LIT> : ExpandExtractElementF64 ( MBB , MI )


<s> MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , GetCPISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF (


<s> BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else if ( NumElts == <NUM_LIT> ) { BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else return SDValue ( ) ; unsigned Bits32 = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( ! isa < ConstantSDNode > ( V ) && ! V . isUndef ( ) ) continue ; bool BitSet = V . isUndef ( ) ? false : cast < ConstantSDNode > ( V ) -> getZExtValue ( ) ; if ( BitSet ) Bits32 |= BoolMask << ( i * BitsPerBool ) ; } SDValue Base = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( Bits32 , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( isa < ConstantSDNode > ( V ) || V . isUndef ( ) ) continue ; Base = DAG . getNode ( <STR_LIT> , dl , VT , Base , V , DAG . getConstant ( i , dl , <STR_LIT> ) ) ; } return


<s> assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = getOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true


<s> return __builtin_mve_vcmpeqq_m_sv4si ( __a ,


<s> static inline uint32_t helper_reencode_ldst_pos_imm ( uint32_t pInst , uint32_t pImm ) { return ( pInst & ~ ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) )

| ( ( pImm & get_mask ( <NUM_LIT> ) ) << <NUM_LIT> ) ;


<s> int64_t ImmVal = Imm ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> )


<s> std :: set < MachineInstr * > getPhiNodes (


<s> unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( DL ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc =


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { bool closeParen = printVariantKind (


<s> MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; assert ( DAG . getTargetLoweringInfo ( ) . getBooleanContents ( InVT ) == TargetLoweringBase :: ZeroOrNegativeOneBooleanContent && <STR_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue


<s> if ( VSXSelfCopyCrash && SrcReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; DestReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ||


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI . adjustsStack


<s> static void lowerAlignmentHint ( const MachineInstr * MI , MCInst & LoweredMI , unsigned Opcode ) { if ( ! MI -> hasOneMemOperand ( ) ) return ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; unsigned AlignmentHint = <NUM_LIT>


<s> const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs , NumArgRegs ) ; if ( RegNum != NumArgRegs && ArgRegs [ RegNum ] == <STR_LIT> ) { State . AllocateReg ( ArgRegs [ RegNum


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; unsigned RegNum = matchRegisterNameAlias ( Tok . getString ( ) . lower ( ) , false ) ; MCContext & Ctx = getContext ( ) ; const MCRegisterInfo * RI = Ctx . getRegisterInfo ( ) ; if ( ! RI -> getRegClass ( <STR_LIT> ) . contains ( RegNum ) ) return MatchOperand_NoMatch ; SMLoc S = getLoc


<s> static void sparc_file_end ( void ) { if ( got_helper_needed ) { const char * name = XSTR ( got_helper_rtx , <NUM_LIT> ) ; bool do_cfi ; if ( USE_HIDDEN_LINKONCE ) { tree decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; DECL_VISIBILITY_SPECIFIED ( decl ) = <NUM_LIT> ; resolve_unique_section ( decl , <NUM_LIT> , flag_function_sections ) ; allocate_struct_function ( decl , true ) ; cfun -> is_thunk = <NUM_LIT> ; current_function_decl = decl


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , mii ) ,

InstInfo ( nullptr ) , Code16GCC ( false ) {


<s> init_idents ( ) ; id = TREE_VALUE ( TREE_VALUE ( model_attr ) ) ; if ( id == small_ident1 || id == small_ident2 ) return ADDR_AREA_SMALL ; } return


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == nullptr && ! IndirectTlsSegRefs && ( Subtarget -> isTargetGlibc ( ) || Subtarget -> isTargetAndroid ( ) || Subtarget -> isTargetFuchsia ( ) ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) { case <NUM_LIT>


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) )


<s> RegisterBankInfo :: InstructionMapping <ISA_LIT>RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [


<s> static SDValue getScalarMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { if ( isAllOnesConstant ( Mask ) ) return Op ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT>


<s> EVT SrcVT , DestVT ; SrcVT = TLI . getValueType ( DL , Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return


<s> emitLabel ( Symbol ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF :: STB_LOCAL ) ; Symbol -> setExternal


<s> return ( __m512 ) __builtin_ia32_movshdup512_mask ( ( __v16sf ) __A , ( __v16sf )


<s> return ( __m256i ) __builtin_ia32_pmovsxbq256_mask ( ( __v16qi ) __A ,


<s> if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && nb == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - ne ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( nb < <NUM_LIT> && ne


<s> const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT> ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; CallingConv :: ID CC = F . getCallingConv ( ) ; for ( unsigned i = <NUM_LIT> ; i < SplitEVTs . size ( ) ; ++ i ) { Register CurVReg = VRegs [ i ] ; ArgInfo CurArgInfo = ArgInfo { CurVReg , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) , <NUM_LIT> } ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; if ( MRI . getType ( CurVReg ) . getSizeInBits ( ) == <NUM_LIT> ) { CurVReg = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , CurVReg ) . getReg ( <NUM_LIT> ) ; } else if ( TLI . getNumRegistersForCallingConv ( Ctx , CC , SplitEVTs [ i ] ) == <NUM_LIT> ) { MVT NewVT = TLI . getRegisterTypeForCallingConv ( Ctx , CC , SplitEVTs [ i ] ) ; if ( EVT ( NewVT ) != SplitEVTs [ i ] ) { unsigned ExtendOp = TargetOpcode :: G_ANYEXT ; if ( F . getAttributes ( ) . hasAttribute ( AttributeList :: ReturnIndex , Attribute :: SExt ) ) ExtendOp = TargetOpcode :: G_SEXT ; else if ( F . getAttributes ( ) . hasAttribute ( AttributeList :: ReturnIndex , Attribute :: ZExt ) ) ExtendOp = TargetOpcode :: G_ZEXT ; LLT NewLLT ( NewVT ) ; LLT OldLLT ( <STR_LIT> ( CurArgInfo . Ty ) ) ; CurArgInfo . Ty = EVT ( NewVT ) . getTypeForEVT ( Ctx ) ; if ( NewVT . isVector ( ) ) { if ( OldLLT . isVector ( ) ) { if ( NewLLT . getNumElements ( ) > OldLLT . getNumElements ( ) ) { if ( NewLLT . getNumElements ( ) != OldLLT . getNumElements ( ) * <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Undef = MIRBuilder . buildUndef ( { OldLLT } ) ; CurVReg = MIRBuilder . buildMerge ( { NewLLT } , { CurVReg , Undef } ) . getReg ( <NUM_LIT> ) ; } else


<s> break ; } } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; int Scale = RPI . Type == RegPairInfo :: FPR128 ? <NUM_LIT> : <NUM_LIT> ; Offset -= RPI . isPaired ( ) ? <NUM_LIT> * Scale : Scale ; if ( AFI -> hasCalleeSaveStackFreeSpace ( ) && RPI . Type != RegPairInfo :: FPR128 && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT>


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx rval , rtx mem ,


<s> Inst . addOperand ( MCOperand :: CreateImm ( ModImm . Bits |


<s> Value * <ISA_LIT>IREmitter :: visitTESTNM (


<s> bool evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const override { return


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; if ( offset < <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; } Val |=


<s> builtin_arg args [ SIMD_MAX_BUILTIN_ARGS ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = NEON_ARG_CONSTANT ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) { rtx arg = expand_normal ( CALL_EXPR_ARG ( exp , ( expr_args_k ) ) ) ; bool op_const_int_p = ( CONST_INT_P ( arg ) && ( * insn_data [ icode ] . operand [ operands_k ] . predicate ) ( arg , insn_data [ icode ] . operand [ operands_k ] . mode ) ) ; args [ k ] = op_const_int_p ? NEON_ARG_CONSTANT : NEON_ARG_COPY_TO_REG ; } else if ( d -> qualifiers [ qualifiers_k ] & qualifier_pointer ) args [ k ] = NEON_ARG_MEMORY ; else args [ k ] = NEON_ARG_COPY_TO_REG ; } args [ k ] =


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : case V2HQmode : case V2UHQmode : case V2HAmode


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> static DecodeStatus DecodeVecShiftR16Imm ( MCInst & Inst , unsigned Imm , uint64_t

Addr , const MCDisassembler * Decoder ) {


<s> HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( VOIDmode , dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == <NUM_LIT> ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI -> getOperand ( <NUM_LIT>


<s> ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o


<s> MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ?


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this ,


<s> if ( ! Reg . isVirtual ( ) ) return nullptr ; if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) { if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr


<s> if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI -> getOperand ( OpNum ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MBB . erase (


<s> static void fatal ( const char * msg ) { fprintf ( stderr , <STR_LIT> , msg ) ; abort (


<s> static machine_mode aarch64_simd_container_mode ( scalar_mode mode , poly_int64 width ) { if ( TARGET_SVE && maybe_ne ( width , <NUM_LIT> ) && known_eq ( width , BITS_PER_SVE_VECTOR ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; gcc_assert ( known_eq ( width , <NUM_LIT> ) || known_eq ( width , <NUM_LIT> ) ) ; if ( TARGET_SIMD ) { if ( known_eq ( width , <NUM_LIT> ) ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ; else switch ( mode ) { case E_SFmode : return V2SFmode ; case E_HFmode : return V4HFmode ; case E_BFmode : return V4BFmode ; case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case E_QImode


<s> auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr ,


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( NumElts != <NUM_LIT> || l == <NUM_LIT> ) continue ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Mask [ i + l ] , Mask [ i ] + l ) ) return false ; } } return true


<s> MCFixupKind Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return ; MCContext & Ctx = Asm . getContext ( ) ; MCFixupKindInfo Info = getFixupKindInfo ( Kind ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; bool IsLittleEndian = ( Endian == <STR_LIT> ) ; if ( IsLittleEndian && ( NumBytes == <NUM_LIT>


<s> if ( const Instruction * I = dyn_cast < Instruction > ( Obj ) ) { if ( FuncInfo . StaticAllocaMap . count ( static_cast < const AllocaInst * > ( Obj ) ) || FuncInfo . MBBMap [ I -> getParent ( ) ] == FuncInfo . MBB ) { Opcode = I -> getOpcode ( ) ; U = I ; } } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy


<s> StringRef ArchName = TargetTriple . getArchName ( ) ; if ( ArchName . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else if ( ArchName . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb1Only ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT


<s> if ( is<ISA_LIT>64 ( ) || isFP64 ( ) ) FpFormat = FP_FORMAT_D ; else FpFormat = FP_FORMAT_S


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { if ( getKind ( ) != VK_NONE ) OS << getVariantKindName ( ) ; Expr -> print ( OS


<s> <STR_LIT> expandPredBlockMask ( <STR_LIT> BlockMask , <STR_LIT> Kind ) { using PredBlockMask = <STR_LIT> ; assert ( Kind != <STR_LIT> && <STR_LIT> ) ; assert ( countTrailingZeros ( ( unsigned ) BlockMask ) != <NUM_LIT> && <STR_LIT> ) ; auto ChooseMask = [ & ] ( PredBlockMask AddedThen , PredBlockMask AddedElse ) { return Kind == <STR_LIT> ? AddedThen : AddedElse ; } ; switch ( BlockMask ) { case PredBlockMask :: T : return ChooseMask ( PredBlockMask :: TT


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) . isOneValue ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Src . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> isNullValue ( )

) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ;


<s> * get_cumulative_args ( cum ) += rx_function_arg_size


<s> unsigned getVarArgsFrameIndex ( ) const { return


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn (


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) ) ; return ( Base << <NUM_LIT>


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > (


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Reserved . set ( <STR_LIT> + i ) ; } const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved


<s> assert ( isUndefOrZero ( Mask [ i ] ) || ( Mask [ i ] >= <NUM_LIT> ) ) ; if ( Mask [ i ] == SM_SentinelUndef ) continue ; if ( Mask [ i ] == SM_SentinelZero ) { if ( ! isUndefOrZero ( RepeatedMask [ i % LaneSize ] ) ) return false ; RepeatedMask [ i % LaneSize ] = SM_SentinelZero ; continue ; } if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; int LocalM = Mask [ i ] < Size ? Mask [ i ] % LaneSize


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>64Target , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>64LETarget


<s> bool rs6000_builtin_is_supported_p ( enum rs6000_builtins fncode ) { HOST_WIDE_INT fnmask = rs6000_builtin_info [ fncode ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) return false ; else return true


<s> switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_<ISA_LIT>_THM_CALL : { uint64_t dest = pTargetSymValue + pReloc . addend ( ) + <NUM_LIT> ; int64_t branch_offset = static_cast < int64_t > ( dest ) - pSource ; if ( m_bUsingThumb2 ) { if ( ( branch_offset > <ISA_LIT>GNULDBackend :: THM2_MAX_FWD_BRANCH_OFFSET ) || ( branch_offset < <ISA_LIT>GNULDBackend :: THM2_MAX_BWD_BRANCH_OFFSET ) ) { result = true ; break ; } } else { if ( ( branch_offset > <ISA_LIT>GNULDBackend :: THM_MAX_FWD_BRANCH_OFFSET ) || ( branch_offset < <ISA_LIT>GNULDBackend :: THM_MAX_BWD_BRANCH_OFFSET ) ) { result = true ; break ; } } break ; } case llvm :: ELF ::


<s> if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { EVT VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << TRI -> getAsmName


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ||


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_named_abort ( unsigned char const code ) { __builtin_tabort (


<s> Inst . setOpcode ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( get<ISA_LIT>SubSuperRegister


<s> if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return


<s> if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align


<s> return ( __m128d ) __builtin_ia32_addpd128_mask ( ( __v2df ) __A , ( __v2df )


<s> } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef (


<s> bool invert = InvertFPCondCode ( ( <STR_LIT> ) cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ) ; return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True . getValueType ( ) ,


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val > - <NUM_LIT> && Val <


<s> ArrayRef < int > HiMask = Mask . slice ( Mask . size ( ) / <NUM_LIT> ) ; int NumElements = VT . getVectorNumElements ( ) ; int SplitNumElements = NumElements / <NUM_LIT> ; MVT ScalarVT = VT . getScalarType ( ) ; MVT SplitVT = <STR_LIT> ( ScalarVT , NumElements / <NUM_LIT> ) ; auto SplitVector = [ & ] ( SDValue V ) { while ( V . getOpcode ( ) == <STR_LIT> ) V = V -> getOperand ( <NUM_LIT> ) ; MVT OrigVT = V . getSimpleValueType ( ) ; int OrigNumElements = OrigVT . getVectorNumElements ( ) ; int OrigSplitNumElements = OrigNumElements / <NUM_LIT> ; MVT OrigScalarVT = OrigVT . getScalarType ( ) ; MVT OrigSplitVT = <STR_LIT> ( OrigScalarVT , OrigNumElements / <NUM_LIT> ) ; SDValue LoV , HiV ; auto * BV = dyn_cast < BuildVectorSDNode > ( V ) ; if ( ! BV ) { LoV = DAG . getNode ( <STR_LIT> , DL , OrigSplitVT , V , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; HiV = DAG . getNode ( <STR_LIT> , DL , OrigSplitVT , V , DAG . getIntPtrConstant ( OrigSplitNumElements ) ) ; } else { SmallVector < SDValue , <NUM_LIT> > LoOps , HiOps ; for ( int i = <NUM_LIT> ; i < OrigSplitNumElements ; ++ i ) { LoOps . push_back ( BV -> getOperand ( i ) ) ; HiOps . push_back ( BV -> getOperand ( i + OrigSplitNumElements ) ) ; } LoV = DAG . getNode ( <STR_LIT> , DL , OrigSplitVT , LoOps ) ; HiV = DAG . getNode ( <STR_LIT> , DL , OrigSplitVT , HiOps ) ; } return std :: make_pair ( DAG . getNode ( <STR_LIT> , DL , SplitVT , LoV ) , DAG . getNode ( <STR_LIT> , DL , SplitVT , HiV ) ) ; } ; SDValue LoV1 , HiV1 , LoV2 , HiV2 ; std :: tie ( LoV1 , HiV1 ) = SplitVector ( V1 ) ; std :: tie ( LoV2 , HiV2 ) = SplitVector ( V2 ) ; auto HalfBlend = [ & ] ( ArrayRef < int > HalfMask ) { bool UseLoV1 = false , UseHiV1 = false , UseLoV2 = false , UseHiV2 = false ; SmallVector < int , <NUM_LIT> > V1BlendMask , V2BlendMask , BlendMask ; for ( int i = <NUM_LIT> ; i < SplitNumElements ; ++ i ) { int M = HalfMask [ i ] ; if ( M >= NumElements ) { if ( M >= NumElements + SplitNumElements ) UseHiV2 = true ; else UseLoV2 =


<s> __builtin_ia32_pmovswb128mem_mask ( ( unsigned long long * ) __P , ( __v8hi )


<s> return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , NULL


<s> return ( int ) __builtin_loongarch_crc_w_b_w ( ( char ) _1 , ( int


<s> MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; MRI . constrainRegClass ( scratch , TRCsp ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; MRI . constrainRegClass ( incr , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( incr ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , scratch ) . addReg ( oldval ) . addReg ( incr ) . addImm ( Cond ) ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>_32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>_64Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( PR ) ; initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass (


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( HorizOpcode , LHS , RHS , DAG , Subtarget , IsFadd , PostShuffleMask ) ) { SDValue HorizBinOp = DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ; if ( ! PostShuffleMask . empty ( ) ) HorizBinOp = DAG . getVectorShuffle ( VT , SDLoc ( HorizBinOp ) , HorizBinOp , DAG . getUNDEF ( VT ) , PostShuffleMask ) ; return HorizBinOp ; } return SDValue ( )


<s> for ( unsigned Reg : RegList ) Inst . addOperand ( MCOperand :: createReg (


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ] && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , LocVT , LocInfo ) ) ; return true


<s> } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { UseCycle = RegNo ; bool isSStore = false ; switch ( UseMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSStore = true ; break ; } if ( ( isSStore && ( RegNo % <NUM_LIT> ) ) || UseAlign < <NUM_LIT> ) ++ UseCycle ; } else { UseCycle = RegNo


<s> SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> , Half = NumElems / <NUM_LIT> ; i != Half ; ++ i ) { Mask . push_back ( i +


<s> bool isFBits32 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <=


<s> else { return false ; } SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; unsigned EltsPerReg = ( IsDarwinILP32 && LocVT . SimpleTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned RegResult = State . AllocateRegBlock ( RegList , alignTo ( PendingMembers . size ( ) , EltsPerReg ) / EltsPerReg ) ; if ( RegResult && EltsPerReg == <NUM_LIT> ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ; State . addLoc ( It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } else if ( RegResult ) { assert ( EltsPerReg == <NUM_LIT> && <STR_LIT> ) ; bool UseHigh = false ; CCValAssign :: LocInfo Info ; for ( auto & It : PendingMembers ) { Info = UseHigh ? CCValAssign :: AExtUpper : CCValAssign :: ZExt ; State . addLoc ( CCValAssign :: getReg ( It . getValNo ( ) , <STR_LIT>


<s> static DecodeStatus DecodeVCVTImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler ::


<s> SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if (


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE2 ( ) || Subtarget .

hasX87 ( ) ) ) return AtomicExpansionKind :: None ;


<s> if ( alg == rep_prefix_1_byte || alg == rep_prefix_4_byte || alg == rep_prefix_8_byte ) return ! ( fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] || (

memset ? fixed_regs [ AX_REG ] : fixed_regs [ SI_REG ] ) ) ;


<s> Value * <ISA_LIT>TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr ->


<s> RC = & <STR_LIT> ; } MUL = genMadd ( MF , MRI , TII , Root , InsInstrs , <NUM_LIT> , Opc , RC ) ; break ; case MachineCombinerPattern :: MC_MULADDWI_OP1 : case MachineCombinerPattern :: MC_MULADDXI_OP1 : { const TargetRegisterClass * OrrRC ; unsigned BitSize , OrrOpc , ZeroReg ; if ( Pattern == MachineCombinerPattern :: MC_MULADDWI_OP1 ) { OrrOpc = <STR_LIT> ; OrrRC = & <STR_LIT> ; BitSize = <NUM_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { OrrOpc = <STR_LIT> ; OrrRC = & <STR_LIT> ; BitSize = <NUM_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned NewVR = MRI . createVirtualRegister ( OrrRC ) ; uint64_t Imm = Root . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Root . getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned Val = Root . getOperand ( <NUM_LIT> ) . getImm ( ) ; Imm = Imm << Val ; } uint64_t UImm = Imm << ( <NUM_LIT> - BitSize ) >> ( <NUM_LIT> - BitSize ) ; uint64_t Encoding ; if ( <STR_LIT> ( UImm , BitSize , Encoding ) ) { MachineInstrBuilder MIB1 = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( OrrOpc ) , NewVR ) . addReg ( ZeroReg ) . addImm ( Encoding ) ; InsInstrs . push_back ( MIB1 ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVR , <NUM_LIT> ) ) ; MUL = genMaddR ( MF , MRI , TII , Root , InsInstrs , <NUM_LIT> , Opc , NewVR , RC ) ; } break ; } case MachineCombinerPattern :: MC_MULSUBW_OP1 : case MachineCombinerPattern :: MC_MULSUBX_OP1 : { const TargetRegisterClass * SubRC ; unsigned SubOpc , ZeroReg ; if ( Pattern == MachineCombinerPattern :: MC_MULSUBW_OP1 ) { SubOpc = <STR_LIT> ; SubRC = & <STR_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { SubOpc = <STR_LIT> ; SubRC = & <STR_LIT> ; ZeroReg = <STR_LIT> ; Opc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned NewVR = MRI . createVirtualRegister ( SubRC ) ; MachineInstrBuilder MIB1 = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( SubOpc ) , NewVR ) . addReg ( ZeroReg ) . addOperand ( Root . getOperand ( <NUM_LIT> ) ) ; InsInstrs . push_back ( MIB1 ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVR , <NUM_LIT> ) ) ; MUL = genMaddR ( MF , MRI , TII , Root , InsInstrs , <NUM_LIT> , Opc , NewVR , RC ) ; break ; } case MachineCombinerPattern :: MC_MULSUBW_OP2 : case MachineCombinerPattern :: MC_MULSUBX_OP2 : if ( Pattern == MachineCombinerPattern :: MC_MULSUBW_OP2 ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else


<s> unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; while ( DefMI -> isCopy ( ) ) { unsigned CopyVReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( CopyVReg ) ) return false ; if ( ! MRI -> hasOneDef ( CopyVReg ) ) return false ; DefMI = MRI -> getVRegDef ( CopyVReg ) ; } switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { if ( IsTestAndBranch ) return false ; if ( DefMI -> getParent ( ) != MBB ) return false ; if ( ! MRI -> hasOneNonDBGUse ( VReg ) ) return false ; uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , ( DefMI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; unsigned NewReg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MI -> eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { if ( ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ! (

DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ;


<s> static bool isORCopyInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; default : return


<s> if ( OPTION_GLIBC ) return true ; else return


<s> if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; return ; } bool isSub = NumBytes < <NUM_LIT> ; if ( isSub ) NumBytes = - NumBytes ; while ( NumBytes ) { unsigned RotAmt = <STR_LIT> ( NumBytes ) ; unsigned ThisVal = NumBytes & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; assert ( ThisVal && <STR_LIT> ) ; NumBytes &= ~ ThisVal


<s> LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = ShAmt == <NUM_LIT> ? <NUM_LIT> : RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = ShAmt == <NUM_LIT> ? <NUM_LIT> : RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( III . ZeroIsSpecialNew ) { Register RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( Register :: isVirtualRegister ( RegToModify ) ) { const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify , NewRC ) ; } } } if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill ( DefMI , MI , ForwardKilledOperandReg ) ; return true


<s> ++ Count ; bool CanMergeOpc = Opc == MI -> getOpcode ( ) ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( ! CanMergeOpc ) { bool IsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( Opc , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) Opc ? <NUM_LIT> : <NUM_LIT> ) ; CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode ( MI -> getOpcode ( ) ) ; } if ( CanMergeOpc && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI -> mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool MIIsUnscaled = isUnscaledLdSt ( MI ) ; bool IsNarrowLoad = isNarrowLoad ( MI -> getOpcode ( ) ) ; if ( ! IsNarrowLoad && ! inBoundsForPair ( MIIsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsNarrowLoad || IsNarrowStore ) { if ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } else


<s> unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 ,


<s> return __builtin_ia32_vcvtph2uqq128_mask ( __A , _mm_setzero_si128 ( )


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; O << A64CondCodeToString ( static_cast < <STR_LIT> > ( MO


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } return MI . getOpcode (


<s> if ( ! VT . isInteger ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return nullptr ; RxSBGOperands RISBG ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return nullptr ; if ( Count == <NUM_LIT> ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return nullptr ; if ( VT == <STR_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) { auto * MaskN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( MaskN -> getZExtValue ( ) != RISBG . Mask ) { SDValue NewMask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewMask ) ; return SelectCode ( N ) ; } return nullptr ; } } if ( RISBG . Rotate == <NUM_LIT> && ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> ) ) { unsigned OpCode = ( RISBG . Mask == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( VT == <STR_LIT> ) { if ( Subtarget -> hasHighWord ( ) ) OpCode = ( RISBG . Mask


<s> static unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs - <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: CreateReg ( FirstReg +

getVectorListStart ( ) - <STR_LIT> ) ) ;


<s> Register Reg ; if ( parseRegister ( Reg ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( Reg . StartLoc , Reg . EndLoc ) ) ; return false ; } SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; Register Reg1 , Reg2 ; bool HaveReg1 , HaveReg2 ; const MCExpr * Expr ; const MCExpr * Length ; if ( parseAddress ( HaveReg1 , Reg1 , HaveReg2 , Reg2 , Expr , Length ) ) return true ; if ( HaveReg1 && Reg1 . Group != RegGR && Reg1 . Group != RegV && parseAddressRegister ( Reg1 ) ) return true ; if ( HaveReg2 && parseAddressRegister ( Reg2 ) )


<s> int mmix_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ATTRIBUTE_UNUSED ) { return DW_EH_PE_absptr


<s> if ( ftype -> getNumParams ( ) == <NUM_LIT> && isVaradic ) { int passed_args = dyn_cast < CallInst > ( I ) -> getNumArgOperands ( ) ; if ( passed_args > <NUM_LIT> ) passed_args = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < passed_args ; i ++ ) { final_taint |= ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; } } else { for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( func_md -> getNumOperands ( ) > i ) { MDNode * arg_node = dyn_cast < MDNode > ( func_md -> getOperand ( i ) . get ( ) ) ; MDString * sgx_type = dyn_cast < MDString > ( arg_node -> getOperand ( <NUM_LIT> ) . get ( ) ) ; if ( sgx_type -> getString ( ) . str ( ) . compare ( <STR_LIT> ) == <NUM_LIT> ) final_taint |= ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; } else { if ( ! isVaradic ) final_taint |= ( <NUM_LIT> << ( <NUM_LIT> - i ) ) ; } } MDNode * ret_md = I -> getMetadata ( <STR_LIT> ) ; if ( ret_md -> getNumOperands ( ) > <NUM_LIT> ) { MDString * sgx_type = dyn_cast < MDString > ( ret_md -> getOperand ( <NUM_LIT> ) . get ( ) ) ; if ( sgx_type -> getString ( ) . str ( ) . compare (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) , false ) ; addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( ) )