<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT>


<s> unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> ) { assert ( TM . getInstrInfo ( ) && <STR_LIT> ) ; return new <ISA_LIT>HazardRecognizer970 ( TM


<s> if ( GET_CODE ( x ) == PLUS && GET_MODE_SIZE ( mode ) < <NUM_LIT> && REG_P ( XEXP ( x , <NUM_LIT> ) ) && XEXP ( x , <NUM_LIT> ) == stack_pointer_rtx && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ! thumb_legitimate_offset_p ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) { rtx orig_x = x ; x = copy_rtx ( x ) ; push_reload ( orig_x , NULL_RTX , x_p , NULL , MODE_BASE_REG_CLASS ( mode ) , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && REG_P ( XEXP ( x , <NUM_LIT> ) ) && ! REG_MODE_OK_FOR_REG_BASE_P ( XEXP ( x , <NUM_LIT> ) , mode ) && ! REG_MODE_OK_FOR_REG_BASE_P ( XEXP ( x , <NUM_LIT> ) , mode ) ) { rtx orig_x = x ; x = copy_rtx ( x ) ; push_reload ( orig_x , NULL_RTX , x_p , NULL , MODE_BASE_REG_CLASS ( mode ) ,


<s> rtx body ; if ( ! TARGET_FIX_ERR_A53_835769 ) return false ; if ( ! INSN_P ( insn ) || recog_memoized ( insn ) < <NUM_LIT> ) return false ; attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev


<s> bool isFPXX ( ) const { return IsFPXX


<s> if ( ! isa < Instruction > ( V ) ) return false ; unsigned Opc = cast < Instruction > ( V ) -> getOpcode


<s> return ( __m256i ) __builtin_ia32_pmovqd512_mask ( ( __v8di ) __A ,


<s> unsigned LowElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getBuildVector ( <STR_LIT> , SDLoc ( N ) , { BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) } ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; SDLoc dl ( N ) ; for ( unsigned i = <NUM_LIT> ; i !=


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; machine -> static_chain_stack_bytes = - <NUM_LIT> ; machine -> pacspval_needed


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBZDisplacementBits ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CBZDisplacementBits ; case <STR_LIT> : return BCCDisplacementBits


<s> __inline__ static unsigned long long sh_media_MMULLO_WL ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> if ( in<ISA_LIT>16Mode ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Reg ; OperandMatchResultTy ResTy = parseAnyRegister ( Reg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false


<s> static bool IsIndirectCall ( const MachineInstr & MI ) { return ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode


<s> rtx exp = SET_SRC ( PATTERN ( insn ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MAC : case TYPE_DMAC : if ( REG_P ( XEXP ( exp , <NUM_LIT> ) ) ) return XEXP ( exp , <NUM_LIT> ) ; else return XEXP ( exp , <NUM_LIT> ) ; default : gcc_unreachable (


<s> LoadInst * <ISA_LIT>ParallelDSP :: CreateWideLoad ( MemInstList & Loads , IntegerType * LoadTy ) { assert ( Loads . size ( ) == <NUM_LIT> && <STR_LIT> ) ; LoadInst * Base = Loads [ <NUM_LIT> ] ; LoadInst * Offset = Loads [ <NUM_LIT> ] ; Instruction * BaseSExt = dyn_cast < SExtInst > ( Base -> user_back ( ) ) ; Instruction * OffsetSExt = dyn_cast < SExtInst > ( Offset -> user_back ( ) ) ; assert ( ( BaseSExt && OffsetSExt ) && <STR_LIT> ) ; std :: function < void ( Value * , Value * ) > MoveBefore = [ & ] ( Value * A , Value * B ) -> void { if ( ! isa < Instruction > ( A ) || ! isa < Instruction > ( B ) ) return ; auto * Source = cast < Instruction > ( A ) ; auto * Sink = cast < Instruction > ( B ) ; if ( DT -> dominates ( Source , Sink ) || Source -> getParent ( ) != Sink -> getParent ( ) || isa < PHINode > ( Source ) || isa < PHINode > ( Sink ) ) return ; Source -> moveBefore ( Sink ) ; for ( auto & Op : Source -> operands ( ) ) MoveBefore ( Op , Source ) ; } ; LoadInst * DomLoad = DT -> dominates ( Base , Offset ) ? Base : Offset ; IRBuilder < NoFolder > IRB ( DomLoad -> getParent ( ) , ++ BasicBlock :: iterator ( DomLoad ) ) ; const unsigned AddrSpace = DomLoad ->


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm (


<s> void setArgumentStackSize ( unsigned size ) { ArgumentStackSize = size


<s> void emitLocalEntry ( MCSymbolELF * S , const MCExpr * LocalOffset ) override { report_fatal_error ( <STR_LIT>


<s> vst4_s64 ( int64_t * __a , int64x1x4_t val ) { __builtin_aarch64_simd_xi __o ; int64x2x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ]


<s> MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT (

) ) PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ;


<s> void addT2SOImmNotOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; LLVMContext * Context = & MF -> getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; unsigned ConstAlign = MF -> getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF -> getConstantPool ( ) -> getConstantPoolIndex ( CPV , ConstAlign ) ; unsigned TempReg = MF -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc

) , TempReg ) . addConstantPoolIndex ( Idx ) ;


<s> static rtx gen_mcount_func_rtx ( void ) { if ( ! mcount_func_rtx ) mcount_func_rtx = init_one_libfunc


<s> const MCExpr * Val = <NUM_LIT> ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return <NUM_LIT> ; if ( ! Info . OpDecl ) return ErrorOperand ( Start , <STR_LIT> ) ; unsigned CVal = <NUM_LIT> ; switch ( OpKind


<s> uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Size = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Size = <NUM_LIT> ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<= <NUM_LIT> ; } ++


<s> if ( <ISA_LIT>FI -> usesPICBase ( ) ) { MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol (


<s> OptimizeSize = MinimizeSize = false ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second


<s> Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true ; ++


<s> MachineBasicBlock :: iterator DefMI = MRI -> getVRegDef ( Reg ) ; if ( ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) || DefMI -> getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ; for ( auto I = DefMI ; I != FrameSetup ; ++ I ) if ( I ->

isLoadFoldBarrier ( ) ) return nullptr ;


<s> inline static uint64_t val2MImm ( uint64_t Val ) { if ( Val == <NUM_LIT> ) return <NUM_LIT> ; if ( Val & ( UINT64_C ( <NUM_LIT> ) << <NUM_LIT> )


) ) _mm512_load_pd ( void const * __P ) {


<s> return ( uint64x2_t ) __builtin_aarch64_usublv2si ( ( int32x2_t ) __a , (


<s> case <STR_LIT> : return lowerV2F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8F16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT>


<s> unsigned <ISA_LIT>FastISel :: emitUMULL_rr ( MVT RetVT , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { if ( RetVT != <STR_LIT> ) return <NUM_LIT> ; return fastEmitInst_rrr ( <STR_LIT> , & <STR_LIT> , Op0 , Op0IsKill , Op1 ,


<s> int getStackPointerRegister ( ) override final {


<s> case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMADDSUB ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMOVMSK ( N , DAG , DCI ) ; case <STR_LIT> : case


<s> static HOST_WIDE_INT loongarch_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return <NUM_LIT> ; return crtl


<s> } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 ) ; } return Result


<s> unsigned LaneShift ; if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else if ( ( Binary & ( <NUM_LIT> << <NUM_LIT> ) ) != <NUM_LIT> ) LaneShift = <NUM_LIT> ; else LaneShift = <NUM_LIT> ; unsigned Lane = MI . getOperand ( LnOpIdx ) . getImm ( ) << LaneShift ; unsigned Opc1 = Lane >> <NUM_LIT> ; unsigned Opc2 = Lane & <NUM_LIT> ; assert ( ( Opc1 & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= ( Opc1 << <NUM_LIT> ) ; Binary |= ( Opc2 << <NUM_LIT> ) ; emitWordLE (


<s> SDValue BasePtr = cast < LoadSDNode > ( Load ) -> getBasePtr ( ) ; if ( BasePtr . getOpcode ( ) == <STR_LIT> ) if ( const auto * GA = dyn_cast < GlobalAddressSDNode > ( BasePtr . getOperand ( <NUM_LIT> ) ) ) return GA -> getTargetFlags ( ) != <STR_LIT> ; return true


<s> unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return false


<s> Type * Ty = GTI . getIndexedType ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( Idx ) ) { if ( CI -> isZero ( ) ) continue ; TotalOffs += DL . getTypeAllocSize ( Ty ) * cast < ConstantInt > ( CI ) -> getSExtValue ( ) ; continue ; } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , TotalOffs ) ; if ( ! N ) return false ; TotalOffs = <NUM_LIT> ; } uint64_t ElementSize = DL . getTypeAllocSize ( Ty ) ; unsigned IdxN = getRegForGEPIndex ( Idx ) ; if ( ! IdxN ) return false ; if ( ElementSize != <NUM_LIT> ) { unsigned C = fastEmit_i ( VT , VT , <STR_LIT> , ElementSize ) ; if ( ! C ) return false ; IdxN = emitMul_rr ( VT , IdxN , C ) ; if ( ! IdxN ) return false ; } N = fastEmit_rr ( VT , VT , <STR_LIT> , N , IdxN ) ; if ( ! N ) return false ; } } if (


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>EarlyReturnPass ( ) ,


<s> short getBracCount ( ) const { return BracCount


<s> void emitLocalEntry ( MCSymbol * S , const MCExpr * LocalOffset ) override { llvm_unreachable (


<s> SM . recordStackMap ( * MILabel , MI ) ; unsigned NumShadowBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SMShadowTracker . reset ( NumShadowBytes )


<s> return ( __m128 ) __builtin_ia32_loadaps


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,

TII . get ( Opc ) , ResultReg ) , AM ) ;


<s> SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; if ( VT == <STR_LIT> && InVT == <STR_LIT> ) return Op ; if ( VT == <STR_LIT> ) { unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Promoted = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , Promoted ) ; } std :: vector < SDValue > BuildVectorOps ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) { SDValue Sclr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,

In , DAG . getConstant ( i , <STR_LIT> ) ) ;


<s> bool isCR64 ( ) const { return isReg ( CR64Reg )


<s> MCE . setModuleInfo ( MMI ) ; II = TM . getInstrInfo ( ) ; TD = TM . getTargetData ( ) ; Is64BitMode = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; do { DEBUG ( dbgs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin (


<s> static bool aarch64_check_builtin_call ( location_t loc , vec < location_t > arg_loc , tree fndecl , tree orig_fndecl , unsigned int nargs , tree * args ) { unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS


<s> debug_rtx ( mem ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( scratch ) ; } gcc_assert ( regno >= <NUM_LIT> && regno < FIRST_PSEUDO_REGISTER ) ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; rclass = REGNO_REG_CLASS ( regno ) ; gcc_assert ( rclass == GENERAL_REGS || rclass == BASE_REGS ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PRE_MODIFY ) { gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) == XEXP


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = <STR_LIT> ( Val ) ; if ( Reg && Reg -> Writeable && Reg -> haveFeatures ( STI .

getFeatureBits ( ) ) ) O << Reg -> Name ;


<s> return __builtin_ia32_comisdeq ( ( __v2df ) __A ,


<s> rtx mem = XEXP ( set , opn ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( mem ) != MEM


<s> auto * Mask = dyn_cast < ConstantSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask ) return ; KnownBits Known ; DAG . computeKnownBits ( C . Op0 .


<s> BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF . front ( ) ) ; bool Changed = false ; for ( auto ML : MLI ) { if ( ! ML -> getParentLoop ( ) ) Changed |= ProcessLoop


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasVLX ( ) ) { if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; } if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 ,


<s> unsigned HOST_WIDE_INT const2 = <NUM_LIT> ; if ( ! CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) ) return false ; const1 = UINTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( op1 , <NUM_LIT> ) ) || ~ UINTVAL ( XEXP ( op1 , <NUM_LIT> ) ) != const1 ) return false ; if ( GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ) { const2 = UINTVAL ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ; * sub0 = XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ; } else * sub0 = XEXP ( op0 , <NUM_LIT> ) ; if ( const2 >= GET_MODE_BITSIZE ( GET_MODE ( op0 ) ) ) return false ; * sub1 = XEXP ( op1 , <NUM_LIT> ) ; return exact_log2 ( const1 + ( HOST_WIDE_INT_1U <<


<s> if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; }


<s> Base = Addr ; Index = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> bool hasMSA ( ) const { return getSTI ( ) . getFeatureBits


<s> for ( thunk = DECL_THUNKS ( member ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) maybe_add_dllexport ( thunk ) ; } for ( member = CLASSTYPE_VTABLES ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; } else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t ) ) != NULL_TREE ) { for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllimport ( member ) ; else if ( TREE_CODE ( member ) == FUNCTION_DECL ) { tree thunk ; maybe_add_dllimport ( member ) ; for ( thunk = DECL_THUNKS ( member ) ; thunk ; thunk = DECL_CHAIN ( thunk ) ) maybe_add_dllimport ( thunk ) ; } for ( member = CLASSTYPE_VTABLES ( t ) ; member ; member = DECL_CHAIN ( member ) ) if (


<s> if ( auto ConstBytes = dyn_cast < ConstantSDNode > ( PackStride ) ) return getConstant ( <NUM_LIT> * ConstBytes -> getSExtValue ( ) , <STR_LIT> ) ; return getNode ( <STR_LIT> , <STR_LIT> , { PackStride , getConstant ( <NUM_LIT>


<s> uint32_t Binary ; unsigned Size = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS


<s> SDValue <ISA_LIT>TargetLowering :: LowerVectorINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; unsigned Opc = Op . getOpcode ( ) ; bool IsSigned = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( VT . isScalableVector ( ) ) { if ( InVT . getVectorElementType ( ) == <STR_LIT> ) { unsigned CastOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; EVT CastVT = getPromotedVTForPredicate ( InVT ) ; In = DAG . getNode ( CastOpc , dl , CastVT , In ) ; return DAG . getNode ( Opc , dl , VT , In ) ; } unsigned Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opcode ) ; } uint64_t VTSize = VT . getFixedSizeInBits ( ) ; uint64_t InVTSize = InVT . getFixedSizeInBits ( ) ; if ( VTSize <


<s> InstructionSelect ( ) { DEBUG ( BB -> dump ( )


<s> SDLoc DL ( Op ) ; auto SrcOp = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; EVT ContainerDstVT = getContainerForFixedLengthVector (


<s> return ( vector unsigned short ) __builtin_altivec_vadduhm ( ( vector signed short


<s> for ( unsigned I = <NUM_LIT> ; I < BytesPerElement ; ++ I ) { if ( Bytes [ Start + I ] >= <NUM_LIT> ) { unsigned Elem = Bytes [ Start + I ] ; if ( Base < <NUM_LIT> ) { Base = Elem - I ; if ( unsigned ( Base ) % Bytes . size ( ) + BytesPerElement > Bytes . size ( ) ) return false ; } else if ( unsigned ( Base ) != Elem


<s> Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL .


<s> vld3q_u32 ( const uint32_t * __a ) { uint32x4x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x4_t ) __builtin_aarch64_get_qregciv4si (


<s> return ( __m128i ) __builtin_ia32_movntdqa ( (


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> MemIntrinsicSDNode * MIN = dyn_cast < MemIntrinsicSDNode > ( N ) ; SDValue AddrOp ; if ( LDN || ( MIN && MIN -> getOpcode ( ) == <STR_LIT> ) ) AddrOp = N -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOpcode ( ) == <STR_LIT> ? AddrOp . getOperand ( <NUM_LIT> ) : AddrOp ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlign ( FI -> getIndex ( ) ) . value ( ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ; if ( AddrOp . getOpcode ( ) != <STR_LIT>


<s> unsigned <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( <STR_LIT> ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags

FMF , unsigned ScalarizationCostPassed ) {


<s> const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier


<s> FunctionPass * llvm :: create<ISA_LIT>PreTileConfigPass ( ) { return new <ISA_LIT>PreTileConfig (


<s> if ( needsStackRealignment ( MF ) && MFI ->


<s> DecodeStatus result = decodeInstruction ( DecoderTable64 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } } Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint64_t Inst = ReadFunc ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address ,


<s> std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - <NUM_LIT> ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } } else


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup >

& Fixups , const MCSubtargetInfo & STI ) const {


<s> assert ( And . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { KnownBits Known = DAG . computeKnownBits ( Op0 ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , dl ,


<s> MO_TLSDESC . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; MCInstLowering . lowerOperand ( MO_Sym , Sym ) ; MCInstLowering . lowerOperand ( MO_TLSDESC_LO12 , SymTLSDescLo12 ) ; MCInstLowering . lowerOperand ( MO_TLSDESC , SymTLSDesc ) ; MCInst Adrp ; Adrp . setOpcode ( <STR_LIT> ) ; Adrp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Adrp . addOperand ( SymTLSDesc ) ; EmitToStreamer ( OutStreamer , Adrp ) ; MCInst Ldr ; Ldr . setOpcode ( <STR_LIT> ) ; Ldr . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Ldr . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Ldr . addOperand ( SymTLSDescLo12 ) ; Ldr . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , Ldr ) ; MCInst Add ; Add . setOpcode ( <STR_LIT> ) ; Add . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Add . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Add . addOperand ( SymTLSDescLo12 ) ; Add . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <NUM_LIT> ) ) ) ; EmitToStreamer ( OutStreamer , Add ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( <STR_LIT> ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( OutStreamer , TLSDescCall ) ; MCInst Blr ; Blr . setOpcode ( <STR_LIT> ) ; Blr . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , Blr ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI ) ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer ,


<s> void <ISA_LIT>ConditionalCompares :: invalidateTraces ( ) { Traces -> invalidate ( CmpConv .


<s> if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , <STR_LIT> , XINT ( XVECEXP ( PATTERN ( insn ) ,

<NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , FALSE ) ;


<s> case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndex1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc , <STR_LIT> ) ; case Match_MRS : return Error ( Loc , <STR_LIT> ) ; case Match_MSR : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidComplexRotationEven : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidComplexRotationOdd : return Error ( Loc , <STR_LIT> ) ; case Match_MnemonicFail : { std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , ComputeAvailableFeatures ( STI -> getFeatureBits ( ) ) ) ; return Error ( Loc , <STR_LIT> + Suggestion ) ; } case Match_InvalidSVEPredicateAnyReg : case Match_InvalidSVEPredicateBReg : case Match_InvalidSVEPredicateHReg : case Match_InvalidSVEPredicateSReg : case Match_InvalidSVEPredicateDReg


<s> EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / vectorWidth ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result ,


<s> if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 ,


<s> const <ISA_LIT>RegisterInfo & TRI = * ST . getRegisterInfo ( ) ; const RegisterBankInfo & RBI = * ST . getRegBankInfo ( ) ; MIRBuilder . setInstr ( MI ) ; switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( createMemLibcall ( MIRBuilder , MRI , MI ) == LegalizerHelper :: UnableToLegalize ) return false ; MI . eraseFromParent ( ) ; return true ; case <STR_LIT> : { MachineInstr * Trap = MIRBuilder . buildInstr ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Trap , TII , TRI , RBI ) ; } default : break ; } return


<s> if ( offset == <NUM_LIT> ) return <NUM_LIT> ; if ( offset > <NUM_LIT> && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_SH2A && offset > <NUM_LIT> && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) && ! TARGET_SHMEDIA ) return <NUM_LIT> ; return


<s> if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit (


<s> return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base , Disp


<s> if ( SrcReg != <STR_LIT> ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( MI .

getOperand ( <NUM_LIT> ) . getImm ( ) ) ) , FrameIndex ) ;


<s> NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr


<s> if ( ! to_reg ) return tp ; reg = gen_reg_rtx ( Pmode ) ; insn = gen_rtx_SET ( VOIDmode , reg , tp ) ; insn = emit_insn ( insn ) ; return reg


<s> SDValue <ISA_LIT>TargetLowering :: getSqrtInputTest ( SDValue Op , SelectionDAG & DAG , const DenormalMode & Mode ) const { EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( <STR_LIT> ) || ( VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! Subtarget

. hasVSX ( ) ) ) ) return TargetLowering :: getSqrtInputTest ( Op , DAG , Mode ) ;


<s> skipNonTerminators ( Position , * BI ) ; for ( unsigned BTI = <NUM_LIT> , BTE = BI -> NumTerminators ; BTI != BTE ; ++ BTI ) { skipTerminator ( Position , * TI , true ) ; ++


<s> if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int SplitFactor = std :: max ( IdxsLT . first , SrcLT . first ) ; if ( SplitFactor >


<s> if ( TheTriple . isOSDarwin ( ) ) { if ( TheTriple . getArchName ( ) == <STR_LIT> || TheTriple . getArchName ( ) == <STR_LIT> ) return new Darwin<ISA_LIT>AsmBackend ( T , TT , object :: mach :: CS<ISA_LIT>_V4T ) ; else if ( TheTriple . getArchName ( ) == <STR_LIT> || TheTriple . getArchName ( ) == <STR_LIT> ) return new Darwin<ISA_LIT>AsmBackend ( T , TT , object :: mach :: CS<ISA_LIT>_V5TEJ ) ; else if ( TheTriple . getArchName ( ) == <STR_LIT> || TheTriple . getArchName ( ) == <STR_LIT> ) return new Darwin<ISA_LIT>AsmBackend ( T , TT , object :: mach :: CS<ISA_LIT>_V6 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , object :: mach ::


<s> unsigned int align ; unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && DECL_P ( decl ) && VAR_P ( decl ) && bss_initializer_p ( decl ) ) flags |= SECTION_BSS ; if ( ! decl || ! DECL_P ( decl ) ) align = MIN_UNITS_PER_WORD ; else if ( ( flags & SECTION_CODE ) != <NUM_LIT> ) align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , <NUM_LIT> ) ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes ( TREE_TYPE (

decl ) ) > MIN_UNITS_PER_WORD ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , MODE_64BIT , T . createMCInstrInfo (


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) )


<s> if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer (


<s> if ( ! require_immediate ( argno , actual ) ) return false ; if ( ! IN_RANGE ( actual , min , max ) ) { report_out_of_range ( location , fndecl , argno ,


<s> bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG .


<s> static SDValue BuildVSLDOI ( SDValue LHS , SDValue RHS , unsigned Amt , EVT VT , SelectionDAG & DAG , DebugLoc dl ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> SDValue Ptr = SD -> getBasePtr ( ) , Value = SD -> getValue ( ) ; EVT MemVT = SD -> getMemoryVT ( ) , BasePtrVT = Ptr . getValueType ( ) ; DebugLoc DL = SD -> getDebugLoc ( ) ; SDVTList VTList = DAG .


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ! call_used_regs [ reg ]


<s> while ( N . getOpcode ( ) == <STR_LIT> ) N = N


<s> if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveFReg ( Reg ,


<s> void <ISA_LIT>InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printVectorList ( MI , OpNum , O


<s> __o = __builtin_aarch64_ld2v8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o ,


<s> unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < NumOperands ; ++ i ) { int Val = SVOp -> getMaskElt ( NumOperands - i - <NUM_LIT> ) ; if ( Val < <NUM_LIT> ) Val = <NUM_LIT> ; if ( Val >= NumOperands ) Val -= NumOperands ; Mask |= Val


<s> if ( Opcode == <STR_LIT> ) OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return


<s> std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = F . getFnAttribute ( <STR_LIT> ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return lowerFABS64 ( Op

, DAG , Subtarget -> has<ISA_LIT>32r2 ( ) ) ;


<s> static DecodeStatus DecodeBitfieldMaskOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned msb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned lsb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( lsb > msb ) { Check ( S , MCDisassembler :: SoftFail ) ; lsb = msb ; } uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT>


<s> MVT SExtVT ; MVT FPCastVT = <STR_LIT> ; switch ( VecVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasAVX ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasAVX ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT>


<s> unsigned CPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned CPURegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) /


<s> nds32_compute_stack_frame ( ) ; if ( frame_pointer_needed ) cfun -> machine -> fp_as_gp_p = false ; if ( cfun -> machine -> va_args_size != <NUM_LIT> ) { Rb = cfun -> machine -> va_args_first_regno ; Re = cfun -> machine -> va_args_last_regno ; nds32_emit_stack_push_multiple ( Rb , Re , false , false , false , true ) ; if ( cfun -> machine -> va_args_area_padding_bytes ) { sp_adjust = cfun -> machine -> va_args_area_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } if ( cfun -> machine -> naked_p && ! flag_pic ) return ; Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; if ( ! ( Rb == SP_REGNUM && Re == SP_REGNUM && cfun -> machine -> fp_size == <NUM_LIT> && cfun -> machine -> gp_size == <NUM_LIT> && cfun -> machine -> lp_size == <NUM_LIT> ) ) { nds32_emit_stack_push_multiple ( Rb , Re , cfun -> machine -> fp_size , cfun -> machine -> gp_size , cfun -> machine -> lp_size , false ) ; } if ( cfun -> machine -> use_eh_return_p ) { Rb = cfun -> machine -> eh_return_data_first_regno ; Re = cfun -> machine -> eh_return_data_last_regno ; nds32_emit_stack_push_multiple ( Rb , Re , false , false , false , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_offset = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! satisfies_constraint_Is14 ( GEN_INT ( fpr_offset ) ) ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - <NUM_LIT> * fpr_space ) ; nds32_emit_push_fpr_callee_saved ( <NUM_LIT>


<s> Selects . push_back ( & * NextMIIt ) ; continue ; } break ; } bool User = false ; for ( auto SelMI : Selects ) if ( NextMIIt -> readsVirtualRegister ( SelMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { User = true ; break ; } if ( NextMIIt -> isDebugInstr ( ) ) { if ( User ) { assert ( NextMIIt -> isDebugValue ( ) && <STR_LIT> ) ; DbgValues . push_back ( & * NextMIIt ) ; } } else if ( User || ++ Count > <NUM_LIT> ) break ; } MachineInstr * LastMI = Selects . back ( ) ; bool CCKilled = ( LastMI -> killsRegister ( <STR_LIT> ) || checkCCKill ( * LastMI , MBB ) ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockAfter ( LastMI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; if ( ! CCKilled ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; createPHIsForSelects ( Selects , StartMBB , FalseMBB , MBB ) ; for ( auto SelMI : Selects ) SelMI -> eraseFromParent ( ) ; MachineBasicBlock :: iterator InsertPos = MBB -> getFirstNonPHI ( ) ; for ( auto DbgMI : DbgValues ) MBB -> splice ( InsertPos , StartMBB , DbgMI


<s> if ( LastOpc == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( LastInst -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( LastOpc != <STR_LIT> ) { int LastNumOp = LastInst -> getNumOperands ( ) ; TBB = LastInst -> getOperand ( LastNumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; for ( int i = <NUM_LIT> ; i < LastNumOp - <NUM_LIT> ; i ++ ) { Cond . push_back ( LastInst -> getOperand ( i ) ) ; } return false ; } } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; <STR_LIT> BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != <STR_LIT> && LastOpc == <STR_LIT> ) { int SecondNumOp = SecondLastInst -> getNumOperands ( ) ; TBB = SecondLastInst -> getOperand ( SecondNumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; for ( int i = <NUM_LIT> ; i < SecondNumOp - <NUM_LIT> ; i ++ ) { Cond . push_back ( SecondLastInst -> getOperand ( i ) ) ; } FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( ( SecondLastOpc == <STR_LIT> ) && ( LastOpc == <STR_LIT>


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT>


<s> Mask = ExtendToType ( Mask , ExtMaskVT , DAG , true ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskBitVT , Mask ) ; MVT NewVT = <STR_LIT> ( VT . getScalarType ( ) , NumElts ) ; Src0 = ExtendToType ( Src0 , NewVT , DAG ) ; SDValue Ops [ ] = { N -> getChain ( ) , Src0 , Mask , N -> getBasePtr ( ) , Index } ; SDValue NewGather = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( DAG . getVTList ( NewVT , MaskBitVT , <STR_LIT> ) , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , VT , NewGather . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Extract , NewGather . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ; } SDValue Ops [ ] = { N -> getChain ( ) , Src0 , Mask , N -> getBasePtr ( ) , Index } ; SDValue NewGather = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( DAG . getVTList ( VT , MaskVT , <STR_LIT> )


<s> F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return


<s> return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF ->

getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> } if ( F && F -> isPagerando ( ) ) return false ; } } if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return canGuaranteeTCO ( CalleeCC ) && CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( CCInfo . getNextStackOffset ( ) >

FuncInfo -> getBytesInStackArgArea ( ) ) return false ;


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegNum ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegLst == <NUM_LIT> ) return MCDisassembler :: Fail ; RegNum = RegLst & <NUM_LIT> ; if ( RegNum > <NUM_LIT> ) return


<s> case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! Check ( S , DecodeBFLabelOperand < false , true , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Address , Decoder ) ) || ! Check ( S , DecodeBFLabelOperand < false , false , <NUM_LIT> > ( Inst , Imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { uint32_t CanonicalLCTP = <NUM_LIT> , SBZMask = <NUM_LIT> ; if ( ( Insn & ~ SBZMask ) != CanonicalLCTP ) return MCDisassembler :: Fail ; if ( Insn != CanonicalLCTP ) Check ( S , MCDisassembler :: SoftFail ) ; Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> )


<s> return create<ISA_LIT>AsmBackend ( T , MRI , TT


<s> <ISA_LIT>AsmParser ( const Target & T , MCAsmParser & _Parser , TargetMachine & _TM ) : TargetAsmParser ( T ) , Parser ( _Parser ) , TM ( _TM ) { setAvailableFeatures ( ComputeAvailableFeatures ( & TM . getSubtarget < <ISA_LIT>Subtarget > (


<s> MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; switch ( static_cast < unsigned > ( Fixup . getKind ( ) ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; default : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32 ; } case FK_SecRel_4 : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH20T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH24T ; case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BLX23T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_MOV32T ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { int Val = N -> getMaskElt ( i ) ; if ( Val >= <NUM_LIT> ) Mask |= ( Val - <NUM_LIT> ) ; if ( i != <NUM_LIT> )


<s> int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; y =


<s> void DecodeVPERM2F128Mask ( unsigned Imm , SmallVectorImpl < unsigned > & ShuffleMask ) { return DecodeVPERM2F128Mask ( <STR_LIT> , Imm ,


<s> SDValue SelectFalse = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False


<s> SmallVector < Instruction * , <NUM_LIT> > DecomposedVectors ; SmallVector < Value * , <NUM_LIT> > TransposedVectors ; VectorType * ShuffleTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; if ( isa < LoadInst > ( Inst ) ) { decompose ( Inst , Factor , ShuffleTy , DecomposedVectors ) ; transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getVectorElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getVectorNumElements ( ) /


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( NumBytes == <NUM_LIT> )


<s> SDValue LD = isVectorBroadcast ( Op , Subtarget ) ; if ( LD . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , LD ) ; if ( ( Size == <NUM_LIT> && NumElem <= <NUM_LIT> ) || ( Size == <NUM_LIT> && NumElem < <NUM_LIT> ) ) return SDValue ( ) ; return PromoteSplat ( SVOp , DAG ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode


<s> return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskStart == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskEnd , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops )


<s> if ( <STR_LIT> ( Vec . getNode ( ) ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; if ( ShiftRight != <NUM_LIT> ) SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( ShiftRight , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( IdxVal + SubVecNumElems == NumElems ) { SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( SubVecNumElems * <NUM_LIT> == NumElems ) { Vec = DAG . getNode ( <STR_LIT> , dl , SubVecVT , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , Vec , ZeroIdx ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems - IdxVal , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; } Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , SubVec ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } NumElems = WideOpVT . getVectorNumElements ( ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec


<s> if ( ! MemOpcodes ) return false ; for ( unsigned Form = <NUM_LIT> ; Form < <NUM_LIT> ; Form ++ ) if ( Opcode == MemOpcodes [ Form ] ) return true ; return


<s> MIB . addImm ( <STR_LIT> ) ; MIB . addReg (


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st3v8qi ( ( __builtin_aarch64_simd_qi * ) __a ,


<s> UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , TmpReg , FrameReg , Offset , TII , * this , dl ) ; } MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . addOperand ( MachineOperand :: CreateReg ( FrameReg , false ) ) ; else MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; } else if ( Desc . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , VReg , FrameReg , Offset , false , TII , * this , dl ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , VReg , FrameReg , Offset , TII , * this , dl ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . addOperand ( MachineOperand :: CreateReg ( FrameReg , false ) ) ; else MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false


<s> int mmix_shiftable_wyde_value ( unsigned HOST_WIDEST_INT value ) { int i ; int has_candidate = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i


<s> const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> auto Info = find_if ( Insts , [ & ] ( InstInfo & Info ) {


<s> Value * PtrCast = IC . Builder . CreateBitCast ( Ptr , VecPtrTy , <STR_LIT> ) ; Constant * BoolMask = getNegativeIsTrueBoolVec ( ConstMask ) ; CallInst * NewMaskedLoad = IC . Builder . CreateMaskedLoad ( PtrCast , Align ( <NUM_LIT> ) , BoolMask , ZeroVec ) ; return IC . replaceInstUsesWith (


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT


<s> if ( dsize == <NUM_LIT> ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == <NUM_LIT> ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > <NUM_LIT> ) return false ; dalign /=


<s> for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( sethi ) ) ) return ; use_record = DF_INSN_USES ( use_insn ) ; if ( DF_REF_CHAIN ( use_record ) && DF_REF_CHAIN ( use_record ) -> next ) return ; if ( ! active_insn_p ( use_insn ) ) return ; if ( ! ( recog_memoized ( use_insn ) == CODE_FOR_lo_sum || nds32_symbol_load_store_p ( use_insn ) || ( nds32_reg_base_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) ) ) return ; } group_id = GEN_INT ( relax_group_id ) ; emit_insn_before ( gen_relax_group ( group_id ) , sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( active_insn_p ( use_insn ) ) emit_insn_before ( gen_relax_group (


<s> SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( ! RHS . getOperand ( <NUM_LIT> ) . isUndef ( ) ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( ! RHS . getOperand ( <NUM_LIT> ) . isUndef ( ) ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( ! RHS . isUndef ( ) ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) ShuffleVectorSDNode :: commuteMask ( RMask ) ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { int LIdx = LMask [ i + l ] , RIdx = RMask [ i + l ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) )

|| ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ;


<s> void <ISA_LIT>SEInstrInfo :: storeRegToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const

TargetRegisterInfo * TRI , int64_t Offset ) const {


<s> const DataLayout * getDataLayout ( ) const


<s> return ( uint16x8_t ) __builtin_aarch64_uminpv8hi ( ( int16x8_t ) a ,


<s> __inline__ static unsigned long long sh_media_MMUL_L ( unsigned long long mm , unsigned long


<s> unsigned <ISA_LIT>TTI :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) const { if ( VectorType * VTy = dyn_cast < VectorType > ( Src ) ) { unsigned NumElem = VTy -> getVectorNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { unsigned Cost = TargetTransformInfo :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ; unsigned SplitCost = getScalarizationOverhead ( Src , Opcode == Instruction :: Load , Opcode


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Op ) , GA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) { Result = DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , BA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) { Result = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) ) ; } else return ; break ; } case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return ; uint64_t CVal = C -> getZExtValue ( ) ; switch ( ConstraintLetter ) { case 'I' : if ( isUInt < <NUM_LIT> > ( CVal ) || isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( CVal ) ) break ; return ; case 'J' : { uint64_t NVal = - C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( NVal ) || isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( NVal ) ) { CVal = C -> getSExtValue ( ) ; break ; } return ; } case 'K' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'L' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'M' : { if ( ! isUInt < <NUM_LIT> > ( CVal ) ) return ; if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ ( uint32_t ) CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; return ; } case 'N'


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( )


<s> return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = false


<s> if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y -> getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; SDValue SBB = materializeSBB ( Y . getNode ( ) , NewEFLAGS , DAG ) ; if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; if ( auto * ConstantX = dyn_cast < ConstantSDNode > ( X ) ) { if ( ( IsSub && CC == <STR_LIT> && ConstantX -> isNullValue ( ) ) || ( ! IsSub && CC == <STR_LIT> && ConstantX -> isAllOnesValue


<s> tmp1 = simplify_gen_subreg ( HImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; tmp2 = simplify_gen_subreg ( QImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; emit_insn ( gen_udivmodhiqi3 ( tmp0 , tmp1 , tmp2 ) ) ; if ( signed_p ) { div = gen_rtx_DIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_MOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { div = gen_rtx_UDIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_UMOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } tmp1 = gen_rtx_ZERO_EXTRACT ( mode , tmp0 , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; if ( REG_P ( operands [ <NUM_LIT> ] ) ) insn = emit_move_insn ( operands [ <NUM_LIT> ] , tmp1 ) ; else { scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , tmp1


<s> Op , DAG . getConstant ( NumBits , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> Register OrigZeroReg = MI . getOperand ( PosForOrigZero ) . getReg ( ) ; Register NewZeroReg = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( ( NewZeroReg == <STR_LIT> || NewZeroReg == <STR_LIT> ) && ConstantOpNo != III . ZeroIsSpecialNew ) return false ; if ( ( OrigZeroReg == <STR_LIT> || OrigZeroReg == <STR_LIT> ) && ConstantOpNo != PosForOrigZero ) return false ; } unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( PostRA && MI . getOperand ( ConstantOpNo ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( ConstantOpNo ) . getReg ( ) ; unsigned Opc = MI . getOpcode ( ) ; bool SpecialShift32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool SpecialShift64 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool SetCR = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool RightShift = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get (


<s> if ( known_ge ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return mode ; else return


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMUL_LOHI ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>CTRLoops ( ) : FunctionPass ( ID ) , TM ( <NUM_LIT> ) { initialize<ISA_LIT>CTRLoopsPass ( * PassRegistry :: getPassRegistry


<s> return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_GPRel_4 : if ( isN64 ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF ::


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; if ( SDValue Flags = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) { SDValue Cond = DAG . getConstant ( CC , DL


<s> vld1_u32 ( const uint32_t * a ) { return ( uint32x2_t ) __builtin_aarch64_ld1v2si ( (

const __builtin_aarch64_simd_si * ) a ) ;


<s> case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; } O << '%' << TRI -> getAsmName ( Reg ) ; return false


<s> else base = high ? high_base : low_base ; for ( i = <NUM_LIT> ; i < nunits / <NUM_LIT> ; i ++ ) RTVEC_ELT ( v


<s> unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes >


<s> if ( InstTy == InstType :: Ambiguous && OpSize == <NUM_LIT> ) return true ; return


<s> if ( ( SignedDivRem || UnsignedDivRem ) && Args . size ( ) == <NUM_LIT> ) { if ( const Constant * C = dyn_cast < Constant > ( Args [ <NUM_LIT> ] ) ) { const ConstantInt * CVal = ( C -> getType ( ) -> isVectorTy ( ) ? dyn_cast_or_null < const ConstantInt > ( C -> getSplatValue ( ) ) : dyn_cast < const ConstantInt > ( C ) ) ; if ( CVal != nullptr && ( CVal -> getValue ( ) . isPowerOf2 ( ) || ( - CVal -> getValue ( ) ) . isPowerOf2 ( ) ) ) DivRemConstPow2 = true ; else DivRemConst = true ; } } if ( Ty -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned VF = Ty -> getVectorNumElements ( ) ; unsigned NumVectors = getNumVectorRegs ( Ty ) ; if ( Opcode == Instruction :: Shl || Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) { return NumVectors ; } if ( DivRemConstPow2 ) return ( NumVectors * ( SignedDivRem ? SDivPow2Cost : <NUM_LIT> ) ) ; if ( DivRemConst ) return VF * DivMulSeqCost + getScalarizationOverhead ( Ty , Args ) ; if ( ( SignedDivRem || UnsignedDivRem ) && VF > <NUM_LIT> ) return <NUM_LIT> ; if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) { switch ( ScalarBits ) { case <NUM_LIT> : { if ( ST -> hasVectorEnhancements1 ( ) ) return NumVectors ; unsigned ScalarCost = getArithmeticInstrCost ( Opcode , Ty -> getScalarType ( ) ) ; unsigned Cost = ( VF * ScalarCost ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } case <NUM_LIT> : case <NUM_LIT> : return NumVectors ; default : break ; } } if ( Opcode == Instruction :: FRem


<s> return StringSwitch < <ISA_LIT>ABIInfo > ( CPU ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT>

, <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Default ( <ISA_LIT>ABIInfo :: Unknown ( ) ) ;


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return RegInfo -> getRegClass ( RC ) . getRegister


<s> if ( ! is_sse && ( fpcmp_mode == CCFPUmode || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || standard_80387_constant_p ( op1 ) == <NUM_LIT> ) && GET_CODE ( op1 ) != FLOAT ) || ix86_fp_comparison_strategy ( code ) == IX86_FPCMP_COMI ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == <NUM_LIT> || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == <NUM_LIT> ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp ==


<s> AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > (


<s> return ( __mmask32 ) __builtin_ia32_cmpb256_mask ( ( __v32qi ) __X , ( __v32qi )


<s> CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; }


<s> const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; unsigned SABIAlignment = TD . getABITypeAlignment ( S -> getValueOperand ( ) -> getType ( ) ) ; if ( S -> getAlignment ( ) != <NUM_LIT> && S -> getAlignment ( ) < SABIAlignment ) return false ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM


<s> return __builtin_mve_vcvtq_m_from_f_uv4si ( __arm_vuninitializedq_u32 ( ) ,


<s> if ( Tok . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Val = Parser . getTok ( ) . getIntVal ( ) ; if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser

. getTok ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( LHSC && ! RHSC ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getVTList ( ) , RHS , LHS , CarryIn ) ; if ( LHSC && RHSC && LHSC -> isZero ( ) && RHSC -> isZero ( ) && SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue CarryOut = DAG . getConstant ( <NUM_LIT> , DL , N -> getValueType ( <NUM_LIT> ) ) ; SDValue Res1 = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , CarryIn ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DCI . CombineTo ( N , Res1 , CarryOut ) ; } if ( LHSC && RHSC && ! LHSC -> isZero ( ) && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDLoc DL (


<s> if ( ! sparc_got_symbol ) sparc_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; return


<s> unsigned ExpectedElt = Imm ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { ExpectedElt += <NUM_LIT> ; if ( ExpectedElt == NumElts * <NUM_LIT> ) { ExpectedElt = <NUM_LIT> ; ReverseVEXT = true ; } if ( M [ i ] < <NUM_LIT> ) continue ; if ( ExpectedElt != static_cast < unsigned > ( M [ i ] ) ) return false ; } if ( ReverseVEXT ) Imm


<s> if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) )


<s> static bool isCDisp8 ( uint64_t TSFlags , int Value , int & CValue ) { assert ( ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned CD8_Scale = ( TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( CD8_Scale == <NUM_LIT> ) { CValue = Value


<s> raw_svector_ostream OS ( Str ) ; printInstruction ( MI ,


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) +


<s> regbase = GP_ARG_FIRST ; break ; case E_DFmode : cum -> arg_words += cum -> arg_words & <NUM_LIT> ; regbase = GP_ARG_FIRST ; break ; default : gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) ; case E_BLKmode : if ( type != NULL_TREE && TYPE_ALIGN ( type ) > ( unsigned ) BITS_PER_WORD ) cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; case E_VOIDmode : case E_QImode : case E_HImode : case E_SImode : regbase = GP_ARG_FIRST ; break ; case E_DImode : cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; case E_TImode : cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; } if ( * arg_words >= ( unsigned ) MAX_ARGS_IN_REGISTERS ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> , struct_p ? <STR_LIT> : <STR_LIT> ) ; ret = <NUM_LIT> ; } else { gcc_assert ( regbase != - <NUM_LIT> ) ; if ( ! type || TREE_CODE ( type ) != RECORD_TYPE || ! arg . named || ! TYPE_SIZE_UNIT ( type ) || ! tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( type ) ) ) ret = gen_rtx_REG ( mode , regbase + * arg_words + bias ) ; else { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL && TREE_CODE ( TREE_TYPE ( field ) ) == REAL_TYPE && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD && tree_fits_shwi_p ( bit_position ( field ) ) && int_bit_position ( field ) % BITS_PER_WORD == <NUM_LIT> ) break ; if ( ! field || mode == DFmode ) ret = gen_rtx_REG ( mode , regbase + * arg_words + bias ) ; else { unsigned int chunks ; HOST_WIDE_INT


<s> unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { assert ( ! I -> isBundle


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> NameDecorationStyle getDecorationStyle ( )


<s> if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT>


<s> const char * \ current_section_name ( ) \ { \ switch ( in_section ) \ { \ case no_section : return NULL ; \ case in_text : return <STR_LIT> ; \ case in_data : return <STR_LIT> ; \ case in_sdata : return <STR_LIT> ; \ case in_bss : return <STR_LIT> ;

\ case in_rdata : \ case in_const : \ if ( mips_abi != ABI_32 && mips_abi != ABI_O64 ) \ return <STR_LIT> ; \ else \ return <STR_LIT> ; \ case in_named : \ return in_named_name ; \ } \ abort ( ) ; \ }


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; res = VirtualAlloc ( NULL , size , MEM_RESERVE