<s> if ( size <= PROBE_INTERVAL ) { const HOST_WIDE_INT base = ROUND_UP ( size , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + base ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , base - size ) ) ; } else if ( size <= <NUM_LIT> * PROBE_INTERVAL ) { HOST_WIDE_INT i , rem ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + PROBE_INTERVAL ) ) ) ; emit_stack_probe ( reg1 ) ; for ( i = <NUM_LIT> * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - PROBE_INTERVAL ) ) ; emit_stack_probe ( reg1 ) ; } rem = size - ( i - PROBE_INTERVAL ) ; if ( rem > <NUM_LIT> ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - base ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , reg1 , - rem ) ) ; } else { rtx reg2 = gen_rtx_REG ( Pmode , PROBE_STACK_SECOND_REG ) ; HOST_WIDE_INT rounded_size = size & - PROBE_INTERVAL ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ; HOST_WIDE_INT adjustment = - ( first + rounded_size ) ; if ( ! aarch64_uimm12_shift ( adjustment ) ) { aarch64_internal_mov_immediate ( reg2 , GEN_INT ( adjustment ) , true , Pmode ) ; emit_set_insn ( reg2 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , reg2 ) ) ; } else emit_set_insn ( reg2 , plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ) ; emit_insn ( gen_probe_stack_range ( reg1 , reg1 , reg2 ) ) ; if ( size != rounded_size ) { HOST_WIDE_INT rem = size - rounded_size ; if ( rem > <NUM_LIT> ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg2 , plus_constant ( Pmode ,


<s> static DecodeStatus decodeRegisterClass ( MCInst & Inst , uint64_t RegNo , const unsigned * Regs ) { assert ( RegNo < <NUM_LIT>


<s> return new <ISA_LIT>TLSDynamicCall (


<s> if ( checkOpcode ( I2P . getOperand ( <NUM_LIT> ) , Instruction :: PtrToInt ) ) { User * P2I = cast < User > ( I2P . getOperand ( <NUM_LIT> ) ) ; PointerType * SrcTy = dyn_cast < PointerType > ( P2I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcTy && SrcTy -> getAddressSpace ( ) == <NUM_LIT> ) { Value * Src = P2I -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( Src ) ) return GV -> hasExternalLinkage ( ) ? <NUM_LIT> : P2I ; if ( isa < AllocaInst > ( Src ) || isa < CallBase > ( Src ) ) { return P2I ; } } } } return


<s> SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> if ( resolveBuildVector ( BVN , DefBits , UndefBits ) ) { SDValue NewOp ; DefBits = ~ DefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) ) return NewOp ; UndefBits = ~ UndefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) ) return NewOp ; } return SDValue


<s> SDValue TRUNCATE ( SDValue A , MVT VT ) { return DAG -> getNode ( <STR_LIT> , dl , VT ,


<s> O << <STR_LIT> ; printOperand ( MI , Op


<s> if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true ; } else if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; } else if ( isOpcWithIntImmediate ( Op0 , <STR_LIT> , Srl_imm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( ! BiggerPattern && ( Srl_imm <= <NUM_LIT> || Srl_imm >= VT . getSizeInBits ( ) ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ; return false


<s> EVT CarryVT = Carry . getValueType ( ) ; SDLoc DL ( Op ) ; APInt NegOne = APInt :: getAllOnesValue ( CarryVT . getScalarSizeInBits ( ) ) ; SDValue Result ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; Result = DAG . getNode ( <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ; Carry = ConvertCarryFlagToBooleanCarry ( Result . getValue ( <NUM_LIT> ) , VT , DAG ) ; } else { Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Carry ) ; Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; Result = DAG . getNode ( <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ; Carry = ConvertCarryFlagToBooleanCarry ( Result . getValue ( <NUM_LIT> )


<s> clonei -> vecsize_float = <NUM_LIT> ; break ; case 'd' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'e' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; if ( TYPE_MODE ( base_type ) == QImode ) clonei -> mask_mode = DImode ; else clonei -> mask_mode = SImode ; break ; } if ( clonei -> simdlen == <NUM_LIT> ) { if ( SCALAR_INT_MODE_P ( TYPE_MODE ( base_type ) ) ) clonei -> simdlen = clonei -> vecsize_int ; else clonei -> simdlen = clonei -> vecsize_float ; clonei -> simdlen = clonei -> simdlen / GET_MODE_BITSIZE ( TYPE_MODE ( base_type ) ) ; } else if ( clonei -> simdlen > <NUM_LIT> ) { tree ctype = ret_type ; if ( TREE_CODE ( ret_type ) == VOID_TYPE ) ctype = base_type ; int cnt = GET_MODE_BITSIZE ( TYPE_MODE ( ctype ) ) * clonei -> simdlen ; if ( SCALAR_INT_MODE_P ( TYPE_MODE ( ctype ) ) ) cnt /= clonei -> vecsize_int ; else cnt /= clonei -> vecsize_float ; if ( cnt > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) { if ( explicit_p ) warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , clonei


<s> bool <ISA_LIT>InstructionSelector :: selectUnmergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) && <STR_LIT> ) ; unsigned NumDefs = I . getNumOperands ( ) - <NUM_LIT> ; Register SrcReg = I . getOperand ( NumDefs ) . getReg ( ) ; unsigned DefSize = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumDefs ; ++ Idx ) { MachineInstr & ExtrInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_EXTRACT ) , I . getOperand ( Idx ) . getReg ( ) ) . addReg ( SrcReg ) . addImm ( Idx * DefSize ) ; if ( ! select ( ExtrInst ) ) return false ; } I . eraseFromParent ( )


<s> if ( collectCmovCandidates ( Blocks , AllCmovGroups , true ) ) { for ( auto & Group : AllCmovGroups ) { if ( llvm :: none_of ( Group , [ & ] ( MachineInstr * I ) { return I -> mayLoad ( ) ; } ) ) continue ; Changed = true ; convertCmovInstsToBranches ( Group ) ; } } } SmallVector < MachineLoop * , <NUM_LIT> > Loops ( MLI -> begin ( ) , MLI -> end ( ) ) ; for ( int i = <NUM_LIT> ; i < ( int ) Loops . size ( ) ; ++ i ) for ( MachineLoop * Child : Loops [ i ] -> getSubLoops ( ) ) Loops . push_back ( Child ) ; for ( MachineLoop * CurrLoop : Loops ) { if ( ! CurrLoop -> getSubLoops ( ) . empty ( )


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lanai > X (

getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> Skipped = true ; } if ( ImplicitRd ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |=


<s> if ( ! reload_completed || frame_pointer_needed || cfun -> machine -> func_type != TYPE_NORMAL ) return <NUM_LIT> ; if ( crtl -> args . pops_args && crtl -> args . size


<s> } APInt UsersUsefulBits ( UsefulBits . getBitWidth ( ) , <NUM_LIT> ) ; for ( SDNode * Node : Op . getNode ( ) -> uses ( ) ) { APInt UsefulBitsForUse = APInt ( UsefulBits ) ; getUsefulBitsForUse ( Node , UsefulBitsForUse , Op , Depth ) ; UsersUsefulBits |= UsefulBitsForUse ; } UsefulBits &=


<s> if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , ELFRefKind , DarwinRefKind , Addend ) ) { return false ; } if ( DarwinRefKind != MCSymbolRefExpr :: VK_None ) return false ; return llvm :: is_contained ( AllowedModifiers


<s> bool PostRA = ! MRI . isSSA ( ) ; if ( ( ConstantOpNo != III . OpNoForForwarding ) && ! III . IsCommutative ) return false ; if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; if ( III . SignedImm ) { APInt ActualValue ( <NUM_LIT> , Imm , true ) ; if ( ! ActualValue . isSignedIntN ( III . ImmWidth ) ) return false ; } else { uint64_t UnsignedMax = ( <NUM_LIT> << III . ImmWidth ) - <NUM_LIT> ; if ( ( uint64_t ) Imm > UnsignedMax ) return false ; } if ( PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { unsigned PosForOrigZero = III . ZeroIsSpecialOrig ? III . ZeroIsSpecialOrig : III . ZeroIsSpecialNew + <NUM_LIT> ; Register OrigZeroReg = MI . getOperand ( PosForOrigZero ) . getReg ( ) ; Register NewZeroReg = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( ( NewZeroReg == <STR_LIT> || NewZeroReg == <STR_LIT> ) && ConstantOpNo != III . ZeroIsSpecialNew ) return false ; if ( ( OrigZeroReg == <STR_LIT> || OrigZeroReg == <STR_LIT> ) && ConstantOpNo != PosForOrigZero ) return false ; } unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( PostRA && MI . getOperand ( ConstantOpNo ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( ConstantOpNo ) . getReg ( ) ; unsigned Opc = MI . getOpcode ( ) ; bool SpecialShift32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==


<s> SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , Alignment ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , Alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ; SDValue OutChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; SDValue Ops [ <NUM_LIT> ] = { SDValue ( InFP128 , <NUM_LIT> ) , OutChain } ; return DAG . getMergeValues ( Ops


<s> return __builtin_mve_vcvtq_m_n_from_f_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __imm6 ,


<s> void <ISA_LIT>AsmParser :: createAddu ( unsigned DstReg , unsigned SrcReg , unsigned TrgReg , bool Is64Bit , SmallVectorImpl < MCInst > & Instructions ) { emitRRR ( Is64Bit ? <STR_LIT> : <STR_LIT> , DstReg , SrcReg , TrgReg , SMLoc ( ) ,


<s> if ( ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) || ( MO . isReg

( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) ) {


<s> return arm_gen_constant ( code , SImode , NULL_RTX , INTVAL ( val ) , NULL_RTX , NULL_RTX


<s> static bool selectMergeValues ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2Base ( ) && <STR_LIT> ) ; Register VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI


<s> break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_SBREL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr :: VK_TLSLDM : Type = ELF :: R_<ISA_LIT>_TLS_LDM32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ : Type = ELF :: R_<ISA_LIT>_TLS_DESCSEQ ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF


<s> const SDValue & getBasePtr ( ) const { return getOperand ( <NUM_LIT>


<s> void <ISA_LIT>RegisterInfo :: getInitialFrameState ( std :: vector < MachineMove > & Moves ) const { MachineLocation Dst ( MachineLocation ::


<s> void addPowerTwoOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; } } if ( ! DoMerge ) return false ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; ( * MIB ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end (


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> TempInst . setLoc ( IDLoc ) ; TmpRegNum = ( isLoad && ( BaseRegNum != RegOpNum ) ) ? RegOpNum : AtRegNum ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( HiOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { SR = static_cast < const MCSymbolRefExpr * > ( ExprOffset ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } else { const MCExpr * HiExpr = evaluateRelocExpr ( ExprOffset , <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } } Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( BaseRegNum ) ) ; Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; TempInst . setOpcode ( Inst . getOpcode ( ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( RegOpNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( LoOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( LoExpr ) ) ; }


<s> assert ( BBOffsets . size ( ) == BBSizes . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = BBOffsets . size ( ) ; i != e ; ++ i ) assert ( BBOffsets [ i - <NUM_LIT> ] + BBSizes [ i - <NUM_LIT> ] == BBOffsets [ i ] ) ; if ( isThumb ) { for ( MachineFunction :: iterator MBBI = Fn . begin ( ) , E = Fn . end ( ) ; MBBI != E ; ++


<s> EltVT = <STR_LIT> ; VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue BuildVec = DAG . getConstant ( EltMask , VecVT ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; } SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VecVT , VecVal1 , VecVal2 , BuildVec ) ; if ( VT == <STR_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , VT , Sel ) ; else if ( VT == <STR_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , VT , Sel ) ; else return DAG . getNode ( <STR_LIT> , DL ,


<s> static <ISA_LIT>Operand * CreateSysCR ( unsigned Val , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_SysCR , Ctx ) ; Op -> SysCRImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> RegNo = tryParseRegister ( <STR_LIT> ) ; EndLoc = Parser . getTok ( ) .


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI ) , Parser ( Parser ) , Lexer ( Parser . getLexer ( ) ) , SubtargetInfo ( STI ) { setAvailableFeatures ( ComputeAvailableFeatures ( SubtargetInfo . getFeatureBits


<s> return __builtin_mve_vddupq_n_uv16qi ( __a ,


<s> return ( __m128d ) __builtin_ia32_sqrtpd ( ( __v2df )


<s> static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) return <STR_LIT> ; assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT>


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperands ( const <ISA_LIT>AddressingMode & AM , EVT VT , SDValue & Base , SDValue & Disp ) { Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; } else if ( Base . getValueType ( ) !=


<s> assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ idx ] . getFrameIdx ( ) << <STR_LIT> << CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ; const int Offset = ( i == <NUM_LIT> ) ? - Count :


<s> rtx tmp , reg ; int i ; if ( count == <NUM_LIT> && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - <NUM_LIT> ) base_reg -= <NUM_LIT> ; count ++ ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + <NUM_LIT> ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - ( count * <NUM_LIT> + <NUM_LIT> ) ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( i * <NUM_LIT> ) ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , i + <NUM_LIT> ) = tmp ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( par ) ) ; RTX_FRAME_RELATED_P ( par


<s> static bool sparc_hard_regno_mode_ok ( unsigned int regno , machine_mode mode


<s> const Function & F = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( F . getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front (


<s> return thumb_base_register_rtx_p ( x , QImode ,


<s> return ( __m128 ) vec_vmrghw ( ( __v4sf ) __A , (


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> getT2Imm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { int32_t Imm8 = MI . getOperand ( OpIdx )


<s> initializeCookieSetterPass ( * PassRegistry :: getPassRegistry (


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = neon_valid_immediate ( op , mode , inverse ,


<s> Out . EmitCodeAlignment ( kNaCl<ISA_LIT>InstructionBundleSize ) ; Out . EmitLabel ( RetTarget ) ; } else { Out . EmitBundleLock ( true ) ; MCInst CALLInst ; CALLInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; CALLInst . addOperand ( Op ) ; Out . EmitInstruction ( CALLInst , STI ) ; Out . EmitBundleUnlock ( )


<s> return ( ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_RENAME_LOAD_REGS ) && optimize >=


<s> else if ( Type == ( unsigned ) <STR_LIT> ) return getRegisterPairOdd ( Reg , MF ) ; else if ( Type == ( unsigned ) <STR_LIT> ) return getRegisterPairEven


<s> rtx xa , xa2 , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , <NUM_LIT> , OPTAB_DIRECT ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa2 , xa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( res , tmp , res , mask


<s> __arm_mcrr2 ( const unsigned int __coproc , const unsigned int __opc1 , uint64_t __value , const unsigned int __CRm ) { return __builtin_arm_mcrr2 ( __coproc , __opc1 ,


<s> <ISA_LIT>AsmInstrumentation * Create<ISA_LIT>AsmInstrumentation ( const MCTargetOptions & MCOptions , const MCContext & Ctx , const MCSubtargetInfo * & STI ) { Triple T ( STI -> getTargetTriple ( ) ) ; const bool hasCompilerRTSupport = T . isOSLinux ( ) ; if ( ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions . SanitizeAddress ) { if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ; if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ; } return new <ISA_LIT>AsmInstrumentation


<s> return STI . getTargetTriple ( ) . startswith ( <STR_LIT>


<s> MachineInstr * MI = T2JumpTables [ i ] ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber (


<s> if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; else factor = <NUM_LIT> ; if ( loongarch_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : return factor ; case ADDRESS_REG_REG : return factor ; case ADDRESS_CONST_INT : return factor ; case ADDRESS_SYMBOLIC : return factor * loongarch_symbol_insns ( addr


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; return IsVarArg ? CC_<ISA_LIT>_DarwinPCS_VarArg : CC_<ISA_LIT>_DarwinPCS ; case CallingConv :: Win64 : return IsVarArg ? CC_<ISA_LIT>_Win64_VarArg : CC_<ISA_LIT>_AAPCS ; case CallingConv :: Mono : if ( Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_Mono_DarwinPCS ; else if ( Subtarget -> isTargetWindows ( ) ) report_fatal_error ( <STR_LIT> ) ; else return


<s> FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; while ( <NUM_LIT> ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I )

MadeChange |= processBasicBlock ( MF , * I ) ;


<s> if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT>


<s> Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q'


<s> if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> vabdq_s32 ( int32x4_t a , int32x4_t b ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op ) ; if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , Op . getValueType ( ) ) , Op ) ; return


<s> if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM ? PRFM -> Name : <STR_LIT> , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! PRFM ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail


<s> uint8_t llvmRegnums [ ] = { ALL_REGS <NUM_LIT> } ; uint8_t llvmRegnum = llvmRegnums [ reg ] ; mcInst . addOperand ( MCOperand ::


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; bool IsFadd = N -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsFadd || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , IsFadd ) ) { auto NewOpcode = IsFadd ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpcode , SDLoc ( N ) , VT , LHS


<s> bool <ISA_LIT>Subtarget :: GVIsIndirectSymbol ( GlobalValue * GV , Reloc :: Model RelocM ) const { if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; }


<s> } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) .


<s> return ( useR7AsFramePointer ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim (


<s> bool <STR_LIT> ( SDNode * N ) { return isVINSERTIndex ( N ,


<s> void updateABIInfo ( const PredicateLibrary & P ) { ABI = P . getABI


<s> EVT MemVT = SN -> getMemoryVT ( ) ; if ( MemVT . isInteger ( ) && SN -> isTruncatingStore ( ) ) { if ( SDValue Value = combineTruncateExtract ( SDLoc ( N ) , MemVT , SN -> getValue ( ) , DCI ) ) { DCI . AddToWorklist ( Value . getNode ( ) ) ; return DAG . getTruncStore ( SN -> getChain ( ) , SDLoc ( SN ) , Value , SN -> getBasePtr ( ) , SN -> getMemoryVT ( ) , SN -> getMemOperand ( ) ) ; } } if ( ! SN -> isTruncatingStore ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && canLoadStoreByteSwapped ( Op1 . getValueType ( ) ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT , SN -> getMemOperand ( ) ) ; } if ( ! SN -> isTruncatingStore ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && Subtarget . hasVectorEnhancements2 ( ) ) { ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op1 . getNode ( ) ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; if ( isVectorElementSwap ( ShuffleMask , Op1 . getValueType ( ) ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) ,


<s> SDLoc DL ( N0 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( <STR_LIT> , Res ) ) ; } } if ( Subtarget . hasAVX512 ( ) && VT . isScalarInteger ( ) && SrcVT . isVector ( ) && SrcVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ( N0 . getNode ( ) ) ) { return combinevXi1ConstantToInteger ( N0 , DAG ) ; } if ( Subtarget . hasAVX512 ( ) && SrcVT . isScalarInteger ( ) && VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && isa < ConstantSDNode > ( N0 ) ) { auto * C = cast < ConstantSDNode > ( N0 ) ; if ( C -> isAllOnesValue ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N0 ) , VT ) ; if ( C -> isNullValue ( ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N0 ) , VT ) ; } if ( SDValue V = combineCastedMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return V ; unsigned FPOpcode ; switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue LogicOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue LogicOp1 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc DL0 ( N0 ) ; if ( N0 . hasOneUse ( ) && LogicOp0 . getOpcode ( ) == <STR_LIT> && LogicOp0 . hasOneUse ( ) && LogicOp0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp0 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp1 = DAG . getBitcast ( VT , LogicOp1 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp0 . getOperand ( <NUM_LIT> ) , CastedOp1 ) ; } if ( N0 . hasOneUse ( ) && LogicOp1 . getOpcode ( ) == <STR_LIT> && LogicOp1 . hasOneUse ( ) && LogicOp1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp1 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp0 = DAG . getBitcast ( VT , LogicOp0 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp1 . getOperand ( <NUM_LIT> ) , CastedOp0 ) ; } return SDValue ( )


<s> return __builtin_aarch64_crypto_aesmcv16qi_uu (


<s> Register <ISA_LIT>FrameLowering :: getInitialCFARegister ( const MachineFunction & MF )


<s> EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; } if ( UseGot ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( TlsGetAddr , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExpr ( Expr ) . addReg ( <NUM_LIT> ) ) ; } else { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( TlsGetAddr , MCSymbolRefExpr :: VK_PLT , Ctx ) ) ) ; } } else { if ( SRVK == MCSymbolRefExpr :: VK_TLSGD && ! UseGot ) { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( Sym ) . addReg ( <NUM_LIT> ) ) ; } else { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExpr ( Sym ) . addReg ( <NUM_LIT> ) ) ; } const MCSymbol * TlsGetAddr = Ctx . getOrCreateSymbol ( <STR_LIT> ) ; if ( UseGot ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( TlsGetAddr , MCSymbolRefExpr :: VK_GOT , Ctx ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg (


<s> if ( isGP64bit ( ) ) { if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp64 , TmpReg , <STR_LIT> , false , false , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } if ( TmpReg != <STR_LIT> && loadImmediate ( Hi_32 ( ImmOp64 ) , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; if ( has<ISA_LIT>32r2 ( ) ) { TOut . emitRR ( <STR_LIT> , FirstReg , <STR_LIT> , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , FirstReg , FirstReg , TmpReg , IDLoc , STI ) ; } else { TOut . emitRR ( <STR_LIT> , nextReg ( FirstReg ) , TmpReg , IDLoc , STI ) ; TOut . emitRR ( <STR_LIT> , FirstReg , <STR_LIT> , IDLoc , STI ) ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF


<s> std :: map < unsigned , MachineInstr * > ColCfgs ; getTileShapesCfg ( CfgMI , ShapedTiles ) ; assert ( ShapedTiles . size ( ) && <STR_LIT> ) ; getShapeCfgInstrs ( CfgMI , RowCfgs


<s> MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , <STR_LIT> ) ; Register SrcLoReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> )

) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcLoReg ) ;


<s> BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) processBasicBlock ( * I ) ; if ( checkFnHasLiveInYmm ( MRI ) ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear ( ) ; return EverMadeChange


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } bool needsTOCRestore = false ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { if ( CallOpc == <STR_LIT> ) { needsTOCRestore = true ; } else if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; } } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( needsTOCRestore ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain ,


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeNEONRd ( insn ) ) ) ) ; ++ OpIdx ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; ++ OpIdx ; } assert ( ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> || OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeNEONRm ( insn ) ) ) ) ; ++ OpIdx ; assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; unsigned


<s> bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( create<ISA_LIT>PostLegalizeCombiner (


<s> } Index = matchHWRegsRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFCCRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchACRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128RegisterName ( Identifier ) ; if ( Index !=


<s> return parseSetPopDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPushDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>0Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok .


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) , OpVT = Op . getValueType ( ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . getVectorElementType ( ) . getSizeInBits ( )

== OpVT . getVectorElementType ( ) . getSizeInBits ( ) ) {


<s> } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back (


<s> unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case E_TImode : result = ( unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node ) ; break ; case E_DImode : result = ( unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node ) ; break ; case E_SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case E_HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case E_QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case E_SFmode : result = V4SF_type_node ; break ; case E_DFmode : result = V2DF_type_node ; break ; case E_V4SImode : case E_V8HImode : case E_V16QImode : case E_V4SFmode : case E_V2DImode : case E_V2DFmode : result = type ; default : break ; } break ; case 'b' : switch ( mode ) { case E_TImode : case E_V1TImode : result = bool_V1TI_type_node ; break ; case E_DImode : case E_V2DImode : result = bool_V2DI_type_node ; break ; case E_SImode : case E_V4SImode : result = bool_V4SI_type_node ; break ; case E_HImode : case E_V8HImode : result = bool_V8HI_type_node ; break ; case E_QImode : case E_V16QImode : result = bool_V16QI_type_node ; default : break ; } break ; case 'p' : switch ( mode ) { case E_V8HImode : result = pixel_V8HI_type_node ; default : break ; } default : break ; } if ( result && result != type && TYPE_QUALS ( type ) ) result = build_qualified_type ( result , TYPE_QUALS ( type ) ) ; * no_add_attrs = true ; if ( result ) * node = lang_hooks . types . reconstruct_complex_type ( * node , result ) ; return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Printer . GetBlockAddressSymbol ( MO .


<s> return ( vector signed char ) __builtin_altivec_lvx ( a1 , ( void


<s> DebugLoc dl = MI . getDebugLoc ( ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAreaOffset ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF .

getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> enum aarch64_parse_opt_result parse_res = aarch64_parse_arch ( str , & tmp_arch , & aarch64_isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) { gcc_assert ( tmp_arch ) ; selected_arch = tmp_arch ; explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str


<s> __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st3v8hi ( ( __builtin_aarch64_simd_hi *


<s> return gen_rtx_REG ( Pmode , AARCH64_STRUCT_VALUE_REGNUM


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( LI

) ) return AtomicExpansionKind :: None ;


<s> static bool isAlternatingShuffMask ( const ArrayRef < int > & Mask , int NumElts ) { bool PrevElemFromFirstVec = Mask [ <NUM_LIT> ] < NumElts ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i ++ ) { if ( PrevElemFromFirstVec && Mask [ i ]


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getDarwinDirective ( ) == <STR_LIT> ) return true ; return


<s> if ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_ELF || TARGET_MACHO ) { bool large_toc_ok ; if ( DEFAULT_ABI == ABI_V4 && flag_pic ) return false ; large_toc_ok = ( lra_in_progress && TARGET_CMODEL != CMODEL_SMALL && small_toc_ref ( x , VOIDmode ) ) ; if ( TARGET_TOC && ! large_toc_ok ) return false ; if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT &&

( mode == DFmode || mode == DDmode ) ) ) return false ;


<s> return __builtin_aarch64_lflooruv2sfv2si_us (


<s> <ISA_LIT>FI = MFunc . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI = & MFunc . getFrameInfo ( ) ; TRI = ST -> getRegisterInfo ( ) ; CfgSS = - <NUM_LIT> ; unsigned NumVirtRegs = MRI -> getNumVirtRegs ( ) ; bool HasVirtTileReg = false ; for ( unsigned I = <NUM_LIT> , E = NumVirtRegs ; I != E ; ++ I ) { Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI -> getRegClass ( VirtReg ) -> getID ( ) == <STR_LIT> ) { HasVirtTileReg = true ; break ; } } if ( ! HasVirtTileReg ) return false ; StackSlotForVirtReg . resize ( NumVirtRegs ) ; MayLiveAcrossBlocks . clear ( ) ; MayLiveAcrossBlocks . resize ( NumVirtRegs * <NUM_LIT> ) ; bool Change = false ; assert ( MRI -> isSSA ( ) ) ; for ( MachineBasicBlock & MBB : MFunc ) canonicalizePHIs ( MBB ) ; ReversePostOrderTraversal < MachineFunction * >


<s> MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end


<s> InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; bool HasRs = false ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true


<s> const char * <ISA_LIT>Subtarget :: getBZeroEntry ( ) const { if ( getTargetTriple ( ) . isMacOSX ( ) && ! getTargetTriple (

) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) return <STR_LIT> ;


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM ,

CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl


<s> MachineOperand * OldFlagDef2 = OldMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( ! OldFlagDef1 == ! OldFlagDef2 && <STR_LIT> ) ; if ( ! OldFlagDef1 || ! OldFlagDef2 ) return ; assert ( OldFlagDef1 -> isDead ( ) && OldFlagDef2 -> isDead ( ) && <STR_LIT> ) ; MachineOperand * NewFlagDef1 = NewMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * NewFlagDef2 = NewMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( NewFlagDef1 &&


<s> if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) &&


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutLo = DAG . getSelectCC ( dl , Tmp5 , DAG . getConstant ( <NUM_LIT> , AmtVT ) , Tmp4 , Tmp6 , <STR_LIT> ) ; SDValue OutOps [ ] = { OutLo , OutHi


<s> uint64_t RegNum = cast < ConstantSDNode > ( RegIdx ) -> getZExtValue ( ) ; return <STR_LIT> . getRegister


<s> if ( CPUName . empty ( ) ) CPUName =


<s> return ( __m128 ) __builtin_ia32_sqrtss_mask_round ( ( __v4sf ) __B , ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) -


<s> return ( Val & ( <NUM_LIT> << <NUM_LIT> ) )


<s> Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ^ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; if ( HiIndex >= <NUM_LIT> ) { Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } else { Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } } Locs . clear ( ) ; Locs . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LoMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > HiMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > * MaskPtr = & LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = & HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; ( * MaskPtr ) [ LoIdx ] = Idx ; LoIdx ++ ; } else { Locs [ i ] = std :: make_pair ( MaskIdx , HiIdx ) ; ( * MaskPtr ) [ HiIdx ] = Idx ; HiIdx ++ ; } } SDValue LoShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & LoMask [ <NUM_LIT> ] ) ; SDValue HiShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & HiMask [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT>


<s> MCAsmParser & Parser = getParser ( ) ; Name = StringSwitch < StringRef > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Name ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && Parser . getTok ( ) . getIdentifier ( ) . lower ( ) == <STR_LIT> ) { parseDirectiveReq ( Name , NameLoc ) ; return true ; } size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) return parseSysAlias ( Head , NameLoc , Operands ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; <STR_LIT> CC = parseCondCodeString (


<s> getBDVAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups


<s> static inline bool equal ( tree_map * a , tree_map * b ) { return a -> base . from == b -> base .


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && Triple ( TM -> getTargetTriple

( ) ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister (


<s> } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex (


<s> static tree ix86_handle_fndecl_attribute ( tree * node , tree name , tree , int , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> ,


<s> { MO_PLT , <STR_LIT> } , { MO_PIC_FLAG , <STR_LIT> } , { MO_PCREL_FLAG , <STR_LIT> } , { MO_GOT_FLAG , <STR_LIT> } , { MO_PCREL_OPT_FLAG , <STR_LIT> } , { MO_TLSGD_FLAG , <STR_LIT> } , { MO_TPREL_FLAG , <STR_LIT> } , { MO_GOT_TLSGD_PCREL_FLAG , <STR_LIT> } , { MO_GOT_TPREL_PCREL_FLAG , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> static bool allocateFloat ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { switch ( LocVT . SimpleTy ) { case <STR_LIT> : { State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; unsigned Offset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT>


<s> void adjustBBSize ( MachineBasicBlock * MBB , int Size ) { BBInfo [ MBB -> getNumber ( ) ] . Size +=


<s> const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; setAction ( { G_IMPLICIT_DEF , s64 } , Legal ) ; setAction ( { G_IMPLICIT_DEF , s128 } , Legal ) ; setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) .


<s> if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == <NUM_LIT> || ( AM . Scale > <NUM_LIT> && ( uint64_t ) AM .


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI ) ) return Result ; if ( SDValue R = PerformSubCSINCCombine ( N , DCI ) ) return R ; if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup ->


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & LII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ?

MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ;


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <NUM_LIT> ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( get ( <STR_LIT> ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return


<s> if ( ( isBasePlusOffsetMemoryAccess ( I -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( I -> getOperand ( AddrIdx ) . getReg ( ) ) ) || I -> modifiesRegister ( <STR_LIT> , TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ) continue ; } Filler = I ; return true ; } return false


<s> addr = XEXP ( mem , <NUM_LIT> ) ; if ( REG_P ( addr ) || ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) )

&& CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) ) return <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerTRUNCATEVector ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; unsigned SrcSize = N1 . getValueType ( ) . getSizeInBits ( ) ; assert ( SrcSize <= <NUM_LIT> && <STR_LIT> ) ; SDValue WideSrc = SrcSize == <NUM_LIT> ? N1 : widenVec ( DAG , N1 , DL ) ; EVT TrgVT = Op . getValueType ( ) ; unsigned TrgNumElts = TrgVT . getVectorNumElements ( ) ; EVT EltVT = TrgVT . getVectorElementType ( ) ; unsigned WideNumElts = <NUM_LIT> / EltVT . getSizeInBits ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , WideNumElts ) ; unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ; SmallVector < int , <NUM_LIT> > ShuffV


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction


<s> if ( num_ovld_stanzas >= MAXOVLDSTANZAS ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } curr_ovld_stanza = num_ovld_stanzas ++ ; ovld_stanza * stanza = & ovld_stanzas [ curr_ovld_stanza ] ; stanza -> stanza_id = stanza_name ; consume_whitespace ( ) ; if ( linebuf [ pos ] != ',' ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } safe_inc_pos ( ) ; consume_whitespace ( ) ; stanza -> extern_name = match_identifier ( ) ; if ( ! stanza -> extern_name ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } consume_whitespace ( ) ; if ( linebuf [ pos ] != ',' ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } safe_inc_pos (


<s> return NULL ; } return CurDAG -> getMachineNode ( Opcode , N -> getDebugLoc ( ) , VT , <STR_LIT> , <STR_LIT> , LD -> getBasePtr


<s> sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , unshare_expr ( valist ) , f_sav , NULL_TREE ) ; words = crtl -> args . info . words ; n_gpr = crtl -> args . info . regno ; n_fpr = crtl -> args . info . sse_regno ; if ( cfun -> va_list_gpr_size ) { type = TREE_TYPE ( gpr ) ; t = build2 ( MODIFY_EXPR , type , gpr , build_int_cst ( type , n_gpr * <NUM_LIT> ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } if ( TARGET_SSE && cfun -> va_list_fpr_size ) { type = TREE_TYPE ( fpr ) ; t = build2 ( MODIFY_EXPR , type , fpr , build_int_cst ( type , n_fpr * <NUM_LIT> + <NUM_LIT> * X86_64_REGPARM_MAX ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } type = TREE_TYPE ( ovf ) ; if ( cfun -> machine -> split_stack_varargs_pointer == NULL_RTX ) ovf_rtx = crtl -> args . internal_arg_pointer ; else ovf_rtx = cfun -> machine -> split_stack_varargs_pointer ; t = make_tree ( type , ovf_rtx ) ; if ( words != <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , words * UNITS_PER_WORD ) ; if ( chkp_function_instrumented_p ( current_function_decl ) ) chkp_expand_bounds_reset_for_mem ( ovf , t ) ; t = build2 ( MODIFY_EXPR , type , ovf , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( ix86_varargs_gpr_size ||


<s> MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( MI . getOpcode ( ) == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits ,


<s> bool CantAnalyze = false ; while ( I -> isDebugValue ( ) || ! I -> isTerminator ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( isIndirectBranchOpcode ( I -> getOpcode ( ) ) || isJumpTableBranchOpcode ( I -> getOpcode ( ) ) ) { CantAnalyze = true ; } else if ( isUncondBranchOpcode ( I -> getOpcode ( ) ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ; assert ( ! FBB &&


<s> void addConstpoolOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> const BasicBlockInfo & BBI = BBInfo [ Block ] ; dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << Block << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI <<

format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ;


<s> MachineBasicBlock * target = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) ,

TII -> get ( BtOpc ) ) . addMBB ( target ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getIntImmCodeSizeCost ( unsigned Opcode , unsigned Idx , const


<s> CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; DenseMap < unsigned , SDValue > CopiedRegs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign VA = RVLocs [ i ] ; if ( i == <NUM_LIT> && isThisReturn ) { assert ( ! VA . needsCustom ( ) && VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; InVals . push_back ( ThisVal ) ; continue ; } SDValue Val = CopiedRegs . lookup ( VA . getLocReg ( ) ) ; if ( ! Val ) { Val = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; CopiedRegs [ VA . getLocReg ( ) ] = Val ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL ,


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t )

<STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> unsigned <ISA_LIT>ConstantIslands :: getUserOffset ( CPUser & U ) const { unsigned UserOffset = getOffsetOf ( U . MI ) ; const BasicBlockInfo & BBI = BBInfo [ U . MI -> getParent ( ) -> getNumber ( ) ] ; unsigned KnownBits = BBI . internalKnownBits ( ) ; UserOffset += ( isThumb ? <NUM_LIT> :


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( NumBytes != <NUM_LIT> ) emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , NumBytes , <STR_LIT> , <STR_LIT> ) ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> )


<s> return ( __m64 ) __builtin_ia32_pslld ( ( __v2si


<s> for ( new = imports_list ; new ; new = new -> next ) if ( new -> name == name ) return ; new = ( struct import * ) xmalloc ( sizeof ( struct import ) ) ; new -> next = imports_list ; imports_list = new ; new -> name =


<s> return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm10 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7


<s> int16_t Imm = CN -> getSExtValue ( ) ; Offset = CurDAG -> getTargetConstant ( Imm , DL , CN -> getValueType ( <NUM_LIT> ) ) ; Base = CurDAG -> getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } if ( canBeRepresentedAsSls ( * CN ) ) return false ; } else { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { int16_t Imm = CN -> getSExtValue ( ) ; Offset = CurDAG -> getTargetConstant ( Imm , DL , CN -> getValueType ( <NUM_LIT> ) ) ; Base = CurDAG -> getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; return true ; } if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; <STR_LIT> AluOperator = static_cast < <STR_LIT> > ( Addr . getOpcode ( ) ) ; if ( AluOperator == <STR_LIT> ) { AluOp = CurDAG -> getTargetConstant ( LPAC :: ADD , DL , <STR_LIT> ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( ( RiMode && isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) || ( ! RiMode && isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT>


<s> return DisableFramePointerElim ( MF ) || MFI ->


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask


<s> selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; if ( opts -> x_explicit_tune_core == aarch64_none && opts -> x_explicit_arch != aarch64_no_arch ) selected_tune = &


<s> case GT : return AARCH64_LT ; case LE : return AARCH64_GE ; case LT : return AARCH64_GT ; case GEU : return AARCH64_LS ; case GTU : return AARCH64_CC ; case LEU : return AARCH64_CS ; case LTU : return AARCH64_HI ; default : return - <NUM_LIT> ; } break ; case CC_NZmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_PL ; case LT : return AARCH64_MI ; default : return - <NUM_LIT> ; } break ; case CC_Zmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; default : return - <NUM_LIT> ; } break ; case CC_Cmode : switch ( comp_code ) { case NE : return


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const

MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) {


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT>


<s> gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return


<s> } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; MCSectionELF * Section = OutStreamer -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = CurrentFnSymForSize ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT>


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ParallelDSPPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple (


<s> MachineBasicBlock * RestoreMBB = TargetMBB ; if ( STI . is32Bit ( ) ) { RestoreMBB = MF . CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF . insert ( TargetMBB , RestoreMBB ) ; MBB . removeSuccessor ( TargetMBB ) ; MBB . addSuccessor ( RestoreMBB ) ; RestoreMBB -> addSuccessor ( TargetMBB ) ; MBBI -> getOperand ( <NUM_LIT> ) . setMBB ( RestoreMBB ) ; } unsigned ReturnReg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( RestoreMBB ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( ReturnReg ) . addMBB ( RestoreMBB ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( STI . is32Bit ( ) ) { auto RestoreMBBI = RestoreMBB -> begin ( ) ; restoreWin32EHStackPointers ( * RestoreMBB , RestoreMBBI , DL , true ) ; BuildMI ( * RestoreMBB , RestoreMBBI , DL , TII . get ( <STR_LIT> ) ) . addMBB ( TargetMBB ) ; } } else if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { NumBytes = MFI -> getMaxCallFrameSize ( ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize ,


<s> return decodeRegisterClass ( Inst , RegNo , FRegs


<s> return ( isMOVLMask ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> ) || isCommutedMOVL ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> , true ) || isSHUFPMask ( & BVOps [ <NUM_LIT> ] , <NUM_LIT> ) || isCommutedSHUFP ( &


<s> return ( ( vec_int4 ) ( si_sfx ( ( qword ) ( b ) , ( qword ) ( a ) , (


<s> SDValue Ops [ ] = { BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } } if ( LateMask ) { unsigned Mask = ( unsigned ) getZerosMask ( ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal


<s> unsigned Binary = ( <STR_LIT> ( SoImm ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( SoImm


<s> BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = MBB . end ( ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { MachineInstr * MI = I ; bool IsReturnFrom<ISA_LIT>INTR = Is<ISA_LIT>INTR && MI -> isReturn ( ) ; bool IsControlFlow = MI -> isCall ( ) || MI -> isReturn ( ) ; if ( ( ! IsControlFlow || IsReturnFrom<ISA_LIT>INTR ) && CurState == EXITS_DIRTY ) continue ; if ( hasYmmReg ( MI ) ) { CurState = EXITS_DIRTY ; continue ; } if ( ! IsControlFlow || IsReturnFrom<ISA_LIT>INTR ) continue ; if ( MI -> isCall ( ) && ! callClobbersAnyYmmReg ( MI ) ) continue ; if ( CurState == EXITS_DIRTY ) { insertVZeroUpper ( I , MBB ) ; CurState = EXITS_CLEAN ; } else if ( CurState == PASS_THROUGH ) { BlockStates [ MBB . getNumber ( ) ] . FirstUnguardedCall = I ; CurState = EXITS_CLEAN ; } } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << getBlockExitStateName ( CurState ) << '\n' ) ; if ( CurState == EXITS_DIRTY ) for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; BlockStates [ MBB . getNumber ( ) ] . ExitState


<s> static bool selectCopy ( MachineInstr & I , const TargetInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = guessRegClass ( DstReg , MRI , TRI , RBI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return


<s> unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return


<s> if ( ! ( MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; if ( SHMI + MEMI != <NUM_LIT> ) return false ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI -> getOpcode ( ) != <STR_LIT> && SrcMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) return false ; assert ( SrcMI -> getNumOperands ( ) ==


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> )


<s> Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; bool IsZExt = isa < ZExtInst > ( I ) ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT , DestEVT ; SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; Register AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = ( AssignedReg ? MRI . getRegClass ( AssignedReg ) : ( DestVT == <STR_LIT> ?


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: WebKit_JS : return CC_<ISA_LIT>_WebKit_JS ; case CallingConv :: C : case CallingConv :: Fast : if ( ! Subtarget -> isTargetDarwin ( ) )


<s> T2JumpTables . clear ( ) ; MF . RenumberBlocks ( ) ; } if ( ! isThumb1 ) MF . EnsureAlignment ( <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP . isEmpty ( ) ) { DoInitialPlacement ( MF , CPEMIs ) ; if ( isThumb1 ) MF . EnsureAlignment ( <NUM_LIT> ) ; } AFI -> initConstPoolEntryUId ( CPEMIs . size ( ) ) ; InitialFunctionScan ( MF , CPEMIs ) ; CPEMIs . clear ( ) ; RemoveUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= HandleConstantPoolUser ( MF , i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i

) BRChange |= FixUpImmediateBr ( MF , ImmBranches [ i ] ) ;


<s> if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( valtype ) , valtype , & dummy_mode , & dummy_int , NULL , false ) ) return false ; pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( valtype ) ) return false ; return true


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> CLEAR_HARD_REG_SET ( full_reg_clobbers ) ; SET_HARD_REG_BIT ( full_reg_clobbers , R0_REGNUM ) ; SET_HARD_REG_BIT ( full_reg_clobbers , CC_REGNUM ) ; for ( int regno = P0_REGNUM ; regno <= P15_REGNUM ; ++

regno ) SET_HARD_REG_BIT ( full_reg_clobbers , regno ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5FP16 ( SDValue N , SDValue & Base , SDValue & Offset ) { int Lwb = - <NUM_LIT> + <NUM_LIT> ; int Upb = <NUM_LIT> ; return IsAddressingMode5 ( N , Base , Offset , Lwb


<s> return ( ( vec_double2 ) ( si_rotqby ( ( qword ) ( a ) ,


<s> unsigned Scale = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MachineOperand & Imm = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; Imm . setImm ( Imm . getImm ( ) * Scale ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) && <STR_LIT> ) ; MachineOperand & Imm = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; int64_t ImmVal = Imm . getImm ( ) ; Imm . setImm ( <NUM_LIT> | ( ( ImmVal & <NUM_LIT> ) << <NUM_LIT> ) | ( ImmVal & <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto BuildPSADBW = [ & ] ( SDValue Op0 , SDValue Op1 ) { SDValue Sad = createPSADBW ( DAG , Op0 , Op1 , DL


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,