<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( VA . isUpperBitsInLoc ( ) ) { unsigned ValSizeInBits = Ins [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; unsigned Shift = VA . getLocInfo ( ) == CCValAssign :: ZExtUpper ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( Shift , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; } switch ( VA . getLocInfo (


<s> inline vector float vec_min ( vector float a1


<s> Table = DecoderTable32 ; } else { Size = <NUM_LIT> ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) return MCDisassembler :: Fail ; uint64_t Inst = <NUM_LIT> ; for ( uint64_t I = <NUM_LIT> ; I < Size ; ++ I ) Inst = ( Inst << <NUM_LIT> ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address ,


<s> i960_print_operand_addr ( FILE , ADDR ) { \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( <NUM_LIT> ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( <NUM_LIT> ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD ,

GEN_INT ( <NUM_LIT> ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( <NUM_LIT> ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( <NUM_LIT> ) ) ; \ }


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvttsd_si32 ( __m128d __A ) { int result = ( ( __v2df ) __A ) [ <NUM_LIT> ] ; return result


<s> if ( No<ISA_LIT>CFOpt . getValue ( ) ) return false ; if ( STI -> isTargetDarwin ( ) && ( ! MF . getLandingPads ( ) . empty ( ) || ( MF . getFunction ( ) . needsUnwindTableEntry ( ) && ! TFL -> hasFP ( MF ) ) ) ) return false ; if ( STI -> isTargetWin64 ( ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; unsigned FrameDestroyOpcode = TII -> getCallFrameDestroyOpcode ( ) ; bool UseStackProbe = ! STI -> getTargetLowering ( ) -> getStackProbeSymbolName ( MF ) . empty ( ) ; unsigned StackProbeSize = STI -> getTargetLowering ( ) -> getStackProbeSize ( MF ) ; for ( MachineBasicBlock & BB : MF ) { bool InsideFrameSequence = false ; for ( MachineInstr & MI : BB ) { if ( MI . getOpcode ( ) == FrameSetupOpcode ) { if ( TII -> getFrameSize ( MI ) >= StackProbeSize && UseStackProbe ) return false ; if ( InsideFrameSequence ) return false ; InsideFrameSequence = true


<s> case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; if ( <ISA_LIT>SubTarget -> hasFusion ( ) && ( ! MF -> getFunction ( ) -> optForSize ( ) && ! Base . hasOneUse ( ) ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = GV -> getAlignment ( ) - <NUM_LIT> ; } int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( GV -> getAlignment ( ) < <NUM_LIT> && ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || ( Offset % <NUM_LIT> ) != <NUM_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , <STR_LIT> , Offset , Flags ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { const Constant * C = CP -> getConstVal ( ) ; ImmOpnd = CurDAG -> getTargetConstantPool ( C , <STR_LIT> , CP ->


<s> typename __altivec_bool_ret < vec_step ( T ) > :: __ret \ NAME ( T


<s> bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv ::


<s> createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckl ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode


<s> for ( unsigned i = <NUM_LIT> ; i < and_insns . length ( ) ; i ++ ) { rtx_insn * and_insn = and_insns [ i ] ; rtx and_op = and_ops [ i ] ; rtx and_base = XEXP ( and_op , <NUM_LIT> ) ; if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base


<s> static tree arm_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == <NUM_LIT> )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , VT ) ; <STR_LIT> Flags = Arg . Flags ; Flags . setOrigAlign ( TLI . getABIAlignmentForCallingConv ( Arg . Ty , DL ) ) ; PushBack ( Flags , RegisterVT , VT , true , OrigArgIndices [ ArgNo ] ,


<s> if ( INSN_P ( insn ) ) { if ( FIND_REG_INC_NOTE ( insn , reg ) ) return true ; insn = PATTERN ( insn ) ; } if ( GET_CODE ( insn ) == SET && GET_CODE ( XEXP ( insn , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( insn , <NUM_LIT> ) ) ==

REG && REGNO ( XEXP ( insn , <NUM_LIT> ) ) == REGNO ( XEXP ( insn , <NUM_LIT> ) ) ) return false ;


<s> type_class_index tclass = fi . type_suffix ( <NUM_LIT> ) . tclass ; unsigned int element_bits = GET_MODE_BITSIZE ( m_to_mode ) ; type_suffix_index suffix = find_type_suffix ( tclass , element_bits ) ; return scalar_types [ type_suffixes [ suffix ]


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS


<s> } for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ; mask = ~ Val


<s> case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; std :: vector < EVT > ResTys ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; if ( isUpdating ) ResTys . push_back (


<s> auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < <ISA_LIT>TargetMachine


<s> if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } ix86_set_func_type ( fndecl ) ; ix86_set_indirect_branch_type ( fndecl ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; static bool prev_no_caller_saved_registers ; if ( TARGET_64BIT && ( call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ; else if ( prev_no_caller_saved_registers != cfun -> machine -> no_caller_saved_registers ) reinit_regs ( ) ; if ( cfun -> machine -> func_type != TYPE_NORMAL || cfun -> machine -> no_caller_saved_registers ) { const char * isa ; if ( TARGET_SSE ) isa = <STR_LIT> ; else if ( TARGET_MMX ) isa = <STR_LIT> ; else if ( TARGET_80387 ) isa = <STR_LIT> ; else isa = NULL ; if ( isa != NULL ) { if ( cfun -> machine -> func_type != TYPE_NORMAL ) sorry ( cfun -> machine -> func_type == TYPE_EXCEPTION ? G_ (


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return GetRelocTypeInner ( Target , Fixup


<s> bool has64BitAtomicStore ; if ( Subtarget -> isMClass ( ) ) has64BitAtomicStore = false ; else if ( Subtarget -> isThumb ( ) ) has64BitAtomicStore = Subtarget -> hasV7Ops ( ) ; else has64BitAtomicStore = Subtarget -> hasV6Ops


<s> if ( RV . getNode ( ) ) return RV ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = DAG . getNode ( <STR_LIT> , dl ,


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Assigner . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { if ( Info . OrigRet . Regs . size ( ) > <NUM_LIT> ) return false ; SplitArgs . clear ( ) ; SmallVector < Register , <NUM_LIT> > NewRegs ; splitToValueTypes ( Info . OrigRet , SplitArgs , DL , Info . CallConv ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( RetCC_<ISA_LIT> ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; if ( ! NewRegs . empty ( ) ) MIRBuilder . buildMerge (

Info . OrigRet . Regs [ <NUM_LIT> ] , NewRegs ) ;


<s> if ( CM == CodeModel :: JITDefault ) RM = Reloc :: Static ; else if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> rtx def_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link ->


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; if ( NumOps != <NUM_LIT> && NumOps != <NUM_LIT> && NumOps != <NUM_LIT> && NumOps != <NUM_LIT> ) return false ; if ( ! isUndefOrEqual ( Mask [ <NUM_LIT> ] ,


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( Opc == <STR_LIT> ) { Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops . data ( ) , Ops . size ( ) ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp ,


<s> return mep_lookup_pragma_flag ( funcname , FUNC_CALL


<s> return ELF :: R_<ISA_LIT>_REFLONG ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_REFQUAD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REFLONG ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO32 ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_LO32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOTOFF_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOTOFF_LO32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PLT_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PLT_LO32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI32 ; case <STR_LIT> : return ELF ::


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , unsigned ExtraT , MachineBasicBlock & FMBB , unsigned NumF , unsigned

ExtraF , const BranchProbability & Probability ) const {


<s> void printf32mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI ,


<s> tree arg ; call_expr_arg_iterator iter ; unsigned attr = rs6000_builtin_info [ fcode ] . attr ; enum insn_code icode = d -> icode ; const struct insn_operand_data * insn_op ; bool uses_spr = ( attr & RS6000_BTC_SPR ) ; rtx cr = NULL_RTX ; if ( uses_spr ) icode = rs6000_htm_spr_icode ( nonvoid ) ; insn_op = & insn_data [ icode ] . operand [ <NUM_LIT> ] ; if ( nonvoid ) { machine_mode tmode = ( uses_spr ) ? insn_op -> mode : E_SImode ; if ( ! target || GET_MODE ( target ) != tmode || ( uses_spr && ! ( * insn_op -> predicate ) ( target , tmode ) ) ) target = gen_reg_rtx ( tmode ) ; if ( uses_spr ) op [ nopnds ++ ] = target ; } FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { if ( arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS ) return const0_rtx ; insn_op = & insn_data [ icode ] . operand [ nopnds ] ; op [ nopnds ] = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( op [ nopnds ] , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { int arg_num = ( nonvoid ) ? nopnds : nopnds + <NUM_LIT> ; if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++ ; } switch ( fcode ) { case HTM_BUILTIN_TENDALL : case HTM_BUILTIN_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; case HTM_BUILTIN_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; op [ nopnds ++ ] = gen_rtx_REG ( mode , htm_spr_regno ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds += <NUM_LIT> ; gcc_assert ( nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS ) ; } switch ( nopnds ) { case


<s> bool <ISA_LIT>TargetLowering :: shouldAlignPointerArgs ( CallInst * CI , unsigned & MinSize , unsigned & PrefAlign ) const { if ( ! isa < MemIntrinsic > ( CI ) ) return false ; MinSize = <NUM_LIT> ; PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; setAction ( { G_ZEXT , s32 } , Legal ) ; setAction ( { G_SEXT , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue HiLHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS , ShiftAmt ) ; SDValue HiRHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS , ShiftAmt ) ; SDValue Args [ ] = { HiLHS , LHS , HiRHS , RHS } ; SDValue MulResult = TLI . makeLibCall ( DAG , RTLIB :: MUL_I128 , WideVT , Args , <NUM_LIT> , isSigned , dl ) . first ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG .


<s> for ( auto I = Regs . rbegin ( ) , J = I + <NUM_LIT> , E = Regs . rend ( )


<s> MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C ,


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Reg = <NUM_LIT> ; if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) Reg = <STR_LIT> ; return LoadRegFromStackSlot ( MF , DL , Reg , FrameIdx , & <STR_LIT> , NewMIs , NonRI , SpillsVRS ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get (


<s> return __builtin_mve_vcmpneq_n_v16qi ( ( int8x16_t ) __a , ( int8_t )


<s> else if ( REG_P ( src ) || GET_CODE ( src ) == SUBREG ) src = gen_rtx_REG ( SFmode , true_regnum ( src ) ) ; fp1 = gen_rtx_REG ( SFmode , REGNO ( scratch ) ) ; fp2 = gen_rtx_REG ( SFmode , REGNO ( scratch ) + FP_INC ) ; emit_move_insn ( copy_rtx ( fp1 ) , src ) ; emit_move_insn ( copy_rtx ( fp2 )


<s> auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Gathers . push_back ( II ) ; } } if ( Gathers . empty ( ) ) return false ; for ( IntrinsicInst * I : Gathers ) lowerGather ( I ) ; return


<s> if ( CurGroupDbg . length ( ) ) cgd << <STR_LIT> ; dumpSU ( SU , cgd ) ; ) ; LastEmittedMI = SU -> getInstr ( ) ; if ( SU -> isCall ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; Reset ( ) ; LastEmittedMI = SU -> getInstr ( ) ; return ; } for ( TargetSchedModel :: ProcResIter PI = SchedModel -> getWriteProcResBegin ( SC ) , PE = SchedModel -> getWriteProcResEnd ( SC ) ; PI != PE ; ++ PI ) { if ( SchedModel -> getProcResource ( PI -> ProcResourceIdx ) -> BufferSize == <NUM_LIT> ) continue ; int & CurrCounter = ProcResourceCounters [ PI -> ProcResourceIdx ] ; CurrCounter += PI -> Cycles ; if ( ( CurrCounter > ProcResCostLim ) && ( CriticalResourceIdx == UINT_MAX || ( PI -> ProcResourceIdx != CriticalResourceIdx && CurrCounter > ProcResourceCounters [


<s> void <ISA_LIT>AsmPrinter :: printVFPf32ImmOperand ( const MachineInstr * MI , int OpNum ) { const ConstantFP * FP = MI -> getOperand ( OpNum


<s> matchRegisterNameHelper ( RegNo , Name ) ; if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Name . size ( ) ) ; getLexer ( ) . Lex


<s> for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = <NUM_LIT> ; i < nclobs ; ++ i ) XVECEXP ( insn , <NUM_LIT> , i ) = clobs [ i ] ; return insn


<s> if ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) ) return true ; if ( mode == BLKmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS

( mode ) == MODE_COMPLEX_INT ) return true ;


<s> AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; unsigned Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == Release ) { Domain = <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ,

DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( Domain , <STR_LIT> ) ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT Op1VT = V1 . getValueType ( ) ; EVT Op2VT = V2 . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( Op1VT == Op2VT && <STR_LIT> ) ; assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; SDValue NewV2 = PromoteMVEPredVector ( dl , V2 , Op2VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; EVT ConcatVT = <STR_LIT> ( ElType , NumElts ) ; SDValue ConVec = DAG . getNode ( <STR_LIT> , dl , ConcatVT ) ; auto ExractInto = [ & DAG , & dl ] ( SDValue NewV , SDValue ConVec , unsigned & j ) { EVT NewVT = NewV . getValueType ( ) ; EVT ConcatVT = ConVec . getValueType ( ) ; for ( unsigned i = <NUM_LIT> , e = NewVT . getVectorNumElements ( ) ; i < e ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , DAG . getIntPtrConstant


<s> } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> ) ; Opc = <STR_LIT> ; } if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( IdxVal , dl ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> ) { const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool MinSize = F -> hasFnAttribute ( Attribute :: MinSize ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } N2 = DAG . getIntPtrConstant ( IdxVal << <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return Op ; } } if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits


<s> for ( auto Use : Prev -> uses ( ) ) if ( Use . isKill ( ) ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Use . getReg ( ) , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; MBB . erase ( Prev )


<s> static SDValue combineFMinNumFMaxNum ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . useSoftFloat ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 ) ; SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0


<s> bool <ISA_LIT>PassConfig :: addIRTranslator (


<s> assert ( VT . is256BitVector ( ) && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SDLoc dl ( Op ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = Extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT .


<s> return acle_vector_types [ <NUM_LIT> ] [ type_suffix ( i ) .


<s> return ( __m512i ) __builtin_ia32_psrldq512 ( __A ,


<s> } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C -> getAPIntValue ( ) ; Ops . push_back ( DAG . getConstant ( CInt .

zextOrTrunc ( <NUM_LIT> ) , <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : ScaleFactor = <NUM_LIT> ; break ; } bool UseScaled = true ; if ( ( Addr . getOffset ( ) < <NUM_LIT> ) || ( Addr . getOffset ( ) & ( ScaleFactor - <NUM_LIT> ) ) ) { UseScaled = false ; ScaleFactor = <NUM_LIT> ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ]


<s> bool sh_extending_set_of_reg :: can_use_as_unextended_reg ( void ) const { if ( ( ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND ) && ( from_mode == QImode || from_mode == HImode ) && set_src != NULL ) return arith_reg_operand ( XEXP ( set_src , <NUM_LIT> ) , from_mode ) ; else return false


<s> static tree aarch64_lookup_simd_builtin_type ( machine_mode mode , enum aarch64_type_qualifiers q ) { int i ; int nelts = sizeof ( aarch64_simd_types ) / sizeof ( aarch64_simd_types [ <NUM_LIT> ] ) ; if ( q != qualifier_poly && ! VECTOR_MODE_P ( mode ) ) return aarch64_simd_builtin_std_type ( mode , q ) ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { if ( aarch64_simd_types [ i ] . mode == mode && aarch64_simd_types [ i ]

. q == q ) return aarch64_simd_types [ i ] . itype ;


<s> bool IsIndirect = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; if ( Subtarget -> useMovt ( ) && Subtarget -> isTargetDarwin ( ) == ( RelocM != Reloc :: Static ) ) { unsigned Opc ; switch ( RelocM ) { case Reloc :: PIC_ : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case Reloc :: DynamicNoPIC : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; default : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc )

, DestReg ) . addConstantPoolIndex ( Idx ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getFSOpcode ( unsigned OpcCJE ) { switch ( OpcCJE ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default :


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast


<s> bool SelectAddrIdx ( SDValue Op , SDValue N , SDValue & Base , SDValue &


<s> return ( ( int_size_in_bytes ( type ) > ( <NUM_LIT> * UNITS_PER_WORD ) ) || ( int_size_in_bytes ( type ) == -


<s> if ( f & CC_FLAG_O ) { if ( f & CC_FLAG_C ) return CCmode ; else return CC_ZSOmode ; } else if ( f & CC_FLAG_C ) return CC_ZSCmode ; else return CC_ZSmode


<s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_NEG : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> :


<s> case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_VK1 : case TYPE_VK8 : case TYPE_VK16 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512


<s> if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return MRI -> canReserveReg


<s> if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL && DECL_NAME ( TYPE_NAME ( type ) ) && ! strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( TYPE_NAME ( type ) ) ) , <STR_LIT>


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


, __artificial__ ) ) _mm_undefined_ps ( void ) {


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( isASR ) { if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( ExLoc , <STR_LIT>


<s> e1 = XEXP ( p , <NUM_LIT> ) ; switch ( GET_CODE ( e0 ) ) { case MEM : if ( GET_CODE ( XEXP ( e0 , <NUM_LIT> ) ) != PRE_DEC || GET_CODE ( XEXP ( XEXP ( e0 , <NUM_LIT> ) , <NUM_LIT> ) ) != REG || REGNO ( XEXP ( XEXP ( e0 , <NUM_LIT> ) , <NUM_LIT> ) ) != SP_REGNUM ) abort ( ) ; asm_fprintf ( asm_out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( REGNO ( e1 ) ) ) asm_fprintf ( asm_out_file , <STR_LIT> , ( REGNO ( e1 ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( asm_out_file , <STR_LIT> , REGNO ( e1 ) ) ; break ; case REG : if ( REGNO ( e0 ) == SP_REGNUM ) { if ( GET_CODE ( e1 ) != PLUS || GET_CODE ( XEXP ( e1 , <NUM_LIT> ) ) != REG || REGNO ( XEXP ( e1 , <NUM_LIT> ) ) != SP_REGNUM || GET_CODE ( XEXP ( e1 , <NUM_LIT> ) ) != CONST_INT ) abort ( ) ; asm_fprintf ( asm_out_file , <STR_LIT> , - INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ) ; } else if ( REGNO ( e0 ) == HARD_FRAME_POINTER_REGNUM ) { HOST_WIDE_INT offset ; unsigned reg ; if ( GET_CODE ( e1 ) == PLUS ) { if ( GET_CODE ( XEXP ( e1 , <NUM_LIT> ) ) != REG || GET_CODE ( XEXP ( e1 , <NUM_LIT> ) ) != CONST_INT ) abort ( ) ; reg = REGNO ( XEXP ( e1 , <NUM_LIT> ) ) ; offset = INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ; asm_fprintf ( asm_out_file , <STR_LIT> , HARD_FRAME_POINTER_REGNUM , reg , INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ) ; } else if ( GET_CODE ( e1 ) == REG ) { reg = REGNO ( e1 ) ; asm_fprintf ( asm_out_file , <STR_LIT> , HARD_FRAME_POINTER_REGNUM , reg ) ; } else abort ( ) ; } else if ( GET_CODE ( e1 ) == REG && REGNO ( e1 ) == SP_REGNUM ) { asm_fprintf ( asm_out_file , <STR_LIT> , REGNO


<s> static section * rs6000_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return default_elf_select_rtx_section ( mode


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) )


<s> m_pGpDispSymbol = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Section , ResolveInfo :: Define , ResolveInfo :: Absolute , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null ( ) , ResolveInfo :: Default ) ; pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Absolute , <NUM_LIT> , <NUM_LIT> , FragmentRef


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> &&


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; }


<s> inline vector float vec_vaddfp ( vector float a1 , vector float a2 ) { return ( vector float ) __builtin_altivec_vaddfp ( ( vector float ) a1 , ( vector


<s> virtual bool EmitValueToOffset ( const MCExpr * Offset , unsigned char Value = <NUM_LIT>


<s> return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E )


<s> while ( base_def_link ) { if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( ! and_operation ) return false ; and_insns -> safe_push ( and_insn ) ; and_ops -> safe_push (


<s> void <ISA_LIT>ATTInstPrinter :: printSSECC ( const MCInst * MI , unsigned


<s> Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc =


<s> Offset = getScaledOffsetForBitWidth ( DAG , Offset , DL , RetVT . getScalarSizeInBits ( ) ) ; Opcode = <STR_LIT> ; } if ( Opcode == <STR_LIT> && Offset . getValueType ( ) . isVector ( ) ) std :: swap ( Base , Offset ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( ! isValidImmForSVEVecImmAddrMode ( Offset , RetVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG .


<s> static __inline void _mm_free ( void


<s> bool <ISA_LIT>InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( Subtarget . getFrameLowering ( ) -> has128ByteRedZone ( MF ) ) { const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo


<s> void printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const override { if ( MAI -> getAssemblerDialect ( ) == <NUM_LIT> ) OS << '%' ; OS << <ISA_LIT>ATTInstPrinter :: getRegisterName ( RegNo


<s> assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> return __builtin_ia32_aesenc256kl_u8 ( ( __v2di * ) __A , (


<s> if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; uint8_t Type = MCELF :: GetType ( Data ) ; if ( ( Type != ELF :: STT_FUNC ) || ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> <NUM_LIT> ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else llvm_unreachable (


<s> if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return splitVectorIntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return splitVectorIntUnary ( Op , DAG ) ; assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; return LowerVectorCTLZInRegLUT ( Op , DL ,


<s> bool MadeChange = false ; if ( Buckets . empty ( ) ) return MadeChange ; SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( auto & Bucket : Buckets ) { if ( Bucket . Elements . size

( ) < DispFormPrepMinThreshold ) continue ;


<s> unsigned int __i0 = ( unsigned short ) __w1 << <NUM_LIT> | ( unsigned short ) __w0 ; return _mm_set_pi32 ( __i1


<s> if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Opc == G_ZEXT ) return Size == <NUM_LIT> ? <STR_LIT>


<s> int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , DL . getPointerSizeInBits ( <NUM_LIT> ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return


<s> VariantKind getKind ( ) const { return static_cast < VariantKind > (


<s> unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( ( R << <NUM_LIT> ) |

SysM ) ) return MCDisassembler :: Fail ;


<s> if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) != <NUM_LIT> ; if ( CONST_INT_P ( x ) ) { HOST_WIDE_INT i = INTVAL ( x ) ; if ( ( i >= <NUM_LIT> && i <= <NUM_LIT> ) || ( i >= <NUM_LIT> && i <= <NUM_LIT> ) ) return <NUM_LIT> ; } return <NUM_LIT>


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; const GlobalObject * GO = GV -> getAliaseeObject ( ) ; if ( TLOF -> isGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) { SDValue Small = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Small ) ) ; } else


<s> if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS


<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmOp64 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ImmOp64 = convertIntToDoubleImm ( ImmOp64 ) ; uint32_t ImmOp32 = covertDoubleImmToSingleImm ( ImmOp64 ) ; unsigned TmpReg = <STR_LIT> ; if ( ImmOp32 != <NUM_LIT> ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; } if ( Lo_32 ( ImmOp64 ) == <NUM_LIT> ) { if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp32 , TmpReg , <STR_LIT> , true , false


<s> void <ISA_LIT>WinCOFFStreamer :: EmitThumbFunc ( MCSymbol


<s> if ( cmp1 == const0_rtx ) return cmp0 ; if ( uns_arith_operand ( cmp1 , VOIDmode ) ) return expand_binop ( GET_MODE ( cmp0 ) ,


<s> return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : assert ( ( int64_t ) Value >= <NUM_LIT> && ( int64_t ) Value < ( <NUM_LIT> << <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : assert ( ( int64_t ) Value >= <NUM_LIT> && ( int64_t ) Value < ( <NUM_LIT> << <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; return ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; return ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t Signed = Value ; assert ( Signed >= - ( <NUM_LIT> << <NUM_LIT> ) && Signed < ( <NUM_LIT> << <NUM_LIT> ) && <STR_LIT> ) ; if ( Signed >= <NUM_LIT> ) { Value = ( Value & <NUM_LIT> ) << <NUM_LIT> ; Value |= <NUM_LIT> << <NUM_LIT> ; } else { Value = ( ~ Value & <NUM_LIT> ) << <NUM_LIT> ; } return Value ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t Signed = Value ; assert ( Signed >= - ( <NUM_LIT> << <NUM_LIT> ) && Signed < ( <NUM_LIT> << <NUM_LIT> ) && <STR_LIT> ) ; if ( Signed >= <NUM_LIT> ) { Value = ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; Value |= <NUM_LIT> << <NUM_LIT> ; } else { Value = ( ( ~ Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; } return Value ; } case <STR_LIT> : case <STR_LIT>


<s> getTargetStreamer ( ) . emitARM64WinCFIEpilogEnd (


<s> void emitARM64WinCFISaveFRegP ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT>


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSysReg ( OperandVector & Operands ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return


<s> void EmitARM64WinCFISaveRegP ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT> << Offset <<


<s> return restricted ? std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) : std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 'v' && Constraint [ Size - <NUM_LIT> ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( <NUM_LIT> , Size - <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , RegNo ) ; if ( ! Failed && RegNo >= <NUM_LIT> && RegNo <=


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) +

MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ;


<s> rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & <NUM_LIT> ) && ! TARGET_PREFER_KNOWN_REP_MOVSB_STOSB && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , <NUM_LIT> ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , <NUM_LIT> ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , <NUM_LIT> ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , <NUM_LIT> ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode


<s> bool useAA ( ) const override { return


<s> unsigned RegMaskSize = MachineOperand :: getRegMaskSize ( getNumRegs ( ) ) ; memcpy ( UpdatedMask , * Mask , sizeof ( UpdatedMask [ <NUM_LIT> ] ) * RegMaskSize ) ; for ( size_t i = <NUM_LIT> ; i < <STR_LIT> . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegCustomCalleeSaved ( i ) ) { for ( MCSubRegIterator SubReg ( <STR_LIT> . getRegister ( i ) , this , true ) ; SubReg . isValid ( ) ; ++ SubReg


<s> if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if (


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; uint32_t ImmVal = <NUM_LIT> ; if ( MO . isImm ( ) ) ImmVal = static_cast < uint32_t > ( MO . getImm ( ) ) ; else { assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( FixupKind ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; } return ImmVal


<s> addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ]


<s> if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> isLittle ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LoopAccessInfo LAI ( L , SE , TLI , AA , DT , LI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( ! RecordSequentialLoads ( Header ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return


<s> MachineMemOperand * MMO = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; return DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } , N

-> getSimpleValueType ( <NUM_LIT> ) , MMO ) ;


<s> return __builtin_mve_vmaxavq_sv8hi ( __a ,


<s> const Function * F = MF -> getFunction ( ) ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ? CSR_FP_INTR_SaveList : CSR_FP_SaveList ) ; else return ( F -> getCallingConv ( ) == CallingConv


<s> if ( rtx_equal_p ( dst , src ) ) matching_memory = true ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( code == NOT ) emit_insn


<s> AsmTransCBE = x86_asm_table ; AssemblerDialect = AsmWriterFlavor ; bool is64Bit = Triple . getArch ( ) == Triple :: x86_64 ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; PCSymbol = <STR_LIT> ; SupportsDebugInformation = true ; DwarfUsesInlineInfoSection = true ; ExceptionsType = ExceptionHandling :: Dwarf ; AbsoluteEHSectionOffsets =


<s> case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT>


<s> if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( isParsingInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) return <STR_LIT> ( Disp , Start , End ) ; StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode ( )

, ErrMsg ) ) return ErrorOperand ( Start , ErrMsg ) ;


<s> uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; return std :: make_pair ( domain , domain && lookup ( MI -> getOpcode

( ) , domain ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> if ( ! SetHiMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t imm = SetHiMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( imm ) ) return false ; imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT>


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> )


<s> MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> getOperand ( <NUM_LIT> ) . setIsKill


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . c [ ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) &


<s> return SelectAddrModeIndexed ( N , <NUM_LIT> , Base , OffImm


<s> return ( ( vec_uchar16 ) ( si_absdb ( ( qword ) ( a ) , ( qword ) (


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> bool vax_maybe_split_dimode_move ( rtx * operands ) { return ( TARGET_QMATH && ( ! MEM_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PRE_DEC || GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == POST_INC || ! illegal_addsub_di_memory_operand ( operands [ <NUM_LIT> ] , DImode ) ) && ( ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && (

unsigned HOST_WIDE_INT ) INTVAL ( operands [ <NUM_LIT> ] ) >= <NUM_LIT> ) || GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE ) ) ;


<s> SDLoc DL ( Src2 ) ; if ( auto * Op2 = dyn_cast < ConstantSDNode > ( Src2 ) ) { int64_t Value = ( - Op2 -> getAPIntValue ( ) ) . getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Value ) || Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getConstant ( Value , DL , MemVT ) ; } else if ( Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getNode ( <STR_LIT> , DL , MemVT , DAG . getConstant ( <NUM_LIT> , DL , MemVT ) , Src2 ) ; if ( NegSrc2 . getNode ( ) ) return DAG . getAtomic ( <STR_LIT> , DL , MemVT , Node -> getChain ( ) , Node -> getBasePtr ( ) , NegSrc2 , Node -> getMemOperand ( ) , Node -> getOrdering ( ) , Node -> getSynchScope ( ) ) ; return Op


<s> EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) ) return false ; return true


<s> assert ( <STR_LIT> ( MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ) != <STR_LIT> && <STR_LIT> ) ; printAM3PreOrOffsetIndexOp ( MI , Op ,


<s> unsigned <ISA_LIT>CodeEmitter :: getLO16Encoding ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ) ; MCE . addRelocation ( GetRelocation ( MO , <STR_LIT>


<s> break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( ) - <NUM_LIT> ) ) ; if ( ! LastCorrectlyNumberedBB ) LastCorrectlyNumberedBB = & MBB ; } if ( LastCorrectlyNumberedBB ) MF -> RenumberBlocks (


<s> unsigned <ISA_LIT>ABIInfo :: GetFramePtr ( ) const { return <STR_LIT>


<s> int Lane = ( VectorWidth / <NUM_LIT> > <NUM_LIT> ) ? VectorWidth / <NUM_LIT> : <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { IndexGroup [ ( Index * <NUM_LIT> ) % ( VF / Lane


<s> const MCOperand & ScaleOp = MI -> getOperand ( OpNum ) ; O << '#' << ( <NUM_LIT> - ScaleOp .


<s> if ( GET_MODE ( addr ) == Pmode || GET_MODE ( addr ) == VOIDmode ) { reg = copy_addr_to_reg ( addr ) ; REG_POINTER ( reg ) = <NUM_LIT> ; return reg ; } else { gcc_assert ( GET_MODE ( addr ) == DImode && Pmode == SImode ) ; reg = copy_to_mode_reg ( DImode , addr ) ; REG_POINTER ( reg ) =


<s> static unsigned int sh_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( XD_REGISTER_P ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , <NUM_LIT> * UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode )


<s> unsigned Register = QQQQPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler ::


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get

( TargetOpcode :: IMPLICIT_DEF ) , Out ) ;


<s> void <ISA_LIT>FunctionInfo :: createEhDataRegsFI ( ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { const TargetRegisterClass * RC = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & <STR_LIT> : & <STR_LIT> ; EhDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( )


<s> static bool is16BitMemOperand ( const MCInst & MI , unsigned Op , const MCSubtargetInfo & STI ) { const MCOperand & BaseReg = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & Disp = MI . getOperand ( Op


<s> insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current )


<s> MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset FeatureBits = STI . getFeatureBits ( ) ; FeatureBits &= ~ <ISA_LIT>AssemblerOptions :: AllArchRelatedMask ; STI . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( ArchFeature ) ) ) ; AssemblerOptions . back ( ) -> setFeatures ( STI . getFeatureBits


<s> bool IsOnlyPredicatedOn ( MachineInstr * MI ) const { return IsPredicatedOn ( MI ) && VPST -> Predicates . size


<s> static DecodeStatus DecodeJumpTargetXMM ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( JumpOffset


<s> value0 = expand_normal ( arg0 ) ; create_input_operand ( & ops [ <NUM_LIT> ] , value0 , TYPE_MODE ( TREE_TYPE ( arg0 ) ) ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) error ( <STR_LIT> ) ; return target


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getSizeInBits ( ) > <NUM_LIT> ) return TypeSplitVector ; if ( VT . getScalarSizeInBits ( )

== <NUM_LIT> ) return TypePromoteInteger ;


<s> const char * getPassName ( ) const override { return AARCH64_ADVSIMD_NAME


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> auto * Def = RDA -> getReachingMIDef ( MI , <STR_LIT> ) ; if ( ! Def ) return nullptr ; if ( ! ( NewOpcode = VCMPOpcodeToVPT ( Def -> getOpcode ( ) ) ) ) return nullptr ; if ( ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg (


<s> static opt_scalar_float_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == <NUM_LIT> ) { if ( arm_fp16_format == ARM_FP16_FORMAT_IEEE


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; addExpr ( Inst , Memory .


<s> EVT IntTy = Ty . changeVectorElementTypeToInteger ( ) ; EVT ExtIntTy = getPackedSVEVectorVT ( IntTy . getVectorElementCount ( ) ) ; if ( ExtIntTy . getVectorElementType ( ) . getScalarSizeInBits ( ) < IntTy . getVectorElementType ( ) . getScalarSizeInBits ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue LHS = DAG . getAnyExtOrTrunc ( DAG . getBitcast ( IntTy , N -> getOperand ( <NUM_LIT> )


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: printAddrMode3OffsetOperand ( const MachineInstr * MI , int Op , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT>


<s> for ( MachineBasicBlock * S : MBB -> predecessors ( ) ) if ( S == PrevBB && ! TII -> analyzeBranch ( * PrevBB , TBB , FBB , Cond ) && ! TBB && ! FBB ) return S ; return nullptr


<s> return Kind == k_VectorList && ! VectorList .


<s> switch ( Value ) { case FpABIKind :: XX : return <STR_LIT> ; case FpABIKind :: S32 : return <STR_LIT> ; case FpABIKind :: S64 : return


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr ,


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum ,


<s> return GET_CODE ( x ) == MOD && GET_MODE ( x


<s> MachineBasicBlock * CmpParent = CmpInstr . getParent ( ) ; if ( MI . getParent ( ) != CmpParent ) return None ; if ( areCFlagsAliveInSuccessors ( CmpParent ) ) return None ; UsedNZCV NZCVUsedAfterCmp ; for ( MachineInstr & Instr : instructionsWithoutDebug ( std :: next ( CmpInstr . getIterator ( ) ) , CmpParent -> instr_end ( ) ) ) { if ( Instr . readsRegister ( <STR_LIT> , & TRI ) ) { <STR_LIT> CC = findCondCodeUsedByInstr ( Instr ) ; if ( CC == <STR_LIT> ) return None ; NZCVUsedAfterCmp |= getUsedNZCV ( CC ) ; if ( CCUseInstrs ) CCUseInstrs -> push_back ( & Instr ) ; } if ( Instr . modifiesRegister ( <STR_LIT> , & TRI ) )


<s> } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( ) ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) & <NUM_LIT> ) << idx ; HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getSelect ( dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else Imm = DAG . getUNDEF ( VT ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) DstVec = DAG . getBitcast ( VT , Imm ) ; else { SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } for ( unsigned i = <NUM_LIT> , e = NonConstIdx . size ( ) ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target


<s> vst2_u8 ( uint8_t * __a , uint8x8x2_t val ) { __builtin_aarch64_simd_oi __o ; uint8x16x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st2v8qi ( ( __builtin_aarch64_simd_qi *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR16RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeFPR8RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , offset , Addr , Fail , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences


<s> if ( Kind == k_RegisterIndex && RegIdx . Index == <NUM_LIT> && RegIdx . Kind & RegKind_GPR ) return getGPR32Reg ( ) ; assert ( Kind == k_PhysRegister && <STR_LIT> ) ; return PhysReg


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI ->


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT> ) return


<s> BICInst . setOpcode ( <STR_LIT> ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; BICInst . addOperand ( MCOperand :: CreateImm (


<s> unsigned <ISA_LIT>CodeEmitter :: encodeVFPRm ( const MachineInstr & MI , unsigned OpIdx ) const { unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegM ) ; RegM = II -> getRegisterInfo (


<s> } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; auto Offset = ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) - <NUM_LIT> ; if ( Offset ) { O <<


<s> } else { MMO = cast < LoadSDNode > ( StackSlot ) -> getMemOperand ( ) ; StackSlot = StackSlot . getOperand ( <NUM_LIT> ) ; } SDValue Ops [ ] = { Chain , StackSlot } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , Ops , SrcVT , MMO ) ; if ( useSSE ) { Chain = Result . getValue ( <NUM_LIT> ) ; SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( SSFISize , SSFISize , false ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Tys = DAG . getVTList ( <STR_LIT>


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF -> getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return BB ; MachineBasicBlock * RestoreMBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs ( BB )


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get (

TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> addPass ( create<ISA_LIT>SetflagAluCombinerPass


<s> static bool ix86_cannot_force_const_mem ( rtx


<s> return isSignOrZeroExtended ( MI , false ,


<s> unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg

( Op2 , Op2IsKill * RegState :: Kill ) ) ;


<s> if ( SatWidth != DstWidth ) return SDValue ( ) ; if ( SrcVT == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , SrcVal ) , Op . getOperand ( <NUM_LIT> ) ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) ) && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return Op ; return SDValue (


<s> MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer


<s> switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT>


<s> V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; V2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT>

) , V1 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ;


<s> if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( hasFP ( MF ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( PreferFP || MFI -> hasVarSizedObjects ( ) || FPOffset >= <NUM_LIT> || ( FPOffset >= - <NUM_LIT> && Offset > - FPOffset ) ) UseFP = true ; } } if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else { FrameReg = <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> SmallVector < SDValue , <STR_LIT> > ResidueOps ; bool FoundOne = false ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { SDValue Op = BVN -> getOperand ( I ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { unsigned Elem = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! GS . add ( Op . getOperand ( <NUM_LIT> ) , Elem ) ) return SDValue ( ) ; FoundOne = true ; } else if ( Op . isUndef ( ) ) { GS . addUndef ( ) ; } else { if ( ! GS . add ( SDValue ( ) , ResidueOps . size ( ) ) ) return SDValue ( ) ; ResidueOps . push_back ( BVN -> getOperand ( I ) ) ; } } if ( ! FoundOne ) return SDValue ( ) ; if ( ! ResidueOps . empty ( ) ) { while ( ResidueOps . size ( ) < NumElements ) ResidueOps . push_back ( DAG

. getUNDEF ( ResidueOps [ <NUM_LIT> ] . getValueType ( ) ) ) ;


<s> case <STR_LIT> : emitPseudoInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitDataProcessingInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitSaturateInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI


<s> static DecodeStatus DecodeGR32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT>


<s> unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register


<s> case ELF :: R_MIPS_GOT16 : case ELF :: R_MIPS_26 : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> if ( l >= NumLanes / <NUM_LIT> ) LaneMask += NumLanes ; for ( unsigned i = <NUM_LIT> ; i != NumElementsInLane ; ++ i ) ShuffleMask

. push_back ( LaneMask * NumElementsInLane + i ) ;


<s> case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , std :: move ( Offset ) ) ) ; return MatchOperand_Success ; case AsmToken :: LParen : Parser . Lex ( ) ; break ; } const MCExpr * IndexValue = nullptr ; unsigned IndexReg = <NUM_LIT> ; switch ( getLexer ( ) . getKind ( ) ) { default : if ( ParseRegister ( IndexReg , S , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : if ( getParser ( ) . parseExpression ( IndexValue , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Comma : IndexValue = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; break ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: RParen : Parser . Lex ( ) ; Operands . push_back ( IndexValue ? <STR_LIT> ( IndexValue , std :: move ( Offset ) ) : <STR_LIT> ( IndexReg , std :: move ( Offset ) ) ) ; return MatchOperand_Success ; case AsmToken :: Comma : Parser . Lex ( ) ; break ; } unsigned BaseReg = <NUM_LIT> ; if ( ParseRegister ( BaseReg , S , E ) ) return MatchOperand_ParseFail ; if ( ! Parser . getTok ( ) . is ( AsmToken :: RParen ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; Operands . push_back ( IndexValue ? <STR_LIT> ( BaseReg , IndexValue , std :: move ( Offset ) ) : <STR_LIT> (

BaseReg , IndexReg , std :: move ( Offset ) ) ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( mm ) ,


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( * T ,


<s> const class xlogue_layout & xlogue_layout :: get_instance ( ) { enum xlogue_stub_sets stub_set ; bool aligned_plus_8 = cfun ->


<s> pandn_sw ( int32x2_t s , int32x2_t t ) { return __builtin_loongson_pandn_sw ( s , t


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ClearMask . push_back ( i == IdxVal ? i + NumElts : i ) ; SDValue ZeroVector = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getVectorShuffle ( VT , dl , N0 , ZeroVector , ClearMask ) ; } if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget . hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget . hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumEltsIn128 ) ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) { Opc =


<s> if ( CONST_INT_P ( x ) && mips_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( mips_symbolic_constant_p ( base , SYMBOL_CONTEXT_LEA , & type ) ) { if ( mips_use_pcrel_pool_p [ ( int ) type ] ) return false ; if ( SMALL_INT ( offset ) && mips_symbol_insns ( type ,

MAX_MACHINE_MODE ) > <NUM_LIT> ) return true ;


<s> virtual const MCObjectFormat & getObjectFormat (


<s> return ( uint32x4_t ) __builtin_aarch64_addhn2v2di ( ( int32x2_t ) __a , ( int64x2_t )


<s> bool enableMachineSchedDefaultSched ( ) const override { return true


<s> getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } return


<s> LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT (


<s> return ( GET_CODE ( op ) == CONST_INT && INTVAL ( op ) >= low && INTVAL ( op )

<= high && ( INTVAL ( op ) & mask ) == <NUM_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree


<s> bool mask_low_and_shift_p ( machine_mode mode , rtx mask , rtx shift , int maxlen ) { return IN_RANGE ( mask_low_and_shift_len ( mode , mask , shift ) , <NUM_LIT>


<s> if ( ! Bundle . Mask ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } assert ( Bundle . isFixed ( ) && <STR_LIT> ) ; for ( unsigned i = Bundle . FixCount ; i > <NUM_LIT> ; -- i ) { DEBUG ( dbgs ( ) << <STR_LIT> << ( i - <NUM_LIT> ) << <STR_LIT> << unsigned ( Bundle . FixStack [ i - <NUM_LIT> ] ) << '\n' ) ; pushReg ( Bundle . FixStack [ i - <NUM_LIT> ] ) ; } unsigned Mask = calcLiveInMask ( MBB , true ) ; adjustLiveRegs ( Mask , MBB ->