<s> if ( GET_CODE ( op1 ) == PC || GET_CODE ( op2 ) == PC ) { if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) return true ; else { if ( cmpcode == NE || cmpcode == EQ ) { if ( comparator == const0_rtx ) { if ( GET_CODE ( inner ) == ZERO_EXTRACT ) * cost += rtx_cost ( XEXP ( inner , <NUM_LIT> ) , VOIDmode , ZERO_EXTRACT , <NUM_LIT> , speed ) ; else * cost += rtx_cost ( inner , VOIDmode , cmpcode , <NUM_LIT> , speed ) ; return true ; } } else if ( cmpcode == LT || cmpcode == GE ) { if ( comparator == const0_rtx ) return true ; } } } else if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) { if ( GET_CODE ( op1 ) == COMPARE


<s> bool hasMPExtension ( ) const { return


<s> return <STR_LIT> ; case LE : return <STR_LIT> ; case GT : return <STR_LIT> ; case GE : return <STR_LIT> ; case LTU : return <STR_LIT> ; case LEU : return <STR_LIT> ; case GTU : return <STR_LIT> ; case GEU : return <STR_LIT>


<s> bool mep_epilogue_uses ( int regno ) { if ( regno == LP_REGNO && ( profile_arc_flag > <NUM_LIT> || profile_flag > <NUM_LIT> ) ) return true ; return ( reload_completed && mep_interrupt_saved_reg ( regno


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataRel ( ) && IsGlobalInSmallSection (

GV , TM , Kind ) ) return SmallDataSection ;


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default


<s> ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment ( ) ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple


<s> static DecodeStatus DecodeFGRCCRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand ::


<s> static DecodeStatus DecodeSimm23Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn


<s> MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; for ( auto Candidate : <STR_LIT> ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == Candidate ) { IsDef =


<s> uint64_t <ISA_LIT>FrameLowering :: calculateMaxStackAlign ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t MaxAlign = MFI . getMaxAlignment


<s> bool isInRequiredFeatures ( FeatureBitset TestFeatures ) const


<s> MCAsmParser & Parser = getParser ( ) ; Code16GCC = false ; if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is16BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . emitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; Code16GCC = true ; if ( ! is16BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . emitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . emitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is64BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . emitAssemblerFlag ( MCAF_Code64 ) ; } } else


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags &


<s> Triple TheTriple ( TT ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; return new ELF<ISA_LIT>AsmBackend ( T , TheTriple . getOS (


<s> return __builtin_aarch64_crypto_aesimcv16qi_uu ( data


<s> return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } SMLoc FPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int FPReg = tryParseRegister ( ) ; if ( FPReg == - <NUM_LIT> ) { Error ( FPRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( SPReg == - <NUM_LIT> ) { Error ( SPRegLoc , <STR_LIT> ) ; return


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo >


<s> static section * pa_function_section ( tree decl , enum node_frequency freq , bool startup , bool exit ) { if ( ! targetm_common . have_named_sections ) return text_section ; if ( decl && DECL_SECTION_NAME ( decl ) == NULL && DECL_CONTEXT ( decl ) != NULL_TREE && TREE_CODE ( DECL_CONTEXT ( decl ) ) == FUNCTION_DECL && DECL_SECTION_NAME ( DECL_CONTEXT ( decl ) ) == NULL ) return function_section ( DECL_CONTEXT ( decl ) ) ; return default_function_section ( decl , freq , startup


<s> bool hasBaseOrIndexReg ( ) const { return IndexReg . getNode ( ) != <NUM_LIT> ||


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) .

getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets

[ SpillOffsetTable [ I ] . Reg ] = SpillOffsetTable [ I ] . Offset ;


<s> if ( STI . hasFP<ISA_LIT>v8 ( ) ) { if ( STI . hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( STI . hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , STI . hasV8_1aOps ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP3 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( ! STI . hasVFP2 ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . allowsUnalignedMem ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT>


<s> HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ; UseNaClTrap =


<s> struct simd_immediate_info info ; bool is_valid = aarch64_simd_valid_immediate ( const_unspec , & info ) ; gcc_assert ( is_valid && info . insn == simd_immediate_info :: PTRUE ) ; char element_char = sizetochar ( GET_MODE_BITSIZE ( info . elt_mode ) ) ; snprintf ( templ , sizeof ( templ ) , <STR_LIT> , element_char ,

svpattern_token ( info . u . pattern ) ) ;


<s> void getAnalysisUsage ( AnalysisUsage &


<s> return ( __m512i ) __builtin_ia32_vcvtph2dq512_mask_round ( __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16

) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> rtx result = target ; HOST_WIDE_INT val ; if ( ! REG_P ( op0 ) || REGNO ( op0 ) != T_REG || ! CONST_INT_P ( op1 ) ) return false ; if ( ! REG_P ( result ) ) result = gen_reg_rtx ( SImode ) ; val = INTVAL ( op1 ) ; if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movt ( result , get_t_reg_rtx ( ) ) ) ; else if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movnegt ( result , get_t_reg_rtx ( ) ) ) ; else if ( code == EQ || code == NE ) emit_insn ( gen_move_insn ( result , GEN_INT ( code == NE ) ) ) ; else return false ; if ( result != target ) emit_move_insn ( target


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter ) ; if ( RelaxAll ) S -> getAssembler ( )


<s> void addVectorList128Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; static unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs


<s> if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree rhs = gimple_assign_rhs1 ( stmt_info -> stmt ) ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( rhs ) ; if ( ! INTEGRAL_TYPE_P ( lhs_type ) || ! INTEGRAL_TYPE_P ( rhs_type ) || TYPE_PRECISION ( lhs_type ) <= TYPE_PRECISION ( rhs_type ) ) return false ; stmt_vec_info def_stmt_info = stmt_info -> vinfo -> lookup_def ( rhs ) ; return ( def_stmt_info && STMT_VINFO_DATA_REF ( def_stmt_info ) && DR_IS_READ ( STMT_VINFO_DATA_REF


<s> } if ( opts -> x_arm_tune_string ) { arm_selected_tune = arm_parse_cpu_option_name ( all_cores , <STR_LIT> , opts -> x_arm_tune_string ) ; tune_opts = strchr ( opts -> x_arm_tune_string , '+' ) ; } if ( arm_selected_arch ) { arm_initialize_isa ( target -> isa , arm_selected_arch -> common . isa_bits ) ; arm_parse_option_features ( target -> isa , & arm_selected_arch -> common , arch_opts ) ; if ( arm_selected_cpu ) { auto_sbitmap cpu_isa ( isa_num_bits ) ; auto_sbitmap isa_delta ( isa_num_bits ) ; arm_initialize_isa ( cpu_isa , arm_selected_cpu -> common . isa_bits ) ; arm_parse_option_features ( cpu_isa , & arm_selected_cpu -> common , cpu_opts ) ; bitmap_xor ( isa_delta , cpu_isa , target -> isa ) ; bitmap_and_compl ( isa_delta , isa_delta , isa_quirkbits ) ; if ( opts -> x_arm_fpu_index != TARGET_FPU_auto || arm_float_abi == ARM_FLOAT_ABI_SOFT ) bitmap_and_compl ( isa_delta , isa_delta , isa_all_fpbits ) ; if ( ! bitmap_empty_p ( isa_delta ) ) { if ( warn_compatible ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , opts -> x_arm_cpu_string , opts -> x_arm_arch_string ) ; if ( ! arm_selected_tune ) arm_selected_tune = arm_selected_cpu ; arm_selected_cpu = all_cores + arm_selected_arch -> tune_id ; target -> arch_name = arm_selected_arch -> common . name ; } else { arm_selected_arch = all_architectures + arm_selected_cpu -> arch ; target -> core_name = arm_selected_cpu -> common . name ; bitmap_copy ( target -> isa , cpu_isa ) ; } } else { arm_selected_cpu = all_cores + arm_selected_arch -> tune_id ; target -> arch_name = arm_selected_arch -> common . name ; } } else if ( arm_selected_cpu ) { target -> core_name = arm_selected_cpu -> common . name ; arm_initialize_isa ( target -> isa , arm_selected_cpu -> common . isa_bits ) ; arm_parse_option_features ( target -> isa , & arm_selected_cpu -> common , cpu_opts ) ; arm_selected_arch = all_architectures + arm_selected_cpu -> arch ; } else { const cpu_option * sel ; auto_sbitmap sought_isa ( isa_num_bits ) ; bitmap_clear ( sought_isa ) ; auto_sbitmap default_isa ( isa_num_bits )


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveFPLR ( int Offset


<s> const TargetRegisterClass * RC = static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & <STR_LIT> : & <STR_LIT> ; return GlobalBaseReg = MF . getRegInfo ( ) .


<s> assert ( Zeros < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CRRegs [


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( )


<s> void rs6000_live_on_entry ( bitmap regs ) { if ( flag_split_stack ) bitmap_set_bit ( regs , <NUM_LIT>


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetAt (


<s> if ( C . front ( ) != '{' || C . back ( ) != '}' ) return std :: make_pair ( false , false ) ; StringRef :: const_iterator I , B = C . begin ( ) + <NUM_LIT> , E = C . end ( ) - <NUM_LIT> ; I = std :: find_if ( B , E , std :: ptr_fun ( isdigit ) ) ; Prefix . assign ( B , I - B ) ; if ( I == E ) return std ::


<s> break ; default : type = DW_EH_PE_sdata8 ; break ; } return ( global ? DW_EH_PE_indirect : <NUM_LIT> )


__v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> <<


<s> assert ( ( ElSize == <NUM_LIT> || ElSize == <NUM_LIT> || ElSize == <NUM_LIT> || ElSize == <NUM_LIT> ) && <STR_LIT> ) ; APInt UndefElts ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = Width / ElSize ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } int Index = RawMask [ i ] & ( NumElts - <NUM_LIT> ) ; ShuffleMask . push_back (


<s> } if ( CC == CallingConv :: <ISA_LIT>_FastCall ) return CC_<ISA_LIT>_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_<ISA_LIT>_32_FastCC ; else return


<s> assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT>


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; return X


<s> static bool isVUZPMask ( const SmallVectorImpl < int > & M , EVT VT , unsigned & WhichResult ) { unsigned NumElts = VT . getVectorNumElements ( ) ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i !=


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister (


<s> return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case

( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info


<s> return __aarch64_vdupq_laneq_p8 ( __a ,


<s> machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , <NUM_LIT> ) ) ; memsi_addr = loongarch_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - <NUM_LIT> ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = loongarch_force_binary ( Pmode , AND , orig_addr , GEN_INT ( <NUM_LIT> ) ) ; loongarch_emit_binary ( ASHIFT , shift , shift , GEN_INT ( <NUM_LIT> ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = loongarch_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval !=


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; break ; case <STR_LIT> : * AddrIdx = <NUM_LIT> ; break ; } switch ( MI . getOperand ( * AddrIdx ) . getReg ( ) ) { default : break ; case


<s> SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl


<s> switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinCFISaveSP ( unsigned Reg


<s> bool <ISA_LIT>LegalizerInfo :: legalizeIntrinsic ( LegalizerHelper & Helper , MachineInstr & MI )


<s> return static_cast < const <ISA_LIT>TargetMachine & > (


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getFixedPointScaleOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> - MO .


<s> } else if ( Use -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: use_iterator UI = Use -> use_begin ( ) , UE = Use -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; Copies [ UI . getUse ( ) . getResNo ( ) ] = * UI ; ++ NumCopies ; } } else if ( Use -> getOpcode ( ) == <STR_LIT> ) { if ( ! Use -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; Use = * Use -> use_begin ( ) ; if ( Use -> getOpcode ( ) != <STR_LIT> || ! Use -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; Copies [ NumCopies ++ ] = Use ; }


<s>
void
<ISA_LIT>ATTAsmPrinter
::
printPICJumpTableEntry
(
const
MachineJumpTableInfo
*
MJTI
,
const
MachineBasicBlock
*
MBB
,
unsigned
uid
)
const
{
const
char
*
JTEntryDirective
=
MJTI
->
getEntrySize
(
)
==
<NUM_LIT>
TAI
->
getData32bitsDirective
(
)
:
TAI
->
getData64bitsDirective
(
)
;
O
<<
JTEntryDirective
<<
' '
;
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
{
if
(
Subtarget
->
isPICStyleRIPRel
(
)
||
Subtarget
->
isPICStyleStub
(
)
)
{
O
<<
TAI
->
getPrivateGlobalPrefix
(
)
<<
getFunctionNumber
(
)
<<
'_'
<<
uid
<<
<STR_LIT>
<<
MBB
->
getNumber
(
)
;
}
else
if
(
Subtarget
->
isPICStyleGOT
(
)
)
{
printBasicBlockLabel
(
MBB
,
false
,
false
,
false


<s> enum rtx_code minmax_code ( rtx x ) { enum rtx_code code = GET_CODE ( x ) ; switch ( code ) { case SMAX : return GE ; case SMIN : return LE ; case UMIN : return LEU ; case UMAX : return GEU


<s> static unsigned int loongarch_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( FCC_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode )


<s> if ( VT . isInteger ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 . getOperand ( <NUM_LIT> ) ) if ( ConstantSDNode * Y1C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) if ( Y1C -> getAPIntValue ( ) == VT . getSizeInBits ( ) - <NUM_LIT> ) { SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , VT ) , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { N0 . getOperand ( <NUM_LIT> ) , Neg , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Ops , array_lengthof ( Ops ) ) ; } return SDValue ( )


<s> return __builtin_mve_vcvtbq_m_f32_f16v4sf ( __arm_vuninitializedq_f32 ( ) ,


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( getTheARM64Target (


<s> unsigned CCValid = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent ( ) ; return JoinMBB


<s> return __builtin_mve_vqnegq_sv16qi ( __a )


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . getRelocationModel ( ) == Reloc :: PIC_ ) report_fatal_error


<s> <STR_LIT> <ISA_LIT>CC ; MachineInstr * ConjMI = emitConjunction ( SelI . getCondReg ( ) , <ISA_LIT>CC , MIB ) ; if ( ! ConjMI ) return false ; emitSelect ( SelI . getReg ( <NUM_LIT> ) , SelI . getTrueReg ( ) , SelI . getFalseReg ( ) , <ISA_LIT>CC , MIB ) ; SelI . eraseFromParent ( )


<s> unsigned <ISA_LIT>TargetLowering :: getGlobalWrapperKind ( const GlobalValue * GV , const unsigned char OpFlags ) const { if ( GV && GV -> isAbsoluteSymbolRef ( ) ) return <STR_LIT> ; CodeModel :: Model M = getTargetMachine (


<s> void WinEHStatePass :: addCXXStateStores ( Function & F , WinEHFuncInfo & FuncInfo ) { calculateWinCXXEHStateNumbers ( & F , FuncInfo ) ; addStateStoresToFunclet ( RegNode , FuncInfo , F , - <NUM_LIT> ) ; int RegNodeEscapeIndex = escapeRegNode ( F


<s> return getTM < <ISA_LIT>TargetMachine


<s> MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; InstrumentMOVSBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , AccessSize , Ctx , Out ) ; EmitLabel ( Out , DoneSym ) ; RestoreFlags ( Out


<s> void printf80mem ( const MachineInstr * MI , unsigned OpNo


<s> emit_insn ( gen_add2_insn ( countreg , GEN_INT ( -


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> if ( ! can_create_pseudo_p ( ) ) { gcc_assert ( target ) ; return gen_lowpart ( mode , target )


<s> if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ; return false


<s> unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , Flags , Offset

, MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;


<s> void <ISA_LIT>MCCodeEmitter :: expandNEG ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst ; uint32_t Binary ; unsigned Size = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst ,


<s> static DecodeStatus DecodeGPRMM16RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address ,


<s> if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup , Value , nullptr ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= DataSize && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes


<s> SDValue SllX = DAG . getNode ( <STR_LIT> , DL , TyX , X , Const1 ) ; SDValue SrlX = DAG . getNode ( <STR_LIT> , DL , TyX , SllX , Const1 ) ; SDValue SrlY = DAG . getNode ( <STR_LIT> , DL , TyY , Y , DAG . getConstant ( WidthY - <NUM_LIT> , <STR_LIT> ) ) ; if ( WidthX > WidthY ) SrlY = DAG . getNode ( <STR_LIT> , DL , TyX , SrlY ) ; else if ( WidthY > WidthX ) SrlY = DAG . getNode ( <STR_LIT> , DL , TyX , SrlY ) ; SDValue SllY = DAG . getNode ( <STR_LIT> , DL , TyX , SrlY , DAG . getConstant ( WidthX - <NUM_LIT> , <STR_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister ; <STR_LIT> ( ) . fromString ( getSysReg ( ) , IsKnownRegister ) ; return IsKnownRegister


<s> static DecodeStatus decodeU8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst


<s> if ( splitBitmaskImm ( Imm , RegSize , Imm0 , Imm1 ) ) return std :: make_pair ( Opc , Opc ) ; return None ; } , [ & TII = TII ] ( MachineInstr & MI , OpcodePair Opcode , unsigned Imm0 , unsigned Imm1 , Register SrcReg , Register NewTmpReg , Register NewDstReg ) { DebugLoc DL = MI .


<s> static SDValue lowerV8I64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_loadu_epi64 ( void const * __P ) { return ( __m256i ) ( * (


<s> auto Mapper = <STR_LIT> ( ) ; std :: string Name = Mapper . toString ( Val ,


<s> return ( t == float128_type_node || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t == long_double_type_node


<s> static MCStreamer * createMachOStreamer ( MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && TAB , std :: unique_ptr < MCObjectWriter > && OW

, std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll , bool DWARFMustBeAtTheEnd ) {


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int idx = SVOp -> getMaskElt ( i ) ; if ( idx < <NUM_LIT> ) MaskVec . push_back ( idx ) ; else if ( idx < ( int ) NumElems ) MaskVec .


<s> case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : { ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! CST ) return ; unsigned Value = CST -> getZExtValue ( ) ; switch ( Letter ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'I' : if ( ( short ) Value == ( int ) Value ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'J' : case 'L' : if ( ( short ) Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case


<s> if ( auto * C = dyn_cast < ConstantInt > ( SingleUser -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getBitWidth ( ) <= <NUM_LIT> && ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) || isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) ) return AddressingMode ( false , false ) ; } else if ( isa < StoreInst > ( SingleUser ) ) return getLoadStoreAddrMode ( HasVector , I -> getType ( ) ) ; } } else if ( auto * StoreI = dyn_cast < StoreInst > ( I ) ) { if ( auto * LoadI = dyn_cast < LoadInst > ( StoreI -> getValueOperand ( ) ) ) if ( LoadI -> hasOneUse ( ) && LoadI -> getParent ( ) == I -> getParent ( ) ) return getLoadStoreAddrMode ( HasVector , LoadI -> getType ( ) ) ; } if ( HasVector && ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ) { Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I ->


<s> unsigned RotAmt = countTrailingZeros ( V ) ; return ( <NUM_LIT> - RotAmt


<s> return FS ; case DFmode : return FT ; default : return I64


<s> bool Is64Bit = TT . isArch64Bit ( ) ; if ( CPU . empty ( ) ) CPU = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { GRLenVT = <STR_LIT> ; GRLen = <NUM_LIT> ; } TargetABI = Is64Bit ? <STR_LIT>


<s> ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordLoadArgsFI ( FI , - ( ArgSize + ( FirstStackArgLoc + VA . getLocMemOffset ( ) ) ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Copy , Chain ) ; } if ( ( isVarArg ) && ( Subtarget -> isABI_O32 ( ) && ArgRegEnd ) ) { if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getRegister ( StackReg , getPointerTy ( ) ) ; TargetRegisterClass * RC = <STR_LIT> ; unsigned StackLoc = ArgLocs . size ( ) - <NUM_LIT> ; for ( ++ ArgRegEnd ; ArgRegEnd <= <STR_LIT> ; ++ ArgRegEnd , ++ StackLoc ) { unsigned Reg = AddLiveIn ( DAG . getMachineFunction ( ) , ArgRegEnd , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordStoreVarArgsFI ( FI , - ( <NUM_LIT> + ( StackLoc * <NUM_LIT> ) ) ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; OutChains . push_back ( DAG . getStore ( Chain , dl , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; if ( ! <ISA_LIT>FI -> getVarArgsFrameIndex ( ) ) <ISA_LIT>FI -> setVarArgsFrameIndex


<s> static machine_mode counter_mode ( rtx count_exp ) { if ( GET_MODE ( count_exp ) != VOIDmode ) return GET_MODE ( count_exp ) ; if ( ! CONST_INT_P ( count_exp ) ) return Pmode ; if ( TARGET_64BIT && ( INTVAL ( count_exp ) & ~ <NUM_LIT> ) )


<s> tryParseRegisterOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , StringRef Mnemonic ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; int RegNo = - <NUM_LIT> ; if ( ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> && Parser . getTok ( ) . is ( AsmToken :: Integer ) ) { RegNo = Parser . getTok ( ) . getIntVal ( ) ; if ( RegNo == <NUM_LIT> ) RegNo = <STR_LIT> ; } else RegNo = tryParseRegister ( Mnemonic ) ; if ( RegNo == -


<s> case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; UpdateValueMap ( I , ResultReg ) ; } return


<s> if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugInstr ( ) ) ++ I ; if ( I != E ) { unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( * I , NPredReg ) ; if ( NCC == CC || NCC == OCC ) return true ; } return


<s> bool <ISA_LIT>SETargetLowering :: isEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>MachineFunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls )


<s> return ( __m128i ) __builtin_ia32_loaddquqi128_mask ( ( __v16qi * ) __P , ( __v16qi ) _mm_setzero_hi (


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy ) const { return <STR_LIT>


<s> SDValue UNORD , EQ ; UNORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; EQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , UNORD , EQ ) ; } else if ( SetCCOpcode == <STR_LIT> ) { SDValue ORD , NEQ ; ORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; NEQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } unsigned Opc = <NUM_LIT> , EQOpc = <NUM_LIT> , GTOpc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = EQOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; Invert = true ; break ; case <STR_LIT> : Swap = true


<s> char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = stack_pointer_rtx ; xops [ <NUM_LIT> ] = GEN_INT ( get_probe_interval ( ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT>


<s> static DecodeStatus decodeBDVAddr64Disp12Operand ( MCInst & Inst , uint64_t Field , uint64_t Address


<s> void addNEONi16splatOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast <


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQPairNode ( SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant


<s> void <ISA_LIT>InstrInfo :: replaceInstrOperandWithImm ( MachineInstr & MI , unsigned OpNo , int64_t Imm ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; Register InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ; MI . getOperand ( OpNo ) . ChangeToImmediate (


<s> if ( TARGET_64BIT && TARGET_LONG64 ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; strcpy ( tmp , <STR_LIT> ) ; output_asm_insn ( strcat ( tmp , & loop_lab [ <NUM_LIT> ] ) , xops ) ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> ,


<s> if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes (

) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_SaveList ;


<s> HOST_WIDE_INT words , n_gpr , n_fpr ; tree f_gpr , f_fpr , f_ovf , f_sav ; tree gpr , fpr , ovf , sav , t ; if ( ! TARGET_64BIT ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = TREE_CHAIN ( f_gpr ) ; f_ovf = TREE_CHAIN ( f_fpr ) ; f_sav = TREE_CHAIN ( f_ovf ) ; valist = build1 ( INDIRECT_REF , TREE_TYPE ( TREE_TYPE ( valist ) ) , valist ) ; gpr = build ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , valist , f_fpr , NULL_TREE ) ; ovf = build ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , valist , f_ovf , NULL_TREE ) ; sav = build ( COMPONENT_REF , TREE_TYPE ( f_sav ) , valist , f_sav , NULL_TREE ) ; words = current_function_args_info . words ; n_gpr = current_function_args_info . regno ; n_fpr = current_function_args_info . sse_regno ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , ( int ) words , ( int ) n_gpr , ( int ) n_fpr ) ; if ( cfun -> va_list_gpr_size ) { t = build ( MODIFY_EXPR , TREE_TYPE ( gpr ) , gpr , build_int_cst ( NULL_TREE , n_gpr * <NUM_LIT> ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } if ( cfun ->


<s> if ( is_popm ) asm_fprintf ( asm_out_file , <STR_LIT> , reg_names [ REGNO ( first_push ) ] , reg_names [ REGNO ( first_push ) + last_reg ] ) ; else asm_fprintf ( asm_out_file , <STR_LIT> , ( int ) stack_adjust , reg_names [ REGNO ( first_push ) ]


<s> unsigned AlignMask = Alignment - <NUM_LIT> ; const std :: vector < MachineConstantPoolEntry > Constants = CP -> getConstants ( ) ; for ( unsigned i = <NUM_LIT> , e = Constants . size ( ) ; i != e ; ++ i ) { if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && ( Constants [ i ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * CPV = ( <ISA_LIT>ConstantPoolValue * ) Constants [ i ] . Val . MachineCPVal ; <ISA_LIT>ConstantPoolMBB * APMBB = dyn_cast < <ISA_LIT>ConstantPoolMBB > ( CPV ) ; if ( ! APMBB


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( TID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( TID . mayStore ( ) )


<s> Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer ,


<s> rtx rs6000_emit_fp_cror ( rtx_code code , machine_mode mode , rtx x ) { rtx cond [ <NUM_LIT> ] ; int n = <NUM_LIT> ; if ( code == LTGT || code == LE || code == UNLT ) cond [ n ++ ] = gen_rtx_fmt_ee ( LT , mode , x , const0_rtx ) ; if ( code == LTGT || code == GE || code == UNGT ) cond [ n ++ ] = gen_rtx_fmt_ee ( GT , mode , x , const0_rtx ) ; if ( code == LE || code == GE || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( EQ , mode , x , const0_rtx ) ; if ( code == UNLT || code == UNGT || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( UNORDERED , mode , x , const0_rtx ) ; gcc_assert ( n == <NUM_LIT> ) ; rtx cc = gen_reg_rtx ( CCEQmode ) ; rtx logical = gen_rtx_IOR ( mode , cond [ <NUM_LIT> ] , cond [ <NUM_LIT> ] ) ; emit_insn ( gen_cceq_ior_compare ( mode , cc , logical , cond [ <NUM_LIT> ] , x , cond [ <NUM_LIT> ] , x


<s> void print ( raw_ostream & OS , const TargetMachine * TM = <NUM_LIT> ) const { if ( isReg ( ) ) { OS << PrintReg ( getReg ( ) ) ; } if ( isImm (


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; } else { return false ; } } if ( VT == <STR_LIT> ) return false ; if ( Fast ) * Fast = true ; return


<s> unsigned Hint = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder ,


<s> MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( ! isWhileLoopStart ( Terminator ) ) continue ; MachineBasicBlock * WLSTarget = getWhileLoopStartTargetBB ( Terminator ) ; if ( WLSTarget == Predecessor ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> <STR_LIT> ) ; return false ; } } } moveBasicBlock ( Predecessor , LoopExit ) ; return true


<s> <STR_LIT> ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , Res ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = Res ; } case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : StrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; StrOpc =


<s> const <ISA_LIT>ELFDynamic & <ISA_LIT>GNULDBackend ::


<s> } bool SetFlags = RDA -> isSafeToDefRegAt ( MI , MCRegister :: from ( <STR_LIT> ) , Ignore ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg


<s> __vector unsigned long long __p = vec_splats ( * __P ) ; __a [ <NUM_LIT> ] = __p [ <NUM_LIT> ] ; return ( __m128 )


<s> auto & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . hasLSE ( ) && ! Subtarget . outlineAtomics ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; AtomicSDNode * AN = cast < AtomicSDNode > ( Op . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl ,


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value ) != - <NUM_LIT>


<s> MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent (


<s> llvm_unreachable ( <STR_LIT> ) ; } int count = <NUM_LIT> ; for ( int i = MI . getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) count += RegSize ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( MSB , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , <STR_LIT> , Ops64 ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SDLoc ( N ) , <STR_LIT> , SDValue ( BFM , <NUM_LIT> ) , SubReg ) ; return Node ; } SDValue Ops [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , VT ) , CurDAG -> getTargetConstant ( MSB ,


<s> TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM


<s> return BBInfo [ LHS . getNumber ( ) ] . postOffset ( ) < BBInfo [ RHS . getNumber ( ) ] . postOffset ( ) ; } ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPUsers . size ( ) << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) { CPUser & U = CPUsers [ i ] ; unsigned UserOffset = getUserOffset


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & Mtc1Tdd = get ( <STR_LIT> ) ; DebugLoc dl = I ->


<s> bool isVectorRegLo ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle ,


<s> if ( ! cum ) return false ; if ( TARGET_SHCOMPACT ) { cum -> byref = shcompact_byref ( cum , mode ,


<s> MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( <STR_LIT> ) ) return true ; return false


<s> bool InputsAreReverseConsecutive = true ; unsigned ElemSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue FirstInput = N -> getOperand ( <NUM_LIT> ) ; bool IsRoundOfExtLoad = false ; if ( FirstInput . getOpcode ( ) == <STR_LIT> && FirstInput . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = dyn_cast < LoadSDNode > ( FirstInput . getOperand ( <NUM_LIT> ) ) ; IsRoundOfExtLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } if ( ( ! IsRoundOfExtLoad && FirstInput . getOpcode ( ) != <STR_LIT> ) || N -> getNumOperands ( ) == <NUM_LIT> ) return SDValue ( ) ; for ( int i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i < e ; ++ i ) { if ( IsRoundOfExtLoad && N -> getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NextInput = IsRoundOfExtLoad ? N -> getOperand ( i ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i ) ; if ( NextInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue PreviousInput = IsRoundOfExtLoad ? N -> getOperand ( i - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( i - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( PreviousInput ) ; LoadSDNode * LD2 = dyn_cast < LoadSDNode > ( NextInput ) ; if ( IsRoundOfExtLoad && LD2 -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isConsecutiveLS ( LD2 , LD1 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreConsecutiveLoads = false ; if ( ! isConsecutiveLS ( LD1 , LD2 , ElemSize , <NUM_LIT> , DAG ) ) InputsAreReverseConsecutive = false ; if ( ! InputsAreConsecutiveLoads && ! InputsAreReverseConsecutive ) return SDValue ( ) ; } assert ( ! ( InputsAreConsecutiveLoads && InputsAreReverseConsecutive ) && <STR_LIT> ) ; SDValue FirstLoadOp = IsRoundOfExtLoad ? FirstInput . getOperand ( <NUM_LIT> ) : FirstInput ; SDValue LastLoadOp = IsRoundOfExtLoad ? N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) . getOperand ( <NUM_LIT> ) : N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; LoadSDNode * LD1 = dyn_cast < LoadSDNode > ( FirstLoadOp ) ; LoadSDNode * LDL = dyn_cast < LoadSDNode > ( LastLoadOp ) ; if ( InputsAreConsecutiveLoads ) { assert ( LD1 && <STR_LIT> ) ; return DAG . getLoad ( N -> getValueType ( <NUM_LIT> ) , dl , LD1 -> getChain ( ) , LD1 -> getBasePtr ( ) , LD1 -> getPointerInfo ( ) , LD1 -> getAlignment ( ) ) ; } if ( InputsAreReverseConsecutive ) { assert ( LDL && <STR_LIT>


<s> if ( swap ) std :: swap ( op0 , op1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) (


<s> assert ( BroadcastIdx < ( int ) Mask . size ( ) && <STR_LIT> <STR_LIT> <STR_LIT> ) ; for ( ; ; ) { switch ( V . getOpcode ( ) ) { case <STR_LIT> : { int OperandSize = Mask . size ( ) / V . getNumOperands ( ) ; V = V . getOperand ( BroadcastIdx / OperandSize ) ; BroadcastIdx %= OperandSize ; continue ; } case <STR_LIT> : { SDValue VOuter = V . getOperand ( <NUM_LIT> ) , VInner = V . getOperand ( <NUM_LIT> ) ; auto ConstantIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstantIdx ) break ; int BeginIdx = ( int ) ConstantIdx -> getZExtValue ( ) ; int EndIdx = BeginIdx + ( int ) VInner . getSimpleValueType ( ) . getVectorNumElements ( ) ; if ( BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx ) { BroadcastIdx -= BeginIdx ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } if ( V . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast ( DL , VT , V . getOperand ( <NUM_LIT> ) , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; if ( V . getOpcode ( ) == <STR_LIT> || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! Subtarget -> hasAVX2 ( ) && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( MayFoldLoad ( V ) && ! cast < LoadSDNode > ( V ) -> isVolatile ( ) ) { LoadSDNode * Ld = cast < LoadSDNode > ( V ) ; SDValue BaseAddr = Ld -> getOperand ( <NUM_LIT> ) ; EVT AddrVT = BaseAddr . getValueType


<s> assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load

. getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ;


<s> return DecodeMem ( Inst , insn , Address

, Decoder , false , DecodeDFPRegsRegisterClass ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower


<s> if ( ! Op ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return MatchOperand_ParseFail ; } Operands -> push_back ( std :: move ( Op ) ) ; return MatchOperand_Success


<s> uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; return getI8Imm ( ( Index * VecVT . getScalarSizeInBits ( ) )


<s> if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; if ( can_issue_more == issue_rate - <NUM_LIT> ) end = false ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } n_nops -- ; } can_issue_more ++ ; * group_end = ( end || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; if ( * group_end && end ) (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; bool CanRealign = canRealignStack ( MF ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; const Function * F = MF . getFunction ( ) ; if ( F -> hasFnAttribute ( Attribute :: StackAlignment ) ) { if ( ! CanRealign ) DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; return CanRealign ; } unsigned StackAlignment = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; if ( MFI -> getMaxAlignment (


<s> static bool CantUseSP ( const MachineFrameInfo & MFI ) { return MFI . hasVarSizedObjects ( ) ||


<s> void Thumb1InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { llvm_unreachable ( <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_psradi256 ( (


<s> return const_cast < <ISA_LIT>TargetLowering * > ( &


<s> PM . add ( create<ISA_LIT>CodeEmitterPass ( * this , MCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) ,


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO ,

<STR_LIT> } , { MO_NO_FLAG , <STR_LIT> } } ;


<s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 :

\ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> SDValue <ISA_LIT>TargetLowering :: lowerExp ( SDValue Op , SelectionDAG & DAG ) const { return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> Register Address = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator I ( MI ) ; if ( Subtarget . has<ISA_LIT>32r6 ( ) || Subtarget . has<ISA_LIT>64r6 ( ) ) { Register BitcastW = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( BitcastW ) . addUse ( StoreVal ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( BitcastW ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm ) ; } else { Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( StoreVal ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse


<s> if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } } } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo


<s> static DecodeStatus DecodeLoadF32 ( MCInst & Inst , uint64_t insn , uint64_t Address , const MCDisassembler


<s> if ( Opcode == <STR_LIT> ) return isTargetShuffleSplat ( Op .


<s> rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value ,


<s> Reserved . set ( <STR_LIT> ) ; } for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isFP64bit ( ) ) { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isABI_O32 ( ) && ! Subtarget . useOddSPReg ( ) ) { for ( const auto & Reg : <STR_LIT> ) Reserved . set ( Reg ) ; } return Reserved


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( bool is64Bit , const Triple & T ) { if ( is64Bit ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : nullptr ; AssemblerDialect = <NUM_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment


<s> SDValue ShAmt = N -> getOperand ( <NUM_LIT> ) ; unsigned ShPartsOpc = <STR_LIT> ; ConstantSDNode * Con = dyn_cast < ConstantSDNode > ( ShAmt ) ; if ( ShAmt -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) > <NUM_LIT> || ( Con && Con -> getZExtValue ( ) >= <NUM_LIT> ) ) return SDValue ( ) ; if ( ShAmt -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ShAmt = DAG . getZExtOrTrunc ( ShAmt , dl , <STR_LIT> ) ; if ( ShOpc == <STR_LIT> ) { if ( ! Con ) ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , ShAmt ) ; else ShPartsOpc = <STR_LIT> ; } else if ( ShOpc == <STR_LIT> ) ShPartsOpc = <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getNode ( ShPartsOpc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Lo , Hi , ShAmt ) ; Hi = SDValue ( Lo . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo


<s> addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; } if ( unaligned_access && i > <NUM_LIT> && ( i + <NUM_LIT> ) == length ) { addr = plus_constant ( Pmode , dst , i - <NUM_LIT> ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i - <NUM_LIT> ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; return true ; } if ( i + <NUM_LIT> <= length ) { reg = gen_lowpart ( HImode , val_reg ) ; addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , HImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storehi ( mem , reg ) ) ; i += <NUM_LIT> ; } if ( i + <NUM_LIT> == length ) { reg = gen_lowpart ( QImode , val_reg ) ; addr = plus_constant ( Pmode


<s> unsigned MemOpc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand (


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> } } if ( ! TARGET_MMX && ! warnedmmx ) { if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { warnedmmx = true ; warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } } } return


<s> if ( isa < MemIntrinsicSDNode > ( Root ) ) return cast < MemIntrinsicSDNode > ( Root ) -> getMemoryVT ( ) ; const unsigned Opcode = Root -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; default : break ; } if ( Opcode != <STR_LIT> ) return EVT ( ) ; const unsigned IntNo = cast < ConstantSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return EVT ( ) ; return getPackedVectorTypeFromPredicateType ( Ctx , Root -> getOperand ( <NUM_LIT> ) ->


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCMN ( MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { MachineRegisterInfo & MRI = MIRBuilder . getMF


<s> Inst . addOperand ( MCOperand :: createReg ( getGPRMM16Reg (


<s> if ( simplejump_p ( insn ) || ( ( JUMP_P ( insn )

|| CALL_P ( insn ) ) ) ) length += <NUM_LIT> ;


<s> void printf80mem ( const MCInst * MI , unsigned OpNo ) { printMemReference ( MI , OpNo


<s> break ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) . add ( predOps ( <STR_LIT> ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >=


<s> MakeLibCallOptions CallOptions ; SDValue Result ; SDLoc dl ( Op ) ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , Call , Op . getValueType ( ) , Ops , CallOptions , dl , Chain ) ; return IsStrict ? DAG . getMergeValues ( { Result


<s> MVT HalfT = <STR_LIT> ; SDLoc dl ( N ) ; SDValue Hi , Lo , Tmp ; if ( ! isOperationLegalOrCustom ( <STR_LIT> , HalfT ) || ! isOperationLegalOrCustom ( <STR_LIT> , HalfT ) ) return ; unsigned OpTypeBits = HalfT . getScalarSizeInBits ( ) ; SDVTList VTList = DAG . getVTList ( HalfT , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , HalfT ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , HalfT ) ) ; Tmp = DAG . getNode ( <STR_LIT> , dl , HalfT , Hi , DAG . getConstant ( OpTypeBits - <NUM_LIT> , dl , getShiftAmountTy ( HalfT , DAG . getDataLayout ( ) ) ) ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VTList , Tmp , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , VTList , Tmp , Hi

, SDValue ( Lo . getNode ( ) , <NUM_LIT> ) ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT> ; return


<s> static DecodeStatus DecodeThreeAddrSRegInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shiftHi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shiftLo = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shift = ( shiftHi << <NUM_LIT> ) | shiftLo ; switch ( Inst . getOpcode ( ) ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi ==


<s> unsigned Offset = Top ? <NUM_LIT> : <NUM_LIT> ; unsigned N = SingleSource ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != (


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getLoadLiteralOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> assert ( Mask . size ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned HalfSize = Mask . size ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != HalfSize ;


_mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> if ( ! Elt . getNode ( ) || ( Elt . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Elt . getNode ( ) ) ) ) return SDValue ( ) ; if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; } if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <NUM_LIT> , <STR_LIT> , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , false , true , false ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , ResNode ) ; } return SDValue


<s> virtual bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { OutOps . push_back ( Op ) ; return


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; unsigned OffImm = MO2


<s> SDValue Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; Results . push_back ( Cycles32 .


<s> void setGlobalBaseReg ( unsigned Reg


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; auto PtrVT = getPointerTy ( DAG


<s> getJumpTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Fixups . push_back ( MCFixup :: create ( <NUM_LIT>

, Expr , MCFixupKind ( <STR_LIT> ) ) ) ;


<s> if ( GET_MODE_CLASS ( info . elt_mode ) == MODE_FLOAT ) { if ( aarch64_float_const_zero_rtx_p ( info . u . mov . value ) ) info . u . mov . value = GEN_INT ( <NUM_LIT> ) ; else { const int buf_size = <NUM_LIT> ; char float_buf [ buf_size ] = { } ; real_to_decimal_for_mode ( float_buf , CONST_DOUBLE_REAL_VALUE ( info . u . mov . value ) , buf_size , buf_size , <NUM_LIT> , info . elt_mode ) ; snprintf ( templ , sizeof ( templ ) , <STR_LIT> , element_char , float_buf ) ; return templ ; } } snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , element_char , INTVAL


<s> else setAction ( { Op , s32 } , Libcall ) ; for ( unsigned Op : { G_SEXT , G_ZEXT } ) { setAction ( { Op , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { Op , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_SELECT , s32 } , Legal ) ; setAction ( { G_SELECT , p0 } , Legal ) ; setAction ( { G_SELECT , <NUM_LIT> , s1 } , Legal ) ; setAction ( { G_CONSTANT , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_CONSTANT , Ty } , WidenScalar ) ; setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { setAction ( { G_FADD , s32 } , Legal ) ; setAction ( { G_FADD , s64 } , Legal ) ; setAction ( { G_LOAD , s64 } , Legal ) ; setAction ( { G_STORE , s64 } , Legal ) ; setAction ( { G_FCMP , s1 } , Legal ) ; setAction ( { G_FCMP , <NUM_LIT>


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT>


<s> int16x4x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; return


<s> if ( ! NoImplicitFloat && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE2 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> return ( Flags & CompareZeroCCMaskMask )


<s> AU . addPreserved < StackProtector > (


<s> V = peekThroughBitcasts ( V ) ; if ( V . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return V . getOperand ( <NUM_LIT> ) ; if ( V . getOpcode ( ) == <STR_LIT> && ( isNullConstant ( V . getOperand ( <NUM_LIT> ) ) || V . getOperand (


<s> unsigned char OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI -> memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState

:: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Pairs << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Pairs ; ++ i ) { const Value * V0 = VL0 [ i ] ; const Value * V1 = VL1 [ i ] ; const auto * Inst0 = dyn_cast < Instruction > ( V0 ) ; const auto * Inst1 = dyn_cast < Instruction > ( V1 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; V0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; V1 -> dump ( ) ) ; if ( ! Inst0 || ! Inst1 ) return false ; if ( Inst0 -> isSameOperationAs ( Inst1 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const APInt * C0 , * C1 ; if ( ! ( match ( V0 , m_APInt ( C0 ) ) && match ( V1 , m_APInt ( C1 ) ) && C0 == C1 ) ) return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true


<s> void setStackRealigned ( bool s ) { StackRealigned =


<s> for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) ISRDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject

( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ;


<s> assert ( v . size ( ) >= <NUM_LIT> ) ; assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest +

<NUM_LIT> , LegalizerInfo :: Unsupported } ) ;


<s> unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL


<s> return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> isPseudo ( ) ) llvm_unreachable (


<s> return ( __mmask8 ) __builtin_ia32_cvtq2mask256 ( ( __v4di )


<s> int64_t NewImm = <NUM_LIT> ; bool SetCR = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( PostRA ) return false ; bool Changed = false ; unsigned DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Comparand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t SExtComparand = ( ( uint64_t ) Comparand & ~ <NUM_LIT> ) != <NUM_LIT> ? ( Comparand | <NUM_LIT> ) : Comparand ; for ( auto & CompareUseMI : MRI -> use_instructions ( DefReg ) ) { unsigned UseOpc = CompareUseMI . getOpcode ( ) ; if ( UseOpc != <STR_LIT> && UseOpc != <STR_LIT> ) continue ; unsigned CRSubReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned TrueReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegToCopy = selectReg ( SExtImm , SExtComparand , Opc , TrueReg , FalseReg , CRSubReg ) ; if ( RegToCopy == <STR_LIT> ) continue ; if ( RegToCopy == <STR_LIT> || RegToCopy == <STR_LIT> ) { CompareUseMI . setDesc ( get ( UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; CompareUseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ; MI . dump ( ) ; CompareUseMI . dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; CompareUseMI . setDesc ( get ( <STR_LIT> ) ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( RegToCopy == TrueReg ? <NUM_LIT> : <NUM_LIT> ) ; CmpIselsConverted ++ ; Changed = true ; DEBUG ( CompareUseMI . dump ( ) ) ; } if ( Changed ) return true ; MissedConvertibleImmediateInstrs ++ ; return false ; } case <STR_LIT> : case <STR_LIT> : { int64_t Addend = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Addend + SExtImm ) ) { ReplaceWithLI = true ; Is64BitLI = Opc == <STR_LIT> ; NewImm = Addend + SExtImm ; break ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << format (


<s> VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ; } return


<s> if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo (


<s> void <ISA_LIT>16InstrInfo :: adjustStackPtrBigUnrestricted ( unsigned SP , int64_t Amount , MachineBasicBlock

& MBB , MachineBasicBlock :: iterator I ) const {


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set


<s> static SDValue PerformShuffleCombine ( SDNode * N , SelectionDAG & DAG , const TargetLowering & TLI ) { DebugLoc dl = N -> getDebugLoc ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EVT = VT . getVectorElementType ( ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; LoadSDNode * LD = NULL ; unsigned LastLoadedElt ; if ( ! EltsFromConsecutiveLoads ( SVN , NumElems , EVT , LD , LastLoadedElt , DAG , MFI , TLI ) ) return SDValue ( ) ; if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( isBaseAlignmentOfN ( <NUM_LIT> , LD -> getBasePtr ( ) . getNode ( ) , TLI ) ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) ) ; return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile (


) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> , __R ) ;


<s> return ( MI . getOpcode ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( )


<s> static bool CanHaveSwappedOperands ( unsigned Opcode ) { switch ( Opcode ) { default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( Loop * L : LI ) for ( Loop * LIt : depth_first ( L ) ) MadeChange |= runOnLoop ( * LIt ) ; return MadeChange


<s> unsigned int size ; enum mode_class mclass ; if ( mode == FCCmode ) return FCC_REG_P ( regno ) ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) ) return ( ( regno - GP_REG_FIRST ) & <NUM_LIT> ) == <NUM_LIT> || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) ) { if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } return false


<s> void <ISA_LIT>InstPrinter :: printU3ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printUImmOperand < <NUM_LIT> > ( MI , OpNum ,


<s> bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex


<s> static ipa_opt_pass_d * make_pass_ipa_frame_header_opt ( gcc :: context * ctxt


<s> if ( asm_noperands ( insn ) >= <NUM_LIT> ) return false ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , <NUM_LIT> , XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ) ; if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , <NUM_LIT> ) ) )


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> && VT != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue B = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) ,

A , Constant ( immInByte * <NUM_LIT> , <STR_LIT> ) ) ;


<s> tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > <NUM_LIT> && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && ! USING_SJLJ_EXCEPTIONS ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> V = rotr32 ( ~ <NUM_LIT> , getSOImmValRotate ( V ) ) & V ; if ( V == <NUM_LIT>


<s> unsigned CCMask = Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get (


<s> if ( ! I ) return nullptr ; if ( I -> getIntrinsicID ( ) != <STR_LIT> )


<s> OS << <STR_LIT> << Symbol -> getName ( )


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE1 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if (


<s> EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( STI ) ) { if ( uint8_t REX = DetermineREXPrefix ( MI , TSFlags , MemOperand , Desc ) ) { EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; Ret = true ; } } switch ( TSFlags & <STR_LIT>


<s> } Type * Ty = MF . getFunction ( ) -> getReturnType ( ) ; if ( auto * STy = dyn_cast < StructType > ( Ty ) ) Ty = STy -> getTypeAtIndex ( ( uint32_t ) <NUM_LIT> ) ; auto * VT = dyn_cast < VectorType


<s> MCSubtargetInfo & STI = copySTI ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature (


<s> void printMemOffs8 ( const MCInst * MI ,


<s> void setExIdxFragment ( RegionFragment *


<s> mep_selected_isa = mep_configs [ <NUM_LIT> ] . isa ; if ( mep_config_string != <NUM_LIT> ) for ( i = <NUM_LIT> ; mep_configs [ i ] . config_name ; i ++ ) if ( strcmp ( mep_config_string , mep_configs [ i ] . config_name ) == <NUM_LIT> ) { mep_selected_isa = mep_configs [ i ] . isa ; break ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mep_intrinsic_insn ) ; i ++ ) mep_intrinsic_insn [ i ] = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cgen_insns ) ; i ++ ) if ( ( cgen_insns [ i ] . isas & mep_selected_isa ) != <NUM_LIT> ) { mep_intrinsic_chain [ i ] = mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] ; mep_intrinsic_insn [ cgen_insns [ i ] .


<s> GetJumpTableSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_'


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT>

, SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> printThumbAddrModeRI5Operand ( MI , Op ,


<s> log_insn ( e . setcc . insn ) ; log_return ( false , <STR_LIT> ) ; } if ( ! reg_dead_after_insn ( m_ccreg , e . cstore . insn ) && ! reg_unused_after_insn ( m_ccreg , e . cstore . insn ) ) { log_msg (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , NMBB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , NMBB ,


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; const bool Is64BitILP32 = STI . isTarget64BitILP32 ( ) ; unsigned FramePtr = TRI -> getFrameRegister ( MF ) ; unsigned MachineFramePtr = Is64BitILP32 ? get<ISA_LIT>SubSuperRegister ( FramePtr , <STR_LIT> , false ) : FramePtr ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool NeedsWinCFI = IsWin64Prologue && MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; bool IsFunclet = isFuncletReturnInstr ( MBBI ) ; MachineBasicBlock * TargetMBB = nullptr ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t MaxAlign = calculateMaxStackAlign ( MF ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; TargetMBB = MBBI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI