<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT FloatTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : FloatTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> ,


<s> SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; NumElts /= <NUM_LIT> ; } EVT MovmskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; Movmsk = combineBitcastvxi1 ( DAG , MovmskVT , Match , DL , Subtarget ) ; } if ( ! Movmsk ) return SDValue ( ) ; Movmsk = DAG . getZExtOrTrunc ( Movmsk , DL , NumElts > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else { unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && Subtarget . hasAVX ( ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; if ( MatchSizeInBits == <NUM_LIT> && BitWidth < <NUM_LIT> && ! Subtarget . hasInt256 ( ) ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; MatchSizeInBits = Match . getValueSizeInBits ( ) ; } MVT MaskSrcVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskSrcVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskSrcVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; SDValue BitcastLogicOp = DAG . getBitcast ( MaskSrcVT , Match ) ; Movmsk = getPMOVMSKB ( DL , BitcastLogicOp , DAG , Subtarget ) ; NumElts = MaskSrcVT . getVectorNumElements ( ) ; } assert ( ( NumElts <= <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; MVT CmpVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( BinOp == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , DL , CmpVT , Movmsk ) ; return DAG . getZExtOrTrunc ( Result , DL , ExtractVT ) ; } SDValue CmpC ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CmpC = DAG . getConstant ( <NUM_LIT> , DL , CmpVT ) ; CondCode = <STR_LIT> :: SETNE ; } else { CmpC = DAG . getConstant ( APInt :: getLowBitsSet ( CmpVT . getSizeInBits ( ) , NumElts ) , DL , CmpVT ) ; CondCode = <STR_LIT> :: SETEQ ; } EVT SetccVT = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , CmpVT ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT , Movmsk


<s> return __builtin_ia32_ucomisdlt ( ( __v2df ) __A , (


<s> <ISA_LIT>VSXFMAMutate ( ) : MachineFunctionPass ( ID )


<s> NeedAddressOverride = true ; } else if ( MemoryOperand < <NUM_LIT> ) { NeedAddressOverride = false ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is16BitMemOperand ( MI , MemoryOperand , STI ) ) ; NeedAddressOverride = is32BitMemOperand ( MI , MemoryOperand ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; NeedAddressOverride = is16BitMemOperand ( MI , MemoryOperand , STI ) ; } else { assert ( STI . hasFeature ( <STR_LIT> ) ) ; assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; NeedAddressOverride = ! is16BitMemOperand ( MI , MemoryOperand , STI ) ; } if ( NeedAddressOverride ) emitByte ( <NUM_LIT> , OS ) ; uint64_t Encoding = TSFlags & <STR_LIT> ; bool HasREX = false ; if ( Encoding ) emitVEXOpcodePrefix ( MemoryOperand , MI , OS ) ; else HasREX = emitOpcodePrefix ( MemoryOperand , MI , STI , OS ) ; uint64_t Form = TSFlags & <STR_LIT> ; switch ( Form ) { default : break ; case <STR_LIT> : { unsigned siReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( ( siReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( siReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( siReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; if ( ( ! STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) ) emitByte ( <NUM_LIT> , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT> : { unsigned siReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; if ( ( ! STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) ) emitByte ( <NUM_LIT> , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT>


<s> return ( int32x2_t ) __builtin_neon_vhaddsv2si


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; MVT NewVT ; unsigned Scale ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return SDValue ( SVOp , <NUM_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += Scale ) { int StartIdx = - <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j !=


<s> int64_t Offset = Addr . getOffset ( ) ; if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ( ImmediateOffsetNeedsLowering || Addr . getOffsetReg ( ) ) && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , <STR_LIT> , Addr . getShift ( ) ) ; }


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> )

. addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> static bool MaskRegClassContains ( unsigned


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( regs == <NUM_LIT> || regs > <NUM_LIT> || ( Vd + regs ) > <NUM_LIT> ) { regs = Vd + regs > <NUM_LIT> ? <NUM_LIT> - Vd : regs ; regs = std :: max ( <NUM_LIT> , regs ) ; regs = std :: min (


<s> MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Changed |= shortenIIF ( MI , LowGPRs , LiveHigh , <STR_LIT> , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) Changed |= shortenIIF ( MI , HighGPRs , LiveLow , <STR_LIT> , <STR_LIT> ) ; unsigned UsedLow = <NUM_LIT> ; unsigned UsedHigh = <NUM_LIT> ; for ( auto MOI = MI . operands_begin ( ) , MOE = MI . operands_end ( ) ; MOI != MOE ; ++ MOI ) { MachineOperand & MO = * MOI ; if ( MO . isReg ( ) ) { if ( unsigned Reg = MO . getReg ( ) ) { assert ( Reg < <STR_LIT> && <STR_LIT> ) ; if ( MO . isDef ( ) ) { LiveLow &= ~ LowGPRs [


<s> static enum aarch_parse_opt_result aarch_handle_pac_ret_b_key ( char * str ATTRIBUTE_UNUSED , char * rest


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Fd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ws = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Lane == <NUM_LIT> ) BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Ws , <NUM_LIT> , <STR_LIT> ) ; else { unsigned Wt = RegInfo . createVirtualRegister ( &


<s> Value * <ISA_LIT>RegisterSema :: getCC ( <STR_LIT> CC ) { Value * CCV = CCVals [ CC ] ; if ( CCV ) return CCV ; bool Inv = false ; bool XOF = false ; bool OZF = false ; <STR_LIT> SF ; switch ( CC ) { case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; OZF = true ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; XOF = true ; break ; case <STR_LIT> : Inv = true ; case <STR_LIT> : SF = <STR_LIT> ; XOF = true ; OZF = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } ; CCV = getSF ( SF ) ; if ( XOF ) CCV = Builder -> CreateXor ( CCV , getSF ( <STR_LIT> ) ) ; if ( OZF ) CCV = Builder -> CreateOr ( CCV , getSF ( <STR_LIT> ) ) ; if ( Inv ) CCV = Builder -> CreateNot ( CCV ) ; setCC ( CC , CCV ) ; return


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext &


<s> InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector ( ) const { return InstSelector . get ( )


<s> mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode


<s> const Function * F = MF . getFunction ( ) ; bool requiresRealignment = RealignStack && ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttr (


<s> unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear


<s> df_ref ref ; for ( ref = DF_INSN_INFO_DEFS ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; if ( type == TYPE_LOAD || type == TYPE_FPLOAD || type == TYPE_VECLOAD ) for ( ref = DF_INSN_INFO_USES ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; return


<s> return new Emitter < JITCodeEmitter >


<s> if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDu = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ATReg = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned NewImm ; <ISA_LIT>FI -> setEmitNOAT ( ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , & NewImm ) ; BuildMI ( MBB , II , DL , TII . get ( ADDu ) , ATReg ) . addReg ( FrameReg ) . addReg ( Reg ) ; FrameReg = ATReg ; Offset = SignExtend64 < <NUM_LIT> > (


<s> else if ( findMaskedBFI ( N -> getOperand ( <NUM_LIT> ) , BFI , ExistingMask , Extended ) ) PossExtraMask = N -> getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; if ( PossExtraMask . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( PossExtraMask . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t ExtraMask = PossExtraMask -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ExtraMask & ExistingMask ) return SDValue ( ) ; SDValue OldBFIVal = BFI . getOperand ( <NUM_LIT> ) ; SDValue NewBFIVal = BFI . getOperand ( <NUM_LIT> ) ; if ( Extended ) { assert ( VT == <STR_LIT> && BFI . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; OldBFIVal = DAG . getNode ( <STR_LIT> , DL , VT , OldBFIVal ) ; NewBFIVal = DAG . getNode ( <STR_LIT> , DL , VT , NewBFIVal ) ; } if ( PossExtraMask . getOperand ( <NUM_LIT> ) != OldBFIVal ) return SDValue ( ) ; BFI = DAG . getNode ( <STR_LIT> , DL , VT , OldBFIVal , NewBFIVal , BFI . getOperand ( <NUM_LIT> ) , BFI . getOperand ( <NUM_LIT> ) ) ; if ( ( ExtraMask | ExistingMask ) == ( - <NUM_LIT> >> ( <NUM_LIT> - VT . getSizeInBits ( ) ) ) ) return BFI ; return DAG . getNode ( <STR_LIT> , DL , VT , BFI , DAG . getConstant ( ExtraMask


<s> case V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) - <NUM_LIT> ) , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , <NUM_LIT> , OPTAB_DIRECT ) ; break ; case V8HImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , <NUM_LIT> ) ; x = expand_simple_binop ( mode , SMAX , tmp0 , input , target , <NUM_LIT> , OPTAB_DIRECT ) ; break ; case V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , <NUM_LIT> ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , <NUM_LIT> , OPTAB_DIRECT ) ; break ; default : gcc_unreachable (


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_LENGTH ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_TYPE ) ; } if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Real ) || getLexer ( ) . is ( AsmToken :: Minus ) ) { const MCExpr * Val ; if ( ! getParser ( ) . parseExpression ( Val , End ) ) { return <STR_LIT> ( Val , Start , End ) ; } } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ! Op -> hasAnyUseOfValue ( <NUM_LIT> ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt < <NUM_LIT> && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnes ( <NUM_LIT> ) << ( <NUM_LIT> - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( <NUM_LIT> - ShAmt ,


<s> bool isBDAddr32Disp20 ( ) const { return isMemDisp20 ( BDMem , GR32Reg


<s> return ( __mmask64 ) __builtin_ia32_ptestnmb512 ( ( __v64qi ) __A , ( __v64qi )


<s> emit_insn ( gen_tldm_hi22 ( temp1 ) ) ; emit_insn ( gen_tldm_lo10 ( temp2 , temp1 ) ) ; if ( TARGET_ARCH32 ) { emit_insn ( gen_tldm_add32 ( o0 , got , temp2 ) ) ; insn = emit_call_insn ( gen_tldm_call32 ( o0 , sparc_tls_get_addr ( ) , const1_rtx ) ) ; } else { emit_insn ( gen_tldm_add64 ( o0 , got , temp2 ) ) ; insn = emit_call_insn ( gen_tldm_call64 ( o0 , sparc_tls_get_addr ( ) , const1_rtx ) ) ; } use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , o0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insn , temp3 , o0 , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLSLD_BASE ) ) ; temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tldo_hix22 ( temp1 , addr ) ) ; emit_insn ( gen_tldo_lox10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tldo_add32 ( ret , temp3 , temp2 , addr ) ) ; else emit_insn ( gen_tldo_add64 ( ret , temp3 , temp2 , addr ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; temp3 = gen_reg_rtx ( Pmode ) ; got = sparc_tls_got ( ) ; emit_insn ( gen_tie_hi22 ( temp1 , addr ) ) ; emit_insn ( gen_tie_lo10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_ld32 ( temp3 , got , temp2 , addr ) ) ; else emit_insn ( gen_tie_ld64 ( temp3 , got , temp2 , addr ) ) ; if ( TARGET_SUN_TLS )


<s> if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Val & ( <NUM_LIT> << i ) ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , i , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( NeedDisjointWriteback && WritebackReg == Inst . end ( ) [ - <NUM_LIT> ] . getReg ( ) ) Check ( S , MCDisassembler :: SoftFail ) ; } } return


<s> auto Splat = get<ISA_LIT>VectorSplat ( MI , MRI ) ; if ( ! Splat ) return false ; if ( Splat -> isReg ( ) ) return


<s> int BitOffset = BroadcastIdx * NumEltBits ; SDValue V = V1 ; for ( ; ; ) { switch ( V . getOpcode ( ) ) { case <STR_LIT> : { V = V . getOperand ( <NUM_LIT> ) ; continue ; } case <STR_LIT> : { int OpBitWidth = V . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; int OpIdx = BitOffset / OpBitWidth ; V = V . getOperand ( OpIdx ) ; BitOffset %= OpBitWidth ; continue ; } case <STR_LIT> : { SDValue VOuter = V . getOperand ( <NUM_LIT> ) , VInner = V . getOperand ( <NUM_LIT> ) ; auto ConstantIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstantIdx ) break ; int EltBitWidth = VOuter . getScalarValueSizeInBits ( ) ; int Idx = ( int ) ConstantIdx -> getZExtValue ( ) ; int NumSubElts = ( int ) VInner . getSimpleValueType ( ) . getVectorNumElements ( ) ; int BeginOffset = Idx * EltBitWidth ; int EndOffset = BeginOffset + NumSubElts * EltBitWidth ; if ( BeginOffset <= BitOffset && BitOffset < EndOffset ) { BitOffset -= BeginOffset ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } assert ( ( BitOffset % NumEltBits ) == <NUM_LIT> && <STR_LIT> ) ; BroadcastIdx = BitOffset / NumEltBits ; bool BitCastSrc = V . getScalarValueSizeInBits ( ) != NumEltBits ; if ( BitCastSrc && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerShuffleAsTruncBroadcast ( DL , VT , V , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; if ( ! BitCastSrc && ( ( V . getOpcode ( ) == <STR_LIT> && V . hasOneUse ( ) ) || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! BroadcastFromReg && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( <STR_LIT> ( V . getNode ( ) ) && cast < LoadSDNode > ( V ) -> isSimple (


<s> Inst . addOperand ( MCOperand :: createImm ( Imm + <NUM_LIT> ) ) ; return


<s> tree r , u ; r = size_int ( NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ) ; u = build2 ( MODIFY_EXPR , TREE_TYPE ( count_tmp ) , count_tmp , r ) ; t = fold_convert ( TREE_TYPE ( count ) , r ) ; t = build2 ( GE_EXPR , boolean_type_node , count_tmp , t ) ; t = build3 ( COND_EXPR , void_type_node , t , NULL_TREE , u ) ; gimplify_and_add ( t , pre_p ) ; } t = size_int ( NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD + INCOMING_FRAME_SP_OFFSET ) ; t = fold_convert ( TREE_TYPE ( count ) , t ) ; t = build2 ( MINUS_EXPR , TREE_TYPE ( count ) , count_tmp , t ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( count ) , t , fold_convert ( TREE_TYPE ( count ) , size_tree ) ) ; t = fold_convert ( TREE_TYPE ( t ) , fold ( t ) ) ; t = fold_build1 ( NEGATE_EXPR , TREE_TYPE ( t ) , t ) ; t = fold_build_pointer_plus ( base , t ) ; gimplify_assign ( addr , t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_gotaddr ) ; gimplify_and_add ( t , pre_p ) ; t = fold_convert ( TREE_TYPE ( count ) , size_tree ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( count ) , count_tmp , t ) ; gimplify_assign ( count , t , pre_p ) ; addr = fold_convert ( build_pointer_type (


<s> if ( CC == <STR_LIT> ) { ++ MBBI ; continue ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; while ( MBBI != E && Pos && ( ! MI -> getDesc ( ) . isBranch ( ) && ! MI -> getDesc ( ) . isReturn ( ) ) ) { MachineInstr * NMI = & * MBBI ; MI = NMI ; DebugLoc ndl = NMI -> getDebugLoc


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo


<s> VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! isLegalInterleavedAccessType ( VecTy , DL ) ) return false ; unsigned NumLoads = getNumInterleavedAccesses ( VecTy , DL ) ; Type * EltTy = VecTy -> getVectorElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> ,


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX ( ) && ! TheTriple

. isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> d . target = operands [ <NUM_LIT> ] ; d . op0 = operands [ <NUM_LIT> ] ; d . op1 = operands [ <NUM_LIT> ] ; sel = operands [ <NUM_LIT> ] ; d . vmode = GET_MODE ( d . target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; gcc_assert ( GET_CODE ( sel ) == CONST_VECTOR ) ; gcc_assert ( XVECLEN ( sel , <NUM_LIT> ) == nelt ) ; gcc_checking_assert ( sizeof ( d . perm ) == sizeof ( perm ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , <NUM_LIT> , i ) ; int ei = INTVAL ( e ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; d . perm [ i ] = ei ; perm [ i ] = ei ; } two_args = canonicalize_perm ( & d )


<s> bool IsInt8 = Offset . isImm ( ) && isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ; switch ( LEAOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return IsInt8 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsInt8 ? <STR_LIT>


<s> if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i )

, i ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ;


<s> void addMemoryIndexed32SImm7Operands ( MCInst & Inst


<s> static unsigned decodeN3VImm ( uint32_t


<s> unsigned Binary = <NUM_LIT> ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> <<


<s> SMShadowTracker . count ( Inst , getSubtargetInfo


<s> unsigned Opc = MI . getOpcode ( ) ; assert ( ! ( FMA3Group . isIntrinsic ( ) && ( SrcOpIdx1 == <NUM_LIT> || SrcOpIdx2 == <NUM_LIT> ) ) && <STR_LIT> ) ; unsigned Case = getThreeSrcCommuteCase ( MI . getDesc ( ) . TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; assert ( Case < <NUM_LIT> && <STR_LIT> ) ; const unsigned Form132Index = <NUM_LIT> ; const unsigned Form213Index


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) { return MCAsmBackend :: getFixupKindInfo ( Kind ) ; } assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds (


<s> void LLVMInitializeDigitalTarget ( )


<s> bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . getOperand ( <NUM_LIT> ) .


<s> return ( int32x2_t ) __builtin_neon_vdup_lanev2si


<s> case G_UMULH : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FCONSTANT : { LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Size = Ty . getSizeInBits ( ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; default : return getInvalidInstructionMapping ( )


<s> SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , P } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( DAG . SignBitIsZero ( Op0 )


<s> MCSubtargetInfo & STI = copySTI ( ) ; for ( auto Feature : Features ) STI . ApplyFeatureFlag ( Feature ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . emitFPU ( ID ) ; return


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , L ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT>


<s> enum machine_mode mode = BLKmode ; rtx src , dest ; if ( TARGET_ALTIVEC && bytes >= <NUM_LIT> && align >= <NUM_LIT> ) { move_bytes = <NUM_LIT> ; mode = V4SImode ; gen_func . mov = gen_movv4si ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_8reg ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_6reg ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_4reg ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ( ! STRICT_ALIGNMENT && align >= <NUM_LIT> ) ) ) { move_bytes = <NUM_LIT> ; mode = DImode ; gen_func . mov = gen_movdi ; } else if ( TARGET_STRING && bytes > <NUM_LIT> && ! TARGET_POWERPC64 ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_2reg ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else if ( TARGET_STRING && bytes > <NUM_LIT> ) { move_bytes = ( bytes > <NUM_LIT> ) ? <NUM_LIT> : bytes ; gen_func . movmemsi = gen_movmemsi_1reg ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; if ( mode != BLKmode ) { rtx tmp_reg = gen_reg_rtx ( mode ) ; emit_insn ( ( * gen_func . mov ) ( tmp_reg , src ) ) ; stores [ num_reg ++ ] = ( * gen_func . mov ) ( dest


<s> } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget ->


<s> const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , CallerF . getContext ( ) ) ; if ( ! analyzeArgInfo ( OutInfo , OutArgs , * AssignFnFixed , * AssignFnVarArg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( OutInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * CallerPreservedMask = TRI -> getCallPreservedMask ( MF , CallerCC ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Info . IsVarArg ) { for ( unsigned i = <NUM_LIT> ; i < OutLocs . size ( ) ; ++ i ) { auto & ArgLoc = OutLocs [ i


<s> return ( __m128i ) __builtin_ia32_vpconflictdi_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_si128 ( )


<s> if ( IsVarArg ) { report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ]


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> return getParser ( ) . getTok ( ) . getLoc


<s> SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <=


<s> if ( MIPosition <= RangeBegin || MIPosition > RangeEnd ) continue ; if ( MI . definesRegister ( DefReg ) ) LastLivePos = std :: min ( LastLivePos , MIPosition ) ; MachineOperand * UseOp = MI . findRegisterUseOperand ( DefReg ) ; if ( ! UseOp ) continue ; if ( UseOp -> isKill ( ) ) LastLivePos = std :: min ( LastLivePos , MIPosition ) ; Uses [ MIPosition ] = UseOp ; } for ( std :: map < unsigned , MachineOperand * > :: iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { if ( I -> first > LastLivePos ) break ; UsesOfImpDefs . push_back ( I ->


<s> const MachineOperand & DstMO = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; unsigned DstReg = DstMO . getReg ( ) ; unsigned SrcReg = SrcMO . getReg ( ) ; auto getRegClass = [ & ] ( unsigned Reg ) { return TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : TRI . getMinimalPhysRegClass ( Reg ) ; } ; if ( DstMO . getSubReg ( ) == <NUM_LIT> && SrcMO . getSubReg ( ) == <NUM_LIT> ) { assert ( getRegClass ( DstReg ) -> getSize ( ) == getRegClass ( SrcReg ) -> getSize ( ) && <STR_LIT> ) ; if ( IsSpill ) storeRegToStackSlot ( MBB , InsertPt , SrcReg , SrcMO . isKill ( ) , FrameIndex , getRegClass ( SrcReg ) , & TRI ) ; else loadRegFromStackSlot ( MBB , InsertPt , DstReg , FrameIndex , getRegClass ( DstReg ) , & TRI ) ; return & * -- InsertPt ; } if ( IsSpill && DstMO . isUndef ( ) && TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { assert ( SrcMO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * SpillRC ; unsigned SpillSubreg ; switch ( DstMO . getSubReg ( ) ) { default : SpillRC = nullptr ; break ; case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> . contains ( SrcReg ) ) { SpillRC = & <STR_LIT> ; SpillSubreg = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { SpillRC = & <STR_LIT> ; SpillSubreg = <STR_LIT> ; } else SpillRC = nullptr ; break ; case <STR_LIT> : if ( <STR_LIT> . contains ( SrcReg ) ) { SpillRC = & <STR_LIT> ; SpillSubreg = <STR_LIT> ; } else SpillRC = nullptr ; break ; } if ( SpillRC ) if ( unsigned WidenedSrcReg = TRI . getMatchingSuperReg ( SrcReg , SpillSubreg , SpillRC ) ) { storeRegToStackSlot ( MBB , InsertPt , WidenedSrcReg , SrcMO . isKill ( ) , FrameIndex , SpillRC , & TRI ) ; return & * -- InsertPt ; } } if ( IsFill && SrcMO . getSubReg ( ) == <NUM_LIT> && DstMO . isUndef ( ) ) { const TargetRegisterClass * FillRC ; switch ( DstMO . getSubReg ( ) ) { default : FillRC = nullptr ; break ; case <STR_LIT> : FillRC = & <STR_LIT> ; break ; case <STR_LIT> : FillRC = & <STR_LIT> ; break ; case <STR_LIT> : FillRC = & <STR_LIT> ; break ; } if ( FillRC ) { assert ( getRegClass ( SrcReg ) -> getSize ( ) == FillRC -> getSize ( )


<s> MachineInstr * EarlierMI = MF . CloneMachineInstr ( & * MI ) ; MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm


<s> switch ( Opc ) { default : continue ; case <STR_LIT> : T2JumpTables . push_back ( & I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk =


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o


<s> if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT>


<s> intptr_t * RetAddrLoc = & StackPtr [ <NUM_LIT> ] ; __msan_unpoison ( RetAddrLoc , sizeof ( * RetAddrLoc ) ) ; assert ( * RetAddrLoc == RetAddr && <STR_LIT> ) ; bool isStub = ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] == <NUM_LIT> ; RetAddr -- ; RetAddr -= <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << ( void * ) RetAddr << <STR_LIT> << ( void * ) StackPtr << <STR_LIT> << TheVM -> getFunctionReferencedName ( ( void * ) RetAddr ) << <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT>


<s> return __builtin_mve_vabdq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __b ,


<s> if ( Op . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) return true ; } return false


<s> return ix86_dep_by_shift_count_body ( PATTERN ( set_insn ) , PATTERN (


<s> DebugLoc dl = Cmp . getDebugLoc ( ) ; SDValue TruncFPSW = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; SDValue FNStSW = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TruncFPSW ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FNStSW , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue TruncSrl = DAG . getNode ( <STR_LIT> , dl


<s> if ( areCFlagsAliveInSuccessors ( CmpInstr -> getParent ( ) ) ) return false ; AccessKind AccessToCheck = AK_Write ; if ( sForm ( * MI ) != MI -> getOpcode ( ) ) AccessToCheck = AK_All ; if ( areCFlagsAccessedBetweenInstrs ( MI , CmpInstr , TRI , AccessToCheck ) ) return false ; UsedNZCV NZCVUsedAfterCmp ; for ( const MachineInstr & Instr : instructionsWithoutDebug ( std :: next ( CmpInstr -> getIterator ( ) ) , CmpInstr -> getParent ( ) -> instr_end ( ) ) ) { if ( Instr . readsRegister ( <STR_LIT> , TRI ) ) { <STR_LIT> CC = findCondCodeUsedByInstr ( Instr ) ; if ( CC == <STR_LIT>


<s> GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 =


<s> SDLoc dl ( Op ) ; if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; MVT HVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HVT ,


<s> PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ; return false


<s> printMemOperandEA ( const MCInst * MI , int


<s> ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregxidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregxidf


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { static const TypeConversionCostTblEntry < <STR_LIT> > NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType (


<s> gcc_assert ( cfun -> stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs , anon_parm_regs ; named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , mode ) + ( mode == BLKmode ? CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) : CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) -


<s> for ( const MachineOperand & MO : MI . uses ( ) ) if ( MO . isReg ( ) && <STR_LIT> !=


<s> static void umips_output_load_store_pair_1 ( bool load_p , rtx reg , rtx mem ) { rtx ops [ ] = { reg , mem } ; if ( load_p ) output_asm_insn ( <STR_LIT> , ops ) ; else output_asm_insn ( <STR_LIT>


<s> MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool Result = ( Index *


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys


<s> if ( Op . isDef ( ) ) { if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) DefFP = true ; continue ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { int R = Reg - <STR_LIT> ; ClearRegs . reset ( R * <NUM_LIT> ,


<s> O << <STR_LIT> ; if ( Count > <NUM_LIT> ) { bool IsVec64 = ( Layout < <STR_LIT> ) ; unsigned SubRegIdx = IsVec64 ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Count ; I ++ ) { std :: string Name = getRegisterName ( MRI . getSubReg ( Reg , SubRegIdx ++ ) ) ; Name [ <NUM_LIT> ] = 'v' ; O << Name << LayoutStr ; if ( I != Count - <NUM_LIT>


<s> VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? <STR_LIT> : <STR_LIT> ; return


<s> CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( ! isTailCall && CLI . CS && CLI . CS -> isMustTailCall ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs ,


<s> MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * NewMBB ; unsigned UserOffset = GetOffsetOf ( UserMI ) + ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; if ( UserMI -> getOpcode ( ) == <STR_LIT> ) UserOffset += <NUM_LIT> ; int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = Fn . CreateMachineBasicBlock ( ) ; Fn . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . CPEMI = BuildMI ( NewIsland , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; NumCPEs ++ ; BBOffsets [ NewIsland -> getNumber ( ) ] = BBOffsets [ NewMBB -> getNumber ( ) ] ; if ( isThumb && BBOffsets [ NewIsland -> getNumber ( ) ] % <NUM_LIT> != <NUM_LIT> ) Size += <NUM_LIT> ; BBSizes [ NewIsland -> getNumber ( ) ] += Size ; AdjustBBOffsetsAfter ( NewIsland , Size ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex ( ID ) ; break ; } DOUT << <STR_LIT> << ID << <STR_LIT> << CPI << <STR_LIT> << * UserMI ; return true


<s> case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 (


<s> static void ReplaceATOMIC_OP_64 ( SDNode * Node , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , unsigned NewOp ) { DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT>

) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ;


<s> void <ISA_LIT>CCState :: PreAnalyzeFormalArgumentsForF128 ( const SmallVectorImpl < <STR_LIT> > & Ins ) { const MachineFunction & MF = getMachineFunction ( ) ; for ( unsigned i = <NUM_LIT> ; i < Ins . size ( ) ; ++ i ) { Function :: const_arg_iterator FuncArg = MF . getFunction ( ) -> arg_begin ( ) ; if ( Ins [ i ] . Flags . isSRet ( ) ) { OriginalArgWasF128 . push_back ( false


<s> return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'y' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; if ( ! isPowerOf2_64 ( MO . getImm ( ) ) ) return true ; O << Log2_64 ( MO . getImm ( ) ) ; return false ; case 'z' : if ( MO . getType ( ) == MachineOperand :: MO_Immediate && MO . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; return false ; } break ; case 'D' : case 'L' : case 'M' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum : OpNum + <NUM_LIT> ; break ; case 'D' : RegOp = OpNum + <NUM_LIT> ; } if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; if ( pParent . getRelRelMap ( ) . lookUp ( pReloc ) != NULL ) return Relocator :: BadReloc ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> && ! rsym -> isLocal ( ) && rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) S = helper_get_PLT_address ( * rsym , pParent ) ; Relocator :: SWord V = S +


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) { M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: Win64 ) ; F -> addAttribute ( <NUM_LIT> , Attribute :: AttrKind ::


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter >


<s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> return __builtin_mve_vrev32q_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a


<s> rtx dest , tp , label , labelno , sum , insns , ret , eqv , addend ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) )


<s> case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } SDValue FIPtr = DAG . CreateStackTemporary ( <STR_LIT> ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr

, DAG . getConstant ( <NUM_LIT> , FIPtr . getValueType ( ) ) ) ;


<s> if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC ) return x ; mode = SELECT_CC_MODE ( code , x , y ) ; if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = <NUM_LIT> ; static rtx prev_args [ <NUM_LIT> ] [ <NUM_LIT> ] ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; reg ++ ) if ( prev_args [ reg ] [ <NUM_LIT> ] == x && prev_args [ reg ] [ <NUM_LIT> ] == y ) break ; if ( reg == <NUM_LIT> ) { reg = next_fcc_reg ; prev_args [ reg ] [ <NUM_LIT> ] = x ; prev_args [ reg ] [ <NUM_LIT> ] = y ; next_fcc_reg = ( next_fcc_reg + <NUM_LIT> ) & <NUM_LIT> ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode ,


<s> if ( Ty -> isIntOrIntVectorTy ( ) ) { ISD = IsUnsigned ? <STR_LIT> : <STR_LIT> ; } else { assert ( Ty -> isFPOrFPVectorTy ( ) && <STR_LIT> ) ; ISD = <STR_LIT> ; } static const CostTblEntry SSE1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE41CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT>


<s> static bool nds32_must_pass_in_stack ( const function_arg_info & arg


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getGPRMM16Reg ( ) )


<s> unsigned int proc ; size_t len = <NUM_LIT> ; sysctlbyname ( <STR_LIT> , & proc , & len , NULL , <NUM_LIT> ) ; if ( len > <NUM_LIT> ) switch ( proc ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . padShortFunctions ( ) ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . LEAusesAG ( ) ) { addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; ShouldPrint =


<s> case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT>


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo


<s> unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE2 ( ) || Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned RegNum = InVT . getSizeInBits


<s> for ( const auto & V : Defs ) if ( const PHINode * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( const auto & V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { User * First = dyn_cast < User >


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF .


<s> if ( x == pic_offset_table_rtx ) return true ; if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress || reload_in_progress ) && ORIGINAL_REGNO (

x ) == REGNO ( pic_offset_table_rtx ) ) return true ;


<s> DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true


<s> if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { printPCLabel ( MI , Op + <NUM_LIT> , O ) ; return ; } const MachineOperand & MO1 = MI -> getOperand ( Op ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; O << <STR_LIT> << getRegisterName ( MO1


<s> inline rtx base_reg_disp :: reg ( void ) const { return reg_


<s> inline unsigned UnknownPadding ( unsigned LogAlign , unsigned KnownBits ) { if ( KnownBits < LogAlign ) return ( <NUM_LIT> << LogAlign ) - ( <NUM_LIT>


<s> opc [ <NUM_LIT> ] = <STR_LIT> ; } else { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } } else { if ( TRI -> getRegSizeInBits ( Reg , MRI ) == <NUM_LIT> ) { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } else { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } } if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( opc [ <NUM_LIT> ] ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( opc [ <NUM_LIT> ] ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } if ( ! FBB ) return <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT>

&& VectorList . LaneIndex <= <NUM_LIT> ;


<s> unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT ,

Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> )


<s> Op = DAG . getVectorShuffle ( <STR_LIT> , DL , Op , DAG . getUNDEF ( <STR_LIT> ) , Mask ) ; return DAG . getNode ( <STR_LIT> ,


<s> } for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) if (

Succ != MBB ) findReturns ( Succ , Cycles ) ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { assert ( MBB -> getParent ( ) -> getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT ( ) ) ; return MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , MCSymbolRefExpr ::


<s> case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> __rv . __o = __builtin_neon_vld2v4hi ( ( const __builtin_neon_hi * )


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) { RetOps . push_back ( Flag ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


const * ) directive , XCOFF_CSECT_DEFAULT_ALIGNMENT_STR ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get (


<s> expand_set_or_cpymem_via_loop ( destmem , NULL , destptr , NULL , gen_lowpart ( QImode , value ) , count , QImode , <NUM_LIT> , max_size


<s> __v4si result ; if ( __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) { if ( __B < <NUM_LIT> ) rshift = ( __v4su ) vec_splat_s32 ( __B ) ; else rshift = ( __v4su ) vec_splats ( ( unsigned int ) __B ) ; } else rshift = vec_splats ( ( unsigned int ) __B ) ; } result = vec_sra ( ( __v4si ) __A , rshift


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> const MCExpr * Expr = getImm ( ) ; addExpr ( Inst ,


<s> static bool xstormy16_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) && !

LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) ) return true ;


<s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > (


<s> return inline_secondary_memory_needed ( class1 , class2 , mode ,


<s> inline vector signed short vec_packpx ( vector unsigned int a1 , vector unsigned


<s> EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: Cmp ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: AddSub ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void addAM2OffsetImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT>


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( )


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveR19R20X ( Offset ) ; return false


<s> return __builtin_mve_vsubq_uv4si ( __a ,


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst ,


<s> static SDValue combineFAndn ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N


<s> case <STR_LIT> : expandACCInstr ( MI , MBB , <STR_LIT> ) ; break ; case <STR_LIT> : expandACCInstr ( MI , MBB , <STR_LIT> ) ; break ; case <STR_LIT> : expandACCInstr ( MI , MBB , <STR_LIT> ) ; break ; case <STR_LIT> : expandACCInstr ( MI , MBB , <STR_LIT> ) ; break ; case <STR_LIT> : expandACCInstr ( MI , MBB , <STR_LIT> ) ; break ; case <STR_LIT> : expandACCInstr ( MI , MBB , <STR_LIT> ) ; break ; case <STR_LIT> : expandACCInstr ( MI , MBB


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return


<s> if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ; if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || Val ==


<s> int64_t Val = Memory . OffsetImm ? ( Memory . OffsetImm -> getValue ( ) / <NUM_LIT> ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand ::


<s> gcc_assert ( BYTES_BIG_ENDIAN ) ; gcc_assert ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) ) ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) for ( j = <NUM_LIT> ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + <NUM_LIT>


<s> unsigned long long res ; __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ( INTVAL ( count ) & ~ ( ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , <NUM_LIT> ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , <NUM_LIT> ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ( INTVAL ( count ) & ~ ( ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) )


<s> case <STR_LIT> : \ return <STR_LIT> # NAME ; switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi )


<s> } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; AddDefaultPred ( MIB ) ; NewMIs . push_back ( MIB


<s> if ( MO . isReg ( ) && MO . isDead ( ) && MO . getReg ( ) == <STR_LIT> ) MO . setIsDead ( false ) ; } return & MI ; } bool Is64Bit ; unsigned NewOpc = TII -> convertToFlagSettingOpc ( MI . getOpcode ( ) , Is64Bit ) ; unsigned NewDestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> hasOneNonDBGUse ( MI . getOperand ( <NUM_LIT> ) . getReg (

) ) ) NewDestReg = Is64Bit ? <STR_LIT> : <STR_LIT> ;


<s> int8x16x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT>


<s> void <ISA_LIT>LowOverheadLoops :: Expand ( LowOverheadLoop & LoLoop ) { auto ExpandLoopEnd = [ this ] ( LowOverheadLoop & LoLoop ) { MachineInstr * End = LoLoop . End ; MachineBasicBlock * MBB = End -> getParent ( ) ; unsigned Opc = LoLoop . IsTailPredicationLegal ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . ToRemove . insert ( LoLoop . Dec ) ; LoLoop . ToRemove . insert ( End ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop ) ; RemoveDeadBranch ( LoLoop . End ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) ConvertVPTBlocks ( LoLoop ) ; for ( auto * I : LoLoop . ToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; I -> eraseFromParent ( ) ; } } PostOrderLoopTraversal DFS ( LoLoop . ML , * MLI ) ; DFS . ProcessLoop ( ) ; const SmallVectorImpl < MachineBasicBlock * > & PostOrder = DFS . getOrder ( ) ; for ( auto * MBB :


<s> } unsigned ResMultiplier = VT . getVectorElementType ( ) . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { assert ( <NUM_LIT> * SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } assert ( SrcVT . getSizeInBits ( ) == <NUM_LIT> * VT . getSizeInBits ( ) ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; unsigned Imm = Src . MinElt * getExtFactor ( VEXTSrc1 ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy


<s> for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( R

-> getOperandUse ( <NUM_LIT> ) , PromotablePHINodes , Bool2IntMap ) ;


<s> __builtin_neon_vst1_lanev4hi ( ( __builtin_neon_hi * ) __a , (


<s> return __builtin_aarch64_crypto_pmulldi_ppp ( a , b


<s> pcmpgtb_u ( uint8x8_t s , uint8x8_t t ) { return __builtin_loongson_pcmpgtb_u ( s , t )


<s> assert ( Factor >= <NUM_LIT> && <STR_LIT> ) ; auto * VecVTy = cast < VectorType > ( VecTy ) ; if ( ! UseMaskForCond && ! UseMaskForGaps && Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) ) { unsigned NumElts = VecVTy -> getNumElements ( ) ; auto * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts /


<s> int Offset = Addr . Offset ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { int Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand ( MMO ) ; } else { MIB . addReg ( Addr . Base . Reg ) ; if ( useAM3 ) { int Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> )


<s> cvtStWriteBackRegAddrMode2 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode2Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands (


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rt = getReg ( Decoder , <STR_LIT> , Rt ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst


<s> const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; setAction ( { G_IMPLICIT_DEF , s64 } , Legal ) ; setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op ,


<s> const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ; } } Fixups . push_back ( MCFixup :: create ( Offset , Expr , ( MCFixupKind ) Kind , Loc ) ) ; if ( AllowTLS && OpNum + <NUM_LIT> < MI . getNumOperands ( ) ) { const MCOperand & MOTLS = MI . getOperand ( OpNum + <NUM_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MOTLS . getExpr ( ) , ( MCFixupKind ) <STR_LIT> , Loc ) ) ; } return <NUM_LIT>


<s> return ( __mmask32 ) __builtin_ia32_ucmpb256_mask ( ( __v32qi ) __X , ( __v32qi )


<s> if ( ! extended && n == <NUM_LIT> ) return arm_fp16_format == ARM_FP16_FORMAT_IEEE ? HFmode : VOIDmode ; return default_floatn_mode ( n , extended


<s> if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > <NUM_LIT> ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI


<s> std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( Ty ) ; int ISD = InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; static const <ISA_LIT>CostTblEntry AVX1CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST . hasAVX ( ) ) { int Idx = FindInTable ( AVX1CostTable , array_lengthof ( AVX1CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [


<s> virtual void EmitValueImpl ( const MCExpr *


<s> if ( reg == NULL && ! reload_in_progress && ! reload_completed ) reg = gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( orig ) == CONST ) { rtx reg_temp ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; reg_temp = ! can_create_pseudo_p ( ) ? reg : gen_reg_rtx ( Pmode


<s> auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Info . Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Info . Callee . getReg ( ) ; if ( CalleeReg && ! Register :: isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Info . Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : Info . OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , Info . CallConv ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , Info . IsVarArg ) ; OutgoingValueAssigner ArgAssigner ( ArgAssignFn ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , ArgInfos , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; MIRBuilder . insertInstr (


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . BaseRegNum == <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return false ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || (

Val > - <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> inline vector float vec_vaddfp ( vector float


<s> const APInt & ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , DL ) ; } return SDValue (


<s> MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( ! Result ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result


<s> return __builtin_aarch64_fix_trunchfdi (


<s> if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )

. Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return __builtin_mve_vmaxaq_m_sv4si ( __a ,


<s> MachineBasicBlock * MBB = End -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; MachineBasicBlock * Latch = End -> getParent ( ) ; MachineInstr * Terminator = & Latch -> instr_back ( ) ; if ( End != Terminator ) { MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Latch -> isLayoutSuccessor ( Exit ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } End -> eraseFromParent ( ) ; Dec -> eraseFromParent ( ) ; } ; auto ExpandBranch = [ this ] ( MachineInstr * Dec , MachineInstr * End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * MBB = Dec -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Dec , Dec -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Dec -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( Dec -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> )


<s> return ( int16x4_t ) __builtin_neon_vreinterpretv4hiv8qi ( (


<s> FunctionPass * llvm :: create<ISA_LIT>RegisterAllocator ( ) { return new <ISA_LIT>RegisterAllocator


<s> offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == <NUM_LIT> && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < <NUM_LIT> ; regno ++ ) { if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += fp_reg_size ; } } if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; if ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) ) bitmap_set_bit ( components ,


<s> unsigned Val = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Val |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= sign1


<s> if ( MachineJumpTableInfo * JtInfo = MF . getJumpTableInfo ( ) ) { const std :: vector < MachineJumpTableEntry > & JT = JtInfo -> getJumpTables ( ) ; for ( unsigned I = <NUM_LIT> ; I < JT . size ( ) ; ++ I ) { const std :: vector < MachineBasicBlock * > & MBBs = JT [ I ] . MBBs ; for ( unsigned J = <NUM_LIT> ; J < MBBs . size ( ) ; ++ J ) MBBs [ J ] -> setAlignment


<s> void <ISA_LIT>InstPrinter :: printMSRSystemRegister ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm


<s> if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency <= <NUM_LIT> )


<s> static void arm_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == <NUM_LIT> ) ; fputs ( <STR_LIT> , file ) ; output_addr_const ( file


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; auto Pred = Parser . getTok ( ) . getString ( ) . lower ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const char * ZM = Pred == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ZM , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex


<s> SwapVector [ UseIdx ] . WillRemove = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( UseMI . dump ( ) ) ; } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { int Repr = EC -> getLeaderValue ( SwapVector [ EntryIdx ] . VSEId ) ; if ( ! SwapVector [ Repr ] . WebRejected ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; int DefIdx = SwapMap [ DefMI ] ; SwapVector [ DefIdx ] . WillRemove = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ) ; } } else if ( SwapVector [ EntryIdx ] . IsSwappable && SwapVector [ EntryIdx ] . SpecialHandling != <NUM_LIT> ) { int Repr = EC -> getLeaderValue ( SwapVector [ EntryIdx ] . VSEId ) ; if ( ! SwapVector [ Repr ] . WebRejected

) handleSpecialSwappables ( EntryIdx ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Extract128BitVector ( Op0 , <NUM_LIT> , DAG , DL ) ; SDValue RHS = Extract128BitVector ( Op0 , NumElems / <NUM_LIT> , DAG , DL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LowerVectorCTPOPInRegLUT ( LHS , DL , Subtarget , DAG )

, LowerVectorCTPOPInRegLUT ( RHS , DL , Subtarget , DAG ) ) ;


<s> unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( regs == <NUM_LIT> || regs > <NUM_LIT> || ( Vd + regs ) > <NUM_LIT> ) { regs = Vd + regs > <NUM_LIT> ? <NUM_LIT> - Vd : regs ; regs = std :: max ( <NUM_LIT> , regs ) ; regs = std :: min ( <NUM_LIT> , regs ) ; S = MCDisassembler


<s> SysAlias ( const char * N , uint16_t E , FeatureBitset F ) : Name ( N ) , Encoding ( E ) , FeaturesRequired ( F


<s> unsigned getT2AddrModeImm12OpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>