<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveKnownElts = true ) { EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; APInt KnownUndef , KnownZero ; unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnes


<s> return ELF :: R_MIPS_PC26_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_DTPRel_4 : return ELF :: R_MIPS_TLS_DTPREL32 ; case FK_DTPRel_8 : return ELF :: R_MIPS_TLS_DTPREL64 ; case FK_TPRel_4 : return ELF :: R_MIPS_TLS_TPREL32 ; case FK_TPRel_8 : return ELF :: R_MIPS_TLS_TPREL64 ; case FK_GPRel_4 : if ( is64Bit ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> :


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ]


<s> int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return true ; return false


<s> std :: unique_ptr < MCObjectTargetWriter > create<ISA_LIT>WinCOFFObjectWriter ( bool Is64Bit ) { return llvm :: make_unique < <ISA_LIT>WinCOFFObjectWriter > (


<s> static bool mips_vector_mode_supported_p ( enum machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : return TARGET_DSP


<s> if ( ArgTy -> isFP128Ty ( ) ) { int FI = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Chain = DAG . getStore ( Chain , DL , Entry . Node , FIPtr , MachinePointerInfo ( ) , Align ( <NUM_LIT> ) ) ; Entry . Node = FIPtr ; Entry . Ty = PointerType :: getUnqual ( ArgTy ) ; } Args . push_back ( Entry ) ; return Chain


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; return Modified


<s> unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; unsigned align = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) { size = <NUM_LIT> ; align = <NUM_LIT> ; } else { if ( size == <NUM_LIT> ) { size = <NUM_LIT> << size ; align *= <NUM_LIT> ; } else { size = <NUM_LIT> << size ; align *= <NUM_LIT> * size ; } } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; else if ( Rm


<s> isFirst = isSingle = isCracked = isLoad = isStore = false ; return <STR_LIT> ; } Opcode = ~ Opcode ; const MCInstrDesc & MCID = TII . get ( Opcode ) ; isLoad = MCID . mayLoad ( ) ; isStore = MCID . mayStore ( ) ; uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags & <STR_LIT> ; isCracked = TSFlags


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result )


<s> bool is64bit = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi ,


<s> static __inline __m64 _mm_subaddhx_pi16 ( __m64 a , __m64 b ) { return ( __m64 ) __builtin_arm_wsubaddhx ( ( __v4hi ) a , ( __v4hi )


<s> } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return <NUM_LIT> ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= <NUM_LIT> ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return <NUM_LIT> ; } if ( Inst && ST -> hasVFP2Base ( ) && isFPSatMinMaxPattern ( Inst , Imm ) ) return <NUM_LIT> ; if ( Inst && Opcode == Instruction :: ICmp && Idx == <NUM_LIT> && Imm


<s> unsigned Reg = <NUM_LIT> ; int64_t Off ; if ( parseSEHRegisterNumber ( <STR_LIT> , Reg ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) )


<s> case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_FPTOSI : { auto & Op0 = MI . getOperand ( <NUM_LIT> ) ; auto & Op1 = MI . getOperand ( <NUM_LIT> ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool FirstArgIsFP = Opc == TargetOpcode :: G_SITOFP ; bool SecondArgIsFP = Opc == TargetOpcode :: G_FPTOSI ; OpRegBankIdx [ <NUM_LIT> ] = getPartialMappingIdx ( Ty0 , FirstArgIsFP ) ; OpRegBankIdx [ <NUM_LIT> ] = getPartialMappingIdx ( Ty1 , SecondArgIsFP ) ; break ; } case TargetOpcode :: G_FCMP : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty1 . getSizeInBits ( ) == Ty2 . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Size = Ty1 . getSizeInBits ( ) ; ( void ) Size ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto FpRegBank = getPartialMappingIdx ( Ty1 , true ) ; OpRegBankIdx = { PMI_GPR8 , PMI_None


<s> OutStreamer -> EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> EmitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT>


<s> if ( LastEMSInfo -> State == EMS_Thumb ) return ; FlushPendingMappingSymbol ( ) ; EmitMappingSymbol ( <STR_LIT> ) ; LastEMSInfo -> State


<s> case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . createTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr


<s> unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( isParsingInlineAsm ( ) ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Tok . getLoc ( ) ) ) ; int64_t ImmDisp = Tok . getIntVal ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( Start , <STR_LIT> ) ; return ParseIntelBracExpression ( SegReg , Start , ImmDisp , Size ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Start , ImmDisp , Size ) ; if ( ! ParseRegister ( SegReg , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( Start , <STR_LIT> ) ; return ParseIntelBracExpression ( SegReg , Start , ImmDisp , Size ) ; } const MCExpr * Val ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok .


<s> return false ; } TM = & MF . getTarget ( ) ; if ( ! TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . padShortFunctions ( ) ) return false ; TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; ReturnBBs . clear ( ) ; VisitedBBs . clear ( ) ; findReturns ( MF . begin ( ) ) ; bool MadeChange = false ; MachineBasicBlock * MBB ; unsigned int Cycles = <NUM_LIT> ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( The<ISA_LIT>LETarget ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( The<ISA_LIT>BETarget ) ; RegisterTargetMachine < ThumbLETargetMachine > A ( TheThumbLETarget


<s> const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( Reg , RegState :: Kill ) ; MBB . erase ( II


<s> unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT , N0 , Sz , DAG ) ; SDValue Amt = DAG . getConstant ( EltTy . getSizeInBits ( ) - lg2 , <STR_LIT> ) ; SDValue SRL = getTargetVShiftNode ( <STR_LIT> , dl , VT , SGN , Amt , DAG ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SDValue Lg2Amt = DAG . getConstant ( lg2 , <STR_LIT> ) ; SDValue SRA = getTargetVShiftNode ( <STR_LIT> , dl , VT , ADD , Lg2Amt , DAG ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ; SmallVector < SDValue , <NUM_LIT> > V ( NumElts ,

DAG . getConstant ( <NUM_LIT> , EltTy ) ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; const unsigned NumFields = <NUM_LIT> ; SDValue Fields [ NumFields ] = { DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) , false , false , <NUM_LIT> ) ; Offset +=


<s> else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , <STR_LIT> ) ; emitInst ( TargetOpcode :: COPY , <STR_LIT> ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask (


<s> void <ISA_LIT>AsmPrinter :: EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) { MCInst I ; I . setOpcode ( Opcode


<s> SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; auto USUBSATBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { SubusLHS , SubusRHS } , USUBSATBuilder ) ; KnownBits Known = DAG . computeKnownBits ( SubusLHS ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc ( SubusLHS ) , ExtType ) ; SDValue UMin = DAG . getNode ( <STR_LIT> , SDLoc ( SubusLHS ) , ExtType , SubusRHS , SaturationConst ) ; SDValue NewSubusLHS = DAG . getZExtOrTrunc ( SubusLHS , SDLoc ( SubusLHS ) , ShrinkedType ) ; SDValue NewSubusRHS = DAG . getZExtOrTrunc ( UMin , SDLoc ( SubusRHS ) ,


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SubusRHS = Op1 ; SDValue MaxLHS = Op0 . getOperand ( <NUM_LIT> ) ; SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; auto USUBSATBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { SubusLHS , SubusRHS } , USUBSATBuilder ) ; KnownBits Known ; DAG . computeKnownBits ( SubusLHS , Known ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc ( SubusLHS ) , ExtType ) ; SDValue UMin = DAG . getNode ( <STR_LIT> , SDLoc ( SubusLHS ) , ExtType , SubusRHS , SaturationConst ) ; SDValue NewSubusLHS = DAG . getZExtOrTrunc ( SubusLHS , SDLoc ( SubusLHS ) , ShrinkedType ) ; SDValue NewSubusRHS = DAG . getZExtOrTrunc ( UMin , SDLoc ( SubusRHS ) , ShrinkedType ) ; SDValue Psubus = SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , ShrinkedType , { NewSubusLHS , NewSubusRHS } , USUBSATBuilder ) ; return DAG . getZExtOrTrunc ( Psubus , SDLoc ( N ) ,


<s> extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2


<s> static MachineBasicBlock * getTargetMBB ( const MachineInstr & Br ) { for ( unsigned I = <NUM_LIT> , E = Br . getDesc (

) . getNumOperands ( ) ; I < E ; ++ I ) {


<s> bool IsSigned = Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ; SDValue Src = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT DstVT = Op . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) return Op ; if ( SrcVT == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) { SDNodeFlags Flags ; Flags . setNoFPExcept ( Op -> getFlags ( ) . hasNoFPExcept ( ) ) ; if ( IsSigned ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Op . getOperand ( <NUM_LIT> ) , Lo , Hi } , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Res . getValue ( <NUM_LIT> ) , Res } , Flags ) ; } else { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } } else { const uint64_t TwoE31 [ ] = { <NUM_LIT>


<s> static <ISA_LIT>Operand CreateReg ( unsigned RegNum , bool Writeback ) { <ISA_LIT>Operand Res ; Res . Kind = Register ; Res . Reg . RegNum


<s> if ( ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) || ! Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal ( ) ; if ( ShiftAmount < <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc


<s> if ( ( Subtarget -> hasSSE3 ( ) || Subtarget -> hasAVX ( ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode (

<STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const unsigned * CURegs = ( Is64Bit ? CU64BitRegs : CU32BitRegs ) ; uint32_t RenumRegs [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> - RegCount ; i < <NUM_LIT> ; ++ i ) { int CUReg = getCompactUnwindRegNum ( CURegs , SavedRegs [ i ] ) ; if ( CUReg == - <NUM_LIT> ) return ~ <NUM_LIT> ; SavedRegs [ i ] = CUReg ; unsigned Countless = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> - RegCount ; j < i ; ++ j ) if ( SavedRegs [ j ] < SavedRegs [ i ] ) ++ Countless ; RenumRegs [ i ] = SavedRegs [ i ] - Countless - <NUM_LIT> ; } uint32_t permutationEncoding = <NUM_LIT> ; switch ( RegCount ) { case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> *


<s> if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , false ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Register , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; Flags . setOrigAlign ( DL . getABITypeAlign


<s> if ( TARGET_ISR_VECTOR_SIZE_4_BYTE ) builtin_define ( <STR_LIT> ) ; else builtin_define ( <STR_LIT> ) ; } if ( TARGET_HARD_FLOAT ) builtin_define ( <STR_LIT> ) ; else builtin_define ( <STR_LIT> ) ; if ( TARGET_ISA_V2 ) builtin_define ( <STR_LIT> ) ; if ( TARGET_ISA_V3 ) builtin_define ( <STR_LIT> ) ; if ( TARGET_ISA_V3M ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FPU_SINGLE ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FPU_DOUBLE ) builtin_define ( <STR_LIT> ) ; if ( TARGET_EXT_FPU_FMA ) builtin_define ( <STR_LIT> ) ; if ( NDS32_EXT_FPU_DOT_E ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { switch ( nds32_fp_regnum ) { case <NUM_LIT> : case <NUM_LIT> : builtin_define ( <STR_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : builtin_define ( <STR_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : builtin_define ( <STR_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : builtin_define ( <STR_LIT> ) ; break ; default : abort ( ) ; } } if ( TARGET_BIG_ENDIAN ) builtin_define ( <STR_LIT> ) ; else builtin_define ( <STR_LIT> ) ; if ( TARGET_REDUCED_REGS ) builtin_define ( <STR_LIT> ) ; if ( TARGET_CMOV ) builtin_define ( <STR_LIT> ) ; if ( TARGET_EXT_PERF ) builtin_define


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode ==

CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ;


<s> y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) , ( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ; result = vec_or ( vec_sll ( ( qword ) ( a ) , x )


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl


<s> if ( U ) Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <STR_LIT> , imm ) ) ) ; else Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <STR_LIT> , imm ) ) ) ; return S


<s> if ( STI . isTargetXPLINK64 ( ) ) return std :: make_unique < <ISA_LIT>XPLINKFrameLowering > ( ) ; return std :: make_unique < <ISA_LIT>ELFFrameLowering >


<s> break ; } if ( lFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( ppFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> mode != MODE_16BIT && isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_ADSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( insn -> mode == MODE_16BIT && insn -> opcodeType == ONEBYTE && insn -> opcode == <NUM_LIT> ) attrMask ^= ATTR_ADSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT && insn -> vectorExtensionType != TYPE_NO_VEX_XOP ) { if ( ( insn -> vectorExtensionType == TYPE_EVEX && wFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_VEX_3B && wFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_XOP && wFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) { uint16_t instructionIDWithREXW ; if ( getIDWithAttrMask ( & instructionIDWithREXW , insn , attrMask | ATTR_REXW ) ) { insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT> ; } const char * SpecName = GetInstrName ( instructionIDWithREXW , miiArg ) ; if ( ! is64Bit ( SpecName ) ) { insn -> instructionID = instructionIDWithREXW ; insn -> spec = specifierForUID ( instructionIDWithREXW ) ; return <NUM_LIT> ; } } } if ( insn -> opcodeType == ONEBYTE && ( ( insn -> opcode & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_ADSIZE ; if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_OPSIZE ; if ( insn -> mode == MODE_16BIT ) attrMask ^= ATTR_ADSIZE | ATTR_OPSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT>


<s> OptForSize = MF . getFunction ( ) . optForSize ( ) ; OptForMinSize = MF . getFunction ( ) . optForMinSize ( ) ; assert ( ( ! OptForMinSize || OptForSize ) && <STR_LIT> ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHEpilogStart (


<s> } else if ( Subtarget -> isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT>


<s> int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> getSymbol ( ) . isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress (


<s> while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) . second ) continue ; if ( MemSDNode * ChainLD = dyn_cast < MemSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ; } else LoadRoots . insert


<s> return __builtin_mve_vbicq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> else type = build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ; type = build_distinct_type_copy ( type ) ; SET_TYPE_STRUCTURAL_EQUALITY ( type ) ; tree mangled_name = get_identifier ( arm_simd_types [ i ] . mangle ) ; tree value = tree_cons ( NULL_TREE , mangled_name , NULL_TREE ) ; TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , value , TYPE_ATTRIBUTES ( type ) ) ; arm_simd_types [ i ] . itype = type ; } tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; arm_simd_intOI_type_node = AARCH_BUILD_SIGNED_TYPE ( OImode ) ; arm_simd_intEI_type_node = AARCH_BUILD_SIGNED_TYPE ( EImode ) ; arm_simd_intCI_type_node = AARCH_BUILD_SIGNED_TYPE ( CImode ) ; arm_simd_intXI_type_node = AARCH_BUILD_SIGNED_TYPE ( XImode ) ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intEI_type_node ) ; TYPE_NAME ( arm_simd_intEI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intOI_type_node ) ; TYPE_NAME ( arm_simd_intOI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intCI_type_node ) ; TYPE_NAME ( arm_simd_intCI_type_node ) =


<s> if ( ST -> hasNEON ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: printThumbITMask ( const MachineInstr * MI , int Op , raw_ostream & O ) { unsigned Mask = MI -> getOperand ( Op ) . getImm ( ) ; unsigned CondBit0 = Mask >> <NUM_LIT> & <NUM_LIT> ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) &


<s> if ( VT . isVector ( ) && isTypeLegal ( VT ) && DAG . isConstantIntBuildVectorOrConstantInt ( N -> getOperand ( <NUM_LIT> ) ) ) return DAG . UnrollVectorOp ( N ) ; return SDValue ( )


<s> bool isFGRH32Asm ( ) const { return ( Kind == k_Register ) &&


<s> emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0


<s> return mips_split_move_p ( dest , src , mips_insn_split_type (


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F


<s> asm_output_aligned_bss ( FILE , DECL , NAME , SIZE , ALIGN ) { \ typedef ( * pfunc ) ( ) ; \ extern pfunc __ctors [ ] ; \ extern pfunc __ctors_end [ ] ; \ pfunc * p ; \ for ( p = __ctors_end ; p > __ctors ;


<s> bool evaluateConstantImm ( int64_t & Imm , <ISA_LIT>MCExpr :: VariantKind & VK ) const { const MCExpr * Val = getImm ( ) ; bool Ret = false ; if ( auto * RE = dyn_cast <


<s> const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; Function :: const_arg_iterator FuncArg = Func . arg_begin ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) && ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_FixedArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , CCInfo . getInRegsParamsCount ( ) > <NUM_LIT> ) ; unsigned CurArgIdx = <NUM_LIT> ; CCInfo . rewindByValRegsInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . isOrigArg ( ) ) { std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ i ] . getOrigArgIndex ( ) ; } EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Ins [ i ] . isOrigArg ( ) && <STR_LIT> ) ; unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , FirstByValReg , LastByValReg , VA , CCInfo ) ; CCInfo . nextInRegsParam ( ) ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL


<s> if ( FValIsAllZeros && Subtarget . hasAVX512 ( ) && Cond . hasOneUse ( ) && CondVT . getVectorElementType ( ) == <STR_LIT> ) { SDValue CondNew = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , DAG . getAllOnesConstant ( DL , CondVT ) ) ; return DAG . getSelect ( DL , VT , CondNew , RHS , LHS ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT , Cond ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( CondVT


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> || SrcRC == <STR_LIT> || SrcRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> || DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( ! TARGET_64BIT && GET_MODE_INNER ( mode ) == TImode ) return false ; if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode


<s> bool hasZeroCycleZeroingFPWorkaround ( ) const { return HasZeroCycleZeroingFPWorkaround


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < ReachingDefAnalysis >


<s> return ( __m512i ) __builtin_ia32_expandloadhi512_maskz ( ( const __v32hi * ) __B ,


<s> int AddrOffset = <STR_LIT> ( Descl . TSFlags ) ; assert ( AddrOffset != - <NUM_LIT> && <STR_LIT> ) ; AddrOffset += <STR_LIT> ( Descl


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_ADD : case G_SEXT : case G_ZEXT : case G_GEP : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_LOAD : case G_STORE : OperandsMapping = Ty . getSizeInBits ( ) == <NUM_LIT> ? getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) : & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : assert ( ( Ty . getSizeInBits ( ) == <NUM_LIT> || Ty . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Ty . getSizeInBits ( ) == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_SEQUENCE : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) != <NUM_LIT> ) return InstructionMapping { } ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; } case G_EXTRACT : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) % <NUM_LIT> != <NUM_LIT> ) return InstructionMapping { } ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , nullptr , nullptr } ) ; break ; } default : return InstructionMapping { } ; } for ( unsigned i = <NUM_LIT> ; i < NumOperands ; i ++ ) { for ( const auto & Mapping : OperandsMapping [ i ]


<s> bool <ISA_LIT>TTIImpl :: emitGetActiveLaneMask ( Loop * L , LoopInfo * LI , ScalarEvolution & SE


<s> if ( TARGET_64BIT && CASE_VECTOR_MODE == DImode ) directive = ASM_QUAD ; gcc_assert ( ! TARGET_64BIT ) ; if ( TARGET_64BIT || TARGET_VXWORKS_RTP ) fprintf ( file , <STR_LIT> , directive , LPREFIX , value , LPREFIX , rel ) ; else if ( HAVE_AS_GOTOFF_IN_DATA ) fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value ) ; else if ( TARGET_MACHO ) { fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value


<s> machine_mode mode_with_wider_elts = aarch64_sve_int_mode ( GET_MODE ( dest ) ) ; machine_mode mode_with_narrower_elts = aarch64_sve_int_mode ( GET_MODE ( src ) ) ; if ( GET_MODE_UNIT_SIZE ( mode_with_wider_elts ) < GET_MODE_UNIT_SIZE ( mode_with_narrower_elts ) ) std ::

swap ( mode_with_wider_elts , mode_with_narrower_elts ) ;


<s> gcc_assert ( ! TARGET_FDPIC ) ; reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { if ( TARGET_FDPIC ) insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32_FDPIC ) ; else insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : if ( TARGET_FDPIC ) { sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32_FDPIC ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; emit_insn ( gen_addsi3 ( reg , reg , gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ) ) ; emit_move_insn ( reg , gen_rtx_MEM ( Pmode , reg ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x

, GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ;


<s> if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget -> isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> == <NUM_LIT> ) ; Reg >>= <NUM_LIT> ; } } else if ( Prefix == <STR_LIT> ) RC = TRI -> getRegClass ( <STR_LIT> ) ; else if ( Prefix == <STR_LIT> )


<s> if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . classifyGlobalReference ( AM . BaseGV ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || isPositionIndependent ( ) ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case


<s> bool useLoadStackGuardNode ( ) const override { return


<s> to_close = <STR_LIT> ; ++ count_string ; if ( count_string >= <NUM_LIT> ) { fputs ( to_close , file ) ; for_string = <STR_LIT> ; for_decimal = <STR_LIT> ; to_close = NULL ; count_string = <NUM_LIT> ; } } else { if ( for_decimal ) fputs ( for_decimal , file ) ; fprintf ( file , <STR_LIT> , c ) ; for_string = <STR_LIT> ; for_decimal = <STR_LIT>


<s> if ( CI -> hasOneUse ( ) && CI -> getParent ( ) == I -> getParent ( ) ) { ZExtCondReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitCmp ( ZExtCondReg , CI ) ) return false ; } } if ( ZExtCondReg == <NUM_LIT> ) { unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = TID . getNumOperands ( ) ; i != e ; ++ i ) if ( TID . OpInfo [ i ] . isPredicate (


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum


<s> if ( Cmp == Result ) return ( Cmp . getValueType ( ) == <STR_LIT> || Cmp . getValueType ( ) == <STR_LIT> ) ; ConstantFPSDNode * CCmp = dyn_cast < ConstantFPSDNode > ( Cmp ) ; ConstantFPSDNode * CResult = dyn_cast < ConstantFPSDNode > ( Result ) ; if ( CCmp && CResult && Cmp . getValueType ( ) == <STR_LIT> && Result . getValueType ( ) == <STR_LIT> ) { bool Lossy ; APFloat CmpVal = CCmp -> getValueAPF ( ) ; CmpVal . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Lossy ) ; return CResult -> getValueAPF ( ) . bitwiseIsEqual ( CmpVal ) ; } return Result -> getOpcode ( ) == <STR_LIT> && Result -> getOperand (


<s> return new <ISA_LIT>SEInstrInfo ( STI )


<s> const <ISA_LIT>Subtarget * STICaller = & TM . getSubtarget < <ISA_LIT>Subtarget > ( * Caller ) ; assert ( ! STICaller -> isUsingPCRelativeCalls ( ) && <STR_LIT> ) ; GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; if ( ! G ) return false ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , GV ) ) return false ; const Function * F = dyn_cast < Function > ( GV ) ; const GlobalAlias * Alias = dyn_cast < GlobalAlias > ( GV ) ; if ( Alias


<s> return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Call : if ( dyn_cast < IntrinsicInst > ( I ) ) return false ; return SelectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I


<s> if ( GET_MODE_UNIT_SIZE ( mode ) == <NUM_LIT> ) return aarch64_tune_params . min_div_recip_mul_sf ; return aarch64_tune_params


<s> Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; } for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) / <NUM_LIT> ; i < e ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL ,

<STR_LIT> , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ;


<s> Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian ) { return createELFObjectWriter ( llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ,


<s> static void emit<ISA_LIT>RegPlusImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , unsigned BaseReg , int NumBytes , <STR_LIT> Pred , unsigned PredReg , const TargetInstrInfo & TII , DebugLoc dl ) { bool isSub = NumBytes < <NUM_LIT> ; if ( isSub ) NumBytes = - NumBytes ; while ( NumBytes ) { unsigned RotAmt = <STR_LIT> ( NumBytes ) ; unsigned ThisVal = NumBytes & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; assert ( ThisVal && <STR_LIT> ) ; NumBytes &= ~ ThisVal ; int SOImmVal = <STR_LIT> ( ThisVal ) ; assert ( SOImmVal != - <NUM_LIT>


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI ,


<s> <ISA_LIT>FlagsCopyLoweringPass ( ) :


<s> if ( BlockCount < InspectionLimit ) { MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; int LimitLeft = InspectionLimit - BlockCount ; for ( MachineBasicBlock :: pred_iterator PB = MBB -> pred_begin ( ) , PE = MBB -> pred_end ( ) ; PB != PE ; ++ PB ) { MachineBasicBlock * PMBB = * PB ; int PredCount = <NUM_LIT> ; for ( MachineBasicBlock :: reverse_iterator PBInst = PMBB -> rbegin ( ) , PME = PMBB -> rend ( ) ; PBInst != PME ; ++ PBInst ) { PredCount ++ ; if ( PredCount >= LimitLeft ) break ; if ( PBInst -> getDesc ( ) . isCall


<s> AlignBranchType . addKind ( <STR_LIT> ) ; AlignBranchType . addKind ( <STR_LIT> ) ; } if ( <ISA_LIT>AlignBranchBoundary . getNumOccurrences ( ) ) AlignBoundary = assumeAligned ( <ISA_LIT>AlignBranchBoundary ) ; if ( <ISA_LIT>AlignBranch . getNumOccurrences (

) ) AlignBranchType = <ISA_LIT>AlignBranchKindLoc ;


<s> unsigned getValueBit ( int64_t Val , unsigned


<s> if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue ( ) ; MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } int MaskLO = Mask [ <NUM_LIT> ] ; if ( MaskLO == SM_SentinelUndef ) MaskLO = Mask [ <NUM_LIT> ] == SM_SentinelUndef ? <NUM_LIT> : Mask [ <NUM_LIT> ] ; int MaskHI = Mask [ <NUM_LIT> ] ; if ( MaskHI == SM_SentinelUndef ) MaskHI = Mask [ <NUM_LIT> ] == SM_SentinelUndef ? <NUM_LIT> : Mask [ <NUM_LIT> ] ; unsigned PermMask = MaskLO / <NUM_LIT> | ( MaskHI / <NUM_LIT> ) << <NUM_LIT> ; if ( IsV1Zero ) { V1 = DAG . getUNDEF ( VT ) ; if ( MaskLO < <NUM_LIT> ) PermMask = ( PermMask & <NUM_LIT> ) | <NUM_LIT> ; if ( MaskHI < <NUM_LIT> ) PermMask = (


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable (


<s> if ( SubReg ) return false ; if ( Register :: isVirtualRegister ( Reg ) ) return MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; return <STR_LIT> . contains


<s> bool isHiImm16And ( ) { if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ConstExpr ) { int64_t Value = ConstExpr -> getValue


<s> bool hasMOVDIR64B ( ) const { return HasMOVDIR64B


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return CInc -> getZExtValue ( ) ; case <STR_LIT> : { if ( DAG . haveNoCommonBitsSet ( Ptr , Inc ) ) { return CInc -> getZExtValue ( ) ; } return <NUM_LIT> ; } default : return


<s> Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) Known . Zero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static rtx or1k_function_value ( const_tree valtype , const_tree , bool ) { return gen_rtx_REG ( TYPE_MODE ( valtype )


<s> if ( STI -> isTargetDarwin ( ) ) return CSR_<ISA_LIT>_TLS_Darwin_RegMask ; assert ( STI -> isTargetELF ( ) && <STR_LIT>


<s> unsigned int abi_id = <NUM_LIT> ; rtx pat = PATTERN ( insn


<s> SDValue <ISA_LIT>TargetLowering :: getFramePointerFrameIndex ( SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT>


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregciv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t ) __builtin_aarch64_get_qregciv2di ( __o


<s> static SmallVector < int , <NUM_LIT> > getPSHUFShuffleMask ( SDValue N ) { MVT VT = N . getSimpleValueType ( ) ; SmallVector < int , <NUM_LIT> > Mask ; bool IsUnary ; bool HaveMask = getTargetShuffleMask ( N . getNode ( ) , VT , Mask , IsUnary ) ; ( void ) HaveMask ; assert ( HaveMask ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode ( ) ) { case <STR_LIT> : return Mask ; case <STR_LIT> : Mask . resize ( <NUM_LIT> ) ; return Mask ; case <STR_LIT> : Mask . erase ( Mask . begin ( ) , Mask


<s> bool OptSize = Attr . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT .


<s> return rs6000_mode_dependent_address_ptr (


<s> if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen


<s> RegisterTarget < Triple :: cjg > X (

getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , DImode , <NUM_LIT> ) ; hi_half [ num ] = adjust_address ( op , DImode , <NUM_LIT> ) ; } else { lo_half [ num ] = simplify_gen_subreg ( DImode


<s> AHi = DAG . getVectorShuffle ( VT , dl , A , A , ShufMask ) ; BHi = DAG . getVectorShuffle ( VT , dl , B , B , ShufMask ) ; AHi = DAG . getBitcast ( ExVT , AHi ) ; BHi = DAG . getBitcast ( ExVT , BHi ) ; AHi = DAG . getNode ( <STR_LIT> , dl , ExVT , AHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; BHi = DAG . getNode ( <STR_LIT> , dl , ExVT , BHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; } SDValue RLo = DAG . getNode ( <STR_LIT> , dl , ExVT , ALo , BLo ) ; SDValue RHi = DAG . getNode ( <STR_LIT> , dl , ExVT , AHi , BHi ) ; RLo = DAG . getNode ( <STR_LIT> , dl , ExVT , RLo , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; RHi = DAG . getNode ( <STR_LIT> , dl , ExVT , RHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RLo , RHi ) ; } if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && ! Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; SDValue AhiBlo =


<s> if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH

) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ;


<s> void <ISA_LIT>TargetStreamer :: emitPersonality ( const MCSymbol * Personality ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister (


<s> addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; addPass ( createMicro<ISA_LIT>SizeReducePass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( create<ISA_LIT>BranchExpansion ( ) )


<s> Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; } unsigned ConvOpcode = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( ConvOpcode , dl , ResVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Val ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; unsigned ByteSize = Op1VT . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Val , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( ByteSize , dl , false ) , DAG . getValueType ( Op1VT ) } ; Val = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , cast < StoreSDNode > ( N ) -> getMemoryVT ( ) , cast < StoreSDNode > ( N ) -> getMemOperand ( ) ) ; DCI . AddToWorklist ( Val . getNode ( ) ) ; return Val


<s> setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT IntVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; LegalizeAction Act = ( IntVT == <STR_LIT> ) ? Promote : Legal ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign


<s> inline SDValue getI32Imm ( uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm


<s> case UNSPEC_LDS : return BEGIN_CONTROL ; case UNSPEC_LDS_A : case UNSPEC_LDSA : return BEGIN_DATA


<s> return ( __m256i ) __builtin_ia32_pmovqd512_mask ( ( __v8di ) __A , ( __v8si )

_mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> } else if ( SignedVal >= INT32_MIN && SignedVal <= INT32_MAX ) { Extension = <STR_LIT> ; MemType = <STR_LIT> ; } else { Extension = <STR_LIT> ; MemType = <STR_LIT> ; } Constant * CV = ConstantInt :: get ( Type :: getIntNTy ( * CurDAG -> getContext ( ) , MemType . getSizeInBits ( ) ) , UnsignedVal ) ; SDValue PoolAddr = getConstantPoolItemAddress ( DL , CV ) ; unsigned Alignment = getTargetLowering ( ) -> getDataLayout ( ) -> getABITypeAlignment ( CV -> getType ( ) ) ; return CurDAG -> getExtLoad ( Extension , DL , DestType , CurDAG -> getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , MemType , false ,


<s> RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; MRI . addLiveOut ( <STR_LIT> ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & RetOps [


<s> } } if ( slot -> isCall ( ) ) insertCallDefsUses ( slot , RegDefs , RegUses ) ; else insertDefsUses ( slot , RegDefs , RegUses ) ; bool done = false ; MachineBasicBlock :: iterator I = slot ; while ( ! done ) { done = ( I == MBB . begin ( ) ) ; if ( ! done ) -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isPosition ( ) || I -> hasDelaySlot ( ) || I -> isBundledWithSucc ( ) ) break ; if ( delayHasHazard ( I , sawLoad , sawStore , RegDefs , RegUses ) ) { insertDefsUses ( I , RegDefs , RegUses ) ; continue ; } return I


<s> for ( auto & OrigArg : OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , CallConv , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , OrigArg . Reg , Offset ) ; } ) ; } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed = TLI . CCAssignFnForCall ( CallConv , false ) ; CCAssignFn * AssignFnVarArg = TLI . CCAssignFnForCall ( CallConv , true ) ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , <NUM_LIT>


<s> DebugLoc DL = MI . getDebugLoc ( ) ; if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> ) return false ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DemoteRegTo32 ( SrcReg ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( FlagUseZeroBasedSandbox ) return false ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( FlagUseZeroBasedSandbox


<s> Inst . addOperand ( MCOperand :: createImm ( JumpOffset ) ) ; return MCDisassembler


<s> emitDirectiveModuleFP ( ABIFlagsSection . getFpABI ( ) ,


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( <STR_LIT> , Res ) ) ; } unsigned FPOpcode ; switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue LogicOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue LogicOp1 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc DL0 ( N0 ) ; if ( N0 . hasOneUse ( ) && LogicOp0 . getOpcode ( ) == <STR_LIT> && LogicOp0 . hasOneUse ( ) && LogicOp0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp0 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp1 = DAG . getBitcast ( VT , LogicOp1 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp0 . getOperand ( <NUM_LIT> ) , CastedOp1 ) ; } if ( N0 . hasOneUse ( ) && LogicOp1 . getOpcode ( ) == <STR_LIT> && LogicOp1 . hasOneUse ( ) && LogicOp1 . getOperand ( <NUM_LIT> ) . getValueType ( )

== VT && ! isa < ConstantSDNode > ( LogicOp1 . getOperand ( <NUM_LIT> ) ) ) {


<s> HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( m -> fs . drap_valid ) { toffset = <NUM_LIT> - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( m -> fs . fp_valid ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len = tlen


<s> V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : Mask ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; assert ( NumV1Elements > <NUM_LIT> && <STR_LIT> ) ; assert ( ( NumV2Elements > <NUM_LIT> || V2IsUndef ) && <STR_LIT> ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : Mask . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) SumV2Indices += i ; else if ( Mask [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( Mask [ i ] >= <NUM_LIT> ) NumV1OddIndices += i % <NUM_LIT> ; if ( NumV2OddIndices < NumV1OddIndices ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; } } } if ( VT . is128BitVector ( ) ) return lower128BitVectorShuffle ( DL , Mask , VT


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRegs


<s> MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { SplitArgs . clear ( ) ; splitToValueTypes ( Info . OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } CallSeqStart . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Handler .


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> ; return Binary ; } Binary |= SBits << <NUM_LIT> ; unsigned Offset = <STR_LIT> ( MO1 . getImm ( ) ) ; assert ( Offset && <STR_LIT> ) ; if ( Offset == <NUM_LIT> ) Offset = <NUM_LIT> ; return Binary | ( Offset << <NUM_LIT> )


<s> inline bool isImmUnsignedi8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <=


<s> StructType * ST = dyn_cast < StructType > ( ExpectedType ) ; if ( ! ST ) return nullptr ; unsigned NumElts = Inst -> arg_size ( ) - <NUM_LIT> ; if ( ST -> getNumElements ( ) != NumElts ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { if ( Inst -> getArgOperand ( i ) -> getType ( ) != ST -> getElementType ( i ) ) return nullptr ; } Value * Res = UndefValue :: get ( ExpectedType ) ; IRBuilder < > Builder ( Inst ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { Value * L = Inst -> getArgOperand ( i ) ; Res = Builder . CreateInsertValue ( Res , L , i ) ; } return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst -> getType ( ) == ExpectedType ) return Inst ; return nullptr


<s> const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) -> setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! IsPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) CallOpc = <STR_LIT> ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG

. getIntPtrConstant ( BytesCalleePops , dl , true ) , InFlag , dl ) ;


<s> void DecodeZeroExtendMask ( unsigned SrcScalarBits , unsigned DstScalarBits , unsigned NumDstElts , bool IsAnyExtend , SmallVectorImpl < int > & Mask ) { unsigned Scale = DstScalarBits / SrcScalarBits ; assert ( SrcScalarBits < DstScalarBits && <STR_LIT>


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( SYMBOL_REF_P ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) && REG_P ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) && REGNO ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; } else if ( TARGET_ELF ) fputs ( <STR_LIT> , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x


<s> unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt


<s> else nwords = CEIL_NWORDS ( size ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nwords ) ) ; if ( size < UNITS_PER_WORD ) XVECEXP ( regs , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( unsigned int i = <NUM_LIT> ; i < nwords ; i ++ ) XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode ,

regno + i * mult ) , GEN_INT ( i * UNITS_PER_WORD ) ) ;


<s> switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( offset , HOST_WIDE_INT_C ( - <NUM_LIT> ) , HOST_WIDE_INT_C ( <NUM_LIT> ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K :


<s> static bool blockEndIsUnreachable ( const MachineBasicBlock & MBB , MachineBasicBlock :: const_iterator MBBI ) { return llvm :: all_of ( MBB . successors ( ) , [ ] ( const MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) ; } ) && std :: all_of ( MBBI , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI . isMetaInstruction (


<s> inline SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> } if ( strstr ( buf , <STR_LIT> ) != NULL ) { unsigned cvariant = parse_field ( buf ) ; if ( ! contains_core_p ( variants , cvariant ) ) { if ( n_variants == <NUM_LIT> ) goto not_found ; variants [ n_variants ++ ] = cvariant ; } continue ; } if ( strstr ( buf , <STR_LIT> ) != NULL ) { unsigned ccore = parse_field ( buf ) ; if ( ! contains_core_p ( cores , ccore ) ) { if ( n_cores == <NUM_LIT> ) goto not_found ; cores [ n_cores ++ ] = ccore ; } continue ; } if ( ! tune && ! processed_exts && strstr ( buf , <STR_LIT> ) != NULL ) { for ( i = <NUM_LIT> ; i < num_exts ; i ++ ) { char * p = NULL ; char * feat_string = concat ( aarch64_extensions [ i ] . feat_string , NULL ) ; bool enabled = true ; p = strtok ( feat_string , <STR_LIT> ) ; while ( p != NULL ) { if ( strstr ( buf , p ) == NULL ) { enabled = false ; break ; } p = strtok ( NULL , <STR_LIT> ) ; } if ( enabled ) extension_flags |= aarch64_extensions [ i ] . flag ; else extension_flags &= ~ ( aarch64_extensions [ i ] . flag ) ; } processed_exts = true ; } } fclose ( f ) ; f = NULL ; if ( n_cores == <NUM_LIT> || n_cores > <NUM_LIT> || ( n_cores == <NUM_LIT> && n_variants != <NUM_LIT> ) || imp == INVALID_IMP ) goto not_found ; if ( n_cores == <NUM_LIT> || arch ) { for ( i = <NUM_LIT> ; aarch64_cpu_data [ i ] . name != NULL ; i ++ ) if ( aarch64_cpu_data [ i ] . implementer_id == imp && cores [ <NUM_LIT> ] == aarch64_cpu_data [ i ] . part_no && ( aarch64_cpu_data [ i ] . variant == ALL_VARIANTS || variants [ <NUM_LIT> ] == aarch64_cpu_data [ i ] . variant ) ) break ; if ( aarch64_cpu_data [ i ] . name == NULL ) goto not_found ; if ( arch ) { const char * arch_id = aarch64_cpu_data [ i ] . arch ; aarch64_arch_driver_info * arch_info = get_arch_from_id ( arch_id ) ; if ( ! arch_info ) goto not_found ; res = concat ( <STR_LIT> ,


<s> if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false


<s> else gcc_unreachable ( ) ; if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src = cfun -> machine -> frame . arg_pointer_offset ; else gcc_unreachable (


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsi_u64 ( unsigned long long __X ) { return __blsi_u64 ( __X


<s> assert ( TT . isOSBinFormatELF ( ) ) ; std :: unique_ptr < MCSubtargetInfo > STI ( TM . getTarget ( ) . createMCSubtargetInfo ( TT . str ( ) , <STR_LIT> , <STR_LIT> ) ) ; assert ( STI && <STR_LIT> ) ; for ( auto & P : AsanMemaccessSymbols ) { MCSymbol * Sym = P . second ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_GROUP , <NUM_LIT> , Sym -> getName ( ) , true ) ) ; OutStreamer -> emitSymbolAttribute ( Sym , MCSA_ELF_TypeFunction ) ; OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Weak ) ; OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Hidden ) ; OutStreamer -> emitLabel ( Sym ) ; unsigned Reg = std :: get < <NUM_LIT> > ( P . first


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 ,

Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> const CmpInst * CI = cast < CmpInst > ( I ) ; Type * Ty = CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; unsigned MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant ( Zero ) ; bool isFloat = ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) ; unsigned CondReg = isFloat ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT>

) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) ;


<s> EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; int NumMaskElts = ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ; if ( ! ResVT . isVector ( ) || NumMaskElts == <NUM_LIT> ) return SDValue ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT ,


<s> bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get (


<s> return ( int16x4_t ) __builtin_neon_vqsubsv4hi (


<s> MCOperand MCOp ; if ( lowerOperand ( MO , MCOp ) ) OutMI . addOperand ( MCOp


<s> return Subtarget . isABI_O32 ( ) || VT . getSizeInBits


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getTestBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; return


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) .

Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V8SImode : V4SImode ; case DImode : return TARGET_AVX512F ? V8DImode : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V4DImode : V2DImode ; case SFmode : if ( TARGET_AVX512F ) return V16SFmode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V8SFmode ; else return V4SFmode ; case DFmode : if ( ! TARGET_VECTORIZE_DOUBLE )


<s> return ( MI . getDesc ( ) . TSFlags & <STR_LIT>


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>Target ,


<s> case SPRRegisterList : Registers = o . Registers ; break ; case CoprocNum : case CoprocReg : Cop = o . Cop ; break ; case Immediate : Imm = o . Imm ; break ; case MemBarrierOpt : MBOpt = o . MBOpt ; break ; case Memory : Mem = o .


<s> Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestOddReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestOddReg ) ; Offset +=


<s> if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; if ( OS . getAssembler ( ) . isBundlingEnabled (


<s> MCFragment * findAssociatedFragment ( )


<s> static bool mep_nongeneral_reg ( rtx x ) { while ( GET_CODE ( x ) == SUBREG ) x = XEXP (


<s> setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( RetCC_<ISA_LIT> ) ; <ISA_LIT>OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg


_mm512_setzero_pd ( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> static DecodeStatus DecodeVecShiftR8Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm


<s> stub_iterator stub_begin ( ) const { return CygMingStubs . begin ( )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT .

isPS4 ( ) ) this -> Options . TrapUnreachable = true ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) , dl ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StoreAddr


<s> return ( int64x2_t ) __builtin_neon_vmullsv2si (


<s> if ( ( SignedDivRem || UnsignedDivRem ) && Args . size ( ) == <NUM_LIT> ) { if ( const Constant * C = dyn_cast < Constant > ( Args [ <NUM_LIT> ] ) ) { const ConstantInt * CVal = ( C -> getType ( ) -> isVectorTy ( ) ? dyn_cast_or_null < const ConstantInt > ( C -> getSplatValue ( ) ) : dyn_cast < const ConstantInt > ( C ) ) ; if ( CVal != nullptr && ( CVal -> getValue ( ) . isPowerOf2 ( ) || ( - CVal -> getValue ( ) ) . isPowerOf2 ( ) ) ) DivRemConstPow2 = true ; else DivRemConst = true ; } } if ( Ty -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned VF = Ty -> getVectorNumElements ( ) ; unsigned NumVectors = getNumVectorRegs ( Ty ) ; if ( Opcode == Instruction :: Shl || Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) { return NumVectors ; } if ( DivRemConstPow2 ) return ( NumVectors * ( SignedDivRem ? SDivPow2Cost : <NUM_LIT> ) ) ; if ( DivRemConst ) return VF * DivMulSeqCost + getScalarizationOverhead ( Ty , Args ) ; if ( ( SignedDivRem || UnsignedDivRem ) && VF > <NUM_LIT> ) return <NUM_LIT> ; if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode

== Instruction :: FMul || Opcode == Instruction :: FDiv ) {


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v


<s> void function_expander :: prepare_prefetch_operands ( ) { unsigned int prfop = INTVAL ( args . last ( ) ) ; args . quick_push ( GEN_INT ( ( prfop & <NUM_LIT> ) != <NUM_LIT> ) ) ; args . quick_push ( GEN_INT ( ( ( prfop >> <NUM_LIT> ) & <NUM_LIT> ) +