<s> const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << '[' ; printRegName ( O , MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; O << ']' << markup ( <STR_LIT> ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || ( op == <STR_LIT> ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs << markup ( <STR_LIT> ) ; } O << ']' << markup ( <STR_LIT>


<s> return createELFObjectWriter ( llvm :: make_unique < <ISA_LIT>ObjectWriter > ( OSABI ) , OS


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx


<s> default : return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> NumIssued = <NUM_LIT> ; HasCTRSet = false ; NumStores = <NUM_LIT>


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) { MachineMemOperand * MemOp = cast < MemSDNode > ( N )


<s> void <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg


<s> getTargetStreamer ( ) . emitARM64WinCFITrapFrame ( ) ; return


<s> if ( ! need_endbr && ! SIBLING_CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; rtx fnaddr = XEXP ( call , <NUM_LIT> ) ; tree fndecl = NULL_TREE ; if ( GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == SYMBOL_REF ) fndecl = SYMBOL_REF_DECL ( XEXP ( fnaddr , <NUM_LIT> ) ) ; if ( fndecl == NULL_TREE ) fndecl = MEM_EXPR ( fnaddr ) ; if ( fndecl && TREE_CODE ( TREE_TYPE ( fndecl ) ) != FUNCTION_TYPE && TREE_CODE ( TREE_TYPE ( fndecl ) ) != METHOD_TYPE ) fndecl = NULL_TREE ; if ( fndecl && TYPE_ARG_TYPES ( TREE_TYPE ( fndecl ) ) ) { tree fntype = TREE_TYPE ( fndecl ) ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) need_endbr = true ; } } if ( ! need_endbr ) continue ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after_setloc ( cet_eb , insn , INSN_LOCATION ( insn ) ) ; continue ; } if ( JUMP_P ( insn ) && flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target


<s> } if ( prev_opcode == op_stc && this_opcode == op_fsft ) hazard = <STR_LIT> ; if ( prev_opcode == op_stc && this_opcode == op_ret ) hazard = <STR_LIT> ; if ( hazard ) fprintf ( file , <STR_LIT> , hazard , opnames [ prev_opcode ] , opnames [ this_opcode ] ) ; prev_opcode =


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 && TARGET_FLOAT64 ) mode = SImode ; return


<s> vld3q_dup_u16 ( const uint16_t * __a ) { uint16x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = (


<s> SDLoc dl ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasP9Altivec ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue Sub = Op0 . getOperand ( <NUM_LIT> ) ; if ( Sub . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = Sub . getOperand ( <NUM_LIT> ) ; SDValue SubOp1 = Sub . getOperand ( <NUM_LIT> ) ; if ( ( SubOp0 . getOpcode ( ) == <STR_LIT> ) && ( SubOp1 . getOpcode ( ) == <STR_LIT> ) ) { return DCI . DAG . getNode ( <STR_LIT> , dl , VT , SubOp0 . getOperand ( <NUM_LIT> ) , SubOp1 . getOperand ( <NUM_LIT> ) , DCI . DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } } if ( Op0 . getValueType ( ) != <STR_LIT> || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; int EltToExtract = DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ConstNode = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstNode || ConstNode -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; EltToExtract = EltToExtract ? <NUM_LIT> : <NUM_LIT> ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getValueType ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue Bitcast = DCI . DAG . getBitcast ( <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bitcast , DCI . DAG .

getTargetConstant ( EltToExtract , dl , <STR_LIT> ) ) ;


<s> const RegisterBank * RegBank = RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ; else if ( DstSize == <NUM_LIT> ) RC = STI . isFP64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } if ( ! RBI . constrainGenericRegister ( DstReg ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) { GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl


<s> static void printSSEAVXCC ( int64_t Imm , raw_ostream & O ) { switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) return Reg + <NUM_LIT> ; switch ( Reg ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( parseSymbolicImmVal ( Expr ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: Create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( DarwinRefKind != MCSymbolRefExpr :: VK_PAGE && DarwinRefKind != MCSymbolRefExpr :: VK_GOTPAGE && DarwinRefKind != MCSymbolRefExpr :: VK_TLVPPAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return MatchOperand_Success


<s> if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO .


<s> SDValue Src ; int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( i > M || M >= HalfSize ) return false ; if ( Idx < <NUM_LIT> || ( Src == V && Idx ==


<s> bool isTargetILP32 ( ) const { return TargetTriple . isArch32Bit ( ) || TargetTriple . getEnvironment


<s> fprintf ( stderr , <STR_LIT> , prefix , flags ) ; dump_target_flag_bits ( flags ) ; fprintf ( stderr , <STR_LIT>


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQuadQRegsNode ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT>


<s> <STR_LIT> Pred ; SDValue PredReg ; SDValue Chain , Base , Offset ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Align = LD -> getAlignment ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Align >= <NUM_LIT> && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre


<s> unsigned Opcode = MCID . getOpcode ( ) ; if ( ! ( <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) ) ) return - <NUM_LIT> ; unsigned NumUses = MCID . getNumOperands ( )


<s> assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; auto ConcatPair = [ & ] ( SDValue V1 , SDValue V2 ) { EVT Op1VT = V1 . getValueType ( ) ; EVT Op2VT = V2 . getValueType ( ) ; assert ( Op1VT == Op2VT && <STR_LIT> ) ; EVT VT = Op1VT . getDoubleNumVectorElementsVT ( * DAG . getContext ( ) ) ; SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; SDValue NewV2 = PromoteMVEPredVector ( dl , V2 , Op2VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; unsigned NumElts = <NUM_LIT> * Op1VT . getVectorNumElements ( ) ; EVT ConcatVT = <STR_LIT> ( ElType , NumElts ) ; SDValue ConVec = DAG . getNode ( <STR_LIT> , dl , ConcatVT ) ; auto ExtractInto = [ & DAG , & dl ] ( SDValue NewV , SDValue ConVec , unsigned & j ) { EVT NewVT = NewV . getValueType ( ) ; EVT ConcatVT = ConVec . getValueType ( ) ; for ( unsigned i = <NUM_LIT> , e = NewVT . getVectorNumElements ( ) ; i < e ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , DAG . getIntPtrConstant ( i , dl ) ) ; ConVec = DAG . getNode ( <STR_LIT> , dl , ConcatVT , ConVec , Elt , DAG . getConstant ( j , dl , <STR_LIT> ) ) ; } return ConVec ; } ; unsigned j = <NUM_LIT> ; ConVec = ExtractInto ( NewV1 , ConVec , j ) ; ConVec = ExtractInto ( NewV2 , ConVec , j ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ConVec , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; } ; SmallVector < SDValue > ConcatOps ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; while ( ConcatOps . size ( ) > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> , E = ConcatOps . size ( ) ; I != E ; I += <NUM_LIT> ) { SDValue V1 = ConcatOps [ I ] ; SDValue V2 = ConcatOps [ I + <NUM_LIT> ] ; ConcatOps [ I / <NUM_LIT> ] = ConcatPair ( V1 , V2 ) ; } ConcatOps . resize ( ConcatOps . size (


<s> if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; width = ( width + div - <NUM_LIT> ) /


<s> return ( int16x8_t ) __builtin_neon_vabdlsv8qi (


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameLoadOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses )


<s> EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , <NUM_LIT> ) ; Chain = Addr . getValue


<s> void emitARM64WinCFIMachineFrame ( ) override { OS <<


<s> <ISA_LIT>XPLINKFrameLowering :: <ISA_LIT>XPLINKFrameLowering ( ) : <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , false ) , RegSpillOffsets ( - <NUM_LIT> ) { RegSpillOffsets . grow (


<s> gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; if ( GET_CODE ( x ) != CONST_VECTOR || ! CONST_VECTOR_DUPLICATE_P ( x ) || ! CONST_INT_P ( CONST_VECTOR_ENCODED_ELT ( x , <NUM_LIT> ) ) || INTVAL ( CONST_VECTOR_ENCODED_ELT

( x , <NUM_LIT> ) ) == <NUM_LIT> ) return opt_machine_mode ( ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = StartInsertPt -> getParent ( ) ; if ( ! RDA . isReachingDefLiveOut ( StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( StartInsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , Register NumElements ) { if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; if ( ! MBB


<s> if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , <NUM_LIT> ) ; } else for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true


<s> default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return <NUM_LIT> ; if ( mask_mode != dest_mode ) mask = simplify_gen_subreg ( dest_mode , mask , mask_mode , <NUM_LIT> ) ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return <NUM_LIT> ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return <NUM_LIT> ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; rtx tmp = gen_rtx_IOR ( dest_mode , gen_rtx_AND ( dest_mode , gen_rtx_NOT ( dest_mode , mask ) , op_false ) , gen_rtx_AND ( dest_mode , mask , op_true ) ) ; emit_insn ( gen_rtx_SET ( dest ,


<s> if ( Available . size ( ) == <NUM_LIT> ) dbgs ( ) << <STR_LIT> ; Candidate c ( SU , * HazardRec ) ; c . dumpCosts ( ) ; dbgs ( ) << <STR_LIT> ; ) ; Available . erase ( SU


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > <NUM_LIT> && INT_REGNO_P ( regno )


<s> if ( ! ( Subtarget . hasDQI ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . hasBWI ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> <ISA_LIT>CC ; if ( isNullConstant ( Op1 ) ) { <ISA_LIT>CC = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return SDValue (


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand


<s> WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != Idx + NumElts ) ) return false ; Idx +=


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> )

| ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; case rk_DoubleReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return nullptr ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; } Op -> Reg .


<s> for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; unsigned Offset ; if ( TII -> getMemOpBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> for ( size_t i = <NUM_LIT> ; i < pNum ;

++ i ) createEntry ( <NUM_LIT> , m_SectionData ) ;


<s> AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! OffsetIsInRange ( Offset , EndInsertOffset , U . MaxDisp , U . NegOk , U . IsSoImm ) ) { BaseInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; EndInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; } EndInsertOffset += CPUsers [ CPUIndex ] . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ; } DEBUG ( errs ( ) << <STR_LIT> ) ; -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = llvm :: getITInstrPredicate ( MI , PredReg ) ; if ( CC != <STR_LIT> ) MI = LastIT ; } NewMBB = SplitBlockBeforeInstr ( MI )


<s> Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & MCID = TII -> get ( Opc ) ; unsigned DestReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; BuildMI ( * Head , Head -> end ( ) , TermDL , MCID ) . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . add ( HeadCond [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MRI -> constrainRegClass ( HeadCond [ <NUM_LIT> ] . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; } Head -> splice ( Head -> end ( ) , CmpBB , CmpBB -> begin ( ) , CmpBB -> end ( ) ) ; unsigned Opc = <NUM_LIT> ; unsigned FirstOp = <NUM_LIT> ; bool isZBranch = false ; switch ( CmpMI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( const Instruction * I ) { const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; unsigned SABIAlignment = TD . getABITypeAlignment ( S -> getValueOperand ( ) -> getType ( ) ) ; bool Aligned = S -> getAlignment ( ) == <NUM_LIT> || S -> getAlignment ( ) >= SABIAlignment ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode


<s> return ParseMemOperand ( RegNo , Start ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; Parser . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . parseExpression ( Val , End ) ) return nullptr ; return <STR_LIT> ( Val , Start , End ) ; } case AsmToken :: LCurly : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return ParseRoundingModeOp ( Start , End ) ; return ErrorOperand ( Start , <STR_LIT>


<s> Rdm |= fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Rm = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> return ( offset . is_constant ( & const_offset ) &&


<s> if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ; return *


<s> ( void ) TT ; return new <ISA_LIT>DCTranslator ( Ctx , DL , OptLevel , MII , MRI , STI


<s> sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , <NUM_LIT> , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT ,


<s> if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> ,


<s> bool <ISA_LIT>InstructionSelector :: selectTurnIntoCOPY ( MachineInstr & I , MachineRegisterInfo & MRI , const unsigned DstReg , const TargetRegisterClass *

DstRC , const unsigned SrcReg , const TargetRegisterClass * SrcRC ) const {


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } APInt VP1 = Value + <NUM_LIT> ; if ( VP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VP1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } } else { APInt VNM1 = - Value - <NUM_LIT> ; if ( VNM1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNM1 . logBase2 ( ) , <STR_LIT> ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getConstant ( <NUM_LIT> , VT ) , Add ) ; } APInt VNP1 = - Value + <NUM_LIT> ; if ( VNP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNP1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand (


<s> uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > <NUM_LIT> ) break ; } if ( LoopSize > <NUM_LIT> && LoopSize <= <NUM_LIT> ) return <NUM_LIT> ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML


<s> static void arm_elf_asm_constructor ( rtx symbol , int priority ) { arm_elf_asm_cdtor ( symbol ,


<s> MVT VT = N0 . getSimpleValueType ( ) ; assert ( ( VT . is128BitVector ( ) && ( VT . getScalarSizeInBits ( ) == <NUM_LIT> || VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) != N1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; SDValue WideVec = N0 . getOperand ( <NUM_LIT> ) ; MVT WideVT = WideVec . getSimpleValueType ( ) ; if ( ! WideVT . is256BitVector ( ) ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; const APInt & ExtIndex0 = N0 . getConstantOperandAPInt ( <NUM_LIT> ) ; const APInt & ExtIndex1 = N1 . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ExtIndex1 == <NUM_LIT> && ExtIndex0 == NumElts ) ShuffleVectorSDNode :: commuteMask ( NewMask ) ; else if ( ExtIndex0 != <NUM_LIT> || ExtIndex1 != NumElts ) return SDValue ( ) ; if ( NumElts == <NUM_LIT> && ( isSingleSHUFPSMask ( NewMask ) || is128BitUnpackShuffleMask ( NewMask


<s> if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = l , e = l + NumLaneElts / <NUM_LIT> ; i != e ; ++ i ) { ShuffleMask . push_back ( i


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 ,


<s> case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerCATCHRET ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMUL_LOHI ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : return LowerADD ( Op , DAG ) ; case <STR_LIT> : return LowerSUB ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerMINMAX ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerMGATHER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerMSCATTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerGC_TRANSITION_START ( Op , DAG ) ; case <STR_LIT> : return LowerGC_TRANSITION_END ( Op , DAG


<s> <STR_LIT> getExtendForAtomicCmpSwapArg ( ) const override


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI


<s> if ( GrpCount % <NUM_LIT> ) Idx += <NUM_LIT> ; if ( SU != nullptr && ! fitsIntoCurrentGroup ( SU ) ) { if ( Idx == <NUM_LIT> || Idx == <NUM_LIT> ) Idx = <NUM_LIT> ; else if ( Idx == <NUM_LIT> || Idx == <NUM_LIT> ) Idx = <NUM_LIT> ; } return Idx


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( )


<s> EVT EltType = V . getValueType ( ) . getVectorElementType ( ) ; return EltType . getSizeInBits ( ) /


<s> if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , ( MachineInstr * ) NULL ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; } assert ( ( TrueBB == & Dst ) || ( FalseBB == & Dst ) ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Cond , BranchInstrs [ <NUM_LIT> ] ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) && ( FalseBB == & Dst ) ) return

std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Uncond , BranchInstrs [ <NUM_LIT> ] ) ;


<s> static void insn_dependent_p_1 ( rtx x , rtx pat


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo .


<s> if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) ) ) { if ( reg == <NUM_LIT> ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg ( reg , orig ) ) ; return reg ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == <NUM_LIT> ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg ,


<s> <STR_LIT> <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT>


<s> if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; if ( ! regno ) return true ; for ( i = <NUM_LIT> ; i < REGPARM_MAX ; i ++ ) if (

regno == x86_64_int_parameter_registers [ i ] ) return true ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML ) ) dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ; for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ; ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> static void def_builtin ( const char * name , tree type , enum rs6000_builtins code ) { tree t ; unsigned classify = rs6000_builtin_info [ ( int ) code ] . attr ; const char * attr_string = <STR_LIT> ; gcc_assert ( name != NULL ) ; gcc_assert ( IN_RANGE ( ( int ) code , <NUM_LIT> , ( int ) RS6000_BUILTIN_COUNT ) ) ; if ( rs6000_builtin_decls [ ( int ) code ] ) fatal_error ( input_location , <STR_LIT> , name ) ; rs6000_builtin_decls [ ( int ) code ] = t = add_builtin_function ( name , type , ( int ) code , BUILT_IN_MD , NULL , NULL_TREE ) ; if ( ( classify & RS6000_BTC_CONST ) != <NUM_LIT> ) { TREE_READONLY ( t ) = <NUM_LIT> ; TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_PURE ) != <NUM_LIT> ) { DECL_PURE_P ( t ) = <NUM_LIT> ; TREE_NOTHROW ( t ) = <NUM_LIT> ; attr_string = <STR_LIT> ; } else if ( ( classify & RS6000_BTC_FP ) != <NUM_LIT> ) { TREE_NOTHROW ( t ) = <NUM_LIT> ; if ( flag_rounding_math ) { DECL_PURE_P ( t ) = <NUM_LIT> ; DECL_IS_NOVOPS ( t ) =


<s> void setReturnAddrSaveIndex ( int idx )


<s> std :: pair < unsigned , bool > <ISA_LIT>FlagsCopyLoweringPass :: getCondOrInverseInReg ( MachineBasicBlock & TestMBB , MachineBasicBlock :: iterator TestPos , const DebugLoc & TestLoc , <STR_LIT> Cond , CondRegArray & CondRegs ) { unsigned & CondReg = CondRegs [ Cond ] ; unsigned & InvCondReg = CondRegs [ <STR_LIT> ( Cond ) ] ; if ( ! CondReg && ! InvCondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; if ( CondReg ) return { CondReg


<s> auto IsZext = [ & DAG ] ( SDValue V ) { return DAG . computeKnownBits ( V ) . countMaxActiveBits ( ) <= <NUM_LIT> ; } ; bool IsSigned = IsSext ( LHS ) && IsSext ( RHS ) ; bool IsUnsigned = IsZext ( LHS ) && IsZext ( RHS ) ; if ( ! IsSigned && ! IsUnsigned ) return SDValue ( ) ; bool IsTruncateFree = ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && RHS . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ; unsigned InSizeInBits = InVT . getSizeInBits ( ) ; if ( IsUnsigned && ! IsTruncateFree && Subtarget . hasInt256 ( ) && ! ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && VT . is256BitVector ( ) ) && ( InSizeInBits % <NUM_LIT> ) == <NUM_LIT> ) { EVT BCVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , BCVT , DAG . getBitcast ( BCVT , LHS ) , DAG . getBitcast ( BCVT , RHS ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( InVT , Res ) ) ; } LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS


<s> unsigned <ISA_LIT>MachOTargetObjectFile :: getTTypeEncoding (


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; unsigned StackEst = <ISA_LIT>FI -> determineFrameLayout ( MF , false , true ) ; if ( ! StackEst ) return false ; Offset +=


<s> static void tSUBspi_customALF ( const MachineInstr & MI , ALFStatementGroup & alfbb , ALFContext * ctx , string label ) { const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string SP = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT>


<s> assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ; } SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ; } SDValue LockOp = lowerAtomicArithWithLOCK ( N , DAG , Subtarget ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , LockOp .


<s> return new <ISA_LIT>CallFrameOptimization (


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <STR_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> void func_fma_steering :: update_balance ( int parity


<s> const MCExpr * Expr = nullptr ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( )


<s> void print ( raw_ostream & Out ) const { R . print ( Out ) ; Out << <STR_LIT>


<s> default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << <STR_LIT> ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ <NUM_LIT> ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O ) ; return false


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister (


<s> case MachineOperand :: MO_Immediate : OutMO = MCOperand :: createImm ( MO . getImm ( ) ) ; return true ; case MachineOperand :: MO_MachineBasicBlock : OutMO = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; return true ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_BlockAddress : OutMO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_MCSymbol : OutMO = GetSymbolRef ( MO , MO .


<s> MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( & MF . getFunction ( ) , TM ) ) ; FnDescSec -> setAlignment ( Align ( Subtarget -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; CurrentFnDescSym = FnDescSec -> getQualNameSymbol ( ) ; return AsmPrinter :: SetupMachineFunction ( MF )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > (


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode

== V2UHAmode || mode == V2HAmode ) ) return true ;


<s> return SelectCode ( N ) ; } return nullptr ; } } unsigned Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget . hasHighWord ( ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { getUNDEF ( SDLoc ( N ) , OpcodeVT ) , convertTo ( SDLoc ( N ) , OpcodeVT , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N )


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return


<s> rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , <NUM_LIT> ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , <NUM_LIT> , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ <NUM_LIT> ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ <NUM_LIT> ] , two31r , val , tmp [ <NUM_LIT> ] ) ) ; tmp [ <NUM_LIT> ] = expand_simple_binop ( mode , AND , tmp [ <NUM_LIT> ] , two31r , tmp [ <NUM_LIT> ] , <NUM_LIT> , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ <NUM_LIT> ] ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) ; two31 = ix86_build_const_vector ( intmode , <NUM_LIT>


<s> return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) && ! MF . getFunction ( )


<s> CallContext ( ) : Call ( nullptr ) , SPCopy ( nullptr ) , ExpectedDist ( <NUM_LIT> ) , MovVector ( <NUM_LIT> , nullptr )

, NoStackParams ( false ) , UsePush ( false ) { }


<s> uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c )


<s> return <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> S = create<ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF -> getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( LogAlign ) ; unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits (


<s> EVT VT = Op . getValueType ( ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; APInt MulImm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; return DAG . getZExtOrTrunc ( DAG . getVScale ( DL , <STR_LIT> , MulImm . sext ( <NUM_LIT> ) )


<s> const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; if ( const auto * Entry = CostTableLookup ( CostTbl , ISDOpcode , LT . second ) ) return LT . first * Entry -> Cost ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( LT . second == <STR_LIT> && Op2Info == TargetTransformInfo :: OK_UniformConstantValue ) Cost += <NUM_LIT> ; return Cost ; } auto LooksLikeAFreeShift = [ & ] ( ) { if ( ST -> isThumb1Only ( ) || Ty -> isVectorTy ( ) ) return false ; if ( ! CxtI || ! CxtI -> hasOneUse ( ) || ! CxtI -> isShift ( ) ) return false ; if ( Op2Info != TargetTransformInfo :: OK_UniformConstantValue ) return false ; switch ( cast < Instruction > ( CxtI -> user_back ( ) ) -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Sub : case Instruction :: And : case Instruction :: Xor : case Instruction ::


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; Reloc :: Model RM = Subtarget -> getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! Subtarget -> has<ISA_LIT>64 ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText


<s> void expand_df_binop ( rtx ( * fun ) ( rtx , rtx , rtx ,


<s> if ( ! N2C || N2C -> getAPIntValue ( ) . uge ( NumElts ) ) return SDValue ( ) ; uint64_t IdxVal = N2C -> getZExtValue ( ) ; bool IsZeroElt = <STR_LIT> ( N1 ) ; bool IsAllOnesElt = VT . isInteger ( ) && llvm :: isAllOnesConstant ( N1 ) ; if ( ( IsZeroElt || IsAllOnesElt ) && Subtarget . hasSSE41 ( ) && <NUM_LIT> <= EltVT . getSizeInBits ( ) ) { SmallVector < int , <NUM_LIT> > BlendMask ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) BlendMask . push_back ( i == IdxVal ? i + NumElts : i ) ; SDValue CstVector = IsZeroElt ? getZeroVector ( VT , Subtarget , DAG , dl ) : getOnesVector ( VT , DAG , dl ) ; return DAG . getVectorShuffle ( VT , dl , N0 , CstVector , BlendMask ) ; } if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget . hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget . hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } SDValue V = extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumEltsIn128 ) ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getIntPtrConstant ( IdxIn128 , dl ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( IdxVal == <NUM_LIT> && <STR_LIT> ( N0 . getNode ( ) ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) { N1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) &&


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = <NUM_LIT> ; unsigned int offset = <NUM_LIT> ; int


<s> bool WasOriginalArg<ISA_LIT>F128 ( unsigned ValNo ) { return OriginalArgWas<ISA_LIT>F128 [ ValNo ]


<s>
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
unsigned
ErrorInfoIgnore
;
MatchResultTy
Match1
,
Match2
,
Match3
,
Match4
;
Match1
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match2
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match3
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match4
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Op
->
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
(
Match1
==
Match_Success
)
+
(
Match2
==
Match_Success
)
+
(
Match3
==
Match_Success
)
+
(
Match4
==
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
Match1
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match2
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match3
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match4
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
!=
NumMatches
;
++
i
)
{
if
(
i
!=
<NUM_LIT>
)
OS
<<
<STR_LIT>
;
if
(
i
+
<NUM_LIT>
==
NumMatches
)
OS
<<
<STR_LIT>
;
OS
<<
<STR_LIT>
<<
Base
<<
MatchChars
[
i
]
<<
<STR_LIT>
;
}
OS
<<
<STR_LIT>
;
Error
(
IDLoc
,
OS
.
str
(
)
)
;
return
true
;
}
if
(
(
Match1
==
Match_MnemonicFail
)
&&
(
Match2
==
Match_MnemonicFail
)
&&
(
Match3
==
Match_MnemonicFail
)
&&
(
Match4
==
Match_MnemonicFail
)
)
{
if
(
!
WasOriginallyInvalidOperand
)
{
Error
(
IDLoc
,
<STR_LIT>
+
Base
+
<STR_LIT>
)
;
return
true
;
}
SMLoc
ErrorLoc
=
IDLoc
;
if
(
OrigErrorInfo
!=
~
<NUM_LIT>
)
{
if
(
OrigErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
<STR_LIT>
)
;
ErrorLoc
=
(
(
<ISA_LIT>Operand
*
)
Operands
[
OrigErrorInfo
]
)
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)


<s> } else if ( auto val = getConstantVRegVal ( CarryInReg , MRI ) ) { if ( * val != <NUM_LIT> ) return false ; Opcode = <STR_LIT> ; } else return false ; MachineInstr & AddInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) , DstReg ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , CarryOutReg ) . addReg ( <STR_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( AddInst , TII , TRI , RBI ) || ! RBI . constrainGenericRegister ( CarryOutReg , <STR_LIT> , MRI ) ) return false ; I . eraseFromParent ( ) ; return true


<s> unsigned tgt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; tgt <<= <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( tgt + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: createImm ( tgt ) ) ; return MCDisassembler ::


<s> if ( isTargetDarwin ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } uint64_t Bits = getFeatureBits (


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT>


<s> return G1 -> startsBefore ( G2 ) ; } ) ; Color PreferredColor = Parity < <NUM_LIT> ? Color :: Even : Color :: Odd ; while ( Chain * G = getAndEraseNext ( PreferredColor , GV ) ) { Color C = PreferredColor ; if ( Parity == <NUM_LIT> ) C = G -> getPreferredColor ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Parity << <STR_LIT> << ColorNames [ ( int ) C ] << <STR_LIT> ) ; if ( G -> requiresFixup ( ) && C != G -> getPreferredColor ( ) ) { C = G -> getPreferredColor ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << G -> str ( ) << <STR_LIT> <STR_LIT> << ColorNames [ ( int ) C


<s> ScaleFactor = <NUM_LIT> ; break ; } if ( ! UseUnscaled ) { int64_t Offset = Addr . getOffset ( ) ; if ( Offset & ( ScaleFactor - <NUM_LIT> ) ) return EmitStore ( VT , SrcReg , Addr , true ) ; Addr . setOffset ( Offset / ScaleFactor ) ; } if ( ! SimplifyAddress ( Addr , VT , UseUnscaled ? <NUM_LIT> : ScaleFactor , UseUnscaled ) ) return false ; if ( VTIsi1 ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; unsigned ANDReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ANDReg )

. addReg ( SrcReg ) . addImm ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( In ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , MemVT , LoadVT , DAG ) ) { SDLoc dl ( N ) ; if ( IsStrict ) { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , DAG . getBitcast ( InVT , VZLoad ) } ) ; DCI . CombineTo ( N , Convert , Convert . getValue ( <NUM_LIT> ) ) ; } else { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; } DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; DCI . recursivelyDeleteUnusedNodes ( LN ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue (


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } Register LinkReg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) ,


<s> } } if ( Single . getNode ( ) && ( Count > <NUM_LIT> || Single . getOpcode ( ) == <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Single ) ; if ( VT == <STR_LIT> ) return joinDwords ( DAG , DL , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( VT == <STR_LIT> ) return buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( VT == <STR_LIT> ) { SDValue Op01 = buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; SDValue Op23 = buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( Op01 . isUndef ( ) ) Op01 = Op23 ; else if ( Op23 . isUndef ( ) ) Op23 = Op01 ; if ( Op01 . getOpcode ( ) == <STR_LIT> && Op01 == Op23 ) return Op01 ; Op01 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op01 ) ; Op23 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op23 ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op01 , Op23 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } SmallVector < SDValue , <STR_LIT> > Constants ( NumElements , SDValue ( ) ) ; SmallVector < bool , <STR_LIT> > Done ( NumElements , false ) ; unsigned NumConstants = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { SDValue Elem = Elems [ I ] ; if ( Elem . getOpcode ( ) == <STR_LIT> || Elem . getOpcode ( ) == <STR_LIT> ) { NumConstants +=


<s> } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: createSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( OpSym , OutContext ) , DotExpr , OutContext ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( DotExpr ) ) ; return ; } case TargetOpcode :: STATEPOINT : return LowerSTATEPOINT ( * MI , MCInstLowering ) ; case TargetOpcode :: FAULTING_OP : return LowerFAULTING_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: FENTRY_CALL : return LowerFENTRY_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_OP : return LowerPATCHABLE_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : return LowerPATCHABLE_FUNCTION_ENTER ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_RET : return LowerPATCHABLE_RET ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TAIL_CALL : return LowerPATCHABLE_TAIL_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_EVENT_CALL : return LowerPATCHABLE_EVENT_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TYPED_EVENT_CALL : return LowerPATCHABLE_TYPED_EVENT_CALL ( * MI , MCInstLowering ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case


<s> void addMSA128AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMSA128Reg ( ) )


<s> case CallingConv :: CXX_FAST_TLS : case CallingConv :: Swift : case CallingConv :: SwiftTail : case CallingConv :: Tail : if ( Subtarget -> isTargetWindows ( ) && IsVarArg ) return CC_<ISA_LIT>_Win64_VarArg ; if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; if ( ! IsVarArg ) return CC_<ISA_LIT>_DarwinPCS ; return Subtarget -> isTargetILP32 ( ) ? CC_<ISA_LIT>_DarwinPCS_ILP32_VarArg : CC_<ISA_LIT>_DarwinPCS_VarArg ; case CallingConv ::


<s> bool hasZeroCycleZeroing ( ) const { return


<s> case <NUM_LIT> : Suffix = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned VectorReg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg = MRI . getSubReg ( VectorReg , <STR_LIT> ) ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( VectorReg )


<s> return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return


<s> if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; if ( ! Subtarget -> hasCMov ( ) ) return false ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { return false ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> )


<s> static SDValue getBitTestCondition ( SDValue Src , SDValue BitNo , <STR_LIT> CC , const SDLoc & dl , SelectionDAG & DAG ) { if ( Src . getValueType ( ) == <STR_LIT> || Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) == <STR_LIT> && DAG . MaskedValueIsZero ( BitNo , APInt ( BitNo . getValueSizeInBits ( ) , <NUM_LIT> ) ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , dl , Src . getValueType ( ) , BitNo ) ; SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , BitNo ) ; <STR_LIT> Cond = CC == <STR_LIT> ? <STR_LIT> :


<s> PointerSize = <NUM_LIT> ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler =


<s> unsigned Mask = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT> ; Mask |= Elt << (


<s> return ( __m128i ) __builtin_ia32_vcvtph2w128_mask ( __A , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> vmovl_high_u8 ( uint8x16_t a ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && isWorthFoldingADDlow ( N ) ) { GlobalAddressSDNode * GAN = dyn_cast < GlobalAddressSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Base = N . getOperand ( <NUM_LIT> ) ; OffImm = N . getOperand ( <NUM_LIT> ) ; if ( ! GAN ) return true ; const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; const DataLayout * DL = TLI -> getDataLayout ( ) ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) ) Alignment = DL -> getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { return new <ISA_LIT>MCAsmInfo (


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasAVX512 ( ) ) return LowerVectorCTLZ_AVX512 ( Op , DAG ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = extract128BitVector ( Op0 , <NUM_LIT> , DAG , DL ) ; SDValue RHS = extract128BitVector ( Op0 , NumElems / <NUM_LIT> , DAG , DL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , LHS ) , DAG . getNode (

<STR_LIT> , DL , RHS . getValueType ( ) , RHS ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT>


<s> static int sh_pr_n_sets ( void ) { return DF_REG_DEF_COUNT ( TARGET_SHMEDIA ? PR_MEDIA_REG


<s> static MCStreamer * create<ISA_LIT>MachOStreamer ( MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool DWARFMustBeAtTheEnd ) { return createMachOStreamer ( Ctx , MAB , OS

, Emitter , false , DWARFMustBeAtTheEnd ) ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set


<s> static bool isX87NonWaitingControlInstruction ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> return ! TARGET_LINUX_ABI && TARGET_16_BIT &&


<s> addPass ( create<ISA_LIT>MemAluCombinerPass ( )


<s> return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP


<s> if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode ,


<s> else if ( INT_14_BITS ( x ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case HIGH : * total = <NUM_LIT> ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( ( x == CONST0_RTX ( DFmode ) || x == CONST0_RTX ( SFmode ) ) && outer_code != SET ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( mode == DImode ) { if ( TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else { if ( TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } return REG_P ( XEXP ( x , <NUM_LIT> ) ) && REG_P ( XEXP ( x , <NUM_LIT> ) ) ; case DIV : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case UDIV : case MOD : case UMOD : if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return REG_P ( XEXP ( x , <NUM_LIT> ) ) && REG_P ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DImode ) { if ( TARGET_64BIT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( hppa_rtx_costs_shadd_p ( x ) ) return true ; } else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else { * total = COSTS_N_INSNS ( <NUM_LIT>


<s> return getSubExpr ( ) -> evaluateAsRelocatable ( Res ,


<s> cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( <STR_LIT> ,


<s> return true ; case <STR_LIT> : lowerLongBranchLUi ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) ; return true ; case <STR_LIT> : unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr ::


<s> return ( uint64x1_t ) { __builtin_aarch64_usra_ndi_uuus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] ,


<s> static SDValue insert128BitVector ( SDValue Result , SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , const SDLoc & dl ) { assert ( Vec . getValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; return insertSubVector ( Result , Vec , IdxVal , DAG


<s> if ( VT == <STR_LIT> ) return SDValue ( ) ; if ( ! Ld -> isVolatile ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue ( <NUM_LIT> ) ) ; return FILDChain ; } } return SDValue (


<s> if ( ABI . IsO32 ( ) ) PrivateGlobalPrefix = <STR_LIT> ; else if ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = PrivateGlobalPrefix ; AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation =


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeT2AddrModeImm12 ( Inst , imm , Address


<s> static int getMemoryOpOffset ( const MachineInstr * MI ) { int Opcode = MI -> getOpcode ( ) ; bool isAM3 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; unsigned NumOperands = MI -> getDesc ( ) . getNumOperands ( ) ; unsigned OffField = MI -> getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField ; int Offset = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> ( OffField ) * <NUM_LIT> ; if ( isAM3 ) { if ( <STR_LIT> ( OffField ) == <STR_LIT> ) Offset = - Offset ; } else { if ( <STR_LIT> ( OffField ) == <STR_LIT> ) Offset = - Offset ; } return Offset


<s> fnname = targetm . strip_name_encoding ( XSTR ( fn , <NUM_LIT> ) ) ; for ( l = mips16_stubs ; l != NULL ; l = l -> next ) if ( strcmp ( l -> name , fnname ) == <NUM_LIT> ) break ; if ( l == NULL ) { const char * separator ; char * secname , * stubname ; tree stubid , stubdecl ; unsigned int f ; secname = ACONCAT ( ( <STR_LIT> , fp_ret_p ? <STR_LIT> : <STR_LIT> , fnname , NULL ) ) ; stubname = ACONCAT ( ( <STR_LIT> , fp_ret_p ? <STR_LIT> : <STR_LIT> , fnname , NULL ) ) ; stubid = get_identifier ( stubname ) ; stubdecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , stubid , build_function_type_list ( void_type_node , NULL_TREE ) ) ; set_decl_section_name ( stubdecl , secname ) ; DECL_RESULT ( stubdecl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; fprintf ( asm_out_file , <STR_LIT> , ( fp_ret_p ? ( GET_MODE ( retval ) == SFmode ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) , fnname ) ; separator = <STR_LIT> ; for ( f = ( unsigned int ) fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> , separator , ( f & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; separator = <STR_LIT> ; } fprintf ( asm_out_file , <STR_LIT> ) ; assemble_start_function ( stubdecl , stubname ) ; mips_start_function_definition ( stubname , false ) ; if ( fp_ret_p ) { fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ RETURN_ADDR_REGNUM ] ) ; } else { if ( TARGET_EXPLICIT_RELOCS ) { output_asm_insn ( <STR_LIT> , & fn ) ; output_asm_insn ( <STR_LIT> , & fn ) ; } else output_asm_insn ( <STR_LIT> , & fn ) ; } mips_output_args_xfer ( fp_code , 't' ) ; if ( fp_ret_p ) { output_asm_insn ( mips_output_jump ( & fn , <NUM_LIT> , - <NUM_LIT> , true ) , & fn ) ; fprintf ( asm_out_file , <STR_LIT> ) ; switch ( GET_MODE ( retval ) ) { case E_SCmode : mips_output_32bit_xfer ( 'f' , GP_RETURN + TARGET_BIG_ENDIAN , TARGET_BIG_ENDIAN ? FP_REG_FIRST + <NUM_LIT> : FP_REG_FIRST ) ; mips_output_32bit_xfer ( 'f' , GP_RETURN + TARGET_LITTLE_ENDIAN , TARGET_LITTLE_ENDIAN ? FP_REG_FIRST + <NUM_LIT> : FP_REG_FIRST ) ; if ( GET_MODE ( retval ) ==


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return getSubtargetImpl ( ) -> getSelectionDAGInfo


<s> else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; updateValueMap ( I ,


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFITrapFrame (


<s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . has<ISA_LIT>3 ( ) && Subtarget .


<s> if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask2 = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Mask2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ,


<s> return ( int64x2_t ) __builtin_aarch64_sqaddv2di


<s> RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT>


<s> int ResTyNumElts = ResTy . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> ; i < ResTyNumElts ; ++ i ) { int Idx = Indices [ i ] ; if ( <NUM_LIT> <= Idx && Idx < ResTyNumElts ) Using1stVec = true ; if ( ResTyNumElts <= Idx && Idx < ResTyNumElts * <NUM_LIT> ) Using2ndVec = true ; } for ( int Idx : Indices ) Ops . push_back ( DAG . getTargetConstant ( Idx , DL , MaskEltTy ) ) ; SDValue MaskVec = DAG . getBuildVector ( MaskVecTy , DL , Ops ) ; if ( Using1stVec && Using2ndVec ) { Op0 = Op -> getOperand ( <NUM_LIT> ) ; Op1 = Op ->


<s> const bool Crypto = llvm :: is_contained ( RequestedExtensions , <STR_LIT> ) ; if ( ! NoCrypto && Crypto ) { switch ( ArchKind ) { default : case <STR_LIT> :: ARMV8_1A : case <STR_LIT> :: ARMV8_2A : case <STR_LIT> :: ARMV8_3A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : case <STR_LIT> :: ARMV8_7A : case <STR_LIT> :: ARMV8R : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; } } else if ( NoCrypto ) { switch ( ArchKind ) { default : case <STR_LIT> :: ARMV8_1A : case <STR_LIT> :: ARMV8_2A : case <STR_LIT> :: ARMV8_3A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT>


<s> return CurDAG -> getTargetConstant (


<s> calc_live_regs ( & d , live_regs_mask ) ; if ( target_flags != save_flags ) emit_insn ( gen_toggle_sz ( ) ) ; if ( TARGET_SH5 ) { int i ; int offset ; int align ; rtx r0 = gen_rtx_REG ( Pmode , R0_REG ) ; int offset_in_r0 = - <NUM_LIT> ; int sp_in_r0 = <NUM_LIT> ; if ( d % ( STACK_BOUNDARY / BITS_PER_UNIT ) ) d_rounding = ( ( STACK_BOUNDARY / BITS_PER_UNIT ) - d % ( STACK_BOUNDARY / BITS_PER_UNIT ) ) ; offset = d + d_rounding ; output_stack_adjust ( - offset , stack_pointer_rtx , <NUM_LIT> ) ; for ( align = <NUM_LIT> ; align >= <NUM_LIT> ; align -- ) for ( i = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( live_regs_mask [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) { enum machine_mode mode = REGISTER_NATURAL_MODE ( i ) ; int reg = i ; rtx reg_rtx , mem_rtx , pre_dec = NULL_RTX ; if ( mode == SFmode && ( i % <NUM_LIT> ) == <NUM_LIT> && ! TARGET_FPU_SINGLE && FP_REGISTER_P ( i ) && ( live_regs_mask [ ( i ^ <NUM_LIT> ) / <NUM_LIT> ] & ( <NUM_LIT> << ( ( i ^ <NUM_LIT> ) % <NUM_LIT> ) ) ) ) { mode = DFmode ; i -- ; reg -- ; } if ( ( GET_MODE_SIZE ( mode ) % ( STACK_BOUNDARY / BITS_PER_UNIT ) == <NUM_LIT> ) != align ) continue ; offset -= GET_MODE_SIZE ( mode ) ; reg_rtx = gen_rtx_REG ( mode , reg ) ; mem_rtx = gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; GO_IF_LEGITIMATE_ADDRESS ( mode , XEXP ( mem_rtx , <NUM_LIT> ) , try_pre_dec ) ; mem_rtx = NULL_RTX ; try_pre_dec : do if ( HAVE_PRE_DECREMENT && ( offset_in_r0 - offset == GET_MODE_SIZE ( mode ) || mem_rtx == NULL_RTX || i == PR_REG || SPECIAL_REGISTER_P ( i ) ) ) { pre_dec = gen_rtx_MEM ( mode , gen_rtx_PRE_DEC ( Pmode , r0 ) ) ; GO_IF_LEGITIMATE_ADDRESS ( mode , XEXP ( pre_dec , <NUM_LIT> ) , pre_dec_ok ) ; pre_dec = NULL_RTX ; break ; pre_dec_ok : mem_rtx = NULL_RTX ; offset += GET_MODE_SIZE ( mode ) ; } while ( <NUM_LIT> ) ; if ( mem_rtx != NULL_RTX ) goto addr_ok ; if ( offset_in_r0 == - <NUM_LIT> ) { emit_move_insn ( r0 , GEN_INT ( offset ) ) ; offset_in_r0 = offset ; } else if ( offset != offset_in_r0 ) { emit_move_insn ( r0 , gen_rtx_PLUS ( Pmode , r0 , GEN_INT ( offset - offset_in_r0 ) ) ) ; offset_in_r0 += offset - offset_in_r0 ; } if ( pre_dec != NULL_RTX ) { if ( ! sp_in_r0 ) { emit_move_insn ( r0 , gen_rtx_PLUS ( Pmode , r0 , stack_pointer_rtx ) ) ; sp_in_r0 = <NUM_LIT> ; } offset -= GET_MODE_SIZE ( mode ) ; offset_in_r0 -= GET_MODE_SIZE ( mode


<s> Imm = N ; if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N ) -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ; if ( ! CR ) return TM . getCodeModel ( ) == CodeModel :: Small ; return CR -> getUnsignedMax ( ) . ult ( <NUM_LIT>


<s> static SDValue performAddSubCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( SDValue Val = performUADDVCombine ( N , DAG ) ) return Val ; if ( SDValue Val = performAddDotCombine ( N , DAG ) )


<s> SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize - TFI . getOffsetOfLocalArea ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed (


<s> llvm :: FastISel * <STR_LIT> ( FunctionLoweringInfo &


<s> auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; Value * Val , * LHS , * RHS ; bool isNarrow = false ; if ( match ( V , m_Trunc ( m_Value ( Val ) ) ) ) { if ( cast < TruncInst > ( I ) -> getDestTy ( ) -> getIntegerBitWidth ( ) == BitWidth ) isNarrow = IsNarrowSequence < BitWidth > ( Val , VL ) ; } else if ( match ( V , m_Add ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) { isNarrow = false ; } else if ( match ( V , m_ZExtOrSExt ( m_Value ( Val ) ) ) ) { if ( cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) == BitWidth ) isNarrow = true ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) ) ; if ( match ( Val , m_Load ( m_Value ( Val ) ) ) ) { auto * Ld = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Ld -> dump ( ) ) ; VL . push_back ( Ld ) ; isNarrow = true ; } else if ( ! isa < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) VL . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } if ( isNarrow ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; VL . push_back ( I ) ; } else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; return isNarrow


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability


<s> return __builtin_ia32_ucomieq ( ( __v4sf ) __A , ( __v4sf )


<s> return build_string_literal ( strlen ( objfmt ) + <NUM_LIT>


<s> int16_t i [ <NUM_LIT> ] ; } u ; u . v = a ; u . i [ pos ] =


<s> std :: string IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; if ( IDVal == <STR_LIT> ) return parseLiteralValues ( <NUM_LIT> ,


<s> Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; HasConstElts = true ; } if ( SplatIdx == - <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else Imm = DAG . getUNDEF ( VT ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) DstVec = DAG . getBitcast ( VT , Imm ) ; else { SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } for ( unsigned i = <NUM_LIT> ; i < NonConstIdx . size ( ) ; ++ i ) { unsigned InsertIdx = NonConstIdx [ i ] ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , DstVec , Op . getOperand ( InsertIdx ) , DAG . getIntPtrConstant ( InsertIdx , dl ) ) ; } return


<s> void <ISA_LIT>MCCodeEmitter :: EmitByte ( unsigned char C , raw_ostream & OS )


<s> TLInfoSE . swap ( TLInfo ) ; if ( ! InstrInfo16 ) { InstrInfo . reset ( <ISA_LIT>InstrInfo :: create ( * TM ) ) ; FrameLowering . reset ( <ISA_LIT>FrameLowering :: create ( * TM , * this ) ) ; TLInfo . reset ( <ISA_LIT>TargetLowering :: create ( * TM ) ) ; }


<s> bool <ISA_LIT>Subtarget :: useAA ( )


<s> bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST


<s> rtx x = widen_memory_access ( mem1 , mode , <NUM_LIT> ) ; MEM_NOTRAP_P ( x ) = MEM_NOTRAP_P ( mem1 ) && MEM_NOTRAP_P ( mem2 ) ; return


<s> bool isImplicitlyTypedVectorList ( ) const { return Kind == k_VectorList && VectorList . Count == NumRegs && VectorList . NumElements

== <NUM_LIT> && VectorList . RegisterKind == VectorKind ;


<s> break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT>


<s> return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext (

) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ;


<s> if ( const ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( CP -> getConstVal ( ) , CP -> getValueType ( <NUM_LIT> ) , CP -> getAlignment ( ) , CP -> getOffset ( ) , TF ) ; if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol

( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ;