<s> bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill ) MIB -> addRegisterKilled


<s> const char * section = <STR_LIT> ; char buf [ <NUM_LIT> ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT>


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) PrivateGlobalPrefix = <STR_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue =


<s> if ( FenceOrdering == AtomicOrdering :: SequentiallyConsistent && FenceSSID == SyncScope :: System ) { if ( Subtarget . hasMFence ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return SDValue ( Res


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_srli_epi32 ( __m128i __A , int __B ) { __v4su rshift ; __v4si result = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) { if ( __B < <NUM_LIT> ) rshift = ( __v4su ) vec_splat_s32 ( __B ) ; else rshift = ( __v4su ) vec_splats ( ( unsigned int ) __B ) ; } else rshift = vec_splats ( ( unsigned int ) __B ) ; result = vec_sr ( ( __v4si ) __A ,


<s> bool <ISA_LIT>BaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( create<ISA_LIT>GlobalMergePass ( getTargetLowering ( ) ) ) ; return false


<s> const MCInstrDesc & <ISA_LIT>16InstrInfo :: AddiuSpImm (


<s> enum rs6000_builtins fn = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; switch ( fn ) { case RS6000_BUILTIN_RSQRTF : if ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( V4SFmode ) && out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ ALTIVEC_BUILTIN_VRSQRTFP ] ; break ; case RS6000_BUILTIN_RSQRT : if ( VECTOR_UNIT_VSX_P ( V2DFmode ) && out_mode == DFmode && out_n == <NUM_LIT> && in_mode == DFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; break ; case RS6000_BUILTIN_RECIPF : if ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( V4SFmode ) && out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ ALTIVEC_BUILTIN_VRECIPFP ] ; break ; case RS6000_BUILTIN_RECIP


<s> if ( RegNum == <NUM_LIT> ) RegNum = matchReqRegisterNameAlias ( Name , RegKind :: SVEVector ) ; return


<s> if ( Opc != TargetOpcode :: G_SHL && Opc != TargetOpcode :: G_ASHR && Opc != TargetOpcode :: G_LSHR ) return <NUM_LIT> ; auto MaybeShiftAmt = getConstantVRegValWithLookThrough ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! MaybeShiftAmt ) return <NUM_LIT> ; uint64_t ShiftAmt = MaybeShiftAmt -> Value . getZExtValue ( ) ; MachineInstr * ShiftLHS = getDefIgnoringCopies ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( IsSupportedExtend ( * ShiftLHS ) ) return ( ShiftAmt <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; LLT Ty = MRI . getType ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . isVector ( ) ) return <NUM_LIT> ; unsigned ShiftSize = Ty . getSizeInBits ( ) ; if ( ( ShiftSize == <NUM_LIT> && ShiftAmt <= <NUM_LIT> ) || ( ShiftSize == <NUM_LIT> && ShiftAmt <= <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFNEG ( SDValue Op , SelectionDAG & DAG ) const { LLVMContext * Context = DAG . getContext ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT>


<s> end_sequence ( ) ; gcc_assert ( INSN_P ( seq ) ) ; last_insn = seq ; while ( NEXT_INSN ( last_insn ) != NULL_RTX ) last_insn = NEXT_INSN ( last_insn ) ; compare = SET_SRC ( XVECEXP ( PATTERN ( last_insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; PUT_CODE ( XEXP ( compare , <NUM_LIT> ) , GET_CODE ( comparison ) ) ; XEXP ( compare , <NUM_LIT> ) = gen_rtx_LABEL_REF ( VOIDmode , label ) ; emit_insn ( seq


<s> MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I


<s> if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false


<s> OperandMatchResultTy parseGRH32 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands


<s> PrivateGlobalPrefix = <STR_LIT> ; } AsmTransCBE = x86_asm_table ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue =


<s> if ( const auto * SI = dyn_cast < BinaryOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) if ( ( SI -> getOpcode ( ) == Instruction :: Shl ) && ( C -> getZExtValue ( ) < <NUM_LIT> ) ) { unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( SI -> getOperand ( <NUM_LIT> ) ) ; return emitAddSub_rx ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ExtendType , C -> getZExtValue ( ) , SetFlags , WantResult ) ; } unsigned RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( RHS ) ; return emitAddSub_rx ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ExtendType , <NUM_LIT> , SetFlags , WantResult ) ; } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; unsigned RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( MulLHS ) ; return emitAddSub_rs ( UseAdd , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , <STR_LIT> , ShiftVal , SetFlags , WantResult ) ; } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) if ( const auto *

SI = dyn_cast < BinaryOperator > ( RHS ) ) {


<s> static void ix86_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_AVX512F && ! TARGET_PREFER_AVX256 ) { sizes -> safe_push ( <NUM_LIT> ) ; sizes -> safe_push ( <NUM_LIT> ) ; sizes -> safe_push ( <NUM_LIT> ) ; } else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) { sizes -> safe_push ( <NUM_LIT> )


<s> } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: CommonLinkage : case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: PrivateLinkage : case GlobalValue :: InternalLinkage : break ; case GlobalValue :: GhostLinkage : cerr << <STR_LIT> ; abort ( ) ; case GlobalValue :: DLLImportLinkage : cerr << <STR_LIT> ; abort ( ) ; case GlobalValue :: DLLExportLinkage : cerr << <STR_LIT> ; abort ( ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } EmitAlignment ( Align , GVar ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) ) { O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << Size << '\n' ; } O << name << <STR_LIT> ; EmitGlobalConstant ( C


<s> MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) ->


, <NUM_LIT> , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( __m256i ) __builtin_ia32_pmaddubsw256 ( ( __v32qi ) __X ,


<s> int Imm = SignExtend32 < <NUM_LIT> > ( Insn ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( CurrentFnSym )


<s> if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; unsigned OpNo = getOpIdxForMO ( MI , MO ) ; unsigned Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MCII . get ( MI . getOpcode ( ) ) , MO . getReg ( ) , OpNo ) ; return CTX . getRegisterInfo ( ) -> getEncodingValue


<s> SDValue Base ; unsigned SrcOpnd ; MachineMemOperand * MMO ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; Chain = ST -> getChain ( ) ; Base = ST -> getBasePtr ( ) ; MMO = ST -> getMemOperand ( ) ; SrcOpnd = <NUM_LIT> ; if ( MMO -> getSize ( ) < <NUM_LIT> ) return SDValue ( ) ; break ; } case <STR_LIT> : { MemIntrinsicSDNode * Intrin = cast < MemIntrinsicSDNode > ( N ) ; Chain = Intrin -> getChain ( ) ; Base = Intrin -> getOperand ( <NUM_LIT> ) ; MMO = Intrin -> getMemOperand ( ) ; SrcOpnd = <NUM_LIT> ; break ; } } SDValue Src = N -> getOperand ( SrcOpnd ) ; MVT VecTy = Src . getValueType (


<s> JITCompilerFunction = F ; return <ISA_LIT>CompilationCallback


<s> SDValue Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , getZeroVector ( MaskVT , Subtarget , DAG , dl ) , Idx , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; SDValue Perm = DAG . getNode ( <STR_LIT> , dl , VecVT , Mask , Vec ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Perm , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } return SDValue ( ) ; } if ( VecVT . is256BitVector ( ) || VecVT . is512BitVector ( ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; Vec = Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; IdxVal -= ( IdxVal / ElemsPerChunk ) * ElemsPerChunk ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx ==


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateFGRReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , RegKind_FGR , RegInfo , S ,


<s> enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = op0 ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0


<s> IsLittleEndian = false ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS =


<s> if ( ! STI -> padShortFunctions ( ) ) return false ; TII = STI -> getInstrInfo ( ) ; ReturnBBs . clear ( ) ; VisitedBBs . clear ( ) ; findReturns ( & MF . front ( ) ) ; bool MadeChange = false ; MachineBasicBlock * MBB ; unsigned int Cycles = <NUM_LIT> ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold


<s> } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset


<s> unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR

) && ! RegInfo -> hasBasePointer ( MF ) ) {


<s> Inst . addOperand ( MCOperand :: createImm


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + TuneCPU


<s> unsigned EIndex = MemOps . size ( ) ; do { const MachineInstr * MI = MemOps [ SIndex ] . MI ; int Offset = MemOps [ SIndex ] . Offset ; const MachineOperand & PMO = getLoadStoreRegOp ( * MI ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? std :: numeric_limits < unsigned > :: max ( ) : TRI -> getEncodingValue ( PReg ) ; unsigned Latest = SIndex ; unsigned Earliest = SIndex ; unsigned Count = <NUM_LIT> ; bool CanMergeToLSDouble = STI -> isThumb2 ( ) && isNotVFP && isValidLSDoubleOffset ( Offset ) ; if ( STI -> isCortexM3 ( ) && isi32Load ( Opcode ) && PReg == getLoadStoreBaseOp ( * MI ) . getReg ( ) ) CanMergeToLSDouble = false ; bool CanMergeToLSMulti = true ; if ( STI -> hasSlowOddRegister ( ) && ! isNotVFP && ( PRegNum % <NUM_LIT> ) == <NUM_LIT> ) CanMergeToLSMulti = false ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) CanMergeToLSMulti = CanMergeToLSDouble = false ; if ( AssumeMisalignedLoadStores && ! mayCombineMisaligned ( * STI , * MI ) ) CanMergeToLSMulti = CanMergeToLSDouble = false ; unsigned Limit ; switch ( Opcode ) { default : Limit = UINT_MAX ; break ; case <STR_LIT> : case <STR_LIT> : Limit = <NUM_LIT> ; break ; } for ( unsigned I = SIndex + <NUM_LIT> ; I < EIndex ; ++ I , ++ Count ) { int NewOffset = MemOps [ I ] . Offset ; if ( NewOffset != Offset + ( int ) Size ) break ; const MachineOperand & MO = getLoadStoreRegOp ( * MemOps [ I ] . MI ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( ( ShifterImm . isASR <<


<s> void addRegGPRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT> ; CMPop = <STR_LIT> ; CALLop = <STR_LIT> ; SPLimitOffset = <NUM_LIT> ; } else { SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT> ; CMPop = <STR_LIT> ; CALLop = <STR_LIT> ; SPLimitOffset = <NUM_LIT> ; } ScratchReg = GetScratchRegister ( Is64Bit , IsLP64 , MF , true ) ; assert ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg ) && <STR_LIT> ) ; addRegOffset ( BuildMI ( stackCheckMBB , DL , TII . get ( LEAop ) , ScratchReg ) , SPReg , false , - MaxStack ) ; addRegOffset ( BuildMI ( stackCheckMBB , DL , TII . get ( CMPop ) ) . addReg ( ScratchReg ) , PReg , false , SPLimitOffset ) ; BuildMI ( stackCheckMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & PrologueMBB ) ; BuildMI ( incStackMBB , DL , TII . get ( CALLop ) ) . addExternalSymbol ( <STR_LIT> ) ; addRegOffset ( BuildMI ( incStackMBB , DL , TII . get ( LEAop ) , ScratchReg ) , SPReg , false , - MaxStack ) ; addRegOffset ( BuildMI ( incStackMBB , DL , TII . get ( CMPop ) ) . addReg ( ScratchReg


<s> if ( MatchAddress ( N , AM ) ) return false ; assert ( T == AM . Segment ) ; AM . Segment = Copy ; EVT VT = N . getValueType ( ) ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) if ( AM . Base . Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> )


<s> const MCSymbol * Symbol = <NUM_LIT> ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = AP . getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand


<s> addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> virtual <ISA_LIT>JITInfo * getJITInfo ( ) { llvm_unreachable ( <STR_LIT>


<s> enum machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { if ( TARGET_64BIT ) { rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> ; int ub = int_size_in_bytes ( valtype ) <= UNITS_PER_WORD ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> + i ) , GEN_INT ( offset ) ) ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( int_size_in_bytes ( valtype ) > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) <

BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ;


<s> if ( ! MOp . isGlobal ( ) ) return false ; auto * CalleeFn = dyn_cast < Function > ( MOp . getGlobal (


<s> return new <ISA_LIT>StackTaggingPreRA ( )


<s> bool IsUnscaled = TII -> isUnscaledLdSt ( LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( LoadI ) . getImm ( ) : getLdStOffsetOp ( LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( StoreI ) . getImm ( ) : getLdStOffsetOp ( StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt , getKillRegState ( StRtIsKill ) ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt , getKillRegState ( StRtIsKill ) ) . addImm ( Immr ) . addImm ( Imms ) ; } } ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( )


<s> selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case


<s> case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSelectCCCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT>


<s> } Register SrcReg = Src . getReg ( ) ; if ( Opc != <STR_LIT> ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; if ( Register :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( Register :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ; isKill = true ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return


<s> SectionData :: FragmentListType & frag_list = m_SectionData -> getFragmentList ( ) ; SectionData :: iterator frag , fragEnd = m_SectionData -> end ( ) ; for ( frag = m_SectionData -> begin ( ) ; frag != fragEnd ; ++ frag ) { frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; } if ( ! m_GOTPLT . empty ( ) ) { m_pGOTPLTFront = m_GOTPLT . front ( ) ; entry_iterator it , end = m_GOTPLT . end ( ) ; for ( it = m_GOTPLT . begin ( ) ; it != end ; ++ it ) { <ISA_LIT>GOTEntry * entry = * it ; frag_list . push_back ( entry ) ; entry -> setParent ( m_SectionData ) ; entry -> setOffset ( offset ) ; offset += entry -> size ( ) ; } } m_GOTPLT . clear ( ) ; if ( ! m_GOT . empty ( ) ) { m_pGOTFront = m_GOT . front ( ) ; entry_iterator it , end = m_GOT . end ( ) ; for ( it = m_GOT . begin ( ) ; it != end ; ++


<s> if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; if ( mode == DImode ) return ( ne == <NUM_LIT> || nb == <NUM_LIT> || ( nb < <NUM_LIT> && ne <= nb ) ) ; if ( mode == SImode ) return ( nb <


<s> static inline bool hasImm ( unsigned TSFlags


<s> DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void *


<s> if ( isLittleEndianTriple ( T ) ) Ret = <STR_LIT> ; else Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( T ) ; if ( ! is64Bit || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( is64Bit && ( T . isOSAIX ( ) || T


<s> return sparc_function_arg_1 ( cum , mode , type , named


<s> MVT LegalVT = getTLI ( ) -> getTypeLegalizationCost ( DL , VecTy ) . second ; if ( ! LegalVT . isVector ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; unsigned VF = VecTy -> getVectorNumElements ( ) / Factor ; Type * ScalarTy = VecTy -> getVectorElementType ( ) ; unsigned VecTySize = DL . getTypeStoreSize ( VecTy ) ; unsigned LegalVTSize = LegalVT . getStoreSize ( ) ; unsigned NumOfMemOps = ( VecTySize + LegalVTSize - <NUM_LIT> ) / LegalVTSize ; Type * SingleMemOpTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl


<s> XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { reg = gen_rtx_REG ( XFmode , base_reg ++ ) ; XVECEXP ( par , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( XFmode , plus_constant ( stack_pointer_rtx , i * <NUM_LIT> ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , i + <NUM_LIT> ) = tmp ; } tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> * count ) ) ) ; RTX_FRAME_RELATED_P ( tmp )


<s> WidenedMask . assign ( Mask . size ( ) / <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) { if ( Mask [ i ] == SM_SentinelUndef && Mask [ i + <NUM_LIT> ] == SM_SentinelUndef ) { WidenedMask [ i / <NUM_LIT> ] = SM_SentinelUndef ; continue ; } if ( Mask [ i ] == SM_SentinelUndef && Mask [ i + <NUM_LIT> ] >= <NUM_LIT> && Mask [ i + <NUM_LIT> ] % <NUM_LIT> == <NUM_LIT> ) { WidenedMask [ i / <NUM_LIT> ] = Mask [ i + <NUM_LIT> ] / <NUM_LIT> ; continue ; } if ( Mask [ i + <NUM_LIT> ] == SM_SentinelUndef && Mask [ i ] >= <NUM_LIT> && Mask [ i ] % <NUM_LIT> == <NUM_LIT> ) { WidenedMask [ i / <NUM_LIT> ] = Mask [ i ] / <NUM_LIT> ; continue ; } if ( Mask [ i ] == SM_SentinelZero || Mask [ i + <NUM_LIT> ]


<s> else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; OriginalCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; unsigned OpStart = <NUM_LIT> ; bool RAXImplicitDead = false ; for ( ; OpStart < MI . getNumOperands ( ) ; ++ OpStart ) { MachineOperand & Op = MI . getOperand ( OpStart ) ; if ( Op . isReg ( ) && Op . isImplicit ( ) && Op . isDead ( ) && TRI -> regsOverlap ( Op . getReg ( ) , <STR_LIT> ) ) { Op . setIsDead ( false ) ; Op . setIsDef (


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; addPass ( create<ISA_LIT>EvexToVexInsts (


<s> unsigned Register = FPR8DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register


<s> bool ErrorAndEatStatement ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None , bool MatchingInlineAsm = false ) { Parser . eatToEndOfStatement ( ) ; return Error ( L , Msg


<s> const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( MI . getOpcode ( ) == getCallFrameSetupOpcode ( ) || MI . getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; SPAdj -= MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == getCallFrameSetupOpcode ( ) ) return SPAdj ; else return - SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return <NUM_LIT> ; return - ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; } addPass ( create<ISA_LIT>EvexToVexInsts ( ) ) ; addPass ( create<ISA_LIT>DiscriminateMemOpsPass ( )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue


<s> bool <ISA_LIT>TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( <STR_LIT> , ResVT ) ) return false ; if ( ResVT . getVectorElementType ( ) == <STR_LIT> ) return Index == <NUM_LIT> || ( ( ResVT . getSizeInBits ( ) == SrcVT . getSizeInBits

( ) * <NUM_LIT> ) && ( Index == ResVT . getVectorNumElements ( ) ) ) ;


<s> return MEMMODEL_SEQ_CST ; } strong = ( is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) ; if ( val & IX86_HLE_ACQUIRE && ! ( is_mm_acquire ( model ) || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST | IX86_HLE_ACQUIRE ; } if ( val & IX86_HLE_RELEASE && ! ( is_mm_release ( model ) || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT>


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static unsigned matchSVEVectorRegName ( StringRef Name ) { return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )

. Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand ::


<s> assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , true , DAG , Subtarget ) ) return Res ; return SDValue


<s> if ( llvm :: all_of ( Offsets , [ ] ( unsigned Offset ) { return Offset == <NUM_LIT> ; } ) ) return SDValue ( ) ; EVT RootVT = Root . getValueType ( ) ; unsigned RootSizeInBits = RootVT . getSizeInBits ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return SDValue ( ) ; for ( SDValue & NewInput : WideInputs ) { assert ( ( WideSizeInBits % NewInput . getValueSizeInBits ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( WideSizeInBits > NewInput . getValueSizeInBits ( ) ) NewInput = widenSubVector ( NewInput , false , Subtarget , DAG , SDLoc ( NewInput ) , WideSizeInBits ) ; assert ( WideSizeInBits == NewInput . getValueSizeInBits ( ) && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) Offsets [ i ] += i * Scale * NumMaskElts ; SmallVector < int , <NUM_LIT> > WideMask ( BaseMask . begin ( ) , BaseMask . end ( ) ) ; for ( int & M : WideMask ) { if ( M < <NUM_LIT> ) continue ; M = ( M % NumMaskElts ) + Offsets [ M / NumMaskElts ] ; } WideMask . append ( ( Scale - <NUM_LIT> ) * NumMaskElts , SM_SentinelUndef ) ; resolveTargetShuffleInputsAndMask ( WideInputs , WideMask ) ; assert ( ! WideInputs . empty ( ) && <STR_LIT> ) ; if ( WideInputs . size ( ) > <NUM_LIT> ) return SDValue ( ) ; Depth += count_if ( Offsets , [ ] ( unsigned Offset ) { return Offset > <NUM_LIT> ; } ) ; SDValue WideRoot = WideInputs


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ,

MRI ) ) return RegOrConstant ( ValAndVReg -> Value . getSExtValue ( ) ) ;


<s> int Splat = getT2SOImmValSplatVal ( Arg ) ; if ( Splat != - <NUM_LIT> ) return Splat ; int Rot = getT2SOImmValRotateVal ( Arg ) ; if ( Rot != - <NUM_LIT>


<s> if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) <= MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return false


<s> static void initiate_bundle_state_table ( void


<s> return ( __m256i ) __builtin_ia32_expandloadhi256_mask ( ( const __v16hi * ) __C ,


<s> if ( bitmap_empty_p ( to_clear_core_bitmap ) ) return ; nb_regs = bitmap_count_bits ( to_clear_core_bitmap ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nb_regs + <NUM_LIT> ) ) ; start_sequence ( ) ; for ( j = <NUM_LIT> , i = minregno ; j < nb_regs ; i ++ ) { if ( ! bitmap_bit_p ( to_clear_core_bitmap , i ) ) continue ; reg = gen_rtx_REG ( SImode , i ) ; set = gen_rtx_SET ( reg , const0_rtx ) ; XVECEXP ( par , <NUM_LIT> , j ++ ) = set ; emit_use ( reg ) ; } vunspec_vec = gen_rtvec ( <NUM_LIT> , gen_int_mode ( <NUM_LIT> , SImode ) ) ; vunspec = gen_rtx_UNSPEC_VOLATILE ( SImode , vunspec_vec , VUNSPEC_CLRM_APSR ) ; XVECEXP ( par , <NUM_LIT> , j ++ ) = vunspec ; rtx ccreg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , ccreg ) ; XVECEXP ( par , <NUM_LIT> , j ) = clobber ; use_seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_after ( use_seq , emit_insn ( par ) ) ; } else { if ( clearing_regno <= maxregno && bitmap_bit_p ( to_clear_bitmap , clearing_regno ) ) { emit_move_insn ( clearing_reg , const0_rtx ) ; emit_use ( clearing_reg ) ; bitmap_clear_bit ( to_clear_bitmap , clearing_regno ) ; } for ( regno = minregno ; regno <= maxregno ; regno ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap , regno ) ) continue ; if ( IS_VFP_REGNUM ( regno ) ) { if ( TARGET_VFP_DOUBLE && VFP_REGNO_OK_FOR_DOUBLE ( regno ) && bitmap_bit_p ( to_clear_bitmap , regno + <NUM_LIT> ) ) { emit_move_insn ( gen_rtx_REG ( DFmode , regno ) , CONST1_RTX ( DFmode ) ) ; emit_use ( gen_rtx_REG ( DFmode , regno ) ) ; regno


<s> Value * <ISA_LIT>IREmitter :: visitTLSADDR ( const SDNode *


<s> gen_interleave_first_low = gen_vec_interleave_lowv8hi ; gen_interleave_second_low = gen_vec_interleave_lowv4si ; inner_mode = QImode ; first_imode = V8HImode ; second_imode = V4SImode ; third_imode = V2DImode ; break ; default : gcc_unreachable ( ) ; } for ( i = <NUM_LIT> ; i < n ; i ++ ) { op = ops [ i + i ] ; if ( inner_mode == HFmode || inner_mode == BFmode ) { rtx even , odd ; machine_mode vec_mode = ( inner_mode == HFmode ) ? V8HFmode : V8BFmode ; op0 = gen_reg_rtx ( vec_mode ) ; even = lowpart_subreg ( vec_mode , force_reg ( inner_mode , op ) , inner_mode ) ; odd = lowpart_subreg ( vec_mode , force_reg ( inner_mode , ops [ i + i + <NUM_LIT> ] ) , inner_mode ) ; emit_insn ( gen_load_even ( op0 , even , odd ) ) ; } else { op0 = gen_reg_rtx ( SImode ) ; emit_move_insn ( op0 , gen_lowpart ( SImode , op ) ) ; op1 = gen_reg_rtx ( V4SImode ) ; op0 = gen_rtx_VEC_MERGE ( V4SImode , gen_rtx_VEC_DUPLICATE ( V4SImode , op0 ) , CONST0_RTX ( V4SImode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( op1 , op0 ) ) ; op0 = gen_reg_rtx ( mode ) ; emit_move_insn ( op0 , gen_lowpart ( mode , op1 ) ) ; emit_insn ( gen_load_even ( op0 , force_reg ( inner_mode , ops [ i + i + <NUM_LIT> ] ) , const1_rtx ) ) ; } ops [ i ] = gen_reg_rtx ( first_imode ) ; emit_move_insn ( ops [ i ] , gen_lowpart ( first_imode , op0


<s> return __builtin_loongson_paddsb ( s , t


<s> HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFInfo = FuncInfo . MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC != CallingConv :: C && CC != CallingConv :: Fast && CC != CallingConv :: <ISA_LIT>_FastCall && CC != CallingConv :: <ISA_LIT>_64_SysV ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( <ISA_LIT>MFInfo -> getBytesToPopOnReturn ( ) != <NUM_LIT> ) return false ; if ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg


<s> return new <ISA_LIT>TargetAsmStreamer ( S , OS , * InstPrint , isVerboseAsm


<s> DebugLoc DL = MI . getDebugLoc ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; Register LabelReg = prepareMBB ( * MBB , MachineBasicBlock :: iterator ( MI ) , DispatchBB , DL ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addFrameReference ( MIB , FI , Offset


<s> return optimizeConvertFromSVBool ( IntrI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return optimizePTest ( IntrI ) ; default : return


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) )


<s> const char * \ current_section_name ( ) \ { \ switch ( in_section ) \ { \ case no_section : return NULL ; \ case in_text : return <STR_LIT> ; \ case in_data : return <STR_LIT> ; \ case in_sdata : return <STR_LIT> ; \ case in_bss : return <STR_LIT> ; \ case in_rdata : \ case in_const :

\ if ( mips_abi != ABI_32 && mips_abi != ABI_O64 ) \ return <STR_LIT> ; \ else \ return <STR_LIT> ; \ case in_named : \ return in_named_name ; \ } \ abort ( ) ; \ }


<s> lo = UINTVAL ( op ) & <NUM_LIT> ; hi = UINTVAL ( op ) >> <NUM_LIT> ; return const_ok_for_arm ( lo ) &&


<s> GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand (


<s> MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred ->


<s> assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; int NumElts = Mask . size ( ) ; int SubvecElts = <NUM_LIT> ; int Src = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> ) { if ( Src < <NUM_LIT> ) Src = Mask [ i ] / NumElts ; if ( Src != ( Mask [ i ] / NumElts ) || ( Mask [ i ] % NumElts ) != i ) break ; } ++ SubvecElts ; } assert ( SubvecElts != NumElts && <STR_LIT> ) ; SubvecElts = PowerOf2Floor ( SubvecElts ) ; if ( ( int ) Zeroable . countLeadingOnes ( ) >= ( NumElts - SubvecElts ) ) { assert ( Src >= <NUM_LIT> && <STR_LIT> ) ; MVT ExtractVT = <STR_LIT> ( <STR_LIT> , SubvecElts ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , ExtractVT , Src == <NUM_LIT> ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Extract , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Shift = lower1BitShuffleAsKSHIFTR ( DL , Mask , VT , V1 , V2 , Subtarget , DAG ) ) return Shift ; unsigned Offset = <NUM_LIT> ; for ( SDValue V : { V1 , V2 } ) { unsigned Opcode ; int ShiftAmt = match1BitShuffleAsKSHIFT ( Opcode , Mask , Offset , Zeroable ) ; if ( ShiftAmt >= <NUM_LIT> ) { MVT WideVT = VT ; if ( ( ! Subtarget . hasDQI ( ) && NumElts == <NUM_LIT> ) || NumElts < <NUM_LIT> ) WideVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getUNDEF (

WideVT ) , V , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> getBitfieldInvertedMaskOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = countTrailingZeros ( v ) ; uint32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; assert ( v != <NUM_LIT> && lsb < <NUM_LIT> && msb < <NUM_LIT> && <STR_LIT> ) ; return lsb | ( msb << <NUM_LIT>


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l + i ] ; int BitI1 = Mask [ l + i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( V2IsSplat ) { if ( ! isUndefOrEqual ( BitI1 , NumElts ) ) return false ; }


<s> return ( __m512i ) __builtin_ia32_pbroadcastb512_gpr_mask ( __A , ( __v64qi )


<s> bool hasXMM ( ) const { return hasSSE1 ( ) || hasAVX


<s> if ( ( Ty . isScalar ( ) && ! isFP ) || Ty . isPointer ( ) ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : return PMI_GPR8 ; case <NUM_LIT> : return PMI_GPR16 ; case <NUM_LIT> : return PMI_GPR32 ; case <NUM_LIT> : return PMI_GPR64 ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Ty . isScalar ( ) ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return PMI_FP32 ; case <NUM_LIT> : return PMI_FP64 ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Ty . getSizeInBits ( )


<s> MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI . eraseFromParent ( ) ; return BB


<s> return ( ( int_size_in_bytes ( type ) > ( <NUM_LIT> * UNITS_PER_WORD )

) || ( int_size_in_bytes ( type ) == - <NUM_LIT> ) ) ;


<s> if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; } else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ; if ( LS && ( LS -> getMemoryVT ( ) == <STR_LIT> || LS -> getMemoryVT ( ) == <STR_LIT> ) && Subtarget . hasFPIdx ( ) ) return false ; } Base =


<s> bool <ISA_LIT>ShortenInst :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; bool Changed =


<s> return ( int32x2_t ) __builtin_aarch64_sqshl_nv2si


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const <ISA_LIT>RegisterInfo & MRI , DebugLoc dl ) { bool isHigh = ! MRI . isLowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! MRI . isLowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , false , false , true ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addReg ( LdReg , false , false , true ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , LdReg , NumBytes , <STR_LIT> , <NUM_LIT> , & TII , true , dl ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl ,


<s> bool hasVP2INTERSECT ( ) const { return HasVP2INTERSECT


<s> if ( NewPt == IPI . first || DT . dominates ( IPI . first , NewPt ) || ( IPI . first -> getParent ( ) != NewPt -> getParent ( ) && DT . dominates ( IPI . first -> getParent ( ) , NewPt -> getParent ( ) ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( IPI . first -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << '\n' ) ; IPI . second . emplace_back ( User , OpNo


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; return AM . Scale == <NUM_LIT> || AM . Scale ==


<s> getActionDefinitionsBuilder ( { G_UADDE , G_USUBO , G_USUBE } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemSize ( { { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemSize ( { { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT>


<s> int64_t Value2 = Value >> Shift ; if ( ( ( Value & ( int64_t ) maskTrailingZeros < uint64_t > ( Shift ) ) == Value ) && ( Value2 >= LBound ) && ( Value2 < HBound ) ) return true ; return


<s> break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) )


<s> SDValue Copy = Op0 -> getOperand ( <NUM_LIT> ) ; if ( Copy . getValueType ( ) == <STR_LIT> && Copy -> getOpcode ( ) == <STR_LIT> ) { SDValue Ops [ ] = { Copy -> getOperand ( <NUM_LIT> ) , Copy -> getOperand ( <NUM_LIT> ) } ; SDValue NewCopy = DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Ops ) ; return NewCopy ; } } APInt DemandedMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; const TargetLowering & TLI = DCI . DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Op0 , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( )


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; if ( ! ( rsym -> reserved ( ) & ( <ISA_LIT>Relocator :: ReserveGOT ) ) ) return Relocator :: BadReloc ; <ISA_LIT>_32GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp (


<s> vec_uint4 bv ; vec_uint4 mask ; bv = vec_splat ( ( vec_uint4 ) ( si_from_uint ( b ) ) , <NUM_LIT> ) ; mask = ( vec_uint4 ) vec_sra ( vec_sl ( bv , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } )

) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , <ISA_LIT>Lowering ( * TM . getTargetLowering ( ) ) , <ISA_LIT>SubTarget ( * TM . getSubtargetImpl ( ) ) { initialize<ISA_LIT>DAGToDAGISelPass ( * PassRegistry :: getPassRegistry ( )


<s> auto IsFreelyInvertable = [ & ] ( SDValue V ) { if ( V -> getOpcode ( ) == <STR_LIT> || V -> getOpcode ( ) == <STR_LIT> ) return CanInvertMVEVCMP ( V ) ; return false ; } ; if ( ! ( IsFreelyInvertable ( N0 ) || IsFreelyInvertable ( N1 ) ) ) return SDValue ( ) ; SDValue NewN0 = DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DAG . getLogicalNOT ( DL , N1 , VT ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL


<s> bool <ISA_LIT>AsmParser :: parseCondCode ( OperandVector & Operands , bool invertCondCode ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Cond = Tok . getString (


<s> i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; if ( deadCPSR ) { assert ( ! MI -> getOperand ( ccOutIdx ) . getReg ( ) && <STR_LIT> ) ; return ; } MachineOperand & MO = MI -> getOperand (


<s> llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_R : case InlineAsm ::


<s> unsigned Directive = <ISA_LIT>SubTarget . getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return Sched :: ILP ; return TargetLowering :: getSchedulingPreference (


<s> return ( ( vec_int4 ) ( si_cgx ( ( qword ) ( a ) , ( qword ) ( b ) ,


<s> return CONST_OK_FOR_L ( value ) ; case 'M' : return CONST_OK_FOR_M ( value ) ; case 'N' : return CONST_OK_FOR_N ( value ) ; case 'O' : return CONST_OK_FOR_O ( value ) ; case


<s> ConstantSDNode * ConstOp1 = dyn_cast < ConstantSDNode > ( CmpOp1 . getNode ( ) ) ; if ( ! ConstOp1 ) return ; int64_t Value = ConstOp1 -> getSExtValue ( ) ; if ( ( Value == - <NUM_LIT> && CCMask == <STR_LIT> ) || ( Value == - <NUM_LIT> && CCMask == <STR_LIT> ) || ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) || ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) ) { CCMask ^= <STR_LIT> ; CmpOp1 = DAG . getConstant ( <NUM_LIT> , CmpOp1 .


<s> OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; emitNops ( NoopsInSledCount ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , Kind ,


<s> if ( CUReg == - <NUM_LIT> ) return ~ <NUM_LIT> ; SavedRegs [ i ] = CUReg ; } std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; uint32_t RenumRegs [ CU_NUM_SAVED_REGS ] ; for ( unsigned i = CU_NUM_SAVED_REGS - RegCount ; i < CU_NUM_SAVED_REGS ; ++ i ) { unsigned Countless = <NUM_LIT> ; for ( unsigned j = CU_NUM_SAVED_REGS - RegCount ; j < i ; ++ j

) if ( SavedRegs [ j ] < SavedRegs [ i ] ) ++ Countless ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { TargetRegistry :: RegisterMCAsmInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ITCondMask ) ; Op -> ITMask . Mask = Mask ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> Value * <ISA_LIT>IREmitter :: visitVQRSHRNs (


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> void <ISA_LIT>MachObjectWriter :: Record<ISA_LIT>Relocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) { unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Log2Size = getFixupKindLog2Size ( Fixup . getKind ( ) ) ; if ( Target . getSymA ( ) && Target . getSymA ( ) -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP ) { RecordTLVPRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; return ; } if ( Target . getSymB ( ) ) { RecordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; return ; } const MCSymbolData * SD = nullptr ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && SD && ! Writer -> doesSymbolRequireExternRelocation ( SD ) && RecordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ) return ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { Type = MachO :: GENERIC_RELOC_VANILLA ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> getSymbol ( ) . isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent


<s> unsigned getSRetReturnReg ( ) const { return


<s> unsigned <ISA_LIT>InstructionSelector :: selectLoadStoreOpCode ( unsigned Opc , unsigned RegBank , unsigned Size ) const { bool isStore = Opc == TargetOpcode :: G_STORE ; if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? Opcodes . STORE8 : Opcodes . LOAD8 ; case


<s> bool enableMachineScheduler ( ) const override


<s> FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 =


<s> case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Reg ) { case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ; case <STR_LIT> : assert ( ! Subtarget . is64Bit


<s> if ( ! MI . hasOneMemOperand ( ) ) return false ; if ( mergedOpcode ( MI . getOpcode ( ) , false ) == <NUM_LIT> ) return false ; const MachineMemOperand * MemOperand = * MI . memoperands_begin ( ) ; if ( MemOperand -> isVolatile


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section ) ; MCELFStreamer :: ChangeSection ( Section ,


<s> StringRef FPType ; bool IsLegal = false ; SmallString < <NUM_LIT> > ImmStrVal ; Imm . toString ( ImmStrVal ) ; if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( UNITS_PER_WORD ) ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR ,


<s> static bool isImmSExti16i8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value &&


<s> SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) ; return true


<s> static __inline qword si_shlqbyi ( qword a , unsigned int count ) { union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; }


<s> return ( float32x2_t ) __builtin_neon_vaddv2sf (


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ,

<STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> static MachineOperand makeImplicit ( const MachineOperand & MO ) { MachineOperand NewMO = MO ; NewMO . setImplicit ( ) ; return NewMO


<s> unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isLiveIn = MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; std :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( const RegAndKill & LHS , const RegAndKill & RHS ) { return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState (


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask


<s> return DecodeCAS ( MI , insn , Address , Decoder , false , false ,


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredWinAlloca ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetMacho ( ) ) ; if ( Subtarget -> isTargetWin64 ( ) ) { if ( Subtarget -> isTargetCygMing ( ) ) { BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define


<s> u . v = a ; u . i [ pos ] = b ; return u


<s> assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> vshiftInt = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( vshiftInt , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> )


<s> case ISA_EXT_FPU64 : return set1 -> fpu == ISA_EXT_FPU64 ; case ISA_EXT_FPU32 : return set1 -> fpu == ISA_EXT_FPU32 || set1 -> fpu == ISA_EXT_FPU64 ; case


<s> case <STR_LIT> : if ( ! LdSt -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; BaseReg = LdSt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction & MF = * LdSt -> getParent ( ) -> getParent ( ) ; unsigned Width = getRegClass ( LdSt -> getDesc ( ) , <NUM_LIT> , TRI , MF


<s> gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; gcc_assert ( n_elt == call_expr_nargs ( exp ) ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( n_elt == <NUM_LIT> && GET_MODE_SIZE ( tmode ) == GET_MODE_SIZE ( inner_mode ) ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> )


<s> return MatchOperand_Success ; } Index = matchFPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFCCRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success


<s> const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; assert ( ( unsigned ) NumBytes >= ArgRegsSaveSize && <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; Register FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize , <STR_LIT> , MachineInstr :: NoFlags ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister = <STR_LIT> ; bool HasFP = hasFP ( MF ) ; for ( auto & I : MFI . getCalleeSavedInfo ( ) ) { unsigned Reg = I . getReg ( ) ; if ( is<ISA_LIT>LowRegister ( Reg ) && ! ( HasFP && Reg == FramePtr ) ) { ScratchRegister = Reg ; break ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , PMBBI , TII

, dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ;


<s> return ( __m128i ) __builtin_ia32_vpdpbusd_v4si ( ( __v4si ) __A , (


<s> ByValArgs . push_back ( FIPtr ) ; } Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , dl , PtrVT , true ) , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned i = <NUM_LIT> , j = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ j ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , dl ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; if ( IsPIC ) { unsigned GPReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , GPReg , getGlobalReg ( DAG , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ; if ( G


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCapFloat32Store ( MachineInstr & MI , MachineBasicBlock * BB


<s> if ( ! RM . hasValue ( ) || * RM == Reloc :: DynamicNoPIC ) return Reloc :: Static ; return * RM


<s> else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) { gcc_assert ( REG_P ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( legitimate_constant_pool_address_p ( x ) ) { if ( TARGET_AIX && ( ! TARGET_ELF || ! TARGET_MINIMAL_TOC ) ) { rtx contains_minus = XEXP ( x , <NUM_LIT> ) ; rtx minus , symref ; const char * name ; while ( GET_CODE ( XEXP ( contains_minus , <NUM_LIT> ) ) != MINUS ) contains_minus = XEXP ( contains_minus , <NUM_LIT> ) ; minus = XEXP ( contains_minus , <NUM_LIT> ) ; symref = XEXP ( minus , <NUM_LIT> ) ; XEXP ( contains_minus , <NUM_LIT> ) = symref ; if ( TARGET_ELF ) { char * newname ; name = XSTR ( symref , <NUM_LIT> ) ; newname = alloca ( strlen ( name ) + sizeof ( <STR_LIT> ) ) ; strcpy ( newname , name ) ; strcat ( newname , <STR_LIT> ) ; XSTR ( symref , <NUM_LIT> ) = newname ; } output_addr_const ( file , XEXP (


<s> const <ISA_LIT>TargetMachine * getTargetMachine (


<s> inline void getAddressOperands ( <ISA_LIT>ISelAddressMode & AM , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp ) { Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp ) ; else if ( AM . ES ) Disp = CurDAG

-> getTargetExternalSymbol ( AM . ES , <STR_LIT> ) ;


<s> assert ( ( isa < ConstantInt > ( Elt ) || isa < ConstantFP > ( Elt ) ) && <STR_LIT> ) ; bool Sign = V -> getElementType ( ) -> isIntegerTy ( ) ? cast < ConstantInt > ( Elt ) -> isNegative ( ) : cast < ConstantFP > ( Elt ) -> isNegative ( ) ; BoolVec . push_back ( ConstantInt :: get ( BoolTy , Sign


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { if ( MBB . empty ( ) ) return <NUM_LIT> ; unsigned NumRemoved = <NUM_LIT> ; auto I = MBB . end ( ) ; do { -- I


<s> void FPS :: handleZeroArgFP ( MachineBasicBlock :: iterator & I ) { MachineInstr * MI = I ; unsigned DestReg = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; MI -> RemoveOperand (


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee ) const { <STR_LIT> SpecialCallConv = <STR_LIT> ; return SpecialCallConv


<s> IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; do { DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { const MCInstrDesc & Desc = I -> getDesc ( ) ; emitInstruction ( * I , & Desc ) ; if ( Desc . getOpcode ( ) == <STR_LIT> ) emitInstruction ( * I , & II -> get ( <STR_LIT> ) ) ; ++ NumEmitted


<s> while ( link ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( use_insn ) ] . will_delete = <NUM_LIT> ; link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( def_insn ) ] . will_delete = <NUM_LIT> ; link = link ->


<s> bool SelectAddrIdxOnly ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Index ) { return <ISA_LIT>Lowering . SelectAddressRegRegOnly ( N ,


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult .


<s> void <ISA_LIT>InstPrinter :: printNoHashImmediate ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << MI -> getOperand ( OpNum ) .


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiti ( ( __builtin_neon_ti


<s> case ADDRESS_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_INC_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_MODIFY_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_FP_IMM7U : output_asm_insn ( <STR_LIT> , operands )


<s> assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT> ) ; MCTargetStreamer & TS = * getParser ( )

. getStreamer ( ) . getTargetStreamer ( ) ;


<s> unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [


<s> if ( featureBits [ <STR_LIT> ] && ( ( Num & <NUM_LIT> ) == <NUM_LIT> || ( Num & <NUM_LIT> ) == <NUM_LIT> ) ) return false ; return


<s> if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT>

) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> assert ( Op1Ty . isVector ( ) && <STR_LIT> ) ; if ( Op1Ty . getSizeInBits ( ) >= <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Op1Ty . getSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } const LLT ScalarTy = LLT :: scalar ( Op1Ty . getSizeInBits ( ) ) ; const RegisterBank & FPRBank = * RBI . getRegBank ( Op1 , MRI , TRI ) ; const TargetRegisterClass * DstRC = getMinClassForRegBank ( FPRBank , Op1Ty . getSizeInBits ( ) * <NUM_LIT> ) ; MachineInstr * WidenedOp1 = emitScalarToVector ( ScalarTy . getSizeInBits ( ) , DstRC , Op1 , MIRBuilder ) ; MachineInstr * WidenedOp2 = emitScalarToVector ( ScalarTy . getSizeInBits ( ) , DstRC , Op2 , MIRBuilder ) ; if ( ! WidenedOp1 || ! WidenedOp2 ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertOpc , InsSubRegIdx


<s> if ( RegNum > getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RegClass ) . getNumRegs ( )


<s> static bool isReassociationCandidate ( const MachineInstr & Inst , bool & Commuted ) { if ( isAssociativeAndCommutative ( Inst ) && hasReassociableOperands ( Inst , Inst . getParent ( ) ) && hasReassociableSibling ( Inst , Commuted ) ) return true ; return


<s> if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body )


<s> rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode


<s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; machine_mode libval_mode = smallest_mode_for_size ( <NUM_LIT> * GET_MODE_BITSIZE ( mode ) , MODE_INT ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , <NUM_LIT> , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) ) ; rtx quotient = simplify_gen_subreg ( mode , libval


<s> bool <ISA_LIT>AsmParser :: parsePrePost ( StringRef Type , int * OffsetValue ) { bool PreOrPost = false ; if ( Lexer . getKind ( ) == Lexer . peekTok ( true ) . getKind ( ) ) { PreOrPost = true ; if ( Lexer . is ( AsmToken :: Minus ) ) * OffsetValue = - SizeForSuffix ( Type ) ; else if ( Lexer . is ( AsmToken :: Plus ) ) * OffsetValue = SizeForSuffix ( Type ) ; else return false ; Parser . Lex ( ) ; Parser . Lex ( ) ; } else if ( Lexer . is ( AsmToken :: Star ) ) { Parser . Lex ( ) ; PreOrPost =


<s> int64_t Value = CE -> getValue ( ) ; return ( ( Value & <NUM_LIT> ) == <NUM_LIT> ) && Value >= <NUM_LIT> &&


<s> VEXTOffsets [ i ] = <NUM_LIT> ; continue ; } else if ( SourceVecs [ i ] . getValueType ( ) . getVectorNumElements ( ) < NumElts ) { ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getUNDEF ( SourceVecs [ i ] . getValueType ( ) ) ) ; continue ; } if ( SourceVecs [ i ] . getValueType ( ) . getVectorElementType ( ) != VT . getVectorElementType ( ) ) return SDValue ( ) ; assert ( SourceVecs [ i ] . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> * NumElts && <STR_LIT> ) ; if ( MaxElts [ i ] - MinElts [ i ] >= NumElts ) { return SDValue ( ) ; } if ( MinElts [ i ] >= NumElts ) { VEXTOffsets [ i ] = NumElts ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; } else if ( MaxElts [ i ] < NumElts ) { VEXTOffsets [ i ] = <NUM_LIT> ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { VEXTOffsets [ i ] = MinElts [ i ] ; SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; unsigned Imm = VEXTOffsets [ i ] * getExtFactor ( VEXTSrc1 ) ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) == <STR_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } SDValue ExtractVec = Entry . getOperand ( <NUM_LIT>


<s> if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI .

GetBasePtr ( ) : ABI . GetStackPtr ( ) ;


<s> if ( ! FuncInfo . CanLowerReturn ) return false ; if ( TLI . supportSplitCSR ( FuncInfo . MF ) ) return false ; const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( RV ) ) { CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; Register RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( CI , <STR_LIT> , VA . getLocInfo ( ) != CCValAssign :: ZExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs .


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N ->


<s> SDValue StoredVal = St -> getValue ( ) ; if ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { assert ( StoredVal . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue


<s> <ISA_LIT>Disassembler ( ) : MCDisassembler ( )


<s> return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA -> getReachingMIDef ( Start , <STR_LIT> ) ) if ( IsMoveLR ( LRDef ) && RDA -> hasSameReachingDef ( Start , LRDef , CountReg ) ) return LRDef ; if ( auto * LRDef = RDA -> getLocalLiveOutMIDef ( MBB , <STR_LIT> ) ) if ( IsMoveLR ( LRDef ) && RDA -> hasSameReachingDef ( Start , LRDef , CountReg ) ) return LRDef ; if ( ! RDA -> isRegUsedAfter ( Start , <STR_LIT> ) ) return Start ; return nullptr


<s> if ( FixupKind != FK_Data_4 ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } FixupKind = FK_PCRel_4 ; } MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4


<s> rtx dwarf = NULL_RTX ; dwarf = alloc_reg_note ( REG_CFA_RESTORE ,


<s> for ( unsigned i = <NUM_LIT> , e = StructT -> getNumElements ( ) ; i != e ; ++ i ) if ( StructT -> getElementType ( i ) != StructT -> getElementType ( <NUM_LIT> ) ) return false ; return true ; } EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT

. isFloatingPoint ( ) ) ) return false ;


<s> void <ISA_LIT>InstPrinter :: printNeonUImm8OperandBare ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MOUImm = MI -> getOperand


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MIB -> setDebugLoc ( DL ) ; MIB -> setDesc ( TII . get (