<s> MCContext & Context = getParser ( ) . getContext ( ) ; Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; switch ( E -> getKind ( ) ) { case MCExpr :: Target : case MCExpr :: Constant : return <NUM_LIT> ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( E ) ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; default : return <NUM_LIT> ; } return MCSymbolRefExpr :: Create ( & SRE -> getSymbol ( ) , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = ExtractModifierFromExpr ( UE -> getSubExpr ( ) , Variant ) ; if ( ! Sub ) return <NUM_LIT> ; return MCUnaryExpr :: Create ( UE -> getOpcode ( ) , Sub , Context ) ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; <ISA_LIT>MCExpr :: VariantKind LHSVariant ,


<s> const <ISA_LIT>FrameLowering * llvm :: create<ISA_LIT>16FrameLowering ( const <ISA_LIT>Subtarget


<s> bool <ISA_LIT>AsmPrinter :: printAsmRegInClass ( const MachineOperand & MO , const TargetRegisterClass * RC , bool isVector , raw_ostream & O ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI -> getRegisterInfo ( ) ; Register Reg = MO


<s> ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; bool BumpSP = RPII == std :: prev ( RegPairs . end ( ) ) ; if ( RPI . IsGPR ) { if ( BumpSP ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; } else { if ( BumpSP ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; } DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg2 ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; const int Offset = RPI . Offset ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( BumpSP ) MIB . addReg ( <STR_LIT> , RegState :: Define ) ; if ( RPI . isPaired ( ) ) MIB . addReg ( Reg2 , getDefRegState ( true ) ) . addReg ( Reg1 , getDefRegState ( true )

) . addReg ( <STR_LIT> ) . addImm ( Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> return new <ISA_LIT>ELFTargetAsmInfo ( *


<s> } const MCInstrDesc & UseMCID = UseMI . getDesc ( ) ; if ( UseMCID . hasOptionalDef ( ) ) { unsigned NumOps = UseMCID . getNumOperands ( ) ; if ( UseMI . getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; } unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { if ( UseOpc == <STR_LIT> && Commute ) return false ; if ( <STR_LIT> ( ImmVal ) ) NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> ( - ImmVal ) ) { ImmVal = - ImmVal ; NewUseOpc = UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc =


<s> if ( has_scale ) return true ; if ( split_cost < <NUM_LIT> ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use (


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Cand . BranchBlock -> succ_size ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } assert ( Cand . BranchBlock -> canFallThrough ( ) && <STR_LIT> ) ; MachineBasicBlock * Succ = ( * Cand . BranchBlock -> succ_begin ( ) == Cand . BranchTargetBlock ) ? * Cand . BranchBlock -> succ_rbegin ( ) : * Cand . BranchBlock -> succ_begin ( ) ; assert ( Succ && <STR_LIT> ) ; if ( ! Succ -> empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! Succ -> isSuccessor ( Cand . BranchTargetBlock ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Cand . FallThroughBlock =


<s> MachineOperand & Row = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Col = MI . getOperand ( <NUM_LIT> ) ; unsigned TMMIdx = MI . getOperand ( <NUM_LIT> ) . getReg ( ) - <STR_LIT> ; ShapeInfos . push_back ( { TMMIdx , ShapeT ( & Row , & Col ) } ) ; } else { int SS = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; for ( auto & ShapeInfo : ShapeInfos ) { DebugLoc DL ; unsigned TMMIdx = ShapeInfo . first ; Register RowReg = ShapeInfo . second . getRow ( ) -> getReg ( ) ; Register ColReg = ShapeInfo . second . getCol ( ) -> getReg ( ) ; int RowOffset = <NUM_LIT> + TMMIdx ; int ColOffset = <NUM_LIT> + TMMIdx * <NUM_LIT> ; Register SubRowReg = TRI -> getSubReg ( RowReg , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubRowReg ) ; MachineInstrBuilder StoreRow = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addFrameReference ( StoreRow , SS , RowOffset ) . addReg ( SubRowReg ) ; MachineInstrBuilder StoreCol = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addFrameReference ( StoreCol , SS , ColOffset ) . addReg ( ColReg ) ; } ShapeInfos . clear (


<s> requiresVirtualBaseRegisters ( const MachineFunction & MF


<s> int in_struct_p , volatile_p ; if ( GET_CODE ( ref ) != MEM ) return ; in_struct_p = MEM_IN_STRUCT_P ( ref ) ; volatile_p = MEM_VOLATILE_P


<s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; return Concat128BitVectors ( V1 , V2 , ResVT ,


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>1 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getTarget ( ) .


<s> __builtin_ia32_storeapd256_mask ( ( __v4df * ) __P , (


<s> static bool IsDirectBranch ( const MachineInstr &


<s> Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs


<s> Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder & MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) ; AddSubReg ( MIB , DestReg , Indices [ SubReg ] , RegState :: Define , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , <NUM_LIT> , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] ,


<s> return new <ISA_LIT>FastISel ( funcInfo ,


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true


<s> std :: list < fma_node * > * fma_node :: get_children ( ) { return this ->


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI ->


<s> Relocator :: DWord s = ( pUpper16 & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> , u = pUpper16 & <NUM_LIT> , l = pLower16 & <NUM_LIT> , j1 = ( pLower16 & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT>

, j2 = ( pLower16 & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ;


<s> if ( mips_split_p [ symbol_type ] ) { addr = gen_rtx_HIGH ( Pmode , mips_unspec_address ( addr , symbol_type ) ) ; addr = mips_force_temporary ( temp , addr ) ; base = mips_force_temporary ( temp , gen_rtx_PLUS (


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm .


<s> unsigned STReg = getSTReg ( FPRegNo ) ; unsigned OldSlot = getSlot ( FPRegNo ) ; unsigned TopReg = Stack [ StackTop - <NUM_LIT> ] ; Stack [ OldSlot ] = TopReg ; RegMap [ TopReg ] = OldSlot ; RegMap [ FPRegNo ] = ~ <NUM_LIT> ; Stack [ -- StackTop ] =


<s> static MachineInstr * genFusedMultiplyAccNeg ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg , unsigned IdxMulOpd , unsigned MaddOpc , unsigned MnegOpc , const TargetRegisterClass * RC ) { assert ( IdxMulOpd == <NUM_LIT> ) ; Register NewVR = genNeg ( MF , MRI , TII , Root , InsInstrs , InstrIdxForVirtReg , MnegOpc , RC ) ; return genFusedMultiply ( MF , MRI , TII , Root , InsInstrs , IdxMulOpd , MaddOpc

, RC , FMAInstKind :: Accumulator , & NewVR ) ;


<s> unsigned Mask = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i + <NUM_LIT> ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT> ; Mask |= Elt << (


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>_32Target


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; unsigned removed = <NUM_LIT> ; while ( I != REnd && removed < <NUM_LIT> ) { if ( I -> isDebugInstr ( ) ) { ++ I ; continue ; } if ( ! getAnalyzableBrOpc ( I -> getOpcode ( ) ) ) break ; I -> eraseFromParent ( ) ; I = MBB . rbegin ( ) ; ++


<s> return static_cast < MCObjectStreamer &


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregoiv2di_pss (


<s> if ( ! MI ) return NULL ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfoImpl :: commuteInstruction (


<s> return Variant == <ISA_LIT>MCExpr :: VK_AARCH64_None || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_GOT || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC ; } return isLabel < <NUM_LIT> , <NUM_LIT> > (


<s> bool <ISA_LIT>FastISel :: SelectSelect ( const Instruction * I ) { const SelectInst * SI = cast < SelectInst > ( I ) ; EVT DestEVT = TLI . getValueType ( SI -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned CondReg = getRegForValue ( SI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned TrueReg = getRegForValue ( SI -> getTrueValue ( ) ) ; if ( TrueReg == <NUM_LIT> ) return false ; unsigned FalseReg = getRegForValue ( SI -> getFalseValue ( ) ) ; if ( FalseReg == <NUM_LIT> ) return false ; MRI . constrainRegClass ( CondReg , & <STR_LIT> ) ; unsigned ANDReg = createResultReg ( & <STR_LIT>


<s> OutStreamer . SwitchSection ( TheSection ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; typedef <ISA_LIT>COFFMachineModuleInfo :: externals_iterator externals_iterator ; for ( externals_iterator I = COFFMMI . externals_begin ( ) , E = COFFMMI . externals_end ( ) ; I != E ; ++ I ) { OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I

) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_prefetch_i64gather_pd ( __m512i index , __mmask8 mask , void * addr , int scale , int hint ) { __builtin_ia32_gatherpfqpd ( mask , ( __v8di ) index , ( long long const


<s> else return false ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) && ! HONOR_NANS ( compare_mode ) && ! HONOR_SIGNED_ZEROS ( compare_mode ) ) max_p = ! max_p ; else return


<s> return __builtin_aarch64_lceilhfsi (


<s> gcc_assert ( ! last_bytes || part_bytes_reg ) ; if ( BYTES_BIG_ENDIAN && last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> * ( <NUM_LIT> - last_bytes ) ) ) ) ; part_bytes_reg = tmp ; while ( last_bytes ) { mem = adjust_automodify_address ( dstbase , QImode , plus_constant ( Pmode , dst , last_bytes - <NUM_LIT> ) , dstoffset + last_bytes - <NUM_LIT> ) ; emit_move_insn ( mem , gen_lowpart ( QImode , part_bytes_reg ) ) ; if ( -- last_bytes ) { tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> ) ) ) ; part_bytes_reg = tmp ; } } } else { if ( last_bytes > <NUM_LIT> ) { mem = adjust_automodify_address ( dstbase , HImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_lowpart ( HImode , part_bytes_reg ) ) ; last_bytes -= <NUM_LIT> ; if ( last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_addsi3 ( dst , dst , const2_rtx ) ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> ) ) ) ; part_bytes_reg = tmp ; dstoffset += <NUM_LIT> ; } } if ( last_bytes ) { mem = adjust_automodify_address ( dstbase , QImode , dst ,


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cmpord_ss ( __m128 __A , __m128 __B ) { __vector unsigned int a , b ; __vector unsigned int c , d ; static const __vector unsigned int float_exp_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( float_exp_mask ,


<s> for ( auto * I : Tys ) { if ( ! I -> isVectorTy ( ) ) continue ; if ( I -> getScalarSizeInBits ( ) * I -> getVectorNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , <NUM_LIT> , <NUM_LIT> ) + getMemoryOpCost ( Instruction :: Load , I , <NUM_LIT> , <NUM_LIT> ) ; } return


<s> const auto Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; if ( IsMachO ) { if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) || Parser . getTok ( ) . is ( AsmToken :: String ) ) { MCSymbol * Func = getParser ( ) . getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) .


<s> return ( __m512 ) __builtin_ia32_movaps512_mask ( ( __v16sf ) __A , ( __v16sf ) _mm512_setzero_ps ( )


<s> const bool Is64Bit = getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ; unsigned FixupKind = Fixup . getKind ( ) ; if ( IsCrossSection ) { if ( FixupKind == FK_Data_4 || FixupKind == llvm :: <STR_LIT> || ( FixupKind == FK_Data_8 && Is64Bit ) ) { FixupKind = FK_PCRel_4 ; } else { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } } MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( Is64Bit ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_I386_REL32 ; case FK_Data_4 : case <STR_LIT>


<s> int64_t AddrDispShift ; int Dist ; if ( ! chooseBestLEA ( Insns -> second , MI , DefMI , AddrDispShift , Dist ) ) continue ; if ( Dist < <NUM_LIT> ) { DefMI -> removeFromParent ( ) ; MBB -> insert ( MachineBasicBlock :: iterator ( & MI ) , DefMI ) ; InstrPos [ DefMI ] = InstrPos [ & MI ] - <NUM_LIT> ; assert ( ( ( InstrPos [ DefMI ] == <NUM_LIT> && MachineBasicBlock :: iterator ( DefMI ) == MBB -> begin ( ) ) || InstrPos [ DefMI ] > InstrPos [ & * std :: prev ( MachineBasicBlock :: iterator ( DefMI ) ) ] ) && <STR_LIT> ) ; } MRI -> clearKillFlags ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumSubstLEAs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( AddrDispShift ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; Changed =


<s> case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFABS ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN (


<s> void <ISA_LIT>ExpandISEL :: populateBlocks ( BlockISELList & BIL ) { for ( auto & MI : BIL ) { assert ( isISEL ( * MI ) && <STR_LIT> ) ; MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & ConditionRegister = MI -> getOperand ( <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Dest << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueValue << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FalseValue << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ConditionRegister << <STR_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( IsADDIInstRequired ) { BuildMI ( * TrueBlock , TrueBlockI , dl , TII -> get ( isISEL8 ( * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; TrueBlock -> addLiveIn ( TrueValue . getReg ( ) ) ; } if ( IsORIInstRequired ) { FalseBlock -> addLiveIn ( FalseValue . getReg ( ) ) ; } if ( NewSuccessor ) { NewSuccessor -> addLiveIn ( Dest . getReg ( ) ) ; NewSuccessor -> addLiveIn ( TrueValue . getReg ( ) ) ; NewSuccessor -> addLiveIn ( FalseValue . getReg ( ) ) ; NewSuccessor -> addLiveIn ( ConditionRegister . getReg ( ) ) ; } if ( IsORIInstRequired ) BuildMI ( * FalseBlock , FalseBlockI , dl , TII -> get ( isISEL8 ( * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( FalseValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> eraseFromParent


<s> case <STR_LIT> : case <STR_LIT> : return ( int64_t ) Value / <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data

, unsigned DataSize , uint64_t Value , bool IsPCRel ) const {


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Stxr = <STR_LIT> ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT>


<s> SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee ,


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) if ( SDValue V = lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT>


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned add = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( add )


<s> switch ( pst_info . analyze ( type ) ) { case pure_scalable_type_info :: IS_PST : return ( pst_info . num_zr ( ) > NUM_FP_ARG_REGS || pst_info . num_pr ( ) > NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( type


<s> } if ( isVarArg ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) return false ; if ( Subtarget -> isTargetWin64 ( ) ) return false ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = ( ( <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size


<s> VectorType * VTy = cast < VectorType > ( II . getType ( ) ) ; auto * SplatValue = dyn_cast_or_null < ConstantInt > ( getSplatValue ( OpIndices ) ) ; if ( ! SplatValue || SplatValue -> getValue ( ) . uge ( VTy -> getElementCount ( ) . getKnownMinValue ( ) ) ) return None ; IRBuilder < > Builder ( II . getContext ( )


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Res = ExpandBIT_CONVERT ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerShift ( N , DAG , Subtarget ) ; break ; } if ( Res . getNode ( ) ) Results


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetMachO ( ) ) ; Subtarget -> getFrameLowering ( ) -> emitStackProbeCall ( * BB -> getParent ( ) ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> return DAG . getLoad ( getPointerTy ( ) , DL , DAG . getEntryNode ( ) , ThreadPointer , MachinePointerInfo ( )


<s> emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; if ( MACHOPIC_INDIRECT ) funexp = machopic_indirect_call_target ( funexp ) ; insn = emit_call_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_CALL ( VOIDmode , funexp , const0_rtx ) , gen_rtx_USE ( VOIDmode , const0_rtx ) , simple_return_rtx ) ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns


<s> return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ; case E_TImode : return QUAL_TYPE ( TI ) ; case E_OImode : return arm_simd_intOI_type_node ; case E_EImode : return arm_simd_intEI_type_node ; case E_CImode : return arm_simd_intCI_type_node ; case E_XImode : return arm_simd_intXI_type_node ; case E_HFmode : return arm_fp16_type_node ; case E_SFmode : return


<s> rtx sh_extending_set_of_reg :: use_as_unextended_reg ( rtx_insn * use_at_insn ) const { gcc_assert ( can_use_as_unextended_reg ( ) ) ; rtx r = XEXP ( set_src , <NUM_LIT> ) ; rtx r0 = simplify_gen_subreg ( SImode , r , from_mode , <NUM_LIT> ) ; if ( modified_between_p ( r , insn , use_at_insn ) ) { rtx r1 = gen_reg_rtx ( SImode ) ; emit_insn_after ( gen_move_insn ( r1 , r0 ) , insn ) ; return r1 ; } else { sh_remove_reg_dead_or_unused_notes ( insn , SUBREG_P ( r ) ? REGNO ( SUBREG_REG ( r ) ) : REGNO ( r ) ) ; return r0


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case


<s> <ISA_LIT>Operand * ErrorOperand ( SMLoc Loc , StringRef Msg ) { Error ( Loc , Msg


<s> void crx_function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int l = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; if ( ! last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < <NUM_LIT> ) ) return ; if ( mode == SImode || mode == HImode || mode == QImode || mode == DImode ) { if ( l <= <NUM_LIT> ) cum -> ints += <NUM_LIT> ; else cum -> ints += l ; } else if ( mode == SFmode || mode == DFmode ) cum -> ints += l ; else if ( ( mode ) ==


<s> int64_t Imm = ShiftExtend . Amount / <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm


<s> bool isMem512 ( ) const { return Kind == Memory && ( ! Mem . Size


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; MCSymbol * LocalEntryLabel = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: createSub (

LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ;


<s> return m_pParent . elfSegmentTable ( ) . end ( ) == baseSeg ? <NUM_LIT> :


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; Is<ISA_LIT>64 = TheTriple . is<ISA_LIT>64 ( ) ; IsDarwin = TheTriple .


<s> if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ; } return false


<s> if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == nullptr ) return AM . Base . Reg ; Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg


<s> if ( CI -> use_empty ( ) ) return false ; if ( handlePowSpecialCases ( CI , Func , M ) ) return true ; std :: string MASSVEntryName = createMASSVFuncName ( Func , Subtarget ) ; FunctionCallee FCache = M . getOrInsertFunction ( MASSVEntryName , Func . getFunctionType ( ) , Func . getAttributes ( ) ) ; CI -> setCalledFunction (


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( )


<s> MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand &


<s> return ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode (


<s> rtx dst_itr , src_itr ; rtx dstmem_m , srcmem_m , dst_itr_m , src_itr_m ; rtx dst_end ; rtx double_word_mode_loop , byte_mode_loop ; rtx tmp ; int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & <NUM_LIT> ) == <NUM_LIT> ; unsigned HOST_WIDE_INT total_bytes = UINTVAL ( size ) ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return <NUM_LIT> ; if ( TARGET_REDUCED_REGS ) start_regno = <NUM_LIT> ; else start_regno = <NUM_LIT> ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , <NUM_LIT> ) ) ; if ( total_bytes < <NUM_LIT> ) { dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_label ( byte_mode_loop ) ; nds32_emit_post_inc_load_store ( tmp , src_itr , QImode , true ) ; nds32_emit_post_inc_load_store ( tmp , dst_itr , QImode , false ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , NE , NULL , SImode , <NUM_LIT> , byte_mode_loop ) ; return true ; } else if ( total_bytes % <NUM_LIT> == <NUM_LIT> ) { dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_label ( double_word_mode_loop ) ; src_itr_m = src_itr ; dst_itr_m = dst_itr ; srcmem_m = srcmem ; dstmem_m = dstmem ; nds32_emit_mem_move_block ( start_regno , <NUM_LIT> , & dst_itr_m , & dstmem_m , &


<s> if ( ! <ISA_LIT>SelectAddress ( C , AM , false ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg


<s> unsigned getT2AddrModeImm8OffsetOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT>


<s> static bool timode_mem_p ( rtx x ) { return MEM_P ( x ) && ( TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || ! misaligned_operand ( x ,


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2div8hi (


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back (


<s> float64x1x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rdf ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregcidf ( __o , <NUM_LIT> ) } ; return ret


<s> virtual const DataLayout * getDataLayout ( )


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) DisableJumpTables = true ; Subtarget . SetJITMode ( ) ; PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return false


<s> oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask , oldval ) ; else si_op = generator . fn_4 ( memsi , mask , inverted_mask , oldval ) ; emit_insn ( si_op


<s> MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( Subtarget . isABI_O32 ( ) && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Load = DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; InVals . push_back ( Load ) ; OutChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; } } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor (

Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> return __builtin_mve_vrshlq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) ,


<s> const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) && ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { BaseKill = Loc -> killsRegister ( Base ) ; MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg ,


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT>


<s> one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count ==


<s> case <STR_LIT> : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT>


<s> void <ISA_LIT>BaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig . getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MI -> substituteRegister ( Orig . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex (

CPI ) . addImm ( PCLabelId ) . cloneMemRefs ( Orig ) ;


<s> } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT>


<s> } if ( Mld -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = Mld -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT LdVT = Mld -> getMemoryVT ( ) ; SDLoc dl ( Mld ) ; assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getScalarSizeInBits ( ) ; unsigned FromSz = LdVT . getScalarSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask (


<s> unsigned NumElems = SVOp -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; unsigned NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , false , DAG ) ; unsigned OpSrc ; if ( ! NumZeros ) return false ; if ( ! isShuffleMaskConsecutive ( SVOp , <NUM_LIT> , NumElems - NumZeros ,

NumZeros , NumElems , OpSrc ) ) return false ;


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code ,


<s> gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) && REG_P ( reg_3 ) && REG_P ( reg_4 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) || REGNO ( reg_3 ) == REGNO ( reg_4 ) ) return false ; } else { mem_1 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; mem_3 = operands [ <NUM_LIT> ] ; reg_3 = operands [ <NUM_LIT> ] ; mem_4 = operands [ <NUM_LIT> ] ; reg_4 = operands [ <NUM_LIT> ] ; } if ( ! MEM_P ( mem_1 ) || aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) || MEM_VOLATILE_P ( mem_3 ) || MEM_VOLATILE_P ( mem_4 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_3 , & base_3 , & offset_3 ) ; if ( base_3 == NULL_RTX || offset_3 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_4 , & base_4 , & offset_4 ) ; if ( base_4 == NULL_RTX || offset_4 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) || ! rtx_equal_p ( base_2 , base_3 ) || ! rtx_equal_p ( base_3 , base_4 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; offval_3 = INTVAL ( offset_3 ) ; offval_4 = INTVAL ( offset_4 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( ( offval_1 != ( offval_2 + msize ) || offval_1 != ( offval_3 + msize * <NUM_LIT> ) || offval_1 != ( offval_4 + msize * <NUM_LIT> ) ) && ( offval_4 != ( offval_3 + msize ) || offval_4 != ( offval_2 + msize * <NUM_LIT> ) || offval_4 != ( offval_1 + msize * <NUM_LIT> ) ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) || reg_mentioned_p ( reg_2 , mem_2 ) || reg_mentioned_p ( reg_3 , mem_3 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_4 , mem_4 ) ) return false ; } if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , bool Is64Bit , bool IsLittleEndian , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI


<s> const MCRegisterClass * RC_out = ( VectorList . Count == <NUM_LIT> ) ? & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] : & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; unsigned I , E = RC_out -> getNumRegs ( ) ; for ( I = <NUM_LIT> ; I < E ; I ++ ) if ( RC_in -> getRegister ( I ) == VectorList . RegNum ) break ; assert ( I < E && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RC_out -> getRegister


<s> static InstructionContext contextForAttrs ( uint16_t attrMask


<s> cum -> nregs -= int_nregs ; cum -> sse_nregs -= sse_nregs ; cum -> regno += int_nregs ; cum -> sse_regno += sse_nregs ; return int_nregs ; } else { int align = ix86_function_arg_boundary ( mode , type ) / BITS_PER_WORD ; cum -> words = ROUND_UP (


<s> static rtx loongarch_libcall_value ( machine_mode mode , const_rtx fun


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo


<s> static bool CC_<ISA_LIT>32_SVR4_Custom_Dummy ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign

:: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) {


<s> SmallString < <NUM_LIT> > ImmStrVal ; Imm . toString ( ImmStrVal ) ; if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; else if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; if (


getBuildVector ( <STR_LIT> , DL , VPermMask ) ) ;


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT>


<s> CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case CortexA35 : break ; case CortexA53 : PrefFunctionAlignment = <NUM_LIT> ; break ; case CortexA55 : break ; case CortexA72 : case CortexA73 : case


<s> unsigned Shift = ( NumOperands == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < NumOperands ; ++ i ) { int Val = SVOp -> getMaskElt ( NumOperands - i - <NUM_LIT> ) ; if ( Val < <NUM_LIT> ) Val = <NUM_LIT> ; if ( Val >= NumOperands ) Val -= NumOperands ; Mask |= Val ; if ( i != NumOperands - <NUM_LIT>


<s> static inline bool mode_supports_pre_modify_p ( machine_mode


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair


<s> auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) { Gathers . push_back ( II ) ; if ( isa < GetElementPtrInst > ( II -> getArgOperand ( <NUM_LIT> ) ) ) optimiseOffsets ( cast < Instruction > ( II -> getArgOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) { Scatters . push_back ( II ) ; if ( isa < GetElementPtrInst > ( II -> getArgOperand ( <NUM_LIT> ) ) ) optimiseOffsets ( cast < Instruction > ( II -> getArgOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) , II -> getParent ( ) , LI ) ; } } } bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = <NUM_LIT> ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return


<s> return ( ( __v4si ) __X ) [ __N & <NUM_LIT>


<s> SDValue CarryOp1 = Carry . getOperand ( <NUM_LIT> ) ; if ( CarryCC == <STR_LIT> ) return CarryOp1 ; if ( CarryCC == <STR_LIT> ) { if ( CarryOp1 . getOpcode ( ) == <STR_LIT> && CarryOp1 . getNode ( ) -> hasOneUse ( ) && CarryOp1 . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( CarryOp1 . getOperand ( <NUM_LIT> ) ) ) { SDValue SubCommute = DAG . getNode ( <STR_LIT> , SDLoc ( CarryOp1 ) , CarryOp1 -> getVTList ( ) , CarryOp1 . getOperand ( <NUM_LIT> )

, CarryOp1 . getOperand ( <NUM_LIT> ) ) ;


<s> } assert ( ! ( ( Undef1 || Zero1 ) && ( Undef2 || Zero2 ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createUnpackShuffleMask ( VT , Unpckl , true , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } createUnpackShuffleMask ( VT , Unpckh , false , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } if ( IsUnary && ( Zero1 || Zero2 ) ) { if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; V1 = Zero1 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; return true ; } } if ( ! IsUnary ) { ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; std :: swap ( V1 , V2 ) ; return true ; } ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT>


<s> if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; -- I


<s> MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ; SDValue V ; if ( Subtarget . hasDQI ( ) ) { V = getExtendInVec ( <STR_LIT> , dl , ExtVT , In , DAG ) ; assert ( ! VT . is512BitVector ( ) && <STR_LIT> ) ; } else { SDValue NegOne = getOnesVector ( ExtVT , DAG , dl ) ; SDValue Zero = getZeroVector ( ExtVT , Subtarget , DAG , dl ) ; V = DAG . getNode ( <STR_LIT> , dl , ExtVT , In , NegOne , Zero ) ; if ( ExtVT == VT ) return V ; } return DAG . getNode ( <STR_LIT> ,


<s> dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return <NUM_LIT> ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF )


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return


<s> rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , fun


<s> code = * dp ++ ; decoder = unw_decode_table [ inside_body ] [ code >> <NUM_LIT> ] ; dp = ( * decoder ) ( dp , code , arg ) ; return dp


<s> force = is_costly_group ( group_insns , next_insn ) ; if ( ! force ) return can_issue_more ; if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , * group_count , can_issue_more ) ; if ( rs6000_sched_insert_nops == sched_finish_regroup_exact ) { if ( * group_end ) can_issue_more = <NUM_LIT> ; if ( can_issue_more && ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } * group_end = true ; return <NUM_LIT> ; } if ( rs6000_sched_insert_nops < sched_finish_regroup_exact ) { int n_nops = rs6000_sched_insert_nops ; if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn


<s> static DecodeStatus decodePCDBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) * <NUM_LIT> + Address ) ) ; return MCDisassembler ::


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ;


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv2di ( (


<s> encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; break ; case LO_SUM : * patternp ++ = 'L' ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; break ; case HIGH : * patternp ++ = 'H' ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; break ; case SYMBOL_REF : * patternp ++ = 's' ; break ; case LABEL_REF : * patternp ++ = 'l' ; break ; case CONST_INT : case CONST_DOUBLE : * patternp ++ = 'i' ; break ; case UNSPEC


<s> bool llvm :: lower<ISA_LIT>MachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , AsmPrinter & AP ) { OutMI . setOpcode ( MI


<s> return ( __m512i ) __builtin_ia32_pmovsxbd512_mask ( ( __v16qi ) __A , ( __v16si ) _mm512_undefined_epi32 ( )


<s> Op = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } } if ( Op . getOpcode ( ) == <STR_LIT> && onlyZeroFlagUsed ( SDValue ( N , <NUM_LIT> ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) >= <NUM_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SrcVT ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( <NUM_LIT> , dl , SrcVT ) ) ; } if ( Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Trunc = Op ; Op = Op . getOperand ( <NUM_LIT> ) ; EVT OpVT = Op . getValueType ( ) ; APInt UpperBits = APInt :: getBitsSetFrom ( OpVT . getSizeInBits ( ) , VT . getSizeInBits ( ) ) ; if ( OpVT == <STR_LIT> && DAG . MaskedValueIsZero ( Op , UpperBits ) && onlyZeroFlagUsed ( SDValue ( N , <NUM_LIT> ) ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , OpVT ) ) ; } if ( ! Trunc . hasOneUse ( ) || ! Op . hasOneUse ( ) ) return SDValue ( ) ; unsigned NewOpc ; switch ( Op . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( needCarryOrOverflowFlag ( SDValue ( N , <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( needCarryOrOverflowFlag ( SDValue ( N , <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; } SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , VT


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return std :: make_unique < <ISA_LIT>ELFObjectWriter


<s> if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: <ISA_LIT>_FastCall ) ; F -> addAttribute ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ; } return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; bool isFloat = ( Ty -> isDoubleTy ( ) || Ty -> isFloatTy ( ) ) ; if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned CmpOpc ; unsigned CondReg ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; CondReg = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; CondReg = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; CondReg = <STR_LIT> ; break ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> )


<s> <ISA_LIT>CCState ( CallingConv :: ID CC , bool isVarArg , MachineFunction & MF , const TargetMachine & TM , SmallVector < CCValAssign , <NUM_LIT> > & locs , LLVMContext & C , ParmContext PC ) : CCState ( CC , isVarArg , MF , TM , locs , C ) { assert ( ( ( PC == Call ) || ( PC == Prologue ) ) && <STR_LIT> <STR_LIT> ) ; CallOrPrologue =


<s> unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( isThumb || isThumb2 ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolMBB :: Create ( F -> getContext ( ) , DispatchBB , PCLabelId , PCAdj ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI ->


<s> if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = MF . getFunction ( ) ; const auto & DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; ArgInfo OrigRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL ,


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL


<s> for ( auto * Ld0 : Loads ) { for ( auto * Ld1 : Loads ) { if ( Ld0 == Ld1 ) continue ; if ( AreSequentialAccesses < LoadInst > ( Ld0 , Ld1 , * DL , * SE ) ) { LoadPairs [ Ld0 ] = Ld1 ; if ( BaseLoads . count ( Ld0 ) ) { LoadInst * Base = BaseLoads [ Ld0 ] ; BaseLoads [ Ld1 ] = Base ; SequentialLoads [ Base ] . push_back ( Ld1 ) ; } else { BaseLoads [ Ld1 ] = Ld0 ; SequentialLoads [ Ld0 ] . push_back ( Ld1 ) ; } } } } return LoadPairs . size ( ) >


<s> case <STR_LIT> : return isThumb1 ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : return isThumb1 ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned CPI = getCombinedIndex (


<s> const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .


<s> IterationCountDCE ( LoLoop ) ; MachineBasicBlock :: iterator InsertPt = LoLoop . StartInsertPt ; MachineInstr * Start = LoLoop . Start ; MachineBasicBlock * MBB = LoLoop . StartInsertBB ; unsigned Opc = LoLoop . getStartOpcode ( ) ; MachineOperand & Count = LoLoop . getLoopStartOperand ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , Start -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT>


<s> unsigned VaListSize = ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetWindows ( ) ) ? PtrSize : <NUM_LIT> ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand


<s> MCSection * <ISA_LIT>TargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( IsConstantInSmallSection ( DL , C , * TM )


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved <


<s> return ( __m128i ) __builtin_ia32_vcvtph2dq128_mask ( __C , (


<s> ShuffleVectorSDNode :: commuteMask ( CommutedMask ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SmallVector < int , <NUM_LIT> > UnpackMask ; createUnpackShuffleMask ( VT , UnpackMask , ( i >> <NUM_LIT> ) % <NUM_LIT> , i % <NUM_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , UnpackMask ) ||

isTargetShuffleEquivalent ( CommutedMask , UnpackMask ) ) return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : writebackLoad = true ; writebackReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } if ( CountPopulation_32 ( Val ) == <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Val & ( <NUM_LIT> << i ) ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , i , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( writebackLoad && writebackReg == Inst . end ( ) [ - <NUM_LIT> ] . getReg ( ) ) Check


<s> IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo & MFI = Fn -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( Fn -> getDataLayout ( ) , & MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) , RegDU , * IM , Slot , Filler ) ) return false ; insertDelayFiller ( Filler


<s> } if ( STI . hasLoadStoreOnCond2 ( ) ) { if ( unsigned CondOpcode = getConditionalLoadImmediate ( Opcode ) ) { MI . setDesc ( get ( CondOpcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } } if ( Opcode == <STR_LIT> ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { MachineOperand FirstOp = MI . getOperand ( <NUM_LIT> ) ; const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addOperand ( FirstOp ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get (


<s> unsigned <ISA_LIT>TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const { return ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT> )


<s> assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SignBits [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; bool IsPositive [ <NUM_LIT> ] = { false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue Opd = N -> getOperand ( i ) ; SignBits [ i ] = DAG . ComputeNumSignBits ( Opd ) ; IsPositive [ i ] = DAG . SignBitIsZero ( Opd ) ; } bool AllPositive = IsPositive [ <NUM_LIT> ]


<s> } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> ) ; } Stubs . clear


<s> switch ( CC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static void pru_set_current_function ( tree fndecl ) { tree old_tree = ( pru_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( pru_previous_fndecl ) : NULL_TREE ) ; tree new_tree = ( fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) : NULL_TREE ) ; if ( fndecl && fndecl != pru_previous_fndecl ) { pru_previous_fndecl = fndecl ; if ( old_tree == new_tree


<s> if ( isFrameSetup ( I ) ) I . getOperand ( <NUM_LIT> ) . setImm (


<s> bool hasAndNotCompare ( SDValue ) const override { return


<s> memset ( sc -> rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; sc -> first_instruction = <NUM_LIT> ; sc -> pending_data_specs = <NUM_LIT> ; sc -> current_cycle = <NUM_LIT> ; memset ( sc -> mem_ops_in_group , <NUM_LIT> , sizeof ( mem_ops_in_group ) ) ; } else { memcpy ( sc -> prev_cycle_state , prev_cycle_state , dfa_state_size ) ; sc -> last_scheduled_insn = last_scheduled_insn ; memcpy ( sc -> rws_sum , rws_sum , sizeof ( rws_sum ) ) ; memcpy ( sc -> rws_insn , rws_insn , sizeof ( rws_insn ) ) ; sc -> first_instruction =


<s> bool writeNopData ( uint64_t Count , MCObjectWriter


<s> __vector unsigned int c , d ; static const __vector unsigned int float_exp_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B


<s> int64_t Val = MCE -> getValue ( ) ; if ( Val & <NUM_LIT> ) return false ; return ( Val >= - ( <NUM_LIT> << <NUM_LIT> ) && Val <=


<s> <ISA_LIT>ABIInfo ABI = <ISA_LIT>ABIInfo :: computeTargetABI ( STI . getTargetTriple ( ) , STI . getCPU ( ) , Options ) ; return new <ISA_LIT>AsmBackend ( T , MRI , STI . getTargetTriple ( ) , STI .


crtl -> preferred_stack_boundary = <NUM_LIT> ;


<s> assert ( DestVT . getSizeInBits ( ) > <NUM_LIT> && <STR_LIT> ) ; if ( SrcVT . getSizeInBits ( ) * <NUM_LIT> != DestVT . getSizeInBits ( ) && SrcVT . getSizeInBits ( ) * <NUM_LIT> != DestVT . getSizeInBits ( ) ) return SDValue ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned DestEltSize = DestVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; SDValue Mid , SplitLo , SplitHi , ExtLo , ExtHi ; EVT MidVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts ) ; EVT SplitVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts / <NUM_LIT> ) ; EVT ExtVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , DestEltSize ) , NumElts / <NUM_LIT> ) ; Mid = DAG . getNode ( N -> getOpcode ( ) , dl , MidVT , Op ) ; SplitLo = DAG . getNode ( <STR_LIT> , dl , SplitVT , Mid , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SplitHi = DAG . getNode ( <STR_LIT> , dl , SplitVT , Mid , DAG . getIntPtrConstant ( NumElts / <NUM_LIT> ) ) ; ExtLo = DAG . getNode ( N -> getOpcode ( ) , dl , ExtVT , SplitLo ) ; ExtHi = DAG . getNode ( N -> getOpcode ( ) , dl , ExtVT , SplitHi ) ; return DAG . getNode ( <STR_LIT> , dl


<s> void <ISA_LIT>AsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , const char * Modifier ) { if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { printOperand ( MI , opNum + <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , opNum ) ; return ; } printOperand ( MI , opNum ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> ) ; O <<


<s> MachineIRBuilder B ( MI ) ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; GISelObserverWrapper WrapperObserver ( & NewInstrObserver ) ; LegalizerHelper Helper ( * MF , WrapperObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : { Helper . narrowScalar ( MI , <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) { SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineMerges ( * NewMI , DeadInstrs ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ; } else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else for ( auto Op : NewMI -> operands ( ) ) { if ( Op . isReg ( ) ) { assert ( MRI . getType ( Op . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MRI . setRegBank ( Op . getReg ( ) , getRegBank ( <STR_LIT> ) ) ; } } } return ; } case TargetOpcode :: G_UNMERGE_VALUES : { SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineMerges ( MI , DeadInstrs ) ; for ( MachineInstr * DeadMI : DeadInstrs )


<s> return ( __m64 ) __builtin_ia32_pavgb ( ( __v8qi ) __A , ( __v8qi )


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg (

MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const { return


<s> if ( ! DisableInstrFormPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopInstrFormPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None

) addPass ( createHardwareLoopsPass ( ) ) ;


<s> static tree ia64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= IA64_BUILTIN_max ) return error_mark_node ; return ia64_builtins [ code ]


<s> EVT SVT = In . getValueType ( ) ; if ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) return SDValue ( ) ; assert ( Subtarget -> hasFp256 ( ) && <STR_LIT> ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT>


<s> <ISA_LIT>ATTAsmParser ( const Target & T , MCAsmParser & parser , TargetMachine & TM ) : TargetAsmParser ( T ) , Parser ( parser ) , TM ( TM ) { setAvailableFeatures ( ComputeAvailableFeatures ( & TM . getSubtarget <


<s> for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg


<s> FunctionPass * llvm :: createThumb2ITBlockPass ( ) { return new Thumb2ITBlockPass (


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . add ( MO ) ; } MIB . addReg ( DstReg , RegState ::

ImplicitDefine | getDeadRegState ( DstIsDead ) ) ;


<s> return false ; } if ( Option == <STR_LIT> ) { IsPicEnabled = true ; getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false ; } Warning ( Parser . getTok ( )


<s> for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) MIB . addOperand ( I


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr


<s> second_call = <NUM_LIT> ; call = mips_call_expr_from_insn ( insn , & second_call ) ; if ( ! call ) continue ; gcc_assert ( MEM_P ( XEXP ( call , <NUM_LIT> ) ) ) ; reg = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ! REG_P ( reg ) ) continue ; symbol = mips_find_pic_call_symbol ( insn , reg , true ) ; if ( symbol ) { mips_annotate_pic_call_expr ( call


<s> if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> )


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) for ( std :: map < const char * , const <STR_LIT> * > :: const_iterator it = <ISA_LIT>FI -> StubsNeeded . begin ( ) ; it != <ISA_LIT>FI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const <STR_LIT> * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; emitXRayTable (


<s> if ( kind == vector_stmt && aarch64_extending_load_p ( stmt_info ) ) stmt_cost = <NUM_LIT> ; if ( kind == vector_stmt && aarch64_integer_truncation_p ( stmt_info ) ) stmt_cost = <NUM_LIT> ; if ( STMT_VINFO_GROUPED_ACCESS ( stmt_info ) ) { stmt_vec_info first = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; unsigned int count = DR_GROUP_SIZE ( first ) - DR_GROUP_GAP ( first ) ; unsigned int elt_bits = GET_MODE_UNIT_BITSIZE ( TYPE_MODE ( vectype ) ) ; if ( multiple_p ( count * elt_bits , <NUM_LIT> ) && aarch64_advsimd_ldp_stp_p ( kind , stmt_info )


<s> if ( SupportedVectorShiftWithBaseAmnt ( ExtVT , Subtarget , Opcode ) ) { unsigned LogicalOp = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned Logical<ISA_LIT>Op = getTargetVShiftUniformOpcode ( LogicalOp , false ) ; BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; SDValue BitMask = DAG . getConstant ( - <NUM_LIT> , dl , ExtVT ) ; BitMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , BaseShAmt , Subtarget , DAG ) ; if ( Opcode != <STR_LIT> ) BitMask = getTargetVShiftByConstNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , <NUM_LIT> , DAG ) ; BitMask = DAG . getBitcast ( VT , BitMask ) ; BitMask = DAG . getVectorShuffle ( VT , dl , BitMask , BitMask , SmallVector < int , <NUM_LIT> > ( NumElts , <NUM_LIT> ) ) ; SDValue Res = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , DAG . getBitcast ( ExtVT , R ) , BaseShAmt , Subtarget , DAG ) ; Res = DAG . getBitcast ( VT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , BitMask ) ; if ( Opcode == <STR_LIT> ) { SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , ExtVT ) ; SignMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , SignMask , BaseShAmt , Subtarget , DAG ) ; SignMask = DAG . getBitcast ( VT , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; } return


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> tmp = hard_frame_pointer_rtx ; offset = - offset ; } else { tmp = stack_pointer_rtx ; offset = current_frame_info . total_size - offset ; } offset_r = GEN_INT ( offset ) ; if ( satisfies_constraint_I ( offset_r ) ) emit_insn ( gen_adddi3 ( pic_offset_table_rtx , tmp , offset_r ) ) ; else { emit_move_insn ( pic_offset_table_rtx , offset_r ) ; emit_insn ( gen_adddi3 ( pic_offset_table_rtx , pic_offset_table_rtx , tmp ) ) ; } tmp = gen_rtx_MEM ( DImode , pic_offset_table_rtx ) ; } emit_move_insn ( pic_offset_table_rtx , tmp


<s> case <STR_LIT> : { ResultPtr += MR -> getConstantVal ( ) ; if ( MR -> getRelocationType ( ) == <STR_LIT> ) { if ( ( ( int ) ResultPtr << <NUM_LIT> ) < <NUM_LIT> ) ResultPtr += <NUM_LIT> << <NUM_LIT> ; ResultPtr >>= <NUM_LIT> ; } unsigned LowBits = ( * RelocPos + ResultPtr ) & <NUM_LIT> ; unsigned HighBits = * RelocPos & ~ <NUM_LIT> ; * RelocPos = LowBits | HighBits ; break ; } case <STR_LIT> : { ResultPtr += MR -> getConstantVal ( ) ; unsigned LowBits = ( * RelocPos + ResultPtr ) & <NUM_LIT> ; unsigned HighBits = * RelocPos &


<s> unsigned SuperReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && SrcReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; DestReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_SVCR , Ctx ) ; Op -> SVCR . PStateField = PStateField ; Op -> SVCR . Data =


<s> SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( isConstantSplat ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt

, DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ;


<s> <ISA_LIT>ToTHMStub :: <ISA_LIT>ToTHMStub ( const uint32_t * pData , size_t pSize , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) :

m_pData ( pData ) , m_Name ( <STR_LIT> ) , m_Size ( pSize ) {


<s> MVT VecVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; unsigned NumElemsPerChunk = vecWidth / VecVT . getScalarSizeInBits ( ) ; return Index /


<s> const MCExpr * getImm ( ) const { assert ( Kind == Immediate &&


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ObjectWriter ( uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ObjectWriter


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , IsO32 , Subtarget -> isFP64bit ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL


<s> else for ( int i = <NUM_LIT> ; i <= SaveElts ; i ++ ) ShuffV [ i * Stride - <NUM_LIT> ] = i - <NUM_LIT> ; SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) : DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ; SDValue Arrange = DAG . getVectorShuffle ( WideVT , dl , Wide , ShuffleSrc2 , ShuffV ) ; unsigned ExtendOp = SignedConv ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue Extend ; if ( ! Subtarget . hasP9Altivec ( ) && SignedConv ) { Arrange = DAG . getBitcast ( IntermediateVT , Arrange ) ; Extend = DAG . getNode ( <STR_LIT> , dl , IntermediateVT , Arrange , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) ; } else Extend = DAG . getNode ( ExtendOp


<s> } else { MVT ImmVT = <STR_LIT> ( std :: max ( ( unsigned ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; SDValue Select = DAG . getSelect ( dl , ImmVT , Cond , DAG . getAllOnesConstant ( dl , ImmVT ) , DAG . getConstant ( <NUM_LIT> , dl , ImmVT ) ) ; MVT VecVT = VT . getSizeInBits ( ) >= <NUM_LIT> ? VT : <STR_LIT> ; Select = DAG . getBitcast ( VecVT , Select ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Select , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } } SDValue DstVec ; if ( HasConstElts ) { if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue ImmL = DAG . getConstant ( Lo_32 ( Immediate ) , dl , <STR_LIT> ) ; SDValue ImmH = DAG . getConstant ( Hi_32 ( Immediate ) , dl , <STR_LIT> ) ; ImmL = DAG . getBitcast ( <STR_LIT> , ImmL ) ; ImmH = DAG . getBitcast ( <STR_LIT> , ImmH ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ImmL , ImmH ) ; } else { MVT ImmVT = <STR_LIT> ( std :: max ( ( unsigned ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; SDValue Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; MVT VecVT = VT . getSizeInBits ( ) >= <NUM_LIT> ? VT : <STR_LIT> ; DstVec = DAG . getBitcast ( VecVT , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , DstVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } } else DstVec = DAG .


<s> static MCDisassembler * createThumbDisassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new ThumbDisassembler ( STI


<s> return ; } } StringRef BaseRegStr ; StringRef IndexRegStr ; if ( SM . getBaseReg ( ) ) BaseRegStr = <ISA_LIT>IntelInstPrinter :: getRegisterName ( SM . getBaseReg ( ) ) ; if ( SM . getIndexReg ( ) ) IndexRegStr = <ISA_LIT>IntelInstPrinter :: getRegisterName ( SM . getIndexReg ( ) ) ; IntelExpr Expr ( BaseRegStr , IndexRegStr , SM . getScale ( ) , SM . getImm ( ) , SM . isMemExpr


<s> } case SH_SUBREG : adjust_subreg_index ( body ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , i ) ; break ; case SH_NOSWAP_LD : permute_load ( insn ) ; break ; case SH_NOSWAP_ST : permute_store ( insn ) ; break ; case SH_EXTRACT : adjust_extract ( insn ) ; break ; case


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler


<s> NewPNodes [ OldPN ] = NewPN ; } for ( auto * OldPN : OldPhiNodes ) { PHINode * NewPN = NewPNodes [ OldPN ] ; for ( unsigned j = <NUM_LIT> , e = OldPN -> getNumOperands ( ) ; j != e ; ++ j ) { Value * V = OldPN -> getOperand ( j ) ; Value * NewV = nullptr ; Instruction * ACI = dyn_cast < Instruction > ( V ) ; if ( ACI && isAMXCast ( ACI ) ) NewV = ACI -> getOperand ( <NUM_LIT> ) ; else if ( auto * PrevPN = dyn_cast < PHINode > ( V ) ) NewV = NewPNodes [ PrevPN ] ; assert ( NewV ) ; NewPN -> addIncoming ( NewV , OldPN -> getIncomingBlock ( j ) ) ; } } for ( auto * OldPN : OldPhiNodes ) { PHINode * NewPN = NewPNodes [ OldPN ] ; for ( User * V : make_early_inc_range ( OldPN -> users ( ) ) ) { Instruction * ACI = dyn_cast < Instruction > ( V ) ; if ( ACI && isAMXCast ( ACI ) ) { Type * TyB = ACI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; Type * TyA = ACI -> getType ( ) ; assert ( TyA == DestTy && TyB == SrcTy ) ; ( void ) TyA ; ( void ) TyB ; ACI -> replaceAllUsesWith ( NewPN ) ; DeadInst . insert


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr