<s> GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , Name ) ; EVT LCREVT = TLI . getValueType ( GV -> getType ( ) ) ; if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; return <ISA_LIT>MaterializeGV ( GV , LCREVT . getSimpleVT (


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return *


<s> return ( __m128i ) __builtin_ia32_pminsd128 ( ( __v4si )


<s> for ( auto Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) Mask [ Reg / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( Reg


<s> bool NamedImmMapper :: validImm ( uint32_t


<s> rtx insn ; gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; if ( global_tlsarg ) tlsarg = global_tlsarg ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( <NUM_LIT> , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode


<s> rtx sh_load_function_descriptor ( rtx funcdesc ) { rtx r1 = gen_rtx_REG ( Pmode , R1_REG ) ; rtx pic_reg = gen_rtx_REG ( Pmode , PIC_REG ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ; rtx gotaddr = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , funcdesc , <NUM_LIT> ) ) ; emit_move_insn ( r1 , fnaddr ) ; emit_insn ( gen_blockage ( ) ) ; emit_move_insn ( pic_reg , gotaddr


<s> SmallPtrSet < BasicBlock * , <NUM_LIT> > ExceptBlocks ; for ( BasicBlock & BB : F ) { for ( auto I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ++ I ) { if ( auto * CI = dyn_cast < CallInst > ( I ) ) { auto * Intrin = dyn_cast < IntrinsicInst > ( CI ) ; if ( Intrin ) { continue ; } insertStateNumberStore ( RegNode , CI , - <NUM_LIT> ) ; } else if ( auto * II = dyn_cast < InvokeInst > ( I ) ) { LandingPadInst * LPI = II -> getUnwindDest ( ) -> getLandingPadInst ( ) ; auto InsertionPair = FuncInfo . LandingPadStateMap . insert ( std :: make_pair ( LPI , CurState ) ) ; auto Iter = InsertionPair . first ; int & State = Iter -> second ; bool Inserted = InsertionPair . second ; if ( Inserted ) { auto * EHActions = cast < IntrinsicInst > ( LPI -> getNextNode ( ) ) ; SmallVector < std :: unique_ptr < ActionHandler > , <NUM_LIT> > ActionList ; parseEHActions ( EHActions , ActionList ) ; assert ( ! ActionList . empty ( ) ) ; CurState += ActionList . size ( ) ; State += ActionList . size ( ) - <NUM_LIT> ; for ( auto & Handler : ActionList ) { if ( auto * CH = dyn_cast < CatchHandler > ( Handler . get ( ) ) ) { auto * BA = cast < BlockAddress > ( CH -> getHandlerBlockOrFunc ( ) ) ; for ( BasicBlock * Pred : predecessors ( BA -> getBasicBlock ( ) ) ) assert ( Pred -> isLandingPad ( ) && <STR_LIT> ) ; ExceptBlocks . insert ( BA -> getBasicBlock ( ) ) ; } } } insertStateNumberStore ( RegNode , II , State ) ; } } } Function * RestoreFrame = <STR_LIT> ( TheModule , <STR_LIT> ) ; for ( BasicBlock * ExceptBB : ExceptBlocks


<s> static rtx sh_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , BASE_RETURN_VALUE_REG ( mode )


<s> for ( const char * Name = V -> getNameStart ( ) , * E = Name + V -> getNameLen ( ) ; Name != E ; ++ Name ) if ( isprint


<s> const MachineOperand & Op1 = MI1 . getOperand ( N1 + <STR_LIT> ) ; const MachineOperand & Op2 = MI2 . getOperand ( N2 + <STR_LIT> ) ; assert ( isSimilarDispOp ( Op1 , Op2 ) && <STR_LIT> ) ; if ( Op1 . isJTI ( )


<s> if ( IsMachO ) { if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) || Parser . getTok ( ) . is ( AsmToken :: String ) ) { MCSymbol * Func = getParser ( ) . getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . emitThumbFunc ( Func ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) )


<s> return new <ISA_LIT>OptimizeLEAPass (


<s> MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; } unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit


<s> TargetSupported = ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && ( ( Subtarget -> has<ISA_LIT>32r2 ( ) || Subtarget -> has<ISA_LIT>32 ( ) ) && ( static_cast < const <ISA_LIT>TargetMachine


<s> if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base_Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> ) { AM . IndexReg = N ; AM . Scale =


<s> Register CalleeReg = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachineInstr * CalleeGlobalValue = MIRBuilder . buildGlobalValue ( CalleeReg , Callee . getGlobal ( ) ) ; if ( ! Callee . getGlobal ( ) -> hasLocalLinkage ( ) ) CalleeGlobalValue -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; MIB . addUse ( CalleeReg ) ; } else MIB . add ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , <NUM_LIT> ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm (


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI

-> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> static unsigned aarch64_next_callee_save ( unsigned regno , unsigned limit ) { while ( regno <= limit && ! aarch64_register_saved_on_entry ( regno ) ) regno ++ ; return


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> static bool DisassembleLdStMiscFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , bool isStore , BO B ) { const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; bool isPrePost = isPrePostLdSt ( TID . TSFlags ) ; const TargetOperandInfo * OpInfo = TID . OpInfo ; if ( ! OpInfo ) return false ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( ( ( ! isStore && TID . getNumDefs ( ) > <NUM_LIT> ) || ( isStore && ( TID . getNumDefs ( ) == <NUM_LIT> || isPrePost ) ) ) && <STR_LIT> ) ; if ( isPrePost && isStore ) { assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } bool DualReg = HasDualReg ( Opcode ) ; if ( OpIdx >= NumOps ) return false ; assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; if ( DualReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) + <NUM_LIT> ) ) ) ; ++ OpIdx ; } if ( isPrePost && ! isStore ) { assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn )


<s> AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasV8Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV7Ops ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasV6T2Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV6Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TEOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV4TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasNEON ( ) && emitFPU ) { if ( Subtarget -> hasVFP4 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasVFP4 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP2 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <NUM_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <NUM_LIT> )


<s> rtx addr = plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * num_regs ) ; rtx tmp = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , addr ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , tmp ) , UNSPEC_PUSHPOP_MULT ) ) ; break ; } for ( j = <NUM_LIT> , i ++ ; j < ( num_regs + <NUM_LIT> ) ; i


<s> return MatchOperand_ParseFail ; } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , DB ? DB -> Name : <STR_LIT> , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( Tok . getString ( ) ) ; if ( Mnemonic == <STR_LIT> && ( ! DB || DB -> Encoding != <STR_LIT> ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ! DB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , Tok . getString ( ) ,


<s> if ( AssemblerOptions . back ( ) -> isReorder ( ) ) Warning ( Loc , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Reg ; OperandMatchResultTy ResTy = parseAnyRegister ( Reg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT>


<s> return __builtin_aarch64_urshlv2di_uus ( __a ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; TII = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock ( MBB


<s> void <ISA_LIT>InstrInfo :: expandLOCPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned


<s> if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> assert ( Kind == k_InstSyncBarrierOpt && <STR_LIT> ) ; return ISBOpt


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op .


<s> if ( ! isa < FPMathOperator > ( CI ) )


<s> static SDValue performBitcastCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> && ! ( Op0 -> isMachineOpcode ( ) && Op0 -> getMachineOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; uint64_t idx = cast < ConstantSDNode > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { if ( Op0 -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != idx && idx != <NUM_LIT> ) return SDValue ( ) ; } else if ( Op0 -> getMachineOpcode ( ) == <STR_LIT> ) { if ( idx != <STR_LIT> ) return SDValue ( ) ; idx = <NUM_LIT> ; } if ( Op0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Source = Op0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; EVT SVT = Source -> getValueType ( <NUM_LIT> ) ; if ( ! SVT . isVector ( ) || SVT . getVectorNumElements ( ) != VT . getVectorNumElements ( )


<s> if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; unsigned NumPackedBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; KnownBits Known ; DAG . computeKnownBits ( In , Known ) ; unsigned NumLeadingZeroBits = Known .


<s> return MF . getFrameInfo ( ) . hasVarSizedObjects


<s> MCObjectWriter * llvm :: create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit ) { MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit ) ; return createWinCOFFObjectWriter ( MOTW ,


<s> unsigned NumReusableBytes = FuncInfo -> getBytesInStackArgArea ( ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , F . getContext ( ) ) ; analyzeArgInfo ( OutInfo , OutArgs , * AssignFnFixed , * AssignFnVarArg ) ; NumBytes = alignTo ( OutInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; FPDiff = NumReusableBytes - NumBytes ; assert ( FPDiff % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; } const auto & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , true , FPDiff ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; if ( Info . IsVarArg && Info . IsMustTailCall ) { for ( const auto & F : Forwards ) { Register ForwardedReg = F . PReg ; if ( any_of ( MIB -> uses ( ) , [ & ForwardedReg , & TRI ] ( const MachineOperand & Use ) { if ( ! Use . isReg ( ) ) return false ; return TRI -> regsOverlap ( Use . getReg ( ) , ForwardedReg ) ; } ) ) continue ; MIRBuilder . buildCopy ( ForwardedReg , Register ( F . VReg ) ) ; MIB . addReg ( ForwardedReg , RegState :: Implicit ) ; } } if ( ! IsSibCall ) { MIB -> getOperand ( <NUM_LIT> ) . setImm ( FPDiff ) ; CallSeqStart . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget

( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ;


<s> BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; const uint32_t * RegMask = getTargetMachine ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } if ( ! Is64Bit ) BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( TargetOpcode :: COPY ) , mallocPtrVReg ) . addReg ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; BB -> addSuccessor ( bumpMBB ) ; BB -> addSuccessor ( mallocMBB ) ; mallocMBB -> addSuccessor ( continueMBB ) ; bumpMBB -> addSuccessor ( continueMBB ) ; BuildMI ( * continueMBB , continueMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) )

. addReg ( mallocPtrVReg ) . addMBB ( mallocMBB ) . addReg ( bumpSPPtrVReg ) . addMBB ( bumpMBB ) ;


<s> } if ( SrcVT . bitsLT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 ) ; else if ( SrcVT . bitsGT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; EVT VecVT ; uint64_t EltMask ; SDValue VecVal1 , VecVal2 ; auto setVecVal = [ & ] ( int Idx ) { if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT


<s> <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; } else { I . RemoveOperand ( <NUM_LIT> ) ; I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) . addUse ( DefReg ) ; } return constrainSelectedInstRegOperands ( I , TII


_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void load_got_register ( void ) { if ( ! got_register_rtx ) got_register_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( TARGET_VXWORKS_RTP ) emit_insn ( gen_vxworks_load_got ( ) ) ; else { if ( ! got_helper_rtx ) { char name [ <NUM_LIT> ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name


<s> return ( uint32x4_t ) __builtin_neon_vsubluv4hi ( ( int16x4_t ) __a ,


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName


<s> return ( uint16x8_t ) __builtin_aarch64_usubwv8qi ( ( int16x8_t )


<s> return IN_RANGE ( val , ( - <NUM_LIT> << ( rx_max_constant_size * <NUM_LIT> ) )

, ( <NUM_LIT> << ( rx_max_constant_size * <NUM_LIT> ) ) ) ;


<s> switch ( DECL_MD_FUNCTION_CODE ( fndecl ) ) { case RS6000_BIF_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; initialize ( MF ) ; if ( ! collectISELInstructions ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DumpISELInstructions ( ) ; expandAndMergeISELs ( ) ; return true


<s> if ( DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N ->

getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) ) return false ;


<s> bool Changed = false ; for ( unsigned EntryIdx = <NUM_LIT> ; EntryIdx < SwapVector . size ( ) ; ++ EntryIdx ) { if ( SwapVector [ EntryIdx ] . WillRemove ) { Changed = true ; MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ EntryIdx ] .


<s> static <ISA_LIT>Operand * CreateVectorIndex ( unsigned Idx , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_VectorIndex , Ctx ) ; Op -> VectorIndex . Val =


<s> case MachineOperand :: MO_Register : { assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; unsigned Reg = MO . getReg ( ) ; if ( Modifier && strncmp ( Modifier , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { if ( strncmp ( Modifier + <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Reg = TM . getRegisterInfo ( ) -> getSubReg ( Reg , <STR_LIT> ) ; else if ( strncmp ( Modifier + <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Reg = TM . getRegisterInfo ( ) -> getSubReg ( Reg , <STR_LIT> ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; } O << '%' << getRegisterName ( Reg ) ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand ::


<s> Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Glue = N -> getOperand ( <NUM_LIT> ) ; if ( combineCCMask ( Glue , CCValidVal , CCMaskVal ) && combineMergeChains ( Chain , Glue ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Chain , DAG . getConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getConstant ( CCMaskVal , SDLoc

( N ) , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Glue ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; unsigned StackEst = TFI -> determineFrameLayout ( MF , false ,


<s> if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { SDValue Flag ; const unsigned Reg = ( Subtarget . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl ,


<s> tree arg ; for ( arg = DECL_ARGUMENTS ( current_function_decl ) ; arg ; arg = TREE_CHAIN ( arg ) ) { rtx incoming = DECL_INCOMING_RTL ( arg


<s> SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; std :: string LSDAName = <STR_LIT> ; LSDAName += MF . getFunction ( ) -> getName ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , LSDAName . c_str ( ) , <ISA_LIT>PCLabelIndex , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> static <ISA_LIT>Operand * CreateSysCR ( unsigned Val , SMLoc S , SMLoc E , MCContext


<s> return ; if ( ReportAccMoves ) { dbgs ( ) << <STR_LIT> << ( IsPrimed ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsRestore ? <STR_LIT> :


<s> unsigned FnSize = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII . GetInstSizeInBytes ( MI ) ; } return


<s> <STR_LIT> Mode = <STR_LIT> ( Opcode ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } else if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge =


<s> return __builtin_mve_vaddlvaq_sv4si ( __a ,


<s> bool <ISA_LIT>A53Fix835769 :: runOnMachineFunction ( MachineFunction & F ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Changed = false ; TII = F . getSubtarget ( ) . getInstrInfo ( ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock


<s> if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Amt ) ) if ( auto * AmtSplat = AmtBV -> getConstantSplatNode ( ) ) { APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget


<s> SDNode * MultNode = MultHi . getNode ( ) ; unsigned MultOpc = MultHi . getOpcode ( ) ; if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDValue Chain = CurDAG -> getEntryNode ( ) ; DebugLoc dl = SUBENode -> getDebugLoc ( ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MSub = CurDAG -> getNode ( MultOpc , dl , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , SUBCNode -> getOperand ( <NUM_LIT> ) , SUBENode -> getOperand ( <NUM_LIT> ) ) ; SDValue CopyFromLo = CurDAG -> getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> , MSub ) ; SDValue CopyFromHi = CurDAG -> getCopyFromReg ( CopyFromLo . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT>

, CopyFromLo . getValue ( <NUM_LIT> ) ) ;


<s> Function * F = BB -> getParent ( ) ; LLVMContext & Ctx = F -> getContext ( ) ; BasicBlock * ExitBB = BB -> splitBasicBlock ( AI , <STR_LIT> ) ; BasicBlock * LoopBB = BasicBlock :: Create ( Ctx , <STR_LIT> , F , ExitBB ) ; IRBuilder < > Builder ( AI ) ; std :: prev ( BB -> end ( ) ) -> eraseFromParent ( ) ; Builder . SetInsertPoint ( BB ) ; LoadInst * InitLoaded = Builder . CreateLoad ( Addr ) ; InitLoaded -> setAlignment ( AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Builder . CreateBr ( LoopBB ) ; Builder . SetInsertPoint ( LoopBB ) ; PHINode * Loaded = Builder . CreatePHI ( AI -> getType ( ) , <NUM_LIT> , <STR_LIT> ) ; Loaded -> addIncoming ( InitLoaded , BB ) ; Value * NewVal = performAtomicOp ( AI -> getOperation ( ) , Builder , Loaded , AI -> getValOperand ( ) ) ; Value * Pair = Builder . CreateAtomicCmpXchg ( Addr , Loaded , NewVal , Order , AtomicCmpXchgInst :: getStrongestFailureOrdering ( Order ) ) ; Value * NewLoaded = Builder . CreateExtractValue ( Pair , <NUM_LIT> , <STR_LIT> ) ; Loaded -> addIncoming ( NewLoaded


<s> Value * <ISA_LIT>IREmitter :: visitFTOUI ( const


<s> Inst . addOperand ( MCOperand :: CreateImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemDisp ( ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemSegReg ( )


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( TID . getOperandConstraint ( OpIdx , TOI ::


<s> return isInt64Immediate ( N . getNode


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; LiveRegs . init ( TII -> getRegisterInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>_64Target ( )


<s> SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; } } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT>


<s> case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : case Match_AlignedMemoryRequires64 : case Match_DupAlignedMemoryRequires64 : case Match_AlignedMemoryRequires64or128 : case Match_DupAlignedMemoryRequires64or128 : case Match_AlignedMemoryRequires64or128or256 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getAlignmentLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; switch ( MatchResult ) { default : llvm_unreachable ( <STR_LIT> ) ; case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : return Error ( ErrorLoc , <STR_LIT> ) ; case


<s> } Len /= EltSize ; Idx /= EltSize ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back ( i + Idx ) ; for ( int i = Len ; i != ( int ) HalfElts ;

++ i ) ShuffleMask . push_back ( SM_SentinelZero ) ;


<s> unsigned int getNumFixupKinds ( ) const { return <STR_LIT>


<s> if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2

, Mask , Subtarget , DAG ) ) return Blend ;


<s> bool MadeChange = false ; for ( MachineBasicBlock & MBB : MF ) { bool NeedBTI = false ; bool IsFirstBB = & MBB == & MF . front ( ) ; if ( IsFirstBB ) NeedBTI = true ; if ( MBB . hasAddressTaken ( ) || MBB . isEHPad ( ) || JumpTableTargets . count ( & MBB ) ) NeedBTI = true ; if ( NeedBTI ) { addBTI ( TII , MBB , IsFirstBB ) ; MadeChange = true


<s> else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true , true ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * Preheader ) << <STR_LIT> ; for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; } ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return Changed ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB


<s> static void setAliasRegs ( MachineFunction & MF , BitVector & SavedRegs , unsigned Reg ) { const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) SavedRegs . set


<s> ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ; return DAG


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier (


<s> vmla_n_f32 ( float32x2_t a , float32x2_t b , float32_t c ) { float32x2_t result ; float32x2_t t1 ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root ,


<s> } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) <NUM_LIT> ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -=


<s> } int64_t ImmVal = ValAndVReg -> Value . getSExtValue ( ) ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { if ( ! LookedThroughZExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = isSignExtendShiftType ( Ext ) ? <NUM_LIT> : <NUM_LIT> ; if ( SignExtend && Ext != <STR_LIT> ) return None ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg ( ) ) ) ; OffsetReg = moveScalarRegClass ( OffsetReg , <STR_LIT> , MIB ) ; } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Base . getReg ( ) ) ; } , [ = ]

( MachineInstrBuilder & MIB ) { MIB . addUse ( OffsetReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> bool isMemOffs64_64 ( ) const { return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size


<s> vpmax_s32 ( int32x2_t a , int32x2_t b ) { return __builtin_aarch64_smaxpv2si ( a , b )


<s> int Reg = getIntOperandFromRegisterString ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> mapper ; bool IsValidSpecialReg ; Reg = mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits


<s> return __builtin_ia32_vcvtudq2ph512_mask_round ( ( __v16si ) __B , _mm256_setzero_ph ( ) ,


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( MI . modifiesRegister ( BaseReg , TRI ) ) return false ; } if ( isLdStPairSuppressed ( MI ) ) return false ; if ( Subtarget . isPaired128Slow ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT>


<s> return selectAddr ( MI , MI -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && IsProfitableToFold ( PatternNodeWithChain , N . getNode ( ) , Root ) && IsLegalToFold ( PatternNodeWithChain , N . getNode ( ) , Root , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; return selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) . getOperand


<s> MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: Create ( SSym


<s> static SDValue performSETCCCombine ( SDNode * N , SelectionDAG & DAG ) { EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ( Ty != <STR_LIT> ) && ( Ty != <STR_LIT> ) ) return SDValue ( ) ; if ( ! isLegalDSPCondCode ( Ty , cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( )


<s> SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool (


<s> MaxOps = <NUM_LIT> ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxBranches = <NUM_LIT> ; MaxOps = <NUM_LIT> ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxBranches = <NUM_LIT> ; MaxOps = <NUM_LIT> ; } else if ( ST -> hasSSSE3 ( ) ) { MaxBranches = <NUM_LIT> ; MaxOps = <NUM_LIT> ; } else { return ; } unsigned MaxDepth = <NUM_LIT> ; for ( df_iterator < BasicBlock * > DI = df_begin ( L -> getHeader ( ) ) , DE = df_end ( L -> getHeader ( ) ) ; DI != DE ; ) { if ( ! L -> contains ( * DI ) ) { DI . skipChildren ( ) ; continue ; } MaxDepth = std :: max ( MaxDepth , DI . getPathLength ( ) ) ; if ( MaxDepth > MaxBranches ) return ; for ( BasicBlock :: iterator I = DI -> begin ( ) , IE = DI -> end ( ) ; I != IE ; ++ I ) if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } ++ DI ; } UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . PartialOptSizeThreshold = MaxOps ; if ( MaxDepth > <NUM_LIT> ) UP . MaxCount = ( MaxBranches - <NUM_LIT> ) / (


<s> switch ( ( <STR_LIT> ) Fixup . getKind ( ) ) { default : return false ; case <STR_LIT> : if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static unsigned getFixupKindSize ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case


<s> Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } } if ( Match ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue Chain = LD -> getChain


<s> uint64_t Value = CE -> getValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ( Value & <NUM_LIT> ) != <NUM_LIT> && ( Value & <NUM_LIT> ) != <NUM_LIT> ) return false ; return


<s> <ISA_LIT>AddressMode ( ) : BaseType ( RegBase ) , Scale ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , Disp ( <NUM_LIT> ) , GV ( <NUM_LIT> ) { Base . Reg =


<s> assert ( Kind == KindImm && <STR_LIT> ) ; return


<s> report_non_ice ( location , fndecl , argno ) ; return false ; } value_out = tree_to_uhwi ( arg


<s> if ( RM == Reloc :: Default ) RM = Reloc :: Static ; X -> InitMCCodeGenInfo ( RM , CM ) ; return X


<s> SDValue C63 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ; SDValue RL = Op . getOperand ( <NUM_LIT> ) ; SDValue LH = DAG . getNode ( <STR_LIT> , DL , VT , LL , C63 ) ; SDValue RH = DAG . getNode ( <STR_LIT> , DL , VT , RL , C63 ) ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , LL , RL , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SDValue NegLLTimesRH = DAG . getNode ( <STR_LIT> , DL , VT , LL , RH ) ; SDValue NegLHTimesRL = DAG . getNode ( <STR_LIT> , DL , VT , LH , RL ) ; SDValue NegSum = DAG . getNode ( <STR_LIT> , DL , VT , NegLLTimesRH , NegLHTimesRL ) ; Ops [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Ops [ <NUM_LIT> ] , NegSum ) ; } return DAG . getMergeValues ( Ops ,


<s> SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; } if ( FromEltVT ==


<s> void addImm7Shift2Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > (


<s> E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } } case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: create ( RefKind


<s> targetm . target_option . pragma_parse = arm_pragma_target_parse ; targetm . resolve_overloaded_builtin =


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg

( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & *


<s> if ( parseImmExpr ( Size ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFIAllocStack


<s> if ( ! TARGET_AAPCS_BASED ) return default_cxx_get_cookie_size (


<s> static void reorderSubVector ( MVT VT , SmallVectorImpl < Value * > & TransposedMatrix , ArrayRef < Value * > Vec , ArrayRef < uint32_t > VPShuf , unsigned VecElems , unsigned Stride , IRBuilder < > Builder ) { if ( VecElems == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < Stride ; i ++ ) TransposedMatrix [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , UndefValue :: get ( Vec [ i ] -> getType ( ) ) , VPShuf ) ; return ; } SmallVector < uint32_t , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear (


<s> return ( ( qword ) ( vec_ld ( <NUM_LIT> , ( vector unsigned char * )


<s> if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value


<s> if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return false ; unsigned NumElts = Mask . size ( ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned MaxScale = <NUM_LIT> / EltSizeInBits ; for ( unsigned Scale = <NUM_LIT> ; Scale <= MaxScale ; Scale += Scale ) { unsigned SrcEltBits = EltSizeInBits * Scale ; if ( SrcEltBits < <NUM_LIT> && ! Subtarget . hasBWI ( ) ) continue ; unsigned NumSrcElts = NumElts


<s> MCELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & >


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MFI -> getStackProtectorIndex ( ) > <NUM_LIT>

) return StackSizeInBytes >= <NUM_LIT> ;


<s> switch ( CmpMI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; } unsigned NZCV = <STR_LIT> ( CmpBBTailCC ) ; const MCInstrDesc & MCID = TII -> get ( Opc ) ; MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; if ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . isReg ( ) ) MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , MCID ) . addOperand ( CmpMI -> getOperand ( FirstOp ) ) ; if ( isZBranch ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addOperand ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) ) ; MIB . addImm ( NZCV ) . addImm ( HeadCmpBBCC ) ; if (


<s> SDValue OneConstant , AllOnesVec ; APInt Ones = APInt :: getAllOnesValue ( <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; OneConstant = CurDAG -> getConstant ( Ones , DL , <STR_LIT> ) ; insertDAGNode ( * CurDAG , X , OneConstant ) ; unsigned NumElts = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; AllOnesVec = CurDAG -> getSplatBuildVector ( <STR_LIT> ( <STR_LIT> , NumElts ) , DL , OneConstant ) ; insertDAGNode ( * CurDAG , X , AllOnesVec ) ; AllOnesVec = CurDAG -> getBitcast ( VT , AllOnesVec ) ; insertDAGNode ( * CurDAG , X , AllOnesVec ) ; unsigned NewOpcode = Node -> getOpcode ( ) == <STR_LIT> ? <STR_LIT>


<s> vabdq_s32 ( int32x4_t a , int32x4_t b ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> inline unsigned getAM5FP16Opc ( AddrOpc Opc , unsigned char Offset


<s> void addTLSRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ *

valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; int FPImmEncoding = <STR_LIT> ( FPImmValue


<s> return getSchedModel ( ) . isOutOfOrder ( ) && isSwift


<s> } else { switch ( Pred -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = Pred -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; OpChanged = true ; break ; } case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = <STR_LIT> ; OpChanged = true ; break ; } case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = <STR_LIT> ; OpChanged = true ; break ; } default : return false ; } } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( areCFlagsAccessedBetweenInstrs ( Pred , PTest , TRI ) ) return false ; Pred -> setDesc ( get ( NewOp ) ) ; PTest -> eraseFromParent ( ) ; if ( OpChanged ) { bool succeeded = UpdateOperandRegClass ( * Pred ) ; ( void ) succeeded ; assert ( succeeded &&


<s> <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return DAG . getRegister ( FI ->


<s> const char * mips_output_jump ( rtx * operands , int target_opno , int size_opno , bool link_p ) { static char buffer [ <NUM_LIT> ] ; char * s = buffer ; bool reg_p = REG_P ( operands [ target_opno ] ) ; const char * and_link = link_p ? <STR_LIT> : <STR_LIT> ; const char * reg = reg_p ? <STR_LIT> : <STR_LIT> ; const char * compact = <STR_LIT> ; const char * nop = <STR_LIT> ; const char * short_delay = link_p ? <STR_LIT> : <STR_LIT> ; const char * insn_name = TARGET_CB_NEVER || reg_p ? <STR_LIT> : <STR_LIT> ; if ( ! final_sequence && ( TARGET_CB_MAYBE || ( ISA_HAS_JRC && ! link_p && reg_p ) ) ) { compact = <STR_LIT> ; nop = <STR_LIT> ; } if ( TARGET_USE_GOT && ! TARGET_EXPLICIT_RELOCS ) sprintf ( s , <STR_LIT> , insn_name , and_link , target_opno ) ; else { if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s , <STR_LIT> ) ; if ( reg_p && mips_get_pic_call_symbol ( operands , size_opno ) ) { s += sprintf ( s , <STR_LIT> , size_opno ) ; short_delay = <STR_LIT> ; } else s += sprintf ( s , <STR_LIT> ) ; s += sprintf ( s , <STR_LIT> , insn_name , and_link , reg , compact , short_delay , target_opno , nop ) ; if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s


<s> if ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ; if ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ; } return new <ISA_LIT>AsmInstrumentation


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX512 ) return CSR_64_RT_AllRegs_512_RegMask ; if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_RegMask ; return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask


<s> DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load ) , MMOs ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs ( ) ) VTs . push_back ( VT ) ; } if ( Load ) BeforeOps . push_back ( SDValue ( Load , <NUM_LIT> ) ) ; BeforeOps . insert ( BeforeOps . end ( ) , AfterOps . begin ( ) , AfterOps . end ( ) ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isNullConstant ( BeforeOps [ <NUM_LIT> ] ) ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } BeforeOps [ <NUM_LIT> ] = BeforeOps [ <NUM_LIT> ] ; } } SDNode * NewNode = DAG . getMachineNode ( Opc , dl , VTs , BeforeOps ) ; NewNodes . push_back ( NewNode ) ; if ( FoldedStore ) { AddrOps . pop_back ( ) ; AddrOps . push_back ( SDValue ( NewNode , <NUM_LIT> ) ) ; AddrOps . push_back ( Chain ) ; auto MMOs = extractStoreMMOs ( cast < MachineSDNode > ( N ) -> memoperands ( ) , MF ) ; if ( MMOs . empty ( ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlign ( ) >= Alignment ; SDNode * Store = DAG . getMachineNode ( getStoreRegOpcode ( <NUM_LIT> , DstRC , isAligned , Subtarget ) , dl , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Store ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Store )


<s> gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= <NUM_LIT> ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( store_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2


<s> return new Emitter < JITCodeEmitter > (


<s> isFirst = isSingle = isCracked = isLoad = isStore = false ; return <STR_LIT> ; } Opcode = ~ Opcode ; const TargetInstrDesc & TID = TII . get ( Opcode ) ; isLoad = TID . mayLoad ( ) ; isStore = TID .


<s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const unsigned GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumGPRs = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned VARegSize = ( <NUM_LIT> - NumGPRs ) * <NUM_LIT> ; unsigned VARegSaveSize = ( VARegSize + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ; unsigned ArgOffset = CCInfo . getNextStackOffset ( ) ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; VarArgsFrameIndex = MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize , true , false ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; NumGPRs < <NUM_LIT> ; ++ NumGPRs


<s> if ( MCID . Opcode == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } unsigned Binary = getBinaryCodeForInstr (


<s> SDValue NewML = DAG . getMaskedLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMask ( ) , DAG . getUNDEF ( VT ) , ML -> getMemoryVT ( ) , ML -> getMemOperand ( ) , ML -> getExtensionType ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , NewML , ML -> getSrc0 ( ) ) ; return DCI . CombineTo ( ML , Blend ,

NewML . getValue ( <NUM_LIT> ) , true ) ;


<s> if ( TARGET_FMA ) { x = validize_mem ( force_const_mem ( SFmode , x ) ) ; fp_hi = gen_rtx_FMA ( SFmode , fp_hi , x , fp_lo ) ; emit_move_insn ( target , fp_hi ) ; } else { fp_hi = expand_simple_binop ( SFmode , MULT , fp_hi , x , fp_hi , <NUM_LIT> , OPTAB_DIRECT ) ; fp_hi = expand_simple_binop ( SFmode , PLUS , fp_hi , fp_lo , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( ! rtx_equal_p ( target , fp_hi ) ) emit_move_insn


<s> if ( isThumb ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> ) return true ; if ( ( ( isThumb ( ) && Mnemonic == <STR_LIT> ) || ( isThumbTwo ( ) && Mnemonic == <STR_LIT> ) ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <STR_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) == <NUM_LIT> && ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) || static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm0_1020s4 ( ) ) ) return true ; if ( isThumbTwo ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isReg ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isImm ( ) ) { if ( ( ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getReg ( ) ) || ! is<ISA_LIT>LowRegister ( static_cast < <ISA_LIT>Operand * > (

Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isT2SOImm ( ) ) return false ;


<s> static const struct InstructionSpecifier * specifierForUID ( InstrUID uid ) { return & INSTRUCTIONS_SYM


<s> SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( Subtarget -> hasSSE3 ( ) ) if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT>


<s> unsigned Size = TD -> getTypeAllocSize ( C -> getType ( ) ) ; unsigned Align = TD -> getPreferredAlignmentLog ( GVar ) ; printVisibility ( name , GVar -> getVisibility ( ) ) ; SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } else { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: CommonLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; case GlobalValue :: GhostLinkage : cerr << <STR_LIT> ; abort ( ) ; case GlobalValue :: DLLImportLinkage : cerr << <STR_LIT> ; abort ( ) ; case GlobalValue :: DLLExportLinkage : cerr << <STR_LIT> ; abort ( ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } EmitAlignment ( Align , GVar ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) ) { O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << Size << '\n' ; } O << name <<


<s> unsigned Opcode = MCID . getOpcode ( ) ; if ( ! ( <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) ) ) return - <NUM_LIT> ; unsigned NumUses = MCID . getNumOperands ( ) - MCID .


<s> unsigned AluCode = AluOp . getImm ( ) ; const MCOperand Op2 = Inst . getOperand ( <NUM_LIT> ) ; Value &= ~ ( <NUM_LIT> << PBitShift ) ; if ( ! LPAC :: isPostOp ( AluCode ) && ( ( Op2 . isImm ( ) && Op2 . getImm ( ) != <NUM_LIT> ) || ( Op2 . isReg ( ) && Op2 . getReg ( ) != <STR_LIT> ) || ( Op2 . isExpr ( ) ) ) ) Value |= ( <NUM_LIT> << PBitShift ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Value &= ~ ( <NUM_LIT> << QBitShift


<s> const struct processor * entry = arch ? all_architectures : all_cores ; for ( ; entry -> name != NULL ; entry ++ ) candidates . safe_push ( entry -> name ) ; char * s ; const char * hint = candidates_list_and_hint ( str , s , candidates ) ; if ( hint ) inform ( input_location , <STR_LIT> <STR_LIT> , s , hint ) ; XDELETEVEC ( s )


<s> debug ( <STR_LIT> ) ; return true ; } mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + maskRegNum ) ) ; return false


<s> case <NUM_LIT> : DecodedValue = - <NUM_LIT> ; break ; default : DecodedValue = SignExtend32 < <NUM_LIT> > ( Insn ) ; break ; } Inst . addOperand ( MCOperand :: createImm ( DecodedValue * <NUM_LIT> ) ) ; return MCDisassembler


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) ; if ( RegCtx . AddressReg ( <STR_LIT> ) != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . AddressReg ( <STR_LIT> ) ) ) ; } const std :: string & Fn = FuncName ( AccessSize , IsWrite ) ; MCSymbol * FnSym = Ctx . getOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( FnExpr


<s> rtx rs6000_got_register ( rtx value ATTRIBUTE_UNUSED ) { if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table


<s> regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS ; regno ++ ) { rtx dwarf ; rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , reg ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx dwarf ; rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , reg ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn


<s> return ( __m128d ) __builtin_ia32_cmpgepd ( ( __v2df


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return false ; SDValue Src = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , APInt > :: iterator M = SrcOpMap . find ( Src ) ; if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( SrcOpMap . begin ( ) != SrcOpMap . end ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt EltCount = APInt :: getNullValue ( NumElts ) ; M = SrcOpMap . insert ( std :: make_pair ( Src , EltCount ) ) . first ; SrcOps . push_back ( Src ) ; } unsigned CIdx = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( M -> second [ CIdx ] ) return false ; M -> second . setBit ( CIdx ) ; } for ( DenseMap < SDValue , APInt > :: const_iterator I = SrcOpMap . begin ( ) , E = SrcOpMap . end ( ) ; I != E ;


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash (


<s> User * V = U . getUser ( ) ; while ( V ) { if ( isAMXCast ( dyn_cast < Instruction > ( V ) ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; OpNo = U . getOperandNo ( ) ; V = U . getUser ( ) ; } else if ( isAMXInstrinsic ( V ) ) { return getShape ( cast < IntrinsicInst > ( V ) , OpNo ) ; } else if ( isa < PHINode > ( V ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( Phi ->


<s> bool isPKHASRImm ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> static const char Nops32Bit [ <NUM_LIT> ] [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const char Nops16Bit [ <NUM_LIT> ] [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const char ( * Nops ) [ <NUM_LIT> ] = STI -> getFeatureBits ( )


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; Tok = Parser . getTok ( ) ; if ( ! parseFpABIValue ( FpAbiVal ,


<s> Is64Bit = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! UseControlFlowSpeculationBarrier ) { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsNeedingCSDBBeforeUse . set ( * AI ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , Is64Bit ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) ) . addDef ( DstReg ) . addUse ( SrcReg , RegState :: Kill ) . addUse ( Is64Bit ? MisspeculatingTaintReg : MisspeculatingTaintReg32Bit ) . addImm ( <NUM_LIT> ) ; } MI . eraseFromParent (


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root ,


<s> StringRef Format2 = Name . slice ( Next , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format2 , NameLoc ) ) ; setFpFormat ( Format1 ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; setFpFormat ( Format2 ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; return


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCoprocNum ( unsigned CopVal , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CoprocNum ) ; Op -> Cop . Val = CopVal ; Op -> StartLoc = S ; Op -> EndLoc =


<s> OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC


<s> FunctionPass * llvm :: create<ISA_LIT>FixupSetCC ( ) { return new <ISA_LIT>FixupSetCCPass (


<s> cfun -> machine -> call_abi = ix86_function_abi


<s> LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG


<s> static <ISA_LIT>MCExpr :: VariantKind PermittedModifiers [ ] = { <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 , <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0 , <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1 , <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G0 , } ; unsigned NumModifiers = llvm ::


<s> if ( ST -> genExecuteOnly ( ) ) { if ( isFPImmLegal ( FPVal , VT ) ) return Op ; APInt INTVal = FPVal . bitcastToAPInt ( ) ; SDLoc DL ( CFP ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : { SDValue Lo = DAG . getConstant ( INTVal . trunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue Hi = DAG . getConstant ( INTVal . lshr ( <NUM_LIT> ) . trunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ; if ( ! ST -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( INTVal , DL , <STR_LIT> ) ) ; } } if ( ! ST -> hasVFP3Base ( ) ) return SDValue ( ) ; if ( IsDouble && ! Subtarget -> hasFP64 ( ) ) return SDValue ( ) ; int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op


<s> assert ( HalfMask . size ( ) == HalfNumElts && <STR_LIT> ) ; unsigned NumLowerHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; unsigned NumUpperHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; assert ( NumLowerHalves + NumUpperHalves <= <NUM_LIT> && <STR_LIT> ) ; unsigned EltWidth = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! UndefLower ) { if ( NumUpperHalves == <NUM_LIT> ) return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) ) { if ( EltWidth == <NUM_LIT> && NumLowerHalves && HalfVT . is128BitVector ( ) && ! is128BitUnpackShuffleMask ( HalfMask ) && ( ! isSingleSHUFPSMask ( HalfMask ) || Subtarget . hasFastVariableCrossLaneShuffle ( ) ) ) return SDValue ( ) ; if ( EltWidth == <NUM_LIT> && V2 . isUndef ( ) ) return SDValue ( ) ; } if ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) return SDValue ( ) ; return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; } assert ( NumUpperHalves == <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) && EltWidth == <NUM_LIT> ) return SDValue


<s> if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp =


<s> if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget )


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects


<s> ReverseIter End = MBB -> rend ( ) ; ReverseIter Br = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; auto it = MBB -> begin ( ) ; for ( ; it != MBB -> end ( ) ; ++ it ) { if ( & * it == & * Br ) break ; } if ( ( Br != End ) && ! Br -> isIndirectBranch ( ) && ( Br -> isConditionalBranch ( ) || ( Br -> isUnconditionalBranch ( ) && IsPIC ) ) ) MBBInfos


<s> OS << <STR_LIT> << <STR_LIT> ( ArchExt )


<s> size = int_size_in_bytes ( type ) ; if ( MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P ( type ) && size <= <NUM_LIT> ) return <NUM_LIT> ; if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { if ( size < <NUM_LIT> ) return <NUM_LIT> ; if ( size == <NUM_LIT> ) return ( TARGET_MMX ? <NUM_LIT> : <NUM_LIT> ) ; if ( size == <NUM_LIT> ) return ( TARGET_SSE ? <NUM_LIT> : <NUM_LIT> ) ; } if ( mode == XFmode ) return <NUM_LIT> ; if ( size > <NUM_LIT> ) return <NUM_LIT> ; return


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << Name . upper ( ) ; else O << <STR_LIT> << formatImm


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( )


<s> bool ForceTailPredication = EnableTailPredication == TailPredication :: ForceEnabledNoReductions || EnableTailPredication == TailPredication :: ForceEnabled ; Value * ElemCount = ActiveLaneMask -> getOperand ( <NUM_LIT> ) ; auto * EC = SE -> getSCEV ( ElemCount ) ; auto * TC = SE -> getSCEV ( TripCount ) ; int VectorWidth = VecTy -> getNumElements ( ) ; ConstantInt * ConstElemCount = nullptr ; if ( ! SE -> isLoopInvariant ( EC , L ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ( ConstElemCount = dyn_cast < ConstantInt > ( ElemCount ) ) ) { ConstantInt * TC = dyn_cast < ConstantInt > ( TripCount ) ; if ( ! TC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } uint64_t TC1 = TC -> getZExtValue ( ) * VectorWidth ; uint64_t TC2 = ConstElemCount -> getZExtValue ( ) + <NUM_LIT> ; if ( TC1 != TC2 ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TC1 << <STR_LIT> << TC2 << <STR_LIT> ) ; return false ; } } else if ( ! ForceTailPredication ) { auto * VW = SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth ) ) ; auto * ECPlusVWMinus1 = SE -> getAddExpr ( EC , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth - <NUM_LIT> ) ) ) ; auto * Ceil = SE -> getUDivExpr ( ECPlusVWMinus1 , VW ) ; ( void ) TC ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; TC -> dump ( ) ; dbgs ( ) << <STR_LIT> ; EC -> dump (


<s> unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) : CurDAG ->

getTargetConstant ( - RHSC , <STR_LIT> ) ;


<s> unsigned Opc = N -> getOpcode ( ) ; assert ( ( ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) || ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) ) && <STR_LIT> ) ; const bool Scaled = Opc == <STR_LIT> || Opc == <STR_LIT> ; const bool Signed = Opc == <STR_LIT> || Opc == <STR_LIT> ; const bool Extended = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; SDLoc DL ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Pg = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; SDValue Ty = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType


<s> static section * mips_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT


<s> tree aarch64_general_builtin_decl ( unsigned code , bool


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS


<s> } if ( InstCnt ) * InstCnt += BitGroups . size ( ) ; for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { TruncateToInt32 ( BG . V , dl ) , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , TruncateToInt32 ( BG . V , dl ) , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } } if ( LateMask ) { unsigned Mask = ( unsigned ) getZerosMask ( ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + (

unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ;


<s> unsigned <STR_LIT> ( Type * Ty , bool IsComplex ) const { unsigned NumVectorInstToHideOverhead = <NUM_LIT>


<s> if ( Entry . Special ) return ReduceSpecial ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI ,