<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( UseFSRMForMemcpy && Subtarget . hasFSRM ( ) ) return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , Size , <STR_LIT> ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue (


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWin64 ( )


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind


<s> enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return <NUM_LIT> ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return <NUM_LIT> ; else return cost ; } if ( dep_type != REG_DEP_OUTPUT


<s> unsigned RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! getConstantVRegVal ( RHS , MRI ) ) std :: swap ( RHS , LHS ) ; const auto RHSImm = getConstantVRegVal ( RHS , MRI ) ; if ( ! RHSImm || * RHSImm != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; const auto Pred = ( CmpInst :: Predicate ) CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ; const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ; unsigned CBOpc = <NUM_LIT> ; if ( CmpWidth <= <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else if ( CmpWidth == <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else return false ; auto MIB = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( CBOpc ) ) . addUse ( LHS ) . addMBB ( DestMBB ) ; constrainSelectedInstRegOperands ( * MIB . getInstr ( ) ,


<s> bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; std :: map < unsigned , Chain * > ActiveChains ; std :: set < std :: unique_ptr < Chain >> AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * >


<s> void <ISA_LIT>WinCOFFStreamer :: emitWinEHHandlerData ( SMLoc Loc ) { MCStreamer :: emitWinEHHandlerData ( Loc )


<s> emitLeadingFence ( Builder , CI , Ord ) ; Value * LoHi = Builder . CreateCall ( IntCmpXchg , { Addr , CmpLo , CmpHi , NewLo , NewHi } ) ; emitTrailingFence ( Builder , CI , Ord ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) )


<s> if ( isConsecutiveAccess ( MemOp0 , MemOp1 , DL ,


<s> SDLoc & DL = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; IsTailCall = false


<s> BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } } if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformORCombine_i1 ( N , DCI , Subtarget ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) ) { if ( SDValue Res = PerformORCombineToBFI ( N , DCI , Subtarget ) ) return Res ; } if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) )


<s> bool <ISA_LIT>ConstantIslands :: FixUpImmediateBr ( MachineFunction & Fn , ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return FixUpUnconditionalBr ( Fn , Br ) ; return FixUpConditionalBr ( Fn ,


( unsigned long long __C , unsigned long long __V ) {


<s> if ( ! GetImm ( MI2 , <NUM_LIT> , Offset2 ) ) return false ; Register Reg1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( ( Offset1 == ( Offset2 - <NUM_LIT> ) ) && ( ConsecutiveRegisters ( Reg1 ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG , DebugLoc dl ) { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; case


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue G = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , SB , G ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; unsigned e = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual (

N -> getMaskElt ( i ) , i ) ) return false ;


<s> y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) , ( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ; result = vec_or ( vec_sll ( ( qword ) ( a ) ,


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode =


<s> const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } O << <STR_LIT> ; printOperand ( MI , Op , O ) ; O <<


<s> unsigned NumElem = SrcVTy -> getNumElements ( ) ; auto * MaskTy = FixedVectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int MaskSplitCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment


<s> const char * name ; if ( ! TREE_PUBLIC ( decl ) || DECL_COMMON ( decl ) || ( DECL_INITIAL ( decl ) == NULL_TREE && DECL_ALIGN ( decl ) <= BIGGEST_ALIGNMENT ) || DECL_INITIAL ( decl ) == error_mark_node || ( flag_zero_initialized_in_bss && initializer_zerop ( DECL_INITIAL ( decl ) ) ) ) return ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = ( * targetm . strip_name_encoding ) (


<s> OperandMatchResultTy parseFP128 ( SmallVectorImpl < MCParsedAsmOperand


<s> bool hasCondMov ( ) const { return HasCondMov


<s> return ; } if ( ( ! TARGET_SH2E && ! TARGET_SH4 ) || TARGET_HITACHI || sh_cfun_attr_renesas_p ( ) ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_next_o = TYPE_FIELDS ( va_list_type_node ) ; f_next_o_limit = TREE_CHAIN ( f_next_o ) ; f_next_fp = TREE_CHAIN ( f_next_o_limit ) ; f_next_fp_limit = TREE_CHAIN ( f_next_fp ) ; f_next_stack = TREE_CHAIN ( f_next_fp_limit ) ; next_o = build ( COMPONENT_REF , TREE_TYPE ( f_next_o ) , valist , f_next_o , NULL_TREE ) ; next_o_limit = build ( COMPONENT_REF , TREE_TYPE ( f_next_o_limit ) , valist , f_next_o_limit , NULL_TREE ) ; next_fp = build ( COMPONENT_REF , TREE_TYPE ( f_next_fp ) , valist , f_next_fp , NULL_TREE ) ; next_fp_limit = build ( COMPONENT_REF , TREE_TYPE ( f_next_fp_limit ) , valist , f_next_fp_limit , NULL_TREE ) ; next_stack = build ( COMPONENT_REF , TREE_TYPE ( f_next_stack ) , valist , f_next_stack , NULL_TREE ) ; u = make_tree ( ptr_type_node , expand_builtin_saveregs ( ) ) ; t = build ( MODIFY_EXPR , ptr_type_node , next_fp , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nfp = current_function_args_info . arg_count [ SH_ARG_FLOAT ] ; if ( nfp < <NUM_LIT> ) nfp = <NUM_LIT> - nfp ; else nfp = <NUM_LIT> ; u = fold ( build ( PLUS_EXPR , ptr_type_node , u , build_int_cst ( NULL_TREE , UNITS_PER_WORD *


<s> unsigned <ISA_LIT>TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG &


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr


<s> if ( __alignment == <NUM_LIT> || ( sizeof ( void * ) == <NUM_LIT> && __alignment == <NUM_LIT> ) ) __alignment = sizeof ( void * ) ; if ( posix_memalign ( & __ptr , __alignment

, __size ) == <NUM_LIT> ) return __ptr ;


<s> SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; SDValue POTAddress = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; POTAddress = DAG . getLoad ( PtrVT , dl , Chain , POTAddress , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; Chain = POTAddress . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , POTReg , POTAddress ) ; SDValue Ops [ <NUM_LIT> ] =


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectIntAddrMSA ( SDValue Addr , SDValue & Base , SDValue &


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT ,


<s> bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto RC = Is32Bit ? & <STR_LIT> : & <STR_LIT> ; return emitADDS ( MRI . createVirtualRegister ( RC )


<s> for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ! <STR_LIT> . contains ( Reg ) || MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; unsigned LastVSRUsedForSpill = <NUM_LIT> ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; Register Reg = CS . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } if ( LastVSRUsedForSpill != <NUM_LIT> ) { CS . setDstReg ( LastVSRUsedForSpill ) ; BVAllocatable . reset ( LastVSRUsedForSpill ) ; LastVSRUsedForSpill = <NUM_LIT> ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; LastVSRUsedForSpill =


<s> for ( MachineRegisterInfo :: livein_iterator I = MF . getRegInfo ( ) . livein_begin ( ) , E = MF . getRegInfo ( ) . livein_end ( ) ; I != E ; ++ I ) { if ( I -> first == <STR_LIT> ) { AFI -> setR3IsLiveIn ( true ) ; break ; } } NumBytes = ( NumBytes + <NUM_LIT> ) & ~ <NUM_LIT> ; MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , - VARegSaveSize ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT>


<s> static DecodeStatus DecodeStoreI32 ( MCInst & Inst , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeMem ( Inst , insn , Address

, Decoder , false , DecodeI32RegisterClass ) ;


<s> rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg ( sel_mode , sel ) ) ; else aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d ->


<s> if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + <STR_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + <STR_LIT> ) . isReg ( ) && isScale ( MI -> getOperand ( Op + <STR_LIT> ) ) && MI -> getOperand ( Op + <STR_LIT> ) . isReg ( ) && ( MI -> getOperand ( Op + <STR_LIT> ) . isImm ( ) || MI -> getOperand ( Op + <STR_LIT> ) . isGlobal ( ) || MI -> getOperand ( Op + <STR_LIT> ) . isCPI ( ) || MI ->

getOperand ( Op + <STR_LIT> ) . isJTI ( ) ) ;


<s> return ( __m128i ) __builtin_ia32_vpconflictdi_128_mask ( ( __v2di ) __A , ( __v2di )


<s> if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 -> getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 -> getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex (


<s> if ( parseToken ( AsmToken :: Comma ) ) return addErrorSuffix ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitValueToAlignment


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ResultTy = Extend -> getType ( ) ; if ( ResultTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } } Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , ResultTy , Ptr , Builder ) ; if ( ! BasePtr ) return nullptr ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , OriginalTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; Root = Extend ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits (

) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) } ) ;


<s> } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 , CCR , Cmp2 , DAG ) ; } return Result


<s> case <STR_LIT> : Sign *= - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) *


<s> MBB . erase_instr ( & MI ) ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ClobberReg , RegState :: Define ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ClobberReg ) ; } else { MachineInstr * Fence = BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; addRegOffset ( BuildMI ( MBB , Fence , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) , <STR_LIT> , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) -> addRegisterDead ( <STR_LIT> , TRI ) ; } ++ NumFences ; Modified = true ; } if ( Modified ) ++


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( )


<s> case GE : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCX_NOOVmode ; else return CC_NOOVmode ; } else { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode


<s> int name_len ; const char * name ; const char * unique_name = NULL ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; if ( make_unique ) unique_name = IDENTIFIER_POINTER ( get_file_function_name ( <STR_LIT> ) ) ; name_len = strlen ( name ) + strlen ( suffix ) + <NUM_LIT> ; if ( make_unique ) name_len += strlen ( unique_name )


<s> return parseAddress ( Operands , BDMem , <STR_LIT> , GR64Reg


<s> if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; IRBuilder < > Builder ( LI ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( LI -> getPointerOperand ( ) , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> mode = CCmode , code = GTU ; break ; case C ( 'l' , 'e' ) : mode = CCmode , code = LE ; break ; case C ( 'l' , 's' ) : mode = CCmode , code = LEU ; break ; case C ( 'l' , 't' ) : mode = CCmode , code = LT ; break ; case C ( 'm' , 'i' ) : mode = CC_NZmode , code = LT ; break ; case C ( 'n' , 'e' ) : mode = CC_NZmode , code = NE ; break ; case C ( 'p' , 'l' ) : mode = CC_NZmode , code = GE ; break ; case C ( 'v' , 'c' ) : mode = CC_Vmode , code = EQ ; break ; case C ( 'v' , 's' ) : mode = CC_Vmode , code = NE ; break ; default : error_at ( loc , <STR_LIT> , constraints [ i ] ) ; continue ; } rtx dest = outputs [ i ] ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! SCALAR_INT_MODE_P ( dest_mode ) ) { error_at ( loc , <STR_LIT> ) ; continue ; } if ( ! saw_asm_flag ) { constraints [ i ] = <STR_LIT> ; outputs [ i ] = gen_rtx_REG ( CCmode , CC_REGNUM ) ; saw_asm_flag = true ; } else { constraints [ i ] = <STR_LIT> ; outputs [ i ] = gen_rtx_SCRATCH ( word_mode ) ; } rtx x = gen_rtx_REG ( mode , CC_REGNUM ) ; x = gen_rtx_fmt_ee ( code , word_mode , x , const0_rtx


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GV -> getType ( )


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue Undef = DAG . getUNDEF ( Ptr . getValueType ( ) ) ; SDValue Ops [ ] = { Chain , Val , Ptr , Undef } ; return SignedSat ? DAG . getTargetMemSDNode < TruncSStoreSDNode > ( VTs , Ops , Dl , MemVT , MMO ) : DAG . getTargetMemSDNode < TruncUSStoreSDNode > ( VTs , Ops , Dl , MemVT


<s> if ( epilogue_completed ) { if ( regno == LR_REGNUM ) return <NUM_LIT> ; } return


<s> if ( AlignBoundary == Align :: None ( ) || AlignBranchType == <ISA_LIT>AlignBranchKind :: AlignBranchNone ) return false ; MCAssembler & Assembler = OS . getAssembler ( ) ; MCSection * Sec = OS . getCurrentSectionOnly


<s> switch ( Kind ) { case FK_Data_2 : return ELF :: R_390_PC16 ; case FK_Data_4 : return ELF :: R_390_PC32 ; case FK_Data_8 : return ELF :: R_390_PC64 ; case <STR_LIT> : return ELF :: R_390_PC16DBL ; case <STR_LIT> : return ELF :: R_390_PC32DBL ; case <STR_LIT> : return ELF :: R_390_PLT16DBL ; case <STR_LIT> : return ELF ::


<s> if ( CONST_OK_FOR_N ( disp ) ) { * spill_fill_data . prev_addr [ iter ] = gen_rtx_POST_MODIFY ( DImode , spill_fill_data . iter_reg [ iter ] , gen_rtx_PLUS ( DImode , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; REG_NOTES ( spill_fill_data . prev_insn [ iter ] ) = gen_rtx_EXPR_LIST ( REG_INC , spill_fill_data . iter_reg [ iter ] , REG_NOTES ( spill_fill_data . prev_insn [ iter ] ) ) ; } else { if ( ! CONST_OK_FOR_I ( disp ) ) { rtx tmp = gen_rtx_REG ( DImode , next_scratch_gr_reg ( ) ) ; emit_move_insn ( tmp , disp_rtx ) ; disp_rtx = tmp ; } emit_insn ( gen_adddi3 ( spill_fill_data . iter_reg [ iter ] , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; } } else if ( disp == <NUM_LIT> && spill_fill_data . init_reg [ iter ] == stack_pointer_rtx && frame_pointer_needed ) { mem = gen_rtx_MEM ( GET_MODE (


<s> void <ISA_LIT>InstPrinter :: printMemRegReg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , STI


<s> std :: vector < std :: string > getCallMagicLabels ( ) { std :: vector < std :: string > labels ; for ( int i = <NUM_LIT> ; i < sgx_call_magic_labels_index ; i ++ ) labels . push_back (


<s> void setSRetReturnReg ( unsigned Reg )


<s> bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc ( ) , CondReg ) ; auto & CMovRC = * MRI -> getRegClass ( CMovI .

getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ValTy == LLT :: scalar ( <NUM_LIT> ) ) { assert ( ( * MI . memoperands_begin ( ) ) -> getSuccessOrdering ( ) == AtomicOrdering :: Monotonic || ( * MI . memoperands_begin ( ) ) -> getSuccessOrdering ( ) == AtomicOrdering :: Unordered ) ; assert ( ST -> hasLSE2 ( ) && <STR_LIT> ) ; LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; MachineInstrBuilder NewI ; if ( MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) { NewI = MIRBuilder . buildInstr ( <STR_LIT> , { s64 , s64 } , { } ) ; MIRBuilder . buildMerge ( ValReg , { NewI -> getOperand ( <NUM_LIT> ) , NewI -> getOperand ( <NUM_LIT> ) } ) ; } else { auto Split = MIRBuilder . buildUnmerge ( s64 , MI . getOperand ( <NUM_LIT> ) ) ; NewI = MIRBuilder . buildInstr ( <STR_LIT> , { } , { Split -> getOperand

( <NUM_LIT> ) , Split -> getOperand ( <NUM_LIT> ) } ) ;


<s> static <ISA_LIT>Operand * CreateCondCode ( <STR_LIT> Code ,


<s> rtx sym ; int select = sel ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= <NUM_LIT> && select <= <NUM_LIT> ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( regno ,


<s> void <ISA_LIT>ExpandPseudo :: ExpandVST ( MachineBasicBlock :: iterator & MBBI ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const NEONLdStTableEntry * TableEntry = LookupNEONLdSt ( MI . getOpcode ( ) ) ; assert ( TableEntry && ! TableEntry -> IsLoad && <STR_LIT> ) ; NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx =


<s> else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- )

XVECEXP ( x , i , j ) = replace_with_subreg ( XVECEXP ( x , i , j ) , reg , new_reg ) ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) .

addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( readsLocalId ( II ) ) return true ; if ( readWorkgroupInvariant ( II ) ) return false ; if ( isPureFunction ( II ) ) return false ; } if ( isa < CallInst > ( I


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { return RM . hasValue ( ) ?


<s> int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI


<s> unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded =


<s> if ( ! DefMI -> mayLoad ( ) || DefMI -> getNumOperands ( ) < <NUM_LIT> ) return true ; unsigned Flags = DefMI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI -> hasOneMemOperand ( ) ) ; Val = ( * DefMI -> memoperands_begin ( ) ) -> getValue ( ) ; if ( ! Val ) Val = ( * DefMI -> memoperands_begin ( ) )


<s> unsigned getRsaSize ( void ) const {


<s> static unsigned getFixupKindLog2Size ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_1 : case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4


<s> SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT>


<s> VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; } return isConsecutiveLSLoc ( N -> getOperand ( <NUM_LIT> ) , VT , Base , Bytes , Dist , DAG ) ; } if ( N -> getOpcode ( ) == <STR_LIT> ) { EVT VT ; switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT>


<s> if ( Mode == <STR_LIT> || Mode == <STR_LIT> ) Parser . Lex ( ) ; else if ( Mode == <STR_LIT> || Mode == <STR_LIT> ) return Error ( L , <STR_LIT> ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( )


<s> MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit


<s> if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) ||

MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ;


<s> for ( auto & BB : * MF ) { for ( auto & I : BB ) { if ( I . getOpcode ( ) == <STR_LIT> ) { ReTags . push_back ( & I ) ; int FI = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; TaggedSlots . insert ( FI ) ; assert ( I . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; } } } if ( ReTags . empty ( ) ) return false ; if ( mayUseUncheckedLoadStore ( )


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv ::


<s> int64_t ElementBits = VT . getScalarSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt


<s> __arm_vldrhq_u32 ( uint16_t const * __base ) { return __builtin_mve_vldrhq_uv4si ( ( __builtin_neon_hi * )


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_zeroupper ( void ) { __builtin_ia32_vzeroupper ( )


<s> <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const MCExpr * OffsetExpr ; int64_t OffsetVal ; SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) || ! OffsetExpr -> evaluateAsAbsolute ( OffsetVal


<s> rtx op1 = XEXP ( addis_value , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) && satisfies_constraint_L ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = op0 ; fuse_ops [ <NUM_LIT> ] = op1 ; addis_str = <STR_LIT> ; } } else if ( GET_CODE ( addis_value ) == HIGH ) { rtx value = XEXP ( addis_value , <NUM_LIT> ) ; if ( GET_CODE ( value ) == UNSPEC && XINT ( value , <NUM_LIT> ) == UNSPEC_TOCREL ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_ELF ) addis_str = <STR_LIT> ; else if ( TARGET_XCOFF ) addis_str = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( GET_CODE ( value ) == PLUS ) { rtx op0 = XEXP ( value , <NUM_LIT> ) ; rtx op1 = XEXP ( value , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == UNSPEC && XINT ( op0 , <NUM_LIT> ) == UNSPEC_TOCREL && CONST_INT_P ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( op0 , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( op0 , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ]


<s> auto * Caller = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CalleeCC ) ) return false ; if ( any_of ( Ins , [ ] ( const <STR_LIT> & IA ) { return IA . Flags . isByVal ( ) ; } ) ) return false ; if ( any_of ( Outs , [ ] ( const <STR_LIT> & OA ) { return OA . Flags . isByVal ( ) ; } ) ) return false ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) return false ; if ( ! callsShareTOCBase ( Caller , Callee ,


<s> warnIfRegIndexIsAT ( FirstReg , IDLoc ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; MCOperand & FirstOffset = Inst . getOperand ( <NUM_LIT> ) ; signed NextOffset = FirstOffset . getImm ( ) + <NUM_LIT> ; MCOperand SecondOffset = MCOperand :: createImm ( NextOffset ) ; if ( ! isInt < <NUM_LIT> > ( FirstOffset . getImm ( ) ) || ! isInt < <NUM_LIT> > ( NextOffset ) ) return true ; if ( ! IsLittleEndian ) std :: swap ( FirstReg , SecondReg ) ; TOut . emitRRX ( Opcode , FirstReg , BaseReg , FirstOffset , IDLoc , STI ) ; TOut . emitRRX ( Opcode , SecondReg , BaseReg


<s> } } } if ( frame_pointer_needed ) { for ( i = <NUM_LIT> , offset = local_fsize ; i >= <NUM_LIT> ; i -- ) if ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) { load_reg ( i , offset , FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } else { for ( i = <NUM_LIT> , offset = local_fsize - actual_fsize ; i >= <NUM_LIT> ; i -- ) { if ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) { if ( merge_sp_adjust_with_load == <NUM_LIT> && local_fsize == <NUM_LIT> && VAL_14_BITS_P ( - actual_fsize ) ) merge_sp_adjust_with_load = i ; else load_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { if ( frame_pointer_needed ) set_reg_plus_d ( <NUM_LIT> , FRAME_POINTER_REGNUM , offset ) ; else set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset ) ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( regs_ever_live [ i ] || ( ! TARGET_64BIT && regs_ever_live [ i + <NUM_LIT> ] ) ) { rtx src = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC ( DFmode , tmpreg ) ) ; rtx dest = gen_rtx_REG ( DFmode , i ) ; emit_move_insn ( dest , src ) ; } } emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { rtx delta = GEN_INT ( - <NUM_LIT> ) ; rtx insn ; set_reg_plus_d ( STACK_POINTER_REGNUM , FRAME_POINTER_REGNUM , <NUM_LIT> ) ; insn = emit_insn ( gen_pre_load ( frame_pointer_rtx , stack_pointer_rtx , delta ) ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( word_mode , stack_pointer_rtx , delta ) ) , REG_NOTES ( insn ) ) ; } } else if ( merge_sp_adjust_with_load ) { rtx delta = GEN_INT (


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleOddSPReg ( ) { <ISA_LIT>TargetStreamer :: emitDirectiveModuleOddSPReg ( ) ; OS << <STR_LIT> << ( ABIFlagsSection . OddSPReg ? <STR_LIT> : <STR_LIT> )


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg


<s> HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX =


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , MII ( mii ) , InstInfo ( nullptr ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; Instrumentation . reset ( Create<ISA_LIT>AsmInstrumentation ( Options , Parser . getContext ( ) , STI )


<s> unsigned Directive = DAG -> TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || CurSlots == <NUM_LIT> ) { CurGroup . clear ( ) ; CurSlots = CurBranches = <NUM_LIT> ; } else { CurGroup . push_back ( <NUM_LIT> ) ; ++ CurSlots


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo


<s> static char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> , arm_text_section_count ++ ) ; if ( flag_pic ) strcat ( buf ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo


<s> case <STR_LIT> ## X : return <STR_LIT> ## X ; \ case <STR_LIT> ## X : return <STR_LIT> ## X ; \ case <STR_LIT> ## X : return <STR_LIT> | <STR_LIT> ## X switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; CONV ( EQ ) ; CONV ( NE ) ; CONV ( GT


<s> if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = FixedVectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) ,


<s> void Initialize ( const MachineFunction & MF , bool isPIC , bool


<s> Value * <ISA_LIT>IREmitter :: visitSRA_FLAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg (


<s> tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int form_int ; enum rtx_code code ; if ( TREE_CODE ( form ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCFPmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0


<s> MachineInstr * Def = RDA -> getMIOperand ( LoLoop . Start , isDo ( LoLoop . Start ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! Def ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _subborrow_u32 ( unsigned char __CF , unsigned

int __X , unsigned int __Y , unsigned int * __P ) {


<s> <ISA_LIT>MCAsmStreamer :: <ISA_LIT>MCAsmStreamer ( MCContext & Ctx , std :: unique_ptr < formatted_raw_ostream > os , bool isVerboseAsm , MCInstPrinter * printer , bool showInst ) : MCStreamer ( Ctx ) , OSOwner ( std :: move ( os ) ) , OS ( * OSOwner ) , MAI ( Ctx . getAsmInfo ( ) ) , InstPrinter ( printer ) , CommentStream ( CommentToEmit ) , IsVerboseAsm ( isVerboseAsm ) , ShowInst ( showInst ) { assert (


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) ==


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MF . getRegInfo ( ) . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsELF32_ABI = Subtarget . isELF32_ABI ( ) ; bool IsMachoABI = Subtarget . isMachoABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && IsELF32_ABI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , IsMachoABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT>


<s> static DecodeStatus DecodeStoreI64 ( MCInst & Inst , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder ,


<s> SmallVectorImpl < MachineInstr * > & getDefUses ( ) { return DefUses


<s> const tree decl2 = default_version_info -> this_node -> decl ; if ( is_function_default_version ( decl2 ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; error_at ( DECL_SOURCE_LOCATION ( default_node -> decl ) , <STR_LIT> <STR_LIT> ) ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ; struct cgraph_node * dispatcher_node = NULL ; struct cgraph_function_version_info * dispatcher_version_info = NULL ; dispatch_decl = make_dispatcher_decl ( default_node -> decl ) ; dispatcher_node = cgraph_node :: get_create ( dispatch_decl ) ; gcc_assert ( dispatcher_node != NULL ) ; dispatcher_node -> dispatcher_function = <NUM_LIT> ; dispatcher_version_info = dispatcher_node -> insert_new_function_version ( ) ; dispatcher_version_info -> next = default_version_info ; dispatcher_node -> definition = <NUM_LIT> ; it_v = default_version_info ; while ( it_v != NULL ) { it_v -> dispatcher_resolver = dispatch_decl ; it_v = it_v ->


<s> int n_groups ; if ( sched_verbose ) fprintf ( dump , <STR_LIT> ) ; if ( reload_completed && rs6000_sched_groups ) { if ( sel_sched_p ( ) ) return ; if ( rs6000_sched_insert_nops == sched_finish_none ) return ; if ( rs6000_sched_insert_nops == sched_finish_pad_groups ) n_groups = pad_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; else n_groups = redefine_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; if ( sched_verbose >= <NUM_LIT> ) { fprintf ( dump , <STR_LIT> , n_groups ) ; print_rtl ( dump , current_sched_info


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , TargetCC ,


<s> unsigned short base_mode_size = GET_MODE_SIZE ( base_mode ) ; int nregs = size / base_mode_size , i ; rtx regs ; regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( base_mode , regno ) , GEN_INT ( base_mode_size * i ) ) ; regno += base_mode_size


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT . isScalableVector ( ) ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Subtarget -> hasLS64 ( ) && VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getFixedSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : { if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . isScalableVector ( ) ) { if ( VT . getVectorElementType ( ) != <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; } uint64_t VTSize = VT . getFixedSizeInBits ( ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VTSize == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } case 'x' : if ( ! Subtarget -> hasFPARMv8 ( ) )


<s> const MachineInstr * L2 = * Entry . second . begin ( ) ; const MachineInstr * L1 = Entry . first ; if ( ! MDT -> dominates ( L2 , L1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; SmallVector < const MachineInstr * , <NUM_LIT> > Args ; Args . push_back (


<s> if ( CONST_INT_P ( si1 ) && CONST_INT_P ( si2 ) ) { unsigned HOST_WIDE_INT const1 = ( UINTVAL ( si1 ) & mask_32bit ) << <NUM_LIT> ; unsigned HOST_WIDE_INT const2 = UINTVAL ( si2 ) & mask_32bit ; emit_move_insn ( dest , GEN_INT ( const1 | const2 ) ) ; return ; } if ( CONST_INT_P ( si1 ) ) emit_move_insn ( dest , GEN_INT ( ( UINTVAL ( si1 ) & mask_32bit ) << <NUM_LIT> ) ) ; else { rtx si1_di = gen_rtx_REG ( DImode , regno_or_subregno ( si1 ) ) ; rtx shift_rtx = gen_rtx_ASHIFT ( DImode , si1_di , GEN_INT ( <NUM_LIT>


<s> static DecodeStatus DecodeMemAS ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder , bool isLoad , DecodeFunc DecodeSX ) { unsigned sx = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeAS ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address


<s> unsigned Width ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return


<s> unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( is64Bit ) { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) ,

Offset , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> (


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , Mask [ <NUM_LIT> ] == SM_SentinelUndef ? DAG . getUNDEF ( <STR_LIT> ) : V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ]


<s> DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> << CFARegisterOffset << <STR_LIT> << RegOffsets [ <NUM_LIT> ] << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } uint32_t CompactUnwindEncoding = CU :: UNWIND_<ISA_LIT>_MODE_FRAME ; switch ( StackAdjust ) { case <NUM_LIT> : break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; default : DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } static struct { unsigned Reg ; unsigned Encoding ; } GPRCSRegs [ ] = { { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R6 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R5 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R4 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R12 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R11 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R10 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R9 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R8 } } ; int CurOffset = - <NUM_LIT> - StackAdjust ; for ( auto CSReg : GPRCSRegs ) { auto Offset = RegOffsets . find ( CSReg . Reg ) ; if ( Offset == RegOffsets . end ( ) ) continue ; int RegOffset = Offset -> second ; if ( RegOffset != CurOffset - <NUM_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << MRI . getName ( CSReg . Reg ) << <STR_LIT> << RegOffset << <STR_LIT> << CurOffset << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } CompactUnwindEncoding |= CSReg . Encoding ; CurOffset -= <NUM_LIT> ; } if ( FloatRegCount == <NUM_LIT> ) return CompactUnwindEncoding ; CompactUnwindEncoding &= ~ CU :: UNWIND_<ISA_LIT>_MODE_MASK ; CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_MODE_FRAME_D ; if ( FloatRegCount >


<s> resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * I , * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * this , * I ,


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister


<s> static bool IsMasked ( Instruction * I ) { auto * Call = dyn_cast < IntrinsicInst > ( I


<s> static SDValue lowerShuffleAsLanePermuteAndBlend ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; int Size = Mask . size ( ) ; int LaneSize = Size / <NUM_LIT> ; if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Flipped = DAG . getBitcast ( PVT , V1 ) ; Flipped = DAG . getVectorShuffle ( PVT , DL , Flipped , DAG . getUNDEF ( PVT ) , { <NUM_LIT> , <NUM_LIT>


<s> void <ISA_LIT>DCModule :: insertExternalWrapperAsm ( BasicBlock * InsertAtEnd , Value * ExternalFunc


<s> return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ; auto TBL2 = MIRBuilder . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { RegSeq , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * RegSeq , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( * TBL2 , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; } unsigned NZCV = <STR_LIT> ( CmpBBTailCC ) ; const MCInstrDesc & MCID = TII -> get ( Opc ) ; MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; if ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . isReg ( ) ) MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , MCID ) . add ( CmpMI -> getOperand ( FirstOp ) ) ; if ( isZBranch ) MIB . addImm ( <NUM_LIT> ) ; else MIB . add ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) ) ; MIB . addImm ( NZCV ) . addImm ( HeadCmpBBCC ) ; if ( isZBranch ) { bool isNZ = CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode (


<s> if ( odd ) { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } else { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf


<s> unsigned RA = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) )


<s> rtx tmp = * ( const rtx * ) y ; rtx tmp2 = * ( const rtx * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? <NUM_LIT> : - <NUM_LIT> ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2


<s> SDValue CmpOp0 = Cmp . getOperand ( <NUM_LIT> ) ; SDValue NewCmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CmpOp0 , DAG . getConstant ( <NUM_LIT> , CmpOp0 . getValueType ( ) ) ) ; SDValue OtherVal = N -> getOperand ( N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG . getConstant ( - <NUM_LIT> , OtherVal . getValueType ( ) ) , NewCmp ) ; return DAG . getNode ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , OtherVal . getValueType ( ) , OtherVal , DAG .

getConstant ( <NUM_LIT> , OtherVal . getValueType ( ) ) , NewCmp ) ;


<s> OutMCInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) )


<s> a = ( __vector unsigned short ) vec_splats ( __A ) ; b = ( __vector unsigned short ) vec_splats ( __B ) ; w0 = vec_vmuleuh ( a , b ) ; w1 = vec_vmulouh ( a , b ) ; c = ( __vector unsigned short ) vec_perm ( w0 , w1 , xform1 ) ; return ( __m64 ) ( ( __vector long long ) c )


<s> if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG


<s> if ( Counter >= CTRLoopLimit ) return false ; Counter ++ ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( TT , * I ) ) return MadeChange ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; BasicBlock * CountedExitBlock = nullptr ; const SCEV * ExitCount = nullptr ; BranchInst * CountedExitBranch = nullptr ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI ) ) continue ; if ( ! DT -> dominates ( * I , * PI ) ) { NotAlways = true ; break ; } } if ( NotAlways )


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> if ( mode != V4SFmode && all_const_zero ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_XOR ( mode , target , target ) ) ) ; return ; } else if ( mode != V4SFmode && easy_vector_constant ( vals , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , vals ) ) ; return ; } else if ( all_same ) ; else { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ) ; return ; } } if ( all_same ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , <NUM_LIT> ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , target , mem ) , x ) ) ) ; x = gen_rtx_VEC_SELECT ( inner_mode , target , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ; rs6000_expand_vector_init ( target , copy ) ; rs6000_expand_vector_set ( target , XVECEXP ( vals , <NUM_LIT> , one_var ) , one_var ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE

( inner_mode ) ) , XVECEXP ( vals , <NUM_LIT> , i ) ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx , false


<s> if ( rclass == FPSCR_REGS && ( ( REG_P ( x ) && REGNO ( x ) >= FIRST_PSEUDO_REGISTER ) || ( MEM_P ( x ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) ) ) return GENERAL_REGS ; } if ( ( ( REGCLASS_HAS_FP_REG ( rclass ) && ( REG_P ( x ) && ( GENERAL_OR_AP_REGISTER_P ( REGNO ( x ) ) || ( FP_REGISTER_P ( REGNO ( x ) ) && mode == SImode && TARGET_FMOVD ) ) ) ) || ( REGCLASS_HAS_GENERAL_REG ( rclass ) && REG_P ( x ) && FP_REGISTER_P ( REGNO ( x ) ) ) ) && ( mode == SFmode || mode == SImode ) ) return FPUL_REGS ; if ( ( rclass == FPUL_REGS || ( REGCLASS_HAS_FP_REG ( rclass ) && mode == SImode ) ) && ( MEM_P ( x ) || ( REG_P ( x ) && ( REGNO ( x ) >= FIRST_PSEUDO_REGISTER || REGNO ( x ) == T_REG || system_reg_operand ( x , VOIDmode ) ) ) ) ) { if ( rclass == FPUL_REGS ) return GENERAL_REGS ; return NO_REGS ; } if ( ( rclass == MAC_REGS || rclass == PR_REGS ) && REG_P ( x ) && ! GENERAL_REGISTER_P ( REGNO ( x ) ) && rclass != REGNO_REG_CLASS ( REGNO ( x ) ) ) return GENERAL_REGS ; if ( rclass == FPUL_REGS && true_regnum ( x ) == - <NUM_LIT> ) return GENERAL_REGS ; if ( ( mode == QImode || mode == HImode ) && rclass != R0_REGS && satisfies_constraint_Sdd ( x ) && sh_disp_addr_displacement ( x ) <= sh_max_mov_insn_displacement ( mode , false ) ) return R0_REGS ; if ( ( mode == QImode || mode == HImode ) && rclass != R0_REGS && GET_CODE ( x

) == SUBREG && true_regnum ( x ) == - <NUM_LIT> ) return R0_REGS ;


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> ,


<s> Value * <ISA_LIT>IREmitter :: visitBR_JT ( const


<s> return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute


<s> bool isCCRegNumber ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> >


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified =


<s> return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC && GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT ) { rtx lhs = SET_DEST ( body ) ; if ( ! MEM_P ( lhs ) ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_ST ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VSX_CVDPSPN ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) return <NUM_LIT> ; for ( ; link ; link = link -> next ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; rtx use_body = PATTERN ( use_insn ) ; if ( GET_CODE ( use_body ) != SET || GET_CODE ( SET_SRC ( use_body ) ) != UNSPEC || XINT ( SET_SRC ( use_body ) , <NUM_LIT> ) != UNSPEC_VSX_XXSPLTW || XVECEXP ( SET_SRC ( use_body ) , <NUM_LIT> , <NUM_LIT> ) != const0_rtx ) return <NUM_LIT> ; } } return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_CONCAT && ( GET_MODE ( SET_SRC ( body ) ) == V2DFmode || GET_MODE ( SET_SRC ( body ) ) == V2DImode ) ) { * special = SH_CONCAT ; return <NUM_LIT> ; } if ( GET_CODE ( body ) == PARALLEL ) { rtx expr = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( expr ) == SET && v2df_reduction_p ( SET_SRC ( expr ) ) ) return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VPERM && XVECLEN ( SET_SRC ( body ) , <NUM_LIT> ) == <NUM_LIT> && REG_P ( XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ) ) { rtx mask_reg = XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) if ( rtx_equal_p ( DF_REF_REG ( use ) , mask_reg ) ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( def_link && ! def_link -> next && const_load_sequence_p ( insn_entry , DF_REF_INSN (


<s> XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; break ; } for ( j = <NUM_LIT> , i ++ ; j < num_regs ; i ++ ) if ( mask & ( <NUM_LIT> << i ) ) { rtx reg = gen_rtx_REG ( SImode , i ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ; tmp = gen_rtx_SET ( gen_frame_mem ( SImode , addr ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j ) = gen_rtx_USE ( VOIDmode , reg ) ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; j ++ ; } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; add_reg_note ( par ,


<s> if ( Outs . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Outs [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) || IsMCU ) return


<s> case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumberOfParts ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += <NUM_LIT> ; return Cost ; } case Instruction :: Select


<s> emit_insn ( GEN_FCN ( CODE_FOR_tcommit ) ( ) ) ; break ; case AARCH64_TME_BUILTIN_TCANCEL : { tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; if ( CONST_INT_P ( op0 ) && UINTVAL ( op0 ) <= <NUM_LIT> ) emit_insn ( GEN_FCN ( CODE_FOR_tcancel ) ( op0 ) ) ; else { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } } break ; default : gcc_unreachable ( )


<s> unsigned int Imm = getShiftExtendAmount ( ) ; Inst . addOperand ( MCOperand :: createImm


<s> case ELF :: R_<ISA_LIT>_GOT_LO32 : case ELF :: R_<ISA_LIT>_GOTOFF_HI32 : case ELF :: R_<ISA_LIT>_GOTOFF_LO32 : case ELF :: R_<ISA_LIT>_TLS_GD_HI32 : case ELF ::


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplat ( SDNode * N , APInt & Imm ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { Register XMMReg = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveXMMRegs . push_back ( DAG . getCopyFromReg ( Chain , DL , XMMReg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Offset = FuncInfo -> getVarArgsGPOffset ( ) ; for ( SDValue Val : LiveGPRs ) { SDValue FIN = DAG . getNode ( <STR_LIT> , DL , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) , RSFIN , DAG . getIntPtrConstant ( Offset ,


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects


<s> initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry ( )


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : assert ( hasReservedCallFrame ( MF )


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( F . getParent ( ) -> getDataLayout ( ) ) ; } LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( BasicTTIImpl ( this ,


<s> OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText (


<s> for ( MachineBasicBlock :: pred_iterator PI = ReturnMBB . pred_begin ( ) , PIE = ReturnMBB . pred_end ( ) ; PI != PIE ; ++ PI ) { bool OtherReference = false , BlockChanged = false ; if ( ( * PI ) -> empty ( ) ) continue ; for ( MachineBasicBlock :: iterator J = ( * PI ) -> getLastNonDebugInstr ( ) ; ; ) { if ( J == ( * PI ) -> end ( ) ) break ; if ( J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( I -> getOpcode ( ) ) ) . copyImplicitOps ( I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( J -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode


<s> static void mips_init_print_operand_punct ( void ) { const char *


<s> void <ISA_LIT>DAGToDAGISel :: EmitSpecialCodeForMain ( MachineBasicBlock * BB , MachineFrameInfo * MFI ) { const TargetInstrInfo * TII = getInstrInfo (


<s> if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue (


<s> ShuffleMask . push_back ( i + NElts / <NUM_LIT> ) ; ShuffleMask . push_back ( i + NElts + NElts / <NUM_LIT>


<s> inline vector unsigned char vec_vmrghb ( vector unsigned char a1 , vector unsigned char


<s> if ( hasFP ( MF ) ) return FramePtr ; return


<s> uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += <STR_LIT> ; } return result


<s> case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTLZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMULH ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerRotate ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op


<s> case _<ISA_LIT>_CMP_EQ_US : return std :: make_tuple ( false , <STR_LIT> ) ; case _<ISA_LIT>_CMP_LT_OS : case _<ISA_LIT>_CMP_LT_OQ : return std :: make_tuple ( true , <STR_LIT> ) ; case _<ISA_LIT>_CMP_NGE_US : case _<ISA_LIT>_CMP_NGE_UQ : return std :: make_tuple ( false , <STR_LIT> ) ; case _<ISA_LIT>_CMP_LE_OS : case _<ISA_LIT>_CMP_LE_OQ : return std :: make_tuple ( true , <STR_LIT> ) ; case _<ISA_LIT>_CMP_NGT_US : case _<ISA_LIT>_CMP_NGT_UQ : return std :: make_tuple ( false , <STR_LIT> ) ; case _<ISA_LIT>_CMP_GT_OS : case _<ISA_LIT>_CMP_GT_OQ : return std :: make_tuple ( true , <STR_LIT> ) ; case _<ISA_LIT>_CMP_NLE_US : case _<ISA_LIT>_CMP_NLE_UQ : return std :: make_tuple ( false , <STR_LIT> ) ; case _<ISA_LIT>_CMP_GE_OS : case _<ISA_LIT>_CMP_GE_OQ : return std :: make_tuple ( true , <STR_LIT> ) ; case _<ISA_LIT>_CMP_NLT_US : case _<ISA_LIT>_CMP_NLT_UQ : return std :: make_tuple ( false , <STR_LIT> ) ; case _<ISA_LIT>_CMP_NEQ_OQ : case _<ISA_LIT>_CMP_NEQ_OS : return std :: make_tuple ( true , <STR_LIT> ) ; case _<ISA_LIT>_CMP_NEQ_UQ : case _<ISA_LIT>_CMP_NEQ_US : return std :: make_tuple ( false , <STR_LIT>


<s> Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( Subtarget ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope


<s> EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder


<s> static SDValue lower512BitShuffle ( const SDLoc & DL , ArrayRef < int > Mask , MVT VT , SDValue V1 , SDValue V2 , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; int NumElts = Mask . size ( ) ; int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . hasBWI ( ) ) { if ( SDValue V = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue V = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } if ( VT == <STR_LIT> ) { V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget ,


<s> int i , j ; if ( mips_macc_chains_last_hilo != <NUM_LIT> ) for ( i = nready - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( mips_linked_madd_p ( mips_macc_chains_last_hilo , ready


<s> SDValue B = FoldableOp . getOperand ( <NUM_LIT> ) ; SDValue C = FoldableOp . getOperand ( <NUM_LIT> ) ; const uint8_t TernlogMagicA = <NUM_LIT> ; const uint8_t TernlogMagicB = <NUM_LIT> ; const uint8_t TernlogMagicC = <NUM_LIT> ; uint8_t Imm ; switch ( FoldableOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Imm = TernlogMagicB & TernlogMagicC ; break ; case <STR_LIT> : Imm = TernlogMagicB | TernlogMagicC ; break ; case <STR_LIT> : Imm = TernlogMagicB ^ TernlogMagicC ; break ; case <STR_LIT> : Imm = ~ ( TernlogMagicB ) & TernlogMagicC ; break ; } switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( A == N0 ) Imm &= ~ TernlogMagicA ; else Imm = ~ ( Imm )


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true


<s> static void CalculateTailCallArgDest ( SelectionDAG & DAG , MachineFunction & MF , bool is<ISA_LIT>64 , SDValue Arg , int SPDiff , unsigned ArgOffset , SmallVector < TailCallArgumentInfo , <NUM_LIT> > & TailCallArguments ) { int Offset = ArgOffset + SPDiff ; uint32_t OpSize = ( Arg . getValueType ( ) . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( OpSize , Offset , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FIN = DAG . getFrameIndex ( FI , VT ) ; TailCallArgumentInfo Info ; Info . Arg =


<s> inline static unsigned char ModRMByte ( unsigned Mod , unsigned RegOpcode , unsigned RM ) { assert ( Mod < <NUM_LIT> && RegOpcode < <NUM_LIT> && RM < <NUM_LIT>


<s> __builtin_ia32_movdqa32store512_mask ( ( __v16si * ) __P , ( __v16si )


<s> size = int_size_in_bytes ( type ) ; if ( TARGET_AAPCS_BASED ) { if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != COMPLEX_TYPE ) return false ; if ( ( ( unsigned HOST_WIDE_INT ) size ) <= UNITS_PER_WORD ) return false ; if ( aapcs_select_return_coproc ( type , fntype ) >= <NUM_LIT> ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < <NUM_LIT> || size > ( <NUM_LIT> * UNITS_PER_WORD ) ) ; return true ; } if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < <NUM_LIT> || size > ( <NUM_LIT> * UNITS_PER_WORD ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && ( TREE_CODE ( type ) != VECTOR_TYPE ) ) return false ; if ( arm_abi != ARM_ABI_APCS ) { return ( size < <NUM_LIT> || size > UNITS_PER_WORD ) ; } if ( size < <NUM_LIT> || size > UNITS_PER_WORD ) return true ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field && TREE_CODE ( field ) != FIELD_DECL ; field = DECL_CHAIN ( field ) ) continue ; if ( field == NULL ) return false ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return true ; if ( arm_return_in_memory ( TREE_TYPE ( field ) , NULL_TREE ) )


<s> bool <ISA_LIT>AsmParser :: ParseIntelInlineAsmIdentifier ( const MCExpr * & Val , StringRef & Identifier , InlineAsmIdentifierInfo & Info , bool IsUnevaluatedOperand , SMLoc & End , bool IsParsingOffsetOperator ) { MCAsmParser & Parser = getParser ( ) ; assert ( isParsingMSInlineAsm ( ) && <STR_LIT> ) ; Val = nullptr ; StringRef LineBuf ( Identifier . data ( ) ) ; SemaCallback -> LookupInlineAsmIdentifier ( LineBuf , Info , IsUnevaluatedOperand ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; do { End = Tok . getEndLoc (


<s> case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = KnownZero . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; KnownZero |= Mask ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; KnownZero |= Mask ; } break ; }


<s> MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! MBB . getParent ( ) -> getFunction ( ) . optForMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI ->


<s> Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( <STR_LIT> ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo


<s> return __builtin_mve_vminq_sv4si ( __a ,


<s> RetAddr -- ; RetAddr -= <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << ( void * ) RetAddr << <STR_LIT> << ( void * ) StackPtr << <STR_LIT> << TheVM -> getFunctionReferencedName ( ( void * ) RetAddr ) << <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if (


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; COMMDirectiveTakesAlignment = true ; SunStyleELFSectionSwitchSyntax =


<s> if ( Subtarget -> hasV8Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isMClass ( ) && Subtarget -> hasThumb2DSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TOps ( ) )