<s> bool isAndroid ( ) const { return IsAndroid


<s> Type * DestTy = I -> getType ( ) ; Value * Op = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Op -> getType ( ) ; EVT SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; EVT DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( Op ) ; unsigned ResultReg ; if ( SrcVT == <STR_LIT> ) { uint64_t Mask = <NUM_LIT> ; switch ( DestVT . SimpleTy


<s> for ( ConstantPoolMapTy :: iterator CPI = ConstantPools . begin ( ) , CPE = ConstantPools . end ( ) ; CPI != CPE ; ++ CPI


<s> int LaneCount = std :: max ( VectorSize / <NUM_LIT> , <NUM_LIT> ) ; for ( int Lane = <NUM_LIT> ; Lane < LaneCount ; Lane ++ ) for ( int i = <NUM_LIT> , LaneSize = VF / LaneCount ; i != LaneSize ; ++

i ) Mask . push_back ( ( i * Stride ) % LaneSize + LaneSize * Lane ) ;


<s> assert ( ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) || MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) && <STR_LIT> ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned BaseReg = MI . getOperand (


<s> if ( crtl -> profile ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4120 || TARGET_FIX_RM7000 || TARGET_FIX_24K || TARGET_MIPS5900 ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4130 && ! ISA_HAS_MACCHI ) cfun -> machine -> all_noreorder_p = false ; mips_offset_table htab ( <NUM_LIT> ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( USEFUL_INSN_P ( subinsn ) ) { rtx body = PATTERN ( insn ) ; int noperands = asm_noperands ( body ) ; if ( noperands >= <NUM_LIT> ) { rtx * ops = XALLOCAVEC ( rtx , noperands ) ; bool * used = XALLOCAVEC ( bool , noperands ) ; const char * string = decode_asm_operands ( body , ops , NULL , NULL , NULL , NULL ) ; get_referenced_operands ( string , used , noperands ) ; for ( int i = <NUM_LIT> ; i < noperands ; ++ i ) if ( used [ i ] ) mips_record_lo_sums ( ops [ i ] , & htab ) ; } else mips_record_lo_sums ( PATTERN ( subinsn ) , & htab ) ; } last_insn = <NUM_LIT> ; hilo_delay = <NUM_LIT> ; delayed_reg = <NUM_LIT> ; lo_reg = gen_rtx_REG ( SImode , LO_REGNUM ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = next_insn ) { next_insn = NEXT_INSN ( insn ) ; if ( USEFUL_INSN_P ( insn ) ) { if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { FOR_EACH_SUBINSN ( subinsn , insn ) if ( INSN_P ( subinsn ) ) { if ( mips_orphaned_high_part_p ( & htab , subinsn ) ) { PATTERN ( subinsn ) =


<s> FunctionPass * createZDCPass ( ) { return new ZDC (


<s> static DecodeStatus DecodeCacheOpMM ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Hint = fieldFromInstruction ( Insn


<s> return constrainSelectedInstRegOperands ( * AddP , TII , TRI , RBI ) ; } unsigned Opc = <NUM_LIT> ; if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } I . setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } if ( I . getOpcode ( ) == TargetOpcode :: G_VECREDUCE_FADD ) { unsigned Opc = <NUM_LIT> ; if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> ,


<s> if ( const auto * Entry = CostTableLookup ( NEONSelShuffleTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; } } if ( ST -> hasMVEIntegerOps ( ) ) { if ( Kind == TTI :: SK_Broadcast ) { static const CostTblEntry MVEDupTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( MVEDupTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost * ST -> getMVEVectorCostFactor ( TTI :: TCK_RecipThroughput ) ; } if ( ! Mask . empty ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( Mask . size ( ) <= LT . second . getVectorNumElements ( ) && ( isVREVMask ( Mask , LT . second , <NUM_LIT> ) || isVREVMask ( Mask , LT . second , <NUM_LIT> ) || isVREVMask ( Mask , LT . second , <NUM_LIT> ) ) ) return ST -> getMVEVectorCostFactor ( TTI :: TCK_RecipThroughput ) * LT . first ; } } int BaseCost = ST -> hasMVEIntegerOps ( ) && Tp -> isVectorTy ( ) ? ST -> getMVEVectorCostFactor ( TTI :: TCK_RecipThroughput ) : <NUM_LIT> ; return BaseCost * BaseT :: getShuffleCost ( Kind , Tp , Mask


<s> bool softPromoteHalfType ( ) const override { return true


<s> } else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getZeroExtendVectorInReg ( ShAmt , SDLoc ( ShAmt ) , <STR_LIT> ) ; } else { SDValue ShOps [ <NUM_LIT> ] = { ShAmt , DAG . getConstant ( <NUM_LIT> , dl , SVT ) , DAG . getUNDEF ( SVT ) , DAG . getUNDEF ( SVT ) } ; ShAmt = DAG . getBuildVector ( <STR_LIT> , dl , ShOps ) ; } MVT EltVT = VT . getVectorElementType ( ) ; MVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT .


<s> int <ISA_LIT>FrameLowering :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; int64_t Offset = ( MFFrame -> getObjectOffset ( FI ) + MFFrame -> getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ; return


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ValVT == <STR_LIT> || ValVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; return false ; } unsigned Off = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT


<s> if ( E ) EVal = <ISA_LIT>MCExpr :: Create ( Variant , E , false , getParser ( ) .


<s> bool <ISA_LIT>AsmBackend :: MayNeedRelaxation ( const MCInst &


<s> } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) && ! PAIRED_VECTOR_MODE ( mode ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = ( ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high_int ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( PAIRED_VECTOR_MODE ( mode ) ) { if ( mode == DImode ) return x ; if ( GET_CODE ( x ) == PLUS ) { rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; rtx y ; op1 = force_reg ( Pmode , op1 ) ; op2 = force_reg ( Pmode , op2 ) ; y = gen_rtx_PLUS ( Pmode , op1 , op2 ) ; if ( ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || mode == DDmode ) && REG_P ( op2 ) ) return force_reg ( Pmode , y ) ; else return y ; } return force_reg ( Pmode , x ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic && GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_WIDE_INT && GET_CODE ( x ) != CONST_DOUBLE && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_ELF ) emit_insn ( gen_elf_high ( reg , x ) ) ; else emit_insn ( gen_macho_high ( reg , x ) ) ; return gen_rtx_LO_SUM ( Pmode , reg


<s> return ( ( FP_REG_CLASS_P ( class1 ) != FP_REG_CLASS_P ( class2 ) ) && ( ! TARGET_VIS3

|| GET_MODE_SIZE ( mode ) > <NUM_LIT> || GET_MODE_SIZE ( mode ) < <NUM_LIT> ) ) ;


<s> const MachineOperand & IndexReg = MI -> getOperand ( OpNo + <STR_LIT> ) ; const MachineOperand & DispSpec = MI -> getOperand ( OpNo + <STR_LIT> ) ; const MachineOperand & SegReg = MI -> getOperand ( OpNo + <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; O << ':' ; } O << '[' ; bool NeedPlus = false ; if ( BaseReg . getReg ( ) ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> ) O << <STR_LIT> ; else { O << <STR_LIT> ; DispVal = - DispVal ; } } O << DispVal ; } } O <<


<s> if ( Bytes . size ( ) < <NUM_LIT> ) return Fail ; Size = <NUM_LIT> ; uint32_t Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return decodeInstruction ( DecoderTable32 , MI , Insn ,


<s> if ( align < <NUM_LIT> ) { rtx scratch1 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( scratch1 , out ) ; if ( align != <NUM_LIT> ) { align_3_label = gen_label_rtx ( ) ; align_2_label = gen_label_rtx ( ) ; align_rtx = expand_binop ( Pmode , and_optab , scratch1 , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_2_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , GTU , NULL , Pmode , <NUM_LIT> , align_3_label ) ; } else { align_rtx = expand_binop ( Pmode , and_optab , scratch1 , const2_rtx , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; } mem = change_address ( src , QImode , out ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; if ( align != <NUM_LIT> ) { emit_label ( align_2_label ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; emit_label ( align_3_label ) ; } emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; } emit_label ( align_4_label )


<s> if ( ! IsTailPredicationLegal ( ) ) return IsDo ? <STR_LIT> : <STR_LIT> ; return VCTPOpcodeToLSTP ( VCTP -> getOpcode ( ) , IsDo


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount ,


<s> TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugInstr ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; Register NPredReg ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( ( NCC ^ CC ) & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos


<s> switch ( RetType -> getTypeID ( ) ) { case Type :: FloatTyID : case Type :: DoubleTyID : return true ; default : ; } if ( F . arg_size ( ) >= <NUM_LIT> ) { Argument & Arg = F . getArgumentList ( ) . front ( ) ; switch ( Arg . getType ( ) -> getTypeID ( ) ) { case Type :: FloatTyID : case Type


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF .

getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ;


<s> return ( __a + ( __b * __aarch64_vget_lane_any


<s> unsigned sx = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RET_REG || ( TARGET_SH2E && regno ==


<s> key . m_GOTPage = m_CurrentGOTPart ; key . m_pInfo = pInfo ; key . m_Addend = <NUM_LIT> ; m_GotTLSGdEntriesMap [ key ] = pEntry ; } else if ( pType == llvm :: ELF :: R_MIPS_TLS_GOTTPREL ) { GotEntryKey key ; key . m_GOTPage = m_CurrentGOTPart ; key . m_pInfo = pInfo ; key . m_Addend = <NUM_LIT> ; m_GotTLSGotEntriesMap [ key ] = pEntry ; } else { llvm_unreachable ( <STR_LIT>


<s> inline static unsigned getTruncatedShiftCount ( MachineInstr * MI , unsigned ShiftAmtOperandIdx ) { unsigned ShiftCountMask = ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Imm = MI -> getOperand ( ShiftAmtOperandIdx ) . getImm ( ) ; return Imm &


<s> } memset ( & d , <NUM_LIT> , sizeof ( d ) ) ; d . target = target ; d . op0 = t1 ; d . op1 = t1 ; d . vmode = vmode ; d . nelt = GET_MODE_NUNITS ( vmode ) ; d . one_vector_p = true


<s> unsigned getGPRMM16Reg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ; return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; else Val = MO . getImm ( ) >> <NUM_LIT> ; bool I = ( Val & <NUM_LIT> ) ; bool J1 = ( Val & <NUM_LIT> ) ; bool J2 = ( Val & <NUM_LIT> ) ; if ( I ^ J1 ) Val &=


<s> if ( Op . isReg ( ) && Op . isImplicit ( ) && Op . isDead ( ) && TRI -> regsOverlap ( Op . getReg ( ) , <STR_LIT> ) ) { Op . setIsDead ( false ) ; Op . setIsDef ( true ) ; RAXImplicitDead = true ; } OriginalCall -> addOperand ( Op ) ; } auto * Marker = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . getInstr ( ) ; if ( MI . shouldUpdateCallSiteInfo ( ) ) MBB . getParent ( ) -> moveCallSiteInfo


<s> if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if (

! getFauxShuffleMask ( Op , Mask , Inputs ) ) return false ;


<s> ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = <STR_LIT> ; SC = <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; MI -> eraseFromParent ( ) ; return


<s> else { if ( type && AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> || slotno == SPARC_FP_ARG_MAX - <NUM_LIT> ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || ( type && VECTOR_TYPE_P ( type ) ) ) && ! (


<s> else if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags ==


<s> unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; if ( SrcVT == <STR_LIT> ) { uint64_t Mask = <NUM_LIT> ; switch ( DestVT . SimpleTy ) { default : return false ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; } unsigned Reg32 = FastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; MRI . constrainRegClass ( Reg32 , & <STR_LIT> ) ; unsigned ANDReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ANDReg ) . addReg ( Reg32 ) . addImm ( <STR_LIT> ( Mask , <NUM_LIT> ) ) ; SrcReg = ANDReg ; } UpdateValueMap ( I , SrcReg ) ; return true


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; const Triple & TT = STI . getTargetTriple ( ) ; bool is<ISA_LIT>64 = TT .


<s> if ( ! InsMI ) return false ; if ( ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return false ; if ( ! mi_match ( InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ZeroInt ( ) ) ) return false ; MatchInfo = ShuffleVectorPseudo ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , { InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; return true


<s> assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; if ( InVT . getSizeInBits ( ) > <NUM_LIT> ) { assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Scale = VT . getScalarSizeInBits ( ) / InVT . getScalarSizeInBits ( ) ; In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , VT . getSizeInBits ( ) / Scale ) ) ; InVT = In . getValueType ( ) ; } if ( VT . getVectorNumElements ( ) == InVT . getVectorNumElements ( ) ) return DAG . getNode ( Signed ? <STR_LIT>


<s> return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) || ( TARGET_E500_DOUBLE && mode ==


<s> uint64_t <ISA_LIT>FrameLowering :: getTOCSaveOffset ( ) const { return


<s> const MCExpr * EVal ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Percent : { unsigned RegNo ; int64_t IntVal ; if ( MatchRegisterName ( RegNo , IntVal ) ) return Error ( S , <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : case AsmToken :: Dollar : case AsmToken :: Exclaim : case AsmToken :: Tilde : if ( ! ParseExpression ( EVal ) ) break ; LLVM_FALLTHROUGH ; default : return Error ( S , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( TLSSym , S , E , is<ISA_LIT>64 ( ) ) ) ; } if ( ! TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal


<s> static bool mt_pass_in_stack ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ) { return ( ( ( type ) != <NUM_LIT> && ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ||


<s> static bool mips_cfun_has_inflexible_gp_ref_p ( void ) { if ( crtl -> has_nonlocal_goto ) return true ; if ( TARGET_ABICALLS_PIC2 ) { if ( ! TARGET_EXPLICIT_RELOCS ) return true ; if ( crtl -> profile ) return true ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return true ; } return mips_find_gp_ref ( & cfun -> machine -> has_inflexible_gp_insn_p


<s> return ( __mmask16 ) __builtin_ia32_kunpckhi ( ( __mmask16 ) __A , ( __mmask16 )


<s> break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgArea ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . isExtInLoc ( ) ) Offset += <NUM_LIT> - ValSize ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! IsVarArg ) return Chain ; unsigned ArgOffset = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgArea + Subtarget -> getStackPointerBias ( ) ) ; SmallVector < SDValue , <NUM_LIT> > OutChains ; for ( ; ArgOffset < <NUM_LIT> * <NUM_LIT> ; ArgOffset += <NUM_LIT> ) { unsigned VReg = MF . addLiveIn ( <STR_LIT> + ArgOffset / <NUM_LIT> , & <STR_LIT> ) ; SDValue VArg = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , ArgOffset + ArgArea , true ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; OutChains . push_back ( DAG . getStore ( Chain , DL , VArg , DAG . getFrameIndex ( FI , PtrVT ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! OutChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutChains ) ; return


<s> void <ISA_LIT>InstPrinter :: printPSRFlag ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { auto V = MI -> getOperand ( OpNo ) . getImm ( ) ; ListSeparator LS ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O <<


<s> progname = <STR_LIT> ; gcc_init_libintl ( ) ; diagnostic_initialize ( global_dc , <NUM_LIT> ) ; if ( atexit ( mkoffload_cleanup ) != <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; const char * host_compiler = getenv ( <STR_LIT> ) ; if ( ! host_compiler ) fatal_error ( input_location , <STR_LIT> ) ; const char * target_driver_name = GCC_INSTALL_NAME ; char * target_compiler = find_target_compiler ( target_driver_name ) ; if ( target_compiler == NULL ) fatal_error ( input_location , <STR_LIT> , target_driver_name ) ; expandargv ( & argc , & argv ) ; for ( int i = <NUM_LIT> ; i < argc ; i ++ ) { if ( startswith ( argv [ i ] , STR ) ) { if ( strcmp ( argv [ i ] + strlen ( STR ) , <STR_LIT> ) == <NUM_LIT> ) offload_abi = OFFLOAD_ABI_LP64 ; else if ( strcmp ( argv [ i ] + strlen ( STR ) , <STR_LIT> ) == <NUM_LIT> ) offload_abi = OFFLOAD_ABI_ILP32 ; else fatal_error ( input_location , <STR_LIT> STR ) ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) save_temps = true ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) verbose = true ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> && i + <NUM_LIT> < argc ) dumppfx = argv [ ++ i ] ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> && i + <NUM_LIT> < argc ) out_obj_filename = argv [ ++ i ] ; } if ( ! out_obj_filename ) fatal_error ( input_location , <STR_LIT> ) ; if ( ! dumppfx ) dumppfx = out_obj_filename ; const char * target_so_filename = prepare_target_image ( target_compiler , argc , argv ) ; const char * host_descr_filename = generate_host_descr_file ( host_compiler ) ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , host_descr_filename ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , out_obj_filename ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; char * * new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false , NULL ) ; obstack_free ( & argv_obstack , NULL ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , symbols [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack


<s> return __builtin_loongson_punpckhhw_u ( s


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , TAB , OS , Emitter


<s> return SelectionDAGISel :: runOnMachineFunction ( MF


<s> if ( MemOp . getOrdering ( ) != AtomicOrdering :: NotAtomic ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned MemBytes = MemOp . getSize ( ) ; if ( MemBytes != <NUM_LIT> ) return false ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy . isVector ( ) ) return false ; unsigned DstSize = DstTy . getSizeInBits ( ) ; if ( DstSize != <NUM_LIT> ) return false ; auto ImmFn = selectAddrModeXRO ( I . getOperand ( <NUM_LIT> ) , MemBytes ) ; if ( ! ImmFn ) return false ; MachineIRBuilder MIB ( I ) ; const RegisterBank & RB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned Opc = RB . getID ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; auto LoadMI = MIB . buildInstr ( Opc , { DstReg } ,


<s> for ( auto & IT : Out ) delete [ ] IT . second ; for ( auto & IT : In ) delete [ ]


<s> unsigned createJumpTableUId ( ) { return JumpTableUId


<s> const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return - <NUM_LIT> ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_NEGATIVE ( * r ) || REAL_VALUE_ISNAN ( * r ) || REAL_VALUE_ISINF ( * r ) || ! real_isinteger ( r , SFmode ) ) return - <NUM_LIT> ; HOST_WIDE_INT hwint = exact_log2 ( real_to_integer ( r ) ) ; if ( ! IN_RANGE ( hwint , <NUM_LIT> , <NUM_LIT> ) ) return - <NUM_LIT> ; return


<s> bool nds32_ls_333_p ( rtx rt , rtx ra , rtx imm , machine_mode mode ) { if ( REGNO_REG_CLASS ( REGNO ( rt ) ) == LOW_REGS && REGNO_REG_CLASS ( REGNO ( ra ) ) == LOW_REGS ) { if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return satisfies_constraint_Iu05 ( imm ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT>

) return satisfies_constraint_Iu04 ( imm ) ;


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { MachineLocation Location ; assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI ->

getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> vld1q_lane_s8 ( const int8_t * __a , int8x16_t __b , const int __c ) { return ( int8x16_t ) __builtin_neon_vld1_lanev16qi ( ( const __builtin_neon_qi * )


<s> if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) || isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ) return SDValue ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( Subtarget . hasAVX512 ( ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getParent ( ) -> getParent ( ) -> getTarget (


<s> const SDValue & TruncInput = Arg . getOperand ( <NUM_LIT> ) ; if ( TruncInput . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( TruncInput . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == Arg . getValueType ( ) ) { Arg = TruncInput . getOperand ( <NUM_LIT> ) ; continue ; } } break ; } int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { Register VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! VR . isVirtual ( ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex (


<s> else if ( ! timode_p ) { for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( general_scalar_to_vector_candidate_p ( insn , cand_mode [ i ] ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) , i == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; bitmap_set_bit ( & candidates [ i ] , INSN_UID ( insn ) ) ; break ; } } } if ( timode_p ) timode_remove_non_convertible_regs ( & candidates [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( ! bitmap_empty_p ( & candidates [ i ] ) ) break ; else if ( i == <NUM_LIT> && dump_file ) fprintf ( dump_file , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) while ( ! bitmap_empty_p ( & candidates [ i ] ) ) { unsigned uid = bitmap_first_set_bit ( & candidates [ i ] ) ; scalar_chain * chain ; if ( cand_mode [ i ] == TImode ) chain = new timode_scalar_chain ; else chain = new general_scalar_chain ( cand_mode [ i ] , cand_vmode [ i ] ) ; chain -> build ( & candidates [ i ] , uid ) ; if ( chain -> compute_convert_gain ( ) > <NUM_LIT> ) converted_insns += chain -> convert ( ) ; else if ( dump_file ) fprintf ( dump_file , <STR_LIT> , chain -> chain_id ) ; delete chain ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , converted_insns ) ; for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) bitmap_release ( & candidates [ i ] ) ; bitmap_obstack_release ( NULL ) ; df_process_deferred_rescans ( ) ; if ( converted_insns ) { if ( crtl -> stack_alignment_needed < <NUM_LIT> ) crtl -> stack_alignment_needed = <NUM_LIT> ; if ( crtl -> stack_alignment_estimated < <NUM_LIT> ) crtl -> stack_alignment_estimated = <NUM_LIT> ; crtl -> stack_realign_needed = INCOMING_STACK_BOUNDARY < crtl -> stack_alignment_estimated ; crtl -> stack_realign_tried = crtl -> stack_realign_needed ; crtl -> stack_realign_processed = true ; if ( ! crtl -> drap_reg ) { rtx drap_rtx = targetm . calls . get_drap_rtx ( ) ; gcc_assert ( ( stack_realign_drap != <NUM_LIT> ) == ( drap_rtx != NULL ) ) ; if ( drap_rtx != NULL ) { crtl -> args . internal_arg_pointer = drap_rtx ; fixup_tail_calls ( ) ; } } if ( TARGET_64BIT ) for ( tree

parm = DECL_ARGUMENTS ( current_function_decl ) ;


<s> if ( Register == <STR_LIT> ) Register = <STR_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return


<s> if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . hasMuxedUnits ( ) && LastMI -> mayLoadOrStore ( ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo ( ) ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls = <NUM_LIT> ; return


<s> return Parser . getContext ( ) . getAsmInfo ( ) -> getAssemblerDialect


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , isN64


<s> bool isVSRpEvenRegNumber ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) && ( ( getImm


<s> if ( DestVT == <STR_LIT> ) { unsigned Reg64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( ResultReg ) . addImm ( <STR_LIT> ) ; ResultReg = Reg64 ; } return


<s> unsigned MaxElt ; SDValue ShuffleVec ; int WindowBase ; int WindowScale ; bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) { } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) { SmallestEltTy = SrcEltTy ; } } unsigned ResMultiplier = VT . getVectorElementType ( ) . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT .


<s> void addUImm7Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> unsigned Ra = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return


<s> if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( ! TARGET_MIPS16 && can_create_pseudo_p ( ) ) ) ) { base = mips_force_temporary ( dest ,


<s> return ( __m256d ) __builtin_ia32_sqrtpd256 ( (


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result )


<s> return ( float32x2_t ) __builtin_neon_vabdfv2sf


<s> switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case


<s> assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm ) ) return false ; if ( ! isRegElgibleForForwarding ( * RegMO , DefMI , MI , KillDefMI ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . ChangeToRegister ( RegMO -> getReg ( ) , false , false , RegMO -> isKill ( ) ) ; if ( ImmMO -> isImm ( ) ) { MI . getOperand ( III . ZeroIsSpecialOrig ) . ChangeToImmediate ( Imm ) ; } else { if ( DefMI . getOpcode ( ) ==

<STR_LIT> ) ImmMO -> setTargetFlags ( <STR_LIT> ) ;


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v


<s> case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FMA : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCEIL : case TargetOpcode :: G_FFLOOR : case TargetOpcode :: G_FNEARBYINT : case TargetOpcode :: G_FNEG : case TargetOpcode ::


<s> return ( __m512i ) __builtin_ia32_loaddquqi512_mask ( ( __v64qi * ) __P , ( __v64qi ) _mm512_setzero_hi (


<s> SMLoc getAlignmentLoc ( ) const { assert ( Kind ==


<s> } virtual void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const LLVM_OVERRIDE { llvm_unreachable ( <STR_LIT> ) ; } virtual bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const LLVM_OVERRIDE ; virtual MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const LLVM_OVERRIDE { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const LLVM_OVERRIDE { return false ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT>


<s> if ( get<ISA_LIT>Subtarget ( ) . hasISEL ( ) ) { addPass ( & EarlyIfConverterID ) ; return true


<s> return ( uint64x2_t ) __builtin_aarch64_ld1v2di ( ( const __builtin_aarch64_simd_di *


<s> return ( __m128 ) __builtin_ia32_rndscaless_mask_round ( ( __v4sf ) __A , ( __v4sf ) __B , __imm , ( __v4sf ) _mm_setzero_ps ( ) , (


<s> case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; break ; } } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt , <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ) ) return false ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true


<s> unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ; if ( CByte && CByte -> getZExtValue ( ) == <NUM_LIT> ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> ,


<s> static SDValue memsetStore ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , uint64_t ByteVal , uint64_t Size , unsigned Align , MachinePointerInfo DstPtrInfo ) { uint64_t StoreVal = ByteVal ; for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) StoreVal |= ByteVal << ( I


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , Parser ( _Parser ) , STI ( sti ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { auto & <ISA_LIT>Target = getThe<ISA_LIT>Target ( ) ; TargetRegistry :: RegisterMCAsmBackend ( <ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmInfo ( <ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( <ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( <ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( <ISA_LIT>Target , createELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis (


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > W ( getTheARM64_32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > V ( getThe<ISA_LIT>_32Target (


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain .


<s> auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg


<s> if ( ! TARGET_PAIRED_FLOAT ) return <NUM_LIT> ; paired_emit_vector_compare ( rcode , dest , op1 , op2


<s> if ( ret != cost ) { const char * dep ; switch ( dep_type ) { default : dep = <STR_LIT> ; break ; case REG_DEP_TRUE : dep = <STR_LIT> ; break ; case REG_DEP_OUTPUT : dep = <STR_LIT> ; break ; case REG_DEP_ANTI : dep = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> <STR_LIT> , ret , cost ,


<s> static bool isVectorPredicate ( MachineInstr * MI ) { return MI -> findRegisterDefOperandIdx ( <STR_LIT> ) !=


<s> unsigned char <ISA_LIT>Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return <STR_LIT> ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( <NUM_LIT> ) ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT> ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return


<s> SDValue RHS = VecIns [ Slot + <NUM_LIT> ] ; VecIns . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ) ; } <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , VecIns . back ( ) , CC , Mask , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return V ; } } if ( Op . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> BinOp ; if ( SDValue Match = DAG . matchBinOpReduction ( Op . getNode ( ) , BinOp , { <STR_LIT> } ) ) { <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , Match , CC , Mask , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return V


<s> } if ( ! Value ) { Value = adjustFixupValue ( Fixup , Value ) ; return ; } unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset <= DataSize && <STR_LIT> ) ; assert ( Value % <NUM_LIT>


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>_64Disassembler


<s> else if ( unsigned_p ) return arm_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else return arm_lookup_simd_builtin_type ( mode ,


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , TAB , OS , Emitter , RelaxAll , true ) ; return create<ISA_LIT>ELFStreamer ( Ctx , TAB , OS ,


<s> if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT> )


<s> static bool mips_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM ||


<s> static SDValue LowerSVEIntrinsicIndex ( SDNode * N , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Op2 . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) )


<s> V2 = peekThroughBitcasts ( V2 ) ; assert ( ( VT . getSizeInBits ( ) % Size ) == <NUM_LIT> && <STR_LIT> ) ; unsigned EltSizeInBits = VT . getSizeInBits ( ) / Size ; APInt UndefSrcElts [ <NUM_LIT> ] ; SmallVector < APInt , <NUM_LIT> > SrcEltBits [ <NUM_LIT> ] ; bool IsSrcConstant [ <NUM_LIT> ] = { getTargetConstantBitsFromNode ( V1 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) , getTargetConstantBitsFromNode ( V2 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { assert ( isUndefOrZero ( M ) && <STR_LIT> ) ; if ( SM_SentinelUndef == M ) KnownUndef . setBit ( i ) ; if ( SM_SentinelZero == M ) KnownZero . setBit ( i ) ; continue ; } unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { KnownUndef . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( ) ) KnownUndef . setBit ( i ) ; else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand (

<NUM_LIT> ) ) ) KnownZero . setBit ( i ) ;


<s> LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = & * MI ; } -- MI ; if ( LastIT ) { unsigned PredReg =


<s> assert ( m_pPLT != NULL && <STR_LIT> ) ; return *


<s> if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , Mnemonic ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , Mnemonic ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . ParseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus


<s> } else { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; Input = DAG . getBitcast ( <STR_LIT> , Input ) ; OpLHS = DAG . getBitcast ( <STR_LIT> , OpLHS ) ; } } else { int MaskElt = getPFIDLane ( ID , RHSID ) ; assert ( MaskElt >= <NUM_LIT> && <STR_LIT> ) ; ExtLane = MaskElt < <NUM_LIT> ? MaskElt : ( MaskElt - <NUM_LIT> ) ; Input = MaskElt < <NUM_LIT> ? V1 : V2 ; if ( VT == <STR_LIT> ) { Input = DAG . getBitcast ( <STR_LIT> , Input ) ; OpLHS = DAG . getBitcast ( <STR_LIT> , OpLHS ) ; } } SDValue Ext = DAG . getNode ( <STR_LIT> , dl , Input . getValueType ( ) . getVectorElementType ( ) , Input , DAG . getVectorIdxConstant ( ExtLane , dl ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , dl , Input . getValueType ( ) , OpLHS , Ext , DAG . getVectorIdxConstant ( RHSID & <NUM_LIT> , dl ) ) ; return DAG . getBitcast ( VT , Ins ) ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( LHSID , V1 , V2 , PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( RHSID , V1 , V2 , PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ; if ( EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) OpLHS = WidenVector ( OpLHS , DAG ) ; SDValue Lane = DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ; return DAG . getNode ( Opcode , dl , VT , OpLHS , Lane ) ; } case OP_VEXT1


<s> if ( MO . isDef ( ) ) { Defs . set ( Reg ) ; if ( ! LPR . contains ( MO . getReg ( ) ) ) MO . setIsDead ( ) ; } else Uses . push_back ( & MO ) ; } for ( auto * MO : Uses ) if ( Defs . test ( getFPReg ( * MO ) ) || ! LPR . contains (

MO -> getReg ( ) ) ) MO -> setIsKill ( ) ;


<s> int MemOp = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOp != - <NUM_LIT> ) MemOp += <STR_LIT> ( Desc ) ; for ( int OpIdx = <NUM_LIT> ; OpIdx < OpEnd ; ++ OpIdx ) { if ( OpIdx == MemOp ) { OpIdx += ( <STR_LIT> - <NUM_LIT> ) ; continue ; } auto & Op = DefMI -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; visitRegister ( C , Op . getReg ( ) , Domain , Worklist ) ; } for ( auto & UseMI : MRI -> use_nodbg_instructions ( CurReg ) ) { if ( usedAsAddr ( UseMI , CurReg , TII ) ) { C . setAllIllegal ( ) ; continue ; } encloseInstr ( C , & UseMI ) ; for ( auto & DefOp : UseMI . defs ( ) ) { if ( ! DefOp . isReg ( ) ) continue ; Register DefReg = DefOp .


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128ToCall ( Op , DAG ,


<s> if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { assert ( Type == MachO :: <ISA_LIT>_RELOC_VANILLA && <STR_LIT> ) ; const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO


<s> if ( sparc_check_64 ( operands [ <NUM_LIT> ] , insn ) <= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } strcpy ( asm_code , opcode ) ; if ( which_alternative != <NUM_LIT> ) return strcat


<s> bool hasXOP ( ) const { return HasXOP


<s> bool isMemDisp20 ( MemoryKind MemKind , RegisterKind RegKind ) const { return isMem ( MemKind , RegKind ) && inRange ( Mem .


<s> unsigned getShiftRight16Imm ( const MachineInstr & MI , unsigned


<s> MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . add ( Src2 ) ; if ( BitSize <= <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( - <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2 ) . addImm ( - <NUM_LIT> ) ; } } else if ( BinOpcode ) BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . add ( Src2 ) ; else if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize )


<s> bool SelectAddrMode2ShOp ( SDValue N , SDValue & Base ,


<s> virtual const <ISA_LIT>BaseInstrInfo * getInstrInfo ( ) const { return InstrInfo


<s> MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) )


<s> const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr

:: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ;


<s> static void registerAsmPrinter ( AsmPrinterCtorFn F ) { AsmPrinterCtor =


<s> case MEK_CHERI_CAP : llvm_unreachable ( <STR_LIT> ) ; break ; case MEK_CALL_HI16 : case MEK_CALL_LO16 : case MEK_GOT : case MEK_GOT_CALL : case MEK_GOT_DISP : case MEK_GOT_HI16 : case MEK_GOT_LO16 : case MEK_GOT_OFST : case MEK_GOT_PAGE : case MEK_GPREL : case MEK_CAPTABLEREL : case MEK_HI : case MEK_HIGHER : case MEK_HIGHEST : case MEK_LO : case MEK_NEG : case MEK_PCREL_HI16 : case MEK_PCREL_LO16 : case MEK_CAPCALL11 : case MEK_CAPCALL20 : case MEK_CAPCALL_LO16 : case MEK_CAPCALL_HI16 : case MEK_CAPTABLE11 : case MEK_CAPTABLE20 : case MEK_CAPTABLE_HI16


<s> constrainSelectedInstRegOperands ( UndefMI , TII , TRI , RBI ) ; return constrainSelectedInstRegOperands ( InsMI , TII , TRI , RBI ) ; } ; switch ( DstTy . getElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : return BuildFn ( <STR_LIT> ) ; case <NUM_LIT> : return BuildFn ( <STR_LIT> ) ; case <NUM_LIT> : return BuildFn ( <STR_LIT> ) ; default : return false


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( Registry ) ; initialize<ISA_LIT>LoadStoreOptPass ( Registry


<s> machine_mode tmode = VOIDmode ; if ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) != void_type_node ) { tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ nopnds ++ ] = target ; } else target = const0_rtx ; FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { if ( arg == error_mark_node ) return const0_rtx ; rtx opnd ; insn_op = & insn_data [ icode ] . operand [ nopnds ] ; if ( TREE_CODE ( arg ) == ADDR_EXPR && MEM_P ( DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ) ) opnd = DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ; else opnd = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( opnd , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { if ( ! CONST_INT_P ( opnd ) ) error ( <STR_LIT> , nopnds ) ; else error ( <STR_LIT> <STR_LIT> , nopnds ) ; return const0_rtx ; } opnd = copy_to_mode_reg ( insn_op -> mode , opnd ) ; } if ( ! void_func && nopnds == <NUM_LIT> && ! strcmp ( insn_op -> constraint , <STR_LIT> ) && insn_op -> mode == tmode && REG_P ( opnd ) && ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( opnd , tmode ) ) target = op [ <NUM_LIT> ] = opnd ; op [ nopnds ++ ]


<s> if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm << <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand (


<s> unsigned Opcode = MBBI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned AddrOpNo = <NUM_LIT> ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; uint64_t Offset = StackSize + MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . getImm ( ) ; unsigned NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -=


<s> if ( Bits == <NUM_LIT> ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; return


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getInfo < <ISA_LIT>FunctionInfo >

( ) -> isSplitCSR ( ) ) return CSR_iOS_CXX_TLS_ViaCopy_SaveList ;


<s> for ( p = mips_cpu_info_table ; p -> name != <NUM_LIT> ; p ++ ) if ( p -> isa == isa ) return p ; return


<s> uint64_t SupportedMask = <NUM_LIT> ; if ( ( ImmVal & SupportedMask ) != ImmVal ) { SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask


<s> static __inline qword si_cgtb ( qword a , qword b ) { return ( ( qword ) ( vec_cmpgt ( ( vec_char16 ) ( a ) , (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo ( )


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShOps ) ; MVT EltVT = VT . getVectorElementType ( ) ; EVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT . getSizeInBits (


<s> void \ init_section ( ) \ { \ if ( in_section != in_init ) \ { \ in_section = in_init ;

\ fprintf ( asm_out_file , <STR_LIT> , INIT_SECTION_ASM_OP ) ; \ } \ }


<s> return ( ( REG_P ( recog_data . operand [ <NUM_LIT> ] ) && REGNO ( recog_data . operand [ <NUM_LIT> ] ) == reg ) || ( recog_data . n_operands

== <NUM_LIT> && REG_P ( recog_data . operand [ <NUM_LIT> ] ) && REGNO ( recog_data . operand [ <NUM_LIT> ] ) == reg ) ) ;


<s> if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( IsStrict ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT> ) ; } } } return SDValue ( )


<s> uint64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned NewOpcode ; if ( And . RegSize == <NUM_LIT> ) NewOpcode = <STR_LIT> ; else { NewOpcode = <STR_LIT> ; Start &= <NUM_LIT> ; End &= <NUM_LIT> ; } MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( NewOpcode ) ) . addOperand ( Dest ) . addReg ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return finishConvertToThreeAddress ( MI , MIB , LV ) ; } } return


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; APFloat RealVal ( <NUM_LIT> ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Real ) ) { if ( Parser . getTok ( ) . getString ( ) != <STR_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> unsigned FrameSize = MFI . getStackSize ( ) ; Align StackAlign = LRI -> hasStackRealignment ( MF ) ? MFI . getMaxAlign ( ) : getStackAlign ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name , bool is64BitReg ) { if ( Name . equals ( <STR_LIT> ) ) return <STR_LIT> ; int CC ; CC = matchCPURegisterName ( Name ) ; if ( CC != - <NUM_LIT> ) return matchRegisterByNumber ( CC , is64BitReg ?


<s> return Subtarget . isMClass ( ) && MF . getFunction


<s> return :: isUNPCKL_v_undef_Mask ( N -> getMask ( ) , N -> getValueType


<s> EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) || ( VT == <STR_LIT> && Subtarget . useAVX512Regs ( ) ) ) { if ( VT == <STR_LIT> && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; unsigned Opcode = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , VT , Op ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; if ( VT == <STR_LIT> ) { SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Undef , Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> return SelectAddrRI12 ( Op , Addr , Base , Disp


<s> static unsigned getDUPLANEOp ( EVT EltType ) { if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> )


<s> auto * Const0L = dyn_cast < ConstantSDNode > ( Op0L -> getOperand ( <NUM_LIT> ) ) ; auto * Const1L = dyn_cast < ConstantSDNode > ( Op1L -> getOperand ( <NUM_LIT> ) ) ; auto * Const0H = dyn_cast < ConstantSDNode > ( Op0H -> getOperand ( <NUM_LIT> ) ) ; auto * Const1H = dyn_cast < ConstantSDNode > ( Op1H -> getOperand ( <NUM_LIT> ) ) ; if ( ! Const0L || ! Const1L || ! Const0H || ! Const1H ) return SDValue ( ) ; unsigned Idx0L = Const0L -> getZExtValue ( ) , Idx1L = Const1L -> getZExtValue ( ) , Idx0H = Const0H -> getZExtValue ( ) , Idx1H = Const1H -> getZExtValue ( ) ; if ( Idx0L > Idx1L ) std :: swap ( Idx0L , Idx1L ) ; if ( Idx0H > Idx1H ) std :: swap ( Idx0H , Idx1H ) ; if ( Idx0L > Idx0H ) { std :: swap ( Idx0L , Idx0H ) ; std :: swap ( Idx1L , Idx1H ) ; } if ( Idx0L != <NUM_LIT> * i || Idx1L != <NUM_LIT> * i + <NUM_LIT> || Idx0H != <NUM_LIT> * i + <NUM_LIT> || Idx1H != <NUM_LIT> * i + <NUM_LIT> ) return SDValue ( ) ; if ( ! Mul ) { Mul = Op0L -> getOperand ( <NUM_LIT> ) ; if ( Mul -> getOpcode ( ) != <STR_LIT> || Mul . getValueType ( ) . getVectorNumElements ( ) != <NUM_LIT> * e ) return SDValue ( ) ; } if ( Mul != Op0L -> getOperand ( <NUM_LIT> ) || Mul != Op1L -> getOperand ( <NUM_LIT> ) || Mul != Op0H -> getOperand ( <NUM_LIT> ) || Mul != Op1H -> getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } ShrinkMode Mode ; if ( ! canReduceVMulWidth ( Mul . getNode ( ) , DAG , Mode ) || Mode ==


<s> bool <ISA_LIT>TargetLowering :: shouldFoldShiftPairToMask ( const SDNode *


<s> return ( __mmask64 ) __builtin_ia32_cmpb512_mask ( ( __v64qi ) __X , ( __v64qi )


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo (


<s> EVT OpVT = X . getValueType ( ) ; unsigned OpSize = OpVT . getSizeInBits ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpSize < <NUM_LIT> || isNullConstant ( Y ) ) return SDValue ( ) ; EVT VT = SetCC -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( SetCC ) ; if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . hasAVX2 ( ) ) ) { EVT VecVT = OpSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT , Y ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VecVT , VecX , VecY ) ; SDValue MovMsk = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) && get_attr_length ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) { asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , ASSEMBLER_DIALECT ? <STR_LIT> : <STR_LIT> , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , label ) ; output_asm_insn ( <STR_LIT> , & op0 ) ; fprintf ( asm_out_file , <STR_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , label ) ; return <STR_LIT> ; } case <NUM_LIT> : return logic ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( ! TARGET_RELAX ) { int label = lf ++ ; gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ) ; asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , ASSEMBLER_DIALECT ? <STR_LIT> : <STR_LIT> , label ) ; fprintf ( asm_out_file , <STR_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; fprintf ( asm_out_file ,


<s> EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue Symbol = withTargetFlags ( Op , callTF , DAG ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . push_back ( Symbol ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>SJLJEHLabel ( ) const { const DataLayout * DL = TM . getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; return OutContext . GetOrCreateSymbol ( Name . str


<s> } } } if ( CC == <STR_LIT> ) { return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Y . getOperand ( <NUM_LIT> ) ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y . getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . getNode ( ) -> hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = NewSub . getValue ( EFLAGS . getResNo ( ) ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewEFLAGS ) ; } } if ( CC == <STR_LIT> ) { return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , Y . getOperand ( <NUM_LIT> ) ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y . getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . getNode ( ) -> hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = NewSub . getValue ( EFLAGS . getResNo ( ) ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , NewEFLAGS ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) ||

! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ;


<s> break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ <NUM_LIT> ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ <NUM_LIT> ] , tmp ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , gen_lowpart ( GET_MODE ( operands [ <NUM_LIT> ] ) , dest ) ) ; return ; } switch ( imode ) { case E_V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpFunc = gen_loongson_pcmpgtb ; break ; case E_V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack =


<s> if ( const Function * F = dyn_cast < Function > ( CV ) ) { MCSymbolXCOFF * FSym = cast < MCSymbolXCOFF > ( getSymbol ( F ) ) ; if ( ! FSym -> hasContainingCsect ( ) ) { const XCOFF :: StorageClass SC = F -> isDeclaration ( ) ? TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) : XCOFF :: C_HIDEXT ; MCSectionXCOFF * Csect = OutStreamer -> getContext ( ) . getXCOFFSection ( FSym -> getName ( ) , XCOFF :: XMC_DS , F -> isDeclaration ( ) ? XCOFF :: XTY_ER : XCOFF :: XTY_SD , SC , SectionKind :: getData ( ) ) ; FSym -> setContainingCsect ( Csect ) ; } return MCSymbolRefExpr :: create ( FSym -> getContainingCsect ( ) -> getQualNameSymbol ( )


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Disable<ISA_LIT>Unaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; } else { return false ; } } if ( VT == <STR_LIT> )


<s> assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; } unsigned StackID = TargetStackID :: Default ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc =


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget <

<ISA_LIT>Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ;


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm8s4Operand ( const MachineInstr * MI , int OpNum ) { const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm * <NUM_LIT> ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm * <NUM_LIT> ; O <<


<s> StringRef Name ; auto DB = <STR_LIT> ( Val ) ; Name = DB ? DB -> Name : <STR_LIT> ; if ( ! Name . empty ( ) ) O << Name ; else O << <STR_LIT>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> if ( LT . first != <NUM_LIT> && MTy . isVector ( ) && MTy . getVectorNumElements ( ) < ValVTy -> getNumElements ( ) ) { Ty = VectorType :: get ( ValVTy -> getElementType ( ) , MTy . getVectorNumElements ( ) ) ; auto * SubCondTy = VectorType :: get ( cast < VectorType > ( CondTy ) -> getElementType ( ) , MTy . getVectorNumElements ( ) ) ; MinMaxCost = getMinMaxCost ( Ty , SubCondTy , IsUnsigned ) ; MinMaxCost *= LT . first - <NUM_LIT> ; NumVecElts = MTy . getVectorNumElements ( ) ; } if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; if ( ST -> hasSSE41 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE41CostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; if ( ST -> hasSSE2 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE2CostTblNoPairWise , ISD , MTy ) ) return MinMaxCost + Entry -> Cost ; unsigned ScalarSize = ValTy -> getScalarSizeInBits ( ) ; if ( ! isPowerOf2_32 ( ValVTy -> getNumElements ( ) ) || ScalarSize != MTy . getScalarSizeInBits ( ) ) return BaseT :: getMinMaxReductionCost ( ValTy , CondTy , IsPairwise , IsUnsigned , CostKind ) ; while ( NumVecElts > <NUM_LIT> ) { unsigned Size = NumVecElts * ScalarSize ; NumVecElts /= <NUM_LIT> ; if ( Size > <NUM_LIT> ) { auto * SubTy = VectorType :: get ( ValVTy -> getElementType ( ) , NumVecElts ) ; MinMaxCost += getShuffleCost ( TTI :: SK_ExtractSubvector , Ty , NumVecElts , SubTy ) ; Ty = SubTy ; } else if ( Size == <NUM_LIT> ) { VectorType * ShufTy ; if ( ValTy -> isFloatingPointTy ( ) ) ShufTy = VectorType :: get ( Type :: getDoubleTy ( ValTy -> getContext ( ) ) , <NUM_LIT> ) ; else ShufTy = VectorType :: get ( Type :: getInt64Ty ( ValTy -> getContext ( ) ) , <NUM_LIT> ) ; MinMaxCost += getShuffleCost ( TTI :: SK_PermuteSingleSrc , ShufTy , <NUM_LIT> , nullptr ) ; } else if ( Size == <NUM_LIT> ) { VectorType * ShufTy


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == VOIDmode ) return const0_rtx ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || * cum +

XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) return NULL_RTX ;


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res , Addr


<s> if ( isPIC ) { HiOpFlags |= <STR_LIT> ; LoOpFlags |= <STR_LIT> ; } if ( GV && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasLazyResolverStub ( GV , TM ) ) { HiOpFlags |= <STR_LIT> ; LoOpFlags |= <STR_LIT> ; if ( GV -> hasHiddenVisibility


<s> fix -> address = address ; fix -> loc = loc ; fix -> mode = mode ; fix -> fix_size = MINIPOOL_FIX_SIZE ( mode ) ; fix -> value = value ; fix -> forwards = get_attr_pool_range ( insn ) ; fix -> backwards = get_attr_neg_pool_range ( insn ) ; fix -> minipool = NULL ; gcc_assert ( fix -> forwards || fix -> backwards ) ; if ( ARM_DOUBLEWORD_ALIGN && fix -> fix_size == <NUM_LIT> ) fix -> forwards -= <NUM_LIT> ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , GET_MODE_NAME ( mode ) , INSN_UID ( insn ) , ( unsigned long ) address , - <NUM_LIT> * ( long

) fix -> backwards , ( long ) fix -> forwards ) ;


<s> if ( AddrReg == <STR_LIT> || AddrReg == <STR_LIT> ) { Register AddrTmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , AddrTmp ) ; MIB . addReg ( AddrReg ) ; MIB . addImm ( <NUM_LIT> ) ; AddrReg = AddrTmp ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( AddrTmp , false , false , true ) ; } MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; MIB . addReg ( PC , RegState :: Define ) ; MIB . addReg ( AddrReg ) ; MIB . addImm ( <NUM_LIT>


<s> unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ) Bits = countTrailingZeros (


) | __C , ( __v8hf ) _mm_setzero_ph ( ) , __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> void <ISA_LIT>ExpandPseudo :: ExpandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; const unsigned * SubReg = TM . getRegisterInfo (


<s> assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [ CPI ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) &&


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( )


<s> MCELFStreamer :: EmitLabel ( Symbol ) ; Labels . push_back (


<s> if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF .

getTarget ( ) . Options . GuaranteedTailCallOpt ) ) {


<s> return ( __mmask16 ) __builtin_ia32_vpshufbitqmb128_mask ( ( __v16qi ) __A , ( __v16qi ) __B , (


<s> for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep


<s> unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL ; } llvm_unreachable (


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) .

hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ;


<s> unsigned <ISA_LIT>TTIImpl :: getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetDarwin ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs ; Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_SELF_MODIFYING_CODE | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolAttribute ( Stubs [ i ] . second . getPointer ( ) , MCSA_IndirectSymbol ) ; const char HltInsts [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OutStreamer . EmitBytes ( StringRef ( HltInsts , <NUM_LIT> ) , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( )


<s> MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg (


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT>

) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) {


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> return ( __m256d ) __builtin_ia32_vfnmsubpd256_mask3 ( ( __v4df ) __A , ( __v4df )


<s> return ( __m256i ) __builtin_ia32_broadcasti32x2_256_mask ( ( __v4si ) __A , ( __v8si ) _mm256_undefined_si256 ( )


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( Hi ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( Hi ) ; } return ResultReg