<s> int Value = Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode ( I -> getOpcode ( ) ) : getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB ; if ( ! isPairedLdSt ( I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( Update ) ) . addOperand ( getLdStRegOp ( I ) ) . addOperand ( getLdStBaseOp ( I ) ) . addImm ( Value ) ; } else { int Scale = getMemScale ( I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( Update ) ) . addOperand ( getLdStRegOp ( I , <NUM_LIT> ) ) . addOperand ( getLdStRegOp ( I , <NUM_LIT> ) ) . addOperand ( getLdStBaseOp ( I ) ) . addImm ( Value / Scale ) ; } ( void ) MIB ; if ( IsPreIdx ) DEBUG ( dbgs ( ) << <STR_LIT> ) ; else DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Update -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> static rtx_insn * arm_call_tls_get_addr ( rtx x , rtx reg , rtx * valuep , int reloc ) { rtx label , labelno , sum ; gcc_assert ( reloc != TLS_DESCSEQ ) ; start_sequence ( ) ; labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg


<s> switch ( Desc . TSFlags & <STR_LIT> ) { default : Addr += <NUM_LIT> ; break ; case <STR_LIT> : Addr += <NUM_LIT> ; break ; case <STR_LIT> : Addr += STI -> getFeatureBits ( ) [ <STR_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; break ; } unsigned AddrMode = ( TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { default : return None ; case <STR_LIT> : return evaluateMemOpAddrForAddrMode_i12 ( Inst , Desc , OpIndex , Addr ) ; case <STR_LIT> : return evaluateMemOpAddrForAddrMode3 ( Inst , Desc , OpIndex , Addr ) ; case <STR_LIT> : return evaluateMemOpAddrForAddrMode5 ( Inst , Desc , OpIndex , Addr ) ; case <STR_LIT> : return evaluateMemOpAddrForAddrMode5FP16 ( Inst , Desc , OpIndex , Addr ) ; case <STR_LIT> : return evaluateMemOpAddrForAddrModeT2_i8s4 ( Inst , Desc


unsigned int __X , unsigned int __Y , unsigned int * __P ) {


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , bool HasAVX2 , bool V2IsSplat ) { SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M ) ; return :: isUNPCKHMask ( M , N -> getValueType (


<s> if ( createMemLibcall ( MIRBuilder , MRI , MI ) == LegalizerHelper :: UnableToLegalize ) return false ; MI . eraseFromParent ( ) ; return true ; case <STR_LIT> : { MachineInstr * Trap = MIRBuilder . buildInstr ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Trap , TII , TRI , RBI ) ; } case <STR_LIT> : { MachinePointerInfo MPO ; auto Tmp = MIRBuilder . buildLoad ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; MIRBuilder . buildStore ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_ADD , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SUB , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_MUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> unsigned Directive = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) { const InstrItineraryData * II = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II ,


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask , APInt & UndefElts ) { SmallVector < APInt , <NUM_LIT> >


<s> static bool bbIsJumpedOver ( MachineBasicBlock * MBB ) { if ( MBB -> pred_size ( ) != <NUM_LIT> || MBB -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * Succ = * MBB -> succ_begin ( ) ; MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; MachineInstr * PredMI = & Pred -> back ( ) ; if ( PredMI -> getOpcode ( ) == <STR_LIT> ) return PredMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) == Succ ; return false


<s> if ( NextI == MergeMI ) ++ NextI ; unsigned Opc = I -> getOpcode ( ) ; bool IsScaled = ! TII -> isUnscaledLdSt ( Opc ) ; int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /= <NUM_LIT> ; } DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith (

* MergeMI ) ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ;


<s> bool isMemWithGRPMM16Base ( ) const { return isMem ( ) && getMemBase


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M ) ; return :: isUNPCKH_v_undef_Mask ( M , N ->


<s> unsigned Opc = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { if ( Opc == <STR_LIT> ) { RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; return N ; } if ( Opc == <STR_LIT> && isNullConstant ( RHS ) ) { if ( AN -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent && AN -> getSyncScopeID ( ) == SyncScope :: System ) { SDValue NewChain = emitLockedStackOp ( DAG , Subtarget , Chain , DL ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ; } SDValue NewChain = DAG . getNode ( <STR_LIT> ,


<s> static DecodeStatus DecodeACRegsDSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler :: Success


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; <STR_LIT> CC = <STR_LIT> ; <STR_LIT> ExtraCC = <STR_LIT> ; if ( optimizeSelect ( SI ) ) return true ; if ( foldXALUIntrinsic ( CC , I , Cond ) ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; } else if ( isa < CmpInst > ( Cond ) && cast < CmpInst > ( Cond ) -> hasOneUse ( ) && isValueAvailable ( Cond ) ) { const auto * Cmp = cast < CmpInst > ( Cond ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate ( Cmp ) ; const Value * FoldSelect = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_FALSE : FoldSelect = SI -> getFalseValue ( ) ; break ; case CmpInst :: FCMP_TRUE : FoldSelect = SI -> getTrueValue ( ) ; break ; } if ( FoldSelect ) { unsigned SrcReg = getRegForValue ( FoldSelect ) ; if ( ! SrcReg ) return false ; unsigned UseReg = lookUpRegForValue ( SI ) ; if ( UseReg ) MRI . clearKillFlags ( UseReg ) ; updateValueMap ( I , SrcReg ) ; return true ; } if ( ! emitCmp ( Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> getOperand ( <NUM_LIT> ) , Cmp -> isUnsigned ( ) ) ) return false ; CC = getCompareCC ( Predicate ) ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_UEQ : ExtraCC = <STR_LIT> ; CC = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : ExtraCC = <STR_LIT> ; CC = <STR_LIT> ; break ; } assert ( ( CC != <STR_LIT> ) && <STR_LIT> ) ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) ) ; } unsigned Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; bool Src1IsKill = hasTrivialKill ( SI -> getTrueValue ( ) ) ; unsigned Src2Reg = getRegForValue ( SI -> getFalseValue ( )


<s> if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx


<s> if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT>


<s> } else if ( poss . equals_lower ( <STR_LIT> ) ) { Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; } if ( Variant != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; } break ; } if ( getParser ( ) . parseExpression ( EVal ) ) return true ; if ( Variant != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex (


<s> if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned RegNum = Tok . getIntVal ( ) ; if ( RegNum != <NUM_LIT> ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * op = <STR_LIT> ( <STR_LIT> , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( op )


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) != SET ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , SET_SRC


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> unsigned RegNum = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNum == <NUM_LIT> )


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < <STR_LIT> > & Ins ,


<s> SDLoc dl ( Op ) ; MVT ResVT = Op . getSimpleValueType ( ) ; unsigned NumOfOperands = Op . getNumOperands ( ) ; assert ( isPowerOf2_32 ( NumOfOperands ) && <STR_LIT> ) ; if ( NumOfOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getScalarType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op .


<s> static DecodeStatus DecodeGRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo *


<s> return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } assert ( Section && <STR_LIT> )


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier


<s> address += get_attr_length ( insn ) ; if ( ( table = is_jump_table ( insn ) ) != NULL ) { address += get_jump_table_size ( table ) ; insn = table ; } } } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && GET_CODE ( fix -> insn ) == BARRIER ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( GET_CODE ( ftmp -> insn ) == BARRIER ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address


<s> auto I = MIRBuilder . buildInstr ( <STR_LIT> , { DefReg } , { SrcReg , SrcReg } ) . addImm ( InvCC ) ; constrainSelectedInstRegOperands ( * I , TII , TRI , RBI ) ; return & *


<s> FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { mips_rewrite_small_data_1 ( & XEXP ( * loc , <NUM_LIT> ) , SYMBOL_CONTEXT_MEM ) ; iter . skip_subrtxes (


<s> int _U_Qfne ( long double a , long double b ) { return ( _U_Qfcmp ( a , b


<s> else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( ) , <NUM_LIT> ) ; MIB . addReg ( Reg ) ; } else return false ; } else { unsigned CallReg = <NUM_LIT> ; if ( Symbol ) { unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> ) ; CallReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , CallReg ) . addReg ( ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( Addr . getGlobalValue ( ) ) CallReg = materializeGV ( Addr . getGlobalValue ( ) ) ; else if ( Addr . getReg ( ) ) CallReg = Addr . getReg ( ) ; if ( ! CallReg ) return false ; const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; CallReg = constrainOperandRegClass ( II , CallReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( CallReg ) ; } for ( auto Reg : CLI . OutRegs ) MIB .


<s> if ( ! isDoubleSpacedVectorIndexed ( ) ) return


<s> static Optional < uint64_t > evaluateMemOpAddrForAddrModeT1_s ( const MCInst & Inst , const MCInstrDesc & Desc , unsigned MemOpIndex , uint64_t Addr ) { return evaluateMemOpAddrForAddrModeT2_pc ( Inst , Desc , MemOpIndex


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl


<s> SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , InFlag ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; InFlag = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; } MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = <STR_LIT> ; Callee . setNode ( nullptr ) ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isELFv2ABI && ! hasNest ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , PtrVT ) ) ; } if ( Callee . getNode ( ) ) { Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; } if ( isTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isPatchPoint ) { setUsesTOCBasePtr ( DAG


<s> <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1


<s> return isMemDisp12 ( ADDR64Reg , BDXMem


<s> switch ( mode ) { case E_SFmode : index = <NUM_LIT> ; break ; case E_DFmode : index = <NUM_LIT> ; break ; case E_XFmode : index = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> fp_load [ index ] , ix86_cost -> fp_store [ index ] ) ; return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( regclass ) ) { int index = sse_store_index ( mode ) ; if ( index == - <NUM_LIT> ) return <NUM_LIT> ; if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> sse_load [ index ] , ix86_cost -> sse_store [ index ] ) ; return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( regclass ) ) { int


<s> enum calling_abi abi = ix86_abi ; if ( fntype == NULL_TREE || TYPE_ATTRIBUTES ( fntype ) == NULL_TREE ) return abi ; if ( abi == SYSV_ABI && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { static int warned ; if ( TARGET_X32 && ! warned ) { error ( <STR_LIT> ) ; warned =


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR && ! Outs . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [


<s> unsigned llvm :: getBLRCallOpcode ( const MachineFunction & MF ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > (

) . hardenSlsBlr ( ) ) return <STR_LIT> ;


<s> if ( TT . getArch ( ) == Triple :: x86_64 ) return llvm :: make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return llvm :: make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSFreeBSD ( ) ) return llvm :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) ) return llvm :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return llvm :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile >


<s> vmlaq_s16 ( int16x8_t a , int16x8_t b , int16x8_t c ) { int16x8_t result


<s> return ( __mmask16 ) __builtin_ia32_cvtb2mask128 ( (


<s> static SDValue combineBrCond ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal


<s> uint64_t TruncBits = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , ShlImm ) ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; TruncBits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return


<s> else Size = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Size != <NUM_LIT> && <STR_LIT> ) ; switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } } if ( Opc == TargetOpcode :: G_ZEXT || Opc == TargetOpcode :: G_ANYEXT ) { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( Size != <NUM_LIT> && <STR_LIT> ) ; switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } } if ( Opc != TargetOpcode :: G_AND ) return <STR_LIT> ; Optional < uint64_t > MaybeAndMask = getImmedFromMO ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! MaybeAndMask ) return <STR_LIT> ; uint64_t AndMask = * MaybeAndMask ; switch ( AndMask ) { default : return <STR_LIT> ; case <NUM_LIT> : return ! IsLoadStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return ! IsLoadStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT>


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <


<s> static __inline uint8x16_t vaesimcq_u8 ( uint8x16_t data ) { return __builtin_aarch64_crypto_aesimcv16qi_uu ( data )


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> :


<s> return ( __m256d ) __builtin_ia32_loadupd256_mask ( ( const double * ) __P , ( __v4df ) __W , (


<s> return ( __m128i ) __builtin_ia32_pmovsdb128_mask ( ( __v4si ) __A , (


<s> if ( cfun -> machine -> load_label_num_insns == <NUM_LIT> ) { mips_process_load_label ( pc_rtx )


<s> if ( mips_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : if ( msa_p ) { if ( mips_signed_immediate_p ( INTVAL ( addr . offset ) , <NUM_LIT> , mips_ldst_scaled_shift ( mode ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } if ( TARGET_MIPS16 && ! mips16_unextended_reference_p ( mode , addr . reg , UINTVAL ( addr . offset ) ) ) return factor * <NUM_LIT> ; return factor ; case ADDRESS_LO_SUM : return msa_p ? <NUM_LIT> : TARGET_MIPS16 ? factor * <NUM_LIT> : factor ; case


<s> return ( unsigned long long ) __builtin_sh_media_MMULHI_WL ( ( v4hi ) mm ,


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) ,

AI -> getPointerOperand ( ) , AI -> getAlign ( ) ) ;


<s> e . rotate_inputs_left ( <NUM_LIT> , <NUM_LIT> ) ; machine_mode mode = e . vector_mode ( <NUM_LIT> ) ; insn_code icode = code_for_dot_prod ( UNSPEC_USDOT , mode ) ; return e . use_exact_insn ( icode


<s> } const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & Fn ) ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; I += <NUM_LIT> ) { if ( ! Fn . getRegInfo ( ) . isPhysRegModified ( CSRegs [ I ] ) ) continue ; if ( MFI -> getStackRegionToHandleCSR ( CSRegs [ I ] ) == this ) Result += this -> Scale ; } return Result


<s> static bool DisassembleMiscFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { if ( MemBarrierInstr ( insn ) ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice

( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( Addr , DemandedMask , Known , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; return


<s> SDValue SetCC = Select -> getOperand ( <NUM_LIT> ) ; if ( SetCC . getOpcode ( ) != <STR_LIT> ) return false ; <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( CC != <STR_LIT> ) return false ; SDValue SelectOp1 = Select -> getOperand ( <NUM_LIT> ) ; SDValue SelectOp2 = Select -> getOperand ( <NUM_LIT> ) ; if ( ! ( SelectOp2 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SelectOp2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) && SelectOp2 . getOperand ( <NUM_LIT> ) == SelectOp1 ) ) return false ; if ( SetCC . getOperand ( <NUM_LIT> ) != SelectOp1 ) return false ; if ( ! ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) || <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) return false ; if ( SelectOp1 . getOpcode ( ) != <STR_LIT> ) return false ; Op0 = SelectOp1 . getOperand


<s> BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; unsigned CPELogAlign = getCPELogAlign ( U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockLogAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockLogAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber


<s> void relaxInstruction ( const MCInst & , llvm :: MCInst & ) const { llvm_unreachable ( <STR_LIT>


<s> if ( VT . isScalableVector ( ) ) return EVT :: getVectorVT

( C , <STR_LIT> , VT . getVectorElementCount ( ) ) ;


<s> static rtx mips16_local_alias ( rtx func ) { if ( mips16_local_aliases == NULL ) mips16_local_aliases = hash_map < rtx , rtx , local_alias_traits > :: create_ggc ( <NUM_LIT> ) ; bool existed ; rtx * slot = & mips16_local_aliases -> get_or_insert ( func , & existed ) ; gcc_assert ( slot != NULL ) ; if ( ! existed


<s> if ( ! warned && warn_psabi ) { warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , computed / BITS_PER_UNIT ) ; } } return false


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> || C -> getZExtValue ( ) == <NUM_LIT> || ( Subtarget . is64Bit ( ) && C -> getZExtValue ( ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode >


<s> void <ISA_LIT>InstPrinter :: printAddrMode2OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs << markup ( <STR_LIT> ) ; return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printRegName ( O , MO1 .


<s> bool NoImplicitFloatOps = F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool isSoftFloat = Subtarget . useSoftFloat ( ) ; assert ( ! ( isSoftFloat && NoImplicitFloatOps ) && <STR_LIT> ) ; if ( isSoftFloat || NoImplicitFloatOps || ! Subtarget . hasSSE1 ( ) ) return None ; static const MCPhysReg XMMArgRegs64Bit


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF &&

SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ;


<s> if ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) return <NUM_LIT> ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) &&


<s> unsigned postOffset ( unsigned LogAlign = <NUM_LIT> ) const { unsigned PO = Offset + Size ; unsigned Align = <NUM_LIT> << LogAlign ; return ( PO + Align - <NUM_LIT> ) /


<s> static DecodeStatus DecodeVecShiftR32ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> ,


<s> bool is<ISA_LIT>1 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>1


<s> bool <ISA_LIT>ELFFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , I . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , I . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } <STR_LIT> RestoreGPRs = ZFI ->


<s> return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * getTargetMachine ( ) . getInstrInfo ( ) , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> RegisterTarget < Triple :: cpu0el , true > Y ( getThe<ISA_LIT>elTarget ( ) ,


<s> else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ; if ( Opc != <STR_LIT> ) { SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getMemIntrinsicNode ( Opc , DL , DAG . getVTList ( <STR_LIT> ) , Ops , array_lengthof ( Ops ) , DstTy , MMO ) ; return std :: make_pair ( FIST , StackSlot ) ; } else { SDValue ftol = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , Value ) ; SDValue eax = DAG . getCopyFromReg ( ftol , DL ,

<STR_LIT> , <STR_LIT> , ftol . getValue ( <NUM_LIT> ) ) ;


<s> assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { seenFloatArg |= VA . getLocVT ( ) . isFloatingPoint ( ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; if ( isVarArg ) { SDValue SetCR ( DAG . getMachineNode ( seenFloatArg ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> ) , <NUM_LIT> ) ; RegsToPass . push_back ( std :: make_pair ( unsigned ( <STR_LIT> ) , SetCR ) ) ; } SDValue InFlag


<s> if ( ST . isThumb ( ) ) Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isThumb ( ) || ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else if ( ST . isAAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> } if ( ( GET_CODE ( x ) == PRE_MODIFY && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) || GET_CODE ( x ) == POST_INC || GET_CODE

( x ) == PRE_DEC ) x = XEXP ( x , <NUM_LIT> ) ;


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; OW -> Write8 ( <NUM_LIT> ) ; break ; } return true


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Ext64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Ext64 , FIdx } ; SDValue Store = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; SDValue Ld = DAG . getLoad ( <STR_LIT> , dl , Store , FIdx

, NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> return <STR_LIT> ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NumBytesToStore << <STR_LIT> ) ; break ; } return


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT . first *


<s> else emit_insn ( gen_move_gpsi ( dest , src ) ) ; return ; } if ( regno == HI_REGNUM ) { if ( REG_P ( dest ) ) { mips_emit_move ( temp , src ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( gen_rtx_REG ( TImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( DImode , LO_REGNUM ) ) ) ; else emit_insn ( gen_mthisi_di ( gen_rtx_REG ( DImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( SImode , LO_REGNUM ) ) ) ; } else { if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( temp , gen_rtx_REG ( TImode , MD_REG_FIRST ) ) ) ; else emit_insn ( gen_mfhisi_di ( temp , gen_rtx_REG ( DImode , MD_REG_FIRST ) ) ) ; mips_emit_move ( dest , temp ) ; } } else if ( mips_direct_save_slot_move_p ( regno , mem , mem == src ) ) mips_emit_move ( dest , src ) ; else { gcc_assert ( ! reg_overlap_mentioned_p ( dest ,


<s> case <STR_LIT> : Reloc = <STR_LIT> ; break ; } } MachineRelocation R ; if ( MO . isGlobal ( ) ) { R = MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getGlobal ( ) , <NUM_LIT> , isa < Function > ( MO . getGlobal ( ) ) ) ; } else if ( MO . isSymbol ( ) ) { R = MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getSymbolName ( ) , <NUM_LIT> ) ; } else if ( MO . isCPI ( ) ) { R = MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } else { assert ( MO . isJTI ( ) ) ; R = MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && Reloc != <STR_LIT> ) { assert ( MovePCtoLROffset && <STR_LIT> ) ; R . setConstantVal ( - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ) ; } MCE . addRelocation ( R ) ; } else if ( MO . isMBB ( ) ) { unsigned Reloc = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Reloc = <STR_LIT> ; else Reloc = <STR_LIT> ; MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getMBB ( ) ) ) ; } else


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue PSHUFB = lowerVectorShuffleWithPSHUFB ( DL , <STR_LIT> , Mask ,

V1 , V2 , Subtarget , DAG ) ) return PSHUFB ;


<s> case <NUM_LIT> : return UNSPEC_CDOT180 ; case <NUM_LIT> : return UNSPEC_CDOT270 ; default : gcc_unreachable


<s> return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: SExt : return <ISA_LIT>SelectSExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: UIToFP : return <ISA_LIT>SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast


<s> if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; TS . setUsesMicro<ISA_LIT> ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16


<s> const MCExpr * <ISA_LIT>ELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { MCSymbol * Sym = TM . getSymbol ( GV ,


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo


<s> return Op ; } } if ( <STR_LIT> ( SVOp , false ) || <STR_LIT> ( SVOp , false ) || <STR_LIT> ( SVOp , false ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) ) return Op ; SmallVector < int , <NUM_LIT> > PermMask ; SVOp -> getMask ( PermMask ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource /


<s> void setFormalArgInfo ( unsigned Size , bool HasByval ) { IncomingArgSize = Size


<s> IInSlot = Res . first ; } if ( LastInstInFunction || ! SafeInSlot ( * IInSlot , * I ) ) { MachineBasicBlock :: instr_iterator Iit = I -> getIterator ( ) ; if ( std :: next ( Iit ) == FI -> end ( ) || std :: next ( Iit ) -> getOpcode ( ) != <STR_LIT> ) { Changed = true ; TII -> insertNop ( * ( I -> getParent ( ) ) , std :: next ( I ) , I -> getDebugLoc ( ) ) -> bundleWithPred ( ) ; NumInsertedNops ++ ; } } } } return Changed


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qidi


<s> return decodeRegisterClass ( Inst , RegNo , XRegs


<s> if ( ( N1 . isUndef ( ) || DAG . ComputeNumSignBits ( VV1 ) > BitSize ) && ( N2 . isUndef ( ) || DAG . ComputeNumSignBits ( VV2 ) > BitSize ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } if ( Subtarget . hasSSE41 ( ) || PackSVT == <STR_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( BitSize * <NUM_LIT> , BitSize ) ; if ( ( N1 . isUndef ( ) || DAG . MaskedValueIsZero ( VV1 , ZeroMask ) ) && ( N2 . isUndef ( ) || DAG . MaskedValueIsZero ( VV2 , ZeroMask ) ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } return false ; } ; SmallVector < int , <NUM_LIT> > BinaryMask ; createPackShuffleMask ( VT , BinaryMask , false ) ; if ( isTargetShuffleEquivalent ( TargetMask , BinaryMask ) ) if ( MatchPACK ( V1 , V2 ) ) return true ; SmallVector < int , <NUM_LIT> > UnaryMask ; createPackShuffleMask ( VT , UnaryMask , true ) ; if ( isTargetShuffleEquivalent ( TargetMask , UnaryMask ) ) if ( MatchPACK ( V1


<s> StringRef Name = Parser . getTok ( ) . getString ( ) ; SMLoc ExtLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } for ( const auto & Extension : Extensions ) { if ( Extension . Name != Name ) continue ; if ( ! Extension . Features ) report_fatal_error ( <STR_LIT> + Name ) ; if ( ( getAvailableFeatures ( ) & Extension . ArchCheck ) != Extension . ArchCheck ) { Error ( ExtLoc , <STR_LIT> + Name + <STR_LIT> <STR_LIT> ) ; return false


<s> case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : if ( simpleCC ) * simpleCC = <STR_LIT> ; if ( reverseCC ) * reverseCC = <STR_LIT> ; return true ; case <STR_LIT> : if ( simpleCC ) * simpleCC = <STR_LIT> ; if ( reverseCC ) * reverseCC = <STR_LIT> ; return true ; case <STR_LIT> : if ( simpleCC ) * simpleCC = <STR_LIT> ; if ( reverseCC ) * reverseCC


<s> __builtin_ia32_scatterpfdps ( ( __mmask16 ) <NUM_LIT> , ( __v16si ) index , ( int const *


<s> if ( isZeroShuffle ( SVOp ) ) return getZeroVector ( VT , Subtarget , DAG , dl ) ; if ( SVOp -> isSplat ( ) ) { SDValue Broadcast = LowerVectorBroadcast ( Op , DAG ) ; if ( Broadcast . getNode ( ) ) return Broadcast ; } SDValue NewOp = LowerVectorIntExtend ( Op , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) { MVT NewVT = NewOp . getValueType ( ) . getSimpleVT ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG


<s> static inline __ev64_opaque__ __internal_ev_mwhgssfaa ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> int count ; for ( count = <NUM_LIT> , reg = FIRST_PSEUDO_REGISTER ; reg -- != <NUM_LIT> ; ) { if ( reg == PR_REG ? pr_live : interrupt_handler ? ( ( df_regs_ever_live_p ( reg ) || ( call_really_used_regs [ reg ] && ( ! fixed_regs [ reg ] || reg == MACH_REG || reg == MACL_REG || reg == PIC_OFFSET_TABLE_REGNUM ) && has_call ) ) && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM && reg != RETURN_ADDRESS_POINTER_REGNUM && reg != T_REG && reg != GBR_REG && reg != FPSCR_MODES_REG && reg != FPSCR_STAT_REG && ( reg != FPSCR_REG || TARGET_FPU_ANY ) ) : ( ( false ) || ( df_regs_ever_live_p ( reg ) && ( ( ! call_really_used_regs [ reg ] && ! ( reg != PIC_OFFSET_TABLE_REGNUM && fixed_regs [ reg ] && call_used_regs [ reg ] ) ) || ( trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY ) ) ) || ( crtl -> calls_eh_return && ( reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg

== EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || reg == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ) ) || ( ( reg == MACL_REG || reg == MACH_REG ) && df_regs_ever_live_p ( reg ) && sh_cfun_attr_renesas_p ( ) ) ) ) {


<s> LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args .


<s> unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ; if ( Tmp > ( SrcBits - VTBits ) ) return Tmp - ( SrcBits - VTBits ) ; return <NUM_LIT> ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; const APInt & ShiftVal = Op . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; if ( ShiftVal . uge ( Tmp ) ) return <NUM_LIT> ; return Tmp - ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = Op . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ShiftVal . uge ( VTBits - <NUM_LIT> ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op , DAG ) ; case <STR_LIT> : return LowerBSWAP ( Op , DAG ) ; case


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo (


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( SrcReg ) ; unsigned DstReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode ) , DstReg ) . addReg ( SrcReg ) ; MI . eraseFromParent ( ) ; return


<s> SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; if ( ! TM . getDataSections ( ) || GV -> hasSection ( ) ) { OutStreamer -> emitLabel ( EmittedInitSym ) ; } llvm :: for_each ( GOAliasMap [ GV ] , [


<s> static SDValue PerformFSUBCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasSSE3orAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isHorizontalBinOp ( LHS , RHS , false ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue ( )


<s> bool OptimizeLEAPass :: chooseBestLEA ( const SmallVectorImpl < MachineInstr * > & List , const MachineInstr & MI , MachineInstr * & LEA , int64_t & AddrDispShift , int & Dist ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags , MI . getOpcode ( ) ) + <STR_LIT> ( Desc ) ; LEA = nullptr ; for ( auto DefMI : List ) { int64_t AddrDispShiftTemp = <NUM_LIT> ; if ( ! isSimilarMemOp ( MI , MemOpNo , * DefMI , <NUM_LIT> , AddrDispShiftTemp ) ) continue ; if ( ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) ) continue ; if ( TII -> getRegClass ( Desc , MemOpNo + <STR_LIT> , TRI , * MF ) != MRI -> getRegClass ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; int DistTemp = calcInstrDist ( * DefMI , MI ) ; assert ( DistTemp != <NUM_LIT> && <STR_LIT> ) ; if ( DistTemp > <NUM_LIT> || LEA == nullptr ) { if ( LEA != nullptr && ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) && isInt < <NUM_LIT> > ( AddrDispShift ) ) continue ; LEA = DefMI ; AddrDispShift = AddrDispShiftTemp ; Dist = DistTemp ; } if ( DistTemp < <NUM_LIT> ) break ; } return LEA


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( <STR_LIT> ( N , N -> getNumOperands ( ) ) ) if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( N ) ) return CFP -> getValueAPF ( ) . isNegZero ( ) ; return


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC ) ) ; SDValue Glue = emitCmp ( DAG , DL , C ) ; return emitSETCC ( DAG , DL , Glue , C . CCValid ,


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( )


<s> __v8hu result ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; shmask = rshift <= shmax ; result = vec_vsrh ( ( __v8hu ) __A , rshift ) ; result = vec_sel ( shmask , result ,


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void * New ) { llvm_report_error ( <STR_LIT>


<s> if ( Idx >= ( int ) NumElems ) { unsigned Opc = V2 . getOpcode ( ) ; if ( Opc == <STR_LIT> || <STR_LIT> ( V2 . getNode ( ) ) ) continue ; if ( Opc != <STR_LIT> || ! isZeroNode ( V2 . getOperand ( Idx - NumElems ) ) ) return false ; } else if ( Idx >= <NUM_LIT> ) { unsigned Opc = V1 . getOpcode ( )


<s> assert ( GISel && <STR_LIT> ) ; return GISel -> getMachineLegalizer


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const auto & Desc = Info -> get ( Inst . getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Inst . getNumOperands ( ) ; i != e ; i


<s> bool <ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) >=


<s> emit_insn ( gen_cstoredi_neg ( tracker , gen_rtx_NE ( CCmode , cc , const0_rtx ) , cc ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; return


<s> if ( get<ISA_LIT>Subtarget ( ) . allowMixed16_32 ( ) ) { addPass ( create<ISA_LIT>ModuleISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>16ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; } else { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; } return


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs ) != ValNo ; Align OrigAlign = ArgFlags . getNonZeroOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == Align ( <NUM_LIT> ) ) ; bool isVectorFloat = <ISA_LIT>State -> WasOriginalArgVectorFloat ( ValNo ) ; if ( ValVT == <STR_LIT> && isVectorFloat ) { if ( ArgFlags . isSplit ( ) ) { Reg = State . AllocateReg ( FloatVectorIntRegs ) ; if ( Reg == <STR_LIT> ) State . AllocateReg ( <STR_LIT> ) ; else if ( Reg == <NUM_LIT> ) State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( IntRegs ) ; } } else if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs ) ; State . AllocateReg ( IntRegs ) ; } else { Reg = State . AllocateReg ( F64Regs ) ; unsigned Reg2 = State . AllocateReg ( IntRegs ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getStoreSize ( ) , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return


<s> const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < Desc . getNumOperands ( ) ; ++ OpNum ) { if ( Inst . getOperand ( OpNum ) . isImm ( ) && Desc . OpInfo [

OpNum ] . OperandType == MCOI :: OPERAND_PCREL ) {


<s> ParseSubtargetFeatures ( CPU , FS ) ; return *


<s> static __inline vec_int4 spu_mulh ( vec_short8 a , vec_short8 b ) { return ( ( vec_int4 ) ( si_mpyh ( ( qword ) ( a )


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerSPLAT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT>


<s> enum rtx_code code = GET_CODE ( op ) ; if ( code == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( op ) ) < GET_MODE_SIZE ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) ) ) { unsigned int index = SUBREG_BYTE ( op ) ; if ( index < <NUM_LIT> ) index += <NUM_LIT> ; else index -= <NUM_LIT> ; SUBREG_BYTE ( op ) = index ; } const char * fmt = GET_RTX_FORMAT ( code ) ; int i , j


<s> SDLoc DL ( Op ) ; if ( <STR_LIT> ( CCVal ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( CCVal -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , CCVal . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( OFCC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) ,


<s> MachineFunction * F = BB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( Subtarget . isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = Subtarget . is64Bit ( ) ? Subtarget . getRegisterInfo ( ) -> getDarwinTLSCallPreservedMask ( ) : Subtarget . getRegisterInfo ( ) -> getCallPreservedMask ( * F , CallingConv :: C ) ; if ( Subtarget . is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( ! isPositionIndependent ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB ,


<s> MCAsmParserExtension :: Initialize ( Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( )


<s> StackOffset Offset ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = { MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) , <STR_LIT> } ; } else if ( Tagged ) { StackOffset SPOffset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; } else { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; } if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) )


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg +=


<s> const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> .


<s> unsigned RangeEnd = Last ; if ( Base == <STR_LIT> ) { if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } } if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } else if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return


<s> MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) return <NUM_LIT> ; if ( ( ~ ZImmVal < <NUM_LIT> ) || <STR_LIT> ( ZImmVal )


<s> const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast <


<s> if ( Mnemonic -> getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , IdVal , S , E ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } const AsmToken & Tok1 = Parser . getTok ( ) ; if ( Tok1 . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const AsmToken & Tok2 = Parser . getTok ( ) ; if ( Tok2 . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) .


<s> const bool WasThumb = isThumb ( StartInfo ) ; if ( ! EndInfo || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer -> EmitAssemblerFlag ( WasThumb ? MCAF_Code16 :


<s> if ( ! Subtarget . is<ISA_LIT>1 ( ) || NVT != <STR_LIT> ) return NULL ; LoadSDNode * LN = cast < LoadSDNode > ( N ) ; if ( LN -> getExtensionType ( ) != <STR_LIT> || LN -> getAddressingMode ( ) != <STR_LIT> ) return NULL ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset0 , Offset1 , Base ; if ( ! SelectAddr ( N , N1 , Offset0 , Base ) || N1 . getValueType ( ) != <STR_LIT> ) return NULL ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Offset0 ) ) Offset1 = CurDAG -> getTargetConstant ( C -> getSExtValue ( ) + <NUM_LIT> , <STR_LIT> ) ; else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( Offset0 ) ) Offset1 = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , <STR_LIT> , CP -> getAlignment ( ) , CP -> getOffset ( ) + <NUM_LIT> , CP -> getTargetFlags ( ) ) ; else return NULL ; if ( TM . getTargetData ( ) -> isBigEndian ( ) ) std :: swap ( Offset0 , Offset1 ) ; SDNode * LD0 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> ,


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI -> getRegisterInfo ( ) ; Register Reg = MO . getReg ( ) ; unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; if ( ! RI -> regsOverlap ( RegToPrint , Reg ) ) return true ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint ,


<s> CCVals [ CC ] = CCV ; if ( ! CCV -> hasName ( ) ) CCV -> setName ( ( Twine ( getCCName ( CC ) ) +

<STR_LIT> + utostr ( CCAssignments [ CC ] ++ ) ) . str ( ) ) ;


<s> if ( non_prefixed == NON_PREFIXED_X ) return false ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ; return ( iform == INSN_FORM_BASE_REG || iform == INSN_FORM_D || iform == INSN_FORM_DS


<s> __inline__ static void sh_media_PUTCFG ( unsigned long long mm , int s , unsigned long long mw ) { __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( mm ) , <STR_LIT> (


<s> RHSMaxIdx = NumEltsOut / NumEltsIn + RHSMinIdx ; SToVRHS = getSToVPermuted ( SToVRHS , DAG , Subtarget ) ; if ( SToVRHS . getValueType ( ) != RHS . getValueType ( ) ) SToVRHS = DAG . getBitcast ( RHS . getValueType ( ) , SToVRHS ) ; RHS = SToVRHS ; } fixupShuffleMaskForPermutedSToV ( ShuffV , LHSMaxIdx , RHSMinIdx , RHSMaxIdx , HalfVec , ValidLaneWidth , Subtarget ) ; Res = DAG . getVectorShuffle ( SVN -> getValueType ( <NUM_LIT> ) , dl , LHS , RHS , ShuffV ) ; if ( ! isa < ShuffleVectorSDNode > ( Res ) ) return Res ; Mask = cast < ShuffleVectorSDNode > ( Res ) -> getMask ( ) ; } SDValue TheSplat = IsLittleEndian ? RHS : LHS ; if ( ! isSplatBV ( TheSplat ) ) return Res ; if ( ! isAlternatingShuffMask ( Mask , NumElts ) ) return Res ; if ( IsLittleEndian ) { if ( Mask [ <NUM_LIT> ] < NumElts ) for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i ] = ( ShuffV [ i - <NUM_LIT> ] + NumElts ) ; else for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i ] = ( ShuffV [ i + <NUM_LIT> ] + NumElts ) ; } else { if ( Mask [ <NUM_LIT> ] < NumElts ) for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i ] = ShuffV [ i + <NUM_LIT> ] - NumElts ; else for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT>

) ShuffV [ i ] = ShuffV [ i - <NUM_LIT> ] - NumElts ;


<s> static SDValue LowerVectorIntUnary ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; assert ( EltVT == Src . getSimpleValueType ( ) . getVectorElementType ( ) && <STR_LIT> ) ; SDLoc dl (


<s> void addVectorListOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> switch ( mode ) { case E_QImode : return QUAL_TYPE ( QI ) ; case E_HImode : return QUAL_TYPE ( HI ) ; case E_SImode : return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ; case E_TImode : return QUAL_TYPE ( TI ) ; case E_OImode : return arm_simd_intOI_type_node ; case E_EImode : return arm_simd_intEI_type_node ; case E_CImode : return arm_simd_intCI_type_node ; case E_XImode : return arm_simd_intXI_type_node ; case E_HFmode : return arm_fp16_type_node ; case E_SFmode : return float_type_node ; case E_DFmode : return double_type_node


<s> int getVarArgsFrameOffset ( ) const { return


<s> if ( slotno == - <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_ARCH32 ) { if ( ( slotno + ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ) > SPARC_INT_ARG_MAX ) return ( SPARC_INT_ARG_MAX - slotno ) * UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> || slotno == SPARC_FP_ARG_MAX - <NUM_LIT> ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && ! ( TARGET_FPU && named ) ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - <NUM_LIT> ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode


<s> const std :: array < std :: array < unsigned , <NUM_LIT> > , <NUM_LIT> > OpcTable { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT>


<s> case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerExtendedLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMUL_LOHI ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static __inline qword si_clgt ( qword a , qword b ) { return ( ( qword ) ( vec_cmpgt ( ( vec_uint4 ) ( a


<s> MVT SadVT = SAD . getSimpleValueType ( ) ; if ( Stages > <NUM_LIT> ) { unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT ) , Mask ) ; SAD = DAG . getNode ( <STR_LIT> , DL , SadVT , SAD , Shuffle ) ; } } MVT Type = Extract -> getSimpleValueType ( <NUM_LIT> ) ; unsigned TypeSizeInBits = Type .


<s> EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; Register DestReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , DestReg ) . addReg (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI ,


<s> VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N , Subtarget ) ) { return false ; } if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , None ) ) return false ; } else { if ( Alignment < <NUM_LIT> ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , Align ( <NUM_LIT> ) ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LD -> getMemoryVT ( ) == <STR_LIT> && LD -> getExtensionType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = <STR_LIT> ; return true


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo (


<s> return __extension__ ( __m128d ) { __F ,


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( ! isPositionIndependent ( ) ) { if ( TLOF -> IsGlobalInSmallSection ( GO


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> if ( mode == BLKmode ) return int_size_in_bytes (


<s> auto & DL = I . getModule ( ) -> getDataLayout ( ) ; switch ( Intrinsic ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) ->


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; recordSled ( CurSled , MI , SledKind :: FUNCTION_ENTER


<s> return ( __m256i ) __builtin_ia32_pmovsxbw256 (


<s> StringRef getPassName ( ) const override { return


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm5 ( SDValue N


<s> SDLoc DL ( Node ) ; EVT PtrVT = Addr . getValueType ( ) ; if ( Opcode == <STR_LIT> ) if ( auto * Const = dyn_cast < ConstantSDNode > ( Src2 ) ) { Opcode = <STR_LIT> ; Src2 = DAG . getConstant ( - Const -> getSExtValue ( ) , DL , Src2 . getValueType ( ) ) ; } SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , DL , WideVT ) , BitShift ) ; if ( Opcode != <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( <NUM_LIT> - BitSize , DL , WideVT ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( uint32_t ( - <NUM_LIT> ) >> BitSize , DL , WideVT ) ) ; SDVTList VTList = DAG . getVTList ( WideVT ,


<s> int16x8_t result = vcombine_s16 ( a , vcreate_s16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b )


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getEHHandlerRegister (


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) ) ; return true


<s> SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( N -> getOpcode ( ) , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; return TLI . expandABS ( N , DAG


<s> if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return

Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> for ( RegDomain D : LegalDstDomainList ) LegalDstDomains . set (


<s> void <ISA_LIT>Subtarget :: initializeProperties ( ) { switch ( ARMProcFamily ) { case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; break ; case ExynosM1 : PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Vulcan : MaxInterleaveFactor = <NUM_LIT> ; break ; case CortexA35 : break ; case CortexA53 :


<s> MachineInstrBuilder MIB = emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , LowOpcode , Size , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ;

++ I ) MIB . add ( MI . getOperand ( I ) ) ;


<s> MachineInstr * Start = LoLoop . Start ; MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; bool IsDo = Start -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = LoLoop . getStartOpcode ( ) ; MachineOperand & Count = LoLoop . getCount ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , InsertPt -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Count


<s> static DecodeStatus DecodeSxtwImm3 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { unsigned ImmVal = Imm |


<s> if ( Subtarget . hasAVX ( ) && N -> getOpcode ( ) == <STR_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( TLI . isTypeLegal ( VT ) && TLI . isTypeLegal ( In . getValueType ( ) ) ) if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG ,


<s> case <STR_LIT> : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( )


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ==


<s> unsigned postKnownBits ( unsigned LogAlign


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS )


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetGlobalAddress (


<s> for ( <STR_LIT> Iter = SeqLs . begin ( ) ; Iter != SeqLs . end ( ) ; ++ Iter ) Iter


<s> func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( abi_reg ) { rtvec v = gen_rtvec ( <NUM_LIT> , func , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( <NUM_LIT> , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr =


<s> static __inline qword si_rotqbybi ( qword a , qword count ) { vec_uchar16 left , right ; left = vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ; right = vec_sub ( vec_splat_u8 ( <NUM_LIT> )


<s> if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) .

addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( <NUM_LIT> , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , gsr ) ,


<s> int regno ; for ( regno = first_reg ; regno < SPARC_INT_ARG_MAX ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( <NUM_LIT> ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , SPARC_INCOMING_INT_ARG_FIRST + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT (


<s> case <STR_LIT> : hiOpc = <STR_LIT> ; break ; case <STR_LIT> : hasChain = true ; break ; case <STR_LIT> : hiOpc = <STR_LIT> ; break ; case <STR_LIT> : hasChain = true ; break ; } SDValue Lo ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( hasChain ) { Lo = DAG . getNode ( Op . getOpcode ( ) , dl , VTs , Src1Lo , Src2Lo , Op . getOperand ( <NUM_LIT> ) ) ; } else { Lo = DAG . getNode ( Op . getOpcode ( ) , dl , VTs , Src1Lo , Src2Lo ) ; } SDValue Hi = DAG . getNode ( hiOpc , dl , VTs , Src1Hi , Src2Hi , Lo . getValue ( <NUM_LIT> ) ) ; SDValue Carry = Hi . getValue ( <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; SDValue Ops [ <NUM_LIT> ] =