<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool <ISA_LIT>AsmParser :: parseCondCode ( OperandVector & Operands , bool invertCondCode ) { SMLoc S = getLoc ( ) ; const AsmToken & Tok = getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Cond = Tok . getString ( ) ; <STR_LIT> CC = parseCondCodeString ( Cond ) ; if ( CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; Lex ( )


<s> const MCExpr * Expr ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( )


<s> static inline int multcosts ( rtx x ATTRIBUTE_UNUSED ) { if ( sh_multcost >= <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ; case


<s> return DisassembleLdStMiscFrm ( MI , Opcode , insn , NumOps ,


<s> while ( ( Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ) != Exit ) { if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp & ( SlotSize - <NUM_LIT> ) ) return ; StackDisp >>= Log2SlotSize ; assert ( ( size_t ) StackDisp < Context . MovVector . size ( ) && <STR_LIT> ) ; if ( Context . MovVector [ StackDisp ] != nullptr ) return ; Context . MovVector [ StackDisp ] = & * I ; for ( const MachineOperand & MO : I -> uses ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( RegInfo . isPhysicalRegister ( Reg ) ) UsedRegs . insert ( Reg ) ; } ++ I ; } if ( I == MBB . end ( ) || ! I -> isCall ( ) ) return ; Context . Call = & * I ; if ( ( ++ I ) -> getOpcode ( ) != FrameDestroyOpcode ) return ; auto MMI = Context . MovVector . begin ( ) , MME = Context . MovVector . end ( ) ; for ( ; MMI != MME ; ++ MMI , Context . ExpectedDist += SlotSize ) if ( * MMI == nullptr ) break ; if ( MMI == Context . MovVector . begin (


<s> static tree sh_handle_interrupt_handler_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs =


<s> unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIB ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIB ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ; auto TBL1 = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIB . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIB . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ; auto TBL2 = MIB . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) } , { RegSeq , IndexLoad -> getOperand ( <NUM_LIT> ) } ) ; constrainSelectedInstRegOperands ( * RegSeq , TII , TRI


<s> return ( __m256i ) __builtin_ia32_vgf2p8mulb_v32qi ( ( __v32qi )


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) return true ; if ( isExtendedBUILD_VECTOR ( N , DAG , false ) ) return true ; return


<s> const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , SPOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( * MBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ; MI -> eraseFromParent ( ) ; return


<s> } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraScale = <NUM_LIT> ; } else if ( is<ISA_LIT>LowRegister ( DestReg ) ) { if ( BaseReg == <STR_LIT> ) { assert ( ! isSub && <STR_LIT> ) ; CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = AddDefaultT1CC ( MIB ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } AddDefaultPred ( MIB . setMIFlags ( MIFlags ) ) ; BaseReg = DestReg ; } while ( Bytes ) { unsigned ExtraImm = std :: min (


<s> unsigned imm8 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; const FeatureBitset & FeatureBits = Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ; DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( imm8 ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( imm8 == <NUM_LIT> && pred != <NUM_LIT> && ( ( FeatureBits [ <STR_LIT> ] ) !=

<NUM_LIT> ) ) S = MCDisassembler :: SoftFail ;


<s> APFloat APF = Op0CN -> getValueAPF ( ) ; if ( APF . isPosZero ( ) ) return SignBit ; APF . clearSign ( ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APF ) ; } else { CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getLowBitsSet ( SizeInBits , SizeInBits - <NUM_LIT> ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) , <NUM_LIT> ) ; SDValue Val = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( ! isa < ConstantFPSDNode > ( Op0 ) ) Val = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; typedef <ISA_LIT>COFFMachineModuleInfo :: externals_iterator externals_iterator ; for ( externals_iterator I = COFFMMI . externals_begin ( ) , E = COFFMMI . externals_end ( ) ; I != E ; ++ I ) { OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportStorageClass ( ) ) DLLExportedFns . push_back ( getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportStorageClass ( ) ) DLLExportedGlobals . push_back ( getSymbol ( I ) ) ; for ( Module :: const_alias_iterator I = M . alias_begin ( ) , E = M . alias_end ( ) ; I != E ; ++ I ) { const GlobalValue * GV = I ; if ( ! GV -> hasDLLExportStorageClass ( ) ) continue ; while ( const GlobalAlias * A = dyn_cast < GlobalAlias > ( GV ) ) GV = A -> getAliasedGlobal ( ) ; if ( isa < Function > ( GV ) ) DLLExportedFns . push_back ( getSymbol ( I ) ) ; else if ( isa < GlobalVariable > ( GV ) ) DLLExportedGlobals . push_back ( getSymbol ( I ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetKnownWindowsMSVC ( )


<s> MachineOperand & mo = mi -> getOperand ( i ) ; if ( ! mo . isReg ( ) ) continue ; int rx = RegIndex ( mo . getReg ( ) ) ; if ( rx < <NUM_LIT>


<s> static std :: atomic < bool > FoldTablesChecked ( false ) ; if ( ! FoldTablesChecked . load ( std :: memory_order_relaxed ) ) { assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable2Addr ) , std :: end ( MemoryFoldTable2Addr ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable2Addr ) , std :: end ( MemoryFoldTable2Addr ) ) == std :: end ( MemoryFoldTable2Addr ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable0 ) , std :: end ( MemoryFoldTable0 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable0 ) , std :: end ( MemoryFoldTable0

) ) == std :: end ( MemoryFoldTable0 ) && <STR_LIT> ) ;


<s> } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { bool ICC = Name [ <NUM_LIT> ] == 'l' || Name [ <NUM_LIT> ] == 'w' ? true : false ; Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( ) , ICC , true , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { bool ICC = Name [ <NUM_LIT> ] == 'l' || Name [ <NUM_LIT> ] == 'w' ? true : false ; Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( ) , ICC , true , NameLoc , Operands ) ; } else


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB


<s> switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( VT . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( VT . getSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits ( ) ) return false ; if ( ! VT . isPow2VectorType ( ) )


<s> OperandMatchResultTy parseBDAddr32 ( OperandVector & Operands )


<s> for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs )


<s> BitGroups . erase ( I ) ; BitGroups . insert ( BitGroups . begin ( ) , BG ) ; } break ; } } for ( auto & BG : BitGroups ) { if ( ! Res ) Res = SelectRotMask64 ( BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; else Res = SelectRotMaskIns64 ( Res , BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; } if ( LateMask ) { uint64_t Mask = getZerosMask ( ) ; bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( ANDIVal , dl ) , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += selectI64ImmInstrCount ( Mask ) +


<s> return __builtin_mve_vmulltq_int_uv8hi ( __a ,


<s> case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isDeadDef ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return & * I ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumLiveDstRejs ; return nullptr ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return & * I ; } PhysRegInfo PRI = AnalyzePhysRegInBundle ( * I , <STR_LIT> , TRI ) ; if ( PRI . Read ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++


<s> __builtin_ia32_pmovsdw256mem_mask ( ( __v8hi * ) __P , (


<s> return NULL_TREE ; } else switch ( fn ) { case BUILT_IN_SQRT : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BUILTIN_RSQRT ] ; case BUILT_IN_SQRTF : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( SFmode


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine


<s> return ( __m64 ) __builtin_ia32_psrad ( ( __v2si )


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( StackAlign > <NUM_LIT> )


<s> else data_section ( ) ; } else { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && (

DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) readonly_data_section ( ) ;


<s> MCInst ITInst ; ITInst . setOpcode ( <STR_LIT> ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Mask ) ) ; Out . EmitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= <NUM_LIT> ) ; for ( const MCInst & Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI (


<s> bool i386_pe_valid_dllimport_attribute_p ( const_tree decl ) { if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; return true


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return combineExtractVectorElt ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineExtractVectorElt_SSE ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineInsertSubvector ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineSelect ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBitcast ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineCMov ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAdd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineADC ( N , DAG , DCI ) ; case <STR_LIT> : return combineMul ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAnd ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineXor ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static bool memOpAlign ( unsigned DstAlign , unsigned SrcAlign ,


<s> FBB = nullptr ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * TargetBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( HasCondBranch ) { FBB = TargetBB ; } else { TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == <STR_LIT>


<s> unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool isUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) | getUndefRegState ( isUndef ) ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; bool isUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) | getUndefRegState ( isUndef ) ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } break ; case <STR_LIT> : case <STR_LIT> : if ( ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { const TargetRegisterClass * RC = RI . getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned StoreOpc , LoadOpc ; bool Is<ISA_LIT>1 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>1 ( ) ; if ( RC == <STR_LIT> ) { LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } else { assert ( RC == <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> bool SVEIntrinsicOpts :: optimizeConvertFromSVBool ( IntrinsicInst * I ) { assert ( I -> getIntrinsicID ( ) == <STR_LIT> && <STR_LIT> ) ; if ( isa < PHINode > ( I -> getArgOperand ( <NUM_LIT> ) )


<s> } ) ) { SDValue X = OtherOp . getOperand ( <NUM_LIT> ) , Y = OtherOp . getOperand ( <NUM_LIT> ) ; FalseOp = DAG . getNode ( <STR_LIT> , DL , VT , X , FalseOp ) ; TrueOp = DAG . getNode ( <STR_LIT> , DL , VT , X , TrueOp ) ; Cmov = DAG . getNode ( <STR_LIT> , DL , VT , FalseOp , TrueOp , Cmov . getOperand ( <NUM_LIT> ) , Cmov . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Cmov , Y ) ; } FalseOp = DAG . getNode ( <STR_LIT> , DL , VT , OtherOp , FalseOp ) ; TrueOp = DAG . getNode ( <STR_LIT> , DL , VT , OtherOp , TrueOp ) ; return DAG . getNode ( <STR_LIT> , DL , VT , FalseOp , TrueOp , Cmov . getOperand ( <NUM_LIT> ) , Cmov . getOperand


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg


<s> if ( SMALL_INT_UNSIGNED ( op1 ) ) ret = <STR_LIT> ; else if ( SMALL_INT ( op1 ) ) ret = <STR_LIT> ; else ret = <STR_LIT> ; } } else if ( code1 == CONST_DOUBLE && mode == SFmode ) { if ( op1 == CONST0_RTX ( SFmode ) ) { if ( GP_REG_P ( regno0 ) ) ret = <STR_LIT> ; } else { delay = DELAY_LOAD ; ret = <STR_LIT> ; } } else if ( code1 == LABEL_REF ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } else if ( code1 == SYMBOL_REF || code1 == CONST ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } else if ( code1 == PLUS ) { rtx add_op0 = XEXP ( op1 , <NUM_LIT> ) ; rtx add_op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == CONST_INT ) add_op0 = XEXP ( op1 , <NUM_LIT> ) , add_op1 = XEXP ( op1 , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = add_op0 ; operands [ <NUM_LIT> ] = add_op1 ; ret = <STR_LIT> ; } else if ( code1 == HIGH ) { operands [ <NUM_LIT> ] = XEXP ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } } else if ( code0 == MEM ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op0 , <NUM_LIT> ) ; if ( code1 == REG ) { int regno1 = REGNO ( op1 ) + subreg_offset1 ; if ( GP_REG_P ( regno1 ) ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } } else if ( code1 == CONST_INT && INTVAL ( op1 ) == <NUM_LIT> ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } else if ( code1 == CONST_DOUBLE && op1 == CONST0_RTX ( mode ) ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT>


<s> const MCExpr * <ISA_LIT>_MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { assert ( ( Offset + MV . getConstant ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext (


<s> else assert ( <NUM_LIT> && <STR_LIT> ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i

!= e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { assert ( MF && <STR_LIT> ) ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWindows ( ) ) return CSR_Win_<ISA_LIT>_AAPCS_SaveList ; if ( MF -> getFunction ( ) . getCallingConv (

) == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_SaveList ;


<s> static bool isMOVLPMask ( ArrayRef < int > Mask , EVT VT ) { if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; return


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> static vector_costs * rs6000_vectorize_create_costs ( vec_info * vinfo , bool costing_for_scalar ) { return new rs6000_cost_data ( vinfo


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> &&


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets [ SpillOffsetTable [

I ] . Reg ] = <STR_LIT> + SpillOffsetTable [ I ] . Offset ;


<s> bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FPReg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg )


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF )


<s> parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo


<s> OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , Kind


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstructions ; for ( MachineInstr & MI : MBB . instrs ( ) ) { if ( isVCTP ( & MI ) ) { HasVCTP = true ; continue ; } if ( ! HasVCTP || MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; ( void ) MIBuilder ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ) ; DeadInstructions . push_back (


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT>


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT


<s> return __builtin_mve_vcvtq_to_f_uv4sf (


<s> static const unsigned CU64BitRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const unsigned * CURegs = ( Is64Bit ? CU64BitRegs : CU32BitRegs ) ; for ( unsigned i = <NUM_LIT> ; i != CU_NUM_SAVED_REGS ; ++ i ) { int CUReg = getCompactUnwindRegNum ( CURegs , SavedRegs [ i ] ) ; if ( CUReg == - <NUM_LIT> ) return ~ <NUM_LIT> ; SavedRegs [ i ] = CUReg ; } std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; uint32_t RenumRegs [ CU_NUM_SAVED_REGS ] ; for ( unsigned i = CU_NUM_SAVED_REGS - RegCount ; i < CU_NUM_SAVED_REGS ; ++ i ) { unsigned Countless = <NUM_LIT> ; for ( unsigned j = CU_NUM_SAVED_REGS - RegCount ; j < i ; ++ j ) if ( SavedRegs [ j ] < SavedRegs [ i ] ) ++ Countless ; RenumRegs [ i ] = SavedRegs [ i ] - Countless - <NUM_LIT> ; } uint32_t permutationEncoding = <NUM_LIT> ; switch ( RegCount ) { case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= <NUM_LIT> * RenumRegs [ <NUM_LIT> ] + RenumRegs [ <NUM_LIT> ] ; break ; case <NUM_LIT> : permutationEncoding |= RenumRegs [ <NUM_LIT>


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( )


<s> if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i +=


<s> case <STR_LIT> : return instCombineSVECmpNE ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II


<s> if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG


<s> bool aarch64_simd_valid_immediate ( rtx op , simd_immediate_info * info , enum simd_immediate_check which ) { machine_mode mode = GET_MODE ( op ) ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags == <NUM_LIT> || vec_flags == ( VEC_ADVSIMD | VEC_STRUCT ) ) return false ; if ( vec_flags & VEC_SVE_PRED ) return aarch64_sve_pred_valid_immediate ( op , info ) ; scalar_mode elt_mode = GET_MODE_INNER ( mode ) ; rtx base , step ; unsigned int n_elts ; if ( GET_CODE ( op ) == CONST_VECTOR && CONST_VECTOR_DUPLICATE_P ( op ) ) n_elts = CONST_VECTOR_NPATTERNS ( op ) ; else if ( ( vec_flags & VEC_SVE_DATA ) && const_vec_series_p ( op , & base , & step ) ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) ; if ( ! aarch64_sve_index_immediate_p ( base ) || ! aarch64_sve_index_immediate_p ( step ) ) return false ; if ( info ) { elt_mode = aarch64_sve_container_int_mode ( mode ) ; * info = simd_immediate_info ( elt_mode , base , step ) ; } return true ; } else if ( GET_CODE ( op ) == CONST_VECTOR && CONST_VECTOR_NUNITS ( op ) . is_constant ( & n_elts ) ) ; else return false ; scalar_float_mode elt_float_mode ; if ( n_elts == <NUM_LIT> && is_a < scalar_float_mode > ( elt_mode , &


<s> void <ISA_LIT>AsmParser :: expandStoreInst ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI , bool IsImmOpnd ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsImmOpnd )


<s> APInt ToMask , FromMask ; SDValue From = ParseBFI ( N , ToMask , FromMask ) ; SDValue To = N -> getOperand ( <NUM_LIT> ) ; SDValue V = To ; if ( V . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; APInt NewToMask , NewFromMask ; SDValue NewFrom = ParseBFI ( V . getNode ( )


<s> EVT PtrVT = Src1 . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( Size , DL , PtrVT ) , DAG

. getConstant ( Size / <NUM_LIT> , DL , PtrVT ) ) ;


<s> assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small && <STR_LIT> ) ; SDValue Hi = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; unsigned char LoFlags = <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , LoFlags ) ; SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> ,


<s> case AsmToken :: Dot : { const MCExpr * EVal ; if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Offset = <STR_LIT> ( EVal , S , E ) ; else return MatchOperand_NoMatch ; break ; } case AsmToken :: LParen : Offset = <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , S , E ) ; break ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , std :: move ( Offset ) ) ) ; return MatchOperand_Success ; case AsmToken :: LParen : Parser . Lex ( ) ; break ; } const MCExpr * IndexValue = nullptr ; unsigned IndexReg = <NUM_LIT> ; switch ( getLexer ( ) . getKind ( ) ) { default : if ( ParseRegister ( IndexReg , S , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : if ( getParser ( ) . parseExpression ( IndexValue , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Comma : IndexValue = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; break ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: RParen : Parser . Lex ( ) ; Operands . push_back ( IndexValue ? <STR_LIT> ( IndexValue , std :: move ( Offset ) ) : <STR_LIT> ( IndexReg , std :: move ( Offset ) ) ) ; return


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Res = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ; return Res >> <NUM_LIT> ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder )


<s> ++ MBB ) { MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; while ( MBBI != MBB -> end ( ) ) { MachineInstr & MI = * MBBI ++ ; if ( MI . getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) .


<s> InstructionSelector * create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & Subtarget

, const <ISA_LIT>RegisterBankInfo & RBI ) {


<s> if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr


<s> inline vector unsigned int vec_vmrglw ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vmrglw ( ( vector signed int ) a1 ,


<s> if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI


<s> if ( TARGET_BACKTRACE ) saved += <NUM_LIT> ; } offsets -> saved_regs = offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + saved ; offsets -> soft_frame = offsets -> saved_regs + CALLER_INTERWORKING_SLOT_SIZE ; if ( crtl -> is_leaf && frame_size == <NUM_LIT> && ! cfun -> calls_alloca ) { offsets -> outgoing_args = offsets -> soft_frame ; offsets -> locals_base = offsets -> soft_frame ; return ; } if ( ARM_DOUBLEWORD_ALIGN && ( offsets -> soft_frame & <NUM_LIT> ) ) { offsets -> soft_frame += <NUM_LIT> ; if ( frame_size + crtl -> outgoing_args_size == <NUM_LIT> ) { int reg = - <NUM_LIT> ; bool prefer_callee_reg_p = false ; if ( ! any_sibcall_could_use_r3 ( ) && arm_size_return_regs ( ) <= <NUM_LIT> && ( offsets -> saved_regs_mask & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> && ( TARGET_THUMB2 || ! ( TARGET_LDRD && current_tune -> prefer_ldrd_strd ) ) ) { reg = <NUM_LIT> ; if ( ! TARGET_THUMB2 ) prefer_callee_reg_p = true ; } if ( reg == - <NUM_LIT> || prefer_callee_reg_p ) { for ( i = <NUM_LIT> ; i <= ( TARGET_THUMB1 ? LAST_LO_REGNUM : <NUM_LIT> ) ; i ++ ) { if ( ! fixed_regs [ i ] && ( offsets -> saved_regs_mask &


<s> Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = <STR_LIT> ( M , Int , Tys ) ; CallInst * CI = Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ) , Addr } ) ; CI -> addParamAttr ( <NUM_LIT> , Attribute :: get ( M -> getContext ( ) , Attribute :: ElementType , Val -> getType (


<s> void processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , MCValue & Target , uint64_t & Value , bool & IsResolved ) { ( void ) adjustFixupValue ( Fixup , Value , & Asm . getContext


<s> return __builtin_loongson_paddusb ( s ,


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> )


<s> void i386_djgpp_asm_named_section ( const char * name , unsigned int flags , tree ) { char flagchars [ <NUM_LIT> ] , * f = flagchars ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( strncmp ( name , LTO_SECTION_NAME_PREFIX , strlen ( LTO_SECTION_NAME_PREFIX ) ) ==


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI

, const MCSubtargetInfo & MCSTI , MCContext & Ctx ) {


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( needPopSpecialFixUp ( MF ) ) { bool Done = emitPopSpecialFixUp ( MBB , true


<s> IntrinsicData IntrinsicToFind = { IntNo , INTR_NO_TYPE , <NUM_LIT> , <NUM_LIT> } ; const IntrinsicData * Data = std :: lower_bound ( std :: begin ( IntrinsicsWithChain ) , std :: end ( IntrinsicsWithChain ) , IntrinsicToFind ) ; if ( Data != std :: end ( IntrinsicsWithChain ) &&

* Data == IntrinsicToFind ) return Data ;


<s> if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear


<s> if ( TARGET_MIPS16 ) { if ( ! mips16_rdhwr_stub ) mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ( ) ; fn = mips16_stub_call_address ( mips16_rdhwr_stub ) ; emit_insn ( PMODE_INSN ( gen_tls_get_tp_mips16 , ( tp , fn ) ) ) ; } else emit_insn ( PMODE_INSN ( gen_tls_get_tp , ( tp ) ) ) ; return


<s> static const <ISA_LIT>MCExpr * CreateUpper16 ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_HI16 , Expr


<s> HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false ; Thumb2DSP =


<s> static DecodeStatus DecodeJumpTargetMM ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( JumpOffset )


<s> return ( int32x4_t ) __builtin_aarch64_saddw2v8hi (


<s> return ( __m128i ) __builtin_ia32_psrlqi128_mask ( ( __v2di ) __A , __imm , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> static bool isShuffleFoldableLoad ( SDValue V ) { while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; return <STR_LIT> ( V . getNode


<s> case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_64_GOTTPOFF ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_64_TLSGD ; break ; case MCSymbolRefExpr :: VK_TLSLD : Type = ELF :: R_<ISA_LIT>_64_TLSLD ; break ; } break ; case FK_PCRel_2 : assert ( Modifier == MCSymbolRefExpr :: VK_None ) ; Type = ELF :: R_<ISA_LIT>_64_PC16 ; break ; case FK_PCRel_1 : assert ( Modifier == MCSymbolRefExpr :: VK_None ) ; Type = ELF :: R_<ISA_LIT>_64_PC8 ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_8 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_64_64 ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_64_GOT64 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_64_GOTOFF64 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_64_TPOFF64 ; break ; case MCSymbolRefExpr :: VK_DTPOFF : Type = ELF :: R_<ISA_LIT>_64_DTPOFF64 ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_64_32S ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_64_GOT32 ; break ; case MCSymbolRefExpr :: VK_GOTPCREL : Type = ELF :: R_<ISA_LIT>_64_GOTPCREL ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_64_TPOFF32 ; break ; case MCSymbolRefExpr :: VK_DTPOFF : Type = ELF :: R_<ISA_LIT>_64_DTPOFF32 ; break ; } break ; case FK_Data_4 : Type = ELF :: R_<ISA_LIT>_64_32 ; break ; case FK_Data_2 : Type = ELF :: R_<ISA_LIT>_64_16 ; break ; case FK_PCRel_1 : case FK_Data_1 : Type = ELF :: R_<ISA_LIT>_64_8 ; break ; } } } else if ( getEMachine ( ) == ELF :: EM_386 ) { if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return false


<s> static bool isSmallTypeLdMerge ( MachineInstr * MI


<s> int64_t Offset ; L = getLoc ( ) ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ||

parseComma ( ) || parseImmExpr ( Offset ) ) return true ;


<s> bool <ISA_LIT>NaClRewritePass :: SandboxStoresInBlock ( MachineBasicBlock & MBB ) { bool Modified = false ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; int AddrIdx ; if ( IsDangerousStore ( MI , & AddrIdx ) ) { SandboxLoadStore ( MBB , MBBI , MI , AddrIdx ) ; Modified = true ; } } return Modified


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo )


<s> if ( rgn == CONTAINING_RGN ( e -> src -> index ) && BLOCK_TO_BB ( bb -> index ) > BLOCK_TO_BB ( e -> src -> index ) ) add_dependee_for_func_arg ( first_arg , e -> src ) ; } } insn = first_arg ; if ( insn == head ) break ; } } else if ( first_arg ) avoid_func_arg_motion ( first_arg , insn


<s> MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> ,


<s> SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( SrcOp . getValueType (


<s> if ( ! isPowerOf2_32 ( NumElem ) ) { unsigned Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ; unsigned SplitCost = getScalarizationOverhead ( Src , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> && ! ST -> hasAVX2 ( ) ) Cost *= <NUM_LIT> ; return Cost


<s> uint64_t SubIdx = Index / NumSubElts ; uint64_t SubElt = Index % NumSubElts ; return getShuffleScalarElt ( Op . getOperand ( SubIdx ) , SubElt , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; uint64_t SrcIdx = Op . getConstantOperandVal ( <NUM_LIT> ) ; return getShuffleScalarElt ( Src , Index + SrcIdx , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . isVector ( ) && SrcVT . getVectorNumElements ( ) == NumElems ) return getShuffleScalarElt ( Src , Index , DAG , Depth + <NUM_LIT> ) ; return SDValue ( ) ; } if ( Opcode == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( Op . getConstantOperandAPInt ( <NUM_LIT> ) == Index ) return Op . getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( Op . getOperand ( <NUM_LIT> ) , Index , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) return ( Index == <NUM_LIT> ) ? Op . getOperand ( <NUM_LIT> ) : DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; if ( Opcode == <STR_LIT> ) return Op . getOperand ( Index


<s> static rtx mips_strip_unspec_call ( rtx src ) { if ( GET_CODE ( src ) == UNSPEC && XINT ( src , <NUM_LIT> ) == UNSPEC_LOAD_CALL ) return mips_strip_unspec_address ( XVECEXP ( src


<s> return ( __m256i ) __builtin_ia32_pshuflw256_mask ( ( __v16hi ) __A , __imm , ( __v16hi ) _mm256_setzero_si256 ( ) ,


<s> EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Div ) ; } SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op1 ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , ScalableWidenedVT , Op1 ) ; Op0Lo = convertFromScalableVector ( DAG , FixedWidenedVT , Op0Lo ) ; Op1Lo = convertFromScalableVector ( DAG , FixedWidenedVT , Op1Lo ) ; Op0Hi = convertFromScalableVector ( DAG , FixedWidenedVT , Op0Hi ) ; Op1Hi = convertFromScalableVector ( DAG , FixedWidenedVT , Op1Hi ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , FixedWidenedVT , Op0Lo , Op1Lo ) ; SDValue ResultHi = DAG . getNode ( Op . getOpcode ( ) , dl , FixedWidenedVT , Op0Hi , Op1Hi ) ; ResultLo = convertToScalableVector ( DAG


<s> break ; case E_V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , <NUM_LIT> ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , <NUM_LIT> , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( x != target ) emit_move_insn ( target


<s> const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFInfo = FuncInfo . MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; if ( TLI . supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return false ; if ( TLI . supportSplitCSR ( FuncInfo . MF ) ) return false ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC != CallingConv :: C && CC != CallingConv :: Fast && CC != CallingConv :: <ISA_LIT>_FastCall && CC != CallingConv :: <ISA_LIT>_StdCall && CC != CallingConv :: <ISA_LIT>_ThisCall && CC != CallingConv :: <ISA_LIT>_64_SysV && CC != CallingConv :: Win64 ) return false ; if ( ! isUInt < <NUM_LIT> > ( <ISA_LIT>MFInfo -> getBytesToPopOnReturn ( ) ) ) return false ; if ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT ==


<s> break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportLinkage ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText ( <STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ; if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText (


<s> hasGPR = true ; LastReg = CSI [ i ] . getReg ( ) ; } if ( hasGPR ) { assert ( LastReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , LastReg ) ; } } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; if ( ! MF . protectCSRs ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } else { if ( Reg != LastReg ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , LastReg ) . addReg ( LastReg ) . addReg ( Reg ) ; } else { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned OpcCJE = <ISA_LIT>InstrInfo :: getFSOpcode ( TII . getCompareRegAndStackOpcode ( LastReg , MRI , * TRI ) ) ; addRegOffset ( BuildMI ( MBB , MI , DL , TII . get ( OpcCJE ) ) . addReg ( LastReg ) , STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , false , <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo -> getStackRegister ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; unsigned Opc = getADDriOpcode ( IsLP64 , SlotSize ) ; MachineInstr * mi = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( SlotSize ) ; mi -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } } } return


<s> else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) { if ( ix86_function_regparm ( type , NULL ) >= <NUM_LIT> && ! cfun -> machine -> arg_reg_available ) return false ; } } return true


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : (


<s> if ( regno == HARD_FRAME_POINTER_REGNUM ) regno = current_frame_info . reg_fp ; else if ( regno == current_frame_info . reg_fp ) regno = HARD_FRAME_POINTER_REGNUM ; } if ( IN_REGNO_P ( regno ) ) return <NUM_LIT> + regno - IN_REG ( <NUM_LIT> ) ; else if ( LOC_REGNO_P ( regno ) ) return <NUM_LIT> + current_frame_info . n_input_regs + regno - LOC_REG ( <NUM_LIT> ) ; else if ( OUT_REGNO_P ( regno ) ) return ( <NUM_LIT> + current_frame_info . n_input_regs + current_frame_info . n_local_regs + regno - OUT_REG (


<s> return __builtin_mve_vfmsq_fv4sf ( __a ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FirstMI << <STR_LIT> ) ; return false ; } auto canRenameMOP = [ TRI ] ( const MachineOperand & MOP ) { if ( MOP . isReg ( ) ) { auto * RegClass = TRI -> getMinimalPhysRegClass ( MOP . getReg ( ) ) ; if ( RegClass -> HasDisjunctSubRegs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MOP << <STR_LIT> ) ; return false ; } } return MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) && ! MOP . isTied ( ) ) ; } ; bool FoundDef = false ; std :: function < bool ( MachineInstr & , bool ) > CheckMIs = [ & ] ( MachineInstr & MI , bool IsDef ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } UsedInBetween . accumulate ( MI ) ; FoundDef = IsDef ; if ( FoundDef ) { if ( MI . isPseudo ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } for ( auto & MOP : MI . operands ( ) ) { if ( ! MOP . isReg ( ) || ! MOP . isDef ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) continue ; if ( ! canRenameMOP ( MOP ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MOP << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } RequiredClasses . insert ( TRI -> getMinimalPhysRegClass ( MOP . getReg ( ) ) ) ; } return true ; } else


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopPreIncPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None )

addPass ( createHardwareLoopsPass ( ) ) ;


<s> rtx orig_rtx = x ; x = copy_rtx ( x ) ; push_reload ( orig_rtx , NULL_RTX , x_p , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; return x ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && HARD_REGISTER_P ( XEXP ( x , <NUM_LIT> ) ) && mode != TImode && mode != TFmode && aarch64_regno_ok_for_base_p ( REGNO ( XEXP ( x , <NUM_LIT> ) ) , true ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; HOST_WIDE_INT low = val & <NUM_LIT> ; HOST_WIDE_INT high = val - low ; HOST_WIDE_INT offs ; rtx cst ; machine_mode xmode = GET_MODE ( x ) ; gcc_assert ( xmode == DImode || xmode == SImode ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return NULL_RTX ; offs = low % GET_MODE_SIZE ( mode ) ; if ( offs != <NUM_LIT> ) { if ( aarch64_uimm12_shift ( high + offs ) ) { low = low - offs ; high = high + offs ; } else { offs = GET_MODE_SIZE ( mode ) - offs ; low = low + offs ; high = high + ( low & <NUM_LIT>


<s> const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( )


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; V2 = DAG . getNode ( <STR_LIT> , DL , VT , V1Mask , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2


<s> Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackPtr ) . addReg ( physSPReg ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor ( testMBB ) ; BuildMI ( tailMBB , DL , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FinalStackPtr ) ; tailMBB -> splice ( tailMBB -> end ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB ->


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNum , RegKind Kind , unsigned ElementWidth , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . ElementWidth = ElementWidth ; Op -> Reg . Kind = Kind ; Op -> StartLoc = S


<s> FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( CALL_P ( insn ) ) { if ( find_reg_note ( insn , REG_SETJMP , NULL ) == NULL ) continue ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after_setloc ( cet_eb , insn , INSN_LOCATION ( insn ) ) ; continue ; } if ( JUMP_P ( insn ) && flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) continue ; rtx_insn * label = as_a < rtx_insn * >


<s> } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return false ; } if ( HasExistingPersonality ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes ( ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L ,


<s> return new <ISA_LIT>InstructionSelector ( Subtarget ,


<s> void <ISA_LIT>64CompilationCallback (


<s> <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; SpillSlotOffset -= SlotSize ; } Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size (


<s> unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX


<s> OffsetIsReg = ! MaybeParseRegister ( Op , false ) ; if ( OffsetIsReg ) OffsetRegNum = Op . getReg ( ) ; } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; OffsetRegShifted = true ; } } else { const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( Offset ) ) return true ; } return false


<s> for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) { CPUser & U = CPUsers [ i ] ; unsigned UserOffset = getUserOffset ( U ) ; if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , U . getMaxDisp ( ) + <NUM_LIT> , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT>


<s> void setVariadicStackIdx ( int Idx ) { VariadicStackIdx = Idx


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDValue WideRes ; if ( isLogicOp ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) WideRes = computeLogicOpInGPR ( N -> getOperand ( <NUM_LIT> ) ) ; else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return nullptr ; else WideRes = getSETCCInGPR ( N -> getOperand ( <NUM_LIT> ) , N -> getOpcode ( ) == <STR_LIT> ? SetccInGPROpts :: SExtOrig : SetccInGPROpts :: ZExtOrig ) ; if ( ! WideRes ) return nullptr ; SDLoc dl ( N ) ; bool Input32Bit = WideRes . getValueType ( ) == <STR_LIT> ; bool Output32Bit = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ; NumSextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; NumZextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue ConvOp = WideRes ; if ( Input32Bit != Output32Bit ) ConvOp = addExtOrTrunc ( WideRes , Input32Bit ? ExtOrTruncConversion :: Ext : ExtOrTruncConversion :: Trunc ) ; return ConvOp .


<s> return - <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return __builtin_ia32_minph512_mask ( __B , __C , _mm512_setzero_ph ( ) ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOV_Q1 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOV_Q2 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOV_Q3 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOV_Q4 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_CALL26 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_CALL19 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_9_ADDRESS ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_6_SHAMT ; break ; case <STR_LIT> : Type = ELF ::


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const

Triple & TT , StringRef CPU , const MCTargetOptions & Options ) {


<s> unsigned <ISA_LIT>InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode


<s> return Decoder -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , <NUM_LIT>


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TLI ( *


<s> uint64_t ExIdx = InScl . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; assert ( ExIdx < NumElts && <STR_LIT> ) ; Ops . push_back ( InVec ) ; Ops . push_back ( ExVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) Mask . push_back ( i == InIdx ? NumElts + ExIdx : i ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { uint64_t ShiftVal = N . getConstantOperandVal ( <NUM_LIT> ) ; if ( NumBitsPerElt <= ShiftVal ) { Mask . append ( NumElts , SM_SentinelZero ) ; return true ; } if ( ( ShiftVal % <NUM_LIT> ) != <NUM_LIT> ) break ; uint64_t ByteShift = ShiftVal / <NUM_LIT> ; unsigned NumBytes = NumSizeInBits / <NUM_LIT> ; unsigned NumBytesPerElt = NumBitsPerElt / <NUM_LIT> ; Ops . push_back ( N . getOperand ( <NUM_LIT> ) ) ; Mask . append ( NumBytes , SM_SentinelZero ) ; if ( <STR_LIT> == Opcode ) { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; i += NumBytesPerElt ) for ( unsigned j = ByteShift ; j != NumBytesPerElt ; ++ j ) Mask [ i + j ] = i + j - ByteShift ; } else { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; i += NumBytesPerElt ) for ( unsigned j = ByteShift ; j != NumBytesPerElt ; ++ j ) Mask [ i + j - ByteShift ] = i + j ; } return true ; } case <STR_LIT> : { SDValue Src = N . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( NumSizeInBits != SrcVT . getSizeInBits ( ) ) break ; DecodeZeroExtendMask ( SrcVT . getScalarType ( ) , VT , Mask ) ; Ops . push_back ( Src


<s> return IsISR && ( FI == ISRDataRegFI [ <NUM_LIT> ] || FI == ISRDataRegFI [ <NUM_LIT>


<s> itin -> FirstStage != ~ <NUM_LIT> ; ++ itin ) { const InstrStage * IS = InstrItins . Stages + itin -> FirstStage ; allStage1Units |= IS -> getUnits ( ) ; } InstrItins . IssueWidth = <NUM_LIT> ; while ( allStage1Units


<s> AddThumb1SBit ( MI , InITBlock ) ; return Result ; } Result = decodeInstruction ( DecoderTableThumb232 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return checkDecodedInstruction ( MI , Size , Address , CS , Insn32 , Result ) ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableVFP32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( Result , MI ) ; return Result ; } } Result = decodeInstruction ( DecoderTableVFPV832 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableNEONDup32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONLdStInsn = Insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONDataInsn = Insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } uint32_t NEONCryptoInsn = Insn32 ; NEONCryptoInsn &= <NUM_LIT> ; NEONCryptoInsn |= ( NEONCryptoInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONCryptoInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8Crypto32 , MI , NEONCryptoInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } uint32_t NEONv8Insn = Insn32 ; NEONv8Insn &= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8NEON32 , MI , NEONv8Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Result = decodeInstruction ( DecoderTableThumb2CoProc32 , MI , Insn32 ,


<s> MachineInstr * MI = MRI . getVRegDef ( Reg ) ; if ( ! MI ) return nullptr ; if ( ! MI -> isPredicable ( ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs


<s> __vector unsigned short c ; if ( __count <= <NUM_LIT> ) { m = ( __vector signed short ) vec_splats ( __m ) ; c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; r = vec_sl ( m , ( __vector unsigned short ) c ) ; return ( __m64 ) ( ( __vector long long ) r ) [ <NUM_LIT> ] ; } else return ( <NUM_LIT> )


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand


<s> static bool isUndefOrInRange ( const SmallVectorImpl < int > & Mask , int Pos , int Size , int Low


<s> Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( <STR_LIT> ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += 'm' ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; Key +=


<s> putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else { gcc_assert ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } break ; case MINUS : if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '-' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']' , file ) ; break ; case UNSPEC : gcc_assert ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) ; output_pic_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , code ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_PLTOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_PCREL : fputs ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> , file ) ; break ; case UNSPEC_GOTPCREL : fputs ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> , file ) ; break ; case UNSPEC_GOTTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_TPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_NTPOFF : if ( TARGET_64BIT ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_DTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTNTPOFF : if ( TARGET_64BIT ) fputs ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_INDNTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_MACHOPIC_OFFSET


<s> case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG , Subtarget ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op ,


<s> inline vector float vec_vminfp ( vector float a1 , vector


<s> void <ISA_LIT>ATTInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << '%' << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << '$' << ( int64_t )


<s> bool ix86_function_naked ( const_tree fn ) { if ( fn && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fn


<s> if ( ! IsThumb ) return Val ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) && Symbol -> isDefined ( ) ) getAssembler ( ) . setIsThumbFunc ( Symbol ) ; return Val


<s> if ( MO . isCPI ( ) ) return true ; if ( MO . isGlobal ( ) ) { if ( isGlobalStubReference ( MO . getTargetFlags ( ) ) ) return true ; if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( MO . getGlobal ( ) )

) if ( GV -> isConstant ( ) ) return true ;


<s> int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst2 = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( InstPtr , true ) , stackGrowth ) ; MAI -> addInitialFrameState (


<s> Modified = false ; for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L ->


<s> default : return false ; case TargetOpcode :: COPY : return Helper . tryCombineCopy ( MI ) ; case TargetOpcode :: G_LOAD : case TargetOpcode


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { IsLittleEndian = false ; UseIntegratedAssembler = true ; CodePointerSize = CalleeSaveStackSlotSize


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler


<s> unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned SrcLo = RegInfo . getSubReg ( Src , <STR_LIT> ) ; unsigned SrcHi = RegInfo . getSubReg ( Src , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , VR0 ) . addReg ( SrcLo , SrcKill ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , DstLo ) . addReg ( VR0 , RegState :: Kill ) ; BuildMI ( MBB , I , DL , TII . get ( TargetOpcode :: COPY ) , VR1 ) . addReg ( SrcHi


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; case CallingConv :: <ISA_LIT>_INTR : if ( Ins . empty (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateBankedReg ( unsigned Reg , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > (


<s> next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; save_area = frame_pointer_rtx ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ; bnd_reg = cum -> bnd_regno + cum -> force_bnd_pass ; if ( chkp_function_instrumented_p ( current_function_decl ) ) for ( i = cum -> regno ; i < max ; i ++ ) { rtx addr = plus_constant ( Pmode , save_area , i * UNITS_PER_WORD ) ; rtx ptr = gen_rtx_REG ( Pmode , x86_64_int_parameter_registers [ i ] ) ; rtx bounds ; if ( bnd_reg <= LAST_BND_REG ) bounds = gen_rtx_REG ( BNDmode , bnd_reg ) ; else { rtx ldx_addr = plus_constant ( Pmode , arg_pointer_rtx , ( LAST_BND_REG - bnd_reg ) * GET_MODE_SIZE ( Pmode ) ) ; bounds = gen_reg_rtx ( BNDmode ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_ldx ( bounds , ldx_addr , ptr ) : gen_bnd32_ldx ( bounds , ldx_addr , ptr ) ) ; } emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr


<s> static SDValue createPSADBW ( SelectionDAG & DAG , const SDValue & Zext0 , const SDValue & Zext1 , const SDLoc & DL , const <ISA_LIT>Subtarget & Subtarget ) { EVT InVT = Zext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned RegSize = std :: max ( <NUM_LIT> , ( unsigned ) InVT . getSizeInBits ( ) ) ; unsigned NumConcat = RegSize / InVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue >


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; return


<s> int getVarArgsFrameOffset ( ) const { return


<s> FCmp32Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_NE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32


<s> return ( __m512i ) __builtin_ia32_cvttpd2uqq512_mask ( ( __v8df ) __A , ( __v8di ) _mm512_setzero_si512 ( )

, ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;