<s> if ( TARGET_SHMEDIA ) { for ( regno = FIRST_TARGET_REG ; regno <= LAST_TARGET_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_really_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; } else for ( regno = FIRST_GENERAL_REG ; regno <= LAST_GENERAL_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_really_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; call_really_used_regs [ FPSCR_MODES_REG ] =


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; size = ( size + va_granularity - <NUM_LIT> ) & ~ ( va_granularity - <NUM_LIT> ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ ,


<s> last2 = <NUM_LIT> ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > <NUM_LIT> && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn


<s> } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand (

<NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root , OptLevel ) ) {


<s> const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; const TargetFrameLowering * TFI = TM -> getFrameLowering ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned StackAlignment = TFI -> getStackAlignment ( ) ; for ( unsigned i = <NUM_LIT> , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RI . getRegClass ( Reg ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setForceFramePointer (


<s> SMShadowTracker . count ( Inst , getSubtargetInfo ( ) , CodeEmitter .


<s> vld4q_dup_s32 ( const int32_t * __a ) { int32x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv4si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x4_t ) __builtin_aarch64_get_qregxiv4si ( __o , <NUM_LIT> ) ; return


<s> static void reassociateOps ( MachineInstr & Root , MachineInstr & Prev , MachineCombinerPattern :: MC_PATTERN Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) { MachineFunction * MF = Root . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const TargetRegisterClass * RC = Root . getRegClassConstraint ( <NUM_LIT> , TII , TRI ) ; unsigned OpIdx [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; MachineOperand & OpA = Prev . getOperand ( OpIdx [ Pattern ] [ <NUM_LIT> ] ) ; MachineOperand & OpB = Root . getOperand ( OpIdx [ Pattern ] [ <NUM_LIT> ] ) ; MachineOperand & OpX = Prev . getOperand ( OpIdx [ Pattern ] [ <NUM_LIT> ] ) ; MachineOperand & OpY = Root . getOperand ( OpIdx [ Pattern ] [ <NUM_LIT> ] ) ; MachineOperand & OpC = Root . getOperand ( <NUM_LIT> ) ; unsigned RegA = OpA . getReg ( ) ; unsigned RegB = OpB . getReg ( ) ; unsigned RegX = OpX . getReg ( ) ; unsigned RegY = OpY . getReg ( ) ; unsigned RegC = OpC . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegA ) ) MRI . constrainRegClass ( RegA , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegB ) ) MRI . constrainRegClass ( RegB , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegX ) ) MRI . constrainRegClass ( RegX , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegY ) ) MRI . constrainRegClass ( RegY , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegC ) ) MRI . constrainRegClass ( RegC , RC ) ; unsigned NewVR = MRI . createVirtualRegister ( RC ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVR , <NUM_LIT> ) ) ; unsigned Opcode = Root . getOpcode ( ) ; bool KillA = OpA . isKill ( ) ; bool KillX = OpX . isKill ( ) ; bool KillY = OpY . isKill ( ) ; MachineInstrBuilder MIB1 = BuildMI ( * MF , Prev . getDebugLoc ( ) , TII -> get ( Opcode ) , NewVR ) . addReg ( RegX , getKillRegState

( KillX ) ) . addReg ( RegY , getKillRegState ( KillY ) ) ;


<s> if ( ! Subtarget -> is64Bit ( ) ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer . EndCOFFSymbolDef


<s> static bool aarch64_use_blocks_for_constant_p (


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if (


<s> insn_length = get_attr_length ( insn ) ; long_jump_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; r5_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code


<s> switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( isIntrinsic ) { VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT>


<s> if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( ) { MCStreamer :: EmitWinEHHandlerData (


<s> bool isImm10 ( ) { if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ! ConstExpr


<s> return ( __m256i ) __builtin_ia32_vpconflictsi_256_mask ( ( __v8si ) __A , ( __v8si ) _mm256_setzero_si256 ( ) ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } Bits >>= <NUM_LIT> ; if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } Bits >>= <NUM_LIT> ; if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } unsigned AddOp = NumBytes > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( AddOp ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( ScratchReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . setMIFlag ( MIFlags ) ; return ; } unsigned LowOp , HighOp ; if ( NumBytes >= <NUM_LIT> ) { LowOp = <STR_LIT> ; HighOp = <STR_LIT> ; } else { LowOp = <STR_LIT> ; HighOp = <STR_LIT> ; NumBytes = abs ( NumBytes ) ; } if ( ( NumBytes & <NUM_LIT> ) || NumBytes == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( LowOp ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( NumBytes & <NUM_LIT> ) . setMIFlag ( MIFlags ) ; SrcReg =


<s> if ( ! CalleeFn ) return false ; AttributeList Attrs = CalleeFn -> getAttributes ( ) ; if ( Attrs . hasAttribute ( AttributeList :: FunctionIndex ,

Attribute :: ReturnsTwice ) ) return true ;


<s> inline vector unsigned int vec_vmsumuhs ( vector unsigned short a1 , vector unsigned short a2 , vector


<s> MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return <NUM_LIT> ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( &


<s> mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) x = out0 , out0 = out1 , out1 = x ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target


<s> Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; } else { Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> : <STR_LIT> , Memory . ShiftImm , Memory . ShiftType ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . OffsetRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> return ( int64x1_t ) { vcvtad_s64_f64 (


<s> if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL ,


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N ,


<s> static SDValue performShiftToAllZeros ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && ( ! Subtarget . hasInt256 ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) ) ) return SDValue ( ) ; SDValue Amt = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Amt ) ) if ( auto * AmtSplat = AmtBV -> getConstantSplatNode ( ) ) { APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType


<s> Instruction * Induction = nullptr ; if ( ! match ( I , m_ICmp ( Pred , m_Instruction ( Induction ) , m_Instruction ( Shuffle ) ) ) || Pred != ICmpInst :: ICMP_ULE || ! L -> isLoopInvariant ( Shuffle ) ) return false ; Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements ) return false ; Instruction * BroadcastSplat = nullptr ; Constant * Const = nullptr ; if ( ! match ( Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( IV ) , m_Zero


<s> return ScaBits == <NUM_LIT> || ScaBits == <NUM_LIT> || ScaBits == <NUM_LIT> ; } if ( ElemTy . isPointerTy ( ) ) { return true


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return isExpImmValue < shift > ( CE


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 (


<s> if ( ! EnableAddressTypePromotion || F . isDeclaration ( ) ) return false ; Func = & F ; ConsideredSExtType = Type :: getInt64Ty ( Func -> getContext ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( )

<< <STR_LIT> << Func -> getName ( ) << '\n' ) ;


<s> int64_t ImmR = Inst . getOperand ( ImmOps ) . getImm ( ) ; int64_t ImmS = Inst . getOperand ( ImmOps + <NUM_LIT> ) . getImm ( ) ; int64_t RegWidth = <NUM_LIT> ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegWidth = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegWidth = <NUM_LIT> ; break ; } if ( ImmS >= RegWidth || ImmS < ImmR ) { return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; } return false ; } case <STR_LIT> : { int64_t ImmVal = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> ICOp = static_cast < <STR_LIT> > ( ImmVal ) ; if ( ! <STR_LIT> ( ICOp ) ) { return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; } return false ; } case <STR_LIT> : { int64_t ImmVal = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> ICOp = static_cast < <STR_LIT> > ( ImmVal ) ; if ( <STR_LIT> ( ICOp ) ) { return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; } return false ; } case <STR_LIT> : { int64_t ImmVal = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> TLBIOp = static_cast < <STR_LIT> > ( ImmVal ) ; if ( ! <STR_LIT> ( TLBIOp ) ) { return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; } return false ; } case <STR_LIT> : { int64_t ImmVal = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> TLBIOp = static_cast < <STR_LIT> > ( ImmVal ) ; if ( <STR_LIT> ( TLBIOp ) )


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( FuncInfo . MF ->


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == <STR_LIT> ) || ( FlagSfiStore && N -> getOpcode ( ) == <STR_LIT> ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base ,


<s> return ( __m256i ) __builtin_ia32_pabsw256 ( ( __v16hi )


<s> return ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand (

<NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) ;


<s> const auto & MFI = MF . getFrameInfo ( ) ; return { ObjectOffset + ( int64_t ) MFI . getStackSize (


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false ; MVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( DstVT ) ; unsigned ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned ResultReg = fastEmitInst_rr ( Opcode , RC , ImplicitDefReg , true , OpReg , false ) ; updateValueMap ( I , ResultReg ) ; return true


<s> if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . Args , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( )


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF )


<s> return isBareImm ( isShiftedInt < <NUM_LIT> , <NUM_LIT>


<s> bool IsPush = isPushOpcode ( MI -> getOpcode ( ) ) ; if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI ->


<s> if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOperand ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOperand ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOperand ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOperand ; return


<s> for ( const MCPhysReg * Regs = MCID . getImplicitDefs ( ) ; * Regs ; ++ Regs ) if ( * Regs == <STR_LIT> ) return true ; return


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT .


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( ImmWithLSL . Val ) ; return CE -> getValue ( ) >= <NUM_LIT> && CE -> getValue


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; const MCOperand & MO = MI . getOperand


<s> if ( GPRSaveSize != <NUM_LIT> ) { if ( IsWin64 ) { GPRIdx = MFI . CreateFixedObject ( GPRSaveSize , - ( int ) GPRSaveSize , false ) ; if ( GPRSaveSize & <NUM_LIT> ) MFI . CreateFixedObject ( <NUM_LIT> - ( GPRSaveSize & <NUM_LIT> ) , - ( int ) alignTo ( GPRSaveSize , <NUM_LIT> ) , false ) ; } else GPRIdx = MFI . CreateStackObject ( GPRSaveSize , Align ( <NUM_LIT> ) , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { Register VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , IsWin64 ? MachinePointerInfo :: getFixedStack ( MF , GPRIdx , ( i - FirstVariadicGPR ) * <NUM_LIT> ) : MachinePointerInfo :: getStack ( MF , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsWin64 ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , Align ( <NUM_LIT> ) , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { Register VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( MF , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsFPRIndex ( FPRIdx ) ; FuncInfo -> setVarArgsFPRSize ( FPRSaveSize ) ; } if ( ! MemOps . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> unsigned isImm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs2 = <NUM_LIT> ; unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn


<s> vst1q_p8 ( poly8_t * a , poly8x16_t b


<s> if ( ! isa < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ) return false ; const auto * II = cast < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ; MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; <STR_LIT> TmpCC ; switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start ( I ) ; BasicBlock :: const_iterator End ( II ) ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr ) ) return false ; const auto * EVI = cast <


<s> return ( int8x8_t ) __builtin_neon_vget_highv16qi


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { if ( ST -> getCPUDirective ( ) == <STR_LIT> ) { UP . Partial = UP . Runtime =


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; int vvvv ; if ( insn -> vectorExtensionType == TYPE_EVEX ) vvvv = ( v2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> | vvvvFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) vvvv = vvvvFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) vvvv &= <NUM_LIT> ; insn -> vvvv = static_cast < Reg > ( vvvv ) ; return <NUM_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SMLoc S = getLexer ( ) . getLoc ( ) ; OperandMatchResultTy ResTy = parseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ; if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return


<s> SDLoc dl ( GA ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult . first


<s> MCStreamer * create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , MCAsmBackend & MAB , MCCodeEmitter & Emitter , raw_ostream & OS ) { return new <ISA_LIT>WinCOFFStreamer ( Context , MAB ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == k_Immediate ) { addExpr ( Inst , getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg (


<s> SubVecTy = FixedVectorType :: get ( SubVecTy -> getElementType ( ) , LaneLen ) ; auto * STVTy = UseScalable ? cast < VectorType > ( getSVEContainerIRType ( SubVecTy ) ) : SubVecTy ; Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = UseScalable ? STVTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) : STVTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * PredTy = VectorType :: get ( Type :: getInt1Ty ( STVTy -> getContext ( ) ) , STVTy -> getElementCount ( ) ) ; static const <STR_LIT> SVEStoreIntrs [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const <STR_LIT> NEONStoreIntrs [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc ; if ( UseScalable ) StNFunc = <STR_LIT> ( SI -> getModule ( ) , SVEStoreIntrs [ Factor - <NUM_LIT> ] , { STVTy } ) ; else StNFunc = <STR_LIT> ( SI -> getModule ( ) , NEONStoreIntrs [ Factor - <NUM_LIT> ] , { STVTy , PtrTy } ) ; Value * PTrue = nullptr ; if ( UseScalable ) { unsigned PgPattern = getSVEPredPatternFromNumElements ( SubVecTy -> getNumElements ( ) ) ; if ( Subtarget -> getMinSVEVectorSizeInBits ( ) == Subtarget -> getMaxSVEVectorSizeInBits ( ) && Subtarget -> getMinSVEVectorSizeInBits ( ) == DL . getTypeSizeInBits ( SubVecTy ) ) PgPattern = <STR_LIT> ; auto * PTruePat = ConstantInt :: get ( Type :: getInt32Ty ( STVTy -> getContext ( ) ) , PgPattern ) ; PTrue = Builder . CreateIntrinsic ( <STR_LIT> , { PredTy } , { PTruePat } ) ; } for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { Value * Shuffle ; unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Shuffle = Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { unsigned IdxJ = StoreCount * LaneLen * Factor + j ; if ( Mask [ IdxJ * Factor + IdxI ] >= <NUM_LIT> ) { StartMask = Mask [ IdxJ * Factor + IdxI


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; DebugLoc dl = MI


<s> switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return


<s> return ( __m128 ) __builtin_ia32_gathersiv4sf ( ( __v4sf ) src , base ,

( __v4si ) index , ( __v4sf ) mask , scale ) ;


<s> static void adjustCodeGenOpts ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model & CM ) { if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel ::


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t


<s> for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return Changed ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } assert ( LoLoop . Start -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( LoLoop . Dec != LoLoop .


) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> unsigned AddrReg = getRegForValue ( BI -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; AddrReg = constrainOperandRegClass ( II , AddrReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,


<s> return Subtarget -> isTargetMachO ( ) &&


<s> if ( n_intregs > <NUM_LIT> ) move_block_from_reg ( BASE_ARG_REG ( SImode ) + first_intreg , adjust_address ( regbuf , BLKmode , n_floatregs * UNITS_PER_WORD ) , n_intregs , n_intregs * UNITS_PER_WORD ) ; if ( TARGET_SHMEDIA ) return XEXP ( regbuf , <NUM_LIT> ) ; fpregs = gen_reg_rtx ( Pmode ) ; emit_move_insn ( fpregs , XEXP ( regbuf , <NUM_LIT> ) ) ; emit_insn ( gen_addsi3 ( fpregs , fpregs , GEN_INT ( n_floatregs * UNITS_PER_WORD ) ) ) ; if ( TARGET_SH4 ) { rtx mem ; for ( regno = NPARM_REGS ( DFmode ) - <NUM_LIT> ; regno >= first_floatreg ; regno -= <NUM_LIT> ) { emit_insn ( gen_addsi3 ( fpregs , fpregs , GEN_INT ( - <NUM_LIT> * UNITS_PER_WORD ) ) ) ; mem = gen_rtx_MEM ( DFmode , fpregs ) ; set_mem_alias_set ( mem , alias_set ) ; emit_move_insn ( mem , gen_rtx ( REG , DFmode , BASE_ARG_REG ( DFmode ) + regno ) ) ; } regno = first_floatreg ; if ( regno & <NUM_LIT> ) { emit_insn ( gen_addsi3 ( fpregs , fpregs , GEN_INT ( - UNITS_PER_WORD ) ) ) ; mem = gen_rtx_MEM ( SFmode , fpregs ) ; set_mem_alias_set ( mem , alias_set ) ; emit_move_insn ( mem , gen_rtx ( REG , SFmode , BASE_ARG_REG ( SFmode ) + regno - ( TARGET_LITTLE_ENDIAN != <NUM_LIT> ) ) ) ; } } else for ( regno = NPARM_REGS ( SFmode ) - <NUM_LIT> ;


<s> Src = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , SrcVT , MPI , None , MachineMemOperand :: MOLoad ) ; Chain = Src . getValue ( <NUM_LIT> ) ; } SDValue StoreOps [ ] = { Chain , Src , StackPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , StoreOps , DstVT , MPI , None , MachineMemOperand :: MOStore ) ; return DAG . getLoad ( DstVT , DL ,


<s> for ( MachineInstr & MI : llvm :: reverse ( llvm :: make_range ( MBB . instr_begin ( ) , CopyDefI . getIterator ( ) ) ) ) { <STR_LIT> Cond = <STR_LIT> ( MI . getOpcode ( )


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && ( ! ST . hasFullFP16 ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) ) ) return SDValue ( ) ; std :: string RecipOp ; RecipOp = Opcode == ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RecipOp = ( ( VT . isVector ( ) ) ? <STR_LIT> : <STR_LIT> ) + RecipOp ; RecipOp += ( VT . getScalarType ( ) == <STR_LIT> )


<s> unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) .

addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ;


<s> return ( ( Val == SM_SentinelUndef ) || ( Val == SM_SentinelZero )


<s> static bool xstormy16_function_value_regno_p ( const unsigned int regno ) { return ( regno == RETURN_VALUE_REGNUM


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr :: VK_ABS_G2_NC


<s> if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; union_defs ( insn_entry , insn , mention ) ; } } FOR_EACH_INSN_INFO_DEF ( mention , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REAL_REG ( mention ) ) ; if ( mode == DImode && GET_CODE ( insn ) == SET && ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( SET_DEST ( insn ) ) ) ) mode = GET_MODE ( SET_DEST ( insn ) ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode || FLOAT128_VECTOR_P ( mode ) ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; else if ( REG_FUNCTION_VALUE_P ( DF_REF_REG ( mention ) ) ) insn_entry [ uid ] . is_live_out = <NUM_LIT> ; union_uses ( insn_entry , insn , mention ) ; } } if ( insn_entry [ uid ] . is_relevant ) { insn_entry [ uid ] . is_load = insn_is_load_p ( insn ) ; insn_entry [ uid ] . is_store = insn_is_store_p ( insn ) ; if ( insn_is_swap_p ( insn ) ) insn_entry [ uid ] . is_swap = <NUM_LIT> ; else { unsigned int special = SH_NONE ; insn_entry [ uid ] . is_swappable = insn_is_swappable_p ( insn_entry , insn , & special ) ; if ( special != SH_NONE && insn_entry [ uid ] . contains_subreg ) insn_entry [ uid ] . is_swappable = <NUM_LIT> ; else if ( special != SH_NONE ) insn_entry [ uid ] . special_handling = special ; else if ( insn_entry [ uid ] . contains_subreg && has_part_mult ( insn ) ) insn_entry [ uid ] . is_swappable = <NUM_LIT> ; else if ( insn_entry [ uid ] . contains_subreg ) insn_entry

[ uid ] . special_handling = SH_SUBREG ;


<s> if ( ! use_cmse ) { * no_add_attrs = true ; warning ( OPT_Wattributes , <STR_LIT> , name ) ; return NULL_TREE ; } if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } fndecl = * node ; if ( ! TREE_PUBLIC ( fndecl ) ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE


<s> uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Align ) ; else OutStreamer -> EmitCommonSymbol ( GVSym , Size , Align ) ; return ; } const unsigned AlignLog = getGVAlignmentLog2 ( GV , DL ) ; MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym ) ; EmitAlignment ( AlignLog , GV ) ; OutStreamer -> EmitLabel ( EmittedInitSym ) ; EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV ->


<s> return pcum -> aapcs_partial ; } if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( arg . mode ) ) return <NUM_LIT> ; if ( NUM_ARG_REGS > nregs && ( NUM_ARG_REGS < nregs + ARM_NUM_REGS2 ( arg . mode , arg . type ) ) && pcum -> can_split ) return ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ; return <NUM_LIT>


<s> if ( ConstantExpr * CE = dyn_cast < ConstantExpr > ( V ) ) { return opActual ( CE -> getOperand (


<s> static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v'


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering (


<s> case <STR_LIT> : return ELF :: R_MIPS_PC21_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PC26_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_DTPRel_4 : return ELF :: R_MIPS_TLS_DTPREL32 ; case FK_DTPRel_8 : return ELF :: R_MIPS_TLS_DTPREL64 ; case FK_TPRel_4 : return ELF :: R_MIPS_TLS_TPREL32 ; case FK_TPRel_8 : return ELF :: R_MIPS_TLS_TPREL64 ; case FK_GPRel_4 : if ( is64Bit ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MICROMIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MICROMIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MICROMIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT>


<s> assert ( RegBank && <STR_LIT> ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; ( void ) DstSize ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; ( void ) SrcSize ; assert ( DstSize <= SrcSize && <STR_LIT> ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( )


<s> assert ( ( ( IdxDupOp == <NUM_LIT> ) || ( IdxDupOp == <NUM_LIT> ) ) && <STR_LIT> ) ; MachineFunction & MF = * Root . getMF ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * Dup = MF . getRegInfo ( ) . getUniqueVRegDef ( Root . getOperand ( IdxDupOp ) . getReg ( ) ) ; if ( Dup -> getOpcode ( ) == TargetOpcode :: COPY ) Dup = MRI . getUniqueVRegDef ( Dup -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register DupSrcReg = Dup -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI . clearKillFlags ( DupSrcReg ) ; MRI . constrainRegClass ( DupSrcReg ,


<s> int mmix_data_alignment ( tree type ATTRIBUTE_UNUSED ,


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter


<s> cl_deferred_option * opt ; vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) ia64_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mfixed_range_ : fix_range ( opt -> arg ) ; break ; default : gcc_unreachable ( ) ; } } if ( TARGET_AUTO_PIC ) target_flags |= MASK_CONST_GP ; if ( optimize >= <NUM_LIT> ) flag_ira_loop_pressure = <NUM_LIT> ; ia64_section_threshold = ( global_options_set . x_g_switch_value ? g_switch_value : IA64_DEFAULT_GVALUE ) ; init_machine_status = ia64_init_machine_status ; if ( align_functions <= <NUM_LIT> ) align_functions = <NUM_LIT> ; if ( align_loops <= <NUM_LIT> ) align_loops = <NUM_LIT> ; if ( TARGET_ABI_OPEN_VMS ) flag_no_common


<s> for ( SDNode :: use_iterator UI = Flags -> use_begin ( ) , UE = Flags -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != Flags . getResNo ( ) ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> || cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; <STR_LIT> CC = getCondFromOpc ( FlagUI -> getMachineOpcode ( ) ) ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo


<s> } emit_insn ( cmp ) ; or_result = gen_reg_rtx ( CCFPmode ) ; cmp = gen_e500_cr_ior_compare ( or_result , compare_result , compare_result2 ) ; compare_result = or_result ; code = EQ ; } else { if ( code == NE || code == LTGT ) code = NE ; else code = EQ ; } emit_insn ( cmp ) ; } else { if ( comp_mode == CCFPmode && TARGET_XL_COMPAT && GET_MODE ( rs6000_compare_op0 ) == TFmode && ! TARGET_IEEEQUAD && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 ) emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , compare_result , gen_rtx_COMPARE ( comp_mode , rs6000_compare_op0 , rs6000_compare_op1 ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( DFmode ) ) ) ) ) ; else if ( GET_CODE ( rs6000_compare_op1 ) == UNSPEC && XINT ( rs6000_compare_op1 , <NUM_LIT> ) == UNSPEC_SP_TEST ) { rtx op1 = XVECEXP ( rs6000_compare_op1 , <NUM_LIT> , <NUM_LIT> ) ; comp_mode = CCEQmode ; compare_result = gen_reg_rtx ( CCEQmode ) ; if ( TARGET_64BIT ) emit_insn ( gen_stack_protect_testdi ( compare_result , rs6000_compare_op0 , op1 ) ) ; else emit_insn ( gen_stack_protect_testsi ( compare_result , rs6000_compare_op0 , op1 ) ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , compare_result , gen_rtx_COMPARE ( comp_mode , rs6000_compare_op0 , rs6000_compare_op1 ) ) ) ; } if ( rs6000_compare_fp_p && ! flag_finite_math_only && ! ( TARGET_HARD_FLOAT && TARGET_E500 && ! TARGET_FPRS ) && ( code == LE || code == GE || code == UNEQ || code == LTGT || code == UNGT || code == UNLT ) ) { enum rtx_code or1 , or2 ; rtx or1_rtx , or2_rtx , compare2_rtx ; rtx or_result = gen_reg_rtx ( CCEQmode ) ; switch ( code ) { case LE : or1 = LT ; or2 = EQ ; break ; case GE : or1 = GT ; or2 = EQ ; break ; case UNEQ : or1 = UNORDERED ; or2 =


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ||


<s> __r = ( __vector unsigned short ) vec_splats ( __m ) ; __c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; __r = vec_sr ( __r , ( __vector unsigned short ) __c ) ; return ( __m64 ) ( ( __vector long long ) __r )


<s> return ( Subtarget . getFeatureBits ( ) & <STR_LIT> )


<s> switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry (


<s> assert ( STI . isTargetWin32 ( ) && <STR_LIT> ) ; assert ( STI . is32Bit ( ) && ! Uses64BitFramePtr && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; Register FramePtr = TRI -> getFrameRegister ( MF ) ; Register BasePtr = TRI -> getBaseRegister ( ) ; WinEHFuncInfo & FuncInfo = * MF . getWinEHFuncInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI . getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } Register UsedReg ; int EHRegOffset = getFrameIndexReference ( MF , FI , UsedReg ) . getFixed


<s> SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ; return


<s> bool IsABICalls = Subtarget -> isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; if ( IsABICalls ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; Subtarget -> isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; } getTargetStreamer ( ) . updateABIInfo ( * Subtarget ) ; if ( ABI . IsO32 ( ) && ( Subtarget -> isABI_FPXX ( ) || Subtarget -> isFP64bit ( ) ) ) getTargetStreamer


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { unsigned AltIdx =


<s> OS << markup ( <STR_LIT> ) << '%' << getRegisterName ( RegNo )


<s> static DecodeStatus DecodeT2SOImm ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { unsigned ctrl = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ctrl == <NUM_LIT> ) { unsigned byte = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( byte ) { case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | imm ) ) ; break ; } } else { unsigned unrot = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy


<s> SDValue CondReg = DAG . getCopyFromReg ( Chain , dl , CCReg , <STR_LIT> ) ; CondReg = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , CondReg ) ; CondReg = DAG . getCopyFromReg ( CondReg , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CondReg , Cst ) ; Cst = DAG . getConstant ( <NUM_LIT> ,


<s> const Constant * <ISA_LIT>TargetLowering :: getTargetConstantFromLoad ( LoadSDNode *


<s> for ( int i = Half ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , NumElems ) ) return false ; return


<s> emit_insn ( gen_movhi ( scratch_hi , outval ) ) ; outval = scratch_hi ; } } emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; if ( reg_overlap_mentioned_p ( base_plus , outval ) ) { if ( ! reg_overlap_mentioned_p ( scratch , outval ) ) std :: swap ( scratch , base_plus ) ; else { rtx scratch_hi = gen_rtx_REG ( HImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movhi ( scratch_hi , outval ) ) ; outval = scratch_hi ; } } emit_insn ( gen_addsi3 ( base_plus , base , GEN_INT ( hi ) ) ) ; base = base_plus ; offset = lo ; } } if ( BYTES_BIG_ENDIAN ) { emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , base , offset + <NUM_LIT> ) ) , gen_lowpart ( QImode , outval ) ) ) ; emit_insn ( gen_lshrsi3 ( scratch , gen_rtx_SUBREG ( SImode , outval , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , base , offset ) ) , gen_lowpart ( QImode , scratch ) ) ) ; } else { emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , base , offset ) ) , gen_lowpart ( QImode , outval ) ) ) ; emit_insn ( gen_lshrsi3 ( scratch , gen_rtx_SUBREG ( SImode , outval , <NUM_LIT> ) , GEN_INT


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> ||

Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) , Parser ( Parser ) , Lexer ( Parser . getLexer ( ) ) , SubtargetInfo ( STI ) { setAvailableFeatures ( ComputeAvailableFeatures ( SubtargetInfo . getFeatureBits


<s> if ( TARGET_64BIT ) return NULL_TREE ; if ( CHECK_STACK_LIMIT > <NUM_LIT> ) alt = tree_cons ( get_identifier ( <STR_LIT> ) , NULL , NULL ) ; else { alt = tree_cons ( NULL , build_int_cst ( NULL , <NUM_LIT> ) , NULL ) ; alt = tree_cons ( get_identifier ( <STR_LIT> ) , alt , NULL ) ; } decl_attributes ( node , alt , flags ) ; return NULL_TREE


<s> return ( __m256i ) __builtin_ia32_psrlv8si_mask ( ( __v8si ) __X , ( __v8si ) __Y , ( __v8si ) _mm256_setzero_si256 ( ) ,


<s> auto MnemonicRange = std :: equal_range ( Start , End , Mnemonic , LessOpcode ( ) ) ; return MnemonicRange . first !=


<s> LLVMContext & Ctx = AI -> getContext ( ) ; unsigned Imm = countTrailingZeros ( cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; Function * BitTest = <STR_LIT> ( AI -> getModule ( ) , IID , AI -> getType ( ) ) ; Value * Addr = Builder . CreatePointerCast ( AI -> getPointerOperand ( ) , Type :: getInt8PtrTy ( Ctx ) ) ; Value * Result = Builder . CreateCall ( BitTest , { Addr , Builder . getInt8 ( Imm ) } ) ; I -> replaceAllUsesWith ( Result ) ; I -> eraseFromParent (


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> static bool isAddWithImmediate ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> unsigned nextIndex = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = N0 -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N0 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> && N1 -> getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) { SDValue ExtVec0 = N0 -> getOperand ( i ) ; SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return SDValue ( ) ; nextIndex += <NUM_LIT> ; } else return SDValue ( ) ; } SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , TLI . getPointerTy ( ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem )


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getType ( DstReg ) . isVector


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned DstBitsPerElt = VT . getScalarSizeInBits ( ) ; unsigned SrcBitsPerElt = <NUM_LIT> * DstBitsPerElt ; assert ( N0 . getScalarValueSizeInBits ( ) == SrcBitsPerElt && N1 . getScalarValueSizeInBits ( ) == SrcBitsPerElt && <STR_LIT> ) ; APInt UndefElts0 , UndefElts1 ; SmallVector < APInt , <NUM_LIT> > EltBits0 , EltBits1 ; if ( ( N0 -> isUndef ( ) || N -> isOnlyUserOf ( N0 . getNode ( ) ) ) && ( N1 -> isUndef ( ) || N -> isOnlyUserOf ( N1 . getNode ( ) ) ) && getTargetConstantBitsFromNode ( N0 , SrcBitsPerElt , UndefElts0 , EltBits0 ) && getTargetConstantBitsFromNode ( N1 , SrcBitsPerElt , UndefElts1 , EltBits1 ) ) { unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumDstElts = VT . getVectorNumElements ( ) ; unsigned NumSrcElts = NumDstElts / <NUM_LIT> ; unsigned NumDstEltsPerLane = NumDstElts / NumLanes ; unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes ; bool IsSigned = ( <STR_LIT> == Opcode ) ; APInt Undefs ( NumDstElts ,


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , IsLittleEndian


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects (


<s> sawStore = true ; if ( sawLoad ) return true ; } for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet


<s> bool function_resolver :: require_matching_pointer_type ( unsigned int argno , unsigned int first_argno , type_suffix_index type ) { type_suffix_index new_type = infer_pointer_type ( argno ) ; if ( new_type == NUM_TYPE_SUFFIXES


<s> switch ( mode ) { case E_DImode : return gen_storewb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case


<s> } if ( lastpos < pos ) return <NUM_LIT> ; char * buf = ( char * ) malloc ( lastpos - pos + <NUM_LIT> ) ; memcpy ( buf , & linebuf [ pos ] , lastpos - pos +


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( Ord == SequentiallyConsistent ) return callIntrinsic ( Builder , <STR_LIT> ) ; else if ( isAtLeastRelease ( Ord ) ) return callIntrinsic ( Builder ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCondCode ( <STR_LIT> CC , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CondCode ) ; Op -> CC .


<s> if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm


<s> int val ; bool pac = ( aarch_ra_sign_scope != AARCH_FUNCTION_NONE ) ; bool bti = ( aarch_enable_bti == <NUM_LIT> ) ; arm_print_asm_arch_directives ( asm_out_file , TREE_TARGET_OPTION ( target_option_default_node ) ) ; if ( TARGET_BPABI ) { if ( arm_active_target . core_name && bitmap_bit_p ( arm_active_target . isa , isa_bit_quirk_no_asmcpu ) && ! startswith ( arm_active_target . core_name , <STR_LIT> ) ) { const char * truncated_name = arm_rewrite_selected_cpu ( arm_active_target . core_name ) ; if ( bitmap_bit_p ( arm_active_target . isa , isa_bit_quirk_no_asmcpu ) ) asm_fprintf ( asm_out_file , <STR_LIT> , truncated_name ) ; } if ( print_tune_info ) arm_print_tune_info ( ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP_SINGLE ) arm_emit_eabi_attribute ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_HARD_FLOAT_ABI ) arm_emit_eabi_attribute (


<s> auto IsMACCandidate = [ ] ( Instruction * I , ParallelMACList & MACCandidates ) { for ( auto & MAC : MACCandidates ) for ( auto * Val : MAC . VL ) if

( I == MAC . Mul || Val == I ) return true ;


<s> assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand (


<s> MVT VT = Op1 . getSimpleValueType ( ) ; MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , dl , EVT ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( G1 -> requiresFixup ( ) != G2 -> requiresFixup ( ) ) return G1 -> requiresFixup ( ) > G2 -> requiresFixup ( ) ; assert ( ( G1 == G2 || ( G1 -> startsBefore ( G2 ) ^ G2 -> startsBefore ( G1 ) ) ) && <STR_LIT> ) ; return G1 -> startsBefore ( G2 ) ; } ) ; Color PreferredColor = Parity < <NUM_LIT> ? Color :: Even : Color :: Odd ; while ( Chain * G = getAndEraseNext ( PreferredColor , GV ) ) { Color C = PreferredColor ; if ( Parity == <NUM_LIT> ) C


<s> uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; return false ; } } Predicated . insert ( MI ) ; } SmallSet < Register , <NUM_LIT> > LiveOuts ; SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ; ML . getExitBlocks ( ExitBlocks ) ; for ( auto * MBB : ExitBlocks ) for ( const MachineBasicBlock :: RegisterMaskPair & RegMask : MBB -> liveins ( ) ) if ( QPRs -> contains ( RegMask . PhysReg ) ) LiveOuts . insert ( RegMask . PhysReg ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveMIs ; assert ( ML . getNumBlocks ( ) ==


<s> int vfp3_const_double_rtx ( rtx x ) { if ( ! TARGET_VFP3 ) return <NUM_LIT>


<s> gcc_assert ( TARGET_LINK_STACK ) ; if ( USE_HIDDEN_LINKONCE ) sprintf (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } return


<s> if ( Subtarget -> isTargetEnvMacho ( ) ) { if ( is64Bit ) return new <ISA_LIT>64_MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } if ( Subtarget -> isTargetELF


<s> if ( St -> isVolatile ( ) ) return SDValue ( ) ; SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( Subtarget -> hasNEON ( ) ) if ( SDValue Store = PerformTruncatingStoreCombine ( St , DCI . DAG ) ) return Store ; if ( Subtarget -> hasMVEIntegerOps ( ) ) if ( SDValue NewToken = PerformSplittingToNarrowingStores ( St , DCI . DAG ) ) return NewToken ; if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI


<s> if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; if ( PPC405_ERRATUM77 ) emit_insn ( gen_memory_barrier ( )


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT>


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const


<s> rtx l , h , x , s ; enum machine_mode wmode , mode ; rtx ( * unpack_l ) ( rtx , rtx , rtx ) ; rtx ( * unpack_h ) ( rtx , rtx , rtx ) ; rtx ( * plus ) ( rtx , rtx , rtx ) ; wmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; switch ( mode ) { case V8QImode : unpack_l = gen_unpack1_l ; unpack_h = gen_unpack1_h ; plus = gen_addv4hi3 ; break ; case V4HImode : unpack_l = gen_unpack2_l ; unpack_h = gen_unpack2_h ; plus = gen_addv2si3 ; break ; default : gcc_unreachable ( ) ; } if ( unsignedp ) x = CONST0_RTX ( mode ) ; else { bool neg ; x = gen_reg_rtx ( mode ) ; neg = ia64_expand_vecint_compare ( LT , mode , x , operands [ <NUM_LIT> ] , CONST0_RTX (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true ; } } else { if ( auto * C = dyn_cast


<s> return ( __m512i ) __builtin_ia32_expanddi512_maskz ( ( __v8di ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8


<s> assert ( ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_PCREL ) && <STR_LIT> <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) ) ) ; return <NUM_LIT> ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; assert ( BE -> getOpcode ( ) == MCBinaryExpr :: Add && <STR_LIT> ) ; const MCExpr * LHS = BE -> getLHS ( ) ; const MCExpr * RHS = BE -> getRHS ( ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef ) std :: swap ( LHS , RHS ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef || RHS -> getKind ( ) != MCExpr :: Constant ) llvm_unreachable ( <STR_LIT> ) ; const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( LHS ) ; ( void ) SRE ; assert ( isInt < <NUM_LIT> > ( cast < MCConstantExpr > ( RHS ) -> getValue ( ) ) && <STR_LIT> ) ; assert ( ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL || SRE -> getKind (

) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ) && <STR_LIT> ) ;


<s> static DecodeStatus DecodeFixedPointScaleImm64 ( MCInst & Inst , unsigned Imm , uint64_t Addr


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const { llvm_unreachable ( <STR_LIT> )


<s> std :: unique_ptr < PBQPRAConstraint > <ISA_LIT>Subtarget :: getCustomPBQPConstraints ( ) const { if ( ! isCortexA57 ( ) ) return


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; SMLoc SRegLoc = getLoc ( ) ; int RegNum = tryParseRegister ( ) ; RegKind RegisterKind = RegKind :: Scalar ; if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: NeonVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: NeonVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: SVEDataVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEDataVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) { StringRef


<s> void addImmSExt8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT>


<s> Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> || LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> || LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB (


<s> return ( __m64 ) __builtin_ia32_punpckhwd ( ( __v4hi )


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter , bool IsThumb ) : MCELFStreamer ( Context , std

:: move ( TAB ) , OS , std :: move ( Emitter ) ) , IsThumb ( IsThumb ) {


<s> void <ISA_LIT>AsmPrinter :: printAddrMode6OffsetOperand ( const MachineInstr * MI , int Op


<s> switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) , CmpLHS ; unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT ,


<s> static Type * getCmpOpsType ( const Instruction * I , unsigned VF = <NUM_LIT> ) { Type * OpTy = nullptr ; if ( CmpInst * CI = dyn_cast < CmpInst > ( I -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; else if ( Instruction * LogicI = dyn_cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( CmpInst * CI0 = dyn_cast < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) if ( isa < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI0 -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy != nullptr ) { if ( VF == <NUM_LIT> ) { assert ( ! OpTy -> isVectorTy ( ) &&


<s> if ( ! TARGET_HPUX && TYPE_MODE ( type ) == TFmode ) return <STR_LIT> ; if ( TYPE_MODE ( type ) == XFmode ) return TARGET_HPUX ?


<s> MCSym = MBB -> getSymbol ( ) ; } else if ( CCPV -> isJT ( ) ) { signed JTI = cast < <ISA_LIT>ConstantPoolJT > ( CCPV ) -> getJTI ( ) ; MCSym = GetJTISymbol ( JTI ) ; } else { assert ( CCPV -> isExtSymbol ( ) && <STR_LIT> ) ; StringRef Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( CCPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , MCSymbolRefExpr :: VK_None , OutContext ) ; if ( CCPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = OutContext . getOrCreateSymbol ( Twine ( MAI -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CCPV -> getLabelID ( ) ) ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; if ( CCPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol (


<s> default : return MatchOperand_NoMatch ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : case AsmToken :: Identifier : { const MCExpr * EVal ; if ( ! parseExpression ( EVal ) ) Offset = <STR_LIT> ( EVal , S , E ) ; else return MatchOperand_NoMatch ; break ; } case AsmToken :: LParen : Offset = <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , S , E ) ; break ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , std :: move ( Offset ) ) ) ; return MatchOperand_Success ; case AsmToken :: LParen : Parser . Lex ( ) ; break ; } const MCExpr * IndexValue = nullptr ; unsigned IndexReg = <NUM_LIT> ; switch ( getLexer ( ) . getKind ( ) ) { default : if ( ParseRegister ( IndexReg , S , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Minus : case AsmToken ::


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { SDLoc dl ( N ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; AM . dump


<s> if ( Zeroable [ i ] ) continue ; SDValue Elt = Op -> getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , Mask ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2


<s> switch ( Cond . size ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : CC = <STR_LIT> ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; break ; case <NUM_LIT> : { bool Is64Bit ; switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Is64Bit = false ; CC = <STR_LIT> ; break ; case <STR_LIT> : Is64Bit = true ; CC = <STR_LIT> ; break ; case <STR_LIT> : Is64Bit = false ; CC = <STR_LIT> ; break ; case <STR_LIT> : Is64Bit = true ; CC = <STR_LIT> ; break ; } Register SrcReg = Cond [ <NUM_LIT> ] . getReg ( ) ; if ( Is64Bit ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } else { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } break ; } case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC =


<s> static int loongarch_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( loongarch_cost -> memory_latency + memory_move_secondary_cost ( mode ,


<s> Register Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Val ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; assert ( Ty == MRI . getType ( Dst ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) Val = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Val ) . getReg ( <NUM_LIT> ) ; const LLT V8S8 = LLT :: vector ( <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; Val = MIRBuilder . buildBitcast ( V8S8 , Val ) . getReg ( <NUM_LIT> ) ; auto CTPOP = MIRBuilder . buildCTPOP ( V8S8 , Val


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveRegSave ( DirectiveID . getLoc (


<s> case <ISA_LIT>Subtarget :: O32 : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> )


<s> Size = getPointerWidth ( ) ; InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ; } return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Info . OpDecl ) ; } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef ) { if ( ! Size ) { Size = Info . Type


<s> struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] .


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>Subtarget :: isDarwin : return new TargetLoweringObjectFileMachO ( ) ; case <ISA_LIT>Subtarget :: isELF : return new TargetLoweringObjectFileELF ( ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget :: isCygwin : case <ISA_LIT>Subtarget ::


<s> if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 &&


<s> if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) ,


<s> uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , dl , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -=


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand ::


<s> int size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( VAR_P ( decl ) && DECL_SECTION_NAME ( decl ) != <NUM_LIT> ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , <STR_LIT> ) != <NUM_LIT> &&

strcmp ( name , <STR_LIT> ) != <NUM_LIT> ) return false ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return