<s> if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; unsigned ByteSize = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( StackSlot ) ; MachineMemOperand * LoadMMO ; if ( FI ) { int SSFI = FI -> getIndex ( ) ; LoadMMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , ByteSize , ByteSize ) ; } else { LoadMMO = cast < LoadSDNode > ( StackSlot ) -> getMemOperand ( ) ; StackSlot = StackSlot . getOperand ( <NUM_LIT> ) ; } SDValue FILDOps [ ] = { Chain , StackSlot } ; SDValue Result = DAG . getMemIntrinsicNode ( useSSE ? <STR_LIT> : <STR_LIT> , DL , Tys , FILDOps , SrcVT , LoadMMO ) ; Chain = Result . getValue ( <NUM_LIT> ) ; if ( useSSE ) { SDValue InFlag = Result . getValue ( <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = Op . getValueSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( SSFISize


<s> bool SVEVecStackRegion :: allocatesType ( const Type * Type ) const { if ( auto ST = dyn_cast < StructType > ( Type ) ) if ( std :: equal ( ST -> element_begin ( ) , ST -> element_end ( ) , ST -> element_begin ( ) ) ) return ( ST -> getNumElements ( ) != <NUM_LIT> ) ? allocatesType ( * ST -> element_begin ( ) ) : false ; if ( isa < ArrayType > ( Type ) ) return allocatesType ( cast < ArrayType > ( Type ) -> getElementType ( ) ) ; const VectorType * VT = dyn_cast < const VectorType


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr ( ) ; Expr -> print ( OS )


<s> if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ; return


<s> void sandboxIndirectJump ( const MCInst & MI , const MCSubtargetInfo & STI ) { unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitBundleLock ( false ) ; emitMask ( AddrReg , IndirectBranchMaskReg


<s> return ( regno <= MMIX_LAST_STACK_REGISTER_REGNUM && ! call_used_or_fixed_reg_p


<s> static bool mips_near_type_p ( const_tree


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _subborrow_u64 ( unsigned char __CF , unsigned long long

__X , unsigned long long __Y , unsigned long long * __P ) {


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , CmpInst :: Predicate VecPred , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind ) ; if ( ! ValTy -> isVectorTy ( ) ) { switch ( Opcode ) { case Instruction :: ICmp : { unsigned ScalarBits = ValTy -> getScalarSizeInBits ( ) ; if ( I != nullptr && ScalarBits >= <NUM_LIT> ) if ( LoadInst * Ld = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( const ConstantInt * C = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( ! Ld -> hasOneUse ( ) && Ld -> getParent ( ) == I -> getParent ( ) && C -> isZero ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += ( I != nullptr ? getOperandsExtensionCost ( I ) : <NUM_LIT> ) ; return Cost ; } case Instruction :: Select : if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } else if ( ST -> hasVector ( ) ) { unsigned VF = cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumVectorRegs ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return


<s> unsigned <ISA_LIT>TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( <ISA_LIT>SubTarget . isDarwin (


<s> else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( )


<s> bool isLoopBackEdge ( MachineBasicBlock * Header


<s> use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , <NUM_LIT> ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_BRANCH


<s> rtx tmp ; set = single_set ( insn ) ; if ( ! set ) return ; tmp = SET_DEST ( set ) ; if ( REG_P ( tmp )


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetEnvMacho ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( Subtarget -> isTargetCOFF ( ) ) { if ( ! Subtarget -> is64Bit ( ) ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef


<s> static bool CC_<ISA_LIT>_SVR4_Custom_AlignFPArgRegs ( unsigned & ValNo , EVT & ValVT , EVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs , NumArgRegs ) ; if ( RegNum != NumArgRegs && ArgRegs [ RegNum ] ==


<s> } if ( mode == V16SFmode ) return regno == FIRST_XD_REG ; if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E ) && mode == SCmode ) || ( ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT>

) || ( TARGET_SH4 && mode == TImode && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT> ) ) return true ;


<s> OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand


<s> NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) .


<s> for ( i = <NUM_LIT> ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = <NUM_LIT> ; else if ( IN_RANGE ( value , - <NUM_LIT> ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst


<s> case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , DL , IsTailCall , DAG ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; bool IsPICCall = ( Subtarget . isABI_N64 ( ) || IsPIC ) ; bool GlobalOrExternal = false , InternalLinkage = false , IsCallReloc = false ; SDValue CalleeLo ; EVT Ty = Callee . getValueType ( ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( IsPICCall ) { const GlobalValue * Val = G -> getGlobal ( ) ; InternalLinkage = Val -> hasInternalLinkage ( ) ; if ( InternalLinkage ) Callee = getAddrLocal ( G , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ; else if ( LargeGOT ) { Callee = getAddrGlobalLargeGOT ( G , Ty , DAG , <STR_LIT> , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Val ) ) ; IsCallReloc = true ; } else { Callee = getAddrGlobal ( G , Ty , DAG , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Val ) ) ; IsCallReloc = true ; } } else Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( ) , <NUM_LIT> , <STR_LIT> ) ; GlobalOrExternal = true ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * Sym = S -> getSymbol ( ) ; if ( ! Subtarget . isABI_N64 ( ) && ! IsPIC ) Callee = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , <STR_LIT> ) ; else if ( LargeGOT ) { Callee = getAddrGlobalLargeGOT ( S , Ty , DAG , <STR_LIT> , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Sym ) ) ; IsCallReloc = true ; } else { Callee = getAddrGlobal ( S , Ty , DAG , <STR_LIT> , Chain , FuncInfo -> callPtrInfo ( Sym ) ) ; IsCallReloc = true ; } GlobalOrExternal = true ; } SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> , Chain ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain ) ; if ( IsTailCall ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys ,


<s> if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT> || IntWidth ==


<s> assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; Register StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo


<s> void <ISA_LIT>InstPrinter :: printZPRasFPR32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; O << getRegisterName ( Reg -


<s> if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Elt ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; return false


<s> ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = Mask . size ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle =


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( bool IsForTls ) { Register GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( * MF , IsForTls ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) , <NUM_LIT> )


<s> void <ISA_LIT>ELFStreamer :: EmitLabel ( MCSymbol * Symbol


<s> DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; Shuffle = SrcVT != MaskVT ? unsigned ( <STR_LIT> ) : unsigned ( <STR_LIT> ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> return ( int8x16_t ) __builtin_neon_vreinterpretv16qiti ( ( __builtin_neon_ti


<s> int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; } return


<s> } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc

== <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N ->


<s> unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * NewMBB ; unsigned UserOffset = GetOffsetOf ( UserMI ) + ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = MF . CreateMachineBasicBlock ( ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . CPEMI = BuildMI ( NewIsland , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; NumCPEs ++ ; BBOffsets [ NewIsland -> getNumber ( ) ] = BBOffsets [ NewMBB -> getNumber ( ) ] ; if ( isThumb && BBOffsets [ NewIsland -> getNumber (

) ] % <NUM_LIT> != <NUM_LIT> ) Size += <NUM_LIT> ;


<s> unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == <NUM_LIT> ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == <NUM_LIT> ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > <NUM_LIT> ) return


<s> if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ; return false


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; assert ( STI . isTargetWin64 ( ) && <STR_LIT> ) ; if ( ! MF . hasWinCFI ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock * NextMBB = MBB . getNextNode ( ) ; if ( NextMBB && ! NextMBB -> isEHFuncletEntry ( ) ) continue ; auto LastRealInstr = llvm :: find_if ( reverse ( MBB ) , isRealInstruction ) ; bool IsEmpty = LastRealInstr == MBB . rend ( ) ; bool IsCall = ! IsEmpty && isCallInstruction ( * LastRealInstr ) ; if ( IsEmpty || IsCall ) { LLVM_DEBUG ( { if ( IsCall ) { dbgs ( ) << <STR_LIT> ; LastRealInstr -> dump ( ) ; dbgs ( ) << '\n' ; } else { dbgs ( ) << <STR_LIT> ; MBB . dump ( ) ; } } ) ; MachineBasicBlock :: iterator MBBI = MBB


<s> rtx_insn * insn ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! loongarch_tls_symbol ) loongarch_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = loongarch_unspec_address ( sym , type ) ; start_sequence ( ) ; if ( type == SYMBOL_TLSLDM ) emit_insn ( loongarch_got_load_tls_ld ( a0 , loc ) ) ; else if ( type == SYMBOL_TLSGD ) emit_insn ( loongarch_got_load_tls_gd ( a0 , loc ) ) ; else gcc_unreachable ( ) ; insn = emit_call_insn ( gen_call_value_internal ( v0 , loongarch_tls_symbol , const0_rtx ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int64_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( ~ imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS , N -> getOperand ( <NUM_LIT> ) ) ; } } } else if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> ) { return AddCombineTo64bitMLAL ( N ,


<s> if ( flag_pic || ix86_cmodel == CM_LARGE || ! ( TARGET_64BIT || HAVE_AS_IX86_GOT32X ) || TARGET_MACHO || TARGET_SEH || TARGET_PECOFF || SYMBOL_REF_LOCAL_P ( call_op ) ) return false ; tree symbol_decl = SYMBOL_REF_DECL ( call_op ) ; if ( ! flag_plt || ( symbol_decl != NULL_TREE && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( symbol_decl ) ) ) ) return true ; return false


<s> unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( featureBits [ <STR_LIT> ] && ! featureBits [ <STR_LIT> ] ) { if ( Rt == <NUM_LIT> || Rt == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } else Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> ExceptionsType = ExceptionHandling :: Dwarf ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; AssemblerDialect = <NUM_LIT> ; SupportsDebugInformation = true


<s> void <ISA_LIT>ExpandPseudo :: CMSEClearGPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const SmallVectorImpl < unsigned > & ClearRegs , unsigned ClobberReg ) { if ( STI -> hasV8_1MMainlineOps ( ) ) { MachineInstrBuilder CLRM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned R : ClearRegs ) CLRM . addReg ( R , RegState :: Define ) ; CLRM . addReg ( <STR_LIT> , RegState :: Define ) ; CLRM . addReg ( <STR_LIT> , RegState


) __blci_u64 ( unsigned long long __X ) {


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF )


<s> return ( __m128d ) __builtin_ia32_gatherdiv2df ( src , base , ( __v2di ) index , mask


<s> unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> auto SubRegCopy = MIB . buildInstr ( TargetOpcode :: COPY , { To } , { } ) . addReg ( Copy . getReg ( <NUM_LIT> ) , <NUM_LIT> , SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( SubRegCopy .


<s> for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertMoves ( MBB


<s> assert ( ( FromW == <NUM_LIT> || FromW ==

<NUM_LIT> || FromW == <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; } } return


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT>


<s> if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) && ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; return BaseT :: getVectorInstrCost ( Opcode , ValTy , Index


<s> static SDValue LowerPredicateLoad ( SDValue Op , SelectionDAG & DAG ) { LoadSDNode * LD = cast < LoadSDNode > ( Op . getNode ( ) ) ; EVT MemVT = LD -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == Op . getValueType ( ) ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ; if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getMergeValues ( { Pred , Load . getValue ( <NUM_LIT>


<s> uint32_t Insn ; DecodeStatus Result ; Size = <NUM_LIT> ; if ( IsMicro<ISA_LIT> ) { Result = readInstruction16 ( Bytes , Address , Size , Insn , IsBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R616 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>16 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( isFP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Size = <NUM_LIT> ; if ( hasCOP3 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isGP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_GP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isPTR64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_PTR6432 , Instr , Insn , Address , this


<s> tree fndecl = current_function_decl ; tree fntype = TREE_TYPE ( fndecl ) ; tree fnargs = DECL_ARGUMENTS ( fndecl ) ; rtx next_arg_reg ; int i ; tree next_arg ; tree cur_arg ; CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; int store_args_on_stack = ( iq2000_can_use_return_insn ( ) ) ; if ( aggregate_value_p ( DECL_RESULT ( fndecl ) , fndecl ) && ! cfun -> returns_pcc_struct && targetm . calls . struct_value_rtx ( TREE_TYPE ( fndecl ) , <NUM_LIT> ) == <NUM_LIT> ) { tree type = build_pointer_type ( fntype ) ; tree function_result_decl = build_decl ( BUILTINS_LOCATION , PARM_DECL , NULL_TREE , type ) ; DECL_ARG_TYPE ( function_result_decl ) = type ; DECL_CHAIN ( function_result_decl ) = fnargs ; fnargs = function_result_decl ; } INIT_CUMULATIVE_ARGS ( args_so_far_v , fntype , NULL_RTX , <NUM_LIT> , <NUM_LIT> ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; regno = GP_ARG_FIRST ; for ( cur_arg = fnargs ; cur_arg != <NUM_LIT> ; cur_arg = next_arg ) { tree passed_type = DECL_ARG_TYPE ( cur_arg ) ; machine_mode passed_mode = TYPE_MODE ( passed_type ) ; rtx entry_parm ; if ( TREE_ADDRESSABLE ( passed_type ) ) { passed_type = build_pointer_type ( passed_type ) ; passed_mode = Pmode ; } function_arg_info arg ( passed_type , passed_mode , true ) ; entry_parm = iq2000_function_arg ( args_so_far , arg ) ; iq2000_function_arg_advance ( args_so_far , arg ) ; next_arg = DECL_CHAIN ( cur_arg ) ; if ( entry_parm && store_args_on_stack ) { if ( next_arg == <NUM_LIT> && DECL_NAME ( cur_arg ) && ( strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) == <NUM_LIT> || strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) == <NUM_LIT> ) ) { last_arg_is_vararg_marker = <NUM_LIT> ; break ; } else { int


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Kind ) ; for ( SmallVectorImpl < std :: pair < unsigned , unsigned > > :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++ I ) Op -> Registers . push_back ( I -> second ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return


<s> SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Enable<ISA_LIT>LongCalls ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Enable<ISA_LIT>LongCalls


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc =


<s> SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; SDValue Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg = DAG . getConstant ( ~ <NUM_LIT> , MaskVT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment


<s> SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 ,


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect (


<s> PCLabelMap . insert ( std :: make_pair


<s> SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; return SDValue ( Res , <NUM_LIT> ) ; } unsigned isDev = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! isDev ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; unsigned Op1 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op2 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op3 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op4 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! Op1 && ! Op2 && ! Op3 && Op4 ) return DAG . getNode ( <STR_LIT> , dl


<s> void SVEIntrinsicOpts :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired <


<s> assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO .


<s> bool <ISA_LIT>TargetLowering :: IsGlobalInSmallSection ( GlobalValue * GV ) { const TargetData * TD = getTargetData ( ) ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypeAllocSize


<s> const MCSymbol * <ISA_LIT>ELFObjectWriter :: ExplicitRelSym ( const MCAssembler & Asm , const MCValue & Target , const MCFragment & F , const MCFixup & Fixup , bool IsPCRel ) const { llvm_unreachable ( <STR_LIT> )


<s> bool NeedSplit = ( BMI != & MI ) || ! hasFallthrough ( * MBB ) ; if ( BMI != & MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> isUnconditionalBranch ( ) ) { MachineBasicBlock * NewDest = getDestBlock ( * BMI ) ; if ( isBlockInRange ( MI , * NewDest ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; changeBranchDestBlock ( * BMI , * DestBB ) ; int NewSize = insertInvertedConditionalBranch ( * MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , MI , * NewDest ) ; int OldSize = TII -> getInstSizeInBytes ( MI ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += ( NewSize - OldSize ) ; MI . eraseFromParent ( )


<s> SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; } Res = Inst


<s> __inline__ static unsigned long long sh_media_MSHARD_W ( unsigned long long mm , unsigned int mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm )


<s> const unsigned FixupKind = Fixup . getKind ( ) ; switch ( FixupKind ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( ( qword ) ( vec_mulo ( ( vec_short8 ) ( a ) , (


<s> EmitByte ( static_cast < uint8_t > ( SizeInWords - <NUM_LIT> )


<s> Register VReg1 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI )


<s> MIB . buildCopy ( { SrcReg } , { I . getOperand ( <NUM_LIT> ) } ) ; RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; } if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto SHA1Inst = MIB . buildInstr ( <STR_LIT> , { DstReg } , { SrcReg } ) ; constrainSelectedInstRegOperands ( * SHA1Inst , TII , TRI , RBI ) ; if ( DstReg != I . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MIB . buildCopy ( { I . getOperand ( <NUM_LIT> ) } , { DstReg } ) ; RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; } I . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t Key = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register DiscReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto DiscVal = getIConstantVRegVal ( DiscReg , MRI ) ; bool IsDiscZero = DiscVal . hasValue ( ) && DiscVal -> isNullValue ( ) ; if ( Key > <NUM_LIT> ) return false ; unsigned Opcodes [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opcode = Opcodes [ IsDiscZero ] [ Key ] ; auto PAC = MIB . buildInstr ( Opcode , { DstReg } , { ValReg } ) ; if ( ! IsDiscZero ) { PAC . addUse ( DiscReg ) ; RBI . constrainGenericRegister ( DiscReg , <STR_LIT> , MRI ) ; } RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; I . eraseFromParent


<s> if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) { return gen_rtx_PARALLEL ( DImode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode ) ) return spe_build_register_parallel (


<s> static SDValue LowerFABSorFNEG ( SDValue Op , SelectionDAG & DAG ) { assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool IsFABS = ( Op . getOpcode ( ) == <STR_LIT> ) ; if ( IsFABS ) for ( SDNode * User : Op -> uses ( ) ) if ( User -> getOpcode ( ) == <STR_LIT> ) return Op ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; bool IsF128 = ( VT == <STR_LIT> ) ; MVT LogicVT ; MVT EltVT ; if ( VT . isVector ( ) ) { LogicVT = VT ; EltVT = VT . getVectorElementType ( ) ; } else if ( IsF128 ) { LogicVT = <STR_LIT> ; EltVT = VT ; } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; const fltSemantics & Sem = EltVT == <STR_LIT> ? APFloat :: IEEEdouble


<s> APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned Idx = <NUM_LIT> , e = Src . getNumOperands ( ) ; Idx < e ; ++ Idx ) { if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Subtarget . hasSSE2 ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( SDValue NotSrc = IsNOT ( Src , DAG ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; NotSrc = DAG . getBitcast ( SrcVT , NotSrc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , NotSrc ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue ( NumBits ) ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue (


<s> MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { continue ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> || ! VA . isRegLoc ( ) || ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } else { switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr16 ( SDNode * Parent , SDValue N , SDValue & Base ,


<s> return __builtin_aarch64_roundv4sf ( __a )


<s> SDValue VecIn2 ; SmallVector < unsigned , <NUM_LIT> > InsertIndices ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Opc = Op . getOperand ( i ) . getOpcode ( ) ; if ( Opc == <STR_LIT> ) continue ; if ( Opc != <STR_LIT> ) { if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; if ( VecIn1 . getNode ( ) == <NUM_LIT> ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( VecIn2 . getNode ( ) == <NUM_LIT> ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } unsigned Idx = cast < ConstantSDNode > ( ExtIdx ) -> getZExtValue ( ) ; if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; } if ( VecIn1 . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; VecIn2 = VecIn2 . getNode ( ) ? VecIn2 : DAG . getUNDEF ( VT ) ; SDValue NV = DAG . getVectorShuffle ( VT , DL , VecIn1 , VecIn2 , & Mask [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> , e = InsertIndices . size ( ) ; i != e ; ++ i ) { unsigned Idx = InsertIndices [


<s> return __builtin_mve_vorrq_m_sv4si ( __arm_vuninitializedq_s32 ( ) ,


<s> if ( TARGET_SVE ) sizes -> safe_push ( BYTES_PER_SVE_VECTOR ) ; sizes -> safe_push ( <NUM_LIT> ) ; sizes -> safe_push


<s> __i1 = __i1 << <NUM_LIT> | ( unsigned char ) __b4 ; __i0 = ( unsigned char ) __b3 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b2 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS

, Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , DL ( computeDataLayout ( is64bit ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) {


<s> if ( ! C ) return Op ; switch ( Op -> getOpcode ( ) ) { default : return Op ; case <STR_LIT> : if ( ( C -> getZExtValue ( ) >> Bit ) & <NUM_LIT> ) return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; return Op ; case <STR_LIT> : if ( C -> getZExtValue ( ) <= Bit && ( Bit - C -> getZExtValue ( ) ) < Op -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { Bit = Bit - C -> getZExtValue ( ) ; return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; } return Op ; case <STR_LIT> : Bit = Bit + C -> getZExtValue


<s> if ( eop0 . ext_code == SIGN_EXTEND && eop1 . ext_code == SIGN_EXTEND && eop0 . from_mode == subreg_mode && eop1 . from_mode == subreg_mode ) { emit_insn ( gen_tstsi_t ( eop0 . use_as_extended_reg ( curr_insn ) , eop1 . use_as_extended_reg ( curr_insn ) ) ) ; return ; } if ( eop0 . ext_code != UNKNOWN && eop1 . ext_code == UNKNOWN ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; rtx tmp0 = gen_reg_rtx


<s> for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI


<s> static bool EqualTypeSize ( Value * V ) { return V -> getType ( ) -> getScalarSizeInBits ( ) == <ISA_LIT>CodeGenPrepare ::


<s> U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : { return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int64_t TmpOffset = Addr . getOffset ( ) ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = GTI . getStructTypeOrNull ( ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . setOffset ( TmpOffset ) ; if ( computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap


<s> static void LowerMemOpCallTo ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue Arg , SDValue PtrOff , int SPDiff , unsigned ArgOffset , bool is<ISA_LIT>64 , bool isTailCall , bool isVector , SmallVector < SDValue , <NUM_LIT> > & MemOpChains , SmallVector < TailCallArgumentInfo , <NUM_LIT> > & TailCallArguments , SDLoc dl ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; if ( ! isTailCall ) { if ( isVector ) { SDValue StackPtr ; if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c


<s> JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; EmitBranchToAt ( ( intptr_t ) Addr , ( intptr_t ) Fn , false , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> * <NUM_LIT> ) ; return Addr ; } void * Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( is64Bit ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } else if ( Subtarget . isDarwinABI ( ) ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE (


<s> return ( __m64 ) __builtin_arm_wmaxub ( ( __v8qi ) __A , ( __v8qi )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , is64Bit , OL ) { initAsmInfo (


<s> V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget ,


<s> { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , } ; static const uint16_t UCvtOpc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false ; MVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( DstVT ) ; Register ImplicitDefReg = createResultReg (


<s> EVT ValVT = VA . getValVT ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , getTargetMachine ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MinReservedArea = std :: max ( MinReservedArea , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( false , false ) ) ; unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; MinReservedArea = ( MinReservedArea + AlignMask ) & ~ AlignMask ; FI -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const unsigned GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs =


<s> unsigned NumBytes = NumVecs * VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLdDup ; if ( is64BitVector || NumVecs == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; VLdDup = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveWord ( unsigned Size , SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . ParseExpression


<s> if ( TARGET_DIRECT_MOVE_64BIT && ! lra_in_progress && ! reload_completed && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode


<s> void PreAnalyzeCallResultForF128 ( const SmallVectorImpl < <STR_LIT> > &

Ins , const TargetLowering :: CallLoweringInfo & CLI ) {


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_extractsubreg ( MVT RetVT , unsigned Op0 , bool Op0IsKill , uint32_t Idx ) { unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( Op0


<s> const BranchInst * BI = cast < BranchInst > ( I ) ; MachineBasicBlock * BrBB = FuncInfo . MBB ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; FastEmitBranch ( Target , DL ) ; return true


<s> static bool sparc_vector_mode_supported_p ( enum machine_mode


<s> case SMM_TSO : implied |= StoreStore ; if ( load_store == <NUM_LIT> && before_after == <NUM_LIT> ) implied |= StoreLoad ; case SMM_PSO : implied |= LoadLoad | LoadStore ; if ( load_store == <NUM_LIT> && before_after == <NUM_LIT> ) implied |= StoreLoad | StoreStore ; case SMM_RMO : break ; default : gcc_unreachable ( ) ; } if ( before_after & <NUM_LIT> ) { if ( is_mm_release ( model ) || is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) { if ( load_store & <NUM_LIT> ) mm |= LoadLoad | StoreLoad ; if ( load_store & <NUM_LIT> ) mm |= LoadStore | StoreStore ; } } if ( before_after & <NUM_LIT> ) { if ( is_mm_acquire ( model ) || is_mm_acq_rel ( model ) || is_mm_seq_cst


<s> unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; computeBlockSize ( UserMBB ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> GetInstSizeInBytes ( UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand


<s> unsigned NumElts = InVT . getVectorNumElements ( ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl (


<s> MBOpt = o . MBOpt ; break ; case k_Memory : Memory = o . Memory ; break ; case k_PostIndexRegister : PostIdxReg = o . PostIdxReg ; break ; case k_MSRMask : MMask = o . MMask ; break ; case k_ProcIFlags : IFlags = o . IFlags ; break ; case k_ShifterImmediate : ShifterImm = o . ShifterImm ; break ; case k_ShiftedRegister : RegShiftedReg = o . RegShiftedReg ; break ; case k_ShiftedImmediate : RegShiftedImm = o . RegShiftedImm ; break ; case k_RotateImmediate : RotImm = o . RotImm ; break ; case k_BitfieldDescriptor : Bitfield = o


<s> static unsigned getBasePointerSaveOffset ( bool is<ISA_LIT>64 , bool isDarwinABI ) { if ( isDarwinABI ) return is<ISA_LIT>64 ? - <NUM_LIT> : -


<s> unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( unsigned ) M [ i ] != Idx || ( unsigned ) M [ i + <NUM_LIT> ]


<s> Disp = DAG . getTargetConstant ( ( ( int ) imm & <NUM_LIT> ) >> <NUM_LIT> , <STR_LIT> ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { if ( ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( ( unsigned short ) Imm >> <NUM_LIT> , getPointerTy ( ) ) ; Base = DAG . getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr >> <NUM_LIT> , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getTargetNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } } Disp = DAG . getTargetConstant ( <NUM_LIT> , getPointerTy ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base = N ; return


<s> if ( TARGET_THUMB_P ( opts -> x_target_flags ) && TARGET_CALLEE_INTERWORKING ) opts -> x_target_flags |= MASK_INTERWORK ; cl_optimization * to = TREE_OPTIMIZATION ( init_optimize ) ; if ( ! opts_set -> x_arm_restrict_it ) opts -> x_arm_restrict_it = arm_arch8 ; if ( ! TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_arm_restrict_it = <NUM_LIT> ; if ( ! opts_set -> x_unaligned_access ) { opts -> x_unaligned_access = ( TARGET_32BIT_P ( opts -> x_target_flags ) && arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ; } else if ( opts -> x_unaligned_access == <NUM_LIT> && ! ( arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; opts -> x_unaligned_access = <NUM_LIT> ; } if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_schedule_insns = <NUM_LIT> ; else opts -> x_flag_schedule_insns = to -> x_flag_schedule_insns ; if ( optimize_function_for_size_p ( cfun ) && TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_flag_shrink_wrap = false ; else opts -> x_flag_shrink_wrap = to ->


<s> for ( auto & BB : F ) { for ( auto & I : BB ) { if ( auto * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( R -> getOperandUse (

<NUM_LIT> ) , PromotablePHINodes , Bool2IntMap ) ;


<s> SDLoc dl ( SVOp ) ; MVT VT = SVOp -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane ) : - <NUM_LIT> ; int EltIdx = SVOp -> getMaskElt ( i ) ; if ( ( EltIdx < <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx < <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx < <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return SDValue ( ) ; } MVT BlendVT = VT ; if ( EltVT == <STR_LIT> || ( EltVT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) { BlendVT = <STR_LIT> ( <STR_LIT> ( EltVT . getSizeInBits ( ) ) ,


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat (


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) )

. addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ;


<s> Mangler & Mang ; AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI


<s> CommentString = <STR_LIT> ; CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = true ; StackGrowsUp = false ; DollarIsPC =


<s> return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getTargetNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } Disp = DAG . getTargetConstant ( <NUM_LIT> , getPointerTy ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base = N ; return true


<s> void <ISA_LIT>FrameInfo :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; static const unsigned HighFPRs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; bool HighFPRsUsed = false ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( HighFPRs ) ; i != e ; ++ i ) HighFPRsUsed |= MRI . isPhysRegUsed ( HighFPRs


<s> static inline unsigned getThumbImmValShift ( unsigned Imm ) { if ( ( Imm & ~ <NUM_LIT> )


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF .

getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> APInt MaskSrc = APInt :: getBitsSetWithWrap ( <NUM_LIT> , <NUM_LIT> - MESrc - <NUM_LIT> , <NUM_LIT> - MBSrc ) ; APInt RotatedSrcMask = MaskSrc . rotl ( SHMI ) ; APInt FinalMask = RotatedSrcMask & MaskMI ; uint32_t NewMB , NewME ; bool Simplified = false ; if ( FinalMask . isZero ( ) ) { bool Is64Bit = ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ; Simplified = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . setDesc ( get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; } else { MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; MI . setDesc ( get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( SrcMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI . getOperand ( <NUM_LIT> ) . setIsKill ( true ) ; SrcMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; } else MI . getOperand ( <NUM_LIT> )


<s>
assert
(
!
Operands
.
empty
(
)
&&
<STR_LIT>
)
;
<ISA_LIT>Operand
&
Op
=
static_cast
<
<ISA_LIT>Operand
&
>
(
*
Operands
[
<NUM_LIT>
]
)
;
assert
(
Op
.
isToken
(
)
&&
<STR_LIT>
)
;
ArrayRef
<
SMRange
>
EmptyRanges
=
;
MatchFPUWaitAlias
(
IDLoc
,
Op
,
Operands
,
Out
,
MatchingInlineAsm
)
;
bool
WasOriginallyInvalidOperand
=
false
;
MCInst
Inst
;
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
Match_Success
:
if
(
!
validateInstruction
(
Inst
,
Operands
)
)
return
true
;
if
(
!
MatchingInlineAsm
)
while
(
processInstruction
(
Inst
,
Operands
)
)
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
ErrorInfo
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
uint64_t
ErrorInfoMissingFeature
=
<NUM_LIT>
;
unsigned
Match
[
<NUM_LIT>
]
;
for
(
unsigned
I
=
<NUM_LIT>
,
E
=
array_lengthof
(
Match
)
;
I
!=
E
;
++
I
)
{
Tmp
.
back
(
)
=
Suffixes
[
I
]
;
Match
[
I
]
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
;
if
(
Match
[
I
]
==
Match_MissingFeature
)
ErrorInfoMissingFeature
=
ErrorInfoIgnore
;
}
Op
.
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
std
::
count
(
std
::
begin
(
Match
)
,
std
::
end
(
Match
)
,
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>


<s> static bool mips_valid_pointer_mode ( scalar_int_mode mode ) { return mode == SImode || ( TARGET_64BIT && mode ==


<s> } else { SDValue Cst = DAG . getConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } } else if ( VT . is256BitVector ( ) ) { if ( Subtarget -> hasInt256 ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { SDValue Cst = DAG . getConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getScalarType ( ) == <STR_LIT> ) { assert ( ( Subtarget -> hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget -> hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> std :: swap ( LHS , RHS ) ; Res = DAG . getCommutedVectorShuffle ( * SVN ) ; Mask = cast < ShuffleVectorSDNode > ( Res ) -> getMask ( ) ; } SmallVector < int , <NUM_LIT> > ShuffV ( Mask . begin ( ) , Mask . end ( ) ) ; SDValue SToVLHS = isScalarToVec ( LHS ) ; SDValue SToVRHS = isScalarToVec ( RHS ) ; if ( SToVLHS || SToVRHS ) { int NumEltsIn = SToVLHS ? SToVLHS . getValueType ( ) . getVectorNumElements ( ) : SToVRHS . getValueType ( ) . getVectorNumElements ( ) ; int NumEltsOut = ShuffV . size ( ) ; int LHSMaxIdx = - <NUM_LIT> ; int RHSMinIdx = - <NUM_LIT> ; int RHSMaxIdx = - <NUM_LIT> ; int HalfVec = LHS . getValueType ( ) . getVectorNumElements ( ) / <NUM_LIT> ; if ( SToVLHS ) { LHSMaxIdx = NumEltsOut / NumEltsIn ; SToVLHS = getSToVPermuted ( SToVLHS , DAG ) ; if ( SToVLHS . getValueType ( ) != LHS . getValueType ( ) ) SToVLHS =

DAG . getBitcast ( LHS . getValueType ( ) , SToVLHS ) ;


<s> I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ; if ( Align ) { SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( - (


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine >


<s> static MCDisassembler * createThumbDisassembler ( const Target & T


<s> bool HasMultipleSuccs = false ; BB2BrMap BrMap ; std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if ( ! examinePred ( * * PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * MBB . getParent ( ) ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst


<s> if ( TREE_CODE ( arg_mask ) != INTEGER_CST ) return false ; unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW ( arg_mask ) ; if ( ( mask | ( HOST_WIDE_INT_M1U << elems ) )


<s> void addVectorIndex8Operands ( MCInst & Inst


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectIntAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { return selectAddrRegImm ( Addr , Base , Offset ) || selectAddrDefault ( Addr ,


<s> __vector signed int c ; __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_vmsumshm ( a , b , zero ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t )


<s> SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , TLS , LowerGlobalAddressWindows ( Op


<s> if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass ( create<ISA_LIT>Os16 ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( get<ISA_LIT>Subtarget ( ) . in<ISA_LIT>16HardFloat ( ) ) addPass ( create<ISA_LIT>16HardFloat ( get<ISA_LIT>TargetMachine


<s> void altivec_expand_lvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , load ,


<s> ELFFileFormat * file_format = getOutputFormat ( ) ; file_format -> getRelaPlt ( ) . setSize ( m_pRelPLT -> numOfRelocs (


<s> short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm & <NUM_LIT> ) == <NUM_LIT> ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( ( int ) imm & <NUM_LIT> ) >> <NUM_LIT> , <STR_LIT> ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { if ( ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( ( unsigned short ) Imm >> <NUM_LIT> , getPointerTy ( ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue (


<s> case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformINTRINSIC_WO_CHAINCombine ( N , DAG , Subtarget


<s> EVT VT ; for ( auto * Use : V . getNode ( ) -> uses ( ) ) if ( auto * MemNode = dyn_cast < MemSDNode >

( Use ) ) if ( MemNode -> getMemoryVT ( ) != VT && VT != EVT ( ) ) return false ;


<s> if ( MayStore ) return ! Defs . insert ( V ) || Uses . count ( V ) || SeenNoObjStore || SeenNoObjLoad ; Uses . insert ( V ) ; return Defs . count (


<s> MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; if ( IsCalleeGlobalPIC ) { Register CalleeReg = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachineInstr * CalleeGlobalValue = MIRBuilder . buildGlobalValue ( CalleeReg , Info . Callee . getGlobal ( ) ) ; if ( ! Info . Callee . getGlobal ( ) -> hasLocalLinkage ( ) ) CalleeGlobalValue -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; MIB . addUse ( CalleeReg ) ; } else MIB . add ( Info . Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( Info . OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto & Arg : Info . OrigArgs ) splitToValueTypes ( Arg , ArgInfos , DL , Info . CallConv ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; bool IsCalleeVarArg = false ; if ( Info . Callee . isGlobal ( ) ) { const Function * CF = static_cast < const Function * > ( Info . Callee . getGlobal ( ) ) ; IsCalleeVarArg = CF -> isVarArg ( ) ; } <ISA_LIT>CCState CCInfo ( Info . CallConv , IsCalleeVarArg , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , Align ( <NUM_LIT> ) ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; <ISA_LIT>OutgoingValueAssigner Assigner ( TLI . CCAssignFnForCall ( ) , Call , false ) ; if ( ! determineAssignments ( Assigner , ArgInfos , CCInfo ) ) return false ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! handleAssignments ( ArgHandler , ArgInfos , CCInfo , ArgLocs , MIRBuilder ) ) return false ; unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; unsigned StackAlignment = F . getParent ( ) -> getOverrideStackAlignment ( ) ; if ( ! StackAlignment ) { const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; StackAlignment = TFL -> getStackAlignment ( ) ; } NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; if ( IsCalleeGlobalPIC ) { MIRBuilder . buildCopy ( Register ( <STR_LIT> ) , MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseRegForGlobalISel ( MF ) ) ; MIB . addDef ( <STR_LIT> , RegState ::


<s> uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElemsPerChunk = VecWidth / VecVT . getScalarSizeInBits ( ) ; return getI8Imm ( Index / NumElemsPerChunk ,


<s> static inline bool hasInefficientLEABaseReg ( const MachineOperand & Base , const MachineOperand & Index ) { return Base . isReg ( ) && isInefficientLEAReg ( Base . getReg ( ) ) && Index . isReg

( ) && Index . getReg ( ) != <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { if ( Subtarget . hasVector ( ) ) VerifyVectorTypes ( Outs ) ; for ( auto & Out : Outs ) if ( Out . ArgVT == <STR_LIT> ) return false ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , isVarArg , MF , RetLocs , Context ) ; return RetCCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> if ( ! isShiftOrExtend ( ) ) return false ; <STR_LIT> Ext = ShiftExtend . ShiftType ; if ( RmSize == <NUM_LIT> && ! ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) return false ; if ( RmSize == <NUM_LIT> && ! ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) return false ; return ShiftExtend . Amount == Log2_32 ( MemSize ) || ShiftExtend


<s> if ( RB == & <STR_LIT> ) return true ; if ( RB == & <STR_LIT> ) return false ; if ( ! MI . isPHI ( ) || Depth > MaxFPRSearchDepth ) return false ; return any_of ( MI . explicit_uses ( ) , [ & ] ( const MachineOperand


<s> default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return


<s> void addImm1_63Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr >


<s> const char * cpu = TREE_STRING_POINTER ( arg ) ; rtx cpuid = NULL_RTX ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_is_info ) ; i ++ ) if ( strcmp ( cpu , cpu_is_info [ i ] . cpu ) == <NUM_LIT> ) { cpuid = GEN_INT ( cpu_is_info [ i ] . cpuid + _DL_FIRST_PLATFORM ) ; break ; } if ( cpuid == NULL_RTX ) { error ( <STR_LIT> , cpu , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx platform = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( TCB_PLATFORM_OFFSET ) ) ) ; emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BUILTIN_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask =


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . Num


<s> } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else


<s> Inst . addOperand ( MCOperand :: createImm ( Add -


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM =


<s> if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg =


<s> SDValue Dst = Op . getOperand ( <NUM_LIT> ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; Val = DAG . getAnyExtOrTrunc ( Val , DL , <STR_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; auto Alignment = Node -> getMemOperand ( ) -> getAlign ( ) ; bool IsVol = Node -> isVolatile ( ) ; auto DstPtrInfo = Node -> getPointerInfo ( ) ; const auto & SDI = static_cast < const <ISA_LIT>SelectionDAGInfo


<s> int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , MemoryTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy

-> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) } ) ;


<s> vec_uchar16 d ; d = vec_and ( ( vec_uchar16 ) ( a ) ,


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue


<s> unsigned Opc ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addReg ( CondReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I ->


<s> uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize


<s> unsigned i ; unsigned nunits = GET_MODE_NUNITS ( mode ) ; unsigned bitsize = GET_MODE_BITSIZE ( inner ) ; unsigned mask = GET_MODE_MASK ( inner ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - <NUM_LIT> ) ; HOST_WIDE_INT val = INTVAL ( last ) ; HOST_WIDE_INT splat_val = val ; HOST_WIDE_INT msb_val = val > <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= copies ; i *= <NUM_LIT> ) { HOST_WIDE_INT small_val ; bitsize /= <NUM_LIT> ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= <NUM_LIT> || ( step == <NUM_LIT> && copies == <NUM_LIT> ) ) ) ; else return false ; for ( i = <NUM_LIT> ; i < nunits - <NUM_LIT> ; ++ i ) { HOST_WIDE_INT desired_val ; if ( ( ( i + <NUM_LIT> ) & ( step

- <NUM_LIT> ) ) == <NUM_LIT> ) desired_val = val ;


<s> int FinalState ; if ( & F . getEntryBlock ( ) == BB ) InitialState = FinalState = ParentBaseState ; for ( Instruction & I : * BB ) { CallSite CS ( & I ) ; if ( ! isStateStoreNeeded ( Personality , CS ) ) continue ; int State = getStateForCallSite ( BlockColors , FuncInfo , CS ) ; if ( InitialState == OverdefinedState ) InitialState = State ; FinalState = State ; } if ( InitialState == OverdefinedState ) { Worklist . push_back ( BB ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << InitialState << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << FinalState << '\n' ) ; InitialStates . insert ( { BB , InitialState } ) ; FinalStates . insert ( { BB , FinalState } ) ; } while ( ! Worklist . empty ( ) ) { BasicBlock * BB = Worklist . front ( ) ; Worklist . pop_front ( ) ; if ( InitialStates . count ( BB ) != <NUM_LIT> ) continue ; int PredState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; if ( PredState == OverdefinedState ) continue ; InitialStates . insert ( { BB , PredState } ) ; FinalStates . insert ( { BB , PredState } ) ; for ( BasicBlock * SuccBB : successors ( BB ) ) Worklist . push_back ( SuccBB ) ; } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB


<s> MVT VT = <STR_LIT> ; TransposedMatrix . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskLow ; SmallVector < int , <NUM_LIT> > MaskLowTemp1 , MaskLowWord ; SmallVector < int , <NUM_LIT> > MaskHighTemp1 , MaskHighWord ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { MaskLow . push_back ( i ) ; MaskLow . push_back ( i + <NUM_LIT> ) ; } createUnpackShuffleMask ( VT , MaskLowTemp1 , true , false ) ; createUnpackShuffleMask ( VT , MaskHighTemp1 , false , false ) ; scaleShuffleMask ( <NUM_LIT> , MaskHighTemp1 , MaskHighWord ) ; scaleShuffleMask ( <NUM_LIT> , MaskLowTemp1 , MaskLowWord


<s> return __builtin_mve_vcmpgtq_sv8hi ( __a ,


<s> unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Ra = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Ra , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return