<s> info . shift = <NUM_LIT> ; if ( ! aarch64_classify_address ( & info , x , mode , c , false ) ) { if ( GET_CODE ( x ) == CONST || GET_CODE ( x ) == SYMBOL_REF ) { int cost_symbol_ref = rtx_cost ( x , Pmode , MEM , <NUM_LIT> , speed ) ; cost_symbol_ref /= COSTS_N_INSNS ( <NUM_LIT> ) ; return cost_symbol_ref + addr_cost -> imm_offset ; } else { return addr_cost -> register_offset ; } } switch ( info . type ) { case ADDRESS_LO_SUM : case ADDRESS_SYMBOLIC : case ADDRESS_REG_IMM : cost += addr_cost -> imm_offset ; break ; case ADDRESS_REG_WB : if ( c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY ) cost += addr_cost -> pre_modify ; else if ( c == POST_INC || c == POST_DEC || c == POST_MODIFY ) cost += addr_cost -> post_modify ; else gcc_unreachable ( ) ; break ; case ADDRESS_REG_REG : cost += addr_cost -> register_offset ; break ; case ADDRESS_REG_SXTW : cost += addr_cost -> register_sextend ; break ; case ADDRESS_REG_UXTW : cost += addr_cost -> register_zextend ; break ; default : gcc_unreachable ( ) ; } if ( info . shift > <NUM_LIT> ) { switch ( GET_MODE_BITSIZE ( mode ) ) { case <NUM_LIT> : cost += addr_cost -> addr_scale_costs . hi ; break ; case <NUM_LIT> : cost += addr_cost -> addr_scale_costs . si ; break ; case <NUM_LIT> : cost += addr_cost ->


<s> SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MachineFrameInfo & MFI = DAG . getMachineFunction ( ) .


<s> unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ; return S


<s> const ConstantFP * FPImm = getConstantFPVRegVal ( RHS , MRI ) ; bool ShouldUseImm = FPImm && ( FPImm -> isZero ( ) && ! FPImm -> isNegative ( ) ) ; auto IsEqualityPred = [ ] ( CmpInst :: Predicate P ) { return P == CmpInst :: FCMP_OEQ || P == CmpInst :: FCMP_ONE || P == CmpInst :: FCMP_UEQ || P == CmpInst :: FCMP_UNE ; } ; if ( ! ShouldUseImm && Pred && IsEqualityPred ( * Pred ) ) { const ConstantFP * LHSImm = getConstantFPVRegVal ( LHS , MRI ) ; if ( LHSImm && ( LHSImm -> isZero ( ) && ! LHSImm -> isNegative ( ) ) ) { ShouldUseImm = true ; std :: swap ( LHS , RHS ) ; } } unsigned CmpOpcTbl [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned CmpOpc = CmpOpcTbl [ ShouldUseImm ] [ OpSize == <NUM_LIT> ] ; auto CmpMI = MIRBuilder . buildInstr ( CmpOpc ) . addUse ( LHS ) ; if ( ! ShouldUseImm ) CmpMI . addUse ( RHS ) ; constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; return &


<s> } nopnds ++ ; } switch ( fcode ) { case HTM_BUILTIN_TENDALL : case HTM_BUILTIN_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; case HTM_BUILTIN_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; op [ nopnds ++ ] = gen_rtx_REG ( mode , htm_spr_regno ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds += <NUM_LIT> ; gcc_assert ( nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS ) ; } switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; if ( attr & RS6000_BTC_CR ) { if ( fcode == HTM_BUILTIN_TBEGIN ) { rtx scratch = gen_reg_rtx


<s> vpaddq_s8 ( int8x16_t a , int8x16_t b ) { int8x16_t result


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! <ISA_LIT>FI -> globalBaseRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = ( const TargetRegisterClass * ) & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC


<s> const LDSymbol * getGOTSymbol ( ) const { return m_pGOTSymbol


<s> vpadalq_u16 ( uint32x4_t a , uint16x8_t b ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> for ( auto & Arg : Args ) ArgTys . push_back ( <STR_LIT> ( Arg . getType ( ) ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; return handleAssignments ( MIRBuilder , AssignFn , ArgTys , VRegs , [ ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; MIRBuilder . buildCopy ( ValReg , PhysReg ) ; } )


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } for ( unsigned i = <NUM_LIT> ; i < Info . size ( ) ; i ++ ) { if ( Info [ i ] . isSpilledToReg ( ) ) continue ; int FrIdx = Info [ i ] . getFrameIdx (


<s> static std :: string getInstrName ( const Value * I , StringRef Suffix ) { assert ( I && <STR_LIT> ) ; if ( I -> hasName ( ) ) return ( I ->


<s> static bool is<ISA_LIT>LogicalCmp ( SDValue Op ) { unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ; return false


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_loadu_epi8 ( void const * __P ) { return ( __m128i ) ( * ( __v16qi_u * ) __P


<s> PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> EVT VT = Op . getValueType ( ) ; SDValue fl1 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( VT . getSizeInBits (


<s> Inst . addOperand ( MCOperand :: CreateImm ( Insn << <NUM_LIT> ) ) ; return MCDisassembler


<s> bool isNeonVectorRegLo ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg


<s> return __builtin_mve_vcmpeqq_v16qi ( ( int8x16_t ) __a ,


<s> if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned

> ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ;


<s> case FlagArithMnemonic :: SBB : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; case FlagArithMnemonic :: ADOX : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; } unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void ) AddI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddI -> dump ( ) ) ; ++ NumAddsInserted


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> } unsigned Opcode = decodeThumbSideEffect ( IsThumb2 , insn ) ; <ISA_LIT>Format Format = <ISA_LIT>Formats [ Opcode ] ; Size = IsThumb2 ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( { errs ( ) << <STR_LIT> << Opcode << <STR_LIT> << <STR_LIT> ( Opcode ) << <STR_LIT> << stringFor<ISA_LIT>Format ( Format ) << '(' << ( int ) Format << <STR_LIT> ; showBitVector ( errs ( ) , insn ) ; } ) ; <ISA_LIT>BasicMCBuilder * Builder = CreateMCBuilder ( Opcode , Format ) ; if ( ! Builder ) return


<s> if ( rx_max_constant_size == <NUM_LIT> || rx_max_constant_size == <NUM_LIT> ) return true ; return IN_RANGE ( val , ( - <NUM_LIT> << ( rx_max_constant_size * <NUM_LIT> ) ) , ( <NUM_LIT> << ( rx_max_constant_size *


<s> if ( ! strict_p && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( ! strict_p && GET_CODE ( offset ) == SUBREG ) offset = SUBREG_REG ( offset ) ; if ( REG_P ( base ) && pru_regno_ok_for_base_p ( REGNO ( base ) , strict_p ) && ( ( CONST_INT_P ( offset ) && pru_valid_const_ubyte_offset ( mode , INTVAL ( offset ) ) ) || ( REG_P ( offset ) && pru_regno_ok_for_index_p (

REGNO ( offset ) , strict_p ) ) ) ) return true ;


<s> return __builtin_mve_vmulhq_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __b ,


<s> return reinterpret_cast < const <ISA_LIT>Subtarget & > ( DAG .


<s> unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( unsigned i = <NUM_LIT> , e = IB -> getNumSuccessors ( ) ; i != e ; ++ i ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ IB -> getSuccessor ( i ) ] ) ; return


<s> if ( isLEA ( MI ) ) LEAs [ getMemOpKey ( MI , <NUM_LIT> ) ] . push_back ( const_cast < MachineInstr * >


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHUFFLE_VECTOR ) ; auto MaybeLane = getSplatIndex ( MI ) ; if ( ! MaybeLane ) return false ; int Lane =


<s> MBBI = std :: prev ( I ) ; if ( FixInvalidRegPairOp ( MBB , MBBI ) ) continue ; ++ Position ; if ( isMemoryOp ( * MBBI ) ) { unsigned Opcode = MBBI -> getOpcode ( ) ; const MachineOperand & MO = MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned Base = getLoadStoreBaseOp ( * MBBI ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MBBI , PredReg ) ; int Offset = getMemoryOpOffset ( MBBI ) ; if ( CurrBase == <NUM_LIT> ) { CurrBase = Base ; CurrOpc = Opcode ; CurrPred = Pred ; MemOps . push_back ( MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } if ( CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred ) { bool Overlap = false ; if ( isLoadSingle ( Opcode ) ) { Overlap = ( Base == Reg ) ; if ( ! Overlap ) { for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugValue ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const


<s> const MCSection * FindAssociatedSection ( ) const override { return getSubExpr ( ) ->


<s> case RDSEED : case RDRAND : { SDVTList VTs = DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Intr . Opc0 , dl , VTs , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { DAG . getZExtOrTrunc ( Result , dl , Op -> getValueType ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , Op -> getValueType ( <NUM_LIT> ) ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , SDValue ( Result . getNode ( ) , <NUM_LIT> ) } ; SDValue isValid = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , Op -> getVTList ( ) , Result , isValid , SDValue ( Result . getNode ( ) , <NUM_LIT> ) ) ; } case GATHER : { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getGatherNode ( Intr . Opc0 , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case SCATTER : { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT>


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT VecVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Op0Casted = DAG . getNode ( <STR_LIT> , dl , VecVT , Op . getOperand (


<s> MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , SrcVT ) ) , DAG . getConstant ( BytesLeft , SizeVT ) , Align , isVolatile , AlwaysInline , false , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> switch ( MBB . back ( ) . getOpcode ( ) ) { case <STR_LIT> : case


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mulx_u64 ( unsigned long long __X , unsigned

long long __Y , unsigned long long * __P ) {


__m128d __Y , const int __P , const int __R ) {


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes


<s> static DecodeStatus decodeS8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodeSImmOperand < <NUM_LIT> > ( Inst , Imm


<s> return rs6000_hard_regno_nregs [ mode ] [


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> void LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI ) ; void LowerPATCHABLE_FUNCTION_EXIT ( const MachineInstr & MI ) ; void LowerPATCHABLE_TAIL_CALL ( const MachineInstr & MI ) ; void EmitXRayTable ( ) ; private : const MachineConstantPool * MCP = nullptr ; bool InConstantPool = false ; std :: map < const char * , const <STR_LIT> * > StubsNeeded ; void EmitSled ( const MachineInstr & MI , SledKind Kind ) ; bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; void emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; void emitInlineAsmStart ( ) const override ; void emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const override ; void EmitJal ( const MCSubtargetInfo & STI , MCSymbol * Symbol ) ; void EmitInstrReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( const MCSubtargetInfo & STI , unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( * this ) { } StringRef getPassName ( )


<s> APFloat RealVal ( APFloat :: IEEEdouble ( ) , ImmOp64 ) ; ImmOp64 = RealVal . bitcastToAPInt ( ) . getZExtValue


<s> return ( unsigned long long ) __builtin_sh_media_MCMPEQ_W ( ( v4hi ) mm , (


<s> if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) return false ; else if ( RHSC < <NUM_LIT> && RHSC >= - <NUM_LIT> ) return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg .


<s> return Kind == Memory && ( ! Mem . Size


<s> for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken


<s> bool hasUnsigned = Subtarget -> hasSSE41 ( ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ; bool hasSigned = Subtarget -> hasSSE41 ( ) || ( Subtarget -> hasSSE2 ( ) && VT == <STR_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : return hasUnsigned ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return hasUnsigned ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return hasSigned ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return hasSigned ? <STR_LIT> : <NUM_LIT> ; } } else if ( DAG . isEqualTo ( LHS , Cond . getOperand ( <NUM_LIT> ) ) && DAG . isEqualTo ( RHS , Cond . getOperand ( <NUM_LIT> ) ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : return hasUnsigned ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return hasUnsigned ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> void addVectorIndexBOperands ( MCInst & Inst , unsigned


<s> unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg || ! Src1Reg ) return false ; emitInst ( DivOpc ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) ; emitInst ( <STR_LIT> ) . addReg ( Src1Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg ) return false ; unsigned MFOpc = ( ISDOpcode == <STR_LIT> || ISDOpcode == <STR_LIT> ) ? <STR_LIT>


<s> bool isMovKSymbolG3 ( ) const { return isMovWSymbol ( <ISA_LIT>MCExpr


<s> unsigned <ISA_LIT>VectorTargetTransformInfo :: getNumberOfRegisters ( bool Vector ) const { const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget >


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < N > ( Imm )


<s> unsigned <ISA_LIT>TTIImpl :: getLoadStoreVecRegBitWidth ( unsigned ) const { return getRegisterBitWidth ( true


<s> return getTargetMachine ( ) . getOptLevel ( ) != <NUM_LIT>


<s> return gen_rtx_SET ( arg , gen_rtx_MEM ( word_mode , gen_rtx_POST_INC (


<s> static Target The<ISA_LIT>beTarget ; return The<ISA_LIT>beTarget


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; } else if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } else { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( Subtarget . isABI_N32 ( ) ) { const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> )


<s> static inline __ev64_opaque__ __ev_set_ufix32_fs_internal ( __ev64_opaque__ a , float b , uint32_t pos ) { __ev64_opaque__ v ; float other ; other = __ev_get_fs_internal ( a , pos ^ <NUM_LIT> ) ; v = __ev_create_ufix32_fs ( b , b


<s> cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Ins ) , DL , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , IntVT , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ) ; SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ANDed ) ; return OneBitOfTruth ; } } } } return SDValue (


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const uint16_t * CURegs = is64Bit ? CU64BitRegs : CU32BitRegs ; for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ; return -


<s> if ( ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> ) { if ( A ) { const MCSymbol & Sym = A -> getSymbol ( ) . AliasedSymbol ( ) ; if ( Asm . isThumbFunc ( & Sym ) ) Value |= <NUM_LIT> ; } } if ( A && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { const MCSymbol & Sym = A -> getSymbol ( )


<s> bool isMemImm7ShiftedOffset ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ RegClassID ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue (


) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> <ISA_LIT>PLT :: <ISA_LIT>PLT ( LDSection & pSection , <ISA_LIT>GOT & pGOTPLT ) :


<s> return ( __m64 ) __builtin_arm_walignr2 ( ( __v8qi ) a , ( __v8qi


<s> return static_cast < <STR_LIT> > ( MI . getOperand ( MI . getDesc ( ) . getNumOperands ( )


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) : MCInstPrinter ( MAI ,


<s> bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue NewSP = Op . getOperand ( <NUM_LIT> ) ; SDValue Backchain ; SDLoc DL ( Op ) ; if ( StoreBackchain ) { SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP ,


<s> DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Res ) , { MemOp } ) ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; LoadedVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant

( <NUM_LIT> , dl , <STR_LIT> ) , LoadedVal , SubReg ) , <NUM_LIT> ) ;


<s>
unsigned
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
int
Reg
=
SavedRegs
.
find_first
(
)
;
Reg
!=
<NUM_LIT>
;
Reg
=
SavedRegs
.
find_next
(
Reg
)
)
dbgs
(
)
<<
' '
<<
PrintReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
unsigned
NumRegsSpilled
=
SavedRegs
.
count
(
)
;
bool
CanEliminateFrame
=
NumRegsSpilled
==
<NUM_LIT>
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
CFSize
=
MFI
.
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
NumRegsSpilled
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
bool
BigStack
=
(
CFSize
>=
<NUM_LIT>
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=


<s> Function * Intrinsic = <STR_LIT> ( F -> getParent ( ) , IntID , Types ) ; return CallInst :: Create ( Intrinsic -> getFunctionType ( ) ,


<s> SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else { return false ; } SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } I . getOperand ( <NUM_LIT> ) . setSubReg ( SubIdx ) ; I . setDesc ( TII . get ( <STR_LIT>


<s> if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm


<s> return ( __m256 ) __builtin_ia32_unpckhps256_mask ( ( __v8sf ) __A , ( __v8sf ) __B , ( __v8sf ) _mm256_setzero_ps ( ) , (


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Ra = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder )


<s> ValDef = MRI . getVRegDef ( Val ) ; Opcode = ValDef -> getOpcode ( ) ; } if ( isa < GAnyCmp > ( ValDef ) ) { CanNegate = true ; MustBeFirst = false ; return true ; } if ( Depth > <NUM_LIT> ) return false ; if ( Opcode == TargetOpcode :: G_AND || Opcode == TargetOpcode :: G_OR ) { bool IsOR = Opcode == TargetOpcode :: G_OR ; Register O0 = ValDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register O1 = ValDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool CanNegateL ; bool MustBeFirstL ; if ( ! canEmitConjunction ( O0 , CanNegateL , MustBeFirstL , IsOR , MRI , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; bool MustBeFirstR ; if ( ! canEmitConjunction ( O1 , CanNegateR , MustBeFirstR , IsOR , MRI , Depth + <NUM_LIT> ) ) return false ; if ( MustBeFirstL && MustBeFirstR ) return false ; if ( IsOR ) { if ( ! CanNegateL && ! CanNegateR ) return false ; CanNegate = WillNegate && CanNegateL && CanNegateR ; MustBeFirst = ! CanNegate ; }


<s> break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0


<s> if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo (


<s> IsGlobalInSmallSectionImpl ( const GlobalValue * GV , const TargetMachine & TM ) const { const <ISA_LIT>Subtarget & Subtarget = * static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration (

) ) || GV -> hasCommonLinkage ( ) ) ) return false ;


<s> printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << OffImm <<


<s> if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { const GlobalValue * GV = MO . getGlobal ( ) ; if ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; O << *


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred != <STR_LIT> || CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return nullptr ; if ( ! is<ISA_LIT>LowRegister ( Reg


<s> bool check ( function_checker & c ) const


<s> else if ( Value == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( - <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT>


<s> strcpy ( str_to_check , TREE_STRING_POINTER ( args ) ) ; if ( len == <NUM_LIT> ) { error ( <STR_LIT> ) ; return false ; } unsigned int num_commas = num_occurences_in_str ( ',' , str_to_check ) ; char * token = strtok_r ( str_to_check , <STR_LIT> , & str_to_check ) ; unsigned int num_attrs = <NUM_LIT> ; while ( token ) { num_attrs ++ ; if ( ! aarch64_process_one_target_attr ( token ) ) { error ( <STR_LIT> , token ) ; return false ; } token = strtok_r ( NULL , <STR_LIT> , & str_to_check ) ; } if ( num_attrs != num_commas + <NUM_LIT> ) { error ( <STR_LIT> , TREE_STRING_POINTER ( args )


<s> if ( v9_form ) rval = <STR_LIT> ; else rval = <STR_LIT> ; } else { if ( emit_nop ) rval = <STR_LIT> ; else rval = <STR_LIT> ; } return rval ; } if ( v9_form ) strcpy ( string , <STR_LIT> ) ; else strcpy ( string , <STR_LIT> ) ; p = strchr ( string , '\0' ) ; * p ++ = '%' ; * p ++ = 'l' ; * p ++ = '0' ; * p ++ = '%' ; * p ++ = '(' ; * p = '\0' ; return


<s> static void addCastAndOpKind ( <STR_LIT> Op , MVT VT , <STR_LIT>


<s> void <ISA_LIT>TargetStreamer :: emitRRX ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , MCOperand Op2 , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MCInst TmpInst


CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ;


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSAIX ( ) ) return std ::

make_unique < TargetLoweringObjectFileXCOFF > ( ) ;


<s> while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear


<s> static std :: string computeDataLayout ( const Triple & T , bool is64Bit ) { std :: string Ret = T . getArch ( ) == Triple :: sparcel ? <STR_LIT> : <STR_LIT> ; Ret += <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret


<s> void FixupSFBPass :: buildCopies ( int Size , MachineInstr * LoadInst , int64_t LdDispImm , MachineInstr * StoreInst , int64_t StDispImm , int64_t LMMOffset , int64_t SMMOffset ) { int LdDisp = LdDispImm ; int StDisp = StDispImm ; while ( Size > <NUM_LIT> ) { if ( ( Size - MOV128SZ >= <NUM_LIT> ) && isYMMLoadOpcode ( LoadInst -> getOpcode ( ) ) ) { Size = Size - MOV128SZ ; buildCopy ( LoadInst , YMMtoXMMLoadMap . at ( LoadInst -> getOpcode ( ) ) , LdDisp , StoreInst , YMMtoXMMStoreMap . at ( StoreInst -> getOpcode ( ) ) , StDisp , MOV128SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV128SZ ; StDisp += MOV128SZ ; LMMOffset += MOV128SZ ; SMMOffset += MOV128SZ ; continue ; } if ( Size - MOV64SZ >= <NUM_LIT> && Is64Bit ) { Size = Size - MOV64SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV64SZ , LMMOffset , SMMOffset ) ; LdDisp +=


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler ( )


<s> return ( __m128i ) __builtin_ia32_cvtpd2udq128_mask ( ( __v2df ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ; return plt0


<s> SDValue WidthMinusOne = DAG . getConstant ( NumBits - <NUM_LIT> , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinusOne , DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ) ; } assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl ,


<s> fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , alloc_offset - seh -> reg_offset [ regno ] ) ; } if ( seh -> cfa_reg != stack_pointer_rtx ) { offset = alloc_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; gcc_assert ( IN_RANGE ( offset , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , f ) ; print_reg ( seh -> cfa_reg , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } if ( crtl ->


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getValueSizeInBits ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; unsigned NumSrcElts = N00 . getValueType (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > (


<s> static bool is_imported_p ( rtx x ) { if ( ! TARGET_DLLIMPORT_DECL_ATTRIBUTES || GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_DLLIMPORT_P ( x ) || SYMBOL_REF_STUBVAR_P ( x


<s> for ( SmallVectorImpl < unsigned > :: iterator I = Defs . begin ( ) , E = Defs . end ( ) ; I != E ; ++ I ) { SmallVector < MachineInstr * , <NUM_LIT> > DefSrcs ; if ( ! Register :: isVirtualRegister ( * I ) ) continue ; MachineInstr * Def = MRI -> getVRegDef ( * I ) ; if ( ! Def ) continue ; elideCopiesAndPHIs ( Def , DefSrcs ) ; for ( MachineInstr * MI : DefSrcs ) { if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; Register DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & * I ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { MRI -> constrainRegClass ( NewReg , MRI -> getRegClass ( ( * I ) -> getReg ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << printReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg ( NewReg , <NUM_LIT> , * TRI ) ; } } Replacements [ MI ] =


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { assert ( <NUM_LIT> && <STR_LIT> ) ; return false


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF )


<s> I . getOperand ( <NUM_LIT> ) . setReg ( AndResult ) ; auto InsertBefore = std :: next ( I . getIterator ( ) ) ; auto SubI = BuildMI ( MBB , InsertBefore , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( SExtResult ) . addUse ( AndResult ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : case G_GEP : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FADD : if ( ! selectFAdd ( MIB , TII , MRI ) ) return false ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_CONSTANT : { unsigned Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getType ( Reg ) . getSizeInBits ( ) != <NUM_LIT> ) return false ; assert ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; } case G_STORE : case G_LOAD :


<s> void <ISA_LIT>LongBranch :: relaxBranches ( ) { SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) ; BlockPosition Position ( Log2 ( MF -> getAlignment ( ) ) ) ; for ( auto & Block : MBBs ) { skipNonTerminators ( Position , Block ) ; for ( unsigned BTI = <NUM_LIT> , BTE = Block . NumTerminators ; BTI != BTE ; ++


<s> EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode ( OpCode ) ; MCInst


<s> unsigned <ISA_LIT>16SPAliasReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> get<ISA_LIT>16SPAliasReg


<s> rtx body = PATTERN ( insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , <NUM_LIT> ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; if ( ! REG_P ( dest_address ) && ! rs6000_sum_of_two_registers_p ( dest_address ) ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) ,


<s> unsigned LhsReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RhsReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpInst :: Predicate Predicate = ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ; static const uint16_t SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } unsigned OpCmp ; LLT Ty = MRI . getType ( LhsReg ) ; switch ( Ty . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; } unsigned ResultReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; RBI . constrainGenericRegister ( ResultReg , * getRegClass ( LLT :: scalar ( <NUM_LIT> ) , * RBI . getRegBank ( ResultReg , MRI , TRI ) ) , MRI ) ; if ( SETFOpc ) { MachineInstr & CmpInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpCmp ) ) . addReg ( LhsReg ) . addReg ( RhsReg ) ; unsigned FlagReg1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FlagReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Set1 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; MachineInstr & Set2 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; MachineInstr & Set3 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg )

. addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ;


<s> return ( vector signed int ) __builtin_altivec_vavgsw ( ( vector signed int


<s> if ( TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , get_decl_name ( decl1 ) , get_decl_name ( decl2 ) , ret ) ; return ret


<s> return ( int64x2_t ) __builtin_neon_vld1_lanev2di ( ( const __builtin_neon_di * ) __a , __b


<s> if ( TARGET_SVE && aarch64_cmp_autovec_modes ( VNx16QImode , V16QImode ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; if ( TARGET_SIMD ) return aarch64_vq_mode ( mode )


<s> N -> getMask ( M ) ; return :: isUNPCKLMask ( M , N -> getValueType ( <NUM_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRri ( SDValue Addr , SDValue & Base , SDValue & Offset ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> )


<s> static bool isCommutedMOVL ( SDNode * N , bool V2IsSplat = false , bool V2IsUndef = false ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; return isCommutedMOVL ( N -> op_begin ( ) , N -> getNumOperands ( )


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS &&


<s> return ( rclass == GENERAL_REGS || rclass ==


<s> if ( EnableBranchCoalescing && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BranchCoalescingPass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( create<ISA_LIT>VSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( create<ISA_LIT>MIPeepholePass ( ) ) ; addPass ( & DeadMachineInstructionElimID


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT . isInteger ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 . getOperand ( <NUM_LIT> ) ) if ( ConstantSDNode * Y1C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) if ( Y1C -> getAPIntValue ( ) == VT . getSizeInBits ( ) - <NUM_LIT> ) { SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> )

, DAG . getConstant ( <NUM_LIT> , VT ) , N0 . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , AbsAddr ,

MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; } unsigned EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; EltNo = ( EltNo + NElts / <NUM_LIT> ) % NElts ; MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_XXPERMDI : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( )


<s> void <ISA_LIT>DAGToDAGISel :: replaceDAGValue ( const SDValue & N , SDValue M ) { CurDAG -> RepositionNode ( N . getNode ( ) -> getIterator ( ) , M . getNode ( ) ) ; ReplaceUses ( N , M


<s> machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == <NUM_LIT> ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; cmp_mode = int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case E_V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case E_V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case E_V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case E_V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode


<s> MaskInst . addOperand ( MCOperand :: CreateReg ( AddrReg ) ) ; MaskInst . addOperand ( MCOperand :: CreateReg (


<s> DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; break ; } case TLSModel :: LocalExec : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; break ; } } return DAG . getNode ( <STR_LIT> , DL , PtrVT , TP ,


<s> SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 ; if ( ! SelectAddr ( In1 , In1 , Tmp0 , Tmp1


<s> case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; } return false


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; return vectorCostAdjustment ( Cost , Opcode , Ty , nullptr


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT>


<s> return ( pInst & ~ ( ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) | ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) ) ) | ( ( pImm & get_mask ( <NUM_LIT> ) ) << <NUM_LIT> ) | ( ( pImm & ( get_mask (

<NUM_LIT> ) << <NUM_LIT> ) ) << <NUM_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT>


<s> EVT CmpVT = LHS . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } const bool FullFP16 = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs


<s> tmp = gen_rtx_REG ( mode , regno ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec


<s> void printopaquemem ( const MachineInstr * MI ,


<s> case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: Intel_OCL_BI : return isTargetWin64 ( ) ; case CallingConv :: <ISA_LIT>_64_Win64 : return


<s> int sh_media_register_for_return ( void ) { int regno ; int tr0_used ; if ( ! crtl -> is_leaf ) return - <NUM_LIT> ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - <NUM_LIT> ; if ( sh_cfun_interrupt_handler_p ( ) ) return - <NUM_LIT> ; tr0_used = flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_really_used_regs [ regno ] && ! df_regs_ever_live_p ( regno ) ) return regno ; return -


<s> int FI = MF . getFrameInfo ( ) . CreateFixedObject ( OpSize , Offset , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FIN = DAG . getFrameIndex ( FI , VT ) ; TailCallArgumentInfo Info ; Info . Arg = Arg ; Info . FrameIdxOp


<s> if ( REG_P ( XEXP ( base_addr , <NUM_LIT> ) ) ) { update_base_p = false ; base_reg = XEXP ( base_addr , <NUM_LIT> ) ; } else { update_base_p = true ; base_reg = XEXP ( XEXP ( base_addr , <NUM_LIT> ) , <NUM_LIT> ) ; } const char * update_base = update_base_p ? <STR_LIT> : <STR_LIT> ; regno = REGNO ( operands [ <NUM_LIT> ] ) ; otherops [ <NUM_LIT> ] = base_reg ; otherops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; otherops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; ; if ( regno >= <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno ) | nds32_regno_to_enable4 ( regno + <NUM_LIT> ) ; sprintf ( buff , <STR_LIT> , update_base , enable4 ) ; } else if ( regno == <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno


<s> return ( VT . isScalarInteger ( ) && TLI ->


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> return ( ( vec_uint4 ) ( si_mpyui ( ( qword ) (


<s> OutStreamer -> AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> emitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbolELF * Stub = cast < MCSymbolELF > ( OutContext . getOrCreateSymbol ( StringRef ( x ) ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . getOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer -> emitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer -> emitLabel ( Stub ) ; assert ( ! isPositionIndependent ( ) && <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( * STI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( * STI , Signature -> ParamSig , LE , true ) ; EmitJal ( * STI , MSymbol ) ; EmitSwapFPIntRetval ( * STI , Signature


<s> if ( Op -> getOperand ( i ) != ExtValue ) return SDValue ( ) ; } else if ( ! ( isNullConstant ( Op -> getOperand ( i ) ) || Op -> getOperand ( i ) . isUndef ( ) ) ) return SDValue ( ) ; } unsigned EltSize = Op -> getSimpleValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; unsigned ExtVTSize = EltSize * Delta ; EltType = <STR_LIT> ( ExtVTSize ) ; NumElt = NumElts / Delta


<s> return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx + <NUM_LIT> )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>BEMCCodeEmitter ( const MCInstrInfo & MCII ,


<s> switch ( Type ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false


<s> return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> , <NUM_LIT>


<s> else if ( TARGET_AVX && all ) { modes -> safe_push ( V16QImode ) ; modes -> safe_push ( V32QImode ) ; } else if ( TARGET_SSE2 ) modes -> safe_push ( V16QImode ) ; if ( TARGET_MMX_WITH_SSE ) modes -> safe_push ( V8QImode ) ; if ( TARGET_SSE2 ) modes -> safe_push (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . OffsetRegNum


<s> Chain = Res . getValue ( <NUM_LIT> ) ; } else { Res = DAG . getNode ( Op . getOpcode ( ) , DL , WideVT , Src ) ; } Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , DL ) ; return Res ; } bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ; if ( VT != <STR_LIT> || IsSigned ) return SDValue ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sign = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , One ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , One ) ) ; SDValue IsNeg = DAG . getSetCC ( DL , <STR_LIT> , Src , Zero , <STR_LIT> ) ; SDValue SignSrc = DAG . getSelect ( DL , <STR_LIT> , IsNeg , Sign , Src ) ; SmallVector < SDValue , <NUM_LIT> > SignCvts ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Chains ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SignSrc ,


<s> unsigned getMaxPrefetchIterationsAhead ( ) const override { return


<s> if ( Subtarget -> isTargetLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) return new TargetLoweringObjectFileNaCl ( ) ; if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) return new TargetLoweringObjectFileCOFF ( ) ; llvm_unreachable ( <STR_LIT>


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned RegAreaSize = ByVal . NumRegs * CC . regSize ( ) ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; if ( RegAreaSize ) FrameObjOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( ( CC . numIntArgRegs ( ) - ByVal . FirstIdx ) * CC . regSize ( ) ) ; else FrameObjOffset = ByVal . Address ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset


<s> fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; if ( uses_toc == <NUM_LIT> ) switch_to_other_text_partition ( ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name


<s> else LastLHSMismatch = i ; if ( M [ i ] == i + NumInputElements ) ++ NumRHSMatch ; else LastRHSMismatch = i ; } if ( NumLHSMatch == NumInputElements - <NUM_LIT> ) { DstIsLeft = true ; Anomaly = LastLHSMismatch ; return true ; } else if ( NumRHSMatch == NumInputElements - <NUM_LIT> ) { DstIsLeft = false ; Anomaly =


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else


<s> rtx_insn * prev = start ; rtx_insn * next = NULL ; * found = false ; while ( prev && prev != insn && distance < LEA_SEARCH_THRESHOLD ) { if ( NONDEBUG_INSN_P ( prev ) && NONJUMP_INSN_P ( prev ) ) { distance = increase_distance ( prev , next , distance ) ; if ( insn_defines_reg ( regno1 , regno2 , prev ) ) { if ( recog_memoized ( prev ) < <NUM_LIT> || get_attr_type ( prev ) != TYPE_LEA ) { * found = true ; return distance ; } } next =


<s> if ( isa < MCSymbolRefExpr > ( Expr ) ) return <STR_LIT> ; if ( const <ISA_LIT>MCExpr * McExpr = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { <ISA_LIT>MCExpr :: VariantKind ExprKind = McExpr -> getKind ( ) ; switch ( ExprKind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO : return <STR_LIT>


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: ParseIntelBracExpression ( unsigned SegReg , SMLoc Start , int64_t ImmDisp , unsigned Size ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc BracLoc = Tok . getLoc ( ) , End = Tok . getEndLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( BracLoc , <STR_LIT> ) ; Parser . Lex ( ) ; SMLoc StartInBrac = Parser . getTok ( ) . getLoc ( ) ; IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; const MCExpr * Disp = nullptr ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( * InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: createAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( ( Parser . getTok ( ) . getKind ( ) == AsmToken :: Identifier || Parser . getTok ( ) . getKind ( ) == AsmToken :: Dot || Parser . getTok ( ) . getKind ( ) == AsmToken :: Real ) && Parser . getTok ( ) . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex (


<s> OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ; Operands . push_back ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg , std :: move ( Offset ) ) : <STR_LIT> ( BaseReg , std :: move ( Offset ) ) ) ; return


<s> auto InsertZExt = [ & ] ( Value * V , Instruction * InsertPt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; Builder . SetInsertPoint ( InsertPt ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; auto * ZExt = cast < Instruction > ( Builder . CreateZExt ( V , ExtTy ) ) ; if ( isa < Argument > ( V ) ) ZExt -> moveBefore ( InsertPt ) ; else ZExt -> moveAfter ( InsertPt ) ; ReplaceAllUsersOfWith ( V , ZExt ) ; NewInsts . insert ( ZExt ) ; TruncTysMap [ ZExt ] = TruncTysMap [ V ] ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; auto * I = cast < Instruction > ( V ) ; if ( Sinks . count ( I ) ) continue ; for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) FixConst ( Const , I ) ; else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; if ( ! shouldPromote ( V ) ||


<s> unsigned getCalleeSavedFrameSize ( ) const { return CalleeSavedFrameSize


<s> BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) .


<s> return <ISA_LIT>Lowering . SelectAddressRegReg ( N , Base , Index , *


<s> UsefulBits . flipAllBits ( ) ; } APInt UsersUsefulBits ( UsefulBits . getBitWidth ( ) , <NUM_LIT> ) ; for ( SDNode * Node : Op . getNode ( ) -> uses ( ) ) { APInt UsefulBitsForUse = APInt ( UsefulBits ) ; getUsefulBitsForUse ( Node , UsefulBitsForUse , Op , Depth ) ; UsersUsefulBits |= UsefulBitsForUse ; } UsefulBits &=


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> case <STR_LIT> : { Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; } } assert ( Count == <NUM_LIT> && <STR_LIT> ) ; IRBuilder < > Builder ( Inst ) ; LLVMContext & Ctx = Builder . getContext ( ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( Inst -> getOperand ( <NUM_LIT> ) , Type :: getInt8PtrTy ( Ctx ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Inst -> replaceAllUsesWith ( NewInst ) ; } if ( ! NewInst ) splitLD ( Inst ) ; } return true


<s> IntegerType * PtrTy = Type :: getIntNTy ( * DAG . getContext ( ) , PtrSize ) ; SDValue TlsGetAddr = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = PtrTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , PtrTy , TlsGetAddr , & Args , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> ,


<s> union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; if ( b & <NUM_LIT> ) { vec_uint4 nan_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 a_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; if ( b & <NUM_LIT> ) { vec_uint4 a_nan = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; a_nan = vec_or ( a_nan , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_nan , x . v ) , a_inf ) ) ; a_nan = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_nan , ( vec_uchar16 ) a_nan , splat_hi ) ; result = vec_or ( result , a_nan ) ; } if ( b & <NUM_LIT> ) { a_inf = vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_inf , x . v ) , a_inf ) ; a_inf = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_inf , ( vec_uchar16 ) a_inf , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( a_inf , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( a_inf , sign ) , result ) ; } } if ( b & <NUM_LIT> ) { vec_uint4 iszero = ( vec_uint4 ) vec_cmpeq ( aabs , ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) ) ; iszero = vec_and ( iszero , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) iszero , x . v ) ) ; if ( b & <NUM_LIT> ) { vec_uint4 denorm_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 isdenorm = vec_nor ( ( vec_uint4 ) vec_cmpgt ( aabs , denorm_mask ) , iszero ) ; isdenorm = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) isdenorm , ( vec_uchar16 ) isdenorm , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( isdenorm , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( isdenorm ,


<s> if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT>


<s> switch ( kind ) { case vector_load : case vector_store : case unaligned_load : case unaligned_store : break ; default : return


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false ; case 'P' : printMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false ; } } printMemReference ( MI , OpNo


<s> if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Reg = <ISA_LIT>MCRegisterClasses [ RegClassID ] .


<s> virtual const MCSection * getAttributesSection ( ) const { return


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>V9Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>V9Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer (

The<ISA_LIT>Target , createMCStreamer ) ;


<s> MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsADDiu ( uint64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { GetInstSeqLs ( ( Imm + <NUM_LIT> ) & <NUM_LIT> , RemSize , SeqLs ) ; AddInstr ( SeqLs , Inst ( ADDiu , Imm &


<s> return ( __m128i ) __builtin_ia32_vpshaq ( ( __v2di


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI =


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Addr = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( true ) ; EmitMask ( Out , Addr , Mask ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo


<s> break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , str ) ; break ; default : gcc_unreachable ( ) ; } return


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand


<s> Value * <ISA_LIT>IREmitter :: visitVPERMV ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Address ) ; if ( ! GEP ) return false ; bool Changed = false ; if ( GEP -> hasOneUse ( ) && dyn_cast < GetElementPtrInst > ( GEP -> getPointerOperand ( ) ) ) { IRBuilder < > Builder ( GEP -> getContext


<s> Imm . toString ( ImmStrVal ) ; if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } if ( IsLegal ) { DEBUG ( dbgs ( ) << <STR_LIT> << FPType << <STR_LIT> << ImmStrVal << <STR_LIT> ) ; return true ; } if ( ! FPType . empty ( ) ) DEBUG ( dbgs ( ) << <STR_LIT> << FPType << <STR_LIT> << ImmStrVal << <STR_LIT> ) ; else DEBUG ( dbgs ( ) << <STR_LIT> << ImmStrVal <<


<s> SDValue <ISA_LIT>TargetLowering :: getReturnAddressFrameIndex ( SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false


<s> static machine_mode zero_call_used_regno_mode ( const unsigned int regno ) { if ( GENERAL_REGNO_P ( regno ) ) return SImode ; else if ( SSE_REGNO_P ( regno ) ) return V4SFmode ; else if ( MASK_REGNO_P ( regno )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> if ( DstVT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getUINTTOFP ( SrcVT , DstVT ) ) ; if ( DstVT . isVector ( ) ) return lowerUINT_TO_FP_vec ( Op , DAG , Subtarget ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( Subtarget . hasAVX512 ( ) && isScalarFPTypeInSSEReg ( DstVT ) && ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) ) ) { return Op ; } if ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { DstVT , <STR_LIT> } , { Chain , Src } ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Src ) ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG , Subtarget ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 && DstVT != <STR_LIT> ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; Align SlotAlign ( <NUM_LIT> ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot ,

TypeSize :: Fixed ( <NUM_LIT> ) , dl ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL64 ( const Target & T , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSNaCl ( ) ) return new NaCl<ISA_LIT>AsmBackend ( T , true ) ; return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( )


<s> <STR_LIT> Cmp ; std :: tie ( Imm , Opc , Cmp ) = Info ; MachineBasicBlock * const MBB = CmpMI -> getParent ( ) ; BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent ( ) ; MachineInstr * BrMI = MBB -> getFirstTerminator (


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack (


<s> if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , <NUM_LIT> ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) )


<s> unsigned BMITargetOperand = branchTargetOperand ( BMI ) ; MachineBasicBlock * NewDest = BMI -> getOperand ( BMITargetOperand ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MI -> setDesc ( TII -> get ( OppositeBranchOpcode ) ) ; BMI -> getOperand ( BMITargetOperand ) . setMBB ( DestBB ) ; MI -> getOperand ( TargetOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NextBB ) ; } else { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addMBB ( NextBB ) ; } Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ; return


<s> unsigned int i ; FOR_EACH_VEC_ELT ( mips_multi_members , i , member ) if ( member -> is_label_p ) fprintf ( asm_out_file , <STR_LIT> , member -> format ) ; else output_asm_insn ( member -> format


<s> <ISA_LIT>CTRLoops ( <ISA_LIT>TargetMachine & TM ) : FunctionPass ( ID ) , TM ( & TM ) { initialize<ISA_LIT>CTRLoopsPass ( * PassRegistry :: getPassRegistry ( )


<s> for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : Table ) if ( Row [ domain - <NUM_LIT> ] ==


<s> getT2AddrModeImm8OpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT> ; int32_t tmp = ( int32_t ) MO2 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp


<s> bool <ISA_LIT>Subtarget :: IsLegalToCallImmediateAddr ( const


<s> Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = offsetReg ; Op -> Mem . Off = <NUM_LIT> ; return Op


<s> void <ISA_LIT>MachObjectWriter :: Record<ISA_LIT>Relocation ( MachObjectWriter * Writer , const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) { unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Log2Size = getFixupKindLog2Size ( Fixup . getKind ( ) ) ; if ( Target . getSymA ( ) && Target . getSymA ( ) -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP ) { RecordTLVPRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; return ; } if ( Target . getSymB ( ) ) { RecordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; return ; } MCSymbolData * SD = <NUM_LIT> ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && SD && ! Writer -> doesSymbolRequireExternRelocation ( SD ) && RecordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ) return ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { Type = MachO :: GENERIC_RELOC_VANILLA ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = MachO :: GENERIC_RELOC_VANILLA ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsExtern << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ) ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE


<s> bool WriteNopData ( uint64_t Count , MCObjectWriter


<s> switch ( rs6000_tune ) { case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : return <NUM_LIT> ; case PROCESSOR_CELL


<s> insn -> reader = reader ; insn -> readerArg = readerArg ; insn -> dlog = logger ; insn -> dlogArg = loggerArg ; insn -> startLocation = startLoc ; insn -> readerCursor = startLoc ; insn -> mode = mode ; insn -> numImmediatesConsumed = <NUM_LIT> ; if ( readPrefixes ( insn ) || readOpcode ( insn ) || getID ( insn ) || insn -> instructionID == <NUM_LIT> || readOperands ( insn ) ) return - <NUM_LIT> ; insn -> length = insn -> readerCursor -


<s> static int loongarch_set_reg_reg_piece_cost ( machine_mode mode , unsigned int units ) { return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units - <NUM_LIT> ) /