<s> case PLUS : if ( TARGET_HARD_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case AND : case XOR : case IOR : if ( mode == SImode ) { enum rtx_code subcode = GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ; if ( subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT || subcode == LSHIFTRT || subcode == ASHIFTRT || ( code == AND && subcode == NOT ) ) { * total = <NUM_LIT> ; return false ; } } * total = COSTS_N_INSNS ( ARM_NUM_REGS ( mode ) ) ; return false ; case MULT : * total = COSTS_N_INSNS ( ARM_NUM_REGS ( mode ) ) ; return false ; case NEG : if ( TARGET_HARD_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; case NOT : * total = COSTS_N_INSNS ( ARM_NUM_REGS ( mode ) ) ; return false ; case IF_THEN_ELSE : * total = <NUM_LIT> ; return false ; case COMPARE : if ( cc_register ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case ABS : if ( TARGET_HARD_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> + ARM_NUM_REGS ( mode ) ) ; return false ; case SIGN_EXTEND : * total = <NUM_LIT> ; if ( GET_MODE_SIZE ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) < <NUM_LIT> ) { if ( ! ( arm_arch4 && MEM_P ( XEXP ( x , <NUM_LIT> ) ) ) ) * total += COSTS_N_INSNS ( arm_arch6 ? <NUM_LIT> : <NUM_LIT> ) ; } if ( mode == DImode ) * total += COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case ZERO_EXTEND : * total = <NUM_LIT> ; if ( ! ( arm_arch4 && MEM_P ( XEXP ( x , <NUM_LIT> ) ) ) ) { switch ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) { case QImode : * total += COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case HImode : * total += COSTS_N_INSNS ( arm_arch6 ? <NUM_LIT> : <NUM_LIT> ) ; case SImode : break ; default : * total += COSTS_N_INSNS ( <NUM_LIT> ) ; } } if ( mode == DImode ) * total += COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case CONST_INT


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI )


<s> unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ; EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ; SDVTList SDTys = DAG . getVTList ( Tys ) ; unsigned NewOp = IsLaneOp ? <STR_LIT> : <STR_LIT> ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOp , SDLoc ( N ) , SDTys , Ops , MemVT , LoadSDN -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > NewResults ; NewResults . push_back ( SDValue ( LD , <NUM_LIT> ) ) ; NewResults . push_back ( SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) ) ; DCI . CombineTo ( LD , NewResults ) ; DCI . CombineTo ( N , SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) ) ; DCI . CombineTo ( User , SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) ) ; break ; } return SDValue (


<s> if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; if ( ! Subtarget . isThumb ( ) && ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString (


<s> if ( VT . isVector ( ) ) return false ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; unsigned Mask = C -> getZExtValue ( ) ; unsigned Demanded = DemandedAPInt . getZExtValue ( ) ; unsigned ShrunkMask = Mask & Demanded ; unsigned ExpandedMask = Mask | ~ Demanded ; if ( ShrunkMask == <NUM_LIT> ) return false ; if ( ExpandedMask == ~ <NUM_LIT> ) return TLO . CombineTo ( Op , Op . getOperand ( <NUM_LIT> ) ) ; auto IsLegalMask = [ ShrunkMask , ExpandedMask ] ( unsigned Mask ) -> bool { return ( ShrunkMask & Mask ) == ShrunkMask && ( ~ ExpandedMask & Mask ) == <NUM_LIT> ; } ; auto UseMask = [ Mask , Op , VT , & TLO ] ( unsigned NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op , NewOp ) ; } ; if ( IsLegalMask ( <NUM_LIT> ) ) return UseMask ( <NUM_LIT> ) ; if ( IsLegalMask ( <NUM_LIT> ) ) return UseMask ( <NUM_LIT> ) ; if ( ShrunkMask < <NUM_LIT> ) return UseMask


<s> assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( TM -> getRelocationModel


<s> case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformMLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformMSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG


<s> } else { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'v' : if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> ) { if ( VT == <STR_LIT> ) return std ::


<s> unsigned Register = PPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeSP ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , SDLoc (


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ; return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset ,


<s> switch ( VVPOC ) { case <STR_LIT> : \ IsBinaryOp = true ; \ break ; } if ( IsBinaryOp ) { assert ( LegalVecVT . isSimple ( ) ) ; return DAG . getNode ( VVPOC , DL , LegalVecVT , Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Mask , AVL ) ; } llvm_unreachable ( <STR_LIT>


<s> Expr . push_back ( ( uint8_t ) ( dwarf :: DW_OP_breg0 + <NUM_LIT> ) ) ; Expr . push_back ( <NUM_LIT> ) ; appendVGScaledOffsetExpr ( Expr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true ) , Comment ) ; SmallString < <NUM_LIT> > DefCfaExpr ; DefCfaExpr . push_back ( dwarf ::


<s> struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree func_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; if ( TARGET_DEBUG_TARGET ) { tree tname = DECL_NAME ( fndecl ) ; fprintf ( stderr , <STR_LIT> ) ; if ( tname ) fprintf ( stderr , <STR_LIT> , ( int ) IDENTIFIER_LENGTH ( tname ) , IDENTIFIER_POINTER ( tname ) ) ; else fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; rs6000_debug_target_options ( args , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; if ( flags ) fprintf ( stderr , <STR_LIT> , flags ) ; fprintf ( stderr , <STR_LIT> ) ; } if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , <STR_LIT> ) == <NUM_LIT> ) return true ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; ret = rs6000_inner_target_options ( args , true ) ; if ( ret ) { ret = rs6000_option_override_internal ( false ) ; new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( ! new_target ) ret = false ; else if ( fndecl


<s> if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else return false ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstReg , MRI ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcReg , MRI ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; uint64_t encoding = <STR_LIT> ( MCE ->


<s> __ev64_opaque__ ev ; ev = ( __ev64_opaque__ ) __ev_create_fs ( a , b ) ; return ( __ev64_opaque__ ) __builtin_spe_evfsctsf ( ( __v2sf ) ev


<s> if ( ! arg . type ) return aarch64_pass_by_reference_1 ( pcum , arg ) ; pure_scalable_type_info pst_info ; switch ( pst_info . analyze ( arg . type ) ) { case pure_scalable_type_info :: IS_PST : if ( pcum && ! pcum -> silent_p && ! TARGET_SVE ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , arg . type ) ; return ( ! arg . named || pcum -> aapcs_nvrn + pst_info . num_zr ( ) > NUM_FP_ARG_REGS || pcum -> aapcs_nprn + pst_info . num_pr ( ) > NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_pass_by_reference_1 ( pcum , arg ) ) ; return true ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info ::


<s> else Expr = MO2 . getExpr ( ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCFixupKind Kind ; if ( Subtarget . isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations ; } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm12 , Fixups ) ; uint32_t Binary = Imm12 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg <<


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) || TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG , <ISA_LIT>SubTarget ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; std :: vector < EVT > NodeTys ; SDValue Ops [ <NUM_LIT> ] , Result , MFFSreg , InFlag , FPreg ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; MFFSreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = Lo ; Ops [ <NUM_LIT> ] = Hi ; Ops [ <NUM_LIT> ] = InFlag ; Result = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; FPreg = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG .


<s> bool convertInstr ( MachineInstr * MI , const TargetInstrInfo

* TII , MachineRegisterInfo * MRI ) const override {


<s> if ( CondSrc -> getOpcode ( ) == <STR_LIT> ) Cond = CondSrc -> getOperand ( <NUM_LIT> ) ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue


<s> static DecodeStatus DecodeThumbBCCTargetOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler :: Success


<s> bool <ISA_LIT>BaseInstrInfo :: isAm2ScaledReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> )


<s> unsigned <ISA_LIT>AsmBackend :: getRelaxedOpcode ( unsigned Op ) const { bool HasThumb2 = STI . getFeatureBits ( ) [ <STR_LIT> ] ; bool HasV8MBaselineOps = STI . getFeatureBits ( ) [ <STR_LIT> ] ; switch ( Op ) { default : return Op ; case <STR_LIT> : return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ; case


<s> const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; } else if ( DispSpec . isMCValue ( ) ) { DispSpec . getMCValue ( ) . print ( O ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> ) ; O << '(' ; if ( BaseReg . getReg ( ) ) printOperand (


<s> void printf80mem ( const MachineInstr * MI , unsigned OpNo ) { printMemReference ( MI , OpNo


<s> MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT . getVectorNumElements ( ) ) ; In = DAG . getNode ( Op . getOpcode ( ) , dl , CastVT , In ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { unsigned CastOpc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT CastVT = VT . changeVectorElementTypeToInteger ( ) ; In = DAG . getNode ( CastOpc , dl , CastVT , In ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , VT , In ) ; } return


<s> } case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; bool IsPagerando = MF . getFunction ( ) . isPagerando ( ) ; return <NUM_LIT> - HasFP - ( STI . isR9Reserved ( ) || IsPagerando ? <NUM_LIT> : <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT>


<s> const InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector


<s> emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_pgoff , GEN_INT ( <NUM_LIT> - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_GE ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , lab_ref , pc_rtx ) ; rtx_insn * j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; add_reg_br_prob_note ( j , profile_probability :: unlikely ( ) ) ; JUMP_LABEL ( j ) = strncmp_label


<s> if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( <NUM_LIT> ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LHS . hasOneUse ( ) && ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N ) ; LHS = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; LHS = DAG . getBitcast ( <STR_LIT> , LHS ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , LHS , RHS ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && RHS . hasOneUse ( ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && RHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N


<s> printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II


<s> const auto & MFI = MF . getFrameInfo ( ) ; if ( ! MF . hasEHFunclets ( ) && ! MFI . hasVarSizedObjects ( ) ) return <STR_LIT> ; else if ( hasStackRealignment ( MF ) ) return


<s> if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; unsigned Opc ; if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg ) return <NUM_LIT> ; unsigned RHSReg ; if ( ! LHSReg ) return <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) RHSReg = materializeInt ( C , <STR_LIT> ) ; else RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; emitInst ( Opc , ResultReg ) . addReg ( LHSReg ) . addReg ( RHSReg ) ; return ResultReg


<s> case <STR_LIT> : if ( ! Subtarget . hasSSE2 ( ) || FromVT != <STR_LIT> ) return false ; return ToVT == <STR_LIT> || ( Subtarget . hasAVX ( ) && ToVT == <STR_LIT> ) ; case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) || FromVT !=


<s> bool <ISA_LIT>DAGToDAGISel :: matchADDRri ( SDValue Addr , SDValue & Base , SDValue & Offset ) { auto AddrTy = Addr -> getValueType ( <NUM_LIT> ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , AddrTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , AddrTy ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return


<s> FrameID = MachineOutlinerTailCall ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , DoesntNeedLRSave ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT>


<s> bool <ISA_LIT>AddressTypePromotion :: shouldGetThrough ( const Instruction * Inst ) { if ( isa < SExtInst > ( Inst ) && ( Inst -> getType ( ) == ConsideredSExtType || Inst -> hasOneUse ( ) ) ) return true ; if ( ! Inst -> hasOneUse ( ) ) return false ; if ( isa < TruncInst > ( Inst


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model


<s> const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; Register NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { Register VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register VSRCTmp2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VSRCTmp1 ) . addReg ( NewVReg ) ; LLVM_DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; insertSwap ( MI , InsertPoint , VSRCTmp2 , VSRCTmp1 ) ; LLVM_DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( VSRCTmp2 ) ; LLVM_DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; } else { insertSwap ( MI , InsertPoint , DstReg


<s> static SDValue combineMinMaxReduction ( SDNode * Extract , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; EVT ExtractVT = Extract -> getValueType ( <NUM_LIT> ) ; if ( ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> BinOp ; SDValue Src = DAG . matchBinOpReduction ( Extract , BinOp , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , true ) ; if ( ! Src ) return SDValue ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getScalarType ( ) ; if ( SrcSVT != ExtractVT || ( SrcVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue MinPos = Src ; while ( SrcVT . getSizeInBits ( ) > <NUM_LIT> ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = splitVector ( MinPos , DAG , DL ) ; SrcVT = Lo . getValueType ( ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT>


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter ) ; if ( RelaxAll ) S -> getAssembler (


<s> return ( uint16x4_t ) __builtin_neon_vcreatev4hi (


<s> const MachineDomTreeNode * MBBInfo :: getNode (


<s> if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , OffsetIsScalable , Width , TRI ) ) return false ; BaseOps . push_back (


<s> if ( reg_set_between_p ( m_ccreg , e . cstore . insn , NEXT_INSN ( BB_END ( e . bb ) ) ) ) log_return ( false , <STR_LIT> , e . bb -> index ) ; if ( reg_set_between_p ( m_ccreg , PREV_INSN ( BB_HEAD ( trace . bb ( ) ) ) , trace . setcc . insn ) ) log_return ( false , <STR_LIT> , trace . bb ( ) -> index ) ; return true


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != <NUM_LIT> ) add_to_hard_reg_set ( & set -> set

, Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ;


<s> auto * FVTy = cast < FixedVectorType > ( VTy ) ; Type * EltTy = FVTy -> getElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) FVTy = FixedVectorType :: get ( DL . getIntPtrType ( EltTy ) , FVTy -> getNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { FVTy = FixedVectorType :: get ( FVTy -> getElementType ( ) , FVTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , FVTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = FVTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { FVTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( )

, LoadInts [ Factor - <NUM_LIT> ] , Tys ) ;


<s> return ( uint64x2_t ) __builtin_neon_vqshluv2di ( ( int64x2_t


<s> return decodeRegisterClass ( Inst , RegNo


<s> auto ValidateRanges = [ ] ( MachineInstr * Start , MachineInstr * End , <ISA_LIT>BasicBlockUtils * BBUtils , MachineLoop & ML ) { MachineBasicBlock * TgtBB = End -> getOpcode ( ) == <STR_LIT> ? End -> getOperand ( <NUM_LIT> ) . getMBB ( ) : End -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( TgtBB != ML . getHeader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML . getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML . getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true ; } ; StartInsertPt = MachineBasicBlock :: iterator ( Start ) ; StartInsertBB = Start -> getParent


<s> HasMMA = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx =


<s> Register UACCPhys = VRM -> getPhys ( ResultReg ) ; Register HintReg = getSubReg ( UACCPhys , ResultOp -> getSubReg ( ) ) ; if ( HintReg >= <STR_LIT> && HintReg <= <STR_LIT> ) Hints . push_back ( HintReg ) ; } break ; } case <STR_LIT> : { ResultOp = & Use . getOperand ( <NUM_LIT> ) ; ResultReg = ResultOp -> getReg ( ) ; if ( MRI -> getRegClass ( ResultReg ) -> contains ( <STR_LIT> ) && VRM -> hasPhys ( ResultReg ) ) { Register ACCPhys = VRM -> getPhys ( ResultReg ) ; assert ( ( ACCPhys >= <STR_LIT> && ACCPhys


<s> if ( MF . getFunction ( ) . optForSize ( ) ) return false ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . padShortFunctions ( ) ) return false ; TSM . init ( & MF . getSubtarget ( ) ) ; ReturnBBs . clear ( ) ; VisitedBBs . clear ( ) ; findReturns ( & MF . front ( ) ) ; bool MadeChange = false ; MachineBasicBlock * MBB ; unsigned int Cycles


<s> bool <ISA_LIT>ConstantPoolSymbol :: hasSameValue ( <ISA_LIT>ConstantPoolValue * ACPV ) { const <ISA_LIT>ConstantPoolSymbol * ACPS = dyn_cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) ; return ACPS && CPV_streq ( ACPS -> S , S

) && <ISA_LIT>ConstantPoolValue :: hasSameValue ( ACPV ) ;


<s> if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> && ! AM . isRIPRel ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base . Reg = N ; return


<s> if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget -> isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1 ) ; return SDValue ( Sub . getNode ( ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> target = nds32_legitimize_target ( icode , target ) ; pat = GEN_FCN ( icode ) (


<s> Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue


<s> assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; unsigned Domain = <STR_LIT> ; if ( Subtarget -> isSwift ( ) &&


<s> SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> )


<s> arm_file_end ( ) ; aof_dump_imports ( asm_out_file ) ; fputs ( <STR_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } if ( round_constant ) offset = ( ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ) ; switch ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) { case PLUS : if ( offset < <NUM_LIT> ) { offset = - offset ; sep = <STR_LIT> ; } else sep = <STR_LIT>


<s> unsigned CondMovOpc ; const TargetRegisterClass * RC ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; unsigned Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; unsigned Src2Reg = getRegForValue ( SI ->


<s> <ISA_LIT>DelaySlotFiller ( ) : MachineFunctionPass


<s> bool <ISA_LIT>TargetLowering :: enableAggressiveFMAFusion ( EVT


<s> return new <ISA_LIT>PassConfig ( this ,


<s> const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( Opcode , DL , NodeTys , Ops ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT>


<s> else return NULL_RTX ; if ( GET_MODE ( extended_op ) != SImode ) return NULL_RTX ; set_of_reg s = sh_find_set_of_reg ( extended_op , insn , prev_nonnote_insn_bb ) ; if ( s . set_src == NULL_RTX ) return NULL_RTX ; if ( t_reg_operand ( s . set_src , VOIDmode ) || negt_reg_operand ( s . set_src , VOIDmode ) ) return extended_op ; else if ( sh_is_logical_t_store_expr ( s . set_src , s . insn ) ) return extended_op ; return NULL_RTX


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { return ( getFramePointerReg ( ) == <STR_LIT> && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF


<s> if ( ! MinInstr ) MinInstr = Traces -> getEnsemble ( MachineTraceMetrics :: TS_MinInstrCount ) ; MachineTraceMetrics :: Trace Trace = MinInstr -> getTrace ( CmpConv . CmpBB ) ; if ( MinSize ) { int CodeSizeDelta = CmpConv . expectedCodeSizeDelta ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CodeSizeDelta << '\n' ) ; if ( CodeSizeDelta < <NUM_LIT> ) return true ; if ( CodeSizeDelta > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned DelayLimit = SchedModel . MispredictPenalty *


<s> return static_cast < const <ISA_LIT>Operand & > ( op ) .


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT>


<s> else ret = <NUM_LIT> + rs6000_register_move_cost ( mode , rclass , GENERAL_REGS ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode )


<s> Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; SDValue BP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDValue Ops [ <NUM_LIT> ] = { BP , Hi . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues (


<s> if ( ! getTargetMachine ( ) . getTargetTriple ( ) . isOSBinFormatELF ( ) )


<s> Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Name = Parser . getTok ( ) . getString ( ) ; SMLoc ExtLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } unsigned FeatureKind = <STR_LIT> ( Name ) ; if ( FeatureKind == <STR_LIT> ) Error ( ExtLoc , <STR_LIT> + Name


<s> SDValue Hi = DAG . getVectorShuffle ( InVT , dl , In , DAG . getUNDEF ( InVT ) , HiMask ) ; Hi = DAG . getNode ( Opc , dl , HalfVT , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; assert ( VT . is128BitVector ( ) && InVT . is128BitVector ( ) && <STR_LIT> ) ; SDValue Curr = In ; SDValue SignExt = Curr ; if ( InVT != <STR_LIT> ) { MVT DestVT = VT == <STR_LIT> ? <STR_LIT> : VT ; unsigned DestWidth = DestVT . getScalarSizeInBits ( ) ; unsigned Scale = DestWidth / InSVT . getSizeInBits ( ) ; unsigned InNumElts = InVT . getVectorNumElements ( ) ; unsigned DestElts = DestVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( InNumElts , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != DestElts ; ++ i ) Mask [ i * Scale + ( Scale - <NUM_LIT> ) ] = i ; Curr = DAG . getVectorShuffle ( InVT , dl , In , In , Mask ) ; Curr = DAG . getBitcast ( DestVT , Curr ) ; unsigned SignExtShift = DestWidth - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , DestVT , Curr , DAG . getTargetConstant ( SignExtShift , dl , <STR_LIT> ) ) ; } if ( VT == <STR_LIT> ) { assert ( Curr . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Sign = DAG . getSetCC ( dl , <STR_LIT> , Zero , Curr , <STR_LIT> ) ; SignExt = DAG . getVectorShuffle ( <STR_LIT> , dl , SignExt , Sign , { <NUM_LIT> ,


<s> mcInst . addOperand ( MCOperand :: createReg (


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment (


<s> WeakRefDirective = <STR_LIT> ; HasLCOMMDirective = true ; DwarfRequiresFrameSection = false ; SupportsDebugInformation =


<s> assert ( ( CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> ) && <STR_LIT> ) ; if ( CmpVT == <STR_LIT> && ! Subtarget . isAtom ( ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { ConstantSDNode * COp0 = dyn_cast < ConstantSDNode > ( Op0 ) ; ConstantSDNode * COp1 = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op0 . getOperand ( <NUM_LIT> ) ; unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits ( In ) + <NUM_LIT> ; if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op1 . getOperand


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI -> getOperand ( <NUM_LIT> )


<s> EVT VT0 = Op0 . getValueType ( ) ; EVT VT1 = Op1 . getValueType ( ) ; if ( VT0 != VT1 || ! VT0 . isSimple ( ) || ! VT0 . isInteger ( ) ) return SDValue ( ) ; APInt SplatVal ; if ( ! <STR_LIT> ( Op1 . getNode ( ) , SplatVal , false ) ||

! SplatVal . isMask ( ) ) return SDValue ( ) ;


<s> SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType >


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { std :: string ArgString ; const Function :: ArgumentListType & ArgList = MF -> getFunction ( ) -> getArgumentList ( ) ; bool First = true ; for ( Function :: ArgumentListType :: const_iterator iter = ArgList . begin ( ) ; iter != ArgList . end ( ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>leAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef

CPU , const MCTargetOptions & Options ) {


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || !


<s> IPI -> second . push_back ( & Use ) ; Instruction * OldInstr = IPI -> first ; Uses OldUses = std :: move ( IPI -> second ) ; InsertPts [ NewPt ] = std :: move


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; unsigned Qn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned fc ; if ( scalar ) { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT>


<s> if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue B = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue C = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDNodeFlags Flags = N -> getFlags ( ) ; if ( ! IsStrict && Flags . hasAllowReassociation ( ) && TLI . isOperationExpand ( <STR_LIT> , VT ) ) { SDValue Fmul = DAG . getNode ( <STR_LIT> , dl , VT , A , B , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fmul , C , Flags ) ; } EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; auto invertIfNegative = [ & DAG , & TLI , & DCI ] ( SDValue & V ) { bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( V , DAG , LegalOperations , CodeSize ) ) { V = NegV ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( Vec , DAG , LegalOperations , CodeSize ) ) { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegV , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue


<s> virtual bool gate ( function * ) { return ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_RENAME_FMA_REGS ) && optimize


<s> EVT VT = LHS . getValueType ( ) ; EVT CondVT = Cond . getValueType ( ) ; SDLoc DL ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( CondVT . isVector ( ) && <STR_LIT> ) ; bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; if ( TValIsAllZeros && Subtarget . hasAVX512 ( ) && Cond . hasOneUse ( ) && CondVT . getVectorElementType ( ) == <STR_LIT> ) { SDValue CondNew = DAG . getNOT ( DL , Cond , CondVT ) ; return DAG . getSelect ( DL , VT , CondNew , RHS , LHS ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros ||


<s> unsigned LaneSize = <NUM_LIT> ; SmallVector < int , <NUM_LIT> > MaskVal ( LaneSize , - <NUM_LIT> ) ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( Mask [ i + l ] < <NUM_LIT> ) continue ; if ( MaskVal [ i ] < <NUM_LIT> ) { MaskVal [ i ] = Mask [ i + l ] - l ; Imm8 |= MaskVal [ i ] << ( i * <NUM_LIT> ) ; continue ; } if ( Mask [ i + l ] != ( signed ) ( MaskVal [ i ] + l )


<s> bool function_checker :: require_immediate_one_of ( unsigned int rel_argno , HOST_WIDE_INT value0 , HOST_WIDE_INT value1 , HOST_WIDE_INT value2 , HOST_WIDE_INT value3 ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( actual != value0 && actual != value1 && actual != value2 && actual != value3 ) { report_not_one_of ( location , fndecl , argno , actual , value0 , value1 , value2 , value3 ) ; return false ; } return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( CoprocOption .


<s> return ( cfun && cfun -> machine && cfun ->


<s> return ; } Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; addExpr ( Inst , Memory


<s> } const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( Subtarget -> is32BitELFABI ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; if ( Kind == MCSymbolRefExpr :: VK_PLT && Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC ) TlsRef = MCBinaryExpr :: createAdd ( TlsRef , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const GlobalValue * GValue = MO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: create


<s> else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MBB != MI . getOperand ( <NUM_LIT> ) .


<s> if ( Name . find ( <STR_LIT> ) != std :: string :: npos ) { if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; } else


<s> static SDValue lowerToAddSubOrFMAddSub ( const BuildVectorSDNode * BV , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue Opnd0 , Opnd1 ; if ( ! isAddSub ( BV , Subtarget , DAG , Opnd0 , Opnd1 ) ) return SDValue ( ) ; MVT VT = BV -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( BV


<s> HOST_WIDE_INT val ; switch ( GET_CODE ( op ) ) { case CONST_INT : val = INTVAL ( op ) ; break ; case CONST_WIDE_INT : { int insns = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) insns += num_insns_constant_multi ( CONST_WIDE_INT_ELT ( op , i ) , DImode ) ; return insns ; } case CONST_DOUBLE : { const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( op ) ; if ( mode == SFmode || mode == SDmode ) { long l ; if ( mode == SDmode ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * rv , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * rv , l ) ; val = l ; mode = SImode ; } else if ( mode == DFmode || mode == DDmode ) { long l [ <NUM_LIT> ] ; if ( mode == DDmode ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * rv , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * rv , l ) ; val = ( unsigned HOST_WIDE_INT ) l [ WORDS_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ] << <NUM_LIT> ; val |= l [ WORDS_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ] & <NUM_LIT> ; mode = DImode ; } else if ( mode == TFmode || mode == TDmode || mode == KFmode || mode == IFmode ) { long l [ <NUM_LIT> ] ; int insns ; if ( mode == TDmode ) REAL_VALUE_TO_TARGET_DECIMAL128 ( * rv , l ) ; else REAL_VALUE_TO_TARGET_LONG_DOUBLE ( * rv , l ) ; val = ( unsigned HOST_WIDE_INT ) l [ WORDS_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ] << <NUM_LIT> ; val |= l [ WORDS_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ] & <NUM_LIT> ; insns = num_insns_constant_multi ( val , DImode ) ; val = ( unsigned HOST_WIDE_INT ) l [ WORDS_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ] << <NUM_LIT> ; val |= l [ WORDS_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ]


<s> return ! In64BitMode && isOSWindows (


<s> if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; I . removeTypes ( ) ; I . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : case TargetOpcode :: G_AND : case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ! Ty . isSized ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const unsigned OpSize = Ty . getSizeInBits ( ) ; { const RegisterBank * PrevOpBank = nullptr ; for ( auto & MO : I . operands ( ) ) { if ( ! MO . isReg ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank * OpBank = RBI . getRegBank ( MO . getReg ( ) , MRI , TRI ) ; if ( !


<s> DebugLoc dl = N -> getDebugLoc ( ) ; if ( ( VT == <STR_LIT> && OpVT == <STR_LIT> ) || ( VT == <STR_LIT> && OpVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( OpVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( OpVT , dl , Op , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( OpVT , dl , Op , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT ,


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lwpval32 ( unsigned int data2 , unsigned int data1 , unsigned int flags ) { __builtin_ia32_lwpval32 ( data2 , data1 , flags


<s> unsigned NumOfOperands = Op . getNumOperands ( ) ; assert ( isPowerOf2_32 ( NumOfOperands ) && <STR_LIT> ) ; SDValue Undef = DAG . getUNDEF ( ResVT ) ; if ( NumOfOperands > <NUM_LIT> ) { unsigned NumOfDefinedOps = <NUM_LIT> ; unsigned OpIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands ; i ++ ) if ( ! Op . getOperand ( i ) . isUndef ( ) ) { NumOfDefinedOps ++ ; OpIdx = i ; } if ( NumOfDefinedOps == <NUM_LIT> ) return Undef ; if ( NumOfDefinedOps == <NUM_LIT> ) { unsigned SubVecNumElts = Op . getOperand ( OpIdx ) . getValueType ( ) . getVectorNumElements ( ) ; SDValue IdxVal = DAG . getIntPtrConstant ( SubVecNumElts * OpIdx , dl ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , Op . getOperand ( OpIdx ) , IdxVal ) ; } MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT ,


<s> bool isGPR32as64 ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> void <ISA_LIT>ExpandPseudo :: CMSESaveClearFPRegs ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc & DL , const LivePhysRegs & LiveRegs , SmallVectorImpl < unsigned > & ScratchRegs ) { if ( STI -> hasV8_1MMainlineOps ( ) ) CMSESaveClearFPRegsV81 (


<s> size_t uns_fcode = ( size_t ) fcode ; const struct builtin_description * d ; size_t i ; rtx ret ; bool success ; HOST_WIDE_INT mask = rs6000_builtin_info [ uns_fcode ] . mask ; bool func_valid_p = ( ( rs6000_builtin_mask & mask ) == mask ) ; if ( TARGET_DEBUG_BUILTIN ) { enum insn_code icode = rs6000_builtin_info [ uns_fcode ] . icode ; const char * name1 = rs6000_builtin_info [ uns_fcode ] . name ; const char * name2 = ( ( icode != CODE_FOR_nothing ) ? get_insn_name ( ( int ) icode ) : <STR_LIT> ) ; const char * name3 ; switch ( rs6000_builtin_info [ uns_fcode ] . attr & RS6000_BTC_TYPE_MASK ) { default : name3 = <STR_LIT> ; break ; case RS6000_BTC_SPECIAL : name3 = <STR_LIT> ; break ; case RS6000_BTC_UNARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_BINARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_TERNARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_PREDICATE : name3 = <STR_LIT> ; break ; case RS6000_BTC_ABS : name3 = <STR_LIT> ; break ; case RS6000_BTC_EVSEL : name3 = <STR_LIT> ; break ; case RS6000_BTC_DST : name3 = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> , ( name1 ) ? name1 : <STR_LIT> , fcode , ( name2 ) ? name2 : <STR_LIT> , ( int ) icode , name3 , func_valid_p ? <STR_LIT> : <STR_LIT> ) ; } if ( ! func_valid_p ) { rs6000_invalid_builtin ( fcode ) ; return expand_call ( exp , target , ignore ) ; } switch ( fcode ) { case RS6000_BUILTIN_RECIP : return rs6000_expand_binop_builtin ( CODE_FOR_recipdf3 , exp , target ) ; case RS6000_BUILTIN_RECIPF : return rs6000_expand_binop_builtin ( CODE_FOR_recipsf3 , exp , target ) ; case RS6000_BUILTIN_RSQRTF : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtsf2 , exp , target ) ; case RS6000_BUILTIN_RSQRT : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtdf2 , exp , target ) ; case POWER7_BUILTIN_BPERMD : return rs6000_expand_binop_builtin ( ( ( TARGET_64BIT ) ? CODE_FOR_bpermd_di : CODE_FOR_bpermd_si ) , exp , target ) ; case RS6000_BUILTIN_GET_TB : return rs6000_expand_zeroop_builtin ( CODE_FOR_rs6000_get_timebase , target ) ; case RS6000_BUILTIN_MFTB : return rs6000_expand_zeroop_builtin ( ( ( TARGET_64BIT ) ? CODE_FOR_rs6000_mftb_di : CODE_FOR_rs6000_mftb_si ) , target ) ; case RS6000_BUILTIN_MFFS : return rs6000_expand_zeroop_builtin ( CODE_FOR_rs6000_mffs , target ) ; case RS6000_BUILTIN_MTFSF : return rs6000_expand_mtfsf_builtin ( CODE_FOR_rs6000_mtfsf , exp ) ; case RS6000_BUILTIN_CPU_INIT : case RS6000_BUILTIN_CPU_IS : case RS6000_BUILTIN_CPU_SUPPORTS : return cpu_expand_builtin ( fcode ,


<s> for ( CPEntry & CPE : CPEs ) { if ( CPE . CPEMI == CPEMI ) return & CPE ; } return


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = MI -> getOperand ( <NUM_LIT>


<s> return __builtin_ia32_bextr_u64 ( __X , ( ( __Y & <NUM_LIT> ) | ( ( __Z & <NUM_LIT> )


<s> int64_t Offset = TargetFrameLowering :: getFrameIndexReference ( MF


<s> unsigned Scale = <NUM_LIT> ; int UOpc = <STR_LIT> ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; default : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & MI , MaxOffs , IsCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned Op = <NUM_LIT> , E = MI . getNumOperands ( ) ; Op != E ; ++ Op ) if ( MI . getOperand ( Op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT>


<s> Position . Address = alignTo ( Position . Address , Block . Alignment ) ; Block . Address = Position . Address ; Position . Address += Block


<s> static enum unwind_info_type rs6000_xcoff_debug_unwind_info (


<s> if ( NumElts > EltSizeInBits ) { assert ( ( NumElts % EltSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = NumElts / EltSizeInBits ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , EltSizeInBits ) ; Vec = DAG . getNode ( <STR_LIT> , DL , BroadcastVT , N00 ) ; Vec = DAG . getBitcast ( VT , Vec ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) ShuffleMask . append ( EltSizeInBits , i ) ; Vec = DAG . getVectorShuffle ( VT , DL , Vec , Vec , ShuffleMask ) ; } else if ( Subtarget . hasAVX2 ( ) && NumElts < EltSizeInBits && ( SclVT == <STR_LIT> || SclVT == <STR_LIT> || SclVT == <STR_LIT> ) ) { assert ( ( EltSizeInBits % NumElts ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = EltSizeInBits / NumElts ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , NumElts * Scale ) ; Vec = DAG . getNode ( <STR_LIT> , DL , BroadcastVT , N00 ) ; ShuffleMask . append ( NumElts * Scale , <NUM_LIT> ) ; Vec = DAG . getVectorShuffle ( BroadcastVT , DL , Vec , Vec , ShuffleMask ) ; Vec = DAG . getBitcast ( VT , Vec ) ; } else { SDValue Scl = DAG . getAnyExtOrTrunc ( N00 , DL , SVT ) ; Vec = DAG . getNode ( <STR_LIT> , DL , VT , Scl ) ; ShuffleMask . append ( NumElts ,


<s> const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setHasCalls ( true ) ; SDValue TGA = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 , DAG ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , TGA ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr ,


<s> static SDValue narrowLoadToVZLoad ( LoadSDNode * LN , MVT MemVT , MVT VT , SelectionDAG & DAG ) { if ( ! LN -> isSimple ( ) ) return SDValue ( ) ; SDVTList Tys = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( LN ) , Tys , Ops , MemVT , LN -> getPointerInfo (

) , LN -> getOriginalAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options


<s> for ( unsigned int opcount = <NUM_LIT> ; opcount < <NUM_LIT> ; opcount ++ ) if ( I -> getOperand ( opcount ) . isReg ( ) ) { lastCmpRegs [ regCount ++ ] = I -> getOperand ( opcount ) . getReg ( ) ; } lastCmp = & ( * I ) ; } } else { if ( ! ( I -> isBranch ( ) ) && ! ( I -> mayStore ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) && I -> getOpcode ( ) != <STR_LIT> ) { for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) if ( I -> getOperand ( opcount ) . isReg ( ) ) { if ( opcount == <NUM_LIT> && ! ( I -> mayStore ( ) ) ) { int targetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( targetReg == lastCmpRegs [ <NUM_LIT> ] || targetReg == lastCmpRegs [ <NUM_LIT> ] ) { canMoveCmp = false ; if ( targetReg == lastCmpRegs [ <NUM_LIT> ] ) overwriteCmpsTwo [ <NUM_LIT> ] = true ; if ( targetReg == lastCmpRegs [ <NUM_LIT> ] ) overwriteCmpsTwo [ <NUM_LIT> ] = true ; } overwrittedRegList . push_back ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } else if ( I -> mayStore ( ) ) { isThereAnyStoreBetween = true ; unsigned target = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; storeList . push_back ( & ( * I ) ) ; for ( std :: list < unsigned int > :: const_iterator overIter = overwrittedRegList . begin ( ) ; overIter != overwrittedRegList . end ( ) ; ++ overIter ) if ( target == * overIter ) { canMoveStore = false ; break ; } } else if ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) { errs ( ) << <STR_LIT> ; MBB -> dump ( ) ; if ( lastCmp != NULL ) { lastCmpRegs [ <NUM_LIT> ] = - <NUM_LIT> ; lastCmpRegs [ <NUM_LIT> ] = - <NUM_LIT> ; lastCmp = NULL ; overwrittedRegList . clear ( ) ; storeList . clear ( ) ; canMoveStore = true ; canMoveCmp = true ; overwriteCmpsTwo [ <NUM_LIT> ] = false ; overwriteCmpsTwo [ <NUM_LIT> ] = false ; isThereAnyStoreBetween = false ; } int regCount = <NUM_LIT> ; for ( unsigned int opcount = <NUM_LIT> ; opcount < <NUM_LIT> ; opcount ++ ) if ( I -> getOperand ( opcount )


<s> inline vector unsigned char vec_vmaxub ( vector unsigned char a1 ,


<s> static int keep_cache_entry ( tree_map * & m ) { return ggc_marked_p ( m -> base


<s> JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E =


<s> return ( ( vec_int4 ) ( si_orx ( ( qword


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock ::


<s> else if ( label && ! NEXT_INSN ( label ) ) { if ( addr + <NUM_LIT> - bp -> address <= CONDJUMP_MAX ) bp -> insert_place = insn ; else gen_far_branch ( bp ) ; } } if ( ! label || ( NEXT_INSN ( label ) && bp -> address - addr < CONDJUMP_MIN ) ) { bp -> near_label = label = gen_label_rtx ( ) ; bp -> insert_place = insn ; bp -> address = addr ; } ok = redirect_jump ( as_a < rtx_jump_insn * > ( insn ) , label , <NUM_LIT> ) ; gcc_assert ( ok ) ; } else { rtx temp = XEXP ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , <NUM_LIT> ) ; beyond = next_active_insn ( as_a < rtx_insn * > ( temp ) ) ; if ( beyond && ( JUMP_P ( beyond ) || ( ( beyond = next_active_insn ( beyond ) ) && JUMP_P ( beyond ) ) ) && GET_CODE ( PATTERN ( beyond ) ) == SET && recog_memoized ( beyond ) == CODE_FOR_jump_compact && ( ( INSN_ADDRESSES ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( beyond ) ) , <NUM_LIT> ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) + ( unsigned ) <NUM_LIT> ) > <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( beyond , INSN_ADDRESSES ( INSN_UID ( beyond ) ) , <NUM_LIT> ) ; } next = next_active_insn ( insn ) ; if ( next && ( JUMP_P ( next ) || ( ( next = next_active_insn ( next ) ) && JUMP_P ( next ) ) ) && GET_CODE ( PATTERN ( next ) ) == SET && recog_memoized ( next ) == CODE_FOR_jump_compact && ( ( INSN_ADDRESSES ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( next ) ) , <NUM_LIT> ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) + ( unsigned ) <NUM_LIT> ) > <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( next , INSN_ADDRESSES ( INSN_UID ( next ) ) , <NUM_LIT> ) ; } else if ( type == TYPE_JUMP || type == TYPE_RETURN ) { int addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; rtx_insn * far_label = <NUM_LIT> ; int dest_uid = <NUM_LIT> ; struct far_branch * bp ; if ( type == TYPE_JUMP ) { if ( CROSSING_JUMP_P ( insn ) ) { emit_insn_before ( gen_block_branch_redirect ( const0_rtx ) , insn ) ; continue ; } far_label = as_a < rtx_insn * > ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT>


<s> if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , ( define_p ) ? <STR_LIT> : <STR_LIT>


<s> bool mips_split_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_mult_move_p ( dest , src , split_type ) ) return false ; unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == <NUM_LIT> && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == <NUM_LIT> && ISA_HAS_LDC1_SDC1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( dest ) ) ) return mips_split_128bit_move_p ( dest , src ) ; return size >


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx xops [ <NUM_LIT> ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ <NUM_LIT> ] , tmp , operands [ <NUM_LIT> ] ) ) ; return true


<s> static Register getVM512Lower ( Register reg ) { return getVM512Upper ( reg ) +


<s> if ( ! MLxEntryMap . insert ( std :: make_pair ( <ISA_LIT>_MLxTable [ i ] . MLxOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i


<s> return ( ( vec_int4 ) ( si_mpys ( ( qword ) ( a ) , (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > (


<s> return hasReservedCallFrame ( MF ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || ( hasFP ( MF ) && ! TRI -> hasStackRealignment ( MF ) ) || TRI


<s> <ISA_LIT>ebTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef

FS , Reloc :: Model RM , CodeModel :: Model CM ) :


<s> unsigned VF = cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumVectorRegs ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector +


<s> void setSVECalleeSavedStackSize ( unsigned Size ) { SVECalleeSavedStackSize =


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple ::

MachO ) return createMachOStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ;


<s> if ( VAL_14_BITS_P ( disp ) ) { insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , plus_constant ( gen_rtx_REG ( Pmode , base ) , disp ) ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) , REG_NOTES ( insn ) ) ; } else { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH


<s> return ( Imm >> ( ChunkIdx * <NUM_LIT> ) ) &


<s> unsigned PtrByteSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; nAltivecParamsAtEnd = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { SDValue Arg = TheCall -> getArg ( i ) ; <STR_LIT> Flags = TheCall -> getArgFlags ( i ) ; MVT ArgVT = Arg . getValueType ( ) ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { if ( ! isVarArg && ! is<ISA_LIT>64 ) { nAltivecParamsAtEnd ++ ; continue ; } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( Arg , Flags , isVarArg , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , isMachoABI ) ) ; if ( CC == CallingConv ::


<s> <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx + <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; ++ NumRegs ; } if ( Binary & <NUM_LIT> )


<s> return ( __m512i ) __builtin_ia32_psrav8di_mask ( ( __v8di ) __X , ( __v8di ) __Y , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 )


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ) ; MI -> eraseFromParent ( ) ; return MBB


<s> rtx base_address = gen_rtx_MEM ( Pmode , pointer ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ix86_save_reg ( regno , maybe_eh_return ) ) { if ( TARGET_64BIT && offset != trunc_int_for_mode ( offset , SImode ) ) { rtx


<s> adjustLiveRegs ( Bundle . Mask , Term ) ; if ( ! Bundle . Mask ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } DEBUG ( dbgs ( ) << <STR_LIT> << BundleIdx << <STR_LIT> ) ; if ( Bundle . isFixed ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; shuffleStackTop ( Bundle . FixStack , Bundle . FixCount , Term ) ; } else { DEBUG ( dbgs ( ) <<


<s> if ( TARGET_64BIT && ix86_abi == MS_ABI ) d_add_builtin_version ( <STR_LIT> ) ; else if ( ! TARGET_64BIT ) d_add_builtin_version


<s> tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = <NUM_LIT> ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ( size + UNITS_PER_WORD - <NUM_LIT> ) & - UNITS_PER_WORD ; align = <NUM_LIT> ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= <NUM_LIT> * ( unsigned ) BITS_PER_WORD ) align = <NUM_LIT> * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == <NUM_LIT> ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - <NUM_LIT> ) ; incr = fold_convert ( sizetype , incr ) ; incr = fold_build2 ( BIT_AND_EXPR , sizetype , incr , size_int ( - align ) ) ; incr = fold_convert ( ptr_type_node , incr ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold_build_pointer_plus_hwi ( incr , rsize - size ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr


<s> const MCExpr * Value ; MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext (


<s> else if ( Imm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( Imm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( Imm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else return MCDisassembler :: Fail ; return MCDisassembler ::


<s> return selectAddrRegImm16 ( Addr , Base , Offset ) || selectAddrDefault ( Addr , Base , Offset


<s> } return SDValue ( ) ; } if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( Subtarget . hasAVX ( ) && VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget


<s> unsigned <ISA_LIT>FastISel :: emitLSL_ri ( MVT RetVT , MVT SrcVT , unsigned Op0 , bool Op0IsKill , uint64_t Shift , bool IsZExt ) { assert ( RetVT . SimpleTy >= SrcVT . SimpleTy && <STR_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; unsigned ImmR = RegSize - Shift ; unsigned ImmS = std :: min < unsigned > ( SrcBits - <NUM_LIT> , DstBits - <NUM_LIT> - Shift ) ; static const unsigned OpcTable [ <NUM_LIT> ] [


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const AddrMode & AM


<s> FunctionPass * llvm :: create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>TargetMachine & TM , MachineCodeEmitter & MCE ) { return new Emitter < MachineCodeEmitter >


<s> assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function


<s> static inline bool helper_use_relative_reloc ( const ResolveInfo & pSym , const


<s> void <ISA_LIT>SEInstrInfo :: expandPseudoMFHiLo ( MachineBasicBlock & MBB ,

MachineBasicBlock :: iterator I , unsigned NewOpc ) const {


<s> static inline unsigned getT1Imm5 ( uint32_t insn ) { return slice ( insn , <NUM_LIT>


<s> SDLoc OpDL ( Op ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue NOOP ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , VTs , Ops )


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> &&


<s> return ( __mmask64 ) __builtin_ia32_kshiftridi ( ( __mmask64 ) __A ,


<s> return __builtin_ia32_vtestzps ( ( __v4sf ) __M , (


<s> unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> ( EncodedImm , EltBits ) ; O << markup (


<s> OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) , EqTy ) ) ; return MatchOperand_Success ; } Lex (


<s> static void get_pc_thunk_name ( char name [ <NUM_LIT> ] , unsigned int regno ) { gcc_assert ( ! TARGET_64BIT ) ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> , reg_names [ regno ] ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , <STR_LIT> ,


<s> static DecodeStatus DecodeBranchTarget7MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( - CE -> getValue ( )


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc


<s> addPass ( create<ISA_LIT>ExpandAtomicPseudoPass (


<s> return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) ->


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) && ! STI . isTargetNaCl ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT>


<s> SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue CP = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , GOTFlag ) ; CP = DAG . getNode ( <STR_LIT> , dl , ValTy , CP ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , OFSTFlag ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , ValTy , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , ValTy


<s> std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isOSWindows ( ) || ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> unsigned MOp , FOp ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : MOp = <STR_LIT> ; FOp = <STR_LIT> ; break ; case <STR_LIT> : MOp = <STR_LIT> ; FOp = <STR_LIT> ; break ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; MachineOperand MSrc = MI -> getOperand ( <NUM_LIT> ) ; unsigned VSrc = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Disp = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand ZeroDisp = MachineOperand :: CreateImm ( <NUM_LIT> ) ; bool hasDisp = Disp . isGlobal ( ) || Disp . isImm ( ) ; if ( hasDisp && MSrc . isReg ( ) ) MSrc . setIsKill ( false ) ; MachineInstrBuilder MIM = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) . addOperand ( MSrc ) . addImm (

<NUM_LIT> ) . addReg ( <NUM_LIT> ) . addDisp ( hasDisp ? Disp : ZeroDisp , <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> ++ StridedLoads ; if ( StridedLoads > MaxStridedLoads / <NUM_LIT> ) return StridedLoads ; } } return StridedLoads ; } ; int StridedLoads = countStridedLoads ( L , SE ) ; DEBUG ( dbgs ( ) << <STR_LIT> << StridedLoads << <STR_LIT> ) ; if ( StridedLoads ) { UP . MaxCount = <NUM_LIT> << Log2_32 ( MaxStridedLoads / StridedLoads ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UP


<s> bool FixupBWInstPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! FixupBWInsts || skipFunction ( MF . getFunction ( ) ) ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; LiveRegs . init ( TII -> getRegisterInfo ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; LLVM_DEBUG ( dbgs ( )


<s> if ( left ) return aarch64_const_vec_all_same_in_range_p ( x , <NUM_LIT> , bit_width - <NUM_LIT> ) ; else return aarch64_const_vec_all_same_in_range_p ( x , <NUM_LIT> , bit_width


<s> assert ( Kind == k_MatrixRegister && <STR_LIT>


<s> int idx ; gen_cas_fn gen ; const gen_cas_fn split_cas [ ] = { gen_aarch64_compare_and_swapqi , gen_aarch64_compare_and_swaphi , gen_aarch64_compare_and_swapsi , gen_aarch64_compare_and_swapdi } ; const gen_cas_fn atomic_cas [ ] = { gen_aarch64_compare_and_swapqi_lse , gen_aarch64_compare_and_swaphi_lse , gen_aarch64_compare_and_swapsi_lse , gen_aarch64_compare_and_swapdi_lse } ; bval = operands [ <NUM_LIT> ] ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : cmp_mode =


<s> if ( N . getOpcode ( ) == <STR_LIT> ) N = N . getOperand ( <NUM_LIT> ) ; if ( N . getOpcode ( ) != <STR_LIT> ) return


<s> static bool is_costly_group ( rtx * group_insns , rtx next_insn ) { int i ; rtx link ; int cost ; int issue_rate = rs6000_issue_rate ( ) ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { rtx insn = group_insns [ i ] ; if ( ! insn ) continue ; for ( link = INSN_DEPEND ( insn ) ; link != <NUM_LIT> ; link = XEXP ( link , <NUM_LIT> ) ) { rtx next = XEXP ( link , <NUM_LIT> ) ; if ( next == next_insn ) { cost = insn_cost ( insn , link


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xsusldtrk ( void ) { __builtin_ia32_xsusldtrk (


<s> static __inline vec_double2 spu_msub ( vec_double2 a , vec_double2 b , vec_double2 c ) { return ( ( vec_double2 ) ( si_dfms ( ( qword ) ( a ) , ( qword ) ( b ) ,


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done &&


<s> unsigned getDPRCalleeSavedAreaOffset ( ) const { return


<s> static SDValue LowerSTORE ( SDValue Op , SelectionDAG & DAG ) { SDLoc dl ( Op ) ; StoreSDNode * St = cast < StoreSDNode > ( Op . getNode ( ) ) ; EVT MemVT = St -> getMemoryVT ( ) ; if ( MemVT == <STR_LIT> ) return LowerF128Store ( Op , DAG ) ; if ( MemVT == <STR_LIT> ) { SDValue Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , St -> getValue ( ) ) ; SDValue Chain = DAG . getStore ( St -> getChain ( ) , dl , Val , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) , St -> getAAInfo ( ) ) ; return Chain ; } return SDValue ( )


<s> if ( GET_MODE_UNIT_SIZE ( vmode ) > <NUM_LIT> ) return false ; if ( ! d -> perm [ <NUM_LIT> ] . is_constant ( & odd ) || ( odd != <NUM_LIT> && odd != <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , odd , <NUM_LIT> ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1


<s> __inline__ static unsigned long long sh_media_MEXTR2 ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> if ( UsedReg == FramePtr ) { unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if ( UsedReg == BasePtr ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , BasePtr ) , FramePtr , false , EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; assert ( <ISA_LIT>FI -> getHasSEHFramePtrSave ( ) ) ; int Offset = getFrameIndexReference ( MF , <ISA_LIT>FI -> getSEHFramePtrSaveIndex ( ) , UsedReg ) ; assert ( UsedReg == BasePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FramePtr ) , UsedReg , true , Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { llvm_unreachable ( <STR_LIT> )


<s> MCInstLowering . Initialize ( & MF -> getContext ( )


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; } } else { assert ( ! strcmp ( Modifier , <STR_LIT> )


<s> static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs ) ; if ( RegNum != NumArgRegs && RegNum % <NUM_LIT> == <NUM_LIT> ) { State . AllocateReg ( ArgRegs [ RegNum ]


<s> bool targetHandlesStackFrameRounding ( ) const override { return true


<s> inline SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> bool Thumb2ITBlockPass :: MoveCopyOutOfITBlock ( MachineInstr * MI , <STR_LIT> CC , <STR_LIT> OCC , SmallSet < unsigned , <NUM_LIT> > & Defs , SmallSet < unsigned , <NUM_LIT> > & Uses ) { if ( ! isCopy ( MI ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent


<s> BitGroup ( SDValue V , unsigned R , unsigned S , unsigned E ) : V ( V ) , RLAmt ( R ) , StartIdx ( S ) , EndIdx ( E ) , Repl32 ( false ) , Repl32CR ( false ) , Repl32Coalesced ( false ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << V . getNode ( ) << <STR_LIT> << R


<s> if ( MI . mayLoad ( ) && MI . getNumOperands ( ) > <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isCPI ( ) ) return MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return -


<s> SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false


<s> static DecodeStatus DecodeACRegsDSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> )


<s> bool <ISA_LIT>InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) )


<s> PM -> add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( )


<s> default : return MCDisassembler :: Fail ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Mask = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! ( FeatureBits [ <STR_LIT> ] ) ) { if ( Mask != <NUM_LIT> ) S = MCDisassembler :: SoftFail ; } else { if ( Mask == <NUM_LIT> || ( Mask != <NUM_LIT> && ValLow > <NUM_LIT> ) || ( ! ( FeatureBits [ <STR_LIT> ] ) && ( Mask & <NUM_LIT> ) ) ) S = MCDisassembler :: SoftFail ; } } } else { if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( Val )


<s> MachineBasicBlock * NewMBB = emitBlockAfter ( MBB ) ; NewMBB -> splice ( NewMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; return


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GO , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isData ( ) && IsGlobalInSmallSection ( GO , TM , Kind ) ) return SmallDataSection ; if ( Kind . isReadOnly ( ) && IsGlobalInSmallSection ( GO , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReferenceSP ( const MachineFunction & MF , int FI , Register & FrameReg , int Adjustment ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FrameReg = TRI -> getStackRegister (


<s> Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( LocVT . getSizeInBits ( ) ) , Val ) ; } else { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( ValVT . getSizeInBits ( ) ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( LocVT . getSizeInBits ( ) ) , Val ) ; } return DAG . getNode ( <STR_LIT> ,