<s> static void expandf64Toi32 ( SDValue Op , SelectionDAG & DAG , SDValue & RetVal1 , SDValue & RetVal2 ) { if ( isFloatingPointZero ( Op ) ) { RetVal1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; RetVal2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return ; } if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) { SDValue Ptr = Ld -> getBasePtr ( ) ; RetVal1 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , Ptr , Ld -> getSrcValue ( ) , Ld -> getSrcValueOffset ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> getAlignment ( ) ) ; EVT PtrType = Ptr . getValueType ( ) ; unsigned NewAlign = MinAlign ( Ld -> getAlignment ( ) , <NUM_LIT> ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) ,

PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , PtrType ) ) ;


<s> case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_8 ; insn -> displacementSize = <NUM_LIT> ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaRegBase + rm ) ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; } break ; case <NUM_LIT> : case <NUM_LIT> : insn -> eaBaseBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_EAX : EA_BASE_RAX ) ; switch ( mod ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; switch ( rm & <NUM_LIT> ) { case <NUM_LIT> : insn -> eaBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_sib : EA_BASE_sib64 ) ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_32 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; break ; } break ; case <NUM_LIT> : insn -> displacementSize = <NUM_LIT> ; case <NUM_LIT> : insn -> eaDisplacement = ( mod == <NUM_LIT> ? EA_DISP_8 : EA_DISP_32 ) ; switch ( rm & <NUM_LIT>


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( TM . is<ISA_LIT>64 ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . is<ISA_LIT>64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , <STR_LIT> ) ; else markSuperRegs ( Reserved , <STR_LIT> )


<s> static int ck810_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( code == CONST_INT && TARGET_HARD_FLOAT && CSKY_VREG_MODE_P ( mode ) ) return ( INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) >= <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( code == CONST_INT ) { if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return ( INTVAL ( index ) < CSKY_LD32_MAX_OFFSET ( SImode ) && INTVAL ( index ) >= <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && INTVAL ( index ) <= CSKY_LD32_MAX_OFFSET ( mode ) && INTVAL ( index ) >= <NUM_LIT> ) return ( ( INTVAL ( index ) % GET_MODE_SIZE ( mode ) ) == <NUM_LIT> ) ; } else if ( code == UNSPEC ) return ( flag_pic == <NUM_LIT> && ( XINT ( index , <NUM_LIT> ) == UNSPEC_PIC_SYMBOL_PLT || XINT ( index , <NUM_LIT> ) == UNSPEC_PIC_SYMBOL_GOT ) ) ; else if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> || ( TARGET_HARD_FLOAT && CSKY_VREG_MODE_P ( mode ) ) ) { if ( is_csky_address_register_rtx_p ( index , strict_p ) ) return <NUM_LIT> ; else if ( code == MULT || code == ASHIFT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index , <NUM_LIT> ) ; return ( is_csky_address_register_rtx_p ( xiop0 , strict_p ) && CONST_INT_P ( xiop1 ) && is_ldr_shift_p ( INTVAL ( xiop1 ) , code ) ) ; } } return


<s> void <ISA_LIT>SETargetLowering :: addMSAIntType ( <STR_LIT> Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty ,


<s> if ( Is64Bit ) { Has<ISA_LIT>_64 = true ; HasCMov = true ; } DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! Is64Bit || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( TT . length ( ) > <NUM_LIT> ) { size_t Pos ; if ( ( Pos = TT . find ( <STR_LIT> ) ) != std :: string :: npos ) { TargetType = isDarwin ; if ( isdigit ( TT [ Pos + <NUM_LIT> ] ) ) DarwinVers = atoi ( & TT [ Pos + <NUM_LIT> ] ) ; else DarwinVers = <NUM_LIT> ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isELF ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isCygwin ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isMingw ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isWindows ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isWindows ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isDarwin


<s> Register ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = Opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT> ) ; assert ( ( NumBytes - EncodedBytes ) %


<s> pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue BV = DAG . getBuildVector ( <STR_LIT> , DL , pshufbMask ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , BV ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , ShufMask ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( VT , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , Undef , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( <STR_LIT> , DL , OpHi , Undef , ShufMask1 ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue res = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , OpHi , ShufMask2 ) ; return DAG . getBitcast ( <STR_LIT> , res ) ; } if ( ! VT . is128BitVector ( ) || ! InVT .

is256BitVector ( ) ) return SDValue ( ) ;


<s> NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( OutReg , true , false , false , isDead ) , FrameIndex ) ; } } else if ( Opc == <STR_LIT> ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill ) , FrameIndex ) ; } else { unsigned OutReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( OutReg , true , false , false , isDead ) , FrameIndex ) ; } } else if ( Opc == <STR_LIT> ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill ) , FrameIndex ) ; } else { unsigned OutReg = MI -> getOperand ( <NUM_LIT> ) . getReg


<s> Relocation :: Type type = pRelocation . type ( ) ; if ( type > <NUM_LIT> ) { return Relocator ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> Value * <ISA_LIT>IREmitter :: visitVTRUNC ( const SDNode * N


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( SrcReg ) && ! RI . isLowRegister ( SrcReg ) ) return false ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( DstReg ) && ! RI . isLowRegister ( DstReg ) ) return false ; } return true ; } case <STR_LIT> : case <STR_LIT>


<s> llvm :: FunctionPass * llvm :: create<ISA_LIT>ModuleISelDagPass ( <ISA_LIT>TargetMachine


<s> void <ISA_LIT>LowOverheadLoops :: Expand ( LowOverheadLoop & LoLoop ) { auto ExpandLoopEnd = [ this ] ( LowOverheadLoop & LoLoop ) { MachineInstr * End = LoLoop . End ; MachineBasicBlock * MBB = End -> getParent ( ) ; unsigned Opc = LoLoop . IsTailPredicationLegal ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . Dec -> eraseFromParent ( ) ; End -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop ) ; RemoveDeadBranch ( LoLoop . End ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) ConvertVPTBlocks ( LoLoop ) ; for ( auto * I : LoLoop . ToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; I -> eraseFromParent ( ) ; } } PostOrderLoopTraversal DFS ( LoLoop . ML , * MLI ) ; DFS . ProcessLoop ( ) ; const SmallVectorImpl < MachineBasicBlock * > & PostOrder = DFS . getOrder ( ) ; for ( auto * MBB : PostOrder ) { recomputeLiveIns ( * MBB ) ; MBB -> sortUniqueLiveIns ( )


<s> fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'w' ) msize = <NUM_LIT> ; else if ( code == 'b' ) msize = <NUM_LIT> ; else if ( code == 'k' ) msize = <NUM_LIT> ; else if ( code == 'q' ) msize = <NUM_LIT> ; else if ( code == 'h' ) msize = <NUM_LIT> ; else if ( code == 'x' ) msize = <NUM_LIT> ; else if ( code == 't' ) msize = <NUM_LIT> ; else if ( code == 'g' ) msize = <NUM_LIT> ; else msize = GET_MODE_SIZE ( GET_MODE ( x ) ) ; regno = REGNO ( x ) ; if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM || regno == FPSR_REG ) { output_operand_lossage ( <STR_LIT> , reg_names [ regno ] ) ; return ; } else if ( regno == FLAGS_REG ) { output_operand_lossage ( <STR_LIT> ) ; return ; } if ( code == 'V' ) { if ( GENERAL_REGNO_P ( regno ) ) msize = GET_MODE_SIZE ( word_mode ) ; else error ( <STR_LIT> ) ; } duplicated = code == 'd' && TARGET_AVX ; switch ( msize ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( GENERAL_REGNO_P ( regno ) && msize > GET_MODE_SIZE ( word_mode ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; case <NUM_LIT> : if ( LEGACY_INT_REGNO_P ( regno ) ) putc ( msize > <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : normal : reg = hi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; if ( ! ANY_QI_REGNO_P ( regno ) ) error ( <STR_LIT> ) ; reg = qi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; reg = qi_high_reg_name [ regno ] ; break ; case <NUM_LIT> : case <NUM_LIT> : if ( SSE_REGNO_P ( regno ) ) { gcc_assert ( !


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default


<s> O << <STR_LIT> ; printLeaMemReference ( MI , OpNo ,


<s> static const Constant * getTargetConstantFromNode ( SDValue Op ) { Op = peekThroughBitcasts ( Op ) ; auto * Load = dyn_cast < LoadSDNode > ( Op ) ; if ( ! Load )


<s> if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> return ( uint8_t ) __builtin_aarch64_reduc_plus_scal_v16qi ( ( int8x16_t


<s> return DecodeCAS ( MI , insn , Address , Decoder , false


<s> assert ( std :: is_sorted ( std :: begin ( BroadcastFoldTable2 ) , std :: end ( BroadcastFoldTable2 ) ) && std :: adjacent_find ( std :: begin ( BroadcastFoldTable2 ) , std :: end ( BroadcastFoldTable2 ) ) == std :: end ( BroadcastFoldTable2 ) && <STR_LIT> ) ; assert ( std :: is_sorted ( std :: begin ( BroadcastFoldTable3 ) , std :: end ( BroadcastFoldTable3 ) ) && std :: adjacent_find ( std :: begin ( BroadcastFoldTable3 ) , std :: end ( BroadcastFoldTable3 ) ) == std :: end ( BroadcastFoldTable3 ) && <STR_LIT> ) ; FoldTablesChecked . store ( true , std :: memory_order_relaxed ) ; } const <ISA_LIT>MemoryFoldTableEntry * Data = llvm :: lower_bound ( Table , RegOp ) ; if ( Data != Table . end ( ) && Data -> KeyOp == RegOp && ! ( Data -> Flags & TB_NO_FORWARD )


<s> MachineBasicBlock * NewMBB = emitBlockAfter ( MBB ) ; NewMBB -> splice ( NewMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB ->


<s> if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) return false ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF .

getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> unsigned <ISA_LIT>ABIInfo :: GetEhDataReg ( unsigned I ) const { static const unsigned EhDataReg [ ] = { <STR_LIT> , <STR_LIT>


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction


<s> for ( j = XVECLEN ( x , <NUM_LIT> ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , <NUM_LIT> ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( note ) == REG &&

GET_MODE ( note ) == mode ) reg_weight -- ;


<s> static bool aarch_rev16_p_1 ( rtx lhs , rtx rhs , machine_mode mode ) { if ( GET_CODE ( lhs ) == AND && GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( lhs , <NUM_LIT> ) , <NUM_LIT> ) ) && INTVAL ( XEXP ( XEXP ( lhs , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && REG_P ( XEXP ( XEXP ( lhs , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( lhs , <NUM_LIT> ) ) && GET_CODE ( rhs ) == AND && GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == LSHIFTRT && REG_P ( XEXP ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) ) && INTVAL ( XEXP ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && CONST_INT_P ( XEXP ( rhs , <NUM_LIT> ) ) && REGNO ( XEXP ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) ) == REGNO ( XEXP ( XEXP ( lhs , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx lhs_mask = XEXP ( lhs ,


<s> MOP . setReg ( GetMatchingSubReg ( MOP . getReg ( ) ) ) ; SeenDef = true ; } } } else { for ( auto & MOP : MI . operands ( ) ) { if ( MOP . isReg ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) { assert ( ( MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) ) ) && <STR_LIT> ) ; MOP . setReg ( GetMatchingSubReg ( MOP . getReg ( ) ) ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return true ; } ; forAllMIsUntilDef ( * I , RegToRename , TRI , LdStLimit , UpdateMIs ) ; for ( auto & MI : iterator_range < MachineInstrBundleIterator < llvm :: MachineInstr >> ( std :: next ( I ) , std :: next ( Paired ) ) ) assert ( all_of ( MI . operands ( ) , [ this , & RenameReg ] ( const MachineOperand & MOP ) { return ! MOP . isReg ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , * RenameReg ) ; } ) && <STR_LIT> <STR_LIT> ) ; } MachineBasicBlock :: iterator InsertionPoint = MergeForward ? Paired : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * Paired ) : getLdStBaseOp ( * I ) ; int Offset = getLdStOffsetOp ( * I ) . getImm ( ) ; int PairedOffset = getLdStOffsetOp ( * Paired ) . getImm ( ) ; bool PairedIsUnscaled = TII -> hasUnscaledLdStOffset ( Paired -> getOpcode ( ) ) ; if ( IsUnscaled != PairedIsUnscaled ) { int MemSize = TII -> getMemScale ( * Paired ) ; if ( PairedIsUnscaled ) { assert ( ! ( PairedOffset % TII -> getMemScale ( * Paired ) ) && <STR_LIT> ) ; PairedOffset /= MemSize ; } else { PairedOffset *= MemSize ; } } MachineInstr * RtMI , * Rt2MI ; if ( Offset == PairedOffset + OffsetStride && ! <ISA_LIT>InstrInfo :: isPreLdSt ( * I ) ) { RtMI = & * Paired ; Rt2MI = & * I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = & *


<s> if ( ! CS . paramHasAttr ( <NUM_LIT> , Attribute :: StructRet ) ) return <NUM_LIT> ; if ( CS . paramHasAttr ( <NUM_LIT> , Attribute :: InReg ) )


<s> StoreSDNode & Nd = * cast < StoreSDNode > ( Op ) ; if ( Nd . getMemoryVT ( ) != <STR_LIT> || ! NoDPLoadStore ) return <ISA_LIT>TargetLowering :: lowerSTORE ( Op , DAG ) ; SDLoc DL ( Op ) ; SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; Chain = DAG . getStore ( Chain , DL , Lo , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( )

, Nd . getAlignment ( ) , Nd . getAAInfo ( ) ) ;


<s> if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = LoadMI -> memoperands_begin ( ) -> getAlignment ( ) ; else if ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) Alignment = <NUM_LIT> ; if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; SmallVector < MachineOperand , <ISA_LIT>AddrNumOperands > MOs ; if ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( )


<s> target_flags &= ~ MASK_INTERWORK ; } if ( TARGET_SOFT_FLOAT ) arm_fpu_attr = FPU_NONE ; else arm_fpu_attr = FPU_VFP ; if ( TARGET_AAPCS_BASED ) { if ( TARGET_CALLER_INTERWORKING ) error ( <STR_LIT> ) ; else if ( TARGET_CALLEE_INTERWORKING ) error ( <STR_LIT> ) ; } if ( ! arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE ) sorry ( <STR_LIT> ) ; if ( use_cmse && ! arm_arch_cmse ) error ( <STR_LIT> ) ; if ( use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM ) error ( <STR_LIT> ) ; if ( TARGET_AAPCS_BASED ) { if ( arm_abi == ARM_ABI_IWMMXT ) arm_pcs_default = ARM_PCS_AAPCS_IWMMXT ; else if (


<s> unsigned Opcode ; int64_t ThisVal = NumBytes ; if ( isInt < <NUM_LIT> > ( NumBytes ) ) Opcode = <STR_LIT> ; else { Opcode = <STR_LIT> ; int64_t MinVal = - int64_t ( <NUM_LIT> ) << <NUM_LIT> ; int64_t MaxVal = ( int64_t ( <NUM_LIT> ) << <NUM_LIT> ) - <NUM_LIT> ; if ( ThisVal < MinVal ) ThisVal = MinVal ; else if ( ThisVal > MaxVal ) ThisVal = MaxVal ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) , Reg ) . addReg ( Reg ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead


<s> const std :: vector < MachineConstantPoolEntry > & Constants = CP -> getConstants ( ) ; for ( unsigned i = <NUM_LIT> , e = Constants . size ( ) ; i != e ; ++ i ) { if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && Constants [ i ] . getAlign ( )


<s> imported [ ( int ) code ] = <NUM_LIT> ; strcpy ( str , import_string ) ; memcpy ( str + MILLI_START , milli_names [ ( int ) code ] ,


<s> assert ( Imm > <NUM_LIT> && Imm <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT>


<s> if ( BYTES_BIG_ENDIAN ) return false ; for ( i = <NUM_LIT> ; i < nelt ; next ++ , i ++ ) { if ( next == <NUM_LIT> * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == <NUM_LIT> ) && ( d -> vmode != V2DImode ) ) return false ; else next = <NUM_LIT> ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT> ]


<s> const MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( Dest ) . addOperand ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( )


<s> case FK_Data_4 : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32NB : COFF :: IMAGE_REL_I386_DIR32NB ; return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32 : COFF :: IMAGE_REL_I386_DIR32 ; case FK_Data_8 : if ( Is64Bit ) return COFF :: IMAGE_REL_AMD64_ADDR64 ; llvm_unreachable (


<s> Value * <ISA_LIT>IREmitter :: visitLCMPXCHG_DAG ( const SDNode *


<s> int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_int_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , <NUM_LIT> , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += <NUM_LIT> ; mode = word_mode ; regno +=


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( Desc . TSFlags & <STR_LIT> ) return false ; static std :: atomic < bool > TableChecked ( false ) ; if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex128CompressTable ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI ) ) return false ; if ( ! CheckVEXInstPredicate ( MI , ST ) ) return false ; if ( ! performCustomAdjustments ( MI , NewOpc , ST ) ) return false ; MI . setDesc ( TII -> get ( NewOpc ) ) ; MI . setAsmPrinterFlag


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , FIOperandNum , this , MF


<s> bool isNameEqual ( std :: string Other , uint64_t FeatureBits =


<s> case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT>


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrModeISOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! isN64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , GA ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , isN32 ( ) || isN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) ,


<s> auto * CINT = dyn_cast < ConstantSDNode > ( Opnd0 ) ; auto * CFP = dyn_cast < ConstantFPSDNode > ( Opnd0 ) ; return ( CINT && CINT -> isNullValue ( ) ) || ( CFP && CFP


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF .


<s> EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> ,


<s> case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasAltivec ( ) ? <NUM_LIT> : <NUM_LIT> ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( <NUM_LIT> ) ; } llvm_unreachable (


<s> TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( RegNo )


<s> extern __inline __m256d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_i64gather_pd ( double const * base , __m256i index , const int scale ) { __v4df src = _mm256_setzero_pd ( ) ; __v4df mask = _mm256_cmp_pd ( src , src , _CMP_EQ_OQ ) ; return ( __m256d ) __builtin_ia32_gatherdiv4df ( src , base , ( __v4di ) index , mask


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT ) const { bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; if ( ( is<ISA_LIT>64 && VT != <STR_LIT> && VT != <STR_LIT> ) || ( ! is<ISA_LIT>64 && VT != <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; bool is64Bit = is<ISA_LIT>64 && VT == <STR_LIT> ; unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , is64Bit ? <STR_LIT> : <STR_LIT> ) . Case ( <STR_LIT> , isDarwinABI ? <NUM_LIT> : ( is64Bit ? <STR_LIT> : <STR_LIT> ) ) . Case ( <STR_LIT> , ( ! is<ISA_LIT>64 && isDarwinABI ) ? <NUM_LIT> : ( is64Bit ? <STR_LIT> : <STR_LIT> ) ) . Default


<s> if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( NumElts != <NUM_LIT> || l == <NUM_LIT> ) continue ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Mask [ i + l ] , Mask [ i ] + l )


<s> return pa_output_millicode_call ( insn , gen_rtx_SYMBOL_REF


<s> PrintDebugValueComment ( MI , OS ) ; OutStreamer -> EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; } case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { const MachineOperand & MO_Sym = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand MO_TLSDESC_LO12 ( MO_Sym ) , MO_TLSDESC ( MO_Sym ) ; MCOperand Sym , SymTLSDescLo12 , SymTLSDesc ; MO_TLSDESC_LO12 . setTargetFlags ( <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; MO_TLSDESC . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; MCInstLowering . lowerOperand ( MO_Sym , Sym ) ; MCInstLowering . lowerOperand ( MO_TLSDESC_LO12 , SymTLSDescLo12 ) ; MCInstLowering . lowerOperand ( MO_TLSDESC , SymTLSDesc ) ; MCInst Adrp ; Adrp . setOpcode ( <STR_LIT> ) ; Adrp . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Adrp . addOperand ( SymTLSDesc ) ; EmitToStreamer ( * OutStreamer , Adrp ) ; MCInst Ldr ; Ldr . setOpcode ( <STR_LIT> ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( SymTLSDescLo12 ) ; Ldr . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitToStreamer ( * OutStreamer ,


<s> void setPICBasePointerSaveIndex ( int


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget . hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Val )


<s> return ( __m64 ) __builtin_ia32_psllw ( ( __v4hi ) __m ,


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) if ( auto * Mask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( Mask -> getZExtValue ( ) == <NUM_LIT> && ! isShuffleFoldableLoad ( V0 ) ) { SDValue NewMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V0


<s> unsigned TlsReg , TlsOffset ; DebugLoc DL ; unsigned ScratchReg = GetScratchRegister ( Is64Bit , IsLP64 , MF , true ) ; assert ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg ) && <STR_LIT> ) ; if ( MF . getFunction ( ) -> isVarArg ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! STI . isTargetLinux ( ) && ! STI . isTargetDarwin ( ) && ! STI . isTargetWin32 ( ) && ! STI . isTargetWin64 ( ) && ! STI . isTargetFreeBSD ( ) && ! STI . isTargetDragonFly ( ) ) report_fatal_error ( <STR_LIT> ) ; StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> ) return ; MachineBasicBlock * allocMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * checkMBB = MF . CreateMachineBasicBlock ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsNested = false ; if ( Is64Bit ) IsNested = HasNestArgument ( & MF ) ; for ( MachineBasicBlock :: livein_iterator i = PrologueMBB . livein_begin ( ) , e = PrologueMBB . livein_end ( ) ; i != e ; i ++ ) { allocMBB -> addLiveIn ( * i ) ; checkMBB -> addLiveIn ( * i ) ; } if ( IsNested ) allocMBB -> addLiveIn ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ; MF . push_front ( allocMBB ) ; MF . push_front ( checkMBB ) ; bool CompareStackPointer = StackSize < kSplitStackAvailable ; if ( Is64Bit ) { if ( STI . isTargetLinux ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = IsLP64 ? <NUM_LIT> : <NUM_LIT> ; } else if ( STI . isTargetDarwin ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; } else if ( STI . isTargetWin64 ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetFreeBSD ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetDragonFly ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else { report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = IsLP64 ? <STR_LIT> : <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; BuildMI ( checkMBB , DL , TII . get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg (

<NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ; return SDValue (


<s> if ( needAlign ( Inst ) || ( ( AlignBranchType & <STR_LIT> ) && isFirstMacroFusibleInst ( Inst , * MCII ) ) ) { OS . insert ( PendingBA = new MCBoundaryAlignFragment


<s> const DebugLoc & DL = RetI . getDebugLoc ( ) ; MachineBasicBlock * ClearBB , * DoneBB ; if ( STI -> hasMinSize ( ) ) { ClearBB = DoneBB = & MBB ; } else { MachineFunction * MF = MBB . getParent ( ) ; ClearBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , ClearBB ) ; MF -> insert ( ++ ClearBB -> getIterator ( ) , DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( ClearBB ) ; MBB . addSuccessor ( DoneBB ) ; ClearBB -> addSuccessor ( DoneBB ) ; for ( const MachineOperand & Op : RetI . operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; assert ( Register :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; ClearBB -> addLiveIn ( Reg ) ; DoneBB -> addLiveIn ( Reg ) ; } ClearBB -> addLiveIn ( <STR_LIT> ) ; DoneBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } for ( unsigned D = <NUM_LIT> ; D < <NUM_LIT> ; D ++ ) { if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] && ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] ) { unsigned Reg = <STR_LIT> + D ; BuildMI ( ClearBB , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] ) { unsigned Reg = <STR_LIT> + D * <NUM_LIT> ; BuildMI ( ClearBB , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ]


<s> MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This1Reg ) . addReg ( Start1Reg ) . addMBB ( StartMBB ) . addReg ( End1Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This2Reg ) . addReg ( Start2Reg ) . addMBB ( StartMBB ) . addReg ( End2Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( CharReg ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( End1Reg , RegState :: Define ) . addReg ( End2Reg , RegState :: Define ) . addReg ( This1Reg ) . addReg ( This2Reg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor (


<s> regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; if ( ! TARGET_BONNELL && parts . scale == <NUM_LIT> && ( ! parts . disp || parts . disp == const0_rtx ) && ( regno0 == regno1 || regno0 == regno2 ) ) return true ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; split_cost = <NUM_LIT> ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += <NUM_LIT> ; if ( parts . base && parts . index ) split_cost += <NUM_LIT> ; if ( parts . scale > <NUM_LIT> ) { if ( regno0 != regno1 ) split_cost += <NUM_LIT> ; else if ( regno2 == regno0 ) split_cost += <NUM_LIT> ; else split_cost += parts .


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm


<s> auto MSRMapper = <STR_LIT> ( STI . getFeatureBits ( ) ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; uint32_t PStateField = <STR_LIT> ( ) . fromString ( Tok . getString ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateField , getContext ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> static Value * simplify<ISA_LIT>movmsk ( const IntrinsicInst & II , InstCombiner :: BuilderTy & Builder ) { Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Type * ResTy = II . getType ( ) ; if ( isa < UndefValue > ( Arg ) ) return Constant :: getNullValue ( ResTy ) ; auto * ArgTy = dyn_cast < FixedVectorType > ( Arg -> getType ( ) ) ; if ( ! ArgTy ) return nullptr ; unsigned NumElts = ArgTy -> getNumElements ( ) ; Type * IntegerVecTy = VectorType :: getInteger ( ArgTy ) ; Type * IntegerTy = Builder . getIntNTy ( NumElts ) ; Value * Res = Builder . CreateBitCast ( Arg , IntegerVecTy ) ; Res = Builder . CreateICmpSLT ( Res , Constant :: getNullValue ( IntegerVecTy ) ) ; Res = Builder . CreateBitCast ( Res , IntegerTy ) ; Res = Builder . CreateZExtOrTrunc ( Res , ResTy ) ; return Res


<s> const LDSymbol * getGpDispSymbol ( ) const { return


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; MaxInstLength = MinInstAlignment = <NUM_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation =


<s> r = sr -> curr . reg + decode_abreg ( abreg , <NUM_LIT> ) ; r -> where = where ; r -> when = sr -> region_start + MIN ( ( int ) t , sr -> region_len -


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex


<s> if ( const <ISA_LIT>InstrRelaxTableEntry * I = lookupRelaxTable ( ShortOp ) ) return I -> DstOp ; return ShortOp


<s> if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , DebugLoc dl , SelectionDAG & DAG ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable (


<s> if ( ! getParamsForOneTrueMaskedElt ( ML , DAG , Addr , VecIndex , Alignment ) ) return SDValue ( ) ; SDLoc DL ( ML ) ; EVT VT = ML -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VT . getVectorElementType ( ) ; SDValue Load = DAG . getLoad ( EltVT , DL , ML -> getChain ( ) , Addr , ML

-> getPointerInfo ( ) , Alignment , ML -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> case TYPE_LOAD_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - <NUM_LIT> ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_SRC ( parallel_element ( insn , <NUM_LIT> ) ) ; break ; case TYPE_STORE_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - <NUM_LIT> ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_DEST ( parallel_element ( insn


<s> if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) , Op ) ; return Op


<s> MCInstLowering . lowerOperand ( MO_Sym , Sym ) ; MCInstLowering . lowerOperand ( MO_TLSDESC_LO12 , SymTLSDescLo12 ) ; MCInstLowering . lowerOperand ( MO_TLSDESC , SymTLSDesc ) ; MCInst Adrp ; Adrp . setOpcode ( <STR_LIT> ) ; Adrp . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Adrp . addOperand ( SymTLSDesc ) ; EmitToStreamer ( * OutStreamer , Adrp ) ; MCInst Ldr ; Ldr . setOpcode ( <STR_LIT> ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( SymTLSDescLo12 ) ; Ldr . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitToStreamer ( * OutStreamer , Ldr ) ; MCInst Add ; Add . setOpcode ( <STR_LIT> ) ; Add . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Add . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Add . addOperand ( SymTLSDescLo12 ) ; Add . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <NUM_LIT> ) ) ) ; EmitToStreamer ( * OutStreamer , Add ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( <STR_LIT> ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( * OutStreamer , TLSDescCall ) ; MCInst Blr ; Blr . setOpcode ( <STR_LIT> ) ; Blr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , Blr ) ; return ; } case <STR_LIT> : case <STR_LIT> : EmitFMov0 ( * MI ) ; return ; case TargetOpcode


<s> return Error ( Loc , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT>


<s> bool <ISA_LIT>AsmBackend :: canPadBranches ( MCObjectStreamer & OS ) const { if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; if ( ! OS . getCurrentSectionOnly ( ) -> getKind ( ) . isText ( ) ) return false ; if ( OS . getAssembler ( ) . isBundlingEnabled ( ) ) return false ; if ( ! ( STI . hasFeature ( <STR_LIT> ) || STI . hasFeature ( <STR_LIT> )


<s> const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , ST . use<ISA_LIT>PreRASchedStrategy ( ) ? std :: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) : std :: make_unique < GenericScheduler > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasStoreFusion ( ) ) DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasFusion ( ) ) DAG ->

addMutation ( createPowerPCMacroFusionDAGMutation ( ) ) ;


<s> switch ( CC ) { default : break ; case <STR_LIT> : { Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ; SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , AD , Op , AD . getValue ( <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , T , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { T , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) , Op .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable (


<s> return ( __m256i ) __builtin_ia32_extracti64x4_mask ( ( __v8di ) __A , __imm , (


<s> unsigned getReg ( ) const override { assert ( Kind == k_Register && <STR_LIT> ) ; return Reg .


<s> unsigned Opc = CCVal . getOpcode ( ) ; if ( CCVal . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( CCVal -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> OFCC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( OFCC , CCVal . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( OFCC , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TVal , FVal , CCVal ,


<s> SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , dl , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( OpNo ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Load ) , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( Op . getNode ( ) -> isStrictFPOpcode ( ) ) { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , Or , Bias } ) ; if ( Op . getValueType ( ) == Sub . getValueType ( ) ) return Sub ; std :: pair < SDValue , SDValue > ResultPair = DAG . getStrictFPExtendOrRound ( Sub , Sub . getValue (

<NUM_LIT> ) , dl , Op . getSimpleValueType ( ) ) ;


<s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } default : return MI . getDesc ( ) .


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( TM . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; return


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg (


<s> default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgArea ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . isExtInLoc ( ) ) Offset += <NUM_LIT> - ValSize ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( ) ) , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } if ( ! IsVarArg ) return Chain ; unsigned ArgOffset = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgArea + Subtarget -> getStackPointerBias ( ) ) ; SmallVector < SDValue , <NUM_LIT> > OutChains ; for ( ; ArgOffset < <NUM_LIT> * <NUM_LIT> ; ArgOffset += <NUM_LIT> ) { unsigned VReg = MF . addLiveIn ( <STR_LIT> + ArgOffset / <NUM_LIT> , & <STR_LIT> ) ; SDValue VArg = DAG . getCopyFromReg ( Chain ,


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Op0 = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( ! MI -> killsRegister ( <STR_LIT> + Op0 ) ) { duplicateToTop ( Op0 , getScratchReg ( ) , I ) ; } else { moveToTop ( Op0 , I ) ; } -- StackTop ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Op0 = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; ++ StackTop ; unsigned RegOnTop = getStackEntry ( <NUM_LIT> ) ; if ( ! MI -> killsRegister ( <STR_LIT> + Op0 ) ) { duplicateToTop ( Op0 , getScratchReg ( ) , I ) ; moveToTop ( RegOnTop , I ) ; } else if ( getSTReg ( Op0 ) != <STR_LIT> ) { moveToTop ( getStackEntry ( <NUM_LIT> ) , I ) ; moveToTop ( Op0 , I ) ; moveToTop ( RegOnTop , I ) ; } assert ( StackTop >= <NUM_LIT> && <STR_LIT> ) ; StackTop -= <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; unsigned SrcReg = getFPReg ( MO1 ) ; const MachineOperand & MO0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned DestReg = getFPReg ( MO0 ) ; if ( MI -> killsRegister ( <STR_LIT> + SrcReg ) ) { unsigned Slot = getSlot ( SrcReg ) ; assert ( Slot < <NUM_LIT> && DestReg < <NUM_LIT> && <STR_LIT> ) ; Stack [ Slot ] = DestReg ; RegMap [ DestReg ] = Slot ; } else { duplicateToTop ( SrcReg , DestReg , I ) ; } } break ; case TargetOpcode :: INLINEASM : { unsigned Kills = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && <STR_LIT> ) ; unsigned FPReg = getFPReg ( Op ) ; Op . setReg ( getSTReg ( FPReg ) ) ; if ( Op . isKill ( ) ) Kills |= <NUM_LIT> << FPReg ; } MachineBasicBlock :: iterator InsertPt = MI ; while ( Kills ) { unsigned FPReg = CountTrailingZeros_32 ( Kills ) ; freeStackSlotAfter ( InsertPt , FPReg ) ; Kills &= ~ ( <NUM_LIT> << FPReg ) ; } return ; } case <STR_LIT> : case <STR_LIT> : unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; unsigned LiveMask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( )


<s> if ( MI . isMoveReg ( ) ) { Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI . getOperand ( <NUM_LIT> ) ; return


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; unsigned Imm8 = getT1Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Opcode == <STR_LIT> ? SignExtend32 < <NUM_LIT> > ( Imm8 << <NUM_LIT> ) + <NUM_LIT> : ( int ) Imm8 ) ) ; NumOpsAdded = <NUM_LIT> ; return true


<s> Parser . Lex ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( true , isABI_O32 ( ) ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32


<s> if ( Subtarget -> isThumb2 ( ) || ( Subtarget -> hasV8MBaselineOps ( ) && Subtarget -> isThumb ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Table ,


<s> if ( ! enableVPU ( ) ) return true ; return ! isSupportedReduction ( II -> getIntrinsicID


<s> int64_t Amount = VRegAndVal -> Value . getSExtValue ( ) ; if ( Amount > <NUM_LIT> ) return true ; auto ExtCst = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , Amount ) ; Observer . changingInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ExtCst . getReg ( <NUM_LIT> ) ) ; Observer . changedInstr ( MI ) ; return


<s> const DataLayout & DL = MF . getDataLayout ( ) ; return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine


<s> inline vector signed short vec_vsubshs ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vsubshs ( ( vector signed short ) a1 ,


<s> IsLittleEndian = ( TheTriple . getArch ( ) == Triple :: sparcel ) ; if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> : nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI


<s> assert ( Reg < <NUM_LIT> && <STR_LIT> ) ; if ( StackTop >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; Stack [ StackTop ] = Reg ; RegMap [ Reg ] = StackTop


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm


<s> FOR_EACH_BB_FN ( bb , cfun ) { insn = BB_END ( bb ) ; while ( insn != BB_HEAD ( bb ) && NOTE_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( ( control_flow_insn_p ( insn ) && GET_CODE ( PATTERN ( insn ) ) == RETURN ) || ( CALL_P ( insn ) && ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ) ) { rtx_insn * seq = aarch64_speculation_clobber_sp ( ) ; emit_insn_before ( seq , insn ) ; fixups_pending --


<s> bool <ISA_LIT>TargetLowering :: useStackGuardXorFP (


<s> tmpInst . addOperand ( MCOperand :: createImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode (


<s> bool UseOffset = true ; const TargetRegisterClass * RC = MRI . getRegClass ( SrcReg ) ; bool Is32BitInt = RC -> hasSuperClassEq ( & <STR_LIT> ) ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = Is32BitInt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = Is32BitInt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( Is32BitInt && <STR_LIT> ) ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; bool IsVSFRC = isVSFRCRegister ( SrcReg ) ; if ( IsVSFRC && ( Opc == <STR_LIT> ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc =


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand ::


<s> case CONST_VECTOR : { * special = SH_CONST_VECTOR ; return <NUM_LIT> ; } case VEC_DUPLICATE : if ( CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( op ) ) == GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == TRUNCATE && REG_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( op ) ) == GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_SELECT ) return rtx_is_swappable_p ( XEXP ( op , <NUM_LIT> ) , special ) ; else return <NUM_LIT> ; case VEC_SELECT : if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) == GET_MODE ( op ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ) { * special = SH_EXTRACT ; return <NUM_LIT> ; } else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_CONCAT && ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DFmode || GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DImode ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ) { * special = SH_XXPERMDI ; return <NUM_LIT> ; } else if ( v2df_reduction_p ( op ) ) return <NUM_LIT> ; else return <NUM_LIT> ; case UNSPEC : { int val = XINT ( op , <NUM_LIT> ) ; switch ( val ) { default : break ; case UNSPEC_VBPERMQ


<s> case <NUM_LIT> : return V8BImode ; case <NUM_LIT> : return V4BImode ; case <NUM_LIT> :


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmian ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhsmi ( a , b


<s> static bool expandNOVLXLoad ( MachineInstrBuilder & MIB , const TargetRegisterInfo * TRI , const MCInstrDesc & LoadDesc , const MCInstrDesc & BroadcastDesc , unsigned SubIdx ) { Register DestReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TRI -> getEncodingValue ( DestReg ) < <NUM_LIT> ) { MIB -> setDesc ( LoadDesc ) ; } else { MIB -> setDesc ( BroadcastDesc


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) ->


<s> unsigned Opc = MBBI -> getOpcode ( ) ; if ( MBBI -> readsRegister ( Base ) ) { int Offset ; bool IsLoad = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = getLoadStoreRegOp ( * MBBI ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( * MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( * MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch ( ) ) { InsertSub = true ; } if ( InsertSub ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) . add ( t1CondCodeOp ( true ) ) . addReg ( Base ) . addImm ( WordOffset * <NUM_LIT> ) . addImm (


<s> } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( Desc . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { assert ( false


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , LHS , RHS } ; SDValue Lo = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , dl , VTs


<s> return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( V2 -> getOpcode ( ) == <STR_LIT> && isSingletonVEXTMask ( ShuffleMask , VT , Imm ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V1 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } unsigned WhichResult ; if ( isVTRNMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVUZPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVTRN_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; if ( isVUZP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; if ( isVZIP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [


<s> SDValue <ISA_LIT>TargetLowering :: LowerADJUST_TRAMPOLINE ( SDValue Op , SelectionDAG & DAG )


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( Imm == <NUM_LIT> )


<s> if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> if ( Flags . isSExt ( ) ) return CCValAssign :: LocInfo :: SExt ; if ( Flags . isZExt ( ) ) return CCValAssign :: LocInfo :: ZExt ; return CCValAssign :: LocInfo ::


<s> case SIMD_ARG_COPY_TO_REG : if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) ) op [ opc ] = convert_memory_address ( Pmode , op [ opc ] ) ; if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) op [ opc ] = copy_to_mode_reg ( mode , op [ opc ] ) ; break ; case SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX : gcc_assert ( opc > <NUM_LIT> ) ; if ( CONST_INT_P ( op [ opc ] ) ) { aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , GET_MODE_NUNITS ( builtin_mode ) , exp ) ; op [ opc ] = GEN_INT ( ENDIAN_LANE_N ( builtin_mode , INTVAL ( op [ opc ] ) ) ) ; } goto constant_arg ; case SIMD_ARG_LANE_INDEX : gcc_assert ( opc > <NUM_LIT> ) ; if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , GET_MODE_NUNITS ( vmode ) , exp ) ; op [ opc ] = GEN_INT ( ENDIAN_LANE_N ( vmode , INTVAL ( op [ opc ] ) ) ) ; } case SIMD_ARG_CONSTANT : constant_arg : if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) { error ( <STR_LIT> , exp , opc + <NUM_LIT> - have_retval ) ; return const0_rtx ; } break ; case SIMD_ARG_STOP : gcc_unreachable ( ) ; } opc ++ ; } } switch ( opc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case


<s> IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( CN -> getType (


<s> void RelaxInstruction ( const MCInst & Inst ,


<s> return ( __m256i ) __builtin_ia32_loaddquqi256_mask ( ( __v32qi * ) __P , ( __v32qi ) __W ,


<s> static DecodeStatus DecodeGPROutRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeCPURegsRegisterClass ( Inst , RegNo


<s> for ( MachineInstr & I : * MBB ) { BBI . Size += TII -> GetInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign


<s> Inst . addOperand ( MCOperand :: CreateImm ( getPrefetch


<s> TargetPassConfig :: addIRPasses ( ) ; addPass ( create<ISA_LIT>StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( )

== CodeGenOpt :: Aggressive && EnableGEPOpt ) {


<s> bool aarch64_is_extend_from_extract ( machine_mode mode , rtx mult_imm , rtx extract_imm ) { HOST_WIDE_INT mult_val , extract_val ; if ( ! CONST_INT_P ( mult_imm ) || ! CONST_INT_P ( extract_imm ) ) return false ; mult_val = INTVAL ( mult_imm ) ; extract_val = INTVAL (


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qidi


<s> if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass


<s> const <ISA_LIT>Subtarget * getSubtarget


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; Register Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorElementCount ( ) . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags


<s> machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) (


<s> static bool isUnalignedLoadStore ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ||

Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static machine_mode rs6000_translate_mode_attribute ( machine_mode mode ) { if ( ( FLOAT128_IEEE_P ( mode ) && ieee128_float_type_node == long_double_type_node ) || ( FLOAT128_IBM_P ( mode ) && ibm128_float_type_node == long_double_type_node ) ) return COMPLEX_MODE_P ( mode ) ? E_TCmode : E_TFmode ; return


<s> static DecodeStatus DecodeBranchImmInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; return


<s> MF . getFrameInfo ( ) . computeMaxCallFrameSize ( MF ) ; TargetLoweringBase :: finalizeLowering ( MF


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT>


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( ! Invert ) CCMask = CCMask ^ <STR_LIT> ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; if ( ! convertPrevCompareToBranch ( MBB , MI , CCMask , JoinMBB ) ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ; MBB -> addSuccessor ( JoinMBB


<s> EndLoc = Parser . getTok ( ) . getLoc ( ) ; return ( RegNo == ( unsigned )


<s> MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , getContext ( ) ) ; Expr = <ISA_LIT>MCExpr :: Create ( Expr , <ISA_LIT>MCExpr :: VK_TLSDESC , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT>


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op . getValueType ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; EVT VT = <STR_LIT> ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT>


<s> MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Asm , Fixup , Target , Value , IsPCRel , Ctx , IsLittleEndian , true ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) { FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; assert ( ( Offset + FullSizeBytes ) <= Data .


<s> MachineInstr * setRegister ( MachineInstr & I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF ->


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) == p . getReg ( ) ) { if ( MO . isDef ( ) ) return RU_Write ; RegUsage =


<s> BaseTAI ( TM ) { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; BaseTAI :: AsmTransCBE =


<s> llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT>


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ; if ( UnpckNode ) return


<s> return ( __m128i ) __builtin_ia32_vaesenclast_v16qi ( ( __v16qi ) __A , ( __v16qi )


<s> if ( ! isTypeSupported ( I -> getType ( ) , RetVT ) ) return false ; if ( ! isTypeSupported ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , SrcVT ) ) return false ; if ( optimizeIntExtLoad ( I , RetVT , SrcVT ) ) return true ; unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! SrcReg ) return false ; bool IsZExt = isa < ZExtInst > ( I ) ; if ( const auto * Arg = dyn_cast < Argument > ( I -> getOperand ( <NUM_LIT> ) ) ) { if ( ( IsZExt && Arg -> hasZExtAttr ( ) ) || ( ! IsZExt && Arg -> hasSExtAttr ( ) ) ) { if ( RetVT == <STR_LIT> && SrcVT != <STR_LIT> ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) .

addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ;


<s> cfun -> machine -> doloop_tag_from_end = is_end ; } tag = GEN_INT ( cfun -> machine -> doloop_tags - <NUM_LIT> ) ; machine_mode opmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; gcc_assert ( opmode == HImode ||


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rn |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned op = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned length = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } for ( unsigned i = <NUM_LIT> ; i < length ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rn + i ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const { if ( ! CallLoweringInfo ) CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( TLInfo ) ) ; return CallLoweringInfo .


<s> x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) , x ) ; x = gen_rtx_SET ( VOIDmode , const0_rtx ,


<s> emit_insn ( gen_rtx_SET ( dest , GEN_INT ( val & <NUM_LIT> ) ) ) ; if ( mode == SImode ) emit_insn ( gen_insv_immsi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; else emit_insn ( gen_insv_immdi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } mask = <NUM_LIT> ; zero_match = ( ( val & mask ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; one_match = ( ( ~ val & mask ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + (

( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW


<s> for ( int i = Pos , e = Pos + Size ; i != e ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , Low ,


<s> assert ( LHSReg && RHSReg && <STR_LIT> ) ; if ( LHSReg == <STR_LIT> || LHSReg == <STR_LIT> || RHSReg == <STR_LIT> || RHSReg == <STR_LIT> ) return <NUM_LIT> ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg


<s> static bool mep_disinterrupt_p ( void ) { if ( cfun -> machine -> disable_interrupts == <NUM_LIT> ) { int disable_interrupts = ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) )


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; if ( ! IgnoreSPUpdates && ! hasReservedCallFrame ( MF ) ) return getFrameIndexReference (


<s> if ( RegNo >= <NUM_LIT> || ( ! hasHighReg && RegNo >= <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( GPRPairDecoderTable [ RegNo ] ) ) ; return MCDisassembler :: Success


<s> if ( Subtarget . hasAVX2 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; if ( Subtarget . hasBWI ( ) &&


<s> assert ( TBB && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else instantiateCondBranch ( MBB , DL , TBB , Cond ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } instantiateCondBranch ( MBB , DL , TBB , Cond ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> )


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; if ( offset < <NUM_LIT> ) { Val = <NUM_LIT>


<s> int64_t <ISA_LIT>GNULDBackend :: maxFwdBranchOffset ( ) const { if ( m_pAttrData -> usingThumb2 ( ) ) { return THM2_MAX_FWD_BRANCH_OFFSET ; } else { return THM_MAX_FWD_BRANCH_OFFSET


<s> static SDValue LowerREADCYCLECOUNTER ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SmallVector < SDValue , <NUM_LIT> > Results ; SDLoc DL (


<s> Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc


<s> return __builtin_mve_vcaddq_rot90_m_sv4si ( __arm_vuninitializedq_s32 ( ) ,


<s> SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , NULL , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , NULL , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT>

, <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;