<s> else { if ( partial_subreg_p ( int_mode , SImode ) ) { gcc_assert ( base == const0_rtx ) ; dest = gen_lowpart ( SImode , dest ) ; int_mode = SImode ; } if ( base != const0_rtx ) { base = aarch64_force_temporary ( int_mode , dest , base ) ; aarch64_add_offset ( int_mode , dest , base , offset , NULL_RTX , NULL_RTX , false ) ; } else aarch64_add_offset ( int_mode , dest , base , offset , dest , NULL_RTX , false ) ; } return ; } sty = aarch64_classify_symbol ( base , const_offset ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( const_offset != <NUM_LIT> && targetm . cannot_force_const_mem ( int_mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( int_mode , dest , base ) ; aarch64_add_offset ( int_mode , dest , base , const_offset , NULL_RTX , NULL_RTX , false ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( ! aarch64_pcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , <NUM_LIT> ) ) ; if ( ptr_mode != Pmode ) base = convert_memory_address ( Pmode , base ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( int_mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( int_mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( const_offset != <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( int_mode , dest , base


<s> shmask . c [ si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , (

vec_uint4 ) ( b ) ) ) ) & <NUM_LIT> ] = <NUM_LIT> ;


<s> CM = CodeModel :: Small ; } if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) { report_fatal_error ( <STR_LIT> ) ; } X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine (


<s> assert ( Bit < <NUM_LIT> && <STR_LIT> ) ; bool UseWReg = Bit < <NUM_LIT> ; unsigned NecessarySize = UseWReg ? <NUM_LIT> : <NUM_LIT> ; if ( Size != NecessarySize ) TestReg = moveScalarRegClass ( TestReg , UseWReg ? <STR_LIT> : <STR_LIT> , MIB ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ UseWReg ] [ IsNegative ] ; auto TestBitMI = MIB . buildInstr ( Opc ) . addReg ( TestReg ) . addImm ( Bit ) . addMBB ( DstMBB ) ; constrainSelectedInstRegOperands ( * TestBitMI , TII , TRI


<s> I != E ; ++ I ) printModuleLevelGV ( I ) ; O << <STR_LIT> ; for ( std :: set < std :: string > :: iterator i = ExternalFunctionNames . begin ( ) , e = ExternalFunctionNames . end ( ) ; i != e ; ++ i ) { O << <STR_LIT> << * i << <STR_LIT> << * i << <STR_LIT> ; } O << <STR_LIT> ; O << <STR_LIT> ; for ( std :: set < std :: string > :: iterator i = ExternalObjectNames . begin ( ) , e = ExternalObjectNames . end ( ) ; i != e ; ++ i ) { O << <STR_LIT> << * i <<


<s> SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand (


<s> case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Op1 ) . addReg ( Op2 ) ) ; updateValueMap ( I ,


<s> if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI ,


, ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> SMLoc Start , End ; if ( isParsingInlineAsm ( ) ) { StringRef AsmTokStr = Tok . getString ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOffsetOfOperator ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_LENGTH ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return <NUM_LIT> ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> (


<s> assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , UseRt ? getT1tRt ( insn ) : getT1tRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx == NumOps ) return true ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRm ( insn ) ) ) ) ; } else { assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( UseRt ? getT1Imm8 ( insn ) : ( Imm3 ? getT1Imm3 ( insn ) : getT1Imm5 (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result )


<s> if ( isP7 && ! BYTES_BIG_ENDIAN ) return false ; if ( ! CONST_INT_P ( bytes_rtx ) ) return expand_compare_loop ( operands ) ; if ( ! CONST_INT_P ( align_rtx ) ) return false ; unsigned int base_align = UINTVAL ( align_rtx ) / BITS_PER_UNIT ; gcc_assert ( GET_MODE ( target ) == SImode ) ; unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; if ( bytes == <NUM_LIT> ) return true ; rtx cond = NULL ; if ( TARGET_P9_MISC ) cond = gen_reg_rtx ( CCUNSmode ) ; int use_vec = ( bytes >= <NUM_LIT> && ! TARGET_32BIT && TARGET_EFFICIENT_UNALIGNED_VSX && TARGET_P8_VECTOR ) ; unsigned HOST_WIDE_INT max_bytes = rs6000_block_compare_inline_limit ; if ( ! use_vec && max_bytes > <NUM_LIT> ) max_bytes = ( ( max_bytes + <NUM_LIT> ) / <NUM_LIT> ) - <NUM_LIT> ; if ( ! IN_RANGE ( bytes , <NUM_LIT> , max_bytes ) ) return expand_compare_loop ( operands ) ; if ( ! TARGET_EFFICIENT_OVERLAPPING_UNALIGNED && ( ( base_align == <NUM_LIT> && bytes > <NUM_LIT> ) || ( base_align == <NUM_LIT> && bytes > <NUM_LIT> ) ) ) return false ; rtx final_label = NULL


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> bool Changed = false ; const <ISA_LIT>InstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; bool InsertNop = false ; if ( std :: next ( I ) != FI -> end ( ) && ! TII -> SafeInForbiddenSlot ( * getNextMachineInstr ( std :: next ( I ) ) ) ) { InsertNop = true ; } else { for ( auto * Succ : FI -> successors (


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LO , HI ; SDValue Chain = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue rd = DAG . getNode ( <STR_LIT> , DL , Tys , Chain ) ; if ( Subtarget . is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue


<s> bool <ISA_LIT>TargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; return


<s> vmlaq_u16 ( uint16x8_t a , uint16x8_t b , uint16x8_t c ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> int offset = info . total_size ; int stack_offset = info . total_size ; if ( ! info . save_fp && ! info . save_lr && ! reg_mask ) return ; if ( CONST_OK_FOR_LETTER_P ( offset , 'O' ) ) base_reg = stack_pointer_rtx ; else { base_reg = gen_rtx_REG ( SImode , GPR_R9 ) ; offset = <NUM_LIT> ; } if ( info . save_fp ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_FP ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) )


<s> if ( ! isCalleeSavedRegister ( MI -> getOperand ( RtIdx ) . getReg ( ) , CSRegs ) || ! isCalleeSavedRegister ( MI -> getOperand ( RtIdx +

<NUM_LIT> ) . getReg ( ) , CSRegs ) || MI -> getOperand ( RtIdx + <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ;


<s> assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; int Size = Mask . size ( ) ; int LaneSize = Size / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ; unsigned PERMMask = <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; SDValue Flipped = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , V1 , DAG . getConstant ( PERMMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( VT , DL , V1


<s> } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { if ( Parser . getTok ( ) . getString ( ) != <STR_LIT> ) return

Error ( DirectiveID . getLoc ( ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI ->


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue (


<s> const GlobalValue * GV = N -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget -> isABI_N64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , GA ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( ) ) ; return getAddrGlobal ( N , Ty , DAG , ( Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) ,


<s> for ( i = <NUM_LIT> ; i < count ; i ++ ) { addr = plus_constant ( to , i * <NUM_LIT> * sign ) ; mem = adjust_automodify_address ( basemem , SImode , addr , offset ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , base_regno + i ) ) ; offset += <NUM_LIT> * sign ; } if ( write_back ) { emit_move_insn ( to , plus_constant ( to , count * <NUM_LIT> * sign ) ) ; * offsetp = offset ; } seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( write_back ? <NUM_LIT> : <NUM_LIT> ) ) ) ; if ( write_back ) { XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( GET_MODE ( to ) , to , plus_constant ( to , count * <NUM_LIT> * sign ) ) ; i = <NUM_LIT> ; count ++ ; } for ( j = <NUM_LIT> ; i < count ; i ++ , j ++ ) { addr = plus_constant ( to , j


<s> void <ISA_LIT>AsmPrinter :: printNoHashImmediate ( const MachineInstr * MI , int OpNum


<s> DAG . getContext ( ) -> emitError ( <STR_LIT> ) ; return SDValue ( ) ; } MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL ,

ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ;


<s> __v4si result = ( __v4si ) __A ; result [ __N & <NUM_LIT> ]


<s> default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) || Ty . getSizeInBits ( ) > <NUM_LIT> ) OpRegBankIdx [ Idx ] = PMI_FirstFPR ; else OpRegBankIdx [ Idx ] = PMI_FirstGPR ; } unsigned Cost = <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : OpRegBankIdx = { PMI_FirstFPR , PMI_FirstGPR } ; break ; case TargetOpcode :: G_FPTOSI : case TargetOpcode :: G_FPTOUI : OpRegBankIdx = { PMI_FirstGPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_FCMP : OpRegBankIdx = { PMI_FirstGPR , PMI_None , PMI_FirstFPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_BITCAST : if ( OpRegBankIdx [ <NUM_LIT> ] != OpRegBankIdx [ <NUM_LIT> ] ) Cost = copyCost ( * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , OpSize [ <NUM_LIT> ] ) ; break ; case TargetOpcode :: G_LOAD : if ( OpRegBankIdx [ <NUM_LIT> ] != PMI_FirstGPR ) Cost = <NUM_LIT> ; else for ( const MachineInstr & UseMI : MRI . use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( isPreISelGenericFloatingPointOpcode ( UseMI . getOpcode ( ) ) ) { OpRegBankIdx [ <NUM_LIT> ] = PMI_FirstFPR ; break ; } break ; case TargetOpcode :: G_STORE : if ( OpRegBankIdx [ <NUM_LIT> ] == PMI_FirstGPR ) { unsigned VReg = MI . getOperand ( <NUM_LIT>


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getScalarSizeInBits ( ) ; return ( Index * ElSize ) %


<s> auto * CIdx = dyn_cast < ConstantSDNode > ( Idx ) ; if ( ! CIdx ) return ; unsigned IdxVal = CIdx -> getZExtValue ( ) ; if ( IdxVal == <NUM_LIT> ) { SDValue HiVec0 = DAG . getNode ( <STR_LIT> , DL , Vec1VT , Vec0 , DAG . getConstant ( NumElts , DL , Idx . getValueType ( ) ) ) ; SDValue ConcatVec = DAG . getNode ( <STR_LIT> , DL , Vec0VT , Vec1 , HiVec0 ) ; Results . push_back ( ConcatVec ) ; } else if ( IdxVal == NumElts ) { SDValue LoVec0 = DAG . getNode ( <STR_LIT> , DL , Vec1VT , Vec0 , DAG . getConstant ( <NUM_LIT> , DL , Idx


<s> enum machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , nmask ; dest = operands [ <NUM_LIT> ] ; op0 = operands [ <NUM_LIT> ] ; op1 = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; vmode = mode == SFmode ? V4SFmode : V2DFmode ; if ( GET_CODE ( op0 ) == CONST_DOUBLE ) { rtvec v ; if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( op0 == CONST0_RTX ( mode ) ) op0 = CONST0_RTX ( vmode ) ; else { if ( mode == SFmode ) v = gen_rtvec ( <NUM_LIT> , op0 , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) ) ; else v = gen_rtvec ( <NUM_LIT> , op0 , CONST0_RTX ( DFmode ) ) ; op0 = force_reg ( vmode , gen_rtx_CONST_VECTOR ( vmode , v ) ) ; } mask = ix86_build_signbit_mask ( mode , <NUM_LIT> , <NUM_LIT> ) ; if ( mode == SFmode ) emit_insn ( gen_copysignsf3_const ( dest , op0 , op1 , mask ) ) ; else emit_insn ( gen_copysigndf3_const ( dest , op0 , op1 , mask ) ) ; } else { nmask = ix86_build_signbit_mask ( mode , <NUM_LIT> , <NUM_LIT> ) ; mask = ix86_build_signbit_mask ( mode , <NUM_LIT>


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> void <ISA_LIT>LongBranch :: relaxBranches ( ) { SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) ; BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( SmallVector < MBBInfo , <NUM_LIT> > :: iterator BI = MBBs . begin ( ) , BE = MBBs . end ( ) ; BI != BE ; ++ BI ) { skipNonTerminators ( Position , * BI ) ; for ( unsigned BTI = <NUM_LIT> , BTE = BI -> NumTerminators ; BTI != BTE ; ++ BTI ) { assert ( Position . Address <= TI -> Address && <STR_LIT> ) ; if ( mustRelaxBranch ( * TI , Position . Address ) ) relaxBranch ( * TI ) ; skipTerminator ( Position , * TI ,


<s> void <ISA_LIT>DAGToDAGISel :: SwapAllSelectUsers ( SDNode * N ) { SmallVector < SDNode * , <NUM_LIT> > ToReplace ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; assert ( ( User -> getMachineOpcode ( ) == <STR_LIT> || User -> getMachineOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; ToReplace . push_back ( User ) ; } for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator UI = ToReplace . begin ( ) , UE = ToReplace . end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; SDNode * ResNode = CurDAG -> getMachineNode ( User -> getMachineOpcode ( ) , SDLoc ( User ) , User -> getValueType ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( User -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ResNode -> dump ( CurDAG


<s> BlockToSetOfInstrsPerColor Out , In , ReachableUses ; BlockToInstrPerColor Gen ; BlockToRegSet Kill ; initReachingDef ( MF , ColorOpToReachedUses , Gen , Kill , ReachableUses , RegToId , DummyOp , ADRPMode ) ; if ( ! DummyOp ) reachingDefAlgorithm ( MF , ColorOpToReachedUses , In , Out , Gen , Kill , ReachableUses , RegToId .


<s> { <STR_LIT> , rs6000_d_handle_target_float_abi } , { <STR_LIT> , rs6000_d_handle_target_object_format } , { NULL ,


<s> unsigned DstRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { if ( ! DisableLeafProc && isLeafProc ( MF ) ) { <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo


<s> getTargetStreamer ( ) . emitARM64WinCFINop ( ) ; return


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target


<s> if ( I -> getName ( ) . startswith ( <STR_LIT> ) || I -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; if ( TD -> getTypeAllocSize ( I -> getType ( ) -> getElementType ( ) ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( BSSGlobals , M , false ) ; return


<s> get<ISA_LIT>BLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It


<s> bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue SrcVal = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT SrcVT = SrcVal . getValueType ( ) ; if ( SrcVT != <STR_LIT> ) { if ( useSVEForFixedLengthVectorVT ( SrcVT ) ) return SDValue ( ) ; return Op ; } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( SrcVT , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; SDLoc dl ( Op ) ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , CallOptions


<s> int xs_hi_general_operand ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( ( GET_CODE ( x ) == CONST_INT ) && ( ( INTVAL ( x ) >= <NUM_LIT> ) || ( INTVAL ( x ) <


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ) ; return IsConstantImm && isShiftedUInt < num , shift > (


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL ; case


<s> if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; if ( Is64Bit ) { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) && TFI -> Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ; } return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT>


<s> bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool isThumb2 ( const MCSubtargetInfo & STI ) const { return isThumb ( STI ) && STI .


<s> return BaseT :: getIntrinsicInstrCost ( ICA


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! LdSt -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! LdSt

-> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ;


<s> static bool contains_core_p ( unsigned * arr , unsigned core ) { if ( arr [ <NUM_LIT> ] != INVALID_CORE


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! STI . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } STI . InitMCProcessorInfo ( CPU ,


<s> unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; bool IsRet64Bit = RetVT == <STR_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = ( IsRet64Bit && ! WantZExt ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = ( IsRet64Bit && ! WantZExt ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = ( IsRet64Bit && ! WantZExt ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : Opc = GPOpcTable [ WantZExt ] [ <NUM_LIT> * Idx + IsRet64Bit ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = FPOpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = FPOpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; } Register ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOLoad , ScaleFactor , MMO ) ; if ( VT == <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , ResultReg , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; ResultReg = ANDReg ; } if ( WantZExt && RetVT == <STR_LIT> && VT <= <STR_LIT> ) { Register Reg64 = createResultReg ( &


<s> return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = <STR_LIT> ; continue ; } assert ( ( DestReg != <STR_LIT> || BaseReg == <STR_LIT> ) && <STR_LIT> ) ; if ( ( DestReg == <STR_LIT> ) && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; break ; } bool HasCCOut = true ; int ImmIsT2SO = <STR_LIT> ( ThisVal ) ; bool ToSP = DestReg == <STR_LIT> ; unsigned t2SUB = ToSP ? <STR_LIT> : <STR_LIT> ; unsigned t2ADD = ToSP ? <STR_LIT> : <STR_LIT> ; unsigned t2SUBi12 = ToSP ? <STR_LIT> : <STR_LIT> ; unsigned t2ADDi12 = ToSP ? <STR_LIT> : <STR_LIT> ; Opc = isSub ? t2SUB : t2ADD ; if ( ImmIsT2SO != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? t2SUBi12 : t2ADDi12 ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) . add ( predOps ( <STR_LIT> )


<s> unsigned <ISA_LIT>FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { return <NUM_LIT>


<s> rtx tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( dep_insn ) , flow_dependent_p_1 , & tmp ) ; return tmp ==


<s> unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; unsigned DstSize = RBI . getSizeInBits (


<s> int regno = REGNO ( reg ) ; if ( ( WORDS_BIG_ENDIAN == <NUM_LIT> ) ^ ( low != <NUM_LIT> ) ) regno += ( TARGET_ARCH64 && SPARC_INT_REG_P


<s> break ; case METHOD_LU32I : emit_insn ( gen_rtx_SET ( x , gen_rtx_IOR ( DImode , gen_rtx_ZERO_EXTEND ( DImode , gen_rtx_SUBREG ( SImode , x , <NUM_LIT> ) ) , GEN_INT ( codes [ i ] . value ) ) ) ) ; break ; case METHOD_LU52I : emit_insn ( gen_lu52i_d ( x , x , GEN_INT ( <NUM_LIT> ) , GEN_INT ( codes [ i ] . value ) ) ) ; break ; case METHOD_INSV : emit_insn ( gen_rtx_SET ( gen_rtx_ZERO_EXTRACT ( DImode , x , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , gen_rtx_REG ( DImode , <NUM_LIT> ) ) ) ; break ; default : gcc_unreachable (


<s> MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned CondReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; int Imm = <NUM_LIT> ; bool UseImm = false ; bool isNegativeImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; Imm = ( int ) ConstInt -> getValue ( ) . getZExtValue ( ) ; if ( Imm < <NUM_LIT> ) { isNegativeImm = true ; Imm = ~ Imm ; } UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm


<s> static void uw_advance_context ( struct _Unwind_Context * context , _Unwind_FrameState * fs ) { uw_update_context ( context ,


<s> if ( ! T . isOSNaCl ( ) ) S = create<ISA_LIT>ELFStreamer ( Context , MAB , OS , Emitter , RelaxAll ) ; else S = create<ISA_LIT>NaClELFStreamer ( Context , MAB , OS , Emitter , RelaxAll ) ; return S


<s> Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = TheTriple . getArch ( ) == Triple :: ppc64 ; if ( TheTriple . getOS ( ) == Triple :: Darwin ) return

new <ISA_LIT>DarwinTargetAsmInfo ( is<ISA_LIT>64 ) ;


<s> MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { SplitArgs . clear ( ) ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; } if ( SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState


<s> return ( __m128i ) __builtin_ia32_vphaddubw (


<s> MachineInstr * MI = T2JumpTables [ i ] ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned NumOps = MCID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs


<s> else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( MI . getOperand ( I ) . getReg ( ) ) ; Binary |= <NUM_LIT> <<


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo / <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> void <ISA_LIT>InstrInfo :: expandZExtPseudo ( MachineInstr * MI , unsigned LowOpcode , unsigned Size ) const { emitGRX32Move ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , LowOpcode , Size ,

MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ;


<s> return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ; int Adj = DefAdj + UseAdj ; Adj += adjustDefLatency ( Subtarget , DefMI , DefMCID , DefAlign ) ; if ( Adj >= <NUM_LIT> || ( int ) Latency > - Adj ) { return Latency


<s> split_const ( * x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( base ) ) { label = mips16_add_constant ( pool , copy_rtx ( get_pool_constant ( base ) ) , get_pool_mode ( base ) ) ; base = gen_rtx_LABEL_REF ( Pmode


<NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ;


<s> AddMACCandidate ( Candidates , Acc , MulOp0 , MulOp1 , <NUM_LIT> ) ; Acc = dyn_cast < Instruction > ( A ) ; } while ( match ( Acc , m_Add ( m_Value ( A ) , m_Mul ( m_Value ( MulOp0 ) , m_Value ( MulOp1 ) ) ) ) ) { AddMACCandidate ( Candidates , Acc , MulOp0 , MulOp1 , <NUM_LIT> ) ; Acc = dyn_cast < Instruction


<s> AtomicSDNode * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; EVT NarrowVT = Node -> getMemoryVT ( ) ; EVT WideVT = <STR_LIT> ; if ( NarrowVT == WideVT ) return Op ; int64_t BitSize = NarrowVT . getSizeInBits ( ) ; SDValue ChainIn = Node -> getOperand ( <NUM_LIT> ) ; SDValue Addr = Node -> getOperand ( <NUM_LIT> ) ; SDValue CmpVal = Node -> getOperand ( <NUM_LIT> ) ; SDValue SwapVal = Node -> getOperand ( <NUM_LIT> ) ; MachineMemOperand * MMO = Node -> getMemOperand ( ) ; SDLoc DL ( Node ) ; EVT PtrVT = Addr . getValueType ( ) ; SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , WideVT ) , BitShift ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , CmpVal , SwapVal , BitShift ,

NegBitShift , DAG . getConstant ( BitSize , WideVT ) } ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) ) ; return


<s> auto CondReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueReg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseReg = MIB -> getOperand ( <NUM_LIT> ) .


<s> else if ( SignExtend32 < <NUM_LIT> > ( Lo12 >> <NUM_LIT> ) == SignExtend32 < <NUM_LIT> > ( Hi20 ) ) Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Lo12 ) ) ) ; else { Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Hi20 ) ) ) ; if ( Lo12 != <NUM_LIT> ) Insts . push_back ( Inst ( <STR_LIT> , Lo12 ) ) ; } if ( SignExtend32 < <NUM_LIT> > ( Hi20 >> <NUM_LIT> ) != SignExtend32 < <NUM_LIT> > ( Higher20 ) ) Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Higher20 ) ) ) ; if ( SignExtend32 < <NUM_LIT> > ( Higher20 >> <NUM_LIT> ) != SignExtend32 < <NUM_LIT> > ( Highest12 ) ) Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Highest12 ) ) ) ; return Insts


<s> unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || ( NumLanes != <NUM_LIT> && NumLanes != <NUM_LIT> ) ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl

, <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ;


<s> static bool shouldSwapCmpOperands ( const Comparison & C ) { if ( C . Op0 . getValueType ( ) == <STR_LIT> ) return false ; if ( isa < ConstantFPSDNode > ( C . Op1 ) ) return false ; auto * ConstOp1 = dyn_cast < ConstantSDNode > ( C . Op1 ) ; if ( ConstOp1 && ConstOp1 -> getZExtValue ( ) == <NUM_LIT> ) return false ; if ( isNaturalMemoryOperand ( C . Op1 , C . ICmpType ) && C . Op1 . hasOneUse ( ) ) return false ; if ( isNaturalMemoryOperand ( C . Op0 , C . ICmpType ) && C . Op0 . hasOneUse ( ) ) { if ( ! ConstOp1 ) return true ; if ( C . ICmpType != <STR_LIT> && isUInt < <NUM_LIT> > ( ConstOp1 -> getZExtValue ( ) ) ) return false ; if ( C . ICmpType != <STR_LIT> && isInt < <NUM_LIT> >

( ConstOp1 -> getSExtValue ( ) ) ) return false ;


<s> case llvm :: ELF :: EF_MIPS_ARCH_4 : case llvm :: ELF :: EF_MIPS_ARCH_5 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32 : case llvm :: ELF :: EF_MIPS_ARCH_64 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32R2 : case llvm :: ELF :: EF_MIPS_ARCH_64R2 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32R6 : case llvm :: ELF :: EF_MIPS_ARCH_64R6 : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; return <STR_LIT> . contains


<s> if ( ! canWidenShuffleElements ( Mask , WidenedMask ) ) return SDValue ( ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; bool IsV1Zero = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsV2Zero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( ! IsV1Zero && ! IsV2Zero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue ( ) ; if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } } int MaskLO = WidenedMask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : WidenedMask


<s> SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT StVT = St -> getMemoryVT ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromEltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToEltSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! isPowerOf2_32 ( NumElems * FromEltSz * ToEltSz ) ) return SDValue ( ) ; if ( <NUM_LIT> != ( NumElems * FromEltSz ) % ToEltSz ) return SDValue ( ) ; unsigned SizeRatio = FromEltSz / ToEltSz ; assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , DL , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ,


<s> else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return true ; assert ( NumV1Elements > <NUM_LIT> && <STR_LIT> ) ; if ( NumV2Elements == <NUM_LIT> ) return false ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : Mask . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) return true ; if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) SumV2Indices += i ; else if ( Mask [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) return true ; if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if

( Mask [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> )


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return


_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static SDValue combineShiftRightArithmetic ( SDNode * N , SelectionDAG & DAG ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( VT . isVector ( ) || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize >= Size || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType (


<s> static DecodeStatus DecodeRegListOperand ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegNum ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegLst == <NUM_LIT> )


<s> AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT>


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( )


<s> return ( ( qword ) ( vec_mulo ( ( vec_short8 ) (


<s> const MachineOperand MO = MI . getOperand ( opIdx ) ; return getMachineOpValue ( MI ,


<s> initialize<ISA_LIT>LongBranchPass ( * PassRegistry :: getPassRegistry (


<s> int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [


<s> if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ForcedVEXEncoding !=


<s> if ( Subtarget . getFrameLowering ( ) -> has128ByteRedZone ( MF ) ) { const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! <ISA_LIT>FI || <ISA_LIT>FI -> getUsesRedZone (


<s> rtx label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; emit_insn ( gen_cmpxf ( tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ) ; emit_jump_insn ( gen_bge ( label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_fyl2xp1_xf3 ( op0 , tmp2 ,


) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> <ISA_LIT>GISelActualAccessor * <ISA_LIT>GISel = new <ISA_LIT>GISelActualAccessor ( ) ; <ISA_LIT>GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; <ISA_LIT>GISel -> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; <ISA_LIT>GISel -> InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ; <ISA_LIT>GISel -> RegBankInfo .


<s> Target & llvm :: getTheARM64Target ( ) { static Target TheARM64Target ; return


<s> if ( Candidate . R . OriginalAddend != PreviousBest . R . OriginalAddend ) return Candidate . R . OriginalAddend < PreviousBest . R


<s> const DebugLoc & dl = MI . getDebugLoc ( ) ; ASSERT_SORTED ( PopTable ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , I -> getOpcode (


<s> Value * <ISA_LIT>IREmitter :: visitADDC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> case V4SImode : case V8SFmode : case V4SFmode : vec_mode = mode ; imode = SImode ; break ; case V8DImode : case V4DImode : case V2DImode : case V8DFmode : case V4DFmode : case V2DFmode : vec_mode = mode ; imode = DImode ; break ; case TImode : case TFmode : vec_mode = VOIDmode ; imode =


<s> CmpInstr -> setDesc ( MCID ) ; CmpInstr -> RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr -> getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr ( CmpInstr , SrcReg , SrcReg2 , MRI , & getRegisterInfo ( ) , this ) ; assert ( ( CmpValue == <NUM_LIT> || CmpValue == <NUM_LIT> ) && <STR_LIT> ) ; if ( CmpValue != <NUM_LIT> || SrcReg2 != <NUM_LIT> ) return false ; if ( ! MRI -> use_nodbg_empty ( CmpInstr -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; return substituteCmpToZero ( CmpInstr , SrcReg ,


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl


<s> if ( ! VT . isFixedLengthVector ( ) ) return false ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void llvm :: addUnpredicatedMveVpredROp ( MachineInstrBuilder & MIB , Register DestReg ) { addUnpredicatedMveVpredNOp ( MIB )


<s> } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg ,


<s> I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else return false ; I . setDesc ( TII . get ( TargetOpcode :: COPY ) ) ; return true ; } case TargetOpcode :: G_ADD : { Register AddDst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddLHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddRHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( AddLHS ) ; if ( Ty . isVector ( ) ) return false ; unsigned Size = Ty . getSizeInBits ( ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; auto MatchCmp = [ & ] ( Register Reg ) -> MachineInstr * { if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return nullptr ; if ( Size == <NUM_LIT> ) return getOpcodeDef ( TargetOpcode :: G_ICMP , Reg , MRI ) ; Register ZExt ; if ( ! mi_match ( Reg , MRI , m_OneNonDBGUse ( m_GZExt ( m_OneNonDBGUse ( m_Reg ( ZExt ) ) ) ) ) ) return nullptr ; auto * Cmp = getOpcodeDef ( TargetOpcode :: G_ICMP , ZExt , MRI ) ; if ( ! Cmp || MRI . getType ( Cmp -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) != <NUM_LIT> ) return nullptr ; return Cmp ; } ; MachineInstr * Cmp = MatchCmp ( AddRHS ) ; if ( ! Cmp ) { std :: swap ( AddLHS , AddRHS ) ; Cmp = MatchCmp ( AddRHS ) ; if ( ! Cmp ) return false ; } auto & PredOp = Cmp -> getOperand ( <NUM_LIT> ) ; auto Pred = static_cast < CmpInst :: Predicate > ( PredOp . getPredicate ( ) ) ; const <STR_LIT> InvCC = changeICMPPredTo<ISA_LIT>CC ( CmpInst :: getInversePredicate ( Pred ) ) ; MIB . setInstrAndDebugLoc (


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) ||


<s> void <ISA_LIT>AddressSanitizer64 :: InstrumentMemOperandLarge ( <ISA_LIT>Operand & Op , unsigned AccessSize , bool IsWrite , const RegisterContext & RegCtx , MCContext & Ctx , MCStreamer & Out ) { unsigned AddressRegI64 = RegCtx . AddressReg ( <STR_LIT> ) ; unsigned ShadowRegI64 = RegCtx . ShadowReg ( <STR_LIT> ) ; ComputeMemOperandAddress ( Op , <STR_LIT> , AddressRegI64 , Ctx , Out ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( AddressRegI64 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; switch ( AccessSize ) { case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitCallAsanReport ( AccessSize , IsWrite , Ctx , Out , RegCtx


<s> break ; case XFmode : index = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> fp_load [ index ] , ix86_cost -> fp_store [ index ] ) ; return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( regclass ) ) { int index ; switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : index = <NUM_LIT> ; break ; case <NUM_LIT> : index = <NUM_LIT> ; break ; case <NUM_LIT> : index = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> sse_load [ index ] , ix86_cost -> sse_store [ index ] ) ; return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( regclass ) ) { int index ; switch ( GET_MODE_SIZE (


<s> _mm_cvttsd_u64 ( __m128d __A ) { return ( unsigned long long ) __builtin_ia32_vcvttsd2usi64 ( ( __v2df


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> hasOrderedMemoryRef ( ) ) { ++ MBBI ; break ; } if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } if ( TII -> isLdStPairSuppressed ( MI ) ) { ++ MBBI ; break ; } bool MergeForward = false ; int SExtIdx = - <NUM_LIT> ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , MergeForward , SExtIdx , ScanLimit ) ; if ( Paired != E ) { MBBI = mergePairedInsns ( MBBI , Paired , MergeForward , SExtIdx ) ; Modified = true ; ++ NumPairCreated ; if ( isUnscaledLdst ( MI -> getOpcode ( ) ) ) ++ NumUnscaledPairCreated ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; int Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } MachineBasicBlock :: iterator Update = findMatchingUpdateInsnForward ( MBBI , ScanLimit , <NUM_LIT> ) ; if ( Update != E ) { MBBI = mergePostIdxUpdateInsn ( MBBI


<s> if ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) && int_size_in_bytes (


<s> auto & TD = DAG . getDataLayout ( ) ; EVT PTy = getPointerTy ( TD ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , DL , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || ABI . IsN64 ( ) ) { Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Addr , getPICJumpTableRelocBase ( Table ,


<s> <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isLittle = false ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout (

isLittle ? std :: string ( <STR_LIT> ) :


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent (


<s> static bool isBrAnalysisUnpredicatedTerminator ( const MachineInstr * MI , const <ISA_LIT>InstrInfo


<s> static bool aarch64_function_ok_for_sibcall ( tree , tree exp ) { if ( crtl -> abi -> id ( ) != expr_callee_abi ( exp ) . id (


<s> if ( ! isMem ( ) ) return false ; return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK || Memory . Alignment


<s> if ( ( unsigned ) Idx >= JumpTableEntryInfo . size ( ) ) JumpTableEntryInfo . resize


<s> <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addLeaAddress ( BuildMI ( MBB , DL , TII . get ( Opc )


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>_64Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_64Target , create<ISA_LIT>_64AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_32Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_64Target


<s> <ISA_LIT>_64RelType Type = getType64 ( Fixup . getKind ( ) , Modifier , IsPCRel ) ; if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Ctx , Fixup . getLoc ( ) , Modifier , Type , IsPCRel , Fixup . getKind ( ) ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU ) &&


<s> auto IsZeroInit = [ ] ( MachineInstr * Def ) { return ! isVectorPredicated ( Def ) && Def -> getOpcode ( ) == <STR_LIT> && Def -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } ; bool AllowScalars = isHorizontalReduction ( MI ) ; for ( auto & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( ! isRegInClass ( MO , QPRs ) && AllowScalars ) continue ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Defs ; RDA . getGlobalReachingDefs ( & MI , MO . getReg ( ) , Defs ) ; for ( auto * Def : Defs ) { if ( Def == & MI || FalseLanesZero . count ( Def ) || IsZeroInit ( Def ) ) continue ; if ( MO . isUse ( ) && isPredicated ) continue ; return false


<s> auto * S = new <ISA_LIT>WinCOFFStreamer ( Context , std :: move ( MAB ) , std :: move ( Emitter ) , std :: move ( OW ) ) ; S -> getAssembler ( ) .

setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ;


<s> static void vr4130_true_reg_dependence_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * insn_ptr ; insn_ptr = ( rtx * ) data ; if ( REG_P ( x ) && * insn_ptr != <NUM_LIT> && reg_referenced_p (

x , PATTERN ( * insn_ptr ) ) ) * insn_ptr = <NUM_LIT> ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( CPU64RegsTable [ RegNo ] ) ) ; return MCDisassembler ::


Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ;


<s> int Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = i + Amt ; SDValue T = DAG . getVectorShuffle ( <STR_LIT> ,


<s> if ( loongarch_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , <STR_LIT> , <NUM_LIT> ) ; return default_elf_select_rtx_section ( mode , x


<s> if ( ! STI . useSoftFloat ( ) && STI . hasVFP2Base ( ) && ! STI . isThumb1Only ( ) ) return CSR_NoRegs_RegMask ; else return CSR_FPRegs_RegMask


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return &


<s> const TargetRegisterClass * QPRs = TRI . getRegClass ( <STR_LIT> ) ; SetVector < MachineInstr * > FalseLanesUnknown ; SmallPtrSet < MachineInstr * , <NUM_LIT> > FalseLanesZero ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Predicated ; MachineBasicBlock * Header = ML . getHeader ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto & MI : * Header ) { if ( ! shouldInspect ( MI ) ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode


<s> insn = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insn , temp3 , o0 , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLSLD_BASE ) ) ; temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tldo_hix22 ( temp1 , addr ) ) ; emit_insn ( gen_tldo_lox10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tldo_add32 ( ret , temp3 , temp2 , addr ) ) ; else emit_insn ( gen_tldo_add64 ( ret , temp3 , temp2 , addr ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; temp3 = gen_reg_rtx ( Pmode ) ; got = sparc_tls_got ( ) ; emit_insn ( gen_tie_hi22 ( temp1 , addr ) ) ; emit_insn ( gen_tie_lo10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_ld32 ( temp3 , got , temp2 , addr ) ) ; else emit_insn ( gen_tie_ld64 ( temp3 , got , temp2 , addr ) ) ; if ( TARGET_SUN_TLS ) { ret = gen_reg_rtx ( Pmode ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_add32 ( ret , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 , addr ) ) ; else emit_insn ( gen_tie_add64 ( ret , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 , addr ) ) ; } else ret = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 ) ; break ; case TLS_MODEL_LOCAL_EXEC : temp1 = gen_reg_rtx ( Pmode ) ; temp2 = gen_reg_rtx ( Pmode ) ; if ( TARGET_ARCH32 ) { emit_insn ( gen_tle_hix22_sp32 ( temp1 , addr ) ) ; emit_insn ( gen_tle_lox10_sp32 ( temp2 , temp1 , addr ) ) ; } else { emit_insn ( gen_tle_hix22_sp64 ( temp1 , addr )


<s> SDNode * Hi64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegEven ) ; SDNode * Lo64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegOdd ) ; unsigned alignment = StNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue OutChains [ <NUM_LIT> ] ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , dl , SDValue ( Hi64 , <NUM_LIT>

) , StNode -> getBasePtr ( ) , MachinePointerInfo ( ) , alignment ) ;


<s> break ; case 'y' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget . hasMMX ( ) ) weight = CW_SpecificReg ; break ; case 'Y' : if ( StringRef ( constraint ) . size ( ) != <NUM_LIT> ) break ; switch ( constraint [ <NUM_LIT> ] ) { default : return CW_Invalid ; case 'z' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) ) return CW_SpecificReg ; return CW_Invalid ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) return CW_Register ; return CW_Invalid ; case 'm' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget . hasMMX ( ) ) return weight ; return CW_Invalid ; case 'i' : case 't' : case '2' : if ( ! Subtarget . hasSSE2 ( ) ) return CW_Invalid ; break ; } break ; case 'v' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; LLVM_FALLTHROUGH ; case 'x' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) ) weight = CW_Register ; break ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case


<s> ELFFileFormat * file_format = pParent . getTarget ( ) . getOutputFormat ( ) ; <ISA_LIT>_32GOTEntry * got_entry1 = pParent . getSymGOTMap ( ) . lookUpFirstEntry ( * rsym ) ; if ( rsym -> isLocal ( ) ) pParent . getSymGOTMap ( ) . lookUpSecondEntry ( * rsym ) -> setValue ( pReloc . symValue ( ) ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: Address GOT_OFF = file_format -> getGOT ( ) . addr ( ) + got_entry1 ->

getOffset ( ) - file_format -> getGOTPLT ( ) . addr ( ) ;


<s> if ( isThumb2 ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> <ISA_LIT>_32Disassembler ( const MCSubtargetInfo & STI ) : <ISA_LIT>GenericDisassembler ( STI , MODE_32BIT


<s> bool <ISA_LIT>AsmParser :: processInstruction ( MCInst & Inst , const OperandVector & Ops ) { return false


<s> } else if ( MEM_P ( src ) ) { mem_operand = XEXP ( src , <NUM_LIT> ) ; src_modifies = side_effects_p ( mem_operand ) ; if ( auto_inc_p ( mem_operand ) ) auto_inc_reg_rtx = XEXP ( mem_operand , <NUM_LIT> ) ; src_volatile = MEM_VOLATILE_P ( src ) ; if ( src_volatile ) { src = copy_rtx ( src ) ; MEM_VOLATILE_P ( src ) = <NUM_LIT> ; } } else mem_operand = NULL_RTX ; if ( mem_operand == NULL_RTX ) { if ( REG_P ( src ) && REG_P ( dest ) && reg_overlap_mentioned_p ( dest , src ) && REGNO ( dest ) > REGNO ( src ) ) direction = - <NUM_LIT> ; } else if ( GET_CODE ( mem_operand ) == PRE_DEC || ( GET_CODE ( mem_operand ) == PLUS && GET_CODE ( XEXP ( mem_operand , <NUM_LIT> ) ) == PRE_DEC ) ) direction = - <NUM_LIT> ; else if ( MEM_P ( src ) && reg_overlap_mentioned_p ( dest , src ) ) { int regno ; gcc_assert ( REG_P ( dest ) ) ; regno = REGNO ( dest ) ; gcc_assert ( refers_to_regno_p ( regno , regno + num_words , mem_operand , <NUM_LIT> ) ) ; if ( refers_to_regno_p ( regno , mem_operand ) ) direction = - <NUM_LIT> ; else if ( refers_to_regno_p ( regno + num_words - <NUM_LIT> , regno + num_words , mem_operand , <NUM_LIT> ) ) direction = <NUM_LIT> ; else gcc_unreachable ( ) ; } end = direction < <NUM_LIT> ? - <NUM_LIT> : num_words ; for ( i = direction < <NUM_LIT> ? num_words - <NUM_LIT> : <NUM_LIT> ; i != end ; i += direction ) { rtx w_src , w_dest , insn ; if ( src_modifies ) w_src = gen_rtx_MEM ( word_mode , mem_operand ) ; else w_src = simplify_gen_subreg ( word_mode , src , mode , i * UNITS_PER_WORD ) ; if ( src_volatile ) MEM_VOLATILE_P ( w_src )


<s> MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr ,


<s> const unsigned RetOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( CallOpc ) ) . addMBB ( CallTarget ) ; Entry -> addSuccessor ( CallTarget ) ; Entry -> addSuccessor ( CaptureSpec ) ; CallTarget -> setHasAddressTaken ( ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( CaptureSpec ) ; CaptureSpec -> setHasAddressTaken ( ) ; CaptureSpec -> addSuccessor ( CaptureSpec ) ; CallTarget -> setAlignment ( <NUM_LIT> ) ; insertRegReturnAddrClobber ( * CallTarget , * Reg ) ; BuildMI ( CallTarget , DebugLoc ( ) , TII


<s> assert ( RC -> contains ( PReg ) && <STR_LIT> ) ; unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg ,


<s> bool isSImm20 ( ) const { return isSImm < <NUM_LIT> >


<s> inline vector unsigned short vec_vsubsuhs ( vector unsigned


<s> if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return CCFPmode ; case LT : case LE : case GT : case GE : case LTGT : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) && y == const0_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXNZmode ; else return CCNZmode ; } else { if ( GET_CODE ( x ) == NOT && y == constm1_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXCmode ; else return CCCmode ; } if ( ! TARGET_ARCH64 && GET_MODE ( x ) == DImode ) { if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , <NUM_LIT> ) == UNSPEC_ADDV || XINT ( y , <NUM_LIT> ) == UNSPEC_SUBV ||

XINT ( y , <NUM_LIT> ) == UNSPEC_NEGV ) ) return CCVmode ;


<s> bool mayNeedRelaxation ( const MCInst & ) const override { return


<s> Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , <STR_LIT> ) ; unsigned SrcOddReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcOddReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestOddReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer (


<s> int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes (


<s> return ( vector unsigned short ) __builtin_altivec_vslh ( ( vector signed short ) a1 , ( vector


<s> SDValue <ISA_LIT>TargetLowering :: getGlobalReg ( SelectionDAG &


<s> TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT (


<s> SDNode * <ISA_LIT>DagToDagISel :: Select ( SDNode * n ) { return NULL


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T

, computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) {


<s> int Offset = getLdStOffsetOp ( MemMI ) . getImm ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } BitVector ModifiedRegs , UsedRegs ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI ->


<s> bool <ISA_LIT>TargetLowering :: lowerInterleavedStore ( StoreInst * SI , ShuffleVectorInst * SVI , unsigned Factor ) const { assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; VectorType * VecTy = SVI -> getType ( ) ; assert ( VecTy -> getVectorNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned LaneLen = VecTy -> getVectorNumElements ( ) / Factor ; Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , LaneLen ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! isLegalInterleavedAccessType ( SubVecTy , DL ) ) return false ; unsigned NumStores = getNumInterleavedAccesses ( SubVecTy , DL ) ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = dyn_cast < VectorType > ( Op0 -> getType ( ) ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { unsigned IdxJ = StoreCount * LaneLen * Factor


<s> } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr ::


<s> SDValue A64CMP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , TheBit . getValueType ( ) ) , DAG . getCondCode ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , A64CMP

, DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DestBB ) ;


<s> case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( isa < ConstantFP > ( CallOperandVal )


<s> return decodeBDAddr20Operand ( Inst ,


<s> if ( ( * iptr & <NUM_LIT> ) == <NUM_LIT> ) break ; } if ( i == NOFFSETS ) return ~ <NUM_LIT> ; iptr += SIGN_EXTEND ( GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> ) ; fixup_plabel [ <NUM_LIT> ] = ( unsigned int ) iptr + <NUM_LIT> ; fixup_plabel [ <NUM_LIT> ] = got [


<s> if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . is256BitVector ( ) && SubVecVT . is128BitVector ( ) ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = peekThroughBitcasts ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( SubVec2 ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , false ) ) return Ld ; } if ( SubVec2 == peekThroughBitcasts ( SubVec ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec ) ; } } } if ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && SubVecVT . is128BitVector ( ) ) return insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( OpVT . is512BitVector ( ) && SubVecVT . is256BitVector ( ) ) return insert256BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( OpVT . getVectorElementType ( ) == <STR_LIT> ) return insert1BitVector ( Op , DAG , Subtarget ) ; return SDValue (


<s> static unsigned calcLiveInMask ( MachineBasicBlock * MBB ) { unsigned Mask = <NUM_LIT> ; for ( const auto & LI : MBB -> liveins (


<s> if ( St -> isVolatile ( ) ) return SDValue ( ) ; SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( St -> isTruncatingStore ( ) && VT . isVector ( ) ) { SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT StVT = St -> getMemoryVT ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromEltSz = VT . getScalarSizeInBits ( ) ; unsigned ToEltSz = StVT . getScalarSizeInBits ( ) ; if ( ! isPowerOf2_32 ( NumElems * FromEltSz * ToEltSz ) ) return SDValue ( ) ; if ( <NUM_LIT> != ( NumElems * FromEltSz ) % ToEltSz ) return SDValue ( ) ; unsigned SizeRatio = FromEltSz / ToEltSz ; assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = DAG . getDataLayout ( ) . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType ,

VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ;


<s> getPrePostIndexedMemOpInfo ( * I , Scale , MinOffset , MaxOffset ) ; if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } else { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } ( void ) MIB ; if ( IsPreIdx ) { ++ NumPreFolded


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool IsSibCall = ! MF . getTarget ( ) . Options . GuaranteedTailCallOpt && Info . CallConv != CallingConv :: Tail && Info . CallConv != CallingConv :: SwiftTail ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CallingConv :: ID CalleeCC = Info . CallConv ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; MachineInstrBuilder CallSeqStart ; if ( ! IsSibCall ) CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , true ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; MIB . addImm ( <NUM_LIT> ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; int FPDiff = <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; if ( ! IsSibCall ) { unsigned NumReusableBytes = FuncInfo -> getBytesInStackArgArea ( ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , F . getContext ( ) ) ; analyzeArgInfo ( OutInfo , OutArgs , * AssignFnFixed , * AssignFnVarArg ) ; NumBytes = alignTo ( OutInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; FPDiff = NumReusableBytes - NumBytes ; if ( FPDiff < <NUM_LIT> && FuncInfo -> getTailCallReservedStack ( ) < ( unsigned ) - FPDiff ) FuncInfo -> setTailCallReservedStack ( - FPDiff ) ; assert ( FPDiff % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; } const auto & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , true , FPDiff ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; if ( Info . IsVarArg && Info . IsMustTailCall ) { for ( const auto & F :


<s> rtx src_reg ; src_reg = src ; if ( GET_CODE ( src_reg ) == SUBREG ) src_reg = SUBREG_REG ( src_reg ) ; if ( GET_CODE ( src_reg ) == REG && SPARC_FP_REG_P ( REGNO ( src_reg ) ) ) src_is_freg = true ; if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_operand ( src , GET_MODE ( src ) ) && ! src_is_freg ) { if ( TARGET_ARCH64 ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( SImode ) ; } else if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_double_operand ( src , GET_MODE ( src ) ) && ! src_is_freg ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else if ( ! TARGET_FPU && register_operand (


<s> int pa_emit_hpdiv_const ( rtx * operands , int unsignedp ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) > <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && pa_magic_milli [ INTVAL ( operands [ <NUM_LIT> ] ) ] ) { rtx ret = gen_rtx_REG ( SImode ,


<s> return ( __m128d ) __builtin_ia32_expanddf128_maskz ( ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( )


<s> SDValue <ISA_LIT>TargetLowering :: lowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x2_t


<s> arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree inner_type = TREE_TYPE ( rtype ) ; tree_vector_builder n_elts ( rtype , VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; sparc_handle_vis_mul8x16 ( & n_elts , code , inner_type , arg0 , arg1 ) ; return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_FPMERGE : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree_vector_builder n_elts ( rtype , <NUM_LIT> * VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; unsigned i ; for ( i = <NUM_LIT> ; i < VECTOR_CST_NELTS ( arg0 ) ; ++ i ) { n_elts . quick_push ( VECTOR_CST_ELT ( arg0 , i ) ) ; n_elts . quick_push ( VECTOR_CST_ELT ( arg1 , i ) ) ; } return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_PDIST : case SPARC_BUILTIN_PDISTN : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( code == SPARC_BUILTIN_PDIST ) { arg2 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg2 ) ; } else arg2 = integer_zero_node ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST && TREE_CODE ( arg2 ) == INTEGER_CST ) { bool overflow = false ; widest_int result = wi :: to_widest ( arg2 ) ; widest_int tmp ; unsigned i ; for ( i = <NUM_LIT> ; i < VECTOR_CST_NELTS ( arg0 ) ; ++ i ) { tree e0 = VECTOR_CST_ELT ( arg0 , i ) ; tree e1 = VECTOR_CST_ELT (


<s> uint64_t Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t bit = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; bit |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t dst = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( bit ) ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , dst * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( dst ) ) ; return Success


<s> attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( <STR_LIT> ,


<s> } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! isT2 && ( Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) != Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getPrefTypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { if ( OffImm < <NUM_LIT> ) { if ( OffImm < - <NUM_LIT> ) return false ; } else { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; } Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT>


<s> static void AnalyzeReturnValues ( CCState & State , SmallVectorImpl < CCValAssign >

& RVLocs , const SmallVectorImpl < ArgT > & Args ) {