<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI -> getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI -> setObjectSize ( RPI .


<s> auto & MBB = * MI . getParent ( ) ; auto & MF = * MBB . getParent ( ) ; auto & MRI = MF . getRegInfo ( ) ; uint64_t Immed ; if ( Root . isImm ( ) ) Immed = Root . getImm ( ) ; else if ( Root . isCImm ( ) ) Immed = Root . getCImm ( ) -> getZExtValue ( ) ; else if ( Root . isReg ( ) ) { auto ValAndVReg = getConstantVRegValWithLookThrough ( Root . getReg ( ) , MRI , true ) ; if ( ! ValAndVReg ) return None ; Immed = ValAndVReg -> Value . getSExtValue ( ) ; } else return


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getThumbBRTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI


<s> APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; Info . Offset = DotDisp . getZExtValue ( ) ; } else if ( ( isParsingMSInlineAsm ( ) || getParser ( ) . isParsingMasm ( ) ) && Tok . is ( AsmToken :: Identifier ) ) { const std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; const StringRef Base = BaseMember . first , Member = BaseMember . second ; if ( getParser ( ) . lookUpField ( SM . getType ( ) , DotDispStr , Info ) && getParser ( ) . lookUpField ( SM . getSymName ( ) , DotDispStr , Info ) && getParser ( ) . lookUpField ( DotDispStr , Info ) && ( ! SemaCallback || SemaCallback -> LookupInlineAsmField ( Base , Member ,

Info . Offset ) ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> rtx regs ; if ( nwords == <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> ) nwords = <NUM_LIT> ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = <NUM_LIT> ; i < nwords ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; } return


<s> static __inline qword si_ceqh ( qword a , qword b ) { return ( ( qword ) ( vec_cmpeq ( ( vec_ushort8 ) ( a )


<s> if ( RegName [ <NUM_LIT> ] == 'q' ) { std :: string RN ( RegName ) ; RN [ <NUM_LIT> ] = 'f' ; OS << RN


<s> void <ISA_LIT>InstrInfo :: getNoop ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT> )


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzcnt_u64 ( unsigned long long __X ) { return __builtin_ctzll ( __X


<s> LowOverheadLoop ( MachineLoop * ML , MachineLoopInfo * MLI , ReachingDefAnalysis * RDA ) : ML ( ML ) , MLI ( MLI ) , RDA ( RDA ) { MF = ML -> getHeader ( ) ->


<s> bool <ISA_LIT>PreTileConfig :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) .


<s> void <ISA_LIT>TargetELFStreamer :: emitArch ( unsigned


<s> MachineBasicBlock :: iterator NextMBBI ; for ( ; MBBI != E ; MBBI = NextMBBI ) { MachineInstr & MI = * MBBI ; NextMBBI = std :: next ( MBBI ) ; if ( isIndirectControlFlowNotComingBack ( MI ) ) { assert ( MI . isTerminator ( )


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , Align ) ; unsigned LoadOp = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , get (


<s> LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; NumElts = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( { NumElts , false } , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , Alignment ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode

( LogicOp , dl , LogicVT , Operand , Mask ) ;


<s> printMemOperand ( const MachineInstr * MI , int opNum , const char * Modifier ) { if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { printOperand ( MI , opNum + <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , opNum ) ; return ; } printOperand ( MI , opNum ) ; O << <STR_LIT>


<s> if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) { FrameIdx = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return


<s> const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; unsigned FixupKind ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveRegPX ( Reg , Offset ) ; return


<s> if ( I -> isDebugValue ( ) ) DBGInstructions . push_back ( & * I ) ; } MachineBasicBlock * MBB = First -> getParent ( ) ; for ( auto * MI : DBGInstructions ) MBB -> insertAfter ( Last , MI ->


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return


<s> return ( __m128d ) vec_mergel ( res , ( __v2df ) __A ) ; __v2df res = ( __v2df ) __A ; res [ <NUM_LIT> ] = ( ( __v4sf )


<s> if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) sec = <NUM_LIT> ; else sec = <NUM_LIT> ; } else if ( decl_readonly_section ( decl , reloc ) ) sec = <NUM_LIT> ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) { switch ( name [ <NUM_LIT> ] ) { case 'b' : sec = <NUM_LIT> ; break ; case 't' : if ( sec == <NUM_LIT> ) sec = <NUM_LIT> ; else sec = <NUM_LIT> ; break ; case 'f' : if ( sec == <NUM_LIT> ) sec = <NUM_LIT> ; else if ( sec == <NUM_LIT> )


<s> else snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } else { if ( TARGET_RELAX_HINT ) snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> ) ; else snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> ) ; } output_asm_insn ( pattern ,


, <NUM_LIT> , ( __mmask32 ) - <NUM_LIT> ) ;


<s> assert ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) && <STR_LIT> ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; EVT PtrVT = getPointerTy ( DAG


<s> if ( ! shouldScheduleAdjacent ( * DAG -> TII , DAG -> MF . getSubtarget ( ) , FirstMI , SecondMI ) ) return false ; for ( SDep & Dep : AnchorDeps ) { if ( Dep . isWeak ( ) ) continue ; SUnit & DepSU = * Dep . getSUnit ( ) ; if ( ! Preds && & DepSU == & DAG -> ExitSU ) continue ; const MachineInstr * DepMI = DepSU . getInstr ( ) ; if ( ! DepMI || DepMI -> isPseudo ( ) || DepMI -> isTransient ( ) ) continue ; FirstMI = Preds ? DepMI : AnchorMI ; SecondMI = Preds ? AnchorMI : DepMI ; if ( ! shouldScheduleAdjacent ( * DAG -> TII , DAG -> MF . getSubtarget ( ) , FirstMI , SecondMI ) ) continue ; SUnit & FirstSU = Preds ? DepSU : AnchorSU ; SUnit & SecondSU = Preds ? AnchorSU : DepSU ; DAG -> addEdge ( & SecondSU , SDep ( & FirstSU , SDep :: Cluster ) ) ; for ( SDep & IDep : AnchorDeps ) if ( IDep . getSUnit ( )

== & DepSU ) IDep . setLatency ( <NUM_LIT> ) ;


<s> if ( FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ) std :: swap ( TrueVal , FalseVal ) ; SDValue <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>CC2 = DAG . getConstant ( CondCode2 , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , TrueVal , <ISA_LIT>CC2 , CCR


<s> -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true


<s> emit_insn ( gen_lshrsi3 ( tmp2 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; tmp3 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_xorsi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp4 , tmp3 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorsi3 ( tmp , tmp3 , tmp4 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_andsi3 ( dst , tmp , const1_rtx ) ) ; } else { if ( rs6000_cost -> muldi >= COSTS_N_INSNS ( <NUM_LIT> ) ) { rtx tmp1 , tmp2 , tmp3 , tmp4 , tmp5 , tmp6 ; tmp1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp2 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; tmp3 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp4 , tmp3 , GEN_INT ( <NUM_LIT> ) ) ) ; tmp5 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp5 , tmp3 , tmp4 ) ) ; tmp6 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp6 , tmp5 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xordi3 ( tmp , tmp5 , tmp6 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_anddi3 ( dst , tmp , const1_rtx )


<s> bool LoadFirstElt = ! isNullConstant ( MaskBV -> getOperand ( <NUM_LIT> ) ) ; bool LoadLastElt = ! isNullConstant ( MaskBV -> getOperand ( NumElts - <NUM_LIT> ) ) ; if ( LoadFirstElt && LoadLastElt ) { SDValue VecLd = DAG . getLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMemOperand ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , VecLd , ML -> getPassThru ( ) ) ; return DCI . CombineTo ( ML , Blend , VecLd . getValue ( <NUM_LIT> ) , true ) ; } if ( ML -> getPassThru ( ) . isUndef ( ) ) return SDValue ( ) ; SDValue NewML = DAG . getMaskedLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMask ( ) , DAG . getUNDEF ( VT ) , ML -> getMemoryVT ( ) , ML -> getMemOperand ( ) , ML -> getExtensionType ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , NewML , ML -> getPassThru ( ) ) ; return DCI . CombineTo ( ML , Blend , NewML . getValue ( <NUM_LIT>


<s> if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; return


<s> bool isBGP ( ) const { return TargetTriple . getVendor ( ) ==


<s> if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; }


<s> unified_syntax = false ; } else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return false


<s> if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT>


<s> void addMSACtrlAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName =


<s> tree addr = std_gimplify_va_arg_expr ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > <NUM_LIT> :

TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ) {


<s> assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT ElVT = VT . getVectorElementType ( ) ; unsigned Factor = VT . getSizeInBits ( ) / <NUM_LIT> ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal ,


<s> switch ( CallingConv ) { default : return false ; case CallingConv :: <ISA_LIT>_StdCall : return ! Subtarget -> is64Bit ( ) ; case CallingConv :: <ISA_LIT>_FastCall : return ! Subtarget -> is64Bit ( ) ; case CallingConv ::


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; Out . EmitBundleLock ( true ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock


<s> return ( __mmask16 ) __builtin_ia32_ucmpb128_mask ( ( __v16qi ) __X , ( __v16qi )


<s> switch ( <ISA_LIT>CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return true ; case <STR_LIT> : return false ; case <STR_LIT> : return false ; case <STR_LIT> : return false ; case <STR_LIT> : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> static DecodeStatus DecodeShiftLeftImm16 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val > <NUM_LIT> ) return MCDisassembler


<s> static void mips_get_cprestore_base_and_offset ( rtx * base , HOST_WIDE_INT * offset , bool load_p ) { const struct mips_frame_info * frame ; frame = & cfun -> machine -> frame ; if ( frame_pointer_needed && ! ( TARGET_CPRESTORE_DIRECTIVE && ! load_p ) ) { * base =


<s> while ( it != ie ) { plt1 = & ( llvm :: cast < PLTEntryBase > ( * it ) ) ; unsigned char * data ; data = static_cast < unsigned char * > ( malloc ( plt1 -> size ( ) ) ) ; if ( ! data ) fatal ( diag :: fail_allocate_memory_plt ) ; memcpy ( data , m_PLT1 , plt1 -> size ( ) ) ; uint32_t * offset ; offset = reinterpret_cast < uint32_t * > ( data + <NUM_LIT> ) ; * offset = SymGOTPCREL ; SymGOTPCREL += GOTEntrySize - m_PLT1Size ; offset = reinterpret_cast < uint32_t * > ( data + <NUM_LIT> ) ; * offset = PLTRelIndex ; PLTRelIndex ++ ; offset = reinterpret_cast < uint32_t * > ( data + <NUM_LIT> ) ; * offset = - ( PLTEntryOffset + <NUM_LIT> + <NUM_LIT> ) ; PLTEntryOffset += m_PLT1Size


<s> bool sh_lshrsi_clobbers_t_reg_p ( rtx shift_amount ) { gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = INTVAL ( shift_amount


<s> SDValue Ops [ ] = { ChainIn , Addr , CmpVal , SwapVal } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , NarrowVT , MMO ) ; SDValue Success = emitSETCC ( DAG , DL , AtomicOp . getValue ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , AtomicOp . getValue ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , Success ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , AtomicOp . getValue ( <NUM_LIT> ) ) ; return SDValue ( ) ; } int64_t BitSize = NarrowVT . getSizeInBits ( ) ; EVT PtrVT = Addr . getValueType ( ) ; SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , DL , WideVT ) , BitShift ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , CmpVal , SwapVal , BitShift , NegBitShift , DAG . getConstant ( BitSize , DL , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , NarrowVT , MMO ) ; SDValue Success = emitSETCC ( DAG , DL , AtomicOp . getValue ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , AtomicOp . getValue ( <NUM_LIT>


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling


<s> Imm |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; bool ValidNamed ; ( void ) <STR_LIT> ( STI . getFeatureBits ( ) ) . toString ( Imm , ValidNamed ) ; return ValidNamed ?


<s> return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn )


<s> rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == <NUM_LIT> ) return false ; if ( sort_regs ) for ( i = <NUM_LIT> ; i < nops - <NUM_LIT> ; i ++ ) for ( j = i + <NUM_LIT> ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( peep2_reg_dead_p ( nops , base_reg_rtx ) ) ; gcc_assert ( ldm_case == <NUM_LIT> || ldm_case == <NUM_LIT> ) ; write_back = TRUE ; } if ( ldm_case == <NUM_LIT> ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ <NUM_LIT> ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = <NUM_LIT> ; if ( ! TARGET_THUMB1 ) base_reg_rtx = newbase ; } for ( i = <NUM_LIT> ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * <NUM_LIT> ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , <NUM_LIT> ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * <NUM_LIT> : <NUM_LIT> ) ) ; return


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_MemBarrierOpt ) ; Op -> MBOpt . Val = Opt ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( (

CurVal >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> return ( __m512i ) __builtin_ia32_pmovzxbq512_mask ( ( __v16qi ) __A , ( __v8di )

_mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static DecodeStatus DecodeVecShiftR16ImmNarrow ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const


<s> STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( )


<s> EVT N00VT = N00 . getValueType ( ) ; if ( N00VT == N10 . getValueType ( ) && ( N00VT == <STR_LIT> || N00VT == <STR_LIT> ) && N00VT . getScalarSizeInBits ( ) == <NUM_LIT> * VT . getScalarSizeInBits ( ) ) { MVT MidVT = ( N00VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( MidVT . getVectorNumElements ( ) ) ; for ( size_t i = <NUM_LIT> ; i < Mask . size ( ) ; ++ i ) Mask [ i ] = i * <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( MidVT , dl , DAG . getNode ( <STR_LIT> , dl , MidVT , N00 ) , DAG . getNode ( <STR_LIT> , dl , MidVT , N10 ) , Mask ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N1 -> getOpcode ( ) != <STR_LIT> ) return SDValue


<s> Iter Filler ; RegDU . setCallerSaved ( * Slot ) ; if ( ! searchRange ( MBB , std :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Slot , Filler ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineBasicBlock * testMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * tailMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * blockMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( physSPReg ) . addReg ( FinalStackPtr ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) .


<s> OperandMatchResultTy parseFP64 ( OperandVector & Operands ) { return parseRegister ( Operands , RegFP , <STR_LIT> , FP64Reg


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const Function & F = MF . getFunction ( ) ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction


<s> for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) save_reg_mask |= ( <NUM_LIT> << reg ) ; if ( frame_pointer_needed ) save_reg_mask |= <NUM_LIT> << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && ( df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) || crtl -> uses_pic_offset_table ) ) save_reg_mask |= <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ; if ( IS_STACKALIGN ( func_type ) ) save_reg_mask |= <NUM_LIT> ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= <NUM_LIT> <<


<s> if ( SDValue R = performANDORCSELCombine ( N , DAG ) ) return R ; if ( ! VT . isVector ( ) || ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT . isScalableVector ( ) ) return performSVEAndCombine ( N , DCI ) ; if ( ! ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ) return SDValue ( ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! BVN ) return SDValue ( ) ; APInt DefBits ( VT . getSizeInBits ( ) ,


<s> if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . LookupSymbol ( Name ) ; if ( Sym ) return reportParseError ( <STR_LIT> ) ; Sym = getContext ( ) .


<s> } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupSetCC ( ) ) ; addPass ( create<ISA_LIT>OptimizeLEAs (


<s> const MCExpr * getImm ( ) const { assert ( Kind == KindImm && <STR_LIT> ) ; return


<s> if ( Count == <NUM_LIT> ) return nullptr ; if ( Count == <NUM_LIT> ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return nullptr ; if ( VT == <STR_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) { auto * MaskN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( MaskN -> getZExtValue ( ) != RISBG . Mask ) { SDValue NewMask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>InstructionSelector :: tryOptCompareBranchFedByICmp ( MachineInstr & I , MachineInstr & ICmp , MachineIRBuilder & MIB ) const { assert ( ICmp . getOpcode ( ) == TargetOpcode :: G_ICMP ) ; assert ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND ) ; if ( ! ProduceNonFlagSettingCondBr ) return false ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( ICmp . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = ICmp . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = ICmp . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getIConstantVRegValWithLookThrough ( RHS , MRI ) ; MachineInstr * AndInst = getOpcodeDef ( TargetOpcode :: G_AND , LHS , MRI ) ; if ( VRegAndVal && ! AndInst ) { int64_t C = VRegAndVal -> Value . getSExtValue ( ) ; if ( C == - <NUM_LIT> && Pred == CmpInst :: ICMP_SGT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , false , DestMBB , MIB ) ; I . eraseFromParent


<s> unsigned NumFixedFPRs = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ I ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( <STR_LIT> [ I ] ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset + Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI


<s> if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { <ISA_LIT>ArchVersion = V7A ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { <ISA_LIT>ArchVersion = V7M ; <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { <ISA_LIT>ArchVersion = V6 ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) { <ISA_LIT>ArchVersion = V6T2 ; <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; <ISA_LIT>ArchFeature = <STR_LIT> ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) { <ISA_LIT>ArchVersion = V5TE ; <ISA_LIT>ArchFeature =


<s> bool <ISA_LIT>SEFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CHERICFI && STI . isCheri ( ) && ! STI . getABI ( ) . IsCheriPureCap ( ) ) for ( auto & I : CSI ) if ( I . getReg ( ) == <STR_LIT> ) { CSI . push_back ( CalleeSavedInfo ( <STR_LIT> , <NUM_LIT> ) ) ; break ; } return false


<s> MCELFStreamer :: EmitInstruction ( Inst , STI ) ; <ISA_LIT>BranchTargetAligner BTA ; unsigned Opcode = Inst . getOpcode ( ) ; if ( BTA . needsSpecialAlignment ( STI . getCPU ( ) , Opcode ) ) { unsigned BA = BTA . getBranchTargetAlignment


<s>
Operands
[
<NUM_LIT>
]
=
<STR_LIT>
(
Repl
,
IDLoc
)
;
}
bool
WasOriginallyInvalidOperand
=
false
;
unsigned
OrigErrorInfo
;
MCInst
Inst
;
switch
(
MatchInstructionImpl
(
Operands
,
Inst
,
OrigErrorInfo
,
isParsingIntelSyntax
(
)
)
)
{
default
:
break
;
case
Match_Success
:
while
(
processInstruction
(
Inst
,
Operands
)
)
;
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
case
Match_MissingFeature
:
Error
(
IDLoc
,
<STR_LIT>
)
;
return
true
;
case
Match_ConversionFail
:
return
Error
(
IDLoc
,
<STR_LIT>
)
;
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
unsigned
ErrorInfoIgnore
;
unsigned
Match1
,
Match2
,
Match3
,
Match4
;
Match1
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match2
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match3
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match4
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Op
->
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
(
Match1
==
Match_Success
)
+
(
Match2
==
Match_Success
)
+
(
Match3
==
Match_Success
)
+
(
Match4
==
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
Match1
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match2
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match3
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match4
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned DivOp = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Div = DAG . getNode ( DivOp , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , VT , Div


<s> if ( RegNo > <NUM_LIT> || ( RegNo & <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; RegNo >>= <NUM_LIT> ; unsigned Register = QPRDecoderTable [ RegNo


<s> bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) )


<s> input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss ( value , value , input ) ) ; else emit_insn ( gen_sse2_movsd ( value , value , input ) ) ; } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31


<s> return __builtin_mve_vmaxvq_uv8hi ( __a ,


<s> if ( Converted . second ) Converted . first -> second . ShouldConvert = shouldConvertImpl ( & C ) ; return Converted . first ->


<s> return ( __m64 ) __builtin_ia32_pfsub ( ( __v2sf ) __A , (


<s> sparc_leaf_function_p = optimize > <NUM_LIT> && leaf_function_p ( ) && only_leaf_regs_used ( ) ; actual_fsize = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; sparc_prologue_data_valid_p = true ; if ( sparc_leaf_function_p ) { frame_base_reg = stack_pointer_rtx ; frame_base_offset = actual_fsize + SPARC_STACK_BIAS ; } else { frame_base_reg = hard_frame_pointer_rtx ; frame_base_offset = SPARC_STACK_BIAS ; } if ( actual_fsize == <NUM_LIT> ) ; else if ( sparc_leaf_function_p ) { if ( actual_fsize <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= <NUM_LIT> ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; insn = emit_insn ( gen_stack_pointer_inc ( reg ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( GEN_INT ( - actual_fsize ) ) , REG_NOTES ( insn ) ) ; } RTX_FRAME_RELATED_P ( insn )


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) SavedRegs .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn )


<s> for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI . getDebugLoc ( ) ; Register Dst = MI . getOperand ( <NUM_LIT>


<s> static MCStreamer * createELFStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) , false , ( T . getArch ( ) == Triple :: thumb || T . getArch ( )

== Triple :: thumbeb ) , T . isAndroid ( ) ) ;


<s> case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> && ! isDarwin ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , PB , Ctx ) ; } switch ( access


<s> SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; } Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> - ( <NUM_LIT> - BitNo ) , dl , <STR_LIT> ) ) ; Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( InvertBit ) Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return Flags


<s> if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; SpillSlotOffset -= SlotSize ; } Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ]


<s> static VEC ( int , heap ) * funcdef_nos ; static void output_deferred_profile_counters ( void ) { unsigned int i ; int align , n ; if ( VEC_empty ( int , funcdef_nos ) ) return ; data_section ( ) ; align = MIN (


<s> SDNode * ABDNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; unsigned IID = getIntrinsicID ( ABDNode ) ; if ( IID == <STR_LIT> || IID == <STR_LIT> ) { SDValue NewABD = tryCombineLongOpWithDup ( IID , ABDNode , DCI , DAG ) ; if ( ! NewABD . getNode ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , NewABD ) ; } } if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType (


<s> return GET_CODE ( p ) == SET && arith_reg_dest ( XEXP ( p , <NUM_LIT> ) , SImode ) && negt_reg_operand ( XEXP ( p ,

<NUM_LIT> ) , VOIDmode ) ? XEXP ( p , <NUM_LIT> ) : NULL ;


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm12Operand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; unsigned OffImm = MO2 . getImm ( ) ; if ( OffImm ) O


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) { SDValue Op0 = ShAmt . getOperand ( <NUM_LIT> ) ; Op0 = DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , <STR_LIT> , Op0 ) ; ShAmt = getShuffleVectorZeroOrUndef ( Op0 , <NUM_LIT> , true , & Subtarget , DAG


<s> void setFeatureBits ( uint64_t Feature , StringRef FeatureString ) { if ( ! ( getSTI ( ) . getFeatureBits ( ) [ Feature ] ) ) { MCSubtargetInfo & STI = copySTI ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ; AssemblerOptions . back ( ) -> setFeatures ( STI


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg ) ; else if ( DestRC == <STR_LIT> ) BuildMI ( MBB , I , DL

, get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;


<s> MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * WaterBB ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> )


<s> if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Ops ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( ) ) Op = & Op1 ; if ( Op && Op -> isReg ( ) && Op -> getReg ( ) == Op2 . getReg ( ) && Coef > <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( Coef + <NUM_LIT> ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg < <NUM_LIT> ) return None ; else if ( dwarfReg < <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_breg0 + dwarfReg ) ; Ops . push_back ( <NUM_LIT> ) ; }


<s> bool <ISA_LIT>Subtarget :: IsLegalToCallImmediateAddr ( const TargetMachine & TM ) const { if ( In64BitMode || isTargetWin32 (


<s> if ( ! IsSP ( MI -> getOperand ( <NUM_LIT> )


<s> bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & <STR_LIT> ; return & <STR_LIT>


<s> return true ; case 'w' : Reg = getWRegFromXReg ( Reg ) ; break ; case 'x' : Reg = getXRegFromWReg ( Reg )


<s> while ( true ) { MachineInstr * MI = MRI -> getVRegDef ( SrcReg ) ; if ( ! MI -> isCopyLike ( ) ) return SrcReg ; unsigned CopySrcReg ; if ( MI -> isCopy ( ) ) CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg


<s> bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag , GV ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOLoFlag ) ; SDValue Ptr = LowerLabelRef ( GAHi , GALo , isPIC , DAG ) ; if ( MOHiFlag & <STR_LIT> ) Ptr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Ptr

, MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool isMachineVerifierClean ( ) const override { return


<s> setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V4T : case <STR_LIT> :: <ISA_LIT>V5T : case <STR_LIT> :: <ISA_LIT>V5TE : case <STR_LIT> :: <ISA_LIT>V6 : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6T2 : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6K : case <STR_LIT> :: <ISA_LIT>V6KZ : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6M : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7A : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7R : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7EM : case <STR_LIT> :: <ISA_LIT>V7M : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V8A : case <STR_LIT> :: <ISA_LIT>V8_1A : case <STR_LIT> :: <ISA_LIT>V8_2A : case <STR_LIT> :: <ISA_LIT>V8_3A : case <STR_LIT> :: <ISA_LIT>V8_4A : case <STR_LIT> :: <ISA_LIT>V8_5A : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V8MBaseline : case <STR_LIT> :: <ISA_LIT>V8MMainline : setAttributeItem ( THUMB_ISA_use , AllowThumbDerived , false ) ; setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; break ; case <STR_LIT> :: IWMMXT : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv1 , false ) ; break ; case <STR_LIT> :: IWMMXT2 : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv2 ,


<s> RegisterMCAsmInfoFn Y ( The<ISA_LIT>elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>Target , create<ISA_LIT>AsmStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackendEB32 ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget , create<ISA_LIT>AsmBackendEL32 ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCSubtargetInfo


<s> NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NeedsWinCFI ) { auto SEH = std :: next ( MBBI ) ; if ( <ISA_LIT>InstrInfo :: isSEHInstruction ( * SEH ) ) SEH -> eraseFromParent ( ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( CSStackSizeInc % Scale == <NUM_LIT> )


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue ImmN ; IsUnary = false ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodeSHUFPMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : DecodeUNPCKHMask ( VT , Mask ) ; break ; case <STR_LIT> : DecodeUNPCKLMask ( VT , Mask ) ; break ; case <STR_LIT> : DecodeMOVHLPSMask ( NumElems , Mask ) ; break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , Mask ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePALIGNRMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue (


<s> static DecodeStatus DecodeBranchTarget7MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> return ( __m128i ) __builtin_ia32_pmovsxbw128_mask ( ( __v16qi ) __A , ( __v8hi ) __W , (


<s> if ( Op . isImm ( ) ) O << Op . getImm ( ) ; else { assert ( Op . isExpr ( ) &&


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_PtrReg ) ; Op -> Reg . RegNum


<s> } SmallVectorImpl < PredicatedMI > & Insts = Block . getInsts ( ) ; for ( auto & PredMI : Insts ) { if ( PredMI . Predicates . count ( VCTP ) || isVCTP ( PredMI . MI ) || VCMPOpcodeToVPT ( PredMI . MI -> getOpcode ( ) ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PredMI . MI << <STR_LIT> ; for ( auto * MI : PredMI . Predicates ) dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( ! ValidateLiveOuts ( ) ) return false ; Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = StartInsertPt -> getParent ( ) ; if ( ! RDA . isReachingDefLiveOut ( StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( StartInsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv8hf ( ( const __builtin_aarch64_simd_hf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregciv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregciv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregciv8hf ( __o , <NUM_LIT> ) ; return ret


<s> EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDLoc DL ( N0 ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > DUPMask ( CCVT . getVectorNumElements ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getVectorShuffle ( CCVT , DL , SetCC , SetCC ,


<s> bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = <STR_LIT> ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr ->


<s> bool <ISA_LIT>InstrInfo :: isZeroImm ( const MachineOperand & op ) const { return op . isImm ( ) && op .


<s> unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && static_cast < unsigned > ( M [ i ] ) != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && static_cast < unsigned > ( M [ i + <NUM_LIT> ] ) != Idx + NumElts ) ) return false ; Idx +=


<s> MachineOperand & CallTarget = MI . getOperand ( <NUM_LIT> ) ; assert ( ( CallTarget . isGlobal ( ) || CallTarget . isReg ( ) ) && <STR_LIT> ) ; unsigned Opc = CallTarget . isGlobal ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * Call = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; Call -> addOperand ( CallTarget )


<s> unsigned DestReg1 = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg1 ) . addConstantPoolIndex ( Idx ) ) ; Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg1 ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ; Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) { GlobalBaseReg = MRI . createVirtualRegister ( TLI . getRegClassFor ( VT ) ) ; AFI -> setGlobalBaseReg ( GlobalBaseReg ) ; } unsigned DestReg2 = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg2 ) . addReg ( DestReg1 ) . addReg ( GlobalBaseReg ) ; if ( ! UseGOTOFF ) MIB . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB )


<s> static inline unsigned getMemExtendImm ( <STR_LIT> ET , bool DoShift ) { return ( unsigned ( ET ) << <NUM_LIT> )


<s> return get<ISA_LIT>SubSuperRegister ( ScratchReg


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X =


<s> if ( Desc . TSFlags & <STR_LIT> ) { if ( isVRRegister ( Reg ) ) Reg = <STR_LIT> +


<s> unsigned cpuSubTypeFromString ( StringRef CPUName ) { unsigned Mcpu = StringSwitch < unsigned > ( CPUName ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_601 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_602 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_603 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_750 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_7400 ) . Cases ( <STR_LIT> ,

<STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_7450 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_970 ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_POWERPC_ALL ) . Default ( MachO :: CPU_SUBTYPE_POWERPC_ALL ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateShiftedImm ( const MCExpr * Val , unsigned ShiftAmount , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_ShiftedImm , Ctx ) ; Op -> ShiftedImm . Val = Val ; Op -> ShiftedImm . ShiftAmount = ShiftAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> break ; } int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast <


<s> if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs ; return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) )

) << getRegisterName ( MO1 . getReg ( ) ) ;


<s> setLeastSignificantFirst ( VRegs ) ; if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex ) ) return false ; return true


<s> MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_AVX512 ( Op , DAG ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT>


<s> case <STR_LIT> : SwapVector [ VecIdx ] . IsLoad = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsLoad = <NUM_LIT> ; SwapVector [ VecIdx ] . IsSwap = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsLoad = <NUM_LIT> ; SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; break ; case <STR_LIT> : SwapVector [ VecIdx ] . IsStore = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsStore = <NUM_LIT> ; SwapVector [ VecIdx ] . IsSwap = <NUM_LIT> ; break ; case <STR_LIT> : if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; else if ( isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; break ; case <STR_LIT> : { if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; else if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_COPYWIDEN ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_SPLAT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> virtual StringRef getPassName ( ) const override { return <STR_LIT>


<s> SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ; Res = DAG . getNode ( <STR_LIT> , dl


<s> void * Result = SemaCallback -> LookupInlineAsmIdentifier ( LineBuf , Info , IsUnevaluatedOperand ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; assert ( End . getPointer ( ) <= EndPtr && <STR_LIT> ) ; if ( End . getPointer ( ) == EndPtr ) break ; } Identifier = LineBuf ; if ( ! Result ) { StringRef InternalName = SemaCallback -> LookupInlineAsmLabel ( Identifier , getSourceManager ( ) , Loc , false ) ; assert ( InternalName . size ( ) && <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Label , Loc , Identifier . size ( ) , InternalName ) ) ; } MCSymbol * Sym = getContext ( ) .


<s> icode = bdesc [ fcode ] . icode ; type = bdesc [ fcode ] . builtin_type ; break ; } fcode -= m -> size ; } if ( bdesc == NULL ) return <NUM_LIT> ; switch ( type ) { case MIPS_BUILTIN_DIRECT : return mips_expand_builtin_direct ( icode , target , arglist , true ) ; case MIPS_BUILTIN_DIRECT_NO_TARGET : return mips_expand_builtin_direct ( icode , target , arglist , false ) ; case MIPS_BUILTIN_MOVT : case MIPS_BUILTIN_MOVF : return mips_expand_builtin_movtf ( type , icode , bdesc [ fcode ] . cond , target , arglist ) ; case MIPS_BUILTIN_CMP_ANY : case MIPS_BUILTIN_CMP_ALL : case MIPS_BUILTIN_CMP_UPPER : case MIPS_BUILTIN_CMP_LOWER : case MIPS_BUILTIN_CMP_SINGLE : return mips_expand_builtin_compare ( type , icode , bdesc [ fcode ] . cond , target , arglist ) ; case MIPS_BUILTIN_BPOSGE32 : return mips_expand_builtin_bposge ( type , target ) ; default : return <NUM_LIT>


<s> void addProcIFlagsOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( unsigned ( getProcIFlags ( ) ) )


<s> if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI ) ) return Result ; if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov )


<s> MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst ,


<s> T . toVector ( CommentToEmit ) ; if ( EOL ) CommentToEmit . push_back


<s> F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB )


<s> if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; Register DestReg = createResultReg ( &


<s> case llvm :: ELF :: R_<ISA_LIT>_64_GOTPCREL : if ( rsym -> reserved ( ) & ReserveGOT ) return ; if ( ! getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) helper_GOT_init ( pReloc , true , * this ) ; else helper_GOT_init ( pReloc , false , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveGOT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PLT32 : if ( rsym -> reserved ( ) & ReservePLT ) return ; if ( getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) return ; if ( rsym -> isDefine ( ) && ! rsym -> isDyn ( ) && ! getTarget ( ) . isSymbolPreemptible ( * rsym ) ) { return ; } helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PC32 : case llvm :: ELF :: R_<ISA_LIT>_64_PC16 : case llvm :: ELF :: R_<ISA_LIT>_64_PC8 : if ( getTarget ( ) . symbolNeedsPLT ( * rsym ) && LinkerConfig :: DynObj != config ( ) . codeGenType ( ) ) { if ( ! ( rsym -> reserved ( ) & ReservePLT ) ) { helper_PLT_init ( pReloc , * this


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; uint64_t Value = CE -> getValue ( ) ; unsigned Elem = Value & <NUM_LIT> ; if ( Elem >= <NUM_LIT> ) Elem = ( Elem >> <NUM_LIT> ) | <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm


<s> if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; case <STR_LIT> : { const MachineInstr & Copy = * MI ; MachineBasicBlock :: iterator AND ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ; if ( AND == MI -> getParent ( ) -> end ( ) ) return false ; MI = AND ; return isSuitableForMask ( MI , Copy . getOperand ( <NUM_LIT> ) . getReg (


<s> assert ( N == <NUM_LIT> || N == <NUM_LIT> ) ; uint64_t Result ; unsigned bit6 = slice ( byte , <NUM_LIT> , <NUM_LIT> ) ; if ( N == <NUM_LIT> ) { Result = slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( bit6 ) Result |= <NUM_LIT> << <NUM_LIT> ; else Result |= <NUM_LIT> << <NUM_LIT> ; }


<s> bool requiresRegisterScavenging ( const MachineFunction & MF )


<s> if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( ! CALL_P ( insn ) ) continue ; pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , <NUM_LIT> ) > <NUM_LIT> ) ; call = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; unspec = XEXP ( call , <NUM_LIT> ) ; if ( GET_CODE ( unspec ) != UNSPEC || XINT ( unspec , <NUM_LIT> ) != UNSPEC_NONSECURE_MEM ) continue ; bitmap_clear ( to_clear_bitmap ) ; bitmap_set_range ( to_clear_bitmap , R0_REGNUM , max_int_regno - R0_REGNUM + <NUM_LIT> ) ; if ( ! lazy_fpclear ) { auto_sbitmap float_bitmap ( maxregno + <NUM_LIT> ) ; bitmap_clear ( float_bitmap ) ; bitmap_set_range ( float_bitmap , FIRST_VFP_REGNUM , max_fp_regno - FIRST_VFP_REGNUM + <NUM_LIT> ) ; bitmap_ior ( to_clear_bitmap , to_clear_bitmap , float_bitmap ) ; } address = RTVEC_ELT ( XVEC ( unspec , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( MEM_P ( address ) ) ; gcc_assert ( REG_P ( XEXP ( address , <NUM_LIT> ) ) ) ; address_regnum = REGNO ( XEXP ( address , <NUM_LIT> ) ) ; if ( address_regnum <= max_int_regno ) bitmap_clear_bit ( to_clear_bitmap , address_regnum ) ; set_block_for_insn ( insn , bb ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; start_sequence ( ) ; emit_insn ( gen_blockage ( ) ) ; fntype = TREE_TYPE ( MEM_EXPR ( address ) ) ; arm_init_cumulative_args ( & args_so_far_v , fntype , NULL_RTX , NULL_TREE ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; uint64_t to_clear_args_mask ; if ( VOID_TYPE_P ( arg_type ) )


<s> SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , NULL ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , RetTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , Callee , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult .


<s> gimple * ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = <NUM_LIT> ; unsigned int actual_versions = <NUM_LIT> ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= <NUM_LIT> ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - <NUM_LIT> ) ) ; default_decl = ( * fndecls ) [ <NUM_LIT> ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = <NUM_LIT> ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority =


<s> is_dest = <NUM_LIT> ; break ; case CALL : used |= <NUM_LIT> ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return


<s> auto __first2 = LR -> liveInstrs . begin ( ) ; while ( __first1 != liveInstrs . end ( ) && __first2 != LR -> liveInstrs . end ( ) ) if ( * __first1 < * __first2 ) ++ __first1 ; else if ( * __first2 <


<s> while ( ! Worklist . empty ( ) ) { MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; if ( Visited . count ( MBB ) ) continue ; for ( MachineInstr & MI : * MBB ) { if ( ! IsInvalidTPInstruction ( MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB = BuildMI ( * PreHeader , PreHeader -> getFirstTerminator ( ) , LoopStart -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) ; LoopStart -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; RevertWhileLoopStartLR ( LoopStart , TII , <STR_LIT> , true ) ; return MIB ; } Visited . insert ( MBB )


<s> void <ISA_LIT>RegisterSema :: insertExternalWrapperAsm ( BasicBlock * WrapperBB , Function * ExtFn ) { DCIRBuilder WBuilder ( WrapperBB ) ; Type * ArgTypes [ <NUM_LIT> ] = { RegSetType -> getPointerTo ( ) , ExtFn -> getType ( ) } ; Function * EWFn = cast < Function > ( ExtFn -> getParent ( ) -> getOrInsertFunction ( <STR_LIT> , FunctionType

:: get ( Type :: getVoidTy ( * Ctx ) , ArgTypes , false ) ) ) ;


<s> if ( SDValue C = IsCMPZCSINC ( N , Cond ) ) if (


<s> void llvm :: addPredicatedMveVpredROp ( MachineInstrBuilder & MIB , unsigned Cond , unsigned Inactive ) { addPredicatedMveVpredNOp ( MIB , Cond ) ; MIB . addReg ( Inactive


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( JumpTarget . getImm ( ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI


<s> EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; SDValue Result = DAG . getNode ( <STR_LIT> ,


<s> uint64_t <ISA_LIT>GOTPLT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { GOTPLTEntry * got = & ( llvm :: cast < GOTPLTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += got -> size (


<s> tocrel_insn = DF_REF_INSN ( def_link -> ref ) ; break ; } gcc_assert ( tocrel_insn ) ; rtx base , offset ; rtx tocrel_expr = SET_SRC ( PATTERN ( tocrel_insn ) ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) gcc_unreachable ( ) ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; rtx const_vector = get_pool_constant ( base ) ; if ( GET_CODE ( const_vector ) == SYMBOL_REF ) const_vector = get_pool_constant ( const_vector ) ; gcc_assert ( GET_CODE ( const_vector ) == CONST_VECTOR ) ; unsigned int new_mask [ <NUM_LIT> ] , i , val ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { val = INTVAL ( XVECEXP ( const_vector , <NUM_LIT> , i ) ) ; if ( val < <NUM_LIT> ) new_mask [ i ] = ( val + <NUM_LIT> ) % <NUM_LIT> ; else new_mask [ i ] = ( ( val + <NUM_LIT> ) % <NUM_LIT> ) + <NUM_LIT> ; } rtx vals = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) XVECEXP ( vals , <NUM_LIT> , i ) = GEN_INT ( new_mask [ i ] ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( vals , <NUM_LIT> ) ) ; rtx new_mem = force_const_mem ( V16QImode , new_const_vector ) ; if ( ! REG_P ( XEXP ( new_mem , <NUM_LIT> ) ) ) { rtx base_reg = force_reg ( Pmode , XEXP ( new_mem , <NUM_LIT> ) ) ; XEXP ( new_mem , <NUM_LIT> ) = base_reg ; rtx_insn * force_insn = get_last_insn ( ) ; remove_insn ( force_insn ) ; rtx_insn * before_load_insn =


<s> Function :: const_arg_iterator FuncArg = Func . arg_begin ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) && ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_FixedArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , CCInfo . getInRegsParamsCount ( ) > <NUM_LIT> ) ; unsigned CurArgIdx = <NUM_LIT> ; CCInfo . rewindByValRegsInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) , InsIdx = <NUM_LIT> ; i != e ; ++ i , ++ InsIdx ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ InsIdx ] . isOrigArg ( ) ) { std :: advance ( FuncArg , Ins [ InsIdx ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ InsIdx ] . getOrigArgIndex ( ) ; } EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ InsIdx ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Ins [ InsIdx ] . isOrigArg ( ) && <STR_LIT> ) ; unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , FirstByValReg , LastByValReg , VA , CCInfo ) ; CCInfo . nextInRegsParam ( ) ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; Register ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; ArgValue = UnpackFromArgumentSlot ( ArgValue , VA , Ins [ InsIdx ] . ArgVT , DL , DAG ) ; if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( ABI . IsO32 ( ) && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { assert ( VA . needsCustom


<s> if ( isLoad ) { status = DecodeRD ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( isImm ) MI . addOperand ( MCOperand :: createImm ( simm13 ) ) ; else { status = DecodeIntRegsRegisterClass ( MI , rs2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } if ( hasAsi ) MI . addOperand ( MCOperand :: createImm


<s> break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; Expr = <ISA_LIT>MCExpr :: create (


<s> Changed = true ; if ( ! DisableDelaySlotFiller && ( TM . getOptLevel ( ) != CodeGenOpt :: None ) ) { bool Filled = false ; if ( <ISA_LIT>CompactBranchPolicy . getValue ( ) != CB_Always || ! TII -> getEquivalentCompactForm ( I ) ) { if ( searchBackward ( MBB , I ) ) { Filled = true ; } else if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) { Filled = true ; } } else if ( searchForward ( MBB , I ) ) { Filled = true ; } } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> GetInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI


<s> <ISA_LIT>VSXSwapRemoval ( ) : MachineFunctionPass ( ID


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; if ( RI -> isSubRegisterEq ( Rn , Rt2 ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> )


<s> MemRefBegin += <STR_LIT> ( Desc ) ; MachineOperand & BaseMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseMO . isReg ( ) ) return false ; BaseReg = BaseMO . getReg ( ) ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; return true


<s> } u ; u . v = a ; return u . f [ pos


<s> llvm :: cast < GOTPLTEntry > ( * it ++ ) . setValue ( <NUM_LIT> ) ; llvm :: cast < GOTPLTEntry > ( * it ++ ) . setValue ( <NUM_LIT> ) ; for ( ; it != end ( ) ; ++ it ) llvm :: cast

< GOTPLTEntry > ( * it ) . setValue ( pltAddr ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printCPSIMod ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo


<s> if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( ! FlagsVal ) FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex (


<s> return ( __m256i ) __builtin_ia32_broadcasti32x2_256_mask ( ( __v4si ) __A , ( __v8si ) _mm256_undefined_si256 ( ) , (


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtt_roundsd_si32 ( __m128d __A , const int __R ) { return ( int ) __builtin_ia32_vcvttsd2si32 ( (


<s> Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( Ty -> isBFloatTy ( ) || ! isElementTypeLegalForScalableVector ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin


<s> static DecodeStatus DecodeFGR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> SDValue DataToTruncate = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MVT VT = DataToTruncate . getSimpleValueType ( ) ; MVT SVT = <STR_LIT> ( ElementType , VT . getVectorNumElements ( ) ) ; if ( isAllOnes ( Mask ) ) return DAG . getTruncStore ( Chain , dl , DataToTruncate , Addr , MachinePointerInfo ( ) , SVT , false , false , SVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType ( ) .


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> && Subtarget . hasInt256 ( ) ) ) ) return SDValue ( ) ; assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) Mask = Mask . getOperand ( <NUM_LIT> ) ; if ( X . getOpcode ( ) == <STR_LIT> ) X = X . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> ) Y = Y . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType


<s> return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) + ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT>


<s> __vector __m64 result ; temp = ( __v4sf ) vec_splat ( ( __vector long long ) __A , <NUM_LIT> ) ; rounded = vec_rint (


<s> AU . setPreservesCFG ( ) ; AU . addPreservedID (


<s> static int sparc_issue_rate ( void ) { switch ( sparc_cpu ) { case PROCESSOR_NIAGARA : case PROCESSOR_NIAGARA2 : case PROCESSOR_NIAGARA3 : default : return <NUM_LIT> ; case PROCESSOR_NIAGARA4 : case PROCESSOR_NIAGARA7 : case PROCESSOR_V9 : return <NUM_LIT> ; case PROCESSOR_SUPERSPARC : return <NUM_LIT> ; case PROCESSOR_HYPERSPARC


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! get<ISA_LIT>Subtarget ( ) . isThumb1Only ( ) ) { if ( get<ISA_LIT>Subtarget ( ) . restrictIT ( ) && ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & IfConverterID


<s> return createELFStreamer ( Context , MAB ,


<s> emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case LE : case LEU : paired_emit_vector_compare ( GE , dest , op0 , op1 , cc_op1 , cc_op0 ) ; return ; case GT : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case EQ : tmp1 = gen_reg_rtx ( V2SFmode ) ; max = gen_reg_rtx ( V2SFmode ) ; min = gen_reg_rtx ( V2SFmode ) ; gen_reg_rtx ( V2SFmode ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( max , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op1 , cc_op0 ) ) ; emit_insn ( gen_selv2sf4 ( min , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp1 , min , max ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp1 , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case NE : paired_emit_vector_compare ( EQ , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLE : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLT : paired_emit_vector_compare ( LT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGE : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGT : paired_emit_vector_compare ( GT , dest , op1


<s> if ( ! Subtarget . isSVR4ABI ( ) || ! Subtarget . is<ISA_LIT>64 ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; auto Attr = Caller -> getFnAttribute ( <STR_LIT> ) ; if ( Attr . getValueAsString ( ) == <STR_LIT> ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg