<s> for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Mode == MULU8 ? <STR_LIT> : <STR_LIT> , DL , ResVT , Mul ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL


<s> if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . hard_fp_offset - cfun -> machine -> frame . locals_offset ; } if ( to == STACK_POINTER_REGNUM ) { if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . frame_size - cfun -> machine -> frame . locals_offset ; } return cfun -> machine ->


<s> const <ISA_LIT>MCSymbolRefExpr * <ISA_LIT>MCSymbolRefExpr :: Create ( VariantKind Kind , const MCSymbol * Symbol , int Offset , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCSymbolRefExpr ( Kind


<s> tmp = ( __v16qu ) _mm_loadu_si128 ( p ) ; mask = ( __v16qu ) vec_cmpgt ( ( __v16qu ) __B , ( __v16qu ) hibit ) ; tmp = vec_sel ( tmp , ( __v16qu


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS


<s> return ( __m128d ) __builtin_ia32_cvtdq2pd ( ( __v4si


<s> const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( VT == <STR_LIT> && ! FullFP16 ) { LHS = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , LHS } ) ; RHS = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { LHS . getValue ( <NUM_LIT> ) , RHS } ) ; Chain = RHS . getValue ( <NUM_LIT> ) ; VT = <STR_LIT> ; } unsigned Opcode = IsSignaling ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , dl , { VT , <STR_LIT> } , { Chain ,


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , <NUM_LIT> ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_mem ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_reg )


<s> static void sh_setup_incoming_varargs ( CUMULATIVE_ARGS * ca , enum machine_mode mode , tree type , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( current_function_stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs ,


<s> } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned char Value = MI -> getOperand ( OpNo ) . getImm (


<s> } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; } else


<s> return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc ,


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType )


<s> bool <ISA_LIT>PreAllocLoadStoreOpt :: RescheduleLoadStoreInstrs ( MachineBasicBlock * MBB ) { bool RetVal = false ; DenseMap < MachineInstr * , unsigned > MI2LocMap ; DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > Base2LdsMap ; DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > Base2StsMap ; SmallVector < unsigned , <NUM_LIT> > LdBases ; SmallVector < unsigned , <NUM_LIT> > StBases ; unsigned Loc = <NUM_LIT> ; MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MachineBasicBlock :: iterator E = MBB -> end ( ) ; while ( MBBI != E ) { for ( ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = MBBI ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . isCall ( ) || MCID . isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI -> isDebugValue ( ) ) MI2LocMap [ MI ] = ++ Loc ; if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( llvm :: getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI -> getOpcode ( ) ; bool isLd = isi32Load ( Opc ) || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; if ( isLd ) { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2LdsMap .


<s> const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; setAction ( { G_IMPLICIT_DEF , s64 } , Legal ) ; setAction ( { G_IMPLICIT_DEF , s128 } , Legal ) ; setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } setAction ( { G_ICMP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR , G_SDIV } ) . legalFor ( { s8 , s16 , s32 , s64 } ) . clampScalar ( <NUM_LIT> , s8 , s64 ) ; setAction ( { G_MERGE_VALUES , s128 } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , s128 } ,


<s> inline vector signed char vec_vcmpgtub ( vector unsigned char a1 , vector unsigned char a2 ) { return ( vector signed char ) __builtin_altivec_vcmpgtub ( ( vector signed char ) a1 ,


<s> temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s8 ( val . val [ <NUM_LIT> ] , vcreate_s8 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> uint32_t CPUType = cantFail ( MachO :: getCPUType ( TT ) ) ; uint32_t CPUSubType = cantFail ( MachO :: getCPUSubType ( TT ) ) ; return create<ISA_LIT>MachObjectWriter ( TT . isArch64Bit (


<s> if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetFromSPToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; int64_t OffsetFromFPToSVEArea = - AFI -> getCalleeSaveBaseToFrameRecordOffset ( ) ; StackOffset FPOffset = StackOffset ( OffsetFromFPToSVEArea , <STR_LIT> ) + StackOffset ( ObjectOffset , <STR_LIT> ) ; StackOffset SPOffset = SVEStackSize + StackOffset ( ObjectOffset , <STR_LIT> ) + StackOffset ( OffsetFromSPToSVEArea , <STR_LIT> ) ; if ( hasFP ( MF ) && ( SPOffset . getBytes ( ) || FPOffset . getScalableBytes ( ) < SPOffset . getScalableBytes ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR ) ) ScalableOffset = - SVEStackSize ; if ( ! UseFP && ( isFixed || isCSR ) )


<s> __builtin_neon_vst1v16qi ( ( __builtin_neon_qi * ) __a ,


<s> if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp + <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; break ; case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; break ; default : break ; } EmitSegmentOverridePrefix ( TSFlags , CurByte , MemOperand , MI , OS ) ; unsigned char LastByte = VEX_PP | ( VEX_L << <NUM_LIT> ) | ( VEX_4V << <NUM_LIT> ) ; if ( VEX_B && VEX_X && ! VEX_W && ! XOP && ( VEX_5M == <NUM_LIT> ) ) { EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitByte ( LastByte | ( VEX_R << <NUM_LIT> ) , CurByte , OS ) ; return ; } EmitByte ( XOP ? <NUM_LIT> : <NUM_LIT>


<s> if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg ( ) ) { DebugLoc DL ; NumPEReloadVSR ++ ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( CSI [ i ] . getDstReg ( ) , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } } if ( AtStart ) I = MBB .


<s> const <ISA_LIT>Subtarget * getST ( ) const { return ST


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>elTarget , create<ISA_LIT>DiagLineInfo ) ; mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>64elTarget ,


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerSymbolOperandDarwin ( const MachineOperand & MO


<s> if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return ( STI . useThumbBacktraces ( ) || STI

. isThumb ( ) ) ? <STR_LIT> : <STR_LIT> ;


) _senduipi ( unsigned long long __R ) {


<s> SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; if ( offset ==


<s> assert ( ( ! Reg || Reg == <STR_LIT> ) && <STR_LIT> ) ; if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ]


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) ) && MF .

getFunction ( ) . getCallingConv ( ) != CallingConv :: HiPE && ! MF . shouldSplitStack ( ) ;


<s> const Instruction * BBTerm = BB -> getTerminator ( ) ; if ( BBTerm -> getNumSuccessors ( ) != <NUM_LIT> ) return <STR_LIT> ; const BasicBlock * TBB = BBTerm -> getSuccessor ( <NUM_LIT> ) ; const BasicBlock * FBB = BBTerm -> getSuccessor ( <NUM_LIT> ) ; auto TProb = FuncInfo . BPI -> getEdgeProbability ( BB , TBB ) ; auto FProb = FuncInfo . BPI -> getEdgeProbability ( BB , FBB ) ; const uint32_t Threshold =


<s> if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair


<s> FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumbFunction ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( AFI -> isThumb2Function ( ) && FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } if ( RegInfo -> hasBasePointer ( MF ) ) { FrameReg = RegInfo -> getBaseRegister ( ) ; Offset -= SPAdj ; } return Offset


<s> ix86_first_cycle_multipass_data_t data = ix86_first_cycle_multipass_data ; gcc_assert ( data -> ifetch_block_n_insns <= core2i7_ifetch_block_max_insns ) ; data -> ifetch_block_len = <NUM_LIT> ; data -> ifetch_block_n_insns =


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; int Size ; if ( Desc . getSize ( ) == <NUM_LIT> || Desc . getSize (

) == <NUM_LIT> ) Size = Desc . getSize ( ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target (


<s> unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue CP = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , GOTFlag ) ; CP = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , CP ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , OFSTFlag ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , ValTy , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , ValTy , Load , Lo ) ; } return ResNode


<s> static const LdStNInstrDesc * getLdStNInstrDesc ( unsigned Opcode ) { unsigned Idx ; for ( Idx = <NUM_LIT> ; Idx != array_lengthof ( LdStNInstInfo ) ; ++ Idx ) if ( LdStNInstInfo [ Idx ] . Opcode == Opcode ) return


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode


<s> if ( tm . getTargetTriple ( ) . isOSAIX ( ) ) return new

<ISA_LIT>AIXAsmPrinter ( tm , std :: move ( Streamer ) ) ;


<s> switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X


<s> case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMULH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op ,


<s> OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction


<s> void <ISA_LIT>LongBranch :: splitMBB ( MachineBasicBlock * MBB ) { ReverseIter End = MBB -> rend ( ) ; ReverseIter LastBr = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; if ( ( LastBr == End ) || ( ! LastBr -> isConditionalBranch ( ) && ! LastBr -> isUnconditionalBranch ( ) ) ) return ; ReverseIter FirstBr = getNonDebugInstr ( std :: next ( LastBr ) , End ) ; if ( ( FirstBr == End ) || ( ! FirstBr -> isConditionalBranch ( ) && ! FirstBr -> isUnconditionalBranch ( ) ) ) return ; assert ( ! FirstBr -> isIndirectBranch ( ) &&


<s> Value * <ISA_LIT>IREmitter :: visitMUL_IMM ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO . getReg


<s> tree decl = TYPE_NAME ( * node ) ; if ( decl ) { DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; DECL_VISIBILITY_SPECIFIED ( decl


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: LowerGETPCXAndEmitMCInsts ( const MachineInstr * MI , const MCSubtargetInfo & STI ) { MCSymbol * GOTLabel = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; MCOperand MCRegOP = MCOperand :: createReg ( MO . getReg ( ) ) ; if ( ! isPositionIndependent ( ) ) { switch ( TM . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , MCRegOP , OutContext , STI ) ; break ; case CodeModel :: Medium : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand lo = create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , GOTLabel , OutContext ) ; EmitOR ( * OutStreamer , MCRegOP , lo , MCRegOP , STI


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo


<s> if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; for ( Function :: const_arg_iterator i = CallerF -> arg_begin ( ) , e = CallerF -> arg_end ( ) ; i != e ; ++ i ) if ( i -> hasByValAttr ( ) ) return false ; if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple TT ( getTargetMachine ( ) . getTargetTriple ( ) ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CallerCC , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) ; for ( auto * V : Sources ) V -> dump ( ) ; for ( auto * I : NewInsts ) I -> dump ( ) ; for ( auto * V : Visited ) { if ( ! Sources . count ( V ) ) V -> dump ( ) ; }


<s> MCSym = OutContext . GetOrCreateSymbol ( OS . str ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr


<s> Inst . addOperand ( MCOperand :: CreateExpr (


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , <STR_LIT> ) ; Register SrcLoReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcHiReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , <STR_LIT> ) ; Register DestLoReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , II , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestHiReg ) ; Offset += <NUM_LIT>


<s> else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base_Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return false ; getAddressOperands ( AM , SDLoc ( N ) , Base , Scale , Index


<s> OperandMatchResultTy ResTy = matchAnyRegisterNameWithoutDollar ( Operands , Identifier , S ) ; return ResTy ; } else if ( Token . is ( AsmToken :: Integer ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } DEBUG ( dbgs ( ) << Parser . getTok ( ) . getKind ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch


<s> __builtin_neon_vst3v4hi ( ( __builtin_neon_hi * ) __a ,


<s> int32x4_t result = vcombine_s32 ( a , vcreate_s32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ; return result


<s> else Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ABI . IsN64 ( ) || ABI . IsN32 ( ) ) Ret += <STR_LIT> ; else Ret +=


<s> unsigned BasePtr ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT>


<s> static bool f64AssignAPCS ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , CCState & State , bool CanFail ) { static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT>


<s> return ( __m128d ) __builtin_ia32_vfmaddsubpd128_maskz ( ( __v2df ) __A , ( __v2df ) __B , (


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNo<ISA_LIT>3D (


<s> if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; else return <NUM_LIT> + ( regno - FIRST_VFP_REGNUM ) / <NUM_LIT> ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return <NUM_LIT> + regno -


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( Imm ==


<s> bool <ISA_LIT>InstrInfo :: isLdStPairSuppressed ( const MachineInstr * MI ) const { static_assert ( MOSuppressPair < ( <NUM_LIT> << MachineMemOperand :: MOTargetNumBits ) , <STR_LIT> ) ; for ( auto * MM : MI -> memoperands ( ) ) { if ( MM -> getFlags ( ) & ( MOSuppressPair

<< MachineMemOperand :: MOTargetStartBit ) ) {


<s> OperandMatchResultTy parseBDLAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , BDLMem ,


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS , is64Bit ( ) , OSABI


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( WriteBack ) { if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> for ( const MachineInstr * MI : D . getArgs ( ) ) { MInstToMCSymbol :: iterator LabelIt = LOHInstToLabel . find ( MI ) ; assert ( LabelIt != LOHInstToLabel . end (


<s> void <ISA_LIT>CodeEmitter :: emitGlobalAddress ( const GlobalValue * GV , unsigned


<s> static void adjust_splat ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; rtx unspec = XEXP ( body , <NUM_LIT> ) ; int half_elts = GET_MODE_NUNITS ( GET_MODE ( unspec ) ) >> <NUM_LIT> ; int lane = INTVAL ( XVECEXP ( unspec , <NUM_LIT> ,


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand (


<s> int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return


<s> SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl ,


<s> if ( ix86_lam_type == lam_u57 ) { unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_TAG_SIZE ) - <NUM_LIT> ; emit_insn ( gen_andqi3 ( tag , tag , GEN_INT ( and_imm ) ) ) ; } tag = expand_simple_binop ( Pmode , ASHIFT , tag , GEN_INT ( IX86_HWASAN_SHIFT ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; rtx ret = expand_simple_binop ( Pmode , IOR , untagged , tag , target , <NUM_LIT>


<s> bool isRegisterSeq ( ) const { return Kind == RegisterSeq


<s> unsigned VFPThumb2PostEncoder ( const MachineInstr & MI , unsigned Val ) const { return <NUM_LIT>


<s> MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT>


<s> Front . pop_back ( ) ; if ( Reached . find ( MI ) != Reached . end ( ) ) continue ; Reached . insert ( MI ) ; if ( MI -> isPHI ( ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { Register Reg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) { continue ; } MachineInstr * NewMI = MRI -> getVRegDef ( Reg ) ; if ( ! NewMI ) continue ; Front . push_back


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI


<s> return __builtin_ia32_addph512_mask ( __B , __C , _mm512_setzero_ph ( ) ,


<s> else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc =


<s> bool IsNakedFunction = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode


<s> else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = ( Value & ~ <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case


<s> bool shouldIgnoreForPipelining ( const MachineInstr * MI ) const override { return MI


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) )


<s> unsigned <ISA_LIT>FrameLowering :: getInitialCFARegister ( const MachineFunction & MF ) const { return TRI -> getDwarfRegNum ( StackPtr


<s> Inst . addOperand ( MCOperand :: createReg ( RegShiftedImm . SrcReg ) ) ; unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ? <NUM_LIT> : RegShiftedImm .


<s> SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; GU = T1 . getNode ( ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , <STR_LIT> ) ; AsmNodeOperands . push_back ( PairedReg ) ; i += <NUM_LIT> ; } } if ( Glue . getNode ( ) )


<s> if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDVTList VTs = DAG . getVTList ( MaskVT


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE


<s> CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg =


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * FixupExpression = MCBinaryExpr :: createAdd ( MO . getExpr ( )

, MCConstantExpr :: create ( - <NUM_LIT> , Ctx ) , Ctx ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( T , TT ) ; MachineLocation FPDst ( MachineLocation :: VirtualFP ) ; MachineLocation FPSrc ( <STR_LIT> , - <STR_LIT> ) ; MAI -> addInitialFrameState ( <NUM_LIT> , FPDst


<s> SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode >


<s> unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder )

) Inst . addOperand ( MCOperand :: createImm ( imm32 ) ) ;


<s> void Thumb2InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( unsigned I = <STR_LIT> ; I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> __asm { mov eax , value cpuid mov esi , rEAX mov dword ptr [ esi ] , eax mov esi , rEBX mov dword ptr [ esi ] ,

ebx mov esi , rECX mov dword ptr [ esi ] , ecx mov esi , rEDX mov dword ptr [ esi ] , edx }


<s> } CallingConv :: ID CalleeCC = Info . CallConv ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; MachineInstrBuilder CallSeqStart ; if ( ! IsSibCall ) CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , true ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; MIB . addImm ( <NUM_LIT> ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; int FPDiff = <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; if ( ! IsSibCall ) { unsigned NumReusableBytes = FuncInfo -> getBytesInStackArgArea ( ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , F . getContext ( ) ) ; <ISA_LIT>OutgoingValueAssigner CalleeAssigner ( AssignFnFixed , AssignFnVarArg , Subtarget , false ) ; if ( ! determineAssignments ( CalleeAssigner , OutArgs , OutInfo ) ) return false ; NumBytes = alignTo ( OutInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; FPDiff = NumReusableBytes - NumBytes ; if ( FPDiff < <NUM_LIT> && FuncInfo -> getTailCallReservedStack ( ) < ( unsigned ) - FPDiff ) FuncInfo -> setTailCallReservedStack ( - FPDiff ) ; assert ( FPDiff % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; } const auto & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( AssignFnFixed , AssignFnVarArg , Subtarget , false ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , true , FPDiff ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , OutArgs , MIRBuilder , CalleeCC , Info . IsVarArg ) ) return false ; Mask = getMaskForArgs ( OutArgs , Info , * TRI , MF ) ; if ( Info . IsVarArg && Info . IsMustTailCall ) { for ( const auto & F : Forwards ) { Register ForwardedReg = F . PReg ; if ( any_of ( MIB -> uses ( ) , [ & ForwardedReg , & TRI ] ( const MachineOperand & Use ) { if ( ! Use . isReg ( ) ) return false ; return TRI -> regsOverlap ( Use . getReg ( ) , ForwardedReg ) ; } ) ) continue ; MIRBuilder . buildCopy ( ForwardedReg , Register ( F . VReg ) ) ; MIB . addReg ( ForwardedReg , RegState :: Implicit


<s> bool isImm7 ( ) const { return isImmediate < - <NUM_LIT> ,


<s> BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else if ( NumElts == <NUM_LIT> ) { BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else if ( NumElts == <NUM_LIT> ) { BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else return SDValue ( ) ; SDValue FirstOp = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( FirstOp ) && std :: all_of ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) , [ & FirstOp ] ( SDUse & U ) { return U . get ( ) . isUndef ( ) || U . get ( ) == FirstOp ; } ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FirstOp , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Ext ) ; } unsigned Bits32 = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( ! isa < ConstantSDNode > ( V ) && ! V . isUndef ( ) ) continue ; bool BitSet = V . isUndef ( ) ? false : cast < ConstantSDNode > ( V ) -> getZExtValue ( ) ; if ( BitSet ) Bits32 |= BoolMask << ( i * BitsPerBool ) ; } SDValue Base = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( Bits32 , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( isa < ConstantSDNode > ( V ) || V . isUndef ( ) ) continue ; Base = DAG . getNode ( <STR_LIT> , dl , VT , Base , V , DAG . getConstant ( i , dl , <STR_LIT> ) ) ; } return


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) )


<s> std :: pair < uint16_t , uint16_t > <ISA_LIT>BaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == <STR_LIT> && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ; return std :: make_pair (


<s> if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } return new <ISA_LIT>GNULDBackend ( pConfig , new <ISA_LIT>GNUInfo ( pConfig . targets ( ) . triple ( )


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { static llvm :: DenseMap < unsigned , MCFixupKindInfo > Infos = { { <STR_LIT> :: fixup_csky_addr32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_addr_hi16 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_addr_lo16 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_pcrel_imm16_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_uimm16_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } } , { <STR_LIT> :: fixup_csky_pcrel_uimm8_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } } , { <STR_LIT> :: fixup_csky_pcrel_imm26_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_imm18_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_got32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_got_imm18_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_gotoff , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_gotpc , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_plt32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_plt_imm18_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_pcrel_imm10_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_uimm7_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } } , { <STR_LIT> :: fixup_csky_doffset_imm18 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_doffset_imm18_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_doffset_imm18_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } } ; assert ( Infos . size ( ) == <STR_LIT> && <STR_LIT> ) ; if ( FirstTargetFixupKind <= Kind && Kind < FirstLiteralRelocationKind ) { assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind ] ; } else if ( Kind < FirstTargetFixupKind ) { return MCAsmBackend :: getFixupKindInfo ( Kind ) ; } else


<s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG -


<s> unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + WhichResult ) ) return false ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult =


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void \ switch_to_section ( enum in_section section , tree decl ) \ { \ switch ( section ) \ { \ case in_text : text_section ( ) ; break ; \ case in_unlikely_executed_text : unlikely_text_section ( ) ; break ; \ case in_data : data_section ( ) ; break

; \ case in_readonly_data : readonly_data_section ( ) ; break ; \ case in_named : named_section ( decl , NULL , <NUM_LIT> ) ; break ; \ case in_drectve : drectve_section ( ) ; break ; \ default : abort ( ) ; break ; \ } \ }


<s> RegT = get<ISA_LIT>RegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , <NUM_LIT> ) ; emitWordLE ( Binary


) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue (


<s> unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE


<s> case <STR_LIT> : assert ( ! IsResolved ) ; if ( TheTriple . isOSBinFormatCOFF ( ) ) return AdrImmBits ( Value & <NUM_LIT> ) ; return AdrImmBits ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value


<s> Changed |= convertToCTRLoop ( * I ) ; } if ( Changed ) { return Changed ; } SmallVector < MachineInstr * , <NUM_LIT> > OldInsts ; CountValue * TripCount = getTripCount ( L , OldInsts ) ; if ( TripCount == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( TripCount -> isImm ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TripCount -> getImm ( ) << <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( TripCount -> getImm ( ) ) ) return false ; } if ( containsInvalidInstruction ( L ) ) { return false ; } MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( Preheader == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ; DebugLoc dl ; if ( InsertPos != Preheader -> end ( ) ) dl = InsertPos -> getDebugLoc ( ) ; MachineBasicBlock * LastMBB = L -> getExitingBlock ( ) ; if ( LastMBB == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ; MachineBasicBlock * LoopStart = L -> getTopBlock ( ) ; if ( L -> getLoopLatch ( ) != LastMBB ) { LoopStart = L -> getLoopLatch ( ) ; if ( ! LastMBB -> isSuccessor ( LoopStart ) ) { return false ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; MachineFunction * MF = LastMBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = is<ISA_LIT>64 ? G8RC : GPRC ; unsigned CountReg ; if ( TripCount -> isReg ( ) ) { const TargetRegisterClass * SrcRC = MF -> getRegInfo ( ) . getRegClass ( TripCount -> getReg ( ) ) ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned CopyOp = ( is<ISA_LIT>64 && SrcRC == GPRC ) ? ( unsigned ) <STR_LIT> : ( unsigned ) TargetOpcode :: COPY ; BuildMI ( * Preheader , InsertPos , dl , TII -> get ( CopyOp ) , CountReg ) . addReg ( TripCount -> getReg ( ) ) ; if ( TripCount -> isNeg ( ) ) { unsigned CountReg1 = CountReg ; CountReg = MF -> getRegInfo (


<s> if ( Op . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) return Op ; MaskedScatterSDNode * N = cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ; SDValue Src = N -> getValue ( ) ; MVT VT = Src . getSimpleValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue NewScatter ; SDValue Index = N -> getIndex ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue Chain = N -> getChain ( ) ; SDValue BasePtr = N -> getBasePtr ( ) ; MVT MemVT = N -> getMemoryVT ( ) . getSimpleVT ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; if ( MemVT . getScalarSizeInBits ( ) < VT . getScalarSizeInBits ( ) ) { assert ( ( MemVT == <STR_LIT> && VT == <STR_LIT> ) && <STR_LIT> ) ; int ShuffleMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Src = DAG . getVectorShuffle ( <STR_LIT> , dl , DAG . getBitcast ( <STR_LIT> , Src ) , DAG . getUNDEF ( <STR_LIT> ) , ShuffleMask ) ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , <NUM_LIT> ) ; Index = ExtendToType ( Index , NewIndexVT , DAG ) ; assert ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , <NUM_LIT> ) ; Mask = ExtendToType ( Mask , ExtMaskVT , DAG , true ) ; VT = <STR_LIT> ; } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { if ( IndexVT == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT>


<s> break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |=


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; MVT VT = RHS . getSimpleValueType ( ) ; SDLoc DL ( N ) ; auto * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; RHS = DAG . getConstant ( - <NUM_LIT> , DL , VT ) ; MachineMemOperand * MMO = cast < MemSDNode > ( N ) -> getMemOperand


<s> static void rs6000_function_arg_advance ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { rs6000_function_arg_advance_1 ( get_cumulative_args ( cum ) , mode , type , named


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mve_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & mve_builtin_data [ i ] ; arm_init_builtin ( fcode , d ,


<s> if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( CP -> getConstVal ( ) , CP -> getValueType ( <NUM_LIT> ) , CP -> getAlign ( ) , CP -> getOffset ( ) , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ; if ( const JumpTableSDNode * JT = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( JT -> getIndex ( ) , JT -> getValueType ( <NUM_LIT>


<s> unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 + <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } if ( passesFPReg ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( SpareReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add


<s> if ( ! LastInstInFunction ) { std :: pair < Iter , bool > Res = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; LastInstInFunction |= Res . second ; IInSlot = Res . first ; } if ( LastInstInFunction || ! SafeInSlot ( * IInSlot , * I ) ) { MachineBasicBlock :: instr_iterator Iit = I -> getIterator ( ) ; if ( std :: next ( Iit ) == FI -> end ( ) || std :: next ( Iit ) -> getOpcode ( ) != <STR_LIT> ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( * MFp , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ) ; NumInsertedNops ++ ; } } } } return


<s> unsigned RR = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src , false ) ; if ( RR == <NUM_LIT> ) return false ; ResultReg = RR ; return true


<s> void setFramePtrSpillOffset ( unsigned o ) { FramePtrSpillOffset =


<s> } } unsigned DelayLimit = SchedModel . MispredictPenalty * <NUM_LIT> / <NUM_LIT> ; unsigned HeadDepth = Trace . getInstrCycles ( * CmpConv . Head -> getFirstTerminator ( ) ) . Depth ; unsigned CmpBBDepth = Trace . getInstrCycles ( * CmpConv . CmpBB -> getFirstTerminator ( ) ) . Depth ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadDepth << <STR_LIT> << CmpBBDepth << '\n' ) ; if ( CmpBBDepth > HeadDepth +


<s> if ( MBB . empty ( ) ) return false ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; if ( MBBI != MBB . begin ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { MachineInstr * PrevMI = prior ( MBBI ) ; unsigned Opcode = PrevMI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> ) || Opcode ==


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( STI . hasLoadStoreOnCond2 ( ) && getConditionalLoadImmediate ( Opcode


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( const auto & Instr : TagStores ) { dbgs ( ) << <STR_LIT> << * Instr . MI ; } ) ; const int kSetTagLoopThreshold = <NUM_LIT> ; if ( Size < kSetTagLoopThreshold ) { if ( TagStores . size ( ) < <NUM_LIT> ) return ; emitUnrolled ( InsertI ) ; } else { MachineInstr * UpdateInstr = nullptr ; int64_t TotalOffset = <NUM_LIT> ; if ( TryMergeSPUpdate ) { if ( InsertI != MBB -> end ( ) && canMergeRegUpdate ( InsertI , FrameReg , FrameRegOffset . getFixed ( ) + Size , & TotalOffset ) ) { UpdateInstr = & * InsertI ++ ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * UpdateInstr ) ; } } if ( ! UpdateInstr && TagStores . size ( ) < <NUM_LIT> ) return ; if ( UpdateInstr ) { FrameRegUpdate =


<s> return SDValue ( ) ; } EVT VT = Mst -> getValue ( ) . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getScalarSizeInBits ( ) ; unsigned ToSz = StVT . getScalarSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems


<s> static const struct mips_cpu_info * mips_default_arch ( void ) { unsigned int i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ ) if ( strcmp ( mips_cpu_info_table [ i ] . name , MIPS_CPU_STRING_DEFAULT ) == <NUM_LIT> ) return mips_cpu_info_table + i ; gcc_unreachable ( )


<s> bool <ISA_LIT>InstrInfo :: isLoadFromConstantPool ( MachineInstr * I ) const { if ( ! I -> hasOneMemOperand ( ) ) return false ; MachineMemOperand * Op = I -> memoperands


<s> if ( NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS ) return <NUM_LIT> ; needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG ( arg . mode , arg . type ) ; remaining_reg_count = NDS32_MAX_GPR_REGS_FOR_ARGS - ( NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) -


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL (


<s> return ( ( vec_int4 ) ( si_shli ( ( qword ) (


<s> return decodeSImmOperand < <NUM_LIT> > ( Inst , Imm


<s> assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext (

) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ;


<s> Value * Store1 = I1 == Out . end ( ) ? Constant :: getNullValue ( IRB . getInt64Ty ( ) ) : I1 -> second ; Value * Store2 = I2 == Out . end ( ) ? Constant :: getNullValue ( IRB . getInt64Ty ( ) ) : I2 -> second ; emitPair ( IRB , Offset , Store1 , Store2 ) ; LastOffset = Offset + <NUM_LIT> ; } if ( LastOffset < Size ) emitZeroes ( IRB , LastOffset , Size -


<s> void addFPImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , CE -> getValue ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val


<s> SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , A64cc , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true


<s> static void checkNumAlignedDPRCS2Regs ( MachineFunction & MF ) { MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setNumAlignedDPRCS2Regs ( <NUM_LIT> ) ; if ( ! SpillAlignedNEONRegs ) return ; if ( MF . getFunction ( ) -> getFnAttributes ( ) . hasNakedAttr ( ) ) return ; if ( ! MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) ) return ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= <NUM_LIT> ) return ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! RegInfo -> canRealignStack ( MF ) ) return ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumSpills


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB .


<s> LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; EVT LoadedVT = LD -> getMemoryVT ( ) ; SDValue Offset , AMOpc ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( LoadedVT == <STR_LIT> && isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> :


<s> for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc


<s> if ( ( TREE_CODE ( exp ) == VAR_DECL || TREE_CODE ( exp ) == FUNCTION_DECL

) && DECL_DLLIMPORT_P ( exp ) ) return false ;


<s> if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = dyn_cast < VectorType > ( Op0 -> getType ( ) ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> ,


<s> bool SelectOffsetUImm12 ( SDValue N , SDValue & UImm12 ) { const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ; if ( ! CN || CN -> getZExtValue ( ) % MemSize != <NUM_LIT> || CN -> getZExtValue ( ) / MemSize > <NUM_LIT> ) return false ; UImm12 = CurDAG -> getTargetConstant ( CN -> getZExtValue


<s> symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; in_section = NULL ; switch_to_section ( function_section ( decl ) ) ; putc ( '.' , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; data . function_descriptor = true ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; if ( ! DECL_IGNORED_P ( decl ) ) { if ( write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG ) xcoffout_declare_function ( file , decl , buffer ) ; else if ( write_symbols == DWARF2_DEBUG ) { name = ( * targetm . strip_name_encoding ) ( name ) ; fprintf ( file , <STR_LIT> , name , name


<s> static bool isSimpleBD12Move ( const MachineInstr * MI , unsigned Flag ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; return ( ( MCID . TSFlags & Flag ) && isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm (

) ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ;


<s> else if ( ! strncmp ( q , <STR_LIT> , <NUM_LIT> ) ) opts -> x_target_flags &= ~ MASK_THUMB ; else if ( ! strncmp ( q , <STR_LIT> , <NUM_LIT> ) ) { if ( ! opt_enum_arg_to_value ( OPT_mfpu_ , q + <NUM_LIT> , & opts -> x_arm_fpu_index , CL_TARGET ) ) { error ( <STR_LIT> , q ) ; return false ; } } else { error ( <STR_LIT> , q ) ; return false ; } arm_option_check_internal ( opts ) ; } return true


<s> return ( unsigned long long ) __builtin_sssubv2si3 ( ( v2si


<s> else if ( ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names [ from ] , reg_class_names [ to ] ) ; dbg_cost_ctrl -- ; } return ret


<s> unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V2 ) ; emitWordLE ( Binary


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitFunctionEntryLabel ( ) { if ( ! Subtarget -> is<ISA_LIT>64 ( ) && ( TM . getRelocationModel ( ) != Reloc :: PIC_ || MF -> getFunction ( ) -> getParent ( ) -> getPICLevel ( ) == PICLevel :: SmallPIC ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; if ( ! Subtarget -> is<ISA_LIT>64 ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> usesPICBase ( ) ) { MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer -> EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: create ( PICBase , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> EmitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT> ) ; } return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; MCSectionELF * Section = OutStreamer -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section


<s> for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) return false ; return true


<s> } Type * I1Type = Type :: getInt1Ty ( VecTy -> getContext ( ) ) ; MaskCost = getReplicationShuffleCost ( I1Type , Factor , VF , UseMaskForGaps ? DemandedLoadStoreElts : APInt :: getAllOnes ( VecTy -> getNumElements ( ) ) , CostKind ) ; if ( UseMaskForGaps ) { auto * MaskVT = FixedVectorType :: get ( I1Type , VecTy -> getNumElements ( ) ) ; MaskCost += getArithmeticInstrCost ( BinaryOperator :: And , MaskVT , CostKind ) ; } } if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = UseMaskedMemOp || NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + MaskCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT>


<s> if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POWER10 ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( rs6000_aix_extabi ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P9_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p ,


<s> FunctionPass * llvm :: create<ISA_LIT>DelaySlotFillerPass ( const <ISA_LIT>TargetMachine & ) { return new Filler (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL64 ( const Target & T , StringRef


<s> EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; RegNo = tryParseRegister ( ) ; return ( RegNo == ( unsigned ) - <NUM_LIT>


<s> static inline bool isThumbImmShiftedVal ( unsigned V ) { V = ( ~ <NUM_LIT> << getThumbImmValShift ( V


<s> const Register MachineFramePtr = STI . isTarget64BitILP32 ( ) ? Register ( get<ISA_LIT>SubSuperRegister ( FramePtr , <NUM_LIT> ) ) : FramePtr ; unsigned DwarfReg = MRI -> getDwarfRegNum ( MachineFramePtr , true ) ; unsigned Offset = ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) + ( Uses64BitFramePtr ? <NUM_LIT> : <NUM_LIT> ) ; BuildCFI ( MBB , MBBI , DebugLoc { } , MCCFIInstruction

:: createOffset ( nullptr , DwarfReg , - Offset ) ) ;


<s> if ( Offset && SD && ! Writer -> doesSymbolRequireExternRelocation ( SD ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , RelocType , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; const MCSymbolData * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , SD , FixedValue ) ) { RelSymbol = SD ; if ( ! SD -> getSymbol ( ) . isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue & <NUM_LIT> ; break ; } MachO :: any_relocation_info MREPair ; MREPair . r_word0 =


<s> } destlo = gen_rtx_REG_offset ( operands [ <NUM_LIT> ] , halfmode , dest , <NUM_LIT> ) ; desthi = gen_rtx_REG_offset ( operands [ <NUM_LIT> ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , destlo ) && reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , desthi ) ) { emit_insn ( gen_xorv16qi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [


<s> MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < <ISA_LIT>HazardRecognizerFPMLx > ( ) ) ; auto BHR = TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; if ( BHR ) MHR -> AddHazardRecognizer ( std :: unique_ptr

< ScheduleHazardRecognizer > ( BHR ) ) ;


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand


<s> if ( ! DstRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } const RegisterBank & VecRB = * RBI . getRegBank ( VecReg , MRI , TRI ) ; const LLT & VecTy = MRI . getType ( VecReg ) ; const TargetRegisterClass * VecRC = getRegClassForTypeOnBank ( VecTy , VecRB , RBI , true ) ; if ( ! VecRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register InsertReg = VecReg ; if ( ! DstReg ) DstReg = MRI . createVirtualRegister ( DstRC ) ; if ( LaneIdx == <NUM_LIT> ) { auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { * DstReg } , { } ) . addReg ( VecReg , <NUM_LIT> , ExtractSubReg ) ; RBI . constrainGenericRegister ( * DstReg , * DstRC , MRI ) ; return & *


<s> return Subtarget -> hasVFP2Base ( ) ; case <STR_LIT> : return Subtarget -> hasVFP2Base ( ) ; case <STR_LIT> : return Subtarget -> hasFP64 ( ) ; case <STR_LIT> : case <STR_LIT> : return Subtarget -> hasMVEFloatOps ( ) ; default : return


<s> return std :: any_of ( std :: begin ( GPRArgRegs ) , std :: end ( GPRArgRegs ) , [ this ,

& MF ] ( MCPhysReg r ) { return isReservedReg ( MF , r ) ; } ) ;


<s> if ( VT != <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; MVT WVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * VT . getVectorNumElements ( ) ) ; if ( WVT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( N1 ) < <NUM_LIT> || DAG . ComputeNumSignBits ( N0 ) < <NUM_LIT> ) return SDValue ( ) ; auto GetZeroableOp = [ & ] ( SDValue Op ) { APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( Op , Mask17 ) ) return Op ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . is128BitVector ( ) && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } return SDValue ( ) ; } ; SDValue ZeroN0 = GetZeroableOp ( N0 ) ; SDValue ZeroN1 = GetZeroableOp ( N1 ) ; if ( ! ZeroN0 && ! ZeroN1 ) return SDValue (


<s> return __builtin_ia32_sqrtsh_mask_round ( __B , __A , _mm_setzero_ph ( ) , ( __mmask8 )