<s> return all_of ( C -> operands ( ) , [ ] ( const Use & U ) { return containsOnlyConstantData ( cast < Constant >


<s> if ( ! InputNode || ! Subtarget . hasVSX ( ) || ! <STR_LIT> ( InputNode ) ) return false ; EVT Ty = Op -> getValueType ( <NUM_LIT> ) ; if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) && <STR_LIT> ( InputNode ) ) return true ; EVT MemVT = InputNode -> getMemoryVT ( ) ; if ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && <STR_LIT> ( InputNode ) && ( MemVT == Ty . getVectorElementType ( ) ) ) return true ; if ( Ty == <STR_LIT>


<s> return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { if ( LHS . getOpcode ( ) == <STR_LIT> ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; } bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNOT ( DL , LHS . getOperand ( <NUM_LIT> ) , VT ) ; assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; return LHS . getOperand ( <NUM_LIT> ) ; } } if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> && LHS . getValueType ( ) == <STR_LIT> ) return LowerVSETCC ( SDValue ( N , <NUM_LIT> ) , Subtarget , DAG ) ; return SDValue


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; const bool HasFullFP16 = Subtarget -> hasFullFP16 ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! HasFullFP16 ) return SDValue ( ) ; auto ZeroExtend = N -> use_begin ( ) ; if ( N -> use_size ( ) != <NUM_LIT> || ZeroExtend -> getOpcode ( ) != <STR_LIT> || ZeroExtend -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; auto Copy = ZeroExtend -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> && Copy -> use_begin ( )


<s> static inline unsigned char getBaseOpcodeFor ( unsigned TSFlags ) { return TSFlags >>


<s> return MI -> findRegisterUseOperandIdx ( <STR_LIT> )


<s> bool shouldTrackPressure ( ) const override { return false


<s> return __builtin_mve_vrhaddq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> Undef2 &= ( SM_SentinelUndef == M2 ) ; Zero1 &= isUndefOrZero ( M1 ) ; Zero2 &= isUndefOrZero ( M2 ) ; } assert ( ! ( ( Undef1 || Zero1 ) && ( Undef2 || Zero2 ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createUnpackShuffleMask ( VT , Unpckl , true , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } createUnpackShuffleMask ( VT , Unpckh , false , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true


<s> Offset += RI -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset + StackSize ; Offset += RI ->


<s> if ( ! TFI . hasFP ( MF ) ) report_fatal_error ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ; else { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( FrameReg == <STR_LIT> || FrameReg == <STR_LIT> ) && <STR_LIT> ) ; } } if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> BV1 = ( ( BV1 && Size != ( int ) BV1 -> getNumOperands ( ) ) ? nullptr : BV1 ) ; BV2 = ( ( BV2 && Size != ( int ) BV2 -> getNumOperands ( ) ) ? nullptr : BV2 ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] == SM_SentinelUndef || Mask [ i ] == ExpectedMask [ i ] ) continue ; if ( <NUM_LIT> <= Mask [ i ] && <NUM_LIT> <= ExpectedMask [ i ] ) { auto * MaskBV = Mask [ i ] < Size ? BV1 : BV2 ; auto * ExpectedBV = ExpectedMask [ i ] < Size ? BV1 : BV2 ; if ( MaskBV && ExpectedBV && MaskBV -> getOperand ( Mask [ i ] % Size ) == ExpectedBV -> getOperand ( ExpectedMask [ i ] % Size ) ) continue ; } return false ; } return


<s> const Function & F = * MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeSet :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildExtract ( Regs , Offsets


<s> unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return <ISA_LIT>MaterializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; if ( ! IsZExt ) { Op0 = EmitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; if ( ! Op0 ) return <NUM_LIT> ; Op0IsKill = true ; SrcVT = RetVT ; SrcBits = SrcVT . getSizeInBits ( ) ; IsZExt = true ; } unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill =


<s> break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . ashr ( ShiftAmt ) , dl , ElementType


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . c [ si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) ( shmask . v )


<s> void <ISA_LIT>DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == <STR_LIT> || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++


<s> } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ; else CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ; } else CanAcceptPredicationCode =


<s> O << getShiftOpcStr ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) { O << <STR_LIT> ; if ( UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << translateShiftImm ( ShImm ) ; if ( UseMarkup )


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) , false ) ; return getTargetVShiftByConstNode ( <ISA_LIT>Opc , SDLoc ( N ) , VT . getSimpleVT ( ) , N0 , EltBits [ <NUM_LIT> ] . getZExtValue ( ) , DAG ) ; } APInt KnownUndef , KnownZero


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr


<s> for ( bs1 = bs0 ; bs1 < HOST_BITS_PER_WIDE_INT ; bs1 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs1 ) ) == <NUM_LIT> ) break ; gcc_assert ( bs1 == HOST_BITS_PER_WIDE_INT || ( ( unsigned HOST_WIDE_INT )


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return - <NUM_LIT>


<s> return ( __m64 ) __builtin_ia32_pfmul ( ( __v2sf ) __A , (


<s> } if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return false ; } if ( HasExistingPersonality ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes ( ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; return


<s> bool hasSMEF64 ( ) const { return HasSMEF64


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const TargetMachine & TM = getTargetMachine ( ) ; bool IsRO = isReadOnly ( GV ) ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) && ! Subtarget -> genExecuteOnly ( ) ) if ( SDValue V = promoteToConstantPool ( GV , DAG , PtrVT , dl ) ) return V ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , UseGOT_PREL ? <STR_LIT> : <NUM_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO


<s> SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( i ) ) ; Ops . push_back ( V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , FloatVT


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> assert ( isa < ConstantSDNode > ( CCVal ) && <STR_LIT> ) ; unsigned CC = cast < ConstantSDNode > ( CCVal ) -> getZExtValue ( ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; unsigned CmpOpc = Cmp . getOpcode ( ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) || ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; assert ( LHS . getValueType ( ) == RHS . getValueType ( ) && <STR_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isa < ConstantSDNode > ( LHS ) && cast < ConstantSDNode > ( LHS ) -> isNullValue ( ) ) std :: swap ( LHS , RHS ) ; if ( ! isa < ConstantSDNode > ( RHS ) || ! cast < ConstantSDNode > ( RHS )

-> isNullValue ( ) ) return SDValue ( ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x ) || SYMBOL_REF_EXTERNAL_P ( x ) ; return DECL_P ( decl ) && ( TREE_PUBLIC ( decl ) || DECL_WEAK ( decl


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( PhysReg ) ) ; if ( TM . isELFv2ABI ( ) && PhysReg == <STR_LIT> ) { return ( getReservedRegs ( MF ) . test


<s> <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc (


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT NewTy ; const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpTy == <STR_LIT> ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> SDValue Build = ST -> getValue ( ) ; if ( MemVT != <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < MemVT . getVectorNumElements ( ) ; I ++ ) { unsigned Elt = DAG . getDataLayout ( ) . isBigEndian ( ) ? MemVT . getVectorNumElements ( ) - I - <NUM_LIT> : I ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Build , DAG . getConstant ( Elt , dl , <STR_LIT> ) ) ) ; } for ( unsigned I = MemVT . getVectorNumElements ( ) ; I < <NUM_LIT> ; I ++ ) Ops . push_back ( DAG


<s> unsigned alignment = ( LocVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Offset = State . AllocateStack ( size , alignment ) ; unsigned Reg = <NUM_LIT> ; if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return


<s> SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , true , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? SM_SentinelUndef : ShuffleMask [ Elt ] ; if ( Idx == SM_SentinelZero ) return EltVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , EltVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , EltVT ) ; if ( Idx == SM_SentinelUndef ) return DAG . getUNDEF ( EltVT ) ; assert ( <NUM_LIT> <= Idx && Idx < ( int ) ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = DAG . getDataLayout ( ) . getABITypeAlignment ( EltVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( NewAlign > Align || ! TLI . isOperationLegalOrCustom ( <STR_LIT> , EltVT ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Shuffle = ( UnaryShuffle ) ? DAG . getUNDEF ( CurrentVT ) : InVec . getOperand


<s> SmallVector < SDValue , <NUM_LIT> > Elts ; MVT SVT = VT . getVectorElementType ( ) ; unsigned SVTBits = SVT . getSizeInBits ( ) ; APInt One ( SVTBits , <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Op = Amt -> getOperand ( i ) ; if ( Op -> isUndef ( ) ) { Elts . push_back ( Op ) ; continue ; } ConstantSDNode * ND = cast < ConstantSDNode > ( Op ) ; APInt C ( SVTBits , ND -> getAPIntValue ( ) . getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Amt ) ; } if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) { SDValue Z = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , getUnpackl ( DAG , dl , VT , Amt , Z ) ) ; SDValue Hi = DAG . getBitcast ( <STR_LIT> , getUnpackh ( DAG ,


<s> SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT ResVT = Op . getSimpleValueType ( ) ; MVT InVT = In . getSimpleValueType (


<s> SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , OrigArg . Flags ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags } ) ; } SmallVector < uint64_t , <NUM_LIT> >


<s> bool <ISA_LIT>FastISel :: SelectFPToInt ( const Instruction * I , bool Signed ) { MVT DestVT ; if ( ! isTypeLegal ( I -> getType ( ) , DestVT ) || DestVT . isVector ( ) ) return false ; unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> ) return false ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else


<s> MCContext & Context = Streamer . getContext ( ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , Context ) ; MCSymbol * PCSym = Context . createTempSymbol ( ) ; Streamer . EmitLabel (


<s> Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; unsigned regSpillArea = Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; regSpillArea += Subtarget -> getStackPointerBias ( ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , VT , New<ISA_LIT> , DAG .


<s> CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , <STR_LIT> ) ; emitInst ( TargetOpcode :: COPY , <STR_LIT> ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg ,


<s> SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; return SDValue ( N , <NUM_LIT>


<s> CCInfo . clearWas<ISA_LIT>F128 ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; EVT ValVT = VA . getValVT ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Vector ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = Subtarget . hasQPX ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT == <STR_LIT> ? <STR_LIT> : ValVT ) ; if ( ValVT == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( )


<s> int64_t ElementBits = VT . getScalarSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow

? ElementBits / <NUM_LIT> : ElementBits ) ) ;


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT>

&& N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI =


<s> float res ; __asm__ ( <STR_LIT> : <STR_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter >


<s> unsigned <ISA_LIT>InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) )


<s> bool Lo = Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; MVT ShuffleVT = <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; Op = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getNode ( <STR_LIT> , DL , RootVT , Op ) , true ) ; return true ; } } if ( ! FloatDomain && ( Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ) { bool Lo = Mask [ <NUM_LIT> ] == <NUM_LIT> ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; MVT ShuffleVT ; switch ( Mask . size ( ) ) { case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; Op = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getNode ( <STR_LIT> , DL , RootVT , Op ) , true ) ; return true ; } if ( Depth < <NUM_LIT> ) return false ; if ( ( Depth >= <NUM_LIT> || HasPSHUFB ) && Subtarget ->


<s> EXECUTE_IF_SET_IN_BITMAP ( insns , <NUM_LIT> , id , bi ) { convert_insn ( DF_INSN_UID_GET ( id ) -> insn ) ; converted_insns


<s> ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregxiv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregxiv8hf (


<s> const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOInsertedReg . isUndef ( ) ) return false ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ; InsertedReg . SubIdx = MOIndex . getImm (


<s> if ( ! ST -> hasAVX512 ( ) ) return false ; if ( cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == <NUM_LIT> ) return false ; Type * ScalarTy = cast < VectorType > ( DataTy ) ->


<s> static void csky_initialize_isa ( sbitmap isa , const enum csky_isa_feature *


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; APInt Ones = APInt :: getAllOnesValue ( <NUM_LIT> ) ; unsigned NumElts = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Vec ; if ( ! Subtarget . hasInt256 ( ) && NumElts == <NUM_LIT> ) { Vec = DAG . getConstant ( Ones , dl , <STR_LIT> ) ; Vec = concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } else { Vec = DAG . getConstant ( Ones , dl , <STR_LIT> ( <STR_LIT> , NumElts ) ) ; } return DAG . getBitcast (


<s> if ( Opcode == Instruction :: And ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative (

) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass >


<s> if ( dep_type != <NUM_LIT> && ( dep_type != REG_DEP_OUTPUT || ! TUNE_20KC ) ) return <NUM_LIT> ; return cost


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction * F = MBB -> getParent ( ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } unsigned MOVOpc = Subtarget -> hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI -> eraseFromParent (


<s> const <ISA_LIT>InstrInfo & TII = * ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & TRI = * ST . getRegisterInfo ( ) ; const RegisterBankInfo & RBI = * ST . getRegBankInfo ( ) ; MIRBuilder . setInstr ( MI ) ; switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( createMemLibcall ( MIRBuilder , MRI , MI ) == LegalizerHelper :: UnableToLegalize ) return false ; MI . eraseFromParent ( ) ; return true ; case <STR_LIT> : { MachineInstr * Trap = MIRBuilder . buildInstr ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Trap , TII , TRI , RBI ) ; } case <STR_LIT> : { Register Tmp = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachinePointerInfo MPO ; MIRBuilder . buildLoad ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; MIRBuilder . buildStore ( Tmp , MI . getOperand ( <NUM_LIT> ) , * MI . getMF ( ) -> getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ) ; MI . eraseFromParent


<s> return GuaranteedTailCallOpt && IsTailCallConvention (


<s> return ( __m512h ) __builtin_ia32_getexpph512_mask ( ( __v32hf ) __A , ( __v32hf ) _mm512_setzero_ph ( ) , ( __mmask32 ) -


<s> unsigned getCalleeSavedStackSize ( )


<s> AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || ( ( M == CodeModel :: Small || M == CodeModel :: Kernel ) && TM . getRelocationModel ( ) == Reloc :: Static ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0


<s> if ( dest_code == REG && GP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == REG ) { if ( DSP_ACC_REG_P ( REGNO ( src ) ) ) { static char retval [ ] = <STR_LIT> ; retval [ <NUM_LIT> ] = reg_names [ REGNO ( src ) ] [ <NUM_LIT> ] ; retval [ <NUM_LIT> ] = reg_names [ REGNO ( src ) ] [ <NUM_LIT> ] ; return retval ; } if ( ST_REG_P ( REGNO ( src ) ) && ISA_HAS_8CC ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( src ) ) ) return ( dbl_p ? <STR_LIT> : <STR_LIT> ) ; if ( ALL_COP_REG_P ( REGNO ( src ) ) ) { static char retval [ ] = <STR_LIT> ; retval [ <NUM_LIT> ] = COPNUM_AS_CHAR_FROM_REGNUM ( REGNO ( src ) ) ; return ( dbl_p ? retval : retval + <NUM_LIT> ) ; } } if ( src_code == MEM ) return ( dbl_p ? <STR_LIT> : <STR_LIT> ) ; if ( src_code == CONST_INT ) { if ( ! TARGET_MIPS16 ) return <STR_LIT> ; if ( INTVAL ( src ) >= <NUM_LIT> && INTVAL ( src ) <= <NUM_LIT> ) return <STR_LIT> ; if ( INTVAL ( src ) < <NUM_LIT> && INTVAL ( src ) >= - <NUM_LIT> ) return <STR_LIT> ; } if ( src_code == HIGH ) return <STR_LIT> ; if ( CONST_GP_P ( src ) ) return <STR_LIT> ; if ( symbolic_operand ( src , VOIDmode ) ) return


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineInstr & MemMI = * I ; MachineBasicBlock :: iterator MBBI = I ; Register BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int Offset = getLdStOffsetOp ( MemMI ) . getImm ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; if ( ! isTagStore ( MemMI ) ) { bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , Offset ) ) return MBBI ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) || ! UsedRegUnits . available ( BaseReg ) ) return E ; } while ( MBBI != B


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM )


<s> return __builtin_aarch64_addpdi ( __a )


<s> break ; case CCValAssign :: AExtUpper : UseUpperBits = true ; LLVM_FALLTHROUGH ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: ZExtUpper : UseUpperBits = true ; LLVM_FALLTHROUGH ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; LLVM_FALLTHROUGH ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned V0 = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return LowerInterruptReturn ( RetOps , DL , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps


<s> return ( uint16x8_t ) __builtin_neon_vcagev8hf


<s> IV -> addIncoming ( ConstantInt :: get ( I16Ty , <NUM_LIT> ) , Preheader ) ; B . SetInsertPoint ( Latch ) ; Value * Inc = B . CreateAdd ( IV , Step , Name + <STR_LIT> ) ; Value * Cond = B . CreateICmpNE ( Inc , Bound , Name + <STR_LIT> ) ; BranchInst :: Create ( Header , Exit , Cond , Latch ) ; IV -> addIncoming ( Inc , Latch ) ; BranchInst * PreheaderBr = cast < BranchInst > ( Preheader -> getTerminator ( ) ) ; BasicBlock * Tmp = PreheaderBr -> getSuccessor ( <NUM_LIT> ) ; PreheaderBr -> setSuccessor ( <NUM_LIT> , Header ) ; DTU . applyUpdatesPermissive ( { { DominatorTree :: Delete , Preheader , Tmp } , { DominatorTree :: Insert , Header , Body } , { DominatorTree :: Insert , Body , Latch } , { DominatorTree :: Insert , Latch , Header } , { DominatorTree :: Insert , Latch , Exit } , { DominatorTree :: Insert , Preheader , Header } , } ) ; if ( LI ) { L -> addBasicBlockToLoop ( Header , * LI ) ; L -> addBasicBlockToLoop ( Body , *


<s> I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end


<s> SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , <STR_LIT> , <STR_LIT> ) ; SDValue Unused = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Chain = Unused . getValue ( <NUM_LIT> ) ; SDValue Glue = Chain . getValue ( <NUM_LIT> ) ; return std :: make_pair ( addIPMSequence ( DL , Glue


<s> return ( ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) || ( ! strict && reg_no >= FIRST_PSEUDO_REGISTER ) ) ; } else if ( ( ( code == POST_MODIFY || code == PRE_MODIFY ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && XEXP ( op , <NUM_LIT> ) == XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) && REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) || ( reload_completed && code == PLUS && REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ) { reg_no = arm_effective_regno ( XEXP ( op , <NUM_LIT> ) , strict ) ; if ( code == PLUS ) val = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; else val = INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; switch ( mode ) { case E_V16QImode : case E_V8QImode : case E_V4QImode : if ( abs ( val ) > <NUM_LIT> ) return FALSE ; break ; case E_V8HImode : case E_V8HFmode : case E_V4HImode : case E_V4HFmode : if ( val % <NUM_LIT> != <NUM_LIT> || abs ( val ) > <NUM_LIT> ) return FALSE ; break ; case E_V4SImode : case E_V4SFmode : if ( val % <NUM_LIT> != <NUM_LIT> || abs ( val ) > <NUM_LIT> ) return FALSE ; break ; default : return FALSE


<s> return _mm_set_epi64 ( ( __m64 ) <NUM_LIT> , * (


<s> return ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC && XINT (

SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) == UNSPEC_MOVA && GET_CODE ( XVECEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> , <NUM_LIT> ) ) == LABEL_REF ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ; SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG

. getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_aarch64_override_tune_string = opts -> x_aarch64_override_tune_string ; ptr -> x_aarch64_branch_protection_string = opts


<s> if ( leaf_function_p ( ) ) ( offset ) = <NUM_LIT> ; else ( offset ) = cfun -> machine -> gp_sp_offset + ( ( UNITS_PER_WORD - (

POINTER_SIZE / BITS_PER_UNIT ) ) * ( BYTES_BIG_ENDIAN != <NUM_LIT> ) ) ;


<s> static void printMemoryImmediateOffset ( const MCAsmInfo & MAI , const MCOperand & OffsetOp , raw_ostream & OS ) { assert ( ( OffsetOp . isImm ( ) || OffsetOp . isExpr ( ) ) && <STR_LIT> ) ; if ( OffsetOp . isImm ( ) ) { assert ( isInt < SizeInBits > ( OffsetOp . getImm ( ) ) && <STR_LIT> ) ; OS << OffsetOp . getImm ( ) ; } else OffsetOp . getExpr ( ) -> print (


<s> if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } rtx_insn * insn ; if ( ( LABEL_REF_P ( orig ) || ( SYMBOL_REF_P ( orig ) && SYMBOL_REF_LOCAL_P ( orig ) && ( SYMBOL_REF_DECL ( orig ) ? ! DECL_WEAK ( SYMBOL_REF_DECL ( orig ) ) : <NUM_LIT> ) && ( ! SYMBOL_REF_FUNCTION_P ( orig ) || arm_fdpic_local_funcdesc_p ( orig ) ) ) ) && NEED_GOT_RELOC && arm_pic_data_is_text_relative ) insn = arm_pic_static_addr ( orig , reg ) ; else { require_pic_register ( pic_reg , compute_now ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; insn = calculate_pic_address_constant ( reg , pic_reg , orig ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == cfun -> machine -> pic_reg ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) { gcc_assert ( CONST_INT_P ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT>


<s> RegOp . setReg ( SubRegCopy . getReg ( <NUM_LIT> ) ) ; if ( ! Register :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * To , MRI ) ; return true


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getLdStSORegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Rm = get<ISA_LIT>RegisterNumbering ( MO1 . getReg ( ) ) ; unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ; bool isAdd = <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ; <STR_LIT> ShOp = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned SBits = getShiftOp ( ShOp ) ; uint32_t Binary = Rm ; Binary |= Rn << <NUM_LIT> ; Binary |= SBits << <NUM_LIT> ; Binary |= ShImm << <NUM_LIT> ; if ( isAdd ) Binary


<s> rtx arm_gen_compare_reg ( rtx_code code , rtx x , rtx y , rtx scratch ) { if ( GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode )

return arm_gen_dicompare_reg ( code , x , y , scratch ) ;


<s> else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; X -> InitMCCodeGenInfo ( RM , CM


<s> void EmitLEA ( <ISA_LIT>Operand & Op , unsigned Size , unsigned Reg , MCStreamer & Out ) { assert ( Size == <NUM_LIT> || Size == <NUM_LIT> ) ; MCInst Inst ; Inst . setOpcode ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( get<ISA_LIT>SubSuperRegister ( Reg ,


<s> return ( __m128i ) __builtin_ia32_aesdeclast128 ( ( __v2di ) __X , ( __v2di )


<s> return __builtin_mve_uqrshl_si ( value ,


<s> int getReturnFunctionAddressRegister ( ) override final { return


<s> StackAlignment = Align ( <NUM_LIT> ) ; CPUDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , bool little , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>Default ) , IsLittle ( little ) , IsSoftFloat ( false ) , IsSingleFloat ( false ) , IsFPXX ( false ) , NoABICalls ( false ) , IsFP64bit ( false ) , UseOddSPReg ( true ) , IsNaN2008bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasCn<ISA_LIT> ( false ) , Has<ISA_LIT>3_32 ( false ) , Has<ISA_LIT>3_32r2 ( false ) , Has<ISA_LIT>4_32 ( false ) , Has<ISA_LIT>4_32r2 ( false ) , Has<ISA_LIT>5_32r2 ( false ) , In<ISA_LIT>16Mode ( false ) , In<ISA_LIT>16HardFloat ( <ISA_LIT>16HardFloat ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , HasDSPR3 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , HasMSA ( false ) , UseTCCInDIV ( false ) , HasEVA ( false ) , TM ( TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies ( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) { PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT>


<s> enum OperandTransfer OpTransfer = Entry . TransferOperands ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; ++ NumReduced ; if ( OpTransfer == OT_OperandsAll ) { MI -> setDesc ( <ISA_LIT>II -> get ( Entry . NarrowOpc ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return true ; } else { MachineBasicBlock & MBB = * MI -> getParent ( ) ; const MCInstrDesc & NewMCID = <ISA_LIT>II -> get ( Entry . NarrowOpc ( ) ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; switch ( OpTransfer ) { case OT_Operand2 : MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; break ; case OT_Operands02 : { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; break ; } case OT_OperandsXOR : { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { MIB . add ( MI -> getOperand ( <NUM_LIT> )


<s> if ( NumElts == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ; } return false


<s> int <ISA_LIT>FunctionInfo :: getMoveF64ViaSpillFI ( const TargetRegisterClass * RC ) { const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MoveF64ViaSpillFI == - <NUM_LIT> ) { MoveF64ViaSpillFI = MF . getFrameInfo ( ) . CreateStackObject ( TRI . getSpillSize ( * RC

) , TRI . getSpillAlignment ( * RC ) , false ) ;


<s> StringRef Suffix ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; } return Sym


<s> bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , <NUM_LIT> > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI -> definesRegister ( <STR_LIT> ) ) { CCUsers . clear


<s>
static
void
printSOImm
(
raw_ostream
&
O
,
int64_t
V
,
const
TargetAsmInfo
*
TAI
)
{
assert
(
V
<
(
<NUM_LIT>
<<
<NUM_LIT>
)
&&
<STR_LIT>
)
;
unsigned
Imm
=
<STR_LIT>
(
V
)
;
unsigned
Rot
=
<STR_LIT>
(
V
)
;
if
(
Rot
)
{
O
<<
<STR_LIT>
<<
Imm
<<
<STR_LIT>
<<
Rot
;
if
(
VerboseAsm
)
O
<<
' '
<<
TAI
->
getCommentString
(
)
<<
' '
<<
(
int
)
<STR_LIT>
(
Imm
,
Rot
)
;
}
else


<s> bool <ISA_LIT>AdvSIMDScalar :: isProfitableToTransform ( const MachineInstr * MI ) const { if ( ! isTransformable ( MI ) ) return false ; unsigned NumNewCopies = <NUM_LIT> ; unsigned NumRemovableCopies = <NUM_LIT> ; unsigned OrigSrc0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OrigSrc1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src0 = <NUM_LIT> , SubReg0 ; unsigned Src1 = <NUM_LIT> , SubReg1 ; if ( ! MRI -> def_empty ( OrigSrc0 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc0 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; Src0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( Src0 ) -- NumNewCopies ; if ( Src0 && MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) ++ NumRemovableCopies ; } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; Src1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( Src1 ) -- NumNewCopies ; if ( Src1 && MRI -> hasOneNonDBGUse (


<s> case <STR_LIT> : switch ( MI . getOperand ( <NUM_LIT> ) . getType ( ) ) { default : return false ; case MachineOperand :: MO_GlobalAddress : return MI . getOperand ( <NUM_LIT> ) .


<s> fprintf ( asm_out_file , <STR_LIT> ) ; ASM_OUTPUT_ALIGN ( asm_out_file , <NUM_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , <STR_LIT> ) ; recurse = <NUM_LIT> ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , <NUM_LIT> ) [ <NUM_LIT> ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , <NUM_LIT> ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , <STR_LIT> ,


<s> if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG (

op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ;


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI32

) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOTOFF_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOTOFF_LO32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PLT_HI32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PLT_LO32 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) ) op [ opc ] = convert_memory_address ( Pmode , op [ opc ] ) ; if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) op [ opc ] = copy_to_mode_reg ( mode , op [ opc ] ) ; break ; case SIMD_ARG_LANE_INDEX : gcc_assert ( opc > <NUM_LIT> ) ; if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , GET_MODE_NUNITS ( vmode ) , exp ) ; op [ opc ] = GEN_INT ( ENDIAN_LANE_N ( vmode , INTVAL ( op [ opc ] ) ) ) ; } case SIMD_ARG_CONSTANT : if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) { error ( <STR_LIT> , exp , opc + <NUM_LIT> - have_retval ) ; return const0_rtx ; } break ; case SIMD_ARG_STOP : gcc_unreachable ( ) ; } opc ++ ; } } switch ( opc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op


<s> for ( int i = <NUM_LIT> ; ; i ++ ) { if ( orig [ i ] == '\0' && equiv [ i ] == '\0' ) return true ; if ( orig [ i ] == '\0' || equiv [ i ] == '\0' ) return false ; if ( orig [ i ] != equiv [ i ] ) { if ( ( orig [ i ] == 'Q' || orig [ i ] == 'L' ) && equiv [ i ] == 'W' ) continue ; if ( ( orig [ i ] == '6' || orig [ i ] == '3' ) && equiv [ i ] == '1' ) continue ; if ( ( orig [ i ] == '4' || orig [ i ] == '2' ) && equiv [ i ] ==


<s> Node = emitIntrinsicWithCCAndChain ( DAG , C . Op0 , C . Opcode ) ; return SDValue ( Node , <NUM_LIT> ) ; case <STR_LIT> : Node = emitIntrinsicWithCC ( DAG , C . Op0 , C . Opcode ) ; return SDValue ( Node , Node -> getNumValues ( ) - <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getTargetConstant ( C . ICmpType , DL , <STR_LIT> ) ) ; if ( C . Opcode


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> void <ISA_LIT>AsmPrinter :: printAddrMode6Operand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI ->


<s> static inline unsigned getMemExtendImm ( <STR_LIT> ET , bool DoShift ) { return ( unsigned ( ET ) <<


<s> if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << <STR_LIT> ( Mode ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Mode == <STR_LIT> ) O << <STR_LIT> ; } else { printOperand ( MI , OpNum , O


<s> int parm_off = <NUM_LIT> ; if ( argc != <NUM_LIT> ) return <STR_LIT> ; ( strncmp ( argv [ <NUM_LIT> ] , OPTSTR_ ## NAME <STR_LIT> , \ ( parm_off = sizeof ( OPTSTR_ ## NAME ) ) ) == <NUM_LIT> ) if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ) { no_link =


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; } return isConsecutiveLSLoc ( N -> getOperand ( <NUM_LIT> ) , VT , Base , Bytes , Dist , DAG ) ; } if ( N -> getOpcode ( ) == <STR_LIT> ) { EVT VT ; switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; } return isConsecutiveLSLoc ( N -> getOperand ( <NUM_LIT> ) , VT , Base , Bytes , Dist , DAG ) ; } return


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; return ret


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) { outRegsUsed =


<s> if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT>


<s> case ADDRESS_REG_UXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return true ; case ADDRESS_REG_SXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return true ; case ADDRESS_REG_WB : size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; switch ( GET_CODE ( x ) ) { case PRE_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case POST_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t TruncMask = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ! isMask_64 ( TruncMask ) ) return SDValue ( ) ; uint64_t Width = CountPopulation_64 ( TruncMask ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Shift -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t LSB = Shift -> getConstantOperandVal ( <NUM_LIT> ) ; if ( LSB > VT . getSizeInBits ( ) || Width > VT . getSizeInBits ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Shift . getOperand ( <NUM_LIT> ) , DAG . getConstant ( LSB , <STR_LIT> ) , DAG . getConstant

( LSB + Width - <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( BVN && Subtarget -> hasNEON ( ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ; return SDValue (


<s> assert ( Offset && <STR_LIT> ) ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } ZFI -> setLowSavedGPR ( LowGPR ) ; ZFI -> setHighSavedGPR ( HighGPR ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( )


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler ::


<s> } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT>


<s> MCInst TmpInst = MI ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : LowerDextDins ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( ! Size ) llvm_unreachable ( <STR_LIT> ) ; EmitInstruction ( Binary , Size ,


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) , hasConsumedDollar ( false ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ; } return


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> )


<s> static VectorType * getVectorType ( IntrinsicInst * I ) { unsigned TypeOp = I -> getIntrinsicID ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto * PtrTy = cast < PointerType > ( I -> getOperand (


<s> assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; break ; case <STR_LIT> : Results . push_back ( LowerINTRINSIC_WO_CHAIN ( SDValue ( N , <NUM_LIT> ) , DAG ) ) ; break ; } break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( N -> isStrictFPOpcode ( ) ? <NUM_LIT> : <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl ) ) ; return ; case <STR_LIT> : { if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return ; SDValue Lowered = LowerTRUNCATEVector ( SDValue ( N , <NUM_LIT> ) , DAG ) ; if ( Lowered ) Results . push_back ( Lowered ) ; return ; } case <STR_LIT> : case <STR_LIT> : return ; case <STR_LIT> : return ; case <STR_LIT> : SDValue Lowered = LowerFP_EXTEND ( SDValue ( N , <NUM_LIT>


<s> return getTLSLDOReloc ( Kind ) ; case MCSymbolRefExpr :: VK_TLSLDM : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLDMReloc ( Kind ) ; case MCSymbolRefExpr :: VK_TLSGD : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSGDReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : if ( IsPCRel && Kind == <STR_LIT> ) return ELF :: R_390_GOTENT ; llvm_unreachable (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImm16Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO


<s> SDValue TrueVal2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FalseVal2 = Op2 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue * K1 = isa < ConstantSDNode > ( LHS1 ) ? & LHS1 : isa < ConstantSDNode > ( RHS1 ) ? & RHS1 : NULL ; SDValue * K2 = isa < ConstantSDNode > ( LHS2 ) ? & LHS2 : isa < ConstantSDNode > ( RHS2 ) ? & RHS2 : NULL ; SDValue K2Tmp = isa < ConstantSDNode > ( TrueVal2 ) ? TrueVal2 : FalseVal2 ; SDValue V1Tmp = ( K1 && * K1 == LHS1 ) ? RHS1 : LHS1 ; SDValue V2Tmp = ( K2 && * K2 == LHS2 ) ? RHS2 : LHS2 ; SDValue V2 = ( K2Tmp == TrueVal2 ) ? FalseVal2 : TrueVal2 ; SDValue V2TmpReg = V2Tmp ; if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2


<s> unsigned StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MaxAdjust > <NUM_LIT> ) Context . MovVector . resize ( MaxAdjust , nullptr ) ; InstClassification Classification ; DenseSet < unsigned int > UsedRegs ; while ( ( Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ) != Exit ) { if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm


<s> int ia64_move_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( src ) == MEM


<s> if ( ! IsOptNone ) { addPass ( create<ISA_LIT>PostLegalizerCombiner ( IsOptNone ) ) ; if ( EnableGISelLoadStoreOptPostLegal ) addPass ( new LoadStoreOpt ( ) ) ; } addPass ( create<ISA_LIT>PostLegalizerLowering (


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> inline vector signed short vec_vmaxsh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vmaxsh ( ( vector signed short ) a1


<s> if ( CONST_OK_FOR_I08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( ( outer_code == AND || outer_code == IOR || outer_code == XOR ) && CONST_OK_FOR_K08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_SHMEDIA64 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( TARGET_SHMEDIA32 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( TARGET_SHMEDIA ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = <NUM_LIT> ; return true ; case CONST_VECTOR : if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) * total = <NUM_LIT> ; else if ( sh_1el_vec ( x , VOIDmode ) ) * total = outer_code != SET ; if ( sh_rep_vec ( x , VOIDmode ) ) * total = ( ( GET_MODE_UNIT_SIZE ( GET_MODE ( x ) ) + <NUM_LIT> ) / <NUM_LIT> + ( outer_code != SET ) ) ; * total = COSTS_N_INSNS ( <NUM_LIT> ) + ( outer_code


<s> return ( __m128i ) __builtin_ia32_pmovqw256_mask ( ( __v4di ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) -


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl <


<s> } } } FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * end = BB_END ( bb ) ; rtx_insn * call_insn = NULL ; if ( bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) { rtx_insn * label = NULL ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) ) label = insn ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) label = insn ; if ( INSN_P ( insn ) ) break ; } gcc_assert ( label ) ; emit_insn_after ( aarch64_speculation_establish_tracker ( ) , label ) ; } for ( insn = BB_HEAD ( bb ) ; ; insn = NEXT_INSN ( insn ) ) { if ( NONDEBUG_INSN_P ( insn ) && recog_memoized ( insn ) >= <NUM_LIT> && ( get_attr_speculation_barrier ( insn ) == SPECULATION_BARRIER_TRUE ) ) { if ( call_insn ) { emit_insn_after ( aarch64_speculation_establish_tracker ( ) , call_insn ) ; call_insn = NULL ; } needs_tracking = true ; } if ( CALL_P ( insn ) ) { bool tailcall = ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ; if ( tailcall && ( need_second_pass || ! needs_tracking ) ) { fixups_pending ++ ; need_second_pass = true ; break ; } needs_tracking = true ; if ( ! call_insn ) emit_insn_before ( aarch64_speculation_clobber_sp ( ) , insn ) ; if ( ! tailcall ) call_insn = insn ; else call_insn = NULL ; } if ( insn == end ) break ; } if ( call_insn ) { rtx_insn * seq = aarch64_speculation_establish_tracker ( ) ; for ( insn = call_insn ; insn != end && DEBUG_INSN_P ( NEXT_INSN ( insn ) ) ; insn = NEXT_INSN ( insn ) ) ; if ( insn == end ) { edge e = find_fallthru_edge ( bb -> succs ) ; if ( e ) { if ( ! INSN_P ( seq ) ) { start_sequence ( ) ; emit_insn ( seq ) ; seq = get_insns ( ) ; end_sequence ( ) ; } for ( rtx_insn * list = seq ; list ; list = NEXT_INSN ( list ) ) INSN_LOCATION ( list ) = INSN_LOCATION ( call_insn ) ; insert_insn_on_edge ( seq , e ) ; } } else emit_insn_after ( seq , call_insn ) ; } } if ( needs_tracking ) { if ( need_second_pass ) { FOR_EACH_BB_FN ( bb , cfun ) { insn = BB_END ( bb ) ; while ( insn != BB_HEAD ( bb ) && NOTE_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( ( control_flow_insn_p ( insn ) && GET_CODE ( PATTERN ( insn ) ) == RETURN ) || ( CALL_P ( insn ) && ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ) ) { rtx_insn * seq = aarch64_speculation_clobber_sp


<s> unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder ,


<s> inline vector signed char vec_sll ( vector signed char a1 , vector unsigned char a2 ) { return ( vector signed char ) __builtin_altivec_vsl ( ( vector signed int


<s> return V -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) && V -> getConstantOperandVal ( <NUM_LIT> ) == Lane + <NUM_LIT> ; } ) ; if ( OtherIt == Op0 -> uses ( ) . end ( ) ) return SDValue ( ) ; SDValue OtherExt ( * OtherIt , <NUM_LIT> ) ; if ( OtherExt . getValueType ( ) != <STR_LIT> ) { if ( OtherExt -> use_size ( ) != <NUM_LIT> || OtherExt -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> || OtherExt -> use_begin ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; OtherExt = SDValue ( * OtherExt -> use_begin ( ) , <NUM_LIT> ) ; } SDValue F64 = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DCI . DAG . getConstant ( Ext . getConstantOperandVal ( <NUM_LIT> ) / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VMOVRRD = DCI . DAG . getNode ( <STR_LIT> , dl


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ; return ! MFI . hasVarSizedObjects


<s> const <ISA_LIT>InstrRelaxTableEntry * llvm :: lookupShortTable ( unsigned RelaxOp ) { auto & Table = ShortTable -> Table ; auto I = llvm :: lower_bound ( Table , RelaxOp ) ; if ( I != Table . end ( ) && I -> KeyOp == RelaxOp ) return & * I ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; bool IsNegPow2 = ( - Divisor ) .


<s> return new <ISA_LIT>WinCOFFStreamer ( Context , MAB , * Emitter ,


<s> int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT>


<s> rtx constv , unspec ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned int elt = <NUM_LIT> - ( sel [ i ] & <NUM_LIT> ) ; perm [ i ] = GEN_INT ( elt ) ; } if ( ! REG_P ( op0 ) ) op0 = force_reg ( V16QImode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( V16QImode , op1 ) ; constv = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( <NUM_LIT> , perm ) ) ; constv = force_reg ( V16QImode , constv ) ; unspec = gen_rtx_UNSPEC ( V16QImode , gen_rtvec ( <NUM_LIT> , op1 , op0 , constv ) , UNSPEC_VPERM ) ; if ( ! REG_P ( target ) ) { rtx tmp = gen_reg_rtx ( V16QImode ) ; emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target ,


<s> static const TargetAsmInfo * createTargetAsmInfo ( const Target & T , const StringRef & TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>DarwinTargetAsmInfo ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : return new <ISA_LIT>COFFTargetAsmInfo ( TheTriple ) ; case Triple :: Win32 : return new <ISA_LIT>WinTargetAsmInfo ( TheTriple ) ; default : return new <ISA_LIT>ELFTargetAsmInfo (


<s> return DisableFramePointerElim ( MF ) || MFI


<s> bool Changed = false ; const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineFunction :: iterator MBBI = MF . begin ( ) ; MachineFunction :: iterator EndMBB = MF . end ( ) ; for ( ; MBBI != EndMBB ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI ) { for ( BasicBlock :: const_iterator II = SI -> begin ( ) ; ( PN = dyn_cast < PHINode > ( II ) ) ; ++ II ) { if ( PN -> getType ( ) == Type :: get<ISA_LIT>_FP80Ty ( LLVMBB -> getContext ( ) ) || ( ! Subtarget . hasSSE1 ( ) && PN -> getType ( ) -> isFloatingPointTy ( ) ) || ( ! Subtarget . hasSSE2 ( ) && PN -> getType ( ) == Type :: getDoubleTy ( LLVMBB -> getContext ( ) ) ) ) { ContainsFPCode = true ; break ; } } } } if ( ContainsFPCode ) { BuildMI ( * MBB , MBBI -> getFirstTerminator ( ) , DebugLoc :: getUnknownLoc ( ) , MF . getTarget ( )

. getInstrInfo ( ) -> get ( <STR_LIT> ) ) ;


<s> MachineInstr & Pred = * SU . getInstr ( ) ; if ( ! shouldScheduleAdjacent ( ST , & Pred , Branch ) ) continue ; bool Success = DAG -> addEdge ( & ExitSU , SDep ( & SU , SDep :: Cluster ) ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; for ( SDep & PredDep : ExitSU . Preds ) if ( PredDep . getSUnit ( ) == & SU ) PredDep . setLatency ( <NUM_LIT> ) ; for ( SDep & SuccDep : SU . Succs ) if ( SuccDep . getSUnit

( ) == & ExitSU ) SuccDep . setLatency ( <NUM_LIT> ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val


<s> if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) ==

MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ;


<s> for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality ::


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return


<s> return vabsq_f32 ( __a ) < vabsq_f32 (


<s> static SDValue PerformBUILD_VECTORCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { SelectionDAG & DAG = DCI . DAG ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) if ( SDValue RV = PerformVMOVDRRCombine ( N , DAG ) ) return RV ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( i ) ) ; Ops . push_back ( V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue BV = DAG . getBuildVector ( FloatVT , dl , Ops ) ; return DAG . getNode ( <STR_LIT> ,


<s> static DecodeStatus DecodeSPE4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst ,


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; std :: string LayoutStr = A64VectorLayoutToString ( Layout ) ; O << <STR_LIT> ; if ( Count > <NUM_LIT> ) { bool IsVec64 = ( Layout < <STR_LIT> ) ? true : false ; unsigned SubRegIdx = IsVec64 ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Count ; I ++ ) { std :: string Name = getRegisterName ( MRI . getSubReg ( Reg , SubRegIdx ++ ) ) ; Name [ <NUM_LIT> ] = 'v' ; O << Name << LayoutStr ; if ( I != Count - <NUM_LIT>


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CCOut ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc =


<s> int64_t Value = ConstExpr -> getValue ( ) ; return ( ( Value & ~ <NUM_LIT> )


<s> return TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( STI . isR9Reserved ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> -


<s> if ( CmpI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = true ; return true


<s> void addMemNoOffsetT2NoSpOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg


<s> return CCZmode ; case GE : case LT : return CCNmode ; case GT : case LE : return CCNZmode ; case GEU : case GTU : case LEU : case LTU : return


<s> if ( ! Load . hasOneUse ( ) ) return false ; if ( LoadNode -> getBasePtr ( ) != StoreNode -> getBasePtr ( ) || LoadNode -> getOffset ( ) != StoreNode -> getOffset ( ) ) return false ; SDValue Chain = StoreNode -> getChain ( ) ; bool ChainCheck = false ; if ( Chain == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; InputChain = LoadNode -> getChain ( ) ; } else if ( Chain . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > ChainOps ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) { SDValue Op = Chain . getOperand ( i ) ; if ( Op == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } int LoadId = LoadNode -> getNodeId ( ) ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = UI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getNodeId ( ) > LoadId ) return false ; } ChainOps . push_back ( Op ) ; } if ( ChainCheck ) InputChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Chain ) , <STR_LIT> , ChainOps ) ; } if ( ! ChainCheck )


<s> if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { APInt immRaw = VFPExpandImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) , Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; APFloat immFP = APFloat ( immRaw , true ) ; double imm = Opcode == <STR_LIT> ? immFP . convertToDouble ( ) : immFP . convertToFloat (


<s> MCOperand lowerSymbolOperandDarwin ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand lowerSymbolOperandELF ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand lowerSymbolOperandCOFF ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI , MRI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( MAI ,


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( ( Imm & <NUM_LIT> ) >> <NUM_LIT>


<s> default : return ParseMemOperand ( ) ; case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return <NUM_LIT> ; return <STR_LIT> ( RegNo , Start , End ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; Parser . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . ParseExpression ( Val , End ) ) return <NUM_LIT> ; return <STR_LIT> ( Val , Start


<s> if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data (


<s> StringRef Name = Sym -> getName ( ) ; Triple TT ( TM . getTargetTriple ( ) ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( ( TT . isWindowsGNUEnvironment ( ) || TT . isWindowsCygwinEnvironment ( ) ) && ( Name [ <NUM_LIT> ] == getDataLayout ( ) . getGlobalPrefix ( ) ) ) Name = Name . drop_front ( ) ; OS << Name ; if ( IsData ) { if ( TT . isKnownWindowsMSVCEnvironment (


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( Subtarget . hasPAuth ( ) && MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . setMIFlag ( MachineInstr


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X (


<s> assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( MFI -> hasVarSizedObjects ( ) && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( MFI -> hasVarSizedObjects ( ) ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else FrameReg = RegInfo -> getBaseRegister ( ) ; } else if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter :: getOSABI ( TheTriple .


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create


<s> int i [ <NUM_LIT> ] ; } x ; vec_uchar16 mask ; count = <NUM_LIT> - count ; x . i [ <NUM_LIT> ] = count <<


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex


<s> rtl_opt_pass * make_pass_insert_bti ( gcc :: context * ctxt ) { return new pass_insert_bti


<s> if ( Info . IsFixed ) Res = AssignFn ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ; else Res = AssignFnVarArg ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ; StackSize = State . getNextStackOffset (


<s> unsigned RR = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src , false ) ; if ( RR ==