<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TM . is<ISA_LIT>64 ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . is<ISA_LIT>64 ( ) && IsPositionIndependent )


<s> return ( __A [ <NUM_LIT> ] <= __B [ <NUM_LIT> ]


<s> bool hasCn<ISA_LIT> ( ) const { return STI . getFeatureBits ( ) [


<s> Ops . insert ( Ops . end ( ) , Opcodes . begin ( ) , Opcodes . end ( ) ) ; OpBegins . push_back ( OpBegins . back ( )


<s> AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return false


<s> rtx op1 , addr ; extract_insn_cached ( insn ) ; op1 = recog_data . operand [ <NUM_LIT> ] ; if ( CONSTANT_P ( op1 ) ) return true ; if ( GET_CODE ( op1 ) == ZERO_EXTEND || GET_CODE ( op1 ) == SIGN_EXTEND ) op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) != MEM ) return false ; addr = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; return GET_CODE ( addr


<s> sty = aarch64_classify_symbol ( base , offset , SYMBOL_CONTEXT_ADR ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_GOTTPREL : case SYMBOL_SMALL_GOT : case SYMBOL_TINY_GOT : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_TPREL : case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( VOIDmode , dest


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT>


<s> static bool mips_valid_lo_sum_p ( enum mips_symbol_type symbol_type , machine_mode mode ) { if ( mips_symbol_insns ( symbol_type , mode ) == <NUM_LIT> ) return false ; if ( mips_lo_relocs [ symbol_type ] == NULL ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) >

GET_MODE_ALIGNMENT ( mode ) ) return false ;


<s> return llvm :: all_of ( MBB . successors ( ) , [ ] ( const MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) ; } ) && std :: all_of ( MBBI , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI .


<s> if ( <STR_LIT> ( Mask . getNode ( ) ) ) return Pg ; auto Op1 = convertToScalableVector ( DAG , ContainerVT , Mask ) ; auto Op2 = DAG . getConstant ( <NUM_LIT> , DL ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateContextImm ( int64_t Val , SMLoc S , SMLoc E , bool Is<ISA_LIT>64 ) { auto Op = make_unique < <ISA_LIT>Operand > ( ContextImmediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 = Is<ISA_LIT>64 ; return Op


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> std :: unique_ptr < MCObjectWriter > create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream & OS ) { auto MOTW = llvm :: make_unique <


<s> for ( unsigned i = <NUM_LIT> , e = RegInfo -> getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RegInfo -> getRegClass ( Reg ) == & <STR_LIT> ) { HasVectorVReg = true ; break ; } } if ( ! HasVectorVReg ) return ; unsigned InVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; unsigned UpdatedVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & EntryBB = * Fn . begin ( ) ; DebugLoc dl ; MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ; BuildMI ( EntryBB , IP , dl , TII .


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage (


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; if ( ! IsPositionIndependent ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( ! IsPositionIndependent )


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS4Operand ( const MachineInstr * MI , int Op ) { printThumbAddrModeRI5Operand ( MI ,


<s> } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false


<s> InsertNOPsLoadStore = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return *


<s> int cost = <NUM_LIT> ; addrtype = crx_decompose_address ( addr , & address ) ; gcc_assert ( addrtype != CRX_INVALID ) ; if ( addrtype == CRX_ABSOLUTE ) cost += <NUM_LIT> ; if ( addrtype == CRX_POST_INC ) cost -= <NUM_LIT> ; if ( address . base ) cost ++ ; if ( address . index && address . scale == <NUM_LIT> ) cost += <NUM_LIT> ; if ( address . disp && ! INT_CST4 ( INTVAL ( address . disp ) ) ) cost += <NUM_LIT> ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , cost ) ; debug_rtx ( addr


<s> return ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) ==


<s> if ( UndefLower && isSequentialOrUndefInRange ( Mask , HalfNumElts , HalfNumElts , <NUM_LIT> ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Hi , DAG . getIntPtrConstant ( HalfNumElts , DL ) ) ; } int HalfIdx1 = - <NUM_LIT> , HalfIdx2 = - <NUM_LIT> ; SmallVector < int , <NUM_LIT> > HalfMask ( HalfNumElts ) ; unsigned Offset = UndefLower ? HalfNumElts : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != HalfNumElts ; ++ i ) { int M = Mask [ i + Offset ] ; if ( M < <NUM_LIT> ) { HalfMask [ i ] = M ; continue ; } int HalfIdx = M / HalfNumElts ; int HalfElt = M % HalfNumElts ; if ( HalfIdx1 < <NUM_LIT> || HalfIdx1 == HalfIdx ) { HalfMask [ i ] = HalfElt ; HalfIdx1 = HalfIdx ; continue ; } if ( HalfIdx2 < <NUM_LIT> || HalfIdx2 == HalfIdx ) { HalfMask [ i ] = HalfElt + HalfNumElts ; HalfIdx2 = HalfIdx ; continue ; } return SDValue ( ) ; } assert ( HalfMask . size ( ) ==


<s> int pos = <NUM_LIT> ; int i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget . isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering ::


<s> bool isReg ( ) const override { return Kind


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL ,

<NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Expr ) ) { int16_t Val ; switch ( getVariantKind ( RelocStr ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : Val = MCE -> getValue ( ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : report_fatal_error ( <STR_LIT>


<s> if ( IsConstantImm ) IsValid = pred ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK


<s> int regno = REGNO ( SUBREG_P ( reg ) ? SUBREG_REG ( reg ) : reg ) ; if ( rtx note = find_regno_note ( src , REG_DEAD , regno

) ) add_shallow_copy_of_reg_note ( dst , note ) ;


<s> static DecodeStatus DecodePCRelLabel19 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { int64_t ImmVal = Imm ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( (


<s> return ( poly128_t ) __builtin_neon_vreinterprettiv2di ( ( int64x2_t


<s> case <STR_LIT> : if ( Use -> isMachineOpcode ( ) ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , Use -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) ; continue ; case <STR_LIT> : { if ( Use -> isMachineOpcode ( ) ) return <NUM_LIT> ; StoreSDNode * STN = cast < StoreSDNode > ( * Use ) ; unsigned MemVTSize = STN -> getMemoryVT ( ) . getSizeInBits ( ) ; if ( MemVTSize == <NUM_LIT> || Use . getOperandNo ( ) != <NUM_LIT> ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , MemVTSize ) ; continue ; } case <STR_LIT> : case <STR_LIT> : case


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc


<s> const <ISA_LIT>InstrRelaxTableEntry * llvm :: lookupShortTable ( unsigned RelaxOp ) { auto & Table = ShortTable -> Table ; auto I = llvm :: lower_bound ( Table


<s> static SDValue PromoteMVEPredVector ( SDLoc dl , SDValue Pred , EVT VT , SelectionDAG & DAG ) { SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue AllZeroes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllZeroes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> , reg_names [


<s> SDValue Parts [ <NUM_LIT> ] ; auto getMovIdx = [ ] ( ArrayRef < int > ShuffleMask , int Start , int Length ) { int MovIdx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Length ; i ++ ) { if ( ShuffleMask [ Start + i ] >= <NUM_LIT> ) { if ( ShuffleMask [ Start + i ] % Length != i ) return - <NUM_LIT> ; MovIdx = ShuffleMask [ Start + i ] / Length ; break ; } } if ( MovIdx == - <NUM_LIT> ) return - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Length ; i ++ ) { if ( ShuffleMask [ Start + i ] >= <NUM_LIT> && ( ShuffleMask [ Start + i ] / Length != MovIdx || ShuffleMask [ Start + i ] % Length != i ) ) return - <NUM_LIT> ; } return MovIdx ; } ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) { int Elt = getMovIdx ( ShuffleMask , Part * QuarterSize , QuarterSize ) ; if ( Elt != - <NUM_LIT> ) { SDValue Input = Op -> getOperand ( <NUM_LIT>


<s> assert ( Fixup . getOffset ( ) + Size <= Data . size ( ) && <STR_LIT> ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; if ( ( Target . isAbsolute ( ) || IsResolved ) && getFixupKindInfo ( Fixup . getKind ( ) ) . Flags & MCFixupKindInfo :: FKF_IsPCRel ) { if ( Size > <NUM_LIT> && ! isIntN ( Size * <NUM_LIT> , SignedValue ) ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SignedValue ) + <STR_LIT> + Twine ( Size ) + ( ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; } else { assert ( ( Size == <NUM_LIT> || isIntN ( Size * <NUM_LIT>

+ <NUM_LIT> , SignedValue ) ) && <STR_LIT> ) ;


<s> else if ( TARGET_PA_20 ) aputs ( <STR_LIT> ) ; else if ( TARGET_PA_11 ) aputs


<s> EVT VT = LHS . getValueType ( ) ; EVT CondVT = Cond . getValueType ( ) ; SDLoc DL ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( CondVT . isVector ( ) && <STR_LIT> ) ; bool FValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; if ( FValIsAllZeros && Subtarget . hasAVX512 ( ) && Cond . hasOneUse ( ) && CondVT . getVectorElementType ( ) == <STR_LIT> ) { SDValue CondNew = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , DAG . getAllOnesConstant ( DL , CondVT ) ) ; return DAG . getSelect ( DL , VT , CondNew , RHS , LHS ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( TValIsAllOnes && FValIsAllZeros ) return DAG


<s> if ( opts -> x_flag_omit_frame_pointer == <NUM_LIT> ) opts -> x_flag_omit_frame_pointer = <NUM_LIT> ; if ( ! opts -> x_optimize_size ) { if ( opts -> x_align_loops <= <NUM_LIT> ) opts -> x_align_loops = aarch64_tune_params . loop_align ; if ( opts -> x_align_jumps <= <NUM_LIT> ) opts -> x_align_jumps = aarch64_tune_params . jump_align ; if ( opts -> x_align_functions <= <NUM_LIT> ) opts -> x_align_functions = aarch64_tune_params . function_align ; } aarch64_pcrelative_literal_loads = false ; if ( opts -> x_pcrelative_literal_loads == <NUM_LIT> ) aarch64_pcrelative_literal_loads = true ; if ( aarch64_cmodel == AARCH64_CMODEL_TINY || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC ) aarch64_pcrelative_literal_loads = true ; if ( flag_mlow_precision_sqrt ) flag_mrecip_low_precision_sqrt =


<s> static bool isPromotableZeroStoreOpcode ( MachineInstr * MI ) { return isPromotableZeroStoreOpcode ( MI -> getOpcode ( )


<s> void printi256mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo ,


<s> return __builtin_loongson_pmuluw ( s


<s> struct aarch64_address_info addr ; unsigned int size , vec_flags ; if ( GET_MODE ( x ) != Pmode && ( ! CONST_INT_P ( x ) || trunc_int_for_mode ( INTVAL ( x ) , Pmode ) != INTVAL ( x ) ) ) { output_operand_lossage ( <STR_LIT> ) ; return false ; } if ( aarch64_classify_address ( & addr , x , mode , true , type ) ) switch ( addr . type ) { case ADDRESS_REG_IMM : if ( known_eq ( addr . const_offset , <NUM_LIT> ) ) { asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] ) ; return true ; } vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_ANY_SVE ) { HOST_WIDE_INT vnum = exact_div ( addr . const_offset , aarch64_vl_bytes ( mode , vec_flags ) ) . to_constant ( ) ; asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , vnum ) ; return true ; } asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , INTVAL ( addr . offset ) ) ; return true ; case ADDRESS_REG_REG : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , reg_names [ REGNO ( addr . offset ) ] ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , reg_names [ REGNO ( addr . offset ) ] , addr . shift ) ; return true ; case ADDRESS_REG_UXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return true ; case ADDRESS_REG_SXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return true ; case ADDRESS_REG_WB : size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; switch ( GET_CODE ( x ) ) { case PRE_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case POST_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return true ; case PRE_DEC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , size ) ; return


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat ( ) const { return true


<s> if ( VT == <STR_LIT> ) return <NUM_LIT> ; unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT>


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } } if ( Size >= <NUM_LIT>


<s> assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << TRI -> getAsmName ( MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT>


<s> return __builtin_aarch64_frintnv4sf (


<s> if ( ! MEM_P ( op ) ) return false ; if ( offsettable_address_p ( true , GET_MODE ( op ) , XEXP ( op , <NUM_LIT> ) )


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum , O ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum , O ) ; return false


<s> <ISA_LIT>GOTEntry * <ISA_LIT>GOT :: createGOTPLT ( ) { <ISA_LIT>GOTEntry * entry = new <ISA_LIT>GOTEntry (


<s> if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Val & ( <NUM_LIT> << i ) ) { if ( CLRM ) { if ( ! Check ( S , DecodeCLRMGPRRegisterClass ( Inst , i , Address , Decoder ) ) ) { return MCDisassembler :: Fail ; } } else { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , i , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( NeedDisjointWriteback && WritebackReg == Inst . end ( ) [ - <NUM_LIT> ] . getReg

( ) ) Check ( S , MCDisassembler :: SoftFail ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> static void emit_soft_tfmode_unop ( enum rtx_code code ,


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI


<s> ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = (


<s> if ( ! IsVerboseAsm ) { OS << '\n' ; return ; } EmitCommentsAndEOL (


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) return getAddrNonPIC ( N , SDLoc ( N


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment (


<s> Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue LoVal = Addr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) || isa < GlobalAddressSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = LoVal . getOperand ( <NUM_LIT> ) ; return true


<s> buf -> isa_level = pInfo . m_IsaLevel ; buf -> isa_rev = pInfo . m_IsaRev ; buf -> gpr_size = pInfo . m_GprSize ; buf -> cpr1_size = pInfo . m_Cpr1Size ; buf -> cpr2_size = pInfo . m_Cpr2Size ; buf -> fp_abi = pInfo . m_FpAbi ; buf -> isa_ext = pInfo . m_IsaExt ; buf -> ases = pInfo . m_Ases ; buf -> flags1 = pInfo . m_Flags1 ; buf -> flags2 = <NUM_LIT> ; return size (


<s> unsigned RA = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( OR ) , RA )

. addReg ( TargetReg ) . addReg ( ZERO ) ;


<s> static bool pa_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( from == to ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return TARGET_64BIT && from == DImode && to == SImode ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return


<s> if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getNode ( <STR_LIT> , DL , VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ] = <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Shuffle ) ; }


<s> return ( vector signed char ) __builtin_altivec_vsel_4si ( ( vector signed int ) a1 , ( vector signed int ) a2


<s> Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; if ( NewOp == <STR_LIT> ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; } SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops . data ( ) , Ops . size ( ) , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue


<s> CCAssignFn * CallerAssignFnVarArg ; std :: tie ( CallerAssignFnFixed , CallerAssignFnVarArg ) = getAssignFnsForCC ( CallerCC , TLI ) ; if ( ! resultsCompatible ( Info , MF , InArgs , * CalleeAssignFnFixed , * CalleeAssignFnVarArg , * CallerAssignFnFixed , * CallerAssignFnVarArg ) ) return false ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; const uint32_t * CalleePreserved = TRI -> getCallPreservedMask


<s> MIB . buildStore ( Val , MI . getOperand ( <NUM_LIT> ) , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VaListSize , Align ( PtrSize ) ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { MachineIRBuilder & MIB = Helper . MIRBuilder ; MIB . buildConstant ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } } return true


<s> static rtx aarch64_gen_unspec_cond ( rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtvec vec = gen_rtvec ( <NUM_LIT> ,


<s> unsigned Reg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( Reg , true ) , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst


<s> static bool sh_cannot_substitute_mem_equiv_p ( rtx ) { if ( TARGET_SHMEDIA ) return false ; return


<s> SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Mask = APInt :: getAllOnesValue ( BitWidth ) , Zeros , Ones ; DAG . ComputeMaskedBits ( Op0 , Mask , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode (


<s> else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { if ( isCN ) { if ( Predicate_immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } else { if ( isCN ) { if ( Predicate_immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { Opc = <STR_LIT> ; if ( isCN ) { if ( Predicate_immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( Predicate_i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } else { Opc = <STR_LIT> ; if ( isCN ) { if ( Predicate_immSext8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( Predicate_i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } break ; } DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; if ( isInc || isDec ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Chain } ; SDValue Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Ret ) -> setMemRefs (


<s> int64_t Size ; if ( getParser ( ) . parseAbsoluteExpression ( Size ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( ) ; getStreamer ( ) . EmitWinCFIAllocStack ( Size , Loc ) ; return


<s> if ( ! N -> isMachineOpcode ( ) ) return false ; DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( N -> getMachineOpcode ( ) ) ; if ( I == MemOp2RegOpTable . end ( ) ) return false ; unsigned Opc = I -> second . first ; unsigned Index = I -> second . second & <NUM_LIT> ; bool FoldedLoad = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; bool FoldedStore = I -> second . second & ( <NUM_LIT> << <NUM_LIT> ) ; const TargetInstrDesc & TID = get ( Opc ) ; const TargetRegisterClass * RC = TID . OpInfo [ Index ] . getRegClass ( & RI ) ; unsigned NumDefs = TID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUnalignedMemAccessFast ( ) ) return false ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= <NUM_LIT> ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , TM ) , dl , VT , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back ( Load ) ; cast < MachineSDNode > ( Load ) -> setMemRefs ( MMOs . first , MMOs . second ) ; } std :: vector < EVT


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return Expand2AddrUndef ( MI , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> )


<s> static SDValue materializeVectorConstant ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return Op ; if ( Subtarget . hasSSE2 ( ) && <STR_LIT> ( Op . getNode ( ) ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> || VT


<s> Optional < unsigned > MaxNumVScale = getMaxVScale ( ) ; assert ( MaxNumVScale && <STR_LIT> )


<s> TSTInst . setOpcode ( <STR_LIT> ) ; TSTInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm (


<s> static __inline vec_ushort8 spu_sumb ( vec_uchar16 a , vec_uchar16 b ) { return ( ( vec_ushort8 ) ( si_sumb ( ( qword ) ( a ) ,


<s> Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } assert ( SrcVT . getSizeInBits ( ) == <NUM_LIT> * VT . getSizeInBits ( ) ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( NumSrcElts ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( NumSrcElts ) ) ; unsigned Imm = Src . MinElt * getExtFactor ( VEXTSrc1 ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy ) continue ; assert ( ShuffleVT . getVectorElementType ( ) == SmallestEltTy ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , ShuffleVT , Src . ShuffleVec ) ; Src . WindowScale = SrcEltTy . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; Src . WindowBase *= Src . WindowScale ; } DEBUG ( for ( auto Src : Sources ) assert ( Src . ShuffleVec . getValueType ( ) == ShuffleVT ) ; ) ; SmallVector < int , <NUM_LIT> > Mask ( ShuffleVT . getVectorNumElements ( ) , - <NUM_LIT> ) ; int BitsPerShuffleLane = ShuffleVT . getVectorElementType ( ) . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) ==


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: matchAnyRegisterWithoutDollar ( OperandVector & Operands , SMLoc S ) { auto Token = Parser . getLexer ( ) . peekTok ( false ) ; if ( Token . is ( AsmToken :: Identifier ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; StringRef Identifier = Token . getIdentifier ( ) ; OperandMatchResultTy ResTy = matchAnyRegisterNameWithoutDollar ( Operands , Identifier , S ) ; return ResTy ; } else if ( Token . is (


<s> static bool isPreIncrementForm ( const MCInst * MI , int


<s> assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ; return ; } O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TRI -> getAsmName ( MO1 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> (

<STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> return ( uint64x1_t ) { vcvtd_u64_f64 ( __a


<s> void emitTCEntry ( const MCSymbol & S


<s> bool useSoftFloat ( ) const { if ( isAIXABI ( ) && ! HasHardFloat ) report_fatal_error ( <STR_LIT> ) ; return !


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _m_empty ( void ) { _mm_empty (


<s> void <ISA_LIT>SEInstrInfo :: expandPseudoMTLoHi ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned LoOpc , unsigned HiOpc , bool HasExplicitDef ) const { DebugLoc DL = I -> getDebugLoc ( ) ; const MachineOperand & SrcLo = I -> getOperand ( <NUM_LIT> ) , & SrcHi = I -> getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LoInst = BuildMI ( MBB , I , DL , get ( LoOpc ) ) ; MachineInstrBuilder HiInst = BuildMI ( MBB , I , DL , get ( HiOpc ) ) ; if ( HasExplicitDef ) { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = getRegisterInfo ( ) .


<s> return TLI . isPositionIndependent ( )


<s> static SDValue getEstimate ( const <ISA_LIT>Subtarget * ST , unsigned Opcode , SDValue Operand , SelectionDAG & DAG , int & ExtraSteps ) { EVT VT = Operand . getValueType ( ) ; if ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) { if ( ExtraSteps == TargetLoweringBase :: ReciprocalEstimate :: Unspecified ) ExtraSteps = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( Opcode , SDLoc (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( ShiftExtend . Amount )


<s> return ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks


<s> if ( ! Flags . isSRet ( ) || Flags . isInReg ( ) ) return false ; if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return false ; if ( Subtarget . isTargetMCU ( ) ) return false ; return


<s> <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new <ISA_LIT>MachineLegalizer ( ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new <ISA_LIT>InstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( *


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return encodeThumbBLOffset ( MO .


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM


<s> enum machine_mode mode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != mode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate )

( target , mode ) ) return gen_reg_rtx ( mode ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed


<s> SDValue Lane = Op . getOperand ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> && Vec . getValueType ( ) . getVectorElementType ( )

. getSizeInBits ( ) < <NUM_LIT> && <STR_LIT> ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeSmallCMGlobalValue ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_GLOBAL_VALUE ) ; auto GV = MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) return true ; auto & TM = ST -> getTargetLowering ( ) -> getTargetMachine ( ) ; unsigned OpFlags = ST -> ClassifyGlobalReference ( GV , TM ) ; if ( OpFlags & <STR_LIT> ) return


<s> x . q = q ; return ( x . f [ <NUM_LIT> ]


<s> return __builtin_aarch64_sshlv2di ( __a ,


<s> if ( RB . getID ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( RB . getID ( ) == <STR_LIT> ) return OpSize == <NUM_LIT> ? & <STR_LIT> : STI . has<ISA_LIT>32r6 ( ) || STI . isFP64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; llvm_unreachable ( <STR_LIT>


<s> EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( isTypeLegal ( V . getValueType ( ) ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V ) ) ; } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ( ! V . getValueType ( ) . isVector ( ) || V . getValueType ( ) .


<s> size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE &&


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { PM -> add ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( Kind == KindImmTLS && <STR_LIT> ) ; addExpr ( Inst , ImmTLS .


<s> return ( int8x8_t ) __builtin_neon_vshrs_nv8qi ( __a ,


<s> HOST_WIDE_INT mode_align = ix86_static_rtx_alignment ( mode ) ; return MAX ( mode_align , align ) ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= <NUM_LIT> && align

< BITS_PER_WORD ) return BITS_PER_WORD ;


<s> unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs ) return ; MVT RegTy = <STR_LIT> ( GPRSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I <


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseProcIFlagsOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag


<s> if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , <NUM_LIT> , NULL ) ) ; assemble_align (


<s> FunctionPass * llvm :: create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>BaseTargetMachine & TM , MachineCodeEmitter &


<s> } unsigned FirstVT = ( unsigned ) <STR_LIT> ; unsigned LastVT = ( unsigned ) <STR_LIT> ; for ( unsigned VT0 = FirstVT ; VT0 <= LastVT ; ++ VT0 ) { for ( unsigned VT1 = FirstVT ; VT1 <= LastVT ; ++ VT1 ) setTruncStoreAction ( ( <STR_LIT> ) VT0 , ( <STR_LIT> ) VT1 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; setLoadExtAction ( <STR_LIT> , ( <STR_LIT> ) VT0 , Expand ) ; } setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; } if ( Subtarget -> hasDSPR2 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget -> hasMSA ( ) ) { addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAIntType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; addMSAFloatType ( <STR_LIT> , & <STR_LIT> ) ; } if ( ! Subtarget -> mipsSEUsesSoftFloat ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( ! Subtarget -> isSingleFloat ( ) ) { if ( Subtarget -> isFP64bit ( ) ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Has<ISA_LIT>64


<s> void <ISA_LIT>InstPrinter :: printSVEPattern ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( auto Pat = <STR_LIT> ( Val ) ) O << Pat -> Name ; else O << '#' << formatImm ( Val


<s> SDValue Pg = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; <STR_LIT> CC = changeTestCCTo<ISA_LIT>CC ( Pred ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Pg , V ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> bool R12AvailableInBlock = LRU . available ( <STR_LIT> ) ; bool CPSRAvailableInBlock = LRU . available ( <STR_LIT> ) ; if ( R12AvailableInBlock && CPSRAvailableInBlock ) Flags |= MachineOutlinerMBBFlags :: UnsafeRegsDead ; LRU . addLiveOuts ( MBB ) ; if ( R12AvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( CPSRAvailableInBlock && ! LRU . available ( <STR_LIT> ) ) return false ; if ( any_of ( MBB , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ; bool LRIsAvailable = MBB . isReturnBlock ( ) && ! MBB . back ( ) . isCall ( ) ? isLRAvailable ( getRegisterInfo ( ) , MBB . rbegin ( ) , MBB . rend ( ) ) : LRU . available ( <STR_LIT> ) ; if ( ! LRIsAvailable ) Flags |=

MachineOutlinerMBBFlags :: LRUnavailableSomewhere ;


<s> if ( isShiftedImm ( ) ) { Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> ) return false ; } else { Shift = <NUM_LIT> ; Expr = getImm


<s> if ( MO . isReg ( ) ) { rv = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; if ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) { rv = <NUM_LIT> >> rv ; } } else if ( MO . isImm ( ) ) { rv = MO . getImm ( ) ; } else if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) { unsigned Reloc = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) Reloc = <STR_LIT> ; else { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { assert ( MovePCtoLROffset && <STR_LIT> ) ; } switch ( MI . getOpcode ( ) ) { default : MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; } } MachineRelocation R ; if ( MO . isGlobal ( ) ) { R = MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue * > ( MO . getGlobal ( ) ) , <NUM_LIT> , isa < Function > ( MO . getGlobal ( ) ) ) ; } else if ( MO . isSymbol ( ) ) { R = MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getSymbolName ( ) , <NUM_LIT> ) ; } else if ( MO .


<s> const __v4si vzero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __asm__ ( <STR_LIT> : <STR_LIT> ( temp ) : <STR_LIT> ( rounded ) : ) ; temp = vec_mergeo ( temp , temp ) ; temp = vec_mergee ( temp , temp ) ; result = ( __v4si ) vec_vpkudum ( ( __vector long long ) temp , ( __vector long long ) vzero ) ; { const __v16qu pkperm = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; result = ( __v4si ) vec_perm ( ( __v16qu ) temp , ( __v16qu ) vzero , pkperm ) ; } return ( __m128i ) result


<s> const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; int regnum = FIRST_ARGUMENT_REGISTER ; assemble_start_function ( thunk_fndecl , fnname ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) regnum += <NUM_LIT> ; fprintf ( file , <STR_LIT> , reg_names [ regnum ] , ( int ) delta & <NUM_LIT> ) ; fputs ( <STR_LIT> , file


<s> if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL


<s> if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != <NUM_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && <STR_LIT> . hasSubClassEq ( RC ) ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT>


<s> gcc_assert ( ok ) ; if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; base = parts . base ; index = parts . index ; disp = parts . disp ; len = <NUM_LIT> ; if ( base && ! index && ! disp ) { if ( addr == stack_pointer_rtx || addr == arg_pointer_rtx || addr == frame_pointer_rtx || addr == hard_frame_pointer_rtx ) len = <NUM_LIT> ; } else if ( disp && ! base && ! index ) len = <NUM_LIT> ; else { if ( disp ) { if ( GET_CODE ( disp ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( disp ) , 'K' ) &&


<s> if ( WVT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! DAG . MaskedValueIsZero ( N1 , Mask17 ) || ! DAG . MaskedValueIsZero ( N0 , Mask17 ) ) return SDValue ( ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue


<s> return __arm_vreinterpretq_u16_f32 (


<s> SItype __umodsi3 ( SItype a , SItype b


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitCondStore ( MachineInstr * MI , MachineBasicBlock * MBB , unsigned StoreOpcode , unsigned STOCOpcode , bool Invert ) const { const <ISA_LIT>InstrInfo * TII = TM . getInstrInfo ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = MI -> getOperand ( <NUM_LIT> ) ; int64_t Disp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned IndexReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CCValid = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && TM . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) ; MI -> eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid

) . addImm ( CCMask ) . addMBB ( JoinMBB ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> )


<s> if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( ) ; else { assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; MAI = new <ISA_LIT>MCAsmInfoELF


<s> if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i < NumElems ; ++ i ) if (

! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ;


<s> const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MF ) ; BitVector CalleeSaveRegs ( RegInfo -> getNumRegs ( ) ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) CalleeSaveRegs . set ( CSRegs [ i ] ) ; BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ; for ( int AvailReg = Available . find_first ( ) ; AvailReg != - <NUM_LIT> ; AvailReg = Available . find_next ( AvailReg ) ) if ( ! CalleeSaveRegs . test ( AvailReg ) ) return AvailReg ; return


<s> if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB


<s> Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1 ) . addReg ( Op2 ) ) ; UpdateValueMap ( I


<s> if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data ( ) ) , Opcodes . size (


<s> address += get_jump_table_size ( table ) ; insn = table ; } } else if ( LABEL_P ( insn ) ) address += get_label_padding ( insn ) ; } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && BARRIER_P ( fix -> insn ) ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( BARRIER_P ( ftmp -> insn ) ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address ; gcc_assert ( ftmp ) ; max_address = minipool_vector_head -> max_address ; if ( ftmp -> address < max_address ) max_address = ftmp -> address + <NUM_LIT> ; last_barrier = create_fix_barrier ( last_added_fix , max_address ) ; } assign_minipool_offsets ( last_barrier ) ; while ( ftmp ) { if ( ! BARRIER_P ( ftmp -> insn ) && ( ( ftmp -> minipool = add_minipool_backward_ref ( ftmp ) ) == NULL ) ) break ; ftmp = ftmp -> next ; } for ( this_fix = fix ; this_fix && ftmp != this_fix ; this_fix = this_fix -> next ) if ( ! BARRIER_P ( this_fix -> insn )


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; printRegName ( O , Reg ) ; assert ( MO2 . isImm ( ) && <STR_LIT> ) ; printRegImmShift ( O , <STR_LIT> ( MO2 . getImm ( ) ) , <STR_LIT> ( MO2 . getImm


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM


<s> bool hasFPIdx ( ) const { return HasFPIdx


<s> <ISA_LIT>AsmLexer ( const Target & T , const MCRegisterInfo & MRI , const MCAsmInfo & MAI ) : <ISA_LIT>BaseAsmLexer ( T , MAI ) { InitRegisterMap ( &


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero (

) ) return N -> getOperand ( <NUM_LIT> ) ;


<s> Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; SDValue Ops [ ] = { CallResult . first , CallResult .


<s> switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op , Op0 , Op1 , Op2 , Op3 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2


<s> unsigned OverflowDestReg = <NUM_LIT> ; unsigned OffsetReg = <NUM_LIT> ; if ( ! UseGPOffset && ! UseFPOffset ) { OffsetDestReg = <NUM_LIT> ; OverflowDestReg = DestReg ; offsetMBB = nullptr ; overflowMBB = thisMBB ; endMBB = thisMBB ; } else { OffsetDestReg = MRI . createVirtualRegister ( AddrRegClass ) ; OverflowDestReg = MRI . createVirtualRegister ( AddrRegClass ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; overflowMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; offsetMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; endMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MF -> insert ( MBBIter , offsetMBB ) ; MF -> insert ( MBBIter , overflowMBB ) ; MF -> insert ( MBBIter , endMBB ) ; endMBB -> splice ( endMBB -> begin ( ) , thisMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , thisMBB -> end ( ) ) ; endMBB -> transferSuccessorsAndUpdatePHIs ( thisMBB ) ; thisMBB -> addSuccessor ( offsetMBB ) ; thisMBB -> addSuccessor ( overflowMBB ) ; offsetMBB -> addSuccessor ( endMBB ) ; overflowMBB -> addSuccessor ( endMBB ) ; OffsetReg = MRI . createVirtualRegister ( OffsetRegClass ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , UseFPOffset ? <NUM_LIT> : <NUM_LIT> ) . addOperand ( Segment ) . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( OffsetReg ) . addImm ( MaxOffset + <NUM_LIT> - ArgSizeA8 ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ( <STR_LIT> ) ) ) . addMBB ( overflowMBB ) ; } if ( offsetMBB ) { assert ( OffsetReg != <NUM_LIT> ) ; unsigned RegSaveReg = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , RegSaveReg ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , <NUM_LIT> ) . addOperand ( Segment ) . setMemRefs ( MMOBegin , MMOEnd ) ; unsigned OffsetReg64 = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , OffsetReg64 ) . addImm ( <NUM_LIT> ) . addReg ( OffsetReg ) . addImm ( <STR_LIT> ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , OffsetDestReg ) . addReg ( OffsetReg64 ) . addReg ( RegSaveReg ) ; unsigned NextOffsetReg = MRI . createVirtualRegister ( OffsetRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , NextOffsetReg )

. addReg ( OffsetReg ) . addImm ( UseFPOffset ? <NUM_LIT> : <NUM_LIT> ) ;


<s> return static_cast < <ISA_LIT>TargetStreamer & >


<s> if ( TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) || TT . isWindowsMSVCEnvironment ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSIAMCU ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ( ! TT . isArch64Bit ( ) && TT . isOSWindows ( ) ) || TT


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF ->

getTarget ( ) ) , TII ( * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) , TLI ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) {


<s> FromMask = APInt :: getLowBitsSet ( ToMask . getBitWidth ( ) , ToMask . countPopulation ( ) ) ; if ( From -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) ) { APInt Shift = cast < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; assert ( Shift . getLimitedValue ( ) < <NUM_LIT> && <STR_LIT> ) ; FromMask <<= Shift . getLimitedValue ( <NUM_LIT>


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Src , BitNo ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { KnownBits Known = DAG . computeKnownBits ( Op0 ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } Src = Op1 ; BitNo = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { Src = AndLHS . getOperand ( <NUM_LIT> ) ; BitNo = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal )


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT )


<s> MI . eraseFromParent ( ) ; Offset = StackOffset ( ) ; return true ; } int64_t NewOffset ; unsigned UnscaledOp ; bool UseUnscaledOp ; int Status = is<ISA_LIT>FrameOffsetLegal ( MI , Offset , & UseUnscaledOp , & UnscaledOp , & NewOffset ) ; if ( Status & <ISA_LIT>FrameOffsetCanUpdate ) { if ( Status & <ISA_LIT>FrameOffsetIsLegal ) MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( UseUnscaledOp ) MI . setDesc ( TII -> get ( UnscaledOp ) ) ; MI . getOperand ( ImmIdx ) . ChangeToImmediate ( NewOffset ) ; return !


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) || ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub =


<s> void setArgumentStackToRestore ( unsigned bytes ) { ArgumentStackToRestore =


<s> mem1 = operands [ <NUM_LIT> ] ; mem2 = operands [ <NUM_LIT> ] ; } if ( REGNO ( reg2 ) == REGNO ( reg1 ) + <NUM_LIT> ) return umips_load_store_pair_p_1 ( load_p , false , reg1 , mem1 , mem2 ) ; if ( REGNO ( reg1 ) == REGNO ( reg2 ) + <NUM_LIT> ) return


<s> case UNW_NAT_NONE : dummy_nat = <NUM_LIT> ; nat_addr = & dummy_nat ; break ; case UNW_NAT_MEMSTK : nat_mask = <NUM_LIT> << ( ( long ) addr & <NUM_LIT> ) / <NUM_LIT> ; break ; case UNW_NAT_REGSTK : nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = <NUM_LIT> << ia64_rse_slot_num ( addr ) ; break ; } } } else { addr = ia64_rse_skip_regs ( ( unsigned long * ) info -> bsp , regnum - <NUM_LIT> ) ; nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = <NUM_LIT> << ia64_rse_slot_num ( addr


<s> unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , BitsPerElement , Start , End ) ) { Start -= <NUM_LIT> - BitsPerElement ; End -= <NUM_LIT> - BitsPerElement ; MVT VecVT = <STR_LIT> ( <STR_LIT> ( BitsPerElement ) , <STR_LIT> / BitsPerElement ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( Start , DL , <STR_LIT> ) , DAG . getConstant (


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC &

target_sect . flag ( ) ) != <NUM_LIT> ) {


<s> LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm


<s> static unsigned getShuffleSHUFImmediate ( ShuffleVectorSDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; assert ( ( NumLaneElts == <NUM_LIT> || NumLaneElts == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Shift = ( NumLaneElts == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt %=


<s> AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; } if ( OpIx >= Operands . size ( ) ) return ; const bool IsWrite = ( OpIx != <NUM_LIT> ) ; InstrumentMemOperand ( Operands [ OpIx ] , AccessSize , IsWrite , Ctx ,


<s> if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( ConstExpr -> getValue ( ) & <NUM_LIT> ) ) ; else if ( isa < <ISA_LIT>MCExpr > ( getImm ( ) ) ) { const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr && SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCSymbolRefExpr > ( getImm ( ) ) ) { const MCSymbolRefExpr * SymbolRefExpr = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr && SymbolRefExpr -> getKind ( ) == MCSymbolRefExpr ::


<s> if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo *


<s> bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsRenamable ( false ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode (


<s> assert ( BeforePrev && <STR_LIT> ) ; MachineFunction * F = BB -> getParent ( ) ; BB -> moveBefore ( Before ) ; auto FixFallthrough = [ & ] ( MachineBasicBlock * From , MachineBasicBlock * To ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> ) ; assert ( From -> isSuccessor ( To ) && <STR_LIT> ) ; MachineInstr & Terminator = * ( -- From -> terminators ( ) . end ( ) ) ; if ( ! Terminator . isUnconditionalBranch ( ) ) { MachineInstrBuilder MIB = BuildMI ( From , Terminator . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addMBB ( To ) ; MIB . addImm ( <STR_LIT> :: AL ) ; MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ; } } ; if ( BBPrevious -> isSuccessor ( BB ) ) FixFallthrough ( BBPrevious , BB ) ; if ( BeforePrev -> isSuccessor ( Before ) ) FixFallthrough ( BeforePrev , Before ) ; if ( BBNext && BB -> isSuccessor ( BBNext ) ) FixFallthrough ( BB , BBNext ) ; F -> RenumberBlocks


<s> if ( CmpOp0 . getValueType ( ) == <STR_LIT> ) { SDValue H0 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp0 ) ; SDValue L0 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp0 ) ; SDValue H1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue L1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue HRes = DAG . getNode ( Opcode , DL , <STR_LIT> , H0 , H1 ) ; SDValue LRes = DAG . getNode ( Opcode , DL


<s> else { assert ( NextVA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ; MemOpChains . push_back ( LowerMemOpCallTo ( Chain , StackPtr , fmrrd . getValue ( <NUM_LIT> ) , dl , DAG , NextVA ,


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ?


<s> int64_t Imm = <NUM_LIT> ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT>


<s> return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( Predicate_simm13 ( CN ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT>


<s> return ( ( AM5Opc >> <NUM_LIT> ) & <NUM_LIT> )


<s> const MachineOperand & MO = Br . getOperand ( I ) ; if ( MO . isMBB ( ) ) return MO . getMBB ( ) ; } assert ( false && <STR_LIT>


<s> if ( ! isImm ( ) ) return false ; if ( ! getImm ( ) . isAbsolute ( ) ) return true ; int64_t Value = getImm ( ) . getConstant ( ) ; return Value == ( int64_t ) ( int8_t )


<s> assert ( ( ! OptForMinSize || OptForSize ) && <STR_LIT> ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) == <STR_LIT> && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> useRetpoline ( ) && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> slowTwoMemOps ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || ! getTargetMachine ( ) . isPositionIndependent ( ) ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE


<s> auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS . getReg ( ) } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( RHS . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII ,


<s> return __builtin_ia32_comisdeq ( ( __v2df ) __A , ( __v2df )


IsComplex ) return NumVectorInstToHideOverhead ;


<s> Value * <ISA_LIT>IREmitter :: visitCALL_PRED ( const SDNode * N


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , TT ) ; if ( TT . isOSBinFormatXCOFF ( ) ) return new XCOFF<ISA_LIT>AsmBackend ( T , TT ) ; return new ELF<ISA_LIT>AsmBackend ( T ,


<s> case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case


<s> MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; dumpBBs ( ) ; ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ; verify (


<s> for ( int i = <NUM_LIT> , j = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j + NumElts / <NUM_LIT> ) ) return false ; if ( V2IsSplat ) { if ( isUndefOrEqual ( BitI1 , NumElts ) ) return false ; } else


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const TargetMachine & TM = getTargetMachine ( ) ; bool IsRO = isReadOnly ( GV ) ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) && ! Subtarget -> genExecuteOnly ( ) ) if ( SDValue V = promoteToConstantPool ( this , GV , DAG , PtrVT , dl ) ) return V ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , UseGOT_PREL ? <STR_LIT> : <NUM_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { SDValue RelAddr ; if ( Subtarget -> useMovt ( ) ) { ++ NumMovwMovt ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; RelAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; } else


<s> thumb1_const_print ( FILE * f , int regno ) { t_file =


<s> Promote = true ; break ; case <STR_LIT> : case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Commute = true ; case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote =


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand ::


<s> auto MIB = BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestReg ) ; if ( KillSrc ) { const MachineFunction * MF = MBB . getParent ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; MIB -> addRegisterKilled ( SrcReg , TRI ) ; } return ; } if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << ( <STR_LIT> - <NUM_LIT> ) ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = STI . hasVector ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> .

contains ( SrcReg ) ) Opcode = <STR_LIT> ;


<s> static StringRef select<ISA_LIT>CPU ( Triple TT , StringRef CPU ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: mips || TT . getArch ( ) == Triple :: mipsel ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } return CPU


<s> static DecodeStatus DecodeBlezlGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI


<s> return N0 -> hasOneUse ( ) && N1 -> hasOneUse ( ) && isZeroExtended ( N0 , DAG ) && isZeroExtended ( N1 , DAG ) ; } return false


<s> return ( __m128 ) __builtin_ia32_cmpnltss ( ( __v4sf ) __A , ( __v4sf )


<s> if ( fcode == AARCH64_BUILTIN_RNG_RNDR ) icode = CODE_FOR_aarch64_rndr ; else if ( fcode == AARCH64_BUILTIN_RNG_RNDRRS ) icode = CODE_FOR_aarch64_rndrrs ; else gcc_unreachable ( ) ; rtx rand = gen_reg_rtx ( DImode ) ; pat = GEN_FCN ( icode ) ( rand ) ; if ( ! pat ) return NULL_RTX ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx res_addr = expand_normal ( arg0 ) ; res_addr = convert_memory_address ( Pmode , res_addr ) ; rtx res_mem = gen_rtx_MEM ( DImode , res_addr ) ; emit_insn ( pat ) ; emit_move_insn ( res_mem , rand


<s> gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg =


<s> return ( uint32x4_t ) __builtin_neon_vceqv4si ( ( int32x4_t ) __a ,


<s> int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp =


<s> mep_note_pragma_flag ( funcname , FUNC_CALL


<s> return ( __m512h ) __builtin_ia32_vfmulcph512_mask_round ( ( __v32hf ) __B , (


<s> CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) AddDefaultPred ( MIB ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , false ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ; return true


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return <STR_LIT>


<s> rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; if ( aarch64_bti_enabled ( ) ) emit_insn ( gen_bti_c ( ) ) ; reload_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( vcall_offset == <NUM_LIT> ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - <NUM_LIT> ) ) == <NUM_LIT> ) ; addr = this_rtx ; if ( delta != <NUM_LIT> ) { if ( delta >= - <NUM_LIT> && delta < <NUM_LIT> ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - <NUM_LIT> && vcall_offset < <NUM_LIT> * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM


<s> machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return NULL_RTX ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return NULL_RTX ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 ) ; if ( pat ) emit_insn (


<s> HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false


<s> BBGen = make_unique < const MachineInstr * [ ] > ( NbReg ) ; std :: fill ( BBGen . get ( ) , BBGen . get ( ) + NbReg , nullptr ) ; BitVector & BBKillSet = Kill [ & MBB ] ; BBKillSet . resize ( NbReg ) ; for ( const MachineInstr & MI : MBB ) { bool IsADRP = MI . getOpcode ( ) == <STR_LIT> ; if ( IsADRP || ! ADRPMode ) for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ( ! ADRPMode && ! MO . isUse ( ) ) || ( ADRPMode && ( ! IsADRP || ! MO . isDef ( ) ) ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; CurReg = ItCurRegId -> second ; if ( ! BBGen [ CurReg ] && ! BBKillSet . test ( CurReg ) ) getSet ( ReachableUses , MBB , CurReg , NbReg ) . insert ( & MI ) ; if ( BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( & MI ) ; } for ( const MachineOperand & MO : MI .


<s> Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Call . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Call . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( Call . getNode ( ) , & Ops [ <NUM_LIT> ] ,


<s> struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; machine -> static_chain_stack_bytes =


<s> if ( Subtarget -> isThumb ( ) ) { if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; } if ( Subtarget -> useMovt ( ) ) return ForCodesize ? <NUM_LIT> : <NUM_LIT> ; return ForCodesize ? <NUM_LIT> :


<s> if ( ConstraintCode [ <NUM_LIT> ] == 'U' ) { switch ( ConstraintCode [ <NUM_LIT> ] ) { default : break ; case 'm' : return InlineAsm :: Constraint_Um ; case 'n' : return InlineAsm :: Constraint_Un ; case 'q' : return InlineAsm :: Constraint_Uq ; case 's' : return InlineAsm :: Constraint_Us ; case 't' : return InlineAsm :: Constraint_Ut ; case 'v' : return InlineAsm :: Constraint_Uv ; case 'y'


<s> TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateImm ( <NUM_LIT> ) ; OutStreamer . EmitInstruction (


<s> SDValue Ops [ <NUM_LIT> ] = { LHS , RHS } ; CompareFlag = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; Opc = <STR_LIT> ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ; Opc = <STR_LIT> ; } return DAG . getNode ( Opc , dl , <STR_LIT> , Chain , Dest , DAG .

getConstant ( <ISA_LIT>CC , <STR_LIT> ) , CompareFlag ) ;


<s> return INVALID_REGNUM ; } return AX_REG ; } else if ( is_thiscall ) { if ( ! DECL_STATIC_CHAIN ( cfun -> decl ) ) return DX_REG ; return AX_REG ; } else if ( regparm < <NUM_LIT> ) { if ( ! DECL_STATIC_CHAIN ( cfun -> decl ) ) return CX_REG ; else { if ( regparm >= <NUM_LIT> ) { sorry ( <STR_LIT> <STR_LIT> ) ; return INVALID_REGNUM ; } return


<s> output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) ) ] ) ; } else gcc_unreachable (


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect


<s> } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = nullptr ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) return true ; OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = &


<s> return helper_sign_extend ( ( ( ( pValue >> <NUM_LIT> ) & <NUM_LIT> ) | ( ( pValue >> <NUM_LIT> ) & <NUM_LIT> ) | ( ( pValue >> <NUM_LIT> ) & <NUM_LIT>

) | ( pValue & <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>_32AsmBackend ( T , OSABI , CPU


<s> SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And10C = dyn_cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) if ( And10C -> getZExtValue ( ) == <NUM_LIT> ) { LHS = Op0 ; RHS = Op1 . getOperand ( <NUM_LIT> ) ; } } else if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { LHS = Op1 ; RHS = Op0 . getOperand


<s> case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; case TargetOpcode :: G_MEMCPY_INLINE : return Helper . tryEmitMemcpyInline ( MI ) ; case TargetOpcode :: G_MEMCPY : case TargetOpcode :: G_MEMMOVE : case TargetOpcode :: G_MEMSET : { unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; if ( Helper . tryCombineMemCpyFamily ( MI , MaxLen ) ) return true ; if ( Opc == TargetOpcode :: G_MEMSET ) return llvm :: <ISA_LIT>GISelUtils :: tryEmitBZero ( MI , B , EnableMinSize ) ; return false


<s> for ( int r = FIRST_GENERAL_REG ; r <= LAST_GENERAL_REG ; r ++ ) if ( TEST_HARD_REG_BIT ( * s , r ) ) return r ; return -


<s> default : changeFPCCToOR<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; assert ( CondCode2 == <STR_LIT> ) ; break ; case CmpInst :: FCMP_ONE : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : CondCode = <STR_LIT> ; CondCode2 =