<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { EVT Ty = Op . getValueType ( ) ; if ( Ty == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; } else if ( Ty . isVector ( ) && Ty . isInteger ( ) && isTypeLegal ( Ty ) ) { return DAG . getNode ( <STR_LIT> , dl , Ty , Op . getOperand ( <NUM_LIT> ) ) ; } else { report_fatal_error ( <STR_LIT> ) ; } } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op .


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( QFRegs [ getReg (


<s> PredicatedInsts . emplace ( MI , std :: make_unique <

PredicatedMI > ( MI , CurrentPredicates ) ) ;


<s> bool Changed = false ; SmallSetVector < Function * , <NUM_LIT> > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_DWARF_CFA ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction (


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel


<s> t = __ev_mwhsmi ( a , b ) ; return __ev_mwsmiaa ( t , ( ( __ev64_s32__ ) { <NUM_LIT> ,


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( ! MF . getTarget ( ) . isPositionIndependent ( ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( ABI . IsN32 ( ) ) { const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } assert ( ABI . IsO32 (


<s> Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Glue = End . getValue (


<s> static inline bool offset_below_red_zone_p ( HOST_WIDE_INT offset ) { return offset < ( DEFAULT_ABI == ABI_V4 ? <NUM_LIT> : TARGET_32BIT ? - <NUM_LIT> :


<s> <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel ::


<s> opts -> x_unaligned_access = ( TARGET_32BIT_P ( opts -> x_target_flags ) && arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ; } else if ( opts -> x_unaligned_access == <NUM_LIT> && ! ( arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; opts -> x_unaligned_access = <NUM_LIT> ; } if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_schedule_insns = <NUM_LIT> ; else opts -> x_flag_schedule_insns = to -> x_flag_schedule_insns ; if ( optimize_function_for_size_p ( cfun ) && TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_flag_shrink_wrap = false ; else opts -> x_flag_shrink_wrap = to -> x_flag_shrink_wrap ; if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_ipa_ra = <NUM_LIT> ; else opts -> x_flag_ipa_ra = to -> x_flag_ipa_ra ; if ( TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_inline_asm_unified = true ; if ( arm_stack_protector_guard == SSP_GLOBAL && opts -> x_arm_stack_protector_guard_offset_str


<s> unsigned getDPRCalleeSavedAreaSize ( ) const { return


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this , PM


<s> if ( TARGET_PORTABLE_RUNTIME ) return false ; return decl && targetm . binds_local_p


<s> fputs ( <STR_LIT> , file ) ; ASM_OUTPUT_LABEL ( file , name ) ; fputs ( DOUBLE_INT_ASM_OP , file ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; if ( DOT_SYMBOLS ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; if ( TREE_PUBLIC ( decl ) && ! DECL_WEAK ( decl ) ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; putc ( '\n' , file ) ; } } else ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; return ; } if ( TARGET_RELOCATABLE && ! TARGET_SECURE_PLT && ( get_pool_size ( ) != <NUM_LIT> || current_function_profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , buf ) ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , *


<s> unsigned RegOpsNum = isMem ( MI , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < <NUM_LIT> || SrcOpIdx1 > RegOpsNum ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < <NUM_LIT> || SrcOpIdx2 > RegOpsNum ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx1 = SrcOpIdx1 ; unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = RegOpsNum ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ; unsigned Op2Reg = MI -> getOperand ( CommutableOpIdx2 ) . getReg ( ) ; for ( CommutableOpIdx1 = RegOpsNum ; CommutableOpIdx1 > <NUM_LIT> ; CommutableOpIdx1 -- ) { if ( Op2Reg != MI -> getOperand ( CommutableOpIdx1 ) . getReg ( ) ) break ; } if ( CommutableOpIdx1 == <NUM_LIT> ) return false ; if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; } return getFMA3OpcodeToCommuteOperands ( MI , SrcOpIdx1


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { PrivateGlobalPrefix =


<s> SDValue <ISA_LIT>TargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; StoreSDNode * ST = cast < StoreSDNode > ( Op ) ; SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST ->


<s> emit_move_insn ( mem , gen_const_mem ( HImode , fnaddr ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , cxt ) ; mem = adjust_address ( m_tramp , SImode ,


<s> bool <ISA_LIT>DAGToDAGISel :: hasNoVMLxHazardUse ( SDNode * N ) const { if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability )


<s> static bool isSHUFPMask ( ArrayRef < int > Mask , EVT VT , bool HasFp256 , bool Commuted = false ) { if ( ! HasFp256 && VT . is256BitVector ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElems = NumElems / NumLanes ; if ( NumLaneElems != <NUM_LIT> && NumLaneElems != <NUM_LIT> ) return false ; unsigned HalfLaneElems = NumLaneElems / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElems ; l += NumLaneElems ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = Mask [ i + l ] ; unsigned RngStart = l + ( ( Commuted == ( i < HalfLaneElems ) ) ? NumElems : <NUM_LIT> ) ; if ( ! isUndefOrInRange ( Idx , RngStart , RngStart + NumLaneElems ) ) return false ; if ( NumElems != <NUM_LIT> || l == <NUM_LIT> || Mask


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype ) ,


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf (

asm_out_file , <STR_LIT> , SDATA_SECTION_ASM_OP ) ; \ in_section = in_sdata ; \ } \ }


<s> void <ISA_LIT>InstructionSelector :: renderLogicalImm32 ( MachineInstrBuilder & MIB , const MachineInstr & I , int OpIdx ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; uint64_t CstVal = I . getOperand ( <NUM_LIT> )


<s> MachineBasicBlock :: iterator begin ( ) const { return getStart (


<s> static bool aarch64_expand_sve_ld1rq ( rtx dest , rtx src ) { src = force_const_mem ( GET_MODE ( src ) , src ) ; if ( ! src ) return false ; if ( ! aarch64_sve_ld1rq_operand_p ( src ) ) { rtx addr = force_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; src = replace_equiv_address ( src , addr ) ; } machine_mode mode = GET_MODE ( dest ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_ld1rq ( mode , dest , src , ptrue ) ) ; return


<s> return new Emitter < MachineCodeEmitter > (


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S , OS )


<s> unsigned <ISA_LIT>TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , CC , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getFixedSizeInBits ( ) < RegisterVT . getFixedSizeInBits ( ) ? VT .

getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF


<s> auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , MemTy , inferAlignFromPtrInfo


<s> if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) && ! ( Size <= <NUM_LIT> && allUsersAreInFunctions ( GVar ) ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , <NUM_LIT> ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) ) { AFI -> markGlobalAsPromotedToConstantPool ( GVar ) ; AFI -> setPromotedConstpoolIncrease ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> ) ; } ++ NumConstpoolPromoted


<s> void tool_cleanup ( bool from_signal ATTRIBUTE_UNUSED ) { for ( int i = <NUM_LIT> ; i < num_temps ;

i ++ ) maybe_unlink ( temp_files [ i ] ) ;


<s> if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return isSupportedType ( Trunc -> getOperand ( <NUM_LIT> ) ) ; if ( auto * ZExt = dyn_cast < ZExtInst > ( V ) ) return isSupportedType ( ZExt -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! isSupportedType (


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget >


<s> ToPromote . insert ( Op32 . getNode ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> || Op32 . getMachineOpcode ( ) == <STR_LIT> ) { if ( ! isUInt < <NUM_LIT> > ( Op32 . getConstantOperandVal ( <NUM_LIT> ) ) ) return false ; ToPromote . insert ( Op32 . getNode ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> || Op32 . getMachineOpcode ( ) == <STR_LIT> ) { ToPromote . insert ( Op32 . getNode ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> || Op32 . getMachineOpcode ( ) == <STR_LIT> ) { ToPromote . insert ( Op32 . getNode ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> && Op32 . getConstantOperandVal ( <NUM_LIT> ) <= Op32 . getConstantOperandVal ( <NUM_LIT> ) ) { SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote1 ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 . getOperand ( <NUM_LIT> ) , ToPromote1 ) ) return false ; ToPromote . insert ( Op32 . getNode ( ) ) ; ToPromote . insert ( ToPromote1 . begin ( ) , ToPromote1 . end ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> || Op32 . getMachineOpcode ( ) == <STR_LIT> ) { unsigned B = Op32 . getMachineOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote1 ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 . getOperand ( B + <NUM_LIT> ) , ToPromote1 ) ) return false ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 . getOperand ( B + <NUM_LIT> ) , ToPromote1 ) ) return false ; ToPromote . insert ( Op32 . getNode ( ) ) ; ToPromote . insert ( ToPromote1 . begin ( ) , ToPromote1 . end ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> || Op32 . getMachineOpcode ( ) == <STR_LIT> ) { SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote1 ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 . getOperand ( <NUM_LIT> ) , ToPromote1 ) ) return false ; if ( ! isUInt < <NUM_LIT> > ( Op32 . getConstantOperandVal ( <NUM_LIT> ) ) ) return false ; ToPromote . insert ( Op32 . getNode ( ) ) ; ToPromote . insert ( ToPromote1 . begin ( ) , ToPromote1 . end ( ) ) ; return true ; } if ( Op32 . getMachineOpcode ( ) == <STR_LIT> ) { SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote1 , ToPromote2 ; bool Op0OK = Peephole<ISA_LIT>64ZExtGather ( Op32 . getOperand ( <NUM_LIT> ) , ToPromote1 ) ; bool Op1OK = Peephole<ISA_LIT>64ZExtGather ( Op32 . getOperand ( <NUM_LIT> ) , ToPromote2 ) ; if ( ! Op0OK && ! Op1OK )


<s> tmpInst . clear ( ) ; tmpInst . setOpcode ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( AtRegNum ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . setLoc ( IDLoc ) ; Out . emitInstruction ( tmpInst , * STI ) ; return


<s> NoAutoPaddingScope ( MCStreamer & OS ) : OS ( OS ) , OldAllowAutoPadding ( OS . getAllowAutoPadding ( ) ) { changeAndComment ( false


<s> if ( ! Fa . hasFnAttribute ( <STR_LIT> ) && ! Fb . hasFnAttribute ( <STR_LIT> ) ) { return true ; } if ( Fa . hasFnAttribute ( <STR_LIT> ) && Fb . hasFnAttribute ( <STR_LIT> ) ) { StringRef KeyA = Fa . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; StringRef KeyB = Fb . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; return KeyA . equals ( KeyB ) ; } if ( Fa . hasFnAttribute ( <STR_LIT> ) ) { StringRef KeyA = Fa . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; return KeyA . equals_lower


<s> return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return SrcReg ; case <STR_LIT> : { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) return <NUM_LIT> ; VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm


<s> return __builtin_ia32_vcvtqq2ph512_mask_round ( ( __v8di ) __C ,


<s> CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , PtrTy , TlsGetAddr , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV ,


<s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; Op -> Mem . Length = Length ; return Op


<s> assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; if ( MemVT == <STR_LIT> && Subtarget -> hasV5TEOps ( ) && ! Subtarget -> isThumb1Only ( ) && LD -> isVolatile ( ) ) { SDLoc dl ( N ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LD -> getChain ( ) , LD -> getBasePtr ( ) } , MemVT , LD


<s> static enum machine_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode


<s> SDValue <ISA_LIT>TargetLowering :: LowerGC_TRANSITION_END ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Op . getOperand


<s> static SDValue LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) { MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : return SDValue (


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) .


<s> return CustomExpandInstNaCl<ISA_LIT> ( Inst ,


<s> if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> InitMCCodeGenInfo ( RM ,


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; SmallPtrSet < const MachineBasicBlock * , <NUM_LIT> > JumpTableTargets ; if ( const MachineJumpTableInfo * JTI = MF . getJumpTableInfo ( ) ) for ( const MachineJumpTableEntry & JTE : JTI -> getJumpTables ( ) ) for ( const MachineBasicBlock * MBB : JTE . MBBs ) JumpTableTargets . insert ( MBB ) ; bool MadeChange = false ; for ( MachineBasicBlock & MBB


<s> static inline bool Thumb2PreloadOpcode ( unsigned Opcode ) { switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> InFlag = SDValue ( ) ; StoreTailCallArgumentsToStackSlot ( DAG , Chain , TailCallArguments , MemOpChains2 , dl ) ; if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains2 [ <NUM_LIT> ] , MemOpChains2 . size ( ) ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI ,


<s> if ( ML -> contains ( Bottom ) && ML -> isLoopLatch ( Bottom ) ) return true ; return


<s> if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Filler , Slot ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB , std :: next ( Filler


<s> MCInst LEASLInst ; LEASLInst . setOpcode ( <STR_LIT> ) ; LEASLInst . addOperand ( RD ) ; MCOperand CZero = MCOperand :: createImm ( <NUM_LIT> ) ; LEASLInst . addOperand ( CZero ) ; LEASLInst . addOperand ( CZero


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatXCOFF ( ) ) return new XCOFF<ISA_LIT>AsmBackend ( T , TT ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT


<s> assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( EltSizeInBits ) ; SDValue Imm = DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ; return getAVX512Node ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , { Op0 , Op1 , Imm } , DAG , Subtarget ) ; } return getAVX512Node ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , { Op0 , Op1 , Amt } , DAG , Subtarget ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . shouldOptForSize ( ) ; bool ExpandFunnel = ! OptForSize && Subtarget . isSHLDSlow ( ) ; if ( ( VT == <STR_LIT> || ( ExpandFunnel && VT == <STR_LIT> ) ) && ! isa < ConstantSDNode > ( Amt ) ) { SDValue Mask = DAG . getConstant ( EltSizeInBits - <NUM_LIT> , DL , Amt . getValueType ( ) ) ; SDValue HiShift = DAG . getConstant ( EltSizeInBits , DL , Amt . getValueType ( ) ) ; Op0 = DAG . getAnyExtOrTrunc ( Op0 , DL , <STR_LIT> ) ; Op1 = DAG . getZExtOrTrunc ( Op1 , DL , <STR_LIT> ) ; Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , Mask ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , HiShift ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Op1 ) ; if ( IsFSHR ) { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , HiShift ) ; } return DAG . getZExtOrTrunc ( Res , DL , VT ) ; } if ( VT == <STR_LIT> || ExpandFunnel ) return SDValue ( ) ; if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned FSHOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( FSHOp , DL , VT , Op0 , Op1 , Amt ) ; } return Op


<s> uint32_t getISAExtensionSetValue ( ) { return ( uint32_t )


<s> else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP ->


<s> void addBDVAddrOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isMem ( BDVMem ) && <STR_LIT>


<s> if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } else cpp_undef ( pfile , <STR_LIT> ) ; aarch64_def_or_undef ( TARGET_FP_F16INST , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_F16INST , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; cpp_undef ( pfile , <STR_LIT> ) ; cpp_undef ( pfile , <STR_LIT> ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( <STR_LIT> ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( <STR_LIT> ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; builtin_define_with_int_value ( <STR_LIT> , c_flt_eval_method


<s> int mask_low_and_shift_len ( machine_mode mode , rtx mask , rtx shift ) { HOST_WIDE_INT shval ; shval = INTVAL ( shift ) & ( GET_MODE_BITSIZE ( mode ) - <NUM_LIT>


<s> for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } SDValue WideLd = DAG . getMaskedLoad ( WideVecVT , dl , Mld -> getChain ( ) , Mld -> getBasePtr ( ) , NewMask , WideSrc0 , Mld -> getMemoryVT ( ) , Mld -> getMemOperand ( ) , <STR_LIT> ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , VT , WideLd ) ; return DCI . CombineTo ( N , NewVec , WideLd . getValue ( <NUM_LIT> )


<s> return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; int64_t Val = CE -> getValue ( ) ; if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = Val ; LaneKind = IndexedLane ; return MatchOperand_Success


( __v16sf ) _mm512_setzero_ps ( ) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> unsigned SrcReg = MI . getOperand ( OpNum ) . getReg ( ) ; unsigned SrcRegNum = Get<ISA_LIT>RegNum ( MI . getOperand ( OpNum ) ) ; if ( <STR_LIT> ( SrcReg ) ) SrcRegNum |= <NUM_LIT> ; return ( ~ SrcRegNum )


<s> Optional < ParamLoadedValue > <ISA_LIT>InstrInfo :: describeLoadedValue ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT>


<s> Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false ; } else if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd =


<s> return MCInstBuilder ( <STR_LIT> ) . addImm


<s> static inline unsigned getMsb ( uint32_t


<s> } status = DecodeASX ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address ,


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error (


<s> if ( TARGET_ABICALLS_PIC2 && ! reload_completed && crtl -> uses_const_pool ) return true ; return mips_find_gp_ref ( & cfun -> machine -> has_flexible_gp_insn_p ,


<s> default : return nullptr ; case <STR_LIT> : Op = OR ; break ; case <STR_LIT> : Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . SimpleTy ) { default : return nullptr ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I16 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI32 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI32 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I32 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI64 ] ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ ConstantI64 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I64 ] ; break ; } assert ( Opc != <NUM_LIT> && <STR_LIT> ) ; SDValue Ret ; if ( isUnOp ) { SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , Val , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Ret ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; SDValue RetVals [ ] = { Undef , Ret


<s> tree decl = def_builtin2 ( mask , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = <NUM_LIT> ; else ix86_builtins_isa [ ( int ) code ] . pure_p = true ; return decl


) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ;


<s> unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( ! SYMBOL_REF_P ( op ) ) return false ; if ( mode_supports_dq_form ( mode ) ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == <NUM_LIT> ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op


<s> SDValue <ISA_LIT>TargetLowering :: LowerOR ( SDValue Op , SelectionDAG & DAG )


<s> const <ISA_LIT>InstrInfo * getInstrInfo (


<s> return ( __m128 ) __builtin_ia32_expandsf128_maskz ( ( __v4sf ) __A , ( __v4sf )

_mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : if ( LT . second != <STR_LIT> ) return ( Cost + <NUM_LIT> ) * LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Cost + <NUM_LIT> ) * LT . first ; case <STR_LIT> : if ( isa < FixedVectorType > ( Ty ) && ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Cost + <NUM_LIT> ) * LT . first ; return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo


<s> const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned I = <NUM_LIT> , E = CPs . size ( ) ; I != E ; ++ I ) { unsigned Size = CPs [ I ] . getSizeInBytes ( TD ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; Align Alignment = CPs [ I ] . getAlign ( ) ; assert ( isAligned ( Alignment , Size ) && <STR_LIT> ) ; unsigned LogAlign = Log2 ( Alignment ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( I ) . addConstantPoolIndex ( I ) . addImm ( Size ) ; CPEMIs . push_back (


<s> const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL (


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget >


<s> unsigned <ISA_LIT>BaseInstrInfo :: extraSizeToPredicateInstructions ( const MachineFunction & MF , unsigned NumInsts ) const { return Subtarget . isThumb2 ( ) ? divideCeil ( NumInsts , <NUM_LIT> )


<s> poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > <NUM_LIT> ) return false ; poly_uint64 first = d -> perm [ <NUM_LIT> ] ; if ( ( maybe_ne ( first , <NUM_LIT> ) && maybe_ne ( first * <NUM_LIT> , nelt ) ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , first , <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , first + nelt , <NUM_LIT> ) ) return false ; high = maybe_ne ( first , <NUM_LIT> ) ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; high = !


<s> V1 = RegInfo . createVirtualRegister ( RC ) ; } if ( Subtarget . isABI_N64 ( ) ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; } else if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } else { MF . getRegInfo ( )


<s> for ( const <ISA_LIT>InstrRelaxTableEntry & Entry : InstrRelaxTable ) Table . push_back ( { Entry . DstOp , Entry . KeyOp } ) ; llvm :: sort ( Table ) ; assert ( std :: adjacent_find ( Table . begin ( ) , Table . end ( ) )


<s> insn_code function_expander :: direct_optab_handler_for_sign ( optab signed_op , optab unsigned_op , unsigned int suffix_i , machine_mode mode ) { if ( mode == VOIDmode ) mode = vector_mode ( suffix_i ) ; optab op = type_suffix ( suffix_i ) . unsigned_p


<s> Inst . addOperand ( MCOperand :: CreateReg (


<s> if ( CPUString . empty ( ) ) { CPUString = <STR_LIT> ; if ( isTargetDarwin ( ) ) { StringRef ArchName = TargetTriple . getArchName ( ) ; unsigned ArchKind = <STR_LIT> ( ArchName ) ; if ( ArchKind == <STR_LIT> ) CPUString = <STR_LIT> ; else if ( ArchKind == <STR_LIT> ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT


<s> p = ggc_alloc < extern_list > ( ) ; p -> next


<s> BlendMask [ i ] = i + Size ; } if ( ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) { if ( SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute ( DL , VT , V1 , V2 , Mask , DAG ) ) return BlendPerm ; if ( SDValue UnpackPerm = lowerVectorShuffleAsUNPCKAndPermute ( DL , VT , V1 , V2 , Mask , DAG ) ) return UnpackPerm ; } V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const


<s> static MCDisassembler * create<ISA_LIT>elDisassembler ( const Target & T , const MCSubtargetInfo &


<s> if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } } if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } else if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } } } if ( check ( Reg < First || Reg > RangeEnd , Start , Twine ( <STR_LIT> ) + <ISA_LIT>InstPrinter :: getRegisterName ( First ) + <STR_LIT> + <ISA_LIT>InstPrinter :: getRegisterName (


<s> SDValue <ISA_LIT>TargetLowering :: LowerSUB ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && Op

. getValueType ( ) . isInteger ( ) && <STR_LIT> ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { return BaseT :: getIntrinsicInstrCost ( ICA , CostKind


<s> Target & getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return


<s> static SDValue getTargetVShiftNode ( unsigned Opc , DebugLoc dl , EVT VT , SDValue SrcOp , SDValue ShAmt , SelectionDAG & DAG ) { assert ( ShAmt . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( isa < ConstantSDNode > ( ShAmt ) ) { uint32_t ShiftAmt = cast < ConstantSDNode > ( ShAmt ) -> getZExtValue ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , SrcOp , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; } } switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc =


<s> return ( __m128i ) __builtin_ia32_pternlogd128_mask ( ( __v4si ) __A , ( __v4si ) __B , (


<s> unsigned getMemBaseNum ( ) const { assert ( ( Kind == k_Memory ) &&


<s> unsigned int i [ <NUM_LIT> ] ; } aa , bb ; aa . v = ( vector unsigned int ) ( a ) ; bb . v = ( vector unsigned int ) ( b


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return


<s> const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } case <STR_LIT> : { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ) { printAnnotation ( O , Annot ) ; return ; } O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << translateShiftImm ( <STR_LIT> ( MO2 . getImm ( ) ) ) << markup ( <STR_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } else break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' <<


<s> if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI , AllOnes ) ) return Result ; if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI


<s> if ( VecVT . is256BitVector ( ) ) { DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; Vec = Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; if ( IdxVal >= NumElems / <NUM_LIT> ) IdxVal -= NumElems / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> )


<s> for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { const TargetInstrDesc & Desc = I -> getDesc ( ) ; emitInstruction ( * I , & Desc ) ; if ( Desc . getOpcode ( ) == <STR_LIT> ) emitInstruction ( * I , & II -> get ( <STR_LIT> ) ) ; NumEmitted


<s> if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ; return RelocM != Reloc :: Static && (


<s> unsigned high_part_offset = subreg_highpart_offset (


<s> bool <ISA_LIT>FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == <STR_LIT> ) return false ; return TLI . isTypeLegal (


<s> int64_t AddrDispShift ; assert ( calcInstrDist ( First , Last ) > <NUM_LIT> && <STR_LIT> ) ; if ( ! isReplaceable ( First , Last , AddrDispShift ) ) { ++ I2 ; continue ; } for ( auto UI = MRI -> use_begin ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> (


<s> OperandMatchResultTy parseGRH32 ( OperandVector & Operands ) { return parseRegister ( Operands , GRH32Reg


<s> } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; if ( SubMode != <STR_LIT> && SubMode != <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode ) ) ) ; int64_t CondVal = insn >> <STR_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( CondVal == <NUM_LIT> ? <NUM_LIT> : CondVal ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; bool isSPVFP = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; unsigned RegClassID = isSPVFP ? <STR_LIT> : <STR_LIT> ; unsigned RegD = decodeVFPRd ( insn , isSPVFP ) ; unsigned char Imm8 = insn & <NUM_LIT> ; unsigned Regs = isSPVFP ? Imm8 : Imm8 / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Regs ; ++ i ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , RegD + i


<s> SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue LSI = DAG . getMemOperand ( cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H , LSI } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( NewOp , dl , Tys , Ops , <NUM_LIT> ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue (


<s> auto * DefRC = MRI -> getRegClass ( OldDefReg ) ; unsigned UnhardenedReg = MRI -> createVirtualRegister ( DefRC ) ; DefOp . setReg ( UnhardenedReg ) ; unsigned HardenedReg = hardenValueInRegister ( UnhardenedReg , MBB , std :: next ( MI . getIterator ( ) ) , Loc ) ; MRI -> replaceRegWith ( OldDefReg , HardenedReg ) ; ++ NumPostLoadRegsHardened ; return


<s> MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( ABI . GetPtrAddiuOp ( ) ) , MaskLSB2 ) . addReg ( ABI . GetNullPtr ( ) ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( ABI . GetPtrAndOp ( ) ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr , <NUM_LIT> , ArePtrs64bit ? <STR_LIT> : <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Incr2 ) . addReg ( Incr ) . addReg ( ShiftAmt ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg (


<s> } unsigned S = <NUM_LIT> ; if ( MemSize == <NUM_LIT> && ! ShiftExtend . ImplicitAmount ) S = <NUM_LIT> ; else if ( MemSize != <NUM_LIT> && ShiftExtend . Amount != <NUM_LIT> ) S = <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( ( OptionHi << <NUM_LIT>


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getSuccessOrdering ( ) ) ) return


<s> if ( Inst . getOperand ( OpNum ) . isImm ( ) && Desc . OpInfo [ OpNum ] . OperandType == MCOI :: OPERAND_PCREL ) { Imm = Inst . getOperand ( OpNum ) . getImm ( ) ; FoundImm = true ; } } if ( ! FoundImm ) return false ; uint64_t Offset = ( ( Desc . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Target = Addr + Imm + Offset ; return


<s> return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment ( ) == Triple :: GNUX32 ; PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true


<s> unsigned Mask = C -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res ; if ( ( C = dyn_cast < ConstantSDNode > ( N1 ) ) ) { unsigned Val = C -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Mask ) || ( Val & ~ Mask ) != Val ) return SDValue ( ) ; Val >>= CountTrailingZeros_32 ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Val , <STR_LIT> ) , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; } else if ( N1 . getOpcode ( ) == <STR_LIT> ) { C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; unsigned Mask2 = C -> getZExtValue ( ) ; if ( <STR_LIT> ( Mask ) && <STR_LIT> ( ~ Mask2 ) && ( CountPopulation_32 ( Mask ) == CountPopulation_32 ( ~ Mask2 ) ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = CountTrailingZeros_32 ( Mask2 ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( lsb , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; } else if ( <STR_LIT> ( ~ Mask ) && <STR_LIT> ( Mask2 ) && ( CountPopulation_32 ( ~ Mask ) == CountPopulation_32 ( Mask2 ) ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask2 == <NUM_LIT>

|| Mask2 == <NUM_LIT> ) ) return SDValue ( ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc =


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = DCI . DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; return DCI . DAG . getMergeValues ( { Res , DCI . DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } , DL ) ; } if ( SDNode * GenericAddSub = DCI . DAG . getNodeIfExists ( <STR_LIT> , DCI . DAG . getVTList ( VT ) , { LHS , RHS } ) ) DCI . CombineTo ( GenericAddSub , SDValue ( N , <NUM_LIT> ) ) ; return SDValue (


<s> if ( cfun -> machine -> load_label_num_insns == <NUM_LIT> ) { mips_process_load_label ( pc_rtx ) ; cfun -> machine -> load_label_num_insns = mips_multi_num_insns ; } return cfun ->


<s> ModulePass * llvm :: create<ISA_LIT>GenScalarMASSEntriesPass ( ) { return new <ISA_LIT>GenScalarMASSEntries ( )


<s> void printf64mem ( const MachineInstr * MI ,


<s> return __builtin_mve_vcmpltq_m_sv16qi ( __a ,


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & C , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget

. useCRBits ( ) ? <STR_LIT> : <STR_LIT> ;


<s> uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , ValTy , ShiftRight . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Pos , DL , <STR_LIT>

) , DAG . getConstant ( SMSize , DL , <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printU3ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> void <ISA_LIT>CodeEmitter :: emitBranchInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . Opcode == <STR_LIT> ) abort ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI )


<s> auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements (


<s> MachineInstr & MVEVPTOptimisations :: ReplaceRegisterUseWithVPNOT ( MachineBasicBlock & MBB , MachineInstr & Instr , MachineOperand & User , Register Target ) { Register NewResult = MRI -> createVirtualRegister ( MRI -> getRegClass ( Target ) ) ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & Instr , Instr . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( NewResult ) . addReg ( Target ) ; addUnpredicatedMveVpredNOp ( MIBuilder


<s> int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( )


<s> int Offset = <NUM_LIT> + mergeSPUpdates ( MBB , MBBI , true ) ; emitSPUpdate ( MBB , MBBI , DL , Offset , true ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , MachineFramePtr ) . addUse ( MachineFramePtr ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( NeedsDwarfCFI ) { unsigned DwarfStackPtr = TRI -> getDwarfRegNum ( Is64Bit ? <STR_LIT> : <STR_LIT> , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: cfiDefCfa ( nullptr , DwarfStackPtr , SlotSize ) ) ; if ( ! MBB . succ_empty ( ) && ! MBB . isReturnBlock ( ) ) { unsigned DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; BuildCFI ( MBB , AfterPop , DL , MCCFIInstruction :: createRestore ( nullptr , DwarfFramePtr ) ) ; -- MBBI ; -- AfterPop ; } -- MBBI ; } } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( ( TRI -> hasStackRealignment ( MF ) ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> hasStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) LEAAmount -= <NUM_LIT> ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr


<s> return __builtin_mve_vrhaddq_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a


<s> static unsigned Get<ISA_LIT>RegNum ( const MCOperand & MO


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } } Base = Addr


<s> const MCOperandInfo * UseInfo = & UseMCID . OpInfo [ UseIdx ] ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; unsigned ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; } else { ZeroReg = UseInfo -> RegClass == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI -> getOperand ( UseIdx ) . setReg ( ZeroReg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return


<s> setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; const Align FunctionAlignment ( <NUM_LIT> ) ; setMinFunctionAlignment (


<s> return ( float32x4_t ) __builtin_neon_vld1v4sf ( ( const __builtin_neon_sf *


<s> return ( long long ) __builtin_ia32_vcvtsd2si64 ( (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; uint64_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; uint64_t OffBits = ( getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) & <NUM_LIT> ) << <NUM_LIT> ; return OffBits |


<s> rtx set_src , left_rtx , size_rtx ; int cost ; set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; left_rtx = XEXP ( XEXP ( set_src , <NUM_LIT> ) , <NUM_LIT> ) ; size_rtx = XEXP ( set_src , <NUM_LIT>


<s> case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT>


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return


<s> return false ; case <STR_LIT> : expandRetRA ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI ,


<s> } else { unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( ! Subtarget . isThumb ( ) ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Subtarget . getStackAlignment ( ) . value ( ) ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; } if ( CFI ) { MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createRestore


<s> if ( TARGET_FAST_INDIRECT_CALLS ) return <NUM_LIT> ; if ( TARGET_PORTABLE_RUNTIME ) return <NUM_LIT> ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < <NUM_LIT> ) || distance < MAX_PCREL17F_OFFSET ) ) return <NUM_LIT> ; if ( ! flag_pic ) return <NUM_LIT> ; if ( ! optimize_size ) { if ( TARGET_NO_SPACE_REGS ) return <NUM_LIT>


<s> static bool canCombine ( MachineBasicBlock & MBB , MachineOperand & MO , unsigned CombineOpc , unsigned ZeroReg = <NUM_LIT> , bool CheckZeroReg = false ) { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineInstr * MI = nullptr ; if ( MO . isReg ( ) && Register :: isVirtualRegister ( MO . getReg ( ) ) ) MI = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ; if ( ! MI || MI -> getParent ( ) != & MBB || ( unsigned ) MI -> getOpcode ( ) != CombineOpc ) return false ; if ( ! MRI . hasOneNonDBGUse ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( CheckZeroReg ) { assert ( MI -> getNumOperands ( ) >= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg

( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;


<s> static SDValue combineSelectAndUse ( SDNode * N , SDValue Slct , SDValue OtherOp , TargetLowering :: DAGCombinerInfo & DCI , bool AllOnes = false ) { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue NonConstantVal ; SDValue CCOp ; bool SwapSelectOps ; if ( ! isConditionalZeroOrAllOnes ( Slct . getNode ( ) , AllOnes , CCOp , SwapSelectOps , NonConstantVal , DAG ) ) return SDValue ( ) ; SDValue TrueVal = OtherOp ; SDValue FalseVal = DAG . getNode ( N -> getOpcode ( ) , N -> getDebugLoc ( ) , VT


<s> const MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget


<s> Register Dst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineIRBuilder MIRBuilder (


<s> vqrdmulhq_n_s32 ( int32x4_t a , int32_t b ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> uint64_t BaseOffset = <NUM_LIT> ; const MachinePointerInfo & PtrInfo = St . getPointerInfo ( ) ; SDValue NewST1 = DAG . getStore ( St . getChain ( ) , DL , SplatVal , BasePtr , PtrInfo , OrigAlignment , St . getMemOperand ( ) -> getFlags ( ) ) ; if ( BasePtr -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) ) { BaseOffset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; BasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; } unsigned Offset = EltOffset ; while ( -- NumVecElts ) { unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( BaseOffset + Offset , DL , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo . getWithOffset ( Offset ) , Alignment , St . getMemOperand ( ) -> getFlags ( ) ) ; Offset += EltOffset


<s> Value * LoHi = Builder . CreateCall ( Ldrex , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( )


<s> if ( STI . isAIXABI ( ) || STI . is<ISA_LIT>64 ( ) ) return ( STI . isELFv2ABI ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( STI . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> static SDValue performDUPCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . is64BitVector ( ) && DCI . isAfterLegalizeDAG ( ) ) { EVT LVT = VT . getDoubleNumVectorElementsVT ( * DCI . DAG . getContext ( ) ) ; if ( SDNode * LN = DCI . DAG . getNodeIfExists ( N -> getOpcode ( ) , DCI . DAG . getVTList ( LVT ) , { N -> getOperand ( <NUM_LIT> ) } ) ) { SDLoc DL ( N ) ; return DCI . DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( LN ,

<NUM_LIT> ) , DCI . DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> uint8x16x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; return


<s> if ( ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; Register BasePtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Opc == <STR_LIT> ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; Register NewDestReg = MI . getOperand (


<s> RegisterTarget < Triple :: mmix > Y ( getThe<ISA_LIT>Target ( ) ,


<s> loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode

, condition_rtx , loc_ref , pc_rtx ) ) ) ;


<s> return ( __m256i ) __builtin_ia32_vpconflictdi_256_mask ( ( __v4di ) __A , ( __v4di ) _mm256_setzero_si256 ( ) , ( __mmask8 ) -


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple &


<s> unsigned NumSubElts = NumElems / <NUM_LIT> ; SDValue Lo = extractSubVector ( In , <NUM_LIT> * NumSubElts , DAG , DL , SrcSizeInBits / <NUM_LIT> ) ; SDValue Hi = extractSubVector ( In , <NUM_LIT> * NumSubElts , DAG , DL , SrcSizeInBits / <NUM_LIT> ) ; unsigned SubSizeInBits = SrcSizeInBits / <NUM_LIT> ; InVT = EVT :: getVectorVT ( Ctx , InVT , SubSizeInBits / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , SubSizeInBits / OutVT . getSizeInBits ( ) ) ; if ( SrcVT . is256BitVector ( ) && DstVT . is128BitVector ( ) ) { Lo = DAG . getBitcast ( InVT , Lo ) ; Hi = DAG . getBitcast ( InVT , Hi ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , Lo , Hi ) ; return DAG . getBitcast ( DstVT , Res ) ; } if ( SrcVT . is512BitVector ( ) && Subtarget . hasInt256 ( ) ) { Lo = DAG . getBitcast ( InVT , Lo ) ; Hi = DAG . getBitcast ( InVT , Hi ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , Lo , Hi ) ; SmallVector < int , <NUM_LIT> > Mask ; int Scale = <NUM_LIT> / OutVT . getScalarSizeInBits ( ) ; scaleShuffleMask < int > ( Scale , ArrayRef < int > ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , Mask ) ; Res = DAG . getVectorShuffle ( OutVT , DL , Res , Res , Mask ) ; if ( DstVT . is256BitVector ( ) ) return DAG . getBitcast ( DstVT , Res ) ; EVT PackedVT = EVT :: getVectorVT ( Ctx , PackedSVT , NumElems ) ; Res = DAG . getBitcast ( PackedVT , Res ) ; return truncateVectorWithPACK ( Opcode , DstVT , Res , DL , DAG , Subtarget ) ; } assert ( SrcSizeInBits >= <NUM_LIT> && <STR_LIT>


<s> static void mips_print_float_branch_condition ( FILE * file , enum rtx_code code , int letter ) { switch ( code ) { case EQ : if ( ISA_HAS_CCF ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file


<s> else type_signature [ op_num ] = 's' ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; eltype = aarch64_simd_builtin_type ( op_mode , qualifiers ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p ) snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name ) ; tree attrs = aarch64_get_attributes ( d -> flags , d -> mode ) ; if ( called_from_pragma ) { unsigned int raw_code = ( fcode << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_GENERAL ; fndecl = simulate_builtin_function_decl ( input_location , namebuf , ftype , raw_code , NULL , attrs ) ; } else fndecl = aarch64_general_add_builtin ( namebuf , ftype , fcode , attrs ) ; aarch64_builtin_decls [ fcode ]


<s> if ( mips_lo_relocs [ symbol_type ] == NULL ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) return false ; return true


<s> PrevState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_OFFSET : case IES_REGISTER : case IES_RPAREN : State = IES_RPAREN ; IC . pushOperator


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; }


<s> static MCInstrAnalysis * create<ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info


<s> void addGPR32NonZeroAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getGPR32Reg ( )


<s> void <ISA_LIT>TargetAsmStreamer :: emit<ISA_LIT>HackELFFlags (


<s> AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > (


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm


<s> DebugLoc DL = Orig -> getDebugLoc ( ) ; bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig


<s> assert ( RC -> vt_end ( ) - RC -> vt_begin ( ) ==


<s> } else return false ; Instruction * Insert = nullptr ; if ( ! match ( BroadcastSplat , m_Shuffle ( m_Instruction ( Insert ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElt ( m_Undef ( ) , m_Instruction ( IV ) , m_Zero ( ) ) ) ) return false ; auto * Phi = dyn_cast < PHINode > ( IV ) ; if ( ! Phi ) return false ; Value * OnEntry = Phi -> getIncomingValueForBlock ( L -> getLoopPreheader ( ) ) ; if ( ! match ( OnEntry , m_Zero ( ) ) ) return false ; Value * InLoop = Phi -> getIncomingValueForBlock ( L -> getLoopLatch ( ) ) ; unsigned Lanes = cast < FixedVectorType > ( Insert -> getType ( ) ) -> getNumElements ( ) ; Instruction * LHS


<s> unsigned FullSize ; switch ( ( unsigned ) Kind ) { case <STR_LIT> : FullSize = <NUM_LIT> ; break ; default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value


<s> static DecodeStatus DecodeMSRMask ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! Val ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm


<s> MachineFunction & MF = * MI . getMF ( ) ; auto Val = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: scalar ( VaListSize * <NUM_LIT> ) ) ; MachineIRBuilder MIB ( MI ) ; MIB . buildLoad ( Val , MI . getOperand ( <NUM_LIT> ) , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , VaListSize , Align ( PtrSize ) ) ) ; MIB . buildStore ( Val , MI . getOperand ( <NUM_LIT> ) , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VaListSize , Align ( PtrSize ) ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { MachineIRBuilder & MIB = Helper . MIRBuilder ; MIB . buildConstant ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true


<s> else frame -> fp_sp_offset = offset ; if ( frame -> mask ) { unsigned x_save_size = LARCH_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + loongarch_save_libcall_count ( frame -> mask ) ; if ( LARCH_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) frame -> save_libcall_adjustment = x_save_size ; offset += x_save_size ; frame -> gp_sp_offset = offset - UNITS_PER_WORD ; } else frame -> gp_sp_offset = offset ; frame -> hard_frame_pointer_offset = offset ; offset += LARCH_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; offset += LARCH_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; frame -> arg_pointer_offset = offset - crtl


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( isIntrinsic ) Cnt = - Cnt ; return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow

? ElementBits / <NUM_LIT> : ElementBits ) ) ;


<s> <ISA_LIT>Relocator :: SWord GOT_S = got_entry -> getOffset ( ) - ( pParent . getTarget ( ) . getGOTPLT ( ) . addr ( ) - pParent . getTarget ( ) . getGOT ( ) . addr ( ) ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; pReloc . target ( ) = GOT_S


<s> if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) )


<s> if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; InitCPUSchedModel ( CPUName ) ; if ( <ISA_LIT>ProcFamily == IntelAtom || <ISA_LIT>ProcFamily == IntelSLM ) PostRAScheduler = true ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable (


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; return *


<s> case VK_<ISA_LIT>_HH : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HM : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PC22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PC10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT13 : closeParen = false ; break ; case VK_<ISA_LIT>_13 : closeParen = false ; break ; case VK_<ISA_LIT>_WPLT30 : closeParen = false ; break ; case VK_Sparc_R_DI<ISA_LIT>32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ;


<s> Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } } return DecodeVMOVModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - imm ) ) ; return


<s> if ( fndecl != NULL_TREE ) { ix86_set_func_type ( fndecl ) ; ix86_set_indirect_branch_type ( fndecl ) ; } return ; } tree old_tree ; if ( ix86_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } ix86_set_func_type ( fndecl ) ; ix86_set_indirect_branch_type ( fndecl ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree )

= save_target_globals_default_opts ( ) ;


<s> if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) && Name == <STR_LIT> ) return FK_NONE ; return MCAsmBackend :: getFixupKind


<s> MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Vulcan : MaxInterleaveFactor = <NUM_LIT> ; break ; case ThunderX


<s> GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer .

getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> if ( fndecl == NULL_TREE ) cfun -> machine -> call_abi = ix86_abi ; else cfun -> machine -> call_abi = ix86_function_type_abi (


<s> unsigned int flags = <NUM_LIT> ; if ( instance . type_suffix ( <NUM_LIT> ) . float_p || instance . type_suffix ( <NUM_LIT> ) . float_p ) flags |= CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS ; return flags


<s> if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Name , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned prfop = Mapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return


<s> if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return CSR_Darwin_<ISA_LIT>_AAPCS_SaveList ; return CSR_<ISA_LIT>_AAPCS_SaveList


<s> } else if ( mutex -> owner == me ) ++ ( mutex -> depth ) ; else return <NUM_LIT> ; return <NUM_LIT>


<s> void printlea64mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> if ( ! TargetSupported ) return <NUM_LIT> ; EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? <NUM_LIT> :


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> const MCExpr * TargetExpr = MCSymbolRefExpr :: create ( Target , MCSymbolRefExpr :: VariantKind :: VK_None , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TargetExpr ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> EmitLabel ( Target ) ; if ( ! Subtarget -> isGP64bit ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) .


<s> MCCodeEmitter * llvm :: create<ISA_LIT>BEMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo


<s> if ( isa < StoreInst > ( V ) || isa < GetElementPtrInst > ( V ) ) return true ; if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( ( isa < Constant > ( V ) && ! isa < ConstantExpr > ( V ) ) || isa < Argument > ( V ) ) return isSupportedType ( V ) ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return isSupportedType ( Trunc ) || isSupportedType ( Trunc -> getOperand ( <NUM_LIT> ) ) ; if ( isa < CastInst > ( V ) && ! isa < SExtInst > ( V ) ) return isSupportedType ( cast < CastInst > ( V ) -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) return false ; if ( ! isSupportedType ( V ) ) return false ; if ( generateSignBits (


<s> virtual void EmitConstantPool ( ) LLVM_OVERRIDE { if ( ! Subtarget -> useConstIslands ( ) ) AsmPrinter :: EmitConstantPool (


<s> if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return <NUM_LIT> ; if ( HILO_REGNO_P ( regno ) ) return mode ==


<s> unsigned <ISA_LIT>TargetMachine :: getModuleMatchQuality ( const Module & M ) { std :: string TT = M . getTargetTriple ( ) ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( ! TT . empty ( ) ) return <NUM_LIT> ; if ( M . getEndianness ( ) == Module :: BigEndian && M

. getPointerSize ( ) == Module :: Pointer32 ) return <NUM_LIT> ;


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return


<s> for ( auto & I : * BB ) { if ( I . mayWriteToMemory ( ) ) Writes . push_back ( & I ) ; auto * Ld = dyn_cast < LoadInst > ( & I ) ; if ( ! Ld || ! Ld -> isSimple ( ) || ! Ld -> hasOneUse ( ) || ! isa < SExtInst > ( Ld -> user_back ( ) ) ) continue ; Loads . push_back ( Ld ) ; } using InstSet = std :: set < Instruction * > ; using DepMap = std :: map < Instruction * , InstSet > ; DepMap RAWDeps ; const auto Size = LocationSize :: unknown ( ) ; for ( auto Read : Loads ) { for ( auto Write : Writes ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( DT -> dominates ( Write , Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { LoadInst * Dominator = DT -> dominates ( Base , Offset


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> void <ISA_LIT>16InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> )


<s> static inline unsigned getNEONModImmVal ( unsigned


<s> switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op


<s> if ( Subtarget -> isTargetMacho ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( Subtarget -> isTargetCOFF ( ) ) { if ( ! Subtarget -> is64Bit ( ) ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer . EndCOFFSymbolDef (


<s> gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , false ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode


<s> Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , <NUM_LIT> ) ; MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( MTS -> getABI ( ) . IsN32 ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> emitInt32 ( ri_gprmask ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ]


<s> SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ; return SDValue ( )


<s> const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetWindows ( ) ) return false ; const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger (


<s> unsigned HOST_WIDE_INT high ; unsigned int i ; high = value & ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; if ( ! LUI_OPERAND ( high ) && ( value & <NUM_LIT> ) == <NUM_LIT> ) { i = mips_build_integer ( codes , CONST_HIGH_PART ( value ) ) ; codes [ i ] .