<s> fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XVECEXP ( tocrel_base_oac , <NUM_LIT> ,


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI


<s> assert ( Subtarget . is64BitELFABI ( ) ) ; const unsigned PtrByteSize = <NUM_LIT> ; const unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; static const MCPhysReg GPR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const MCPhysReg VR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumGPRs = array_lengthof ( GPR ) ; const unsigned NumFPRs = <NUM_LIT> ; const unsigned NumVRs = array_lengthof ( VR ) ; const unsigned ParamAreaSize = NumGPRs * PtrByteSize ; unsigned NumBytes = LinkageSize ; unsigned AvailableFPRs = NumFPRs ; unsigned AvailableVRs = NumVRs ; for ( const <STR_LIT> & Param


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand ::


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU


<s> static TargetLoweringObjectFile * createTLOF ( TargetMachine & TM ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) .

isTargetDarwin ( ) ) return new TargetLoweringObjectFileMachO ( ) ;


<s> fpu_name = ( ptr -> x_arm_fpu_index == TARGET_FPU_auto ? <STR_LIT> : all_fpus [ ptr -> x_arm_fpu_index ] . name ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , TARGET_THUMB2_P ( flags ) ? <STR_LIT> : TARGET_THUMB_P ( flags ) ? <STR_LIT> : <STR_LIT> ) ; if ( ptr -> x_arm_arch_string ) fprintf ( file , <STR_LIT> , indent

, <STR_LIT> , ptr -> x_arm_arch_string ) ;


<s> SDValue Ext1 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT> ) ; auto NodeType = ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( )


<s> LLVMContext & Ctx = M . getContext ( ) ; auto Type = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , false ) ; Function * F = Function :: Create ( Type , GlobalValue :: LinkOnceODRLinkage , Name , & M ) ; F -> setVisibility ( GlobalValue :: HiddenVisibility ) ; F -> setComdat ( M . getOrInsertComdat ( Name ) ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; F -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , F ) ; IRBuilder < > Builder ( Entry ) ; Builder . CreateRetVoid (


<s> uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , ValTy , ShiftRight . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Pos ,

<STR_LIT> ) , DAG . getConstant ( SMSize , <STR_LIT> ) ) ;


<s> auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if ( UxtOp ) { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( UxtOp ) , Desired . getReg ( ) ) . addReg ( Desired . getReg ( ) , RegState :: Kill ) ; if ( ! IsThumb ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; } LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( Addr . getReg ( ) ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . add ( Desired ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr .


<s> unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attributes :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attributes :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attributes :: InReg ) || CS . paramHasAttr ( AttrInd , Attributes :: StructRet ) || CS . paramHasAttr ( AttrInd , Attributes :: Nest ) || CS . paramHasAttr ( AttrInd , Attributes :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp


<s> unsigned aarch64_dbx_register_number ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return AARCH64_DWARF_R0 + regno - R0_REGNUM ; else if ( regno == SP_REGNUM ) return AARCH64_DWARF_SP ; else if ( FP_REGNUM_P ( regno ) ) return AARCH64_DWARF_V0 + regno - V0_REGNUM ; return


<s> Cst = - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ; } if ( MO . isGlobal ( ) ) return MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , RelocID , const_cast < GlobalValue * > ( MO . getGlobal ( ) ) , Cst , isa < Function > ( MO . getGlobal ( ) ) ) ; if ( MO . isSymbol ( ) ) return MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( )

, RelocID , MO . getSymbolName ( ) , Cst ) ;


<s> static DecodeStatus DecodeThumbAddrModePC ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned imm = Val << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( imm )


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { report_fatal_error ( <STR_LIT>


<s> bool <ISA_LIT>ExpandPseudo :: ExpandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isMem = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; if ( StackAdj ) { StackAdj += <ISA_LIT>FL -> mergeSPUpdates ( MBB , MBBI , true ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; } bool IsWin64 = STI -> isTargetWin64 ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; NewMI -> copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 (


<s> HOST_WIDE_INT countval = INTVAL ( count ) ; HOST_WIDE_INT epilogue_size = countval % max_size ; int i ; gcc_assert ( ( max_size & ( max_size - <NUM_LIT> ) ) == <NUM_LIT> ) ; for ( i = max_size ; i >= <NUM_LIT> ; i >>= <NUM_LIT> ) { if ( epilogue_size & i ) { if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } } return ; } if ( max_size > <NUM_LIT> ) { expand_setmem_epilogue_via_loop ( destmem , destptr , value , count , max_size ) ; return ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; if ( TARGET_64BIT ) { dest = change_address ( destmem , DImode , destptr ) ; emit_insn ( gen_strset ( destptr , dest , value ) ) ; dest = adjust_automodify_address_nv ( dest , DImode , destptr , <NUM_LIT> ) ; emit_insn ( gen_strset ( destptr , dest , value ) ) ; } else { dest = change_address ( destmem , SImode , destptr ) ; emit_insn ( gen_strset ( destptr , dest , value ) ) ; dest = adjust_automodify_address_nv ( dest , SImode , destptr , <NUM_LIT> ) ; emit_insn ( gen_strset ( destptr , dest , value


<s> if ( ! TREE_PUBLIC ( decl ) ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_DECLARED_INLINE_P ( decl ) && ! flag_keep_inline_dllexport ) return false ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) return true ; return


<s> return ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONSTANT_ADDRESS_P ( x ) || ( TARGET_HAVE_MOVT && SYMBOL_REF_P ( x ) ) || ( TARGET_THUMB1 && ! label_mentioned_p ( x ) && arm_valid_symbolic_address_p ( x ) &&

arm_disable_literal_pool ) || flag_pic ) ;


<s> if ( ! IsSigned && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { Register TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; Register DestReg = createResultReg ( RC ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ,


<s> static bool expandNOVLXStore ( MachineInstrBuilder & MIB , const TargetRegisterInfo * TRI , const MCInstrDesc & StoreDesc , const MCInstrDesc & ExtractDesc , unsigned SubIdx ) { unsigned SrcReg = MIB -> getOperand ( <STR_LIT> ) . getReg ( ) ; if ( TRI -> getEncodingValue ( SrcReg ) < <NUM_LIT> ) { MIB -> setDesc ( StoreDesc ) ; } else { MIB -> setDesc ( ExtractDesc ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , SubIdx , & <STR_LIT> ) ; MIB -> getOperand ( <STR_LIT> ) . setReg ( SrcReg ) ; MIB . addImm ( <NUM_LIT> ) ; } return


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( )


<s> static inline unsigned getArithExtendImm ( <STR_LIT> ET , unsigned Imm ) { assert ( ( Imm & <NUM_LIT> ) == Imm && <STR_LIT>


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend


<s> return __builtin_mve_vhsubq_m_n_uv4si ( __arm_vuninitializedq_u32 ( ) , __a


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer

. getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> bool hasExtLSX ( ) const { return HasExtLSX


<s> unsigned NumRegs = Regs . size ( ) ; assert ( NumRegs > <NUM_LIT> ) ; bool SafeToClobberCPSR = ! isThumb1 || ( MBB . computeRegisterLiveness ( TRI , <STR_LIT> , InsertBefore , <NUM_LIT> ) == MachineBasicBlock :: LQR_Dead ) ; bool Writeback = isThumb1 ; if ( isThumb1 && isi32Load ( Opcode ) && ContainsReg ( Regs , Base ) ) { assert ( Base != <STR_LIT> && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Writeback = false ; } else if ( Opcode == <STR_LIT> ) { return nullptr ; } } <STR_LIT> Mode = <STR_LIT> ; bool isNotVFP = isi32Load ( Opcode ) || isi32Store ( Opcode ) ; bool haveIBAndDA = isNotVFP && ! isThumb2 && ! isThumb1 ; if ( Offset == <NUM_LIT> && haveIBAndDA ) { Mode = <STR_LIT> ; } else if ( Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> && haveIBAndDA ) { Mode = <STR_LIT> ; } else if ( Offset == - <NUM_LIT> * ( int ) NumRegs && isNotVFP && ! isThumb1 ) { Mode = <STR_LIT> ; } else if ( Offset != <NUM_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( ! getLoadStoreMultipleOpcode ( Opcode , Mode ) ) return nullptr ; if ( NumRegs <= <NUM_LIT> ) return nullptr ; if ( ! SafeToClobberCPSR ) return nullptr ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) { NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; Writeback = false ; } else { moveLiveRegsBefore ( MBB , InsertBefore ) ; if ( ! isLoadSingle ( Opcode ) ) for ( const std :: pair < unsigned , bool > & R : Regs ) LiveRegs . addReg ( R . first ) ; NewBase = findFreeReg ( isThumb1 ? <STR_LIT> : <STR_LIT> ) ; if ( NewBase == <NUM_LIT> ) return nullptr ; } int BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Base == <STR_LIT> ) ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> && Base != <STR_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return nullptr ; bool KillOldBase = BaseKill && ( ! isi32Store ( Opcode ) || ! ContainsReg ( Regs , Base ) ) ; if ( isThumb1 ) { if ( Base != NewBase && ( BaseOpc == <STR_LIT> || BaseOpc == <STR_LIT> ) ) { if ( is<ISA_LIT>LowRegister ( NewBase ) && is<ISA_LIT>LowRegister ( Base ) && ! STI -> hasV6Ops ( ) ) { if ( Pred != <STR_LIT> ) return nullptr ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base ,


<s> if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , <NUM_LIT> ) , Pmode ) && GET_CODE

( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ;


<s> if ( parseOptionalToken ( AsmToken :: Comma ) ) { ControlLoc = getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Control ) ) return true ; } if ( getParser ( ) . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( NumBytes <= <NUM_LIT> ) { Error ( NumBytesLoc , <STR_LIT> ) ; return


<s> unsigned RetryCmpVal = MRI . createVirtualRegister ( RC ) ; unsigned RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * SetMBB = emitBlockAfter ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest


<s> } rtx ccset = gen_rtx_SET ( ccreg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ; if ( dot == <NUM_LIT> ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , dst ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , ccset , clobber )


<s> assert ( v . size ( ) >= <NUM_LIT> ) ; assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> , LegalizerInfo :: NarrowScalar } ) ; return result


<s> return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> ||


<s> RegisterTarget < Triple :: sparcv9 > Y ( The<ISA_LIT>V9Target , <STR_LIT> ,


<s> void setVarArgsFrameIndex ( int Index ) { VarArgsFrameIndex =


<s> SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , fmrrd ) ) ; if ( NextVA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) ) ) ; else { assert ( NextVA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg

( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ;


<s> unsigned DSub1 = createExtractSubreg ( MBB , InsertPt , DL , Reg , <STR_LIT> , & <STR_LIT> ) ; unsigned Out1 = createDupLane ( MBB , InsertPt , DL , DSub0 , <NUM_LIT> ) ; unsigned Out2 = createDupLane ( MBB , InsertPt , DL , DSub0 , <NUM_LIT> ) ; Out = createVExt ( MBB , InsertPt , DL , Out1 , Out2 ) ; unsigned Out3 = createDupLane ( MBB , InsertPt , DL , DSub1 , <NUM_LIT> ) ; unsigned Out4 = createDupLane ( MBB , InsertPt , DL , DSub1 , <NUM_LIT> ) ; Out2 = createVExt ( MBB , InsertPt , DL , Out3 , Out4 ) ; Out = createRegSequence ( MBB , InsertPt , DL , Out , Out2 ) ; } else if ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ) { unsigned Out1 = createDupLane ( MBB , InsertPt , DL , Reg , <NUM_LIT> ) ; unsigned Out2 = createDupLane ( MBB , InsertPt , DL , Reg , <NUM_LIT> ) ; Out = createVExt ( MBB , InsertPt , DL , Out1 , Out2 ) ; } else { assert ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; unsigned PrefLane = getPrefSPRLane ( Reg ) ; unsigned Lane ; switch ( PrefLane ) { case <STR_LIT> : Lane = <NUM_LIT> ; break ; case <STR_LIT> : Lane = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } bool UsesQPR = usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) || usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ; Out = createImplicitDef ( MBB , InsertPt , DL ) ; Out = createInsertSubreg ( MBB , InsertPt , DL , Out , PrefLane , Reg ) ; Out = createDupLane ( MBB , InsertPt , DL , Out , Lane , UsesQPR ) ; eraseInstrWithNoUses ( MI ) ; } return


<s> return EmitF128CSEL ( MI , BB ) ; case TargetOpcode :: STATEPOINT : MI . addOperand ( * MI . getMF ( ) , MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ; LLVM_FALLTHROUGH ; case TargetOpcode :: STACKMAP : case TargetOpcode :: PATCHPOINT : return emitPatchPoint ( MI


<s> if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , true ) ; O << * NLPSym ; return ; } case MachineOperand :: MO_GlobalAddress : { GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { return new Darwin<ISA_LIT>AsmBackend ( T , TheTriple , MRI ) ; } if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T , TheTriple ) ; assert ( TheTriple . isOSBinFormatELF ( ) &&


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( Desc . TSFlags & <STR_LIT> ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned NumOps = Desc . getNumOperands ( ) ; if ( NumOps ) { bool isTwoAddr = NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; unsigned i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned e = NumOps ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> ( Reg ) ) REX |= <NUM_LIT> ; } } switch ( Desc . TSFlags & <STR_LIT> ) { case <STR_LIT> : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned e = NumOps ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << <NUM_LIT> ; } break ; } case <STR_LIT> : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << Bit ; Bit


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return std :: make_unique <


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG


<s> MachineBasicBlock :: iterator Term = MBB -> getFirstTerminator ( ) ; adjustLiveRegs ( Bundle . Mask , Term ) ; if ( ! Bundle . Mask ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BundleIdx << <STR_LIT> ) ; if ( Bundle . isFixed ( ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> static SDValue PerformHWLoopCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { SDValue CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC -> getOpcode ( ) != <STR_LIT> && CC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( CC -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Int = CC -> getOperand ( <NUM_LIT> ) ; unsigned IntOp = cast < ConstantSDNode > ( Int . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> ) return SDValue ( ) ; assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SDValue Chain = N -> getOperand ( <NUM_LIT>


<s> if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( TARGET_SSE_MATH && ! TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P ( mode ) ) return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( CONST_DOUBLE_P ( x ) ) { if ( reg_class_subset_p ( regclass , GENERAL_REGS ) ) return regclass ; if ( TARGET_80387 && standard_80387_constant_p ( x ) > <NUM_LIT> ) { if ( regclass == FLOAT_SSE_REGS ) return FLOAT_REGS ; if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; if ( regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS ) return regclass ; } return NO_REGS


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) )


<s> SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , OldSP , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP ; if ( hasInlineStackProbe ( MF ) ) { NewSP = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , OldSP , NeededSpace ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; } else { NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; } SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ExtraAlignSpace


<s> EVT ValTy = Addr . getValueType ( ) ; Alias = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; } else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0

) || isa < JumpTableSDNode > ( Opnd0 ) ) {


<s> addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << MO2 . getImm ( ) ; } O <<


<s> bool hasFP64 ( ) const { return HasFP64


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t


<s> } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment (


<s> return ( __m128i ) __builtin_ia32_psrlv8hi_mask ( ( __v8hi ) __A , ( __v8hi ) __B , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> return __builtin_ia32_cvtss2si ( ( __v4sf


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel


<s> uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , Is32Bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; unsigned NewReg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MO . setIsKill ( false ) ; if ( ! Is32Bit && Imm < <NUM_LIT> ) NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { if ( ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( DefMI -> findRegisterDefOperandIdx ( <STR_LIT> , true ) != - <NUM_LIT> ) return false ; <STR_LIT> CC = ( <STR_LIT> ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( areCFlagsAccessedBetweenInstrs ( DefMI , MI , & getRegisterInfo ( ) , AK_Write ) ) return false ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI . getOperand ( TargetBBInMI ) . getMBB (


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ) { <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB .


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr ( SDValue Addr , SDValue & Base ,


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isX18Reserved ( ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isX20Reserved ( ) ) ) Reg = <NUM_LIT> ; if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef (


<s> static bool mips_far_type_p ( const_tree type ) { return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL || lookup_attribute ( <STR_LIT>

, TYPE_ATTRIBUTES ( type ) ) != NULL ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( VT . getScalarType ( ) == <STR_LIT> ) return true ; if ( DAG . getNodeIfExists ( <STR_LIT> , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget


<s> static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , <STR_LIT> ,


<s> EncodedValue &= ~ <NUM_LIT> ; return EncodedValue


<s> static int mips_small_data_pattern_1 ( rtx x , enum mips_symbol_context context ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , ALL ) { rtx x = * iter ; if ( GET_CODE ( x ) == LO_SUM || GET_CODE ( x ) == ASM_OPERANDS ) iter . skip_subrtxes ( ) ; else if ( MEM_P ( x


<s> if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK ||


<s> CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } MachineIRBuilder MIRBuilder ( I ) ; Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIRBuilder ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg

} ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MFI . hasVarSizedObjects ( ) && TRI -> needsStackRealignment


<s> bool isImm0_7 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT>


<s> char * strip , * p ; const char * q ; size_t len ; q = ( const char * ) strchr ( name , '$' ) ; if ( q == <NUM_LIT> || q == name ) return name ; len = strlen ( name ) ; strip = XALLOCAVEC ( char , len + <NUM_LIT> ) ; strcpy ( strip , name


<s> return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv16qi (


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState (


<s> return Kind == k_VectorIndex && VectorIndex . Val <


<s> return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { assert ( Subtarget . hasDirectMove ( ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { assert ( Subtarget . hasDirectMove ( ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = ( Subtarget . hasP9Vector ( ) ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg )


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadRetAddr ( SelectionDAG & DAG , SDValue & OutRetAddr , SDValue Chain , bool IsTailCall , bool Is64Bit , int FPDiff , DebugLoc dl ) const { EVT VT = getPointerTy ( ) ; OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr ,

MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>Subtarget :: useMovt ( ) const { return ! NoMovt && hasV8MBaselineOps ( ) && ( isTargetWindows

( ) || ! OptMinSize || genExecuteOnly ( ) ) ;


<s> -- OpUsefulBits ; if ( Op . getOperand ( <NUM_LIT> ) == Orig ) { Mask = ResultUsefulBits & OpUsefulBits ; Mask = Mask . shl ( LSB ) ; } if ( Op . getOperand ( <NUM_LIT> ) == Orig ) Mask |= ( ResultUsefulBits & ~ OpUsefulBits ) ; } else { uint64_t Width = MSB + <NUM_LIT> ; uint64_t LSB = UsefulBits . getBitWidth ( ) - Imm ; OpUsefulBits = OpUsefulBits . shl ( Width ) ; -- OpUsefulBits ; OpUsefulBits = OpUsefulBits . shl ( LSB ) ; if ( Op . getOperand ( <NUM_LIT> ) == Orig ) { Mask = ResultUsefulBits & OpUsefulBits ; Mask . lshrInPlace ( LSB ) ; } if ( Op . getOperand ( <NUM_LIT> ) == Orig ) Mask |= ( ResultUsefulBits &


<s> if ( ( NumElts % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == ShrinkMode :: MULU8 || Mode == ShrinkMode :: MULS8 ) return DAG . getNode ( ( Mode == ShrinkMode :: MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == ShrinkMode :: MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT ,


<s> tree type ; int nvreg = <NUM_LIT> ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) )


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> void <ISA_LIT>ConstantPoolMBB :: print ( raw_ostream & O ) const { O << printMBBReference ( * MBB ) ; <ISA_LIT>ConstantPoolValue :: print ( O


<s> SmallVector < int , <NUM_LIT> > TargetMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> , Size = TargetMask . size ( ) ; i < Size ; ++ i ) { if ( TargetMask [ i ] == SM_SentinelUndef ) continue ; if ( Zeroable [ i ] ) TargetMask [ i ] = SM_SentinelZero ; } return canWidenShuffleElements ( TargetMask


<s> case CallingConv :: <ISA_LIT>_StdCall : { NestReg = <STR_LIT> ; FunctionType * FTy = Func -> getFunctionType ( ) ; const AttrListPtr & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . getParamAttributes ( Idx ) . hasAttribute ( Attributes :: InReg ) ) InRegCount += ( TD -> getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: Fast : NestReg = <STR_LIT> ; break ; } SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr , Disp ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Disp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPtr , Addr ) ; const unsigned char MOV32ri = <NUM_LIT> ; const unsigned char N86Reg = TRI -> getEncodingValue ( NestReg ) & <NUM_LIT> ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( MOV32ri | N86Reg , <STR_LIT> ) , Trmp , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; const unsigned char JMP = <NUM_LIT> ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( JMP , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Disp , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case LTU : cond_str = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( far ) { int veryfar = <NUM_LIT> , delta ; if ( INSN_ADDRESSES_SET_P ( ) ) { delta = ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ) ; if ( delta >= - <NUM_LIT> && delta < <NUM_LIT> ) veryfar = <NUM_LIT> ; } if ( veryfar ) tmpl = <STR_LIT> ; else tmpl = <STR_LIT> ; } else { if ( emit_nop ) tmpl = <STR_LIT> ; else tmpl =


<s> Align Alignment = Subtarget . is<ISA_LIT>64 ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty , Alignment , Align ( <NUM_LIT> ) ) ; return Alignment .


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; O << getRegisterName ( MRI . getSubReg ( Reg , <STR_LIT> )


<s> RelLsIter LoPos = RelocLs . end ( ) , HiPos = * U ; bool MatchedLo = false ; for ( RelLsIter R = RelocLs . begin ( ) ; R != RelocLs . end ( ) ; ++ R ) { if ( ( R -> Reloc . Type == ELF :: R_CPU0_LO16 ) && HasSameSymbol ( * HiPos , * R ) && ( CompareOffset ( * R , * HiPos ) >= <NUM_LIT> ) && ( ( LoPos == RelocLs . end ( ) ) || ( ( CompareOffset ( * R , * LoPos ) < <NUM_LIT> ) ) || ( ! MatchedLo && ! CompareOffset ( * R , * LoPos ) ) ) ) LoPos = R ; MatchedLo = NeedsMatchingLo ( Asm , * R ) && HasMatchingLo ( Asm , R , -- RelocLs . end ( ) ) ; } if ( LoPos != RelocLs . end ( ) ) { HiPos -> Offset = LoPos -> Offset ; RelocLs . insert ( LoPos , * HiPos ) ; RelocLs . erase ( HiPos ) ; } } assert ( Relocs . size ( ) == RelocLs . size ( ) ) ; unsigned I = RelocLs . size ( ) ; for ( RelLsIter R = RelocLs . begin ( ) ; R != RelocLs . end ( ) ; ++


<s> Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt32Immediate ( RHS , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( ( int ) SImm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm (


<s> if ( length == <NUM_LIT> ) return <STR_LIT> ; if ( length == <NUM_LIT> ) { if ( dbr_sequence_length ( ) == <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) return <STR_LIT> ; else return


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createGPRPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl ,


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT>


<s> if ( I != nullptr ) { if ( ( I -> getOpcode ( ) == Instruction :: Load || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && I -> hasOneUse ( ) ) { const User * Us = * I -> users ( ) . begin ( ) ; if ( isa < ZExtInst > ( Us ) || isa < SExtInst > ( Us ) ) { unsigned TypeSize = cast < Instruction > ( Us ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( TypeSize == <NUM_LIT> && ( EltSize == <NUM_LIT> || EltSize == <NUM_LIT> ) ) || ( TypeSize == <NUM_LIT> && EltSize == <NUM_LIT> ) ) && TypeSize * NumElems == <NUM_LIT> ) { ExtSize = TypeSize ; } } } TruncInst * T ; if ( ( I -> getOpcode ( ) == Instruction :: Store || match ( I , m_Intrinsic < <STR_LIT> > ( ) ) ) && ( T = dyn_cast < TruncInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) { unsigned TypeSize = T -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) ; if ( ( ( EltSize == <NUM_LIT> && TypeSize == <NUM_LIT> ) || ( EltSize == <NUM_LIT> && ( TypeSize == <NUM_LIT> || TypeSize == <NUM_LIT> ) ) ) && TypeSize * NumElems == <NUM_LIT> ) ExtSize = TypeSize ; } } if ( ExtSize * NumElems != <NUM_LIT> || NumElems < <NUM_LIT> ) return ScalarCost ; if ( ExtSize == <NUM_LIT> ) return VectorCost ; if ( ExtSize != <NUM_LIT> && ExtSize != <NUM_LIT> ) return ScalarCost ; if ( const auto * BC = dyn_cast < BitCastInst > ( Ptr ) ) Ptr = BC -> getOperand ( <NUM_LIT> ) ; if ( const auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) return ScalarCost ; unsigned Scale = DL . getTypeAllocSize ( GEP -> getResultElementType ( ) ) ; if ( Scale != <NUM_LIT> && Scale * <NUM_LIT> != ExtSize ) return ScalarCost ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( GEP -> getOperand


<s> frame_size -= ( offset + crtl -> outgoing_args_size ) ; fp_offset = <NUM_LIT> ; if ( frame_size >= <NUM_LIT> ) { rtx op0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; emit_move_insn ( op0 , GEN_INT ( - frame_size ) ) ; insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , op0 ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - frame_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( frame_size > <NUM_LIT> ) { int hi_ofs = frame_size & <NUM_LIT> ; int lo_ofs = frame_size & <NUM_LIT> ; if ( hi_ofs ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - hi_ofs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( lo_ofs ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - lo_ofs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } else frame_size = - <NUM_LIT> ; if ( offset > <NUM_LIT> ) { bool skip_wb = false ; if ( frame_pointer_needed ) { skip_wb = true ; if ( fp_offset ) { insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( - offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; aarch64_save_callee_saves ( DImode , fp_offset , R29_REGNUM , R30_REGNUM , false ) ; } else aarch64_pushwb_pair_reg ( DImode , R29_REGNUM , R30_REGNUM , offset ) ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn )


<s> bool <ISA_LIT>DAGToDAGISel :: selectBDAddr ( <STR_LIT> DR , SDValue Addr , SDValue & Base , SDValue &


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ; if ( UnpckNode ) return UnpckNode ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 ,


<s> unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size == <NUM_LIT> )

return AtomicExpansionKind :: MaskedIntrinsic ;


<s> if ( ! insn || ! INSN_P ( insn ) ) return false ; return is_store_insn1 ( PATTERN (


<s> return ST -> isMClass ( ) && ST -> isThumb2 ( ) && L


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : assert ( MI -> getNumOperands ( ) >= <NUM_LIT> ) ; const MachineOperand & Reg = MI -> getOperand ( <NUM_LIT> ) ; assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & RegOrImm = MI -> getOperand ( <NUM_LIT> ) ; if ( RegOrImm . isImm ( ) ) break ; assert ( RegOrImm . isReg ( ) && <STR_LIT> ) ; assert ( RegOrImm . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( RegOrImm . getReg ( )


<s> static bool Is32BitMemOperand ( const MachineInstr & MI , unsigned Op ) { const MachineOperand & BaseReg = MI . getOperand ( Op + <STR_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return


<s> void FPS :: handleCall ( MachineBasicBlock :: iterator & I ) { MachineInstr & MI = * I ; unsigned STReturns = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isImplicit ( ) && <STR_LIT> ) ; if ( Op . isDef ( ) ) STReturns |= <NUM_LIT> << getFPReg ( Op ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) &&


<s> int _U_Qfunle ( long double a , long double


<s> bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction64 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>64 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler


<s> x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return


<s> if ( ! isTypeLegal ( EVT :: getEVT ( Ty1 ) ) ) return false ; assert ( Ty1 -> getPrimitiveSizeInBits ( )


<s> local_p = true ; } switch ( GET_CODE ( x ) ) { case SYMBOL_REF : return symbol_p && ! ( local_p && ! SYMBOL_REF_LOCAL_P ( x ) ) ; case


<s> unsigned Register = GPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> Dcpu16TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT

, CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( * this ) , FrameLowering ( ) {


<s> unsigned Opcode = MI -> getOpcode ( ) ; ReduceEntryVector :: const_iterator Start = std :: begin ( ReduceTable ) ; ReduceEntryVector :: const_iterator End = std :: end ( ReduceTable ) ; std :: pair < ReduceEntryVector :: const_iterator , ReduceEntryVector :: const_iterator > Range = std :: equal_range ( Start , End , Opcode ) ; if ( Range . first == Range . second ) return false ; for ( ReduceEntryVector :: const_iterator Entry = Range . first ; Entry != Range . second ; ++ Entry ) { ReduceEntryFunArgs Arguments ( & ( * MII ) , *


<s> const auto & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ( OptLevel >= CodeGenOpt :: Aggressive ) && ! STI . hasSVE ( ) ) return true ; return


<s> if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfoIgnore , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( UnsizedMemOp && NumSuccessfulMatches > <NUM_LIT> && UnsizedMemOp -> getMemFrontendSize ( ) ) { UnsizedMemOp -> Mem . Size = UnsizedMemOp -> getMemFrontendSize ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( M == Match_Success ) NumSuccessfulMatches = <NUM_LIT> ; InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , UnsizedMemOp -> getStartLoc ( ) , <NUM_LIT> , UnsizedMemOp -> getMemFrontendSize ( ) ) ; } if ( NumSuccessfulMatches == <NUM_LIT> ) { if ( ! MatchingInlineAsm && validateInstruction ( Inst , Operands ) ) return true ; if ( ! MatchingInlineAsm ) while ( processInstruction ( Inst , Operands ) ) ; Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) emitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } else if ( NumSuccessfulMatches > <NUM_LIT> ) { assert ( UnsizedMemOp && <STR_LIT> ) ; return Error ( UnsizedMemOp -> getStartLoc ( ) , <STR_LIT> + Mnemonic + <STR_LIT> , UnsizedMemOp -> getLocRange ( ) ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Unsupported ) == <NUM_LIT> ) { return Error ( IDLoc , <STR_LIT> ,


<s> assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm


<s> return ( __m64 ) __builtin_arm_wunpckelsh (


<s> } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO


<s> if ( ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return std :: max ( BaseT :: getVectorInstrCost ( Opcode , ValTy , Index ) , <NUM_LIT> ) ; } if ( ST -> hasMVEIntegerOps ( ) && ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { return std :: max ( BaseT :: getVectorInstrCost ( Opcode , ValTy , Index ) , ST -> getMVEVectorCostFactor

( ) ) * ValTy -> getVectorNumElements ( ) / <NUM_LIT> ;


<s> emitCodeAlignment ( <NUM_LIT> , & STI , <NUM_LIT> ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; MCFragment * InstructionFragment = getCurrentFragment ( ) ; SMLoc InstLoc = Inst . getLoc ( ) ; if ( LastLabel && ! LastLabel -> isUnset ( ) && LastLabelLoc . isValid ( ) && InstLoc . isValid ( ) ) { const SourceMgr * SourceManager = getContext ( ) . getSourceManager ( ) ; unsigned InstLine = SourceManager -> FindLineNumber ( InstLoc ) ; unsigned LabelLine = SourceManager -> FindLineNumber ( LastLabelLoc ) ; if ( InstLine ==


<s> MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && !


<s> bool isLegalMaskedGatherScatter ( Type * DataType ) const { if ( ! ST -> hasSVE ( ) ) return false ; auto * DataTypeFVTy = dyn_cast < FixedVectorType


<s> bool <ISA_LIT>TargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT == <STR_LIT>


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , false ) , DataLayout ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> : ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> : <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) ,

TLInfo ( * this ) , JITInfo ( * this ) {


<s> if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY


<s> FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = <STR_LIT> ( * I ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( I -> findRegisterUseOperand ( <STR_LIT> ) -> isUndef ( ) ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( & * I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto NewTBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( OldBranchCode == BranchCode && TBB == NewTBB ) continue ; if ( TBB == NewTBB && ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) ) { BranchCode = <STR_LIT> ; } else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) { if ( NewTBB != ( FBB ? FBB : getFallThroughMBB ( & MBB , TBB ) ) ) return true ; BranchCode = <STR_LIT> ; } else return


<s> alfbb . addStatement ( label + <STR_LIT> + MO_name + <STR_LIT> , <STR_LIT> , subtr ) ; SExpr * SP_times_8 = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , <STR_LIT> ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * str = ctx -> store ( ctx -> address ( <STR_LIT> , SP_times_8 ) , ctx -> load ( <NUM_LIT> , MO_name ) ) ; alfbb . addStatement ( label + <STR_LIT> + MO_name , string ( <STR_LIT> ) + MO_name


<s> HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSHSTK = false ; HasIBT = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastGather = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasMacroFusion = false ; HasERMSB = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; SlowTwoMemOps = false ; LEAUsesAG = false ; SlowLEA = false ; Slow3OpsLEA = false ; SlowIncDec = false ; stackAlignment =


<s> } SMLoc S = Tok . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , S ) ) ; Parser . Lex (


<s> SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , GA ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( ) ) ; return getAddrGlobal ( N , Ty , DAG , ( Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode (


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( N ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? <STR_LIT> :


<s> void IncomingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt || VA . getLocInfo ( ) == CCValAssign :: AExt ) { auto Load = buildLoad ( LLT :: scalar ( <NUM_LIT> ) , VA ) ; MIRBuilder . buildTrunc ( ValVReg , Load ) ; } else buildLoad ( ValVReg ,


<s> if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( Y . getOpcode ( ) == <STR_LIT> && Y . getOperand ( <NUM_LIT> ) == X && <STR_LIT> ( Y . getOperand ( <NUM_LIT> ) . getNode ( ) ) && X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { assert ( ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) && <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , X , Mask . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mask ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; EVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getNode ( <STR_LIT> , DL , BlendVT , X ) ; Y = DAG . getNode ( <STR_LIT> , DL , BlendVT , Y ) ; Mask = DAG . getNode ( <STR_LIT> , DL , BlendVT , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , BlendVT , Mask , Y , X ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Mask ) ; } } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) return true ; return false


<s> static SDValue lowerShuffleToEXPAND ( const SDLoc & DL , MVT VT , const APInt & Zeroable , ArrayRef < int > Mask , SDValue & V1 , SDValue & V2 , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { bool IsLeftZeroSide = true ; if ( ! isNonZeroElementsInOrder ( Zeroable , Mask , V1 . getValueType ( ) , IsLeftZeroSide ) ) return SDValue ( ) ; unsigned VEXPANDMask = ( ~ Zeroable ) . getZExtValue ( ) ; MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; SDValue VMask = getMaskNode ( MaskNode , <STR_LIT> ( <STR_LIT> , NumElts ) , Subtarget , DAG , DL ) ; SDValue ZeroVector = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue ExpandedVector = IsLeftZeroSide ? V2 : V1 ; return DAG . getNode ( <STR_LIT> , DL , VT , ExpandedVector , ZeroVector ,


<s> unsigned <ISA_LIT>BaseInstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent


<s> SDValue LRes = DAG . getNode ( Opcode , DL , VTs , Chain , L0 , L1 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , HRes , LRes ) ; SDValue Chains [ <NUM_LIT> ] = { H0 . getValue ( <NUM_LIT> ) , L0 . getValue ( <NUM_LIT> ) , H1 . getValue ( <NUM_LIT> ) , L1 . getValue ( <NUM_LIT> ) , HRes . getValue ( <NUM_LIT> ) , LRes . getValue ( <NUM_LIT> ) } ; SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; SDValue Ops [ <NUM_LIT> ] = { Res , NewChain } ; return DAG . getMergeValues ( Ops , DL ) ; } SDValue HRes = DAG . getNode ( Opcode , DL , <STR_LIT> , H0 , H1 ) ; SDValue LRes = DAG . getNode ( Opcode , DL , <STR_LIT> , L0 , L1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , HRes , LRes ) ; } if ( Chain )


<s> isLeft = false ; NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , false , DAG ) ; if ( ! NumZeros ) return false ; } bool SeenV1 = false ; bool SeenV2 = false ; for ( int i = NumZeros ; i < NumElems ; ++ i ) { int Val = isLeft ? ( i - NumZeros ) : i ; int Idx = SVOp -> getMaskElt ( isLeft ? i : ( i - NumZeros ) ) ; if ( Idx < <NUM_LIT> ) continue ; if ( Idx < NumElems ) SeenV1 = true ; else { Idx -= NumElems ; SeenV2 = true ; } if ( Idx != Val ) return


<s> unsigned char value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( value <= <NUM_LIT> && <STR_LIT>


<s> SDLoc dl ( Op ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; assert ( C && <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getValueType ( ) .


<s> static void MatchParallelMACSequences ( Reduction & R , OpChainList & Candidates ) { Instruction * Acc = R . AccIntAdd ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Acc ) ; std :: function < bool ( Value * ) > Match = [ & Candidates , & Match ] ( Value * V ) -> bool { auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; switch ( I -> getOpcode ( ) ) { case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) AddMACCandidate ( Candidates , I , MulOp0 , MulOp1 ) ; return


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst ,


<s> bool Changed = false ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > InstrsToErase ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { MachineInstr * DefMIToErase = nullptr ; if ( TII -> convertToImmediateForm ( MI , & DefMIToErase ) ) { Changed = true ; NumRRConvertedInPreEmit ++ ; DEBUG ( dbgs ( )


<s> static SDValue PerformBUILD_VECTORCombine ( SDNode * N ,


<s> mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( ! aarch64_pcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , <NUM_LIT> ) ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( dest , imm ) ) ; else { rtx mem = force_const_mem ( mode ,


<s> return ( float32x4_t ) __builtin_neon_vminnmv4sf ( a


<s> return ( __m64 ) __builtin_ia32_pminub ( ( __v8qi )


<s> return SrcScalarBits > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I ) : nullptr ) ; if ( CmpOpTy != nullptr && CmpOpTy -> isFloatingPointTy ( ) ) Cost ++ ; return Cost ; } } else if ( ST -> hasVector ( ) ) { assert ( Dst -> isVectorTy ( ) ) ; unsigned VF = cast < VectorType > ( Src ) -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT> || ST -> hasVectorEnhancements2 ( ) ) { if ( SrcScalarBits == DstScalarBits ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) ) ; unsigned TotCost = VF * ScalarCost


<s> uint64_t encoding = <STR_LIT> ( ~ MCE -> getValue ( ) , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( encoding


<s> for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi =


<s> vec_uint4 sixteen = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return ( ( qword ) ( vec_sl ( vec_mule ( ( vec_short8 ) ( a ) , ( vec_short8 ) ( vec_sl ( ( vec_uint4 ) ( b ) , sixteen )


<s> ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; if ( Mnemonic == <STR_LIT> ) Mnemonic = <STR_LIT> ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ? ( MCFixupKind ) <STR_LIT> : ( MCFixupKind ) <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> add_sve_type_attribute ( tuple_type , num_vectors , <NUM_LIT> , NULL , buffer ) ; make_type_sizeless ( tuple_type ) ; layout_type ( tuple_type ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( tuple_type ) ) && TYPE_MODE_RAW ( tuple_type ) == TYPE_MODE ( tuple_type ) && TYPE_ALIGN ( tuple_type ) == <NUM_LIT> ) ; tree decl = build_decl ( input_location , TYPE_DECL , get_identifier ( buffer ) , tuple_type ) ; TYPE_NAME ( tuple_type ) = decl ; TYPE_STUB_DECL ( tuple_type ) = decl ; lang_hooks . decls . pushdecl ( decl ) ; DECL_ORIGINAL_TYPE ( decl ) =


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> void addImm1_32Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > (


<s> static void sh_file_start ( void ) { default_file_start ( ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_ELF ) fprintf ( asm_out_file , <STR_LIT> , TEXT_SECTION_ASM_OP ) ; else data_section ( ) ; if ( TARGET_LITTLE_ENDIAN ) fputs ( <STR_LIT> , asm_out_file ) ; if ( ! TARGET_ELF ) { if ( TARGET_SHCOMPACT ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_SHMEDIA ) fprintf ( asm_out_file , <STR_LIT> , TARGET_SHMEDIA64


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const { switch ( Idx


<s> int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: Create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( DarwinRefKind != MCSymbolRefExpr :: VK_PAGE && DarwinRefKind != MCSymbolRefExpr :: VK_GOTPAGE && DarwinRefKind != MCSymbolRefExpr :: VK_TLVPPAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE

&& ELFRefKind != <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) {


<s> static MVT getRegOperandVectorVT ( const MCInst * MI , const MVT & ScalarVT


<s> Operands . push_back ( Chain . getOperand ( i ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Operands [ <NUM_LIT> ] , Operands . size ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Op . getOperand ( i * <NUM_LIT> + <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; else return DAG . getNode ( <STR_LIT> ,


<s> rtx function_expander :: get_fallback_value ( machine_mode mode , unsigned int nops , unsigned int merge_argno , unsigned int & argno ) { if ( pred == PRED_z ) return CONST0_RTX ( mode ) ; gcc_assert ( pred == PRED_m ||


<s> SMLoc ExprEnd ; if ( getParser ( ) . parseExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , MemStart , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . parseParenExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc


<s> if ( isa < ConstantSDNode > ( RHS ) || isa < ConstantSDNode > ( LHS ) ) return false ; bool IsRegisterWorthFolding = isWorthFolding ( N , UINT_MAX ) ; if ( ! IsRegisterWorthFolding ) { DEBUG_WITH_TYPE ( <STR_LIT> , dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Scale == <NUM_LIT> ) { Base = LHS ; Offset = RHS ; return true ; } if ( RHS . getOpcode ( ) == <STR_LIT> ) { const SDValue SRHS = RHS . getOperand ( <NUM_LIT> ) ; if ( auto C = dyn_cast < ConstantSDNode > ( SRHS ) ) { const uint64_t Shift = C -> getZExtValue ( ) ; if ( Shift == Scale ) { Base = LHS ; Offset = RHS . getOperand ( <NUM_LIT> ) ; return true ; } if ( ( Shift > Scale ) ) { auto val = Shift - Scale ; unsigned Immr = ( - val % <NUM_LIT> ) ; unsigned Imms = <NUM_LIT> - val ; assert ( ( Imms + <NUM_LIT> == Immr ) && <STR_LIT> ) ; SDValue ImmrInner = CurDAG -> getTargetConstant ( Immr , dl , <STR_LIT> ) ; SDValue ImmsInner = CurDAG -> getTargetConstant ( Imms , dl , <STR_LIT> ) ; SDNode * Inner = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ,

RHS . getOperand ( <NUM_LIT> ) , ImmrInner , ImmsInner ) ;


<s> void incNumLocalDynamicTLSAccesses (


<s> } uint64_t MaxNopLength = <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ; const uint8_t Rest = ThisNopLength - Prefixes ; if ( Rest != <NUM_LIT> ) OS . write ( Nops [ Rest - <NUM_LIT> ] , Rest ) ; Count -=


<s> MVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , NULL , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT>


<s> df_note_add_problem ( ) ; df_analyze ( ) ; mep_reorg_addcombine ( insns ) ; if ( ! mep_vliw_function_p ( cfun -> decl ) ) mep_reorg_regmove ( insns ) ; mep_jmp_return_reorg ( insns ) ; mep_bundle_insns ( insns ) ; mep_reorg_repeat ( insns ) ; if ( optimize && ! profile_flag && ! profile_arc_flag && TARGET_OPT_REPEAT && ( ! mep_interrupt_p ( ) || mep_interrupt_saved_reg

( RPB_REGNO ) ) ) mep_reorg_erepeat ( insns ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> ,


<s> } const MCConstantExpr * CE = static_cast < const MCConstantExpr * > ( getImm ( ) ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createReg


<s> sub = XEXP ( sub , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , <NUM_LIT> ) == UNSPEC_TOC ) return ret ; } } } else if ( crtl -> has_bb_partition && NOTE_P ( insn ) && NOTE_KIND ( insn )

== NOTE_INSN_SWITCH_TEXT_SECTIONS ) ret = <NUM_LIT> ;


<s> if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute ::

SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_RegMask ;


<s> SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MPI , SlotAlign , MachineMemOperand :: MOLoad ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF ) , PtrVT ) ; Align CPAlignment = cast < ConstantPoolSDNode > ( FudgePtr ) -> getAlign ( ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Four , Zero ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , CPAlignment ) ; Chain = Fudge . getValue ( <NUM_LIT> ) ; if ( IsStrict ) { SDValue Add = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , Fild , Fudge } ) ; if ( DstVT == <STR_LIT> ) return Add ; return DAG . getNode ( <STR_LIT> , dl , { DstVT , <STR_LIT> } , { Add . getValue ( <NUM_LIT> ) , Add , DAG . getIntPtrConstant


<s> getStreamer ( ) . setAttributeItem ( Attribute , Value ,