<s> bool hasTOCLoReloc ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) return true ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) return true ; } return false


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> ,


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfo64bit ( ) { if ( ! Subtarget . is64Bit ( ) ) return ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , TM . getPointerSizeInBits ( <NUM_LIT> ) ) ; const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; setAction ( { G_IMPLICIT_DEF , s64 } , Legal ) ; setAction ( { G_IMPLICIT_DEF , s128 } , Legal ) ; setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) { setAction ( { extOp , s64 } , Legal ) ; } getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s32 , s64 } ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) . clampScalar ( <NUM_LIT> , s32 , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> ) ; setAction ( { G_ICMP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR , G_SDIV } ) . legalFor ( { s8 , s16 , s32 , s64

} ) . clampScalar ( <NUM_LIT> , s8 , s64 ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } if ( ! isSafe && ! Sub ) return


<s> unsigned getMemDefaultBaseReg ( ) const { assert ( Kind == Memory && <STR_LIT>


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return DAG . getIntPtrConstant ( <NUM_LIT> * <NUM_LIT> ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { bool LocalChange = false ; for ( MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> printMemOperandEA ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O


<s> taint = inferTaintForCodeGen ( MI -> getPrevNode ( ) , <STR_LIT> , private_set ) ; if ( taint == - <NUM_LIT> || taint == <NUM_LIT> ) taint_flag += <NUM_LIT> ; taint_flag *= <NUM_LIT> ; taint = inferTaintForCodeGen ( MI -> getPrevNode ( ) , <STR_LIT> , private_set ) ; if ( taint == - <NUM_LIT> || taint == <NUM_LIT> ) taint_flag += <NUM_LIT> ; taint_flag *= <NUM_LIT> ; taint = inferTaintForCodeGen ( MI -> getPrevNode ( ) , <STR_LIT>


<s> const MCExpr * getImm ( ) const { assert ( Kind == Immediate && <STR_LIT> ) ; return Imm


<s> assert ( ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) && Subtarget -> hasMMX ( ) && ! DisableMMX ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector ( ) ) return Op ; if ( DstVT == <STR_LIT> && SrcVT . isVector ( ) ) return Op ; if ( SrcVT . isVector ( ) && DstVT . isVector ( ) ) return Op ; return SDValue (


<s> bool isMemWithSimmOffset ( ) const { return isMem ( ) && isConstantMemOff ( ) && isInt < Bits > ( getConstantMemOff


<s> bool <ISA_LIT>FastISel :: SelectIntExt ( const Instruction * I ) { Type * DestTy = I -> getType ( ) ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; EVT SrcVT , DestVT ; SrcVT = TLI . getValueType ( SrcTy , true ) ; DestVT = TLI . getValueType ( DestTy , true ) ; bool isZExt = isa < ZExtInst > ( I ) ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; unsigned ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , DestVT , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; UpdateValueMap ( I , ResultReg


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) return false ; if ( MSA_SUPPORTED_MODE_P ( mode ) ) return


<s> if ( ! Def ) return FirstInSelfLoop ; SmallSet < unsigned , <NUM_LIT> > Defs ; for ( unsigned i = <NUM_LIT> , e = Def -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = Def -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isUse ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> || Reg == <STR_LIT> ) continue ; Defs . insert ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i !=


<s> const static MCFixupKindInfo InfosBE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds


<s> bool isVectorIndex32 ( ) const { return isVectorIndexInRange < <NUM_LIT> > (


<s> Parser . Lex ( ) ; SMLoc SRegLoc = getLoc ( ) ; int RegNum = tryParseRegister ( ) ; RegKind RegisterKind = RegKind :: Scalar ; if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: NeonVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: NeonVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum ==


<s> static SDValue lowerV4X128VectorShuffle ( SDLoc DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr >


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>VSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true


<s> unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; assert ( Offset1 <=


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc dl ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( DAG


<s> RCPair <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT>


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const <ISA_LIT>Subtarget & Subtarget = FuncInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . is64BitELFABI ( ) ) return new

<ISA_LIT>FastISel ( FuncInfo , LibInfo ) ;


<s> if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTargetWin64 ( ) ) return & <STR_LIT> ; else if ( Subtarget . is64Bit ( ) ) return & <STR_LIT> ; const Function * F = MF . getFunction ( ) ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & <STR_LIT> ; return & <STR_LIT>


<s> bool hasShiftExtendAmount ( ) const { assert ( Kind == k_ShiftExtend


<s> if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { tree ptrtype = build_pointer_type ( type ) ; tree addr = std_gimplify_va_arg_expr ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > <NUM_LIT> :

TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ) {


<s> return parseAddress ( Operands , BDXMem ,


<s> int size ; if ( mode == DImode || TARGET_64BIT ) size = <NUM_LIT> ; else size = <NUM_LIT>


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { assert ( ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) && <STR_LIT> ) ; if ( Align >= <NUM_LIT> && ( getRegisterInfo ( ) . canRealignStack ( MF ) ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; }


<s> KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg


<s> unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) -

<NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ;


<s> EmitBinary ( OutStreamer , <STR_LIT> , RS1 ,


<s> void <ISA_LIT>PostRASchedStrategy :: schedNode ( SUnit * SU , bool IsTopNode ) { DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> unsigned <ISA_LIT>TTIImpl :: getCacheLineSize ( ) { if ( CacheLineSize . getNumOccurrences ( ) > <NUM_LIT> ) return CacheLineSize ; unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( CP -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || ( ( M == CodeModel :: Small || M == CodeModel :: Kernel ) && TM . getRelocationModel ( ) == Reloc :: Static ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } return false


<s> bool mayUseThunk ( const MachineFunction & MF


<s> if ( SYMBOL_REF_P ( base ) || LABEL_REF_P ( base ) ) { if ( aarch64_classify_symbol ( base , offset . to_constant ( ) ) != SYMBOL_FORCE_TO_MEM ) return true ; else return mode !=


<s> llvm :: InlineAsm * IA = llvm :: InlineAsm :: get ( AsmFTy , AsmString , <STR_LIT> , true , false , llvm :: InlineAsm :: AD_ATT ) ; CallInst :: Create ( IA , AsmArgs , <STR_LIT> , BB


<s> const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; } if ( ! isSingleSHUFPSMask ( Mask ) ) { if ( IsBlendSupported ) return lowerShuffleAsDecomposedShuffleMerge ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( SDValue Unpack = lowerShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Unpack ; } SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast (


<s> if ( llvm :: sys :: IsLittleEndianHost ) return pData >>


<s> void \ rdata_section ( ) \ { \ if ( in_section != in_rdata ) \ { \ fprintf ( asm_out_file , <STR_LIT> , RDATA_SECTION_ASM_OP ) ; \ in_section = in_rdata


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getThisReturnPreservedMask ( const MachineFunction


<s> xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; xops [ <NUM_LIT> ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; strcpy ( tmp , <STR_LIT> ) ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; output_asm_insn ( strcat ( tmp , & loop_lab [


<s> const MachineBasicBlock :: instr_iterator & E = Arguments -> MI -> getParent ( ) -> instr_end ( ) ; if ( NextMII == E ) return false ; MachineInstr * MI1 = Arguments -> MI ; MachineInstr * MI2 = & * NextMII ; bool ReduceToLwp = ( MI1 -> getOpcode ( ) == <STR_LIT> ) || ( MI1 -> getOpcode ( ) == <STR_LIT> ) || ( MI1 -> getOpcode ( ) == <STR_LIT> ) ; if ( ! CheckXWPInstr ( MI1 , ReduceToLwp , Entry ) ) return false ; if ( ! CheckXWPInstr ( MI2 , ReduceToLwp , Entry ) ) return


<s> if ( DEFAULT_ABI == ABI_ELFv2 ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx cr = gen_rtx_REG ( SImode , CR0_REGNO +


<s> SDValue MergeValues ( ArrayRef < SDValue >


<s> } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } if ( LP64 ) { if ( requiresRegisterScavenging ( MF ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ; } MBB . erase ( II


<s> static SDValue lowerV8F64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG .


<s> if ( reload_completed && rs6000_sched_groups ) { if ( sel_sched_p ( ) ) return ; if ( rs6000_sched_insert_nops == sched_finish_none ) return ; if ( rs6000_sched_insert_nops == sched_finish_pad_groups ) n_groups = pad_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; else n_groups = redefine_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; if ( sched_verbose >= <NUM_LIT> ) { fprintf ( dump , <STR_LIT> , n_groups


<s> addPass ( create<ISA_LIT>TDCPass ( ) ) ; addPass ( createLoopDataPrefetchPass ( )


<s> OperandMatchResultTy parseVR128 ( OperandVector


<s> PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; NonexecutableStackDirective = <STR_LIT>


<s> return ( __m128 ) __builtin_ia32_movss ( ( __v4sf )


<s> MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; unsigned ResultReg ; if ( SrcVT == <STR_LIT> ) { uint64_t Mask = <NUM_LIT> ; switch ( DestVT . SimpleTy ) { default : return false ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; case <STR_LIT> : Mask = <NUM_LIT> ; break ; } unsigned Reg32 = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , <STR_LIT> ) ; ResultReg = emitAnd_ri ( <STR_LIT> , Reg32 , Mask ) ; assert ( ResultReg && <STR_LIT> ) ; } else { ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SrcReg ) ; } updateValueMap ( I ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectT2CMOVSoImmOp ( SDNode * N , SDValue FalseVal , SDValue TrueVal , <STR_LIT> CCVal , SDValue CCR , SDValue InFlag ) { ConstantSDNode * T = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( ! T


<s> DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return <NUM_LIT> ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I ->


<s> assert ( MissingFeatures . any ( ) && <STR_LIT> ) ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MissingFeatures . size


<s> static DecodeStatus DecodeZPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> unsigned CC = <STR_LIT> ; if ( instrInITBlock ( ) ) CC = ITStates . back


<s> const_tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x ) || SYMBOL_REF_EXTERNAL_P (


<s> SDValue <ISA_LIT>TargetLowering :: addTokenForArgument ( SDValue Chain , SelectionDAG & DAG , MachineFrameInfo * MFI , int ClobberedFI ) const { SmallVector < SDValue , <NUM_LIT> > ArgChains ; int64_t FirstByte = MFI -> getObjectOffset ( ClobberedFI ) ; int64_t LastByte = FirstByte + MFI -> getObjectSize ( ClobberedFI ) - <NUM_LIT> ; ArgChains . push_back ( Chain ) ; for ( SDNode :: use_iterator U = DAG . getEntryNode ( ) . getNode ( ) -> use_begin ( ) , UE = DAG . getEntryNode ( ) . getNode ( ) -> use_end ( ) ; U != UE ; ++ U ) if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( * U ) ) if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode >

( L -> getBasePtr ( ) ) ) if ( FI -> getIndex ( ) < <NUM_LIT> ) {


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( <ISA_LIT>TargetMachine & <ISA_LIT>TM ) : TargetLowering ( <ISA_LIT>TM ) , Subtarget ( * <ISA_LIT>TM . getSubtargetImpl ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> void <ISA_LIT>AsmParser :: createAddu ( unsigned DstReg , unsigned SrcReg , unsigned TrgReg , SmallVectorImpl < MCInst > & Instructions ) { MCInst AdduInst ; AdduInst . setOpcode ( <STR_LIT> ) ; AdduInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; AdduInst . addOperand ( MCOperand :: createReg ( SrcReg ) ) ; AdduInst . addOperand ( MCOperand :: createReg ( TrgReg ) ) ; Instructions . push_back ( AdduInst


<s> M = F . getParent ( ) ; DL = & M -> getDataLayout ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LoopAccessInfo LAI ( L , SE , TLI , AA , DT , LI ) ; bool Changes = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; Changes = MatchSMLAD ( F ) ; return Changes


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> return ( __m128d ) __builtin_ia32_getexpsd128_round ( ( __v2df ) __A ,


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { bool is64 = getPointerSize ( )


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeRROperand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << TRI -> getAsmName ( MO2 . getReg


<s> EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( NewRetAddr ) , false , false , <NUM_LIT> ) ; if ( isDarwinABI ) { int NewFPLoc = SPDiff + <ISA_LIT>FrameLowering :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , MachinePointerInfo ::

getFixedStack ( NewFPIdx ) , false , false , <NUM_LIT> ) ;


<s> gcc_assert ( GET_MODE ( reg ) == mode ) ; gcc_assert ( GET_MODE ( base_reg ) == Pmode ) ; if ( load_p ) emit_move_insn ( reg , gen_rtx_MEM ( mode , base_reg ) ) ; else emit_move_insn ( gen_rtx_MEM ( mode , base_reg ) , reg ) ; emit_move_insn ( base_reg , plus_constant ( Pmode , base_reg


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI


<s> PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ; return false


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl ,


<s> mem = gen_frame_mem ( mode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( mode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( mode == DImode ) { rtx set1 , set2 ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset ) ) ; set1 = gen_rtx_SET ( VOIDmode , mem , gen_rtx_REG ( SImode , regno ) ) ; RTX_FRAME_RELATED_P ( set1 ) = <NUM_LIT> ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset + <NUM_LIT> ) ) ; set2 = gen_rtx_SET ( VOIDmode , mem , gen_rtx_REG ( SImode , regno + <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( set2 ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; } } else emit_move_insn ( gen_rtx_REG ( mode , regno


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count % <NUM_LIT> != <NUM_LIT>


<s> StringRef Name = <STR_LIT> ; return MCSymbolRefExpr :: create ( Context . getOrCreateSymbol ( Name ) ,

MCSymbolRefExpr :: VK_None , Context ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ?


<s> if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) return MCDisassembler :: Fail ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( featureBits [ <STR_LIT> ] && ! ( Val == <NUM_LIT> || Val == <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( featureBits [ <STR_LIT> ] && ( ( Val & <NUM_LIT> ) == <NUM_LIT> || ( Val & <NUM_LIT> ) == <NUM_LIT> || ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true


<s> Align Alignment = std :: max ( TargetAlign , MaxAlign ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC (

) && ! RegInfo -> hasBasePointer ( MF ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = { MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) , <STR_LIT> } ; } else if ( Tagged ) { StackOffset SPOffset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; }


<s> if ( OrigTy . getSizeInBits ( ) >= <NUM_LIT> ) return N ; EVT NewVT = getExtensionTo64Bits ( OrigTy ) ; return DAG . getNode ( ExtOpcode , SDLoc ( N


<s> auto MovMI = MIB . buildInstr ( <STR_LIT> , { DstReg } , { } ) . addJumpTableIndex ( JTI , <STR_LIT> ) . addJumpTableIndex ( JTI , <STR_LIT> | <STR_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MovMI , TII , TRI , RBI


<s> void mmix_make_decl_one_only ( tree decl ) { DECL_WEAK ( decl ) =


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiv16qi ( ( int8x16_t


<s> SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty ,

getTargetNode ( N , Ty , DAG , LoFlag ) ) ;


<s> if ( FB [ <STR_LIT> ] ) { fMode = MODE_16BIT ; return ; } else if ( FB [ <STR_LIT> ] ) { fMode = MODE_32BIT ; return ; } else if ( FB [ <STR_LIT> ] ) { fMode =


<s> assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBaseReg ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemSegReg (


<s> deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame


<s> for ( unsigned J = <NUM_LIT> , E = BBOffsets . size ( ) ; J != E ; ++ J ) { DEBUG ( errs ( ) << <STR_LIT> << J << <STR_LIT> << BBOffsets [ J ] <<

<STR_LIT> << BBSizes [ J ] << <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printSVELogicalImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { typedef std :: make_signed_t < T > SignedT ; typedef std :: make_unsigned_t < T > UnsignedT ; uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; UnsignedT PrintVal = <STR_LIT> ( Val , <NUM_LIT> ) ; if ( ( int16_t ) PrintVal == ( SignedT ) PrintVal ) printImmSVE ( ( T ) PrintVal , O ) ; else if ( ( uint16_t ) PrintVal == PrintVal


<s> return ( int64x1_t ) __builtin_neon_vld1_lanedi ( ( const __builtin_neon_di * ) __a , __b


<s> if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root ,


<s> MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88


<s> else { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI .


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent (


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; auto * CondBV = cast < BuildVectorSDNode > ( Cond ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> , Size = VT . getVectorNumElements ( ) ; i < Size ; ++ i ) { SDValue CondElt = CondBV -> getOperand ( i ) ; Mask . push_back ( isa < ConstantSDNode > ( CondElt ) ? i + ( isNullConstant ( CondElt ) ? Size : <NUM_LIT>


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable (


<s> SDValue Pred = Op . getOperand ( <NUM_LIT> ) ; SDValue InVec = Op . getOperand ( <NUM_LIT> ) ; if ( isTypeLegal ( InVec . getValueType ( ) ) ) return Op ; EVT VT = Op . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) { EVT IntResVT = VT . changeTypeToInteger ( ) ; EVT IntVecVT = InVec . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDValue IntInVec = DAG . getNode ( <STR_LIT> , DL , IntVecVT , InVec ) ; SDValue Res = DAG . getNode ( Op . getOpcode ( ) , DL , IntResVT , Pred , IntInVec ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res ) ; } assert ( isTypeLegal ( Pred . getValueType ( ) ) && <STR_LIT> ) ; EVT EltVT = InVec . getValueType ( ) . getVectorElementType ( ) ; EVT NewEltVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT SplitVT = InVec . getValueType ( ) . changeVectorElementType ( NewEltVT ) ; SDValue InVecLo , InVecHi ; std :: tie ( InVecLo , InVecHi ) = DAG . SplitVector ( InVec , DL ) ; InVecLo = DAG . getNode ( <STR_LIT> , DL , SplitVT , InVecLo ) ; InVecHi = DAG . getNode ( <STR_LIT> ,


<s> return create<ISA_LIT>ELFObjectWriter ( OS


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; const Constant * C = LoadMI -> getOpcode ( ) == <STR_LIT> ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default


<s> inline vector signed int vec_vaddsws ( vector signed int a1 , vector signed int a2


<s> unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : { IsZExt = true ; unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case


<s> static void ReplaceCMP_SWAP_128Results ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget -> hasLSE ( ) ) { SDValue Ops [ ] = { createGPRPairNode ( DAG , N -> getOperand ( <NUM_LIT> ) ) , createGPRPairNode ( DAG , N -> getOperand ( <NUM_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , } ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; unsigned Opcode ; switch ( MemOp -> getOrdering ( ) ) { case AtomicOrdering :: Monotonic : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: Acquire : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: Release : Opcode = <STR_LIT> ; break ; case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MachineSDNode * CmpSwap = DAG . getMachineNode ( Opcode , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; DAG . setNodeMemRefs ( CmpSwap , { MemOp } ) ; unsigned SubReg1 = <STR_LIT> , SubReg2 = <STR_LIT> ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( SubReg1 , SubReg2 ) ; Results . push_back ( DAG . getTargetExtractSubreg ( SubReg1 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( DAG . getTargetExtractSubreg ( SubReg2 , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; return ; } auto Desired = splitInt128 ( N -> getOperand ( <NUM_LIT>


<s> LUi = <STR_LIT> ; InstSeqLs SeqLs ; if ( LastInstrIsADDiu | ! Imm ) GetInstSeqLsADDiu ( Imm , Size , SeqLs ) ; else GetInstSeqLs ( Imm , Size , SeqLs ) ; GetShortestSeq ( SeqLs , Insts ) ; return Insts


<s> if ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ <NUM_LIT> ] , sel [ <NUM_LIT> ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return false ; if ( altivec_expand_vec_perm_const ( target , op0 ,


<s> int64x2x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [


<s> MachineInstr & Terminator = * ( -- From -> terminators ( ) . end ( ) ) ; if ( ! Terminator . isUnconditionalBranch ( ) ) { unsigned BrOpc = BBUtils -> isBBInRange ( & Terminator , To , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( From , Terminator . getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . addMBB ( To ) ; MIB . addImm ( <STR_LIT> :: AL ) ; MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ; } } ; if ( BBPrevious -> isSuccessor ( BB ) ) FixFallthrough ( BBPrevious , BB ) ; if ( AfterNext && After -> isSuccessor ( AfterNext ) ) FixFallthrough ( After , AfterNext ) ; if ( BBNext && BB -> isSuccessor ( BBNext ) ) FixFallthrough ( BB , BBNext ) ; BBUtils -> adjustBBOffsetsAfter ( After


<s> uint32_t UnmaskedReg = RegSave & <NUM_LIT> & ( ~ Mask ) ; if ( UnmaskedReg == <NUM_LIT> ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= <NUM_LIT> ; } else if ( UnmaskedReg == ( <NUM_LIT> << <NUM_LIT> ) ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= <NUM_LIT> ; } } if ( ( RegSave & <NUM_LIT> ) != <NUM_LIT> ) EmitInt16 ( <STR_LIT> :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >>


<s> ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , pixel_type_node ) ) ; bool_V16QI_type_node = build_vector_type ( bool_char_type_node , <NUM_LIT> ) ; bool_V8HI_type_node = build_vector_type ( bool_short_type_node , <NUM_LIT> ) ; bool_V4SI_type_node = build_vector_type ( bool_int_type_node , <NUM_LIT> ) ; pixel_V8HI_type_node = build_vector_type ( pixel_type_node , <NUM_LIT> ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , unsigned_V16QI_type_node ) ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , V16QI_type_node ) ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , bool_V16QI_type_node ) ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , unsigned_V8HI_type_node ) ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , V8HI_type_node ) ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier ( <STR_LIT> ) , bool_V8HI_type_node ) ) ; ( * lang_hooks . decls . pushdecl ) ( build_decl ( TYPE_DECL , get_identifier (

<STR_LIT> ) , unsigned_V4SI_type_node ) ) ;


<s> return NULL_TREE ; case ARM_PCS_SVE : error ( <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; case ARM_PCS_TLSDESC : case


<s> initialize<ISA_LIT>MIPeepholePass ( * PassRegistry ::


<s> rtx mem ; rtx_insn * insn ; mem = spill_restore_mem ( reg , cfa_off ) ; insn = emit_insn ( ( * move_fn ) ( mem , reg , GEN_INT ( cfa_off ) ) ) ; spill_fill_data . prev_insn [ iter ] = insn ; if ( frame_reg ) { rtx base ; HOST_WIDE_INT off ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( frame_pointer_needed ) { base = hard_frame_pointer_rtx ; off = -


<s> SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL


<s> inline vector signed char vec_xor ( vector signed char a1 , vector signed char a2 ) { return ( vector signed char ) __builtin_altivec_vxor ( ( vector signed int ) a1


<s> AM . GV = GA -> getGlobal ( ) ; AM . Disp += GA -> getOffset ( ) ; AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , N . getValueType ( ) ) ; AM . SymbolFlags = GA -> getTargetFlags ( ) ; if ( N . getValueType ( ) == <STR_LIT> ) { AM . Scale


<s> if ( op2_def . set_src == NULL_RTX || ! MEM_P ( op2_def . set_src ) || GET_MODE ( op2_def . set_src ) != QImode || ! rx_is_restricted_memory_address ( XEXP ( op2_def . set_src , <NUM_LIT> ) , GET_MODE ( op2_def . set_src ) ) || reg_used_between_p ( operands [ <NUM_LIT> ] , op2_def . insn , curr_insn ) || ! rx_reg_dead_or_unused_after_insn ( curr_insn , REGNO ( op2_reg ) ) ) return false ; rtx mem = op2_def . set_src ; if ( GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == POST_INC || GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == POST_DEC || GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == PRE_DEC ) return false ; rtx_insn * op0_use = rx_find_use_of_reg ( operands [ <NUM_LIT> ] , curr_insn , next_nonnote_nondebug_insn_bb ) ; if ( op0_use == NULL || ! ( GET_CODE ( PATTERN ( op0_use ) ) == SET && RX_REG_P ( XEXP ( PATTERN ( op0_use ) , <NUM_LIT> ) ) && reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , XEXP ( PATTERN ( op0_use ) , <NUM_LIT> ) ) && rtx_equal_p ( mem , XEXP ( PATTERN ( op0_use ) , <NUM_LIT> ) ) ) || ! rx_reg_dead_or_unused_after_insn ( op0_use , REGNO ( operands [ <NUM_LIT> ] ) ) || reg_set_between_p ( operands [

<NUM_LIT> ] , curr_insn , op0_use ) ) return false ;


<s> else if ( REG_P ( addr_op0 ) && CONST_INT_P ( addr_op1 ) ) pattern = <STR_LIT> ; else if ( GET_CODE ( addr_op0 ) == MULT && REG_P ( addr_op1 ) && REG_P ( XEXP ( addr_op0 , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( addr_op0 , <NUM_LIT> ) ) ) pattern = <STR_LIT> ; else gcc_unreachable ( ) ; break ; case POST_MODIFY : addr_op0 = XEXP ( addr , <NUM_LIT> ) ; addr_op1 = XEXP ( addr , <NUM_LIT> ) ; if ( REG_P ( addr_op0 ) && GET_CODE ( addr_op1 ) == PLUS && REG_P ( XEXP ( addr_op1 , <NUM_LIT> ) ) ) pattern = <STR_LIT> ; else if ( REG_P ( addr_op0 ) && GET_CODE ( addr_op1 ) == PLUS && CONST_INT_P ( XEXP ( addr_op1 , <NUM_LIT> ) ) ) pattern = <STR_LIT> ; else gcc_unreachable ( ) ; break ; case POST_INC : if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) { if ( dp ) pattern = <STR_LIT> ; else pattern = <STR_LIT> ; } else gcc_unreachable ( ) ; break ; case POST_DEC : if ( REG_P ( XEXP ( addr , <NUM_LIT>


<s> vld1q_lane_p8 ( const poly8_t * __a , poly8x16_t __b , const int __c ) { return ( poly8x16_t ) __builtin_neon_vld1_lanev16qi ( ( const __builtin_neon_qi * )


<s> SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; RTLIB :: Libcall LC = ArgVT == <STR_LIT> ? RTLIB :: SINCOS_STRET_F64 : RTLIB :: SINCOS_STRET_F32 ; const char * LibcallName = getLibcallName ( LC ) ; SDValue Callee = DAG . getExternalFunctionSymbol ( LibcallName ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: Fast , RetTy , Callee , std :: move


<s> op = XEXP ( op , <NUM_LIT> ) ; if ( REG_P ( op ) ) return true ; switch GET_CODE ( op ) { case PLUS : { if ( ! REG_P ( XEXP ( op , <NUM_LIT> ) ) ) return false ; op = XEXP ( op , <NUM_LIT> ) ; if ( ! CONST_INT_P ( op ) ) return false ; range = INTVAL ( op ) ; if ( ! IN_RANGE ( range , - <NUM_LIT> , <NUM_LIT> ) ) return false ; return ( range % <NUM_LIT> ) == <NUM_LIT> ; } case PRE_INC : case


<s> if ( ! TARGET_SSE ) { if ( warn ) { if ( decl ) error ( <STR_LIT> <STR_LIT> , decl ) ; else error ( <STR_LIT> <STR_LIT> , type ) ; } return <NUM_LIT> ; } return <NUM_LIT> ; } if ( ! decl ) return <NUM_LIT> ; cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && ( target_opts_for_fn ( target -> decl ) -> x_ix86_fpmath & FPMATH_SSE ) && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { if ( ! TARGET_SSE && warn ) return - <NUM_LIT> ; return TARGET_SSE2_P ( target_opts_for_fn ( target -> decl ) -> x_ix86_isa_flags ) ? <NUM_LIT>


<s> for ( ls = sr -> labeled_states ; ls ; ls = ls -> next ) { if ( ls -> label == label ) { free_state_stack ( & sr -> curr ) ; memcpy ( & sr -> curr , & ls -> saved_state , sizeof ( sr ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl


<s> Align Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getAlignValue ( ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I ->


<s> auto Undef = B . buildUndef ( SrcTy ) ; DupSrc = B . buildConcatVectors ( SrcTy . changeElementCount ( ElementCount :: getFixed ( <NUM_LIT> ) ) , { Src1Reg , Undef . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ; } B . buildInstr ( MatchInfo . first , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) } , { DupSrc , Lane } ) ; MI . eraseFromParent ( ) ; return true


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> void printDstIdx16 ( const MCInst * MI , unsigned


<s> if ( optimize_size ) { bool src_aligned = MEM_ALIGN ( operands [ <NUM_LIT> ] ) >= BITS_PER_WORD ; bool dst_aligned = MEM_ALIGN ( operands [ <NUM_LIT> ] ) >= BITS_PER_WORD ; unsigned int interleave_factor = ( src_aligned || dst_aligned ) ? <NUM_LIT> : <NUM_LIT> ; HOST_WIDE_INT bytes_per_iter = ( src_aligned || dst_aligned ) ? <NUM_LIT> : <NUM_LIT> ; if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor , bytes_per_iter ) ; else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor ) ; } else { if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> , <NUM_LIT> ) ; else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length ,


<s> if ( i > M || M >= HalfSize ) return SDValue ( ) ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ; } return SDValue ( ) ; } if ( Idx < <NUM_LIT> ) return SDValue ( ) ; assert ( ( Idx + Len ) <= HalfSize && <STR_LIT> ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base ; if ( isUndefInRange ( Mask , <NUM_LIT> , Idx ) ) { } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , <NUM_LIT> ) ) { Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize


<s> return ( uint16x4_t ) __builtin_aarch64_raddhnv4si ( ( int32x4_t )


<s> DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; uint64_t Masks [ ] = { KnownZero [ <NUM_LIT> ] . getZExtValue ( ) , KnownZero [ <NUM_LIT> ] . getZExtValue ( ) } ; unsigned High , Low ; if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else return Op ; SDValue LowOp = Ops [ Low ] ; SDValue HighOp = Ops [ High ] ; if ( HighOp . getOpcode ( ) == <STR_LIT> ) return Op ; if ( LowOp . getOpcode ( ) == <STR_LIT> ) { int64_t Value = int32_t ( cast < ConstantSDNode > ( LowOp )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo


<s> bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get


<s> bool <ISA_LIT>FastISel :: isTypeSupported ( Type * Ty , MVT & VT , bool IsVectorAllowed ) { if ( Ty -> isVectorTy ( ) && ! IsVectorAllowed ) return false ; if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> )


<s> NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) ->


<s> if ( ! Streamer . IsThumb ) return ; Streamer . getAssembler ( ) . registerSymbol ( * Symbol ) ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T ,

unsigned SyntaxVariant , const MCAsmInfo & MAI ) {


<s> unsigned getAddrMode6OneLane32AddressOpValue ( const MachineInstr & MI , unsigned


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) ->


<s> SDValue CMP1 = N1 -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( CMP0 . getOpcode ( ) != <STR_LIT> || CMP0 != CMP1 ) return SDValue ( ) ; SDValue CMP00 = CMP0 -> getOperand ( <NUM_LIT> ) ; SDValue CMP01 = CMP0 -> getOperand ( <NUM_LIT> ) ; EVT VT = CMP00 . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { bool ExpectingFlags = false ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; ! ExpectingFlags && UI != UE ; ++ UI ) switch ( UI -> getOpcode ( ) ) { default : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ExpectingFlags = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { bool is64BitFP = ( CMP00 . getValueType ( )


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ; return new ELF<ISA_LIT>AsmBackend ( T , IsLittleEndian ? <STR_LIT> : <STR_LIT> , OSABI


<s> unsigned getReg ( ) const override { assert ( isReg ( ) && <STR_LIT> ) ; return Reg .


<s> bool isMem128_RC128 ( ) const { return isMem128 ( ) && isMemIndexReg


<s> return __builtin_mve_vcaddq_rot90v16qi ( __a ,


, ( __mmask32 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> SDValue FIN = DAG . getFrameIndex ( GPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicGPR ; i < NumArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( <ISA_LIT>ArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } } if ( getSubtarget ( ) -> hasFPARMv8 ( ) ) { unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( <ISA_LIT>FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } } FuncInfo -> setVariadicFPRIdx ( FPRIdx ) ; FuncInfo -> setVariadicFPRSize ( FPRSaveSize ) ; } int StackIdx = MFI -> CreateFixedObject ( <NUM_LIT> , CCInfo


<s> SDValue <ISA_LIT>TargetLowering :: getAddrLarge ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; const unsigned char MO_NC


<s> case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) )


<s> SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isVMOVModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , VT , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } NewVal = isVMOVModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , VT , VMVNModImm ) ; if ( NewVal != SDValue ( )


<s> Value * <ISA_LIT>IREmitter :: visitVSHL (


<s> const char * p ; symbol_type = mips_classify_symbolic_expression ( op , context ) ; gcc_assert ( relocs [ symbol_type ] ) ; fputs ( relocs [ symbol_type ] , file ) ; output_addr_const ( file , mips_strip_unspec_address ( op )


<s> if ( TT . isOSBinFormatELF ( ) ) { unsigned Type ; if ( TT . is<ISA_LIT>64 ( ) ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; } if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > (


<s> HOST_WIDE_INT offset ; char buf [ <NUM_LIT> ] ; int i ; switch ( store_multiple_sequence ( operands , nops , regs , & base_reg , & offset ) ) { case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } sprintf ( buf + strlen ( buf ) , <STR_LIT> , REGISTER_PREFIX , reg_names [ base_reg ] , REGISTER_PREFIX ,


<s> CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; return ! ( TARGET_HITACHI || ca -> renesas_abi


<s> EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue Max = DAG . getNode ( <STR_LIT> , DL , VT , Op1 , Op0 ) ; SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0 , Op0 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> pcmpgth_u ( uint16x4_t s , uint16x4_t t ) { return __builtin_loongson_pcmpgth_u ( s , t


<s> Addr = N ; unsigned Alignment = <NUM_LIT> ; MemSDNode * MemN = cast < MemSDNode > ( Parent ) ; if ( isa < LSBaseSDNode > ( MemN ) || ( ( MemN -> getOpcode ( ) == <STR_LIT> || MemN -> getOpcode (

) == <STR_LIT> ) && MemN -> getConstantOperandVal ( MemN -> getNumOperands ( ) - <NUM_LIT> ) == <NUM_LIT> ) ) {


<s> EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal << <NUM_LIT>


<s> if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI ,


<s> for ( int i = MI . getNumOperands ( ) - <NUM_LIT> ; i > OperandToKeep ; i -- ) MI . RemoveOperand ( i ) ; if ( LII . SetCR ) { MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII . Imm ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return ; } else MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI


<s> assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= ( RC -> getSize ( ) / <NUM_LIT> ) && <STR_LIT> ) ; unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI .


<s> return ( __m128d ) __builtin_ia32_vfmaddpd ( - ( __v2df ) __A , (


<s> WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , nullptr , - <NUM_LIT> , <NUM_LIT> ) ; CurFrame -> EpilogMap [ CurrentEpilog ] . push_back ( Inst ) ; CurrentEpilog = nullptr


<s> bool hasSSE4A ( ) const { return HasSSE4A


<s> MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; const MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; Register TempReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DesiredReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsThumb ) { assert ( STI -> hasV8MBaselineOps ( ) && <STR_LIT> ) ; assert ( ( UxtOp == <NUM_LIT> || UxtOp == <STR_LIT> || UxtOp == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( UxtOp == <NUM_LIT> || <STR_LIT> . contains ( DesiredReg ) ) && <STR_LIT> ) ; } MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; if (


<s> SDLoc dl ( Op ) ; SDValue Index = N -> getIndex ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue Chain = N -> getChain ( ) ; SDValue BasePtr = N -> getBasePtr ( ) ; MVT MemVT = N -> getMemoryVT ( ) . getSimpleVT ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT MaskVT = Mask . getSimpleValueType ( ) ; if ( MemVT . getScalarSizeInBits ( ) < VT . getScalarSizeInBits ( ) ) { assert ( ( MemVT == <STR_LIT> && VT == <STR_LIT> ) && <STR_LIT> ) ; int ShuffleMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Src = DAG . getVectorShuffle ( <STR_LIT> , dl , DAG . getBitcast ( <STR_LIT> , Src ) , DAG . getUNDEF ( <STR_LIT> ) , ShuffleMask ) ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , <NUM_LIT> ) ; Index = ExtendToType ( Index , NewIndexVT , DAG ) ; assert ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , <NUM_LIT> ) ; Mask = ExtendToType ( Mask , ExtMaskVT , DAG , true ) ; VT = <STR_LIT> ; } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { if ( IndexVT == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; else { NumElts = <NUM_LIT> ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType (


<s> rtx val ; if ( TARGET_SHCOMPACT && ( ( current_function_args_info . call_cookie & ~ CALL_COOKIE_RET_TRAMP ( <NUM_LIT> ) ) || current_function_has_nonlocal_label ) ) return gen_frame_mem ( SImode , return_address_pointer_rtx ) ; val = get_hard_reg_initial_val ( Pmode , TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ; if ( TARGET_SH1 ) return gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT>


<s> bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysCR ( CRNum , S , getLoc (


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_avg_pu8 ( __m64 __A , __m64 __B ) { __vector unsigned char a , b , c ; a = ( __vector unsigned char ) vec_splats ( __A ) ; b = ( __vector unsigned char ) vec_splats ( __B ) ; c = vec_avg ( a


<s> SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( NumSignBits != InSVT . getSizeInBits ( ) ) return SDValue ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; return truncateVectorCompareWithPACKSS ( VT , In , DL , DAG ,


<s> Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( Enable<ISA_LIT>LongCalls ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CS . arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned


<s> static bool aarch64_scalar_builtin_type_p ( aarch64_simd_type t ) { return ( t == Poly8_t || t == Poly16_t || t == Poly64_t ||


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { if ( Count % <NUM_LIT> != <NUM_LIT> )


<s> void addThumbModImmNeg1_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Val = - CE -> getValue


<s> __inline__ static unsigned long long sh_media_MCNVS_WB ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn


<s> EVT Evt = TLI . getValueType ( DL , Ty , true ) ; if ( Evt == <STR_LIT> || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal (


<s> case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : return false ; } const MachineOperand & MO = I -> getOperand


<s> temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) temp . val [


<s> bool LE = TM . isLittleEndian ( ) ; std :: string Name ( F . getName ( ) ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType ( ) ) ; FPParamVariant PV = whichFPParamVariantNeeded ( F ) ; std :: string AsmText ; AsmText += <STR_LIT> ; AsmText += swapFPIntParams ( PV , M , LE , true ) ; if ( RV != NoFPRet ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } else { AsmText += <STR_LIT> + Name + <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } switch ( RV ) { case FRet : AsmText += <STR_LIT> ; break ; case DRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CFRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CDRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case NoFPRet : break ; } if ( RV != NoFPRet )


<s> unsigned getVectorListCount ( ) const { assert ( Kind == k_VectorList && <STR_LIT> ) ; return VectorList . Count


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = VMRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm


<s> offset -= UNITS_PER_WORD ; } for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . acc_mask ,

( ( regno - DSP_ACC_REG_FIRST ) / <NUM_LIT> ) + <NUM_LIT> ) ) {


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == <STR_LIT> ) || ( FlagSfiStore && N -> getOpcode ( ) == <STR_LIT> ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD ->


<s> } else { if ( regno_base == SP_REGNUM ) sprintf ( pattern , <STR_LIT> , conditional ) ; if ( update ) sprintf ( pattern , <STR_LIT> , conditional ) ; else sprintf ( pattern , <STR_LIT> , conditional ) ; strcat ( pattern , reg_names [ regno_base ] ) ; if ( update ) strcat ( pattern , <STR_LIT> ) ; else strcat ( pattern , <STR_LIT> ) ; } strcat ( pattern , reg_names [ REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , offset ) , <NUM_LIT> ) ) ] ) ; for ( i = offset + <NUM_LIT> ; i < num_saves ; i ++ ) { strcat ( pattern , <STR_LIT> ) ; strcat ( pattern , reg_names [ REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , i ) , <NUM_LIT> ) ) ] ) ; } strcat ( pattern , <STR_LIT> ) ; if ( IS_INTERRUPT ( arm_current_func_type ( ) ) && return_pc ) strcat ( pattern , <STR_LIT> ) ; output_asm_insn ( pattern , & cond )


<s> SmallVector < int , <NUM_LIT> > MaskVec ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( MaskVec [ i ] > ( int ) NumElems ) { MaskVec [ i ] = NumElems ; Changed = true ; } } if ( Changed ) return DAG . getVectorShuffle ( VT , SVOp -> getDebugLoc ( ) , SVOp -> getOperand ( <NUM_LIT> ) , SVOp -> getOperand (

<NUM_LIT> ) , & MaskVec [ <NUM_LIT> ] ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( <ISA_LIT>TargetMachine


<s> bool ListContainsPC = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; if ( ! IsARPop && ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC && ListContainsLR ) return Error ( Operands [ ListNo +


<s> if ( ( N . getOpcode ( ) == <STR_LIT> ) || ( N . getOpcode ( ) == <STR_LIT> && ( N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) ) ) return true ; return


<s> int Base = ( int ) fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( FGR64RegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; return MCDisassembler


<s> static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT .


<s> if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ; else return


<s> case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT>


<s> unsigned NumMaskElts = Mask . size ( ) ; unsigned NumLanes = MaskVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumEltsPerLane = NumMaskElts / NumLanes ; bool FloatDomain = MaskVT . isFloatingPoint ( ) ; if ( ! FloatDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) ) ) { for ( unsigned Shift = <NUM_LIT> ; Shift != NumEltsPerLane ; ++ Shift ) { bool IsVSHLDQ = true ; bool IsVSRLDQ = true ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { unsigned Base = Lane * NumEltsPerLane ; unsigned Ofs = NumEltsPerLane - Shift ; IsVSHLDQ &= isUndefOrZeroInRange ( Mask , Base , Shift ) ; IsVSHLDQ &= isSequentialOrUndefInRange ( Mask , Base + Shift , Ofs , Base ) ; IsVSRLDQ &= isUndefOrZeroInRange ( Mask , Base + Ofs , Shift ) ; IsVSRLDQ &= isSequentialOrUndefInRange ( Mask , Base , Ofs , Base + Shift ) ; if ( ! IsVSHLDQ && ! IsVSRLDQ ) break ; } if ( IsVSHLDQ ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , NumLanes * <NUM_LIT> ) ; PermuteImm = Shift * ( MaskVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; return true ; } if ( IsVSRLDQ ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , NumLanes * <NUM_LIT> ) ; PermuteImm = Shift * ( MaskVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; return true ; } } } for ( int M : Mask ) { if ( M == SM_SentinelZero ) return false ; assert ( SM_SentinelUndef <= M && M < ( int ) Mask . size ( ) && <STR_LIT> ) ; } unsigned InputSizeInBits = MaskVT . getSizeInBits ( ) ; unsigned MaskScalarSizeInBits = InputSizeInBits / Mask . size ( ) ; MVT MaskEltVT = <STR_LIT> ( MaskScalarSizeInBits ) ; if ( MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange

( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) {


<s> if ( I . getOperand ( <NUM_LIT> ) . getIntrinsicID ( ) != <STR_LIT> ) return false ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII


<s> sinkMBB -> addSuccessor ( exitMBB , BranchProbability :: getOne ( ) ) ; BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Scratch ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop1MBB , DL , TII -> get ( <STR_LIT> ) , Scratch2 ) . addReg ( Scratch ) . addReg ( Mask ) ; BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Scratch2 ) . addReg ( ShiftCmpVal ) . addMBB ( sinkMBB ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addReg ( Scratch , RegState :: Kill ) . addReg ( Mask2 ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addReg ( Scratch , RegState :: Kill ) . addReg ( ShiftNewVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( SC ) , Scratch ) . addReg ( Scratch , RegState :: Kill ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop2MBB , DL , TII -> get ( BEQ ) ) . addReg ( Scratch , RegState :: Kill ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Scratch2 ) . addReg ( ShiftAmnt ) ; if ( STI -> has<ISA_LIT>32r2 ( ) ) { BuildMI ( sinkMBB , DL , TII -> get ( SEOp ) , Dest ) . addReg ( Dest ) ; } else { const unsigned ShiftImm = I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; } LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * loop1MBB ) ; computeAndAddLiveIns ( LiveRegs , * loop2MBB ) ; computeAndAddLiveIns ( LiveRegs , * sinkMBB ) ; computeAndAddLiveIns ( LiveRegs , * exitMBB ) ; NMBBI = BB . end ( ) ; I -> eraseFromParent


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( OpNum == <NUM_LIT> ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } break ; case <STR_LIT> : isFloat = true ; case <STR_LIT> : if ( OpNum == <NUM_LIT>


<s> int ObjectOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; return RegInfo -> getLocalAddressRegister ( MF ) == <STR_LIT> ? getFPOffset ( MF , ObjectOffset ) . getFixed ( ) :

getStackOffset ( MF , ObjectOffset ) . getFixed ( ) ;


<s> auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit , OSABI ) ; return createELFObjectWriter ( std :: move ( MOTW


<s> if ( TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A ) return <NUM_LIT> ; if ( TUNE_OCTEON ) return <NUM_LIT> ; if ( TUNE_P5600 || TUNE_I6400 )


<s> bool <ISA_LIT>LegalizerInfo :: legalizeBitfieldExtract ( MachineInstr & MI , MachineRegisterInfo & MRI , LegalizerHelper & Helper ) const { return getIConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) && getIConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg


<s> bool ProtectSpillSupportPass :: isRAXLiveAtMI ( MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; if ( TII -> isRegLiveAtMI ( <STR_LIT> , MI , true ) || TII -> isRegLiveAtMI ( <STR_LIT> , MI , true ) || TII -> isRegLiveAtMI ( <STR_LIT> , MI , true ) || TII -> isRegLiveAtMI ( <STR_LIT> ,


<s> unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? ( stackBias + <NUM_LIT> ) : <NUM_LIT> ; while ( depth -- ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset ) ) ; FrameAddr = DAG . getLoad ( VT , dl , Chain , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler ( STI , true


<s> SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op .


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> emitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody (


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getSubtarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - TD -> getPointerSize ( <NUM_LIT>