<s> if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine ) return ; cfun -> machine -> naked_p = riscv_naked_function_p


<s> SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr


<s> void <ISA_LIT>MergeBaseOffsetOpt :: foldOffset ( MachineInstr & HiLUI , MachineInstr & LoADDI , MachineInstr & Tail , int64_t Offset ) { HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; LoADDI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; DeadInstrs . insert ( & Tail ) ; MRI -> replaceRegWith ( Tail . getOperand ( <NUM_LIT> ) . getReg ( )

, LoADDI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> return emitSelectPseudo ( MI , BB , Subtarget ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitQuietFCMP ( MI , BB , <STR_LIT> , <STR_LIT> , Subtarget ) ; case <STR_LIT> : return emitQuietFCMP ( MI , BB , <STR_LIT> , <STR_LIT> , Subtarget ) ; case <STR_LIT> : return emitQuietFCMP ( MI , BB ,


<s> static vlmul_type calculate_vlmul ( unsigned int sew , unsigned int ratio ) { for ( const vlmul_type vlmul : ALL_LMUL ) if ( calculate_ratio ( sew ,


<s> bool isUImm9Lsb000 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm

) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT


<s> static Register getSPReg ( const <ISA_LIT>Subtarget & STI ) { return


<s> static bool riscv_tls_symbol_p ( const_rtx


<s> static bool any_set_in_bb_p ( hash_set < set_info * > sets , const bb_info * bb ) { for ( const set_info * set : sets ) if ( set -> bb ( )

-> index ( ) == bb -> index ( ) ) return true ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; O << MO . getImm ( ) +


<s> int get_ta ( rtx ta ) { if ( INTVAL ( ta ) == TAIL_ANY ) return INVALID_ATTRIBUTE ; return INTVAL (


<s> virtual bool check ( function_checker &


<s> Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L'


<s> errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown


<s> if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return true ; if ( ScalarTy -> isHalfTy ( ) ) return Subtarget . hasStdExtZfh ( ) ; if ( ScalarTy -> isFloatTy ( ) ) return Subtarget . hasStdExtF ( ) ; if ( ScalarTy -> isDoubleTy ( ) ) return Subtarget . hasStdExtD ( ) ; return


<s> static SDValue getRVVFPExtendOrRound ( SDValue Op , MVT VT , MVT ContainerVT , SDLoc DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( VT . isScalableVector ( ) ) return DAG . getFPExtendOrRound ( Op , DL , VT ) ; assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL


<s> Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; break ; } Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; } return


<s> bool <ISA_LIT>PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false


<s> <STR_LIT> FixupKind = <STR_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax ) { if ( FixupKind == <STR_LIT> ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> static DecodeStatus decodeCLUIImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) &&


<s> if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { if ( Addr . getValueType ( ) . isScalarInteger ( ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; return true ; } } return


<s> enum mask_policy get_prefer_mask_policy ( ) { return MASK_ANY


<s> if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return true ; OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg (


<s> if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t Div = <NUM_LIT> ; unsigned Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; if ( ( Val % <NUM_LIT> ) == <NUM_LIT> && isInt < <NUM_LIT>


<s> return DecodeFPR32RegisterClass ( Inst , RegNo ,


<s> static bool riscv_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { return ( ! riscv_v_ext_vector_mode_p ( mode ) && GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ( class1 == FP_REGS )

!= ( class2 == FP_REGS ) && ! TARGET_XTHEADFMV ) ;


<s> static DecodeStatus DecodeVRM2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ; return


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return ( MFI . hasVarSizedObjects ( ) || ( ! hasReservedCallFrame ( MF ) && MFI . getMaxCallFrameSize ( ) != <NUM_LIT>

) ) && TRI -> hasStackRealignment ( MF ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getVecReg ( ) )


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) )


<s> if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && riscv_regno_mode_ok_for_base_p ( REGNO ( x ) , mode ,


<s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps (

VecVT , ContainerVT , DL , DAG , Subtarget ) ;


<s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize == <NUM_LIT> && ! MF . getFrameInfo ( ) . hasTailCall ( ) && ! MF

. getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ;


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { VariantKind Kind = getKind ( ) ; bool HasVariant = ( ( Kind != VK_<ISA_LIT>_None ) && ( Kind != VK_<ISA_LIT>_CALL ) && ( Kind != VK_<ISA_LIT>_CALL_PLT ) && ( Kind != VK_<ISA_LIT>_CCALL ) ) ; if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK_<ISA_LIT>_CALL_PLT ) OS << <STR_LIT> ; if ( HasVariant )


<s> void setSavedGPRFrameSize ( unsigned bytes ) { SavedGPRFrameSize = bytes


{ MO_TLS_GOT_HI , <STR_LIT> } , { MO_TLS_GD_HI , <STR_LIT> } } ;


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { const DataLayout & DL = MF . getDataLayout ( ) ; int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC , DL

) , RegInfo -> getSpillAlignment ( * RC , DL ) , false ) ;


<s> static SDValue combineSelectAndUseCommutative ( SDNode * N , SelectionDAG & DAG , bool AllOnes ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DAG , AllOnes


<s> Entry . Ty = CallTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , CallTy , DAG . getExternalSymbol ( <STR_LIT> , Ty )


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override { return &


<s> void <ISA_LIT>InstPrinter :: printBDXAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum +


<s> SDValue BasePtr = MemSD -> getBasePtr ( ) ; bool IsTruncatingStore = false ; SDValue Index , Mask , Val , VL ; if ( auto * VPSN = dyn_cast < VPScatterSDNode > ( Op . getNode ( ) ) ) { Index = VPSN -> getIndex ( ) ; Mask = VPSN -> getMask ( ) ; Val = VPSN -> getValue ( ) ; VL = VPSN -> getVectorLength ( ) ; IsTruncatingStore = false ; } else { auto * MSN = cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ; Index = MSN -> getIndex ( ) ; Mask = MSN -> getMask ( ) ; Val = MSN -> getValue ( ) ; IsTruncatingStore = MSN -> isTruncatingStore ( ) ; } MVT VT = Val . getSimpleValueType ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! IsTruncatingStore && <STR_LIT> ) ; ( void ) IsTruncatingStore


<s> if ( required_extensions_p ( op_info -> ret . base_type ) ) { enum vector_type_index ret_type_idx = op_info -> ret . get_function_type_index ( type_info . index ) ; if ( ret_type_idx == NUM_VECTOR_TYPES ) return false ; required_extensions |= get_required_extensions ( ret_type_idx ) ; } for ( unsigned i = <NUM_LIT> ; op_info -> args [ i ] . base_type != NUM_BASE_TYPES ; ++ i ) { if ( ! required_extensions_p ( op_info -> args [ i ] . base_type ) ) continue ; enum vector_type_index vector_type = op_info -> args [ i ] . get_function_type_index ( type_info . index ) ; if ( vector_type == NUM_VECTOR_TYPES ) return false ; required_extensions |= get_required_extensions ( vector_type ) ; if ( op_info -> args [ i ] . base_type == RVV_BASE_eew64_index ) required_extensions |= RVV_REQUIRE_RV64BIT ; } uint64_t riscv_isa_flags = <NUM_LIT> ; if ( TARGET_VECTOR_ELEN_FP_32 ) riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32 ; if ( TARGET_VECTOR_ELEN_FP_64 ) riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_64 ; if ( TARGET_VECTOR_ELEN_64 ) riscv_isa_flags |= RVV_REQUIRE_ELEN_64 ; if ( TARGET_64BIT ) riscv_isa_flags |=


<s> MVT XLenVT = Subtarget . getXLenVT ( ) ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; SDValue Addr ; switch ( Model ) { case TLSModel :: LocalExec : Addr = getStaticTLSAddr ( N , DAG , false ) ; break ; case TLSModel :: InitialExec : Addr = getStaticTLSAddr ( N , DAG


<s> bool has_avl_no_reg ( ) const { return m_avl . has_avl_no_reg (


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) / <NUM_LIT> ; const MCExpr * Expr = MO . getExpr ( ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset ,


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; assert ( IsConstant && <STR_LIT>


<s> else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT>


<s> builder . quick_push ( const1_rtx ) ; builder . quick_push (


<s> return TARGET_MIN_VLEN * <NUM_LIT> ; case LMUL_4 : return TARGET_MIN_VLEN * <NUM_LIT> ; case LMUL_8 : return TARGET_MIN_VLEN * <NUM_LIT> ; default : gcc_unreachable ( )


<s> bool riscv_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out ) { enum riscv_symbol_type symbol_type ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! riscv_symbolic_constant_p ( addr , & symbol_type ) || riscv_symbol_insns ( symbol_type ) == <NUM_LIT> || ! riscv_split_symbol_type ( symbol_type ) ) return false ; if ( low_out ) switch ( symbol_type ) { case SYMBOL_ABSOLUTE : { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr )


<s> bool <ISA_LIT>TargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType


<s> default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent : return


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> switch ( Lmul ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; return true


<s> if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno ==


<s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase


<s> if ( riscv_v_ext_vector_mode_p ( mode ) ) return riscv_vector_chunks * scale ; return scale


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIPU ( SDValue Dest , SDValue & SRC1 , SDValue & SRC2 ) { return RI5CY_pclip_check ( CurDAG , Dest ,


<s> return Opcode == <STR_LIT> || ( ! STI . is64Bit ( ) && Opcode

== <STR_LIT> ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ; return


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr


<s> std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; unsigned Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment


<s> return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_CALL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_LO , <STR_LIT> } , { MO_HI , <STR_LIT> } , { MO_PCREL_LO , <STR_LIT> } , { MO_PCREL_HI , <STR_LIT> } , { MO_GOT_HI , <STR_LIT> } , { MO_TPREL_LO , <STR_LIT> } , { MO_TPREL_HI , <STR_LIT> } , { MO_TPREL_ADD , <STR_LIT> } , { MO_TLS_GOT_HI

, <STR_LIT> } , { MO_TLS_GD_HI , <STR_LIT> } } ;


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) ,


<s> return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType (


<s> switch ( Op . getOpcode ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op ,


<s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } unsigned Reg = FPR64DecoderTable [


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DAG , AllOnes ) ) return Result ; if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DAG ,


<s> } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { return MatchOperand_ParseFail ; } const MCExpr * ModExpr = <ISA_LIT>MCExpr :: create ( SubExpr , VK , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( ModExpr , S , E


<s> int64_t PrevVTYPEImm = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( PrevAVLReg != AVLReg || PrevVTYPEImm != VTYPEImm ) { PrevVSETVLI = & MI ; continue ; } if ( AVLReg == <STR_LIT> ) { Register PrevOutVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OutVL = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PrevOutVL == <STR_LIT> && OutVL != <STR_LIT> ) { PrevVSETVLI = & MI ; continue ; } } MI . eraseFromParent


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU ,

FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) {


<s> unsigned getBranchTargetEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO .


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp


<s> bool isBareSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm


<s> unsigned getMaxInterleaveFactor ( unsigned


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT>


<s> MachineInstr & Tail = * MRI -> use_begin ( DestReg ) -> getParent ( ) ; switch ( Tail . getOpcode ( ) ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; return false ; case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void setAVLReg ( Register Reg ) { AVLReg = Reg


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned PseudoOpcode ; if ( <STR_LIT> ( ST . getTargetABI ( ) ) ) PseudoOpcode = <STR_LIT> ; else PseudoOpcode = <STR_LIT> ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( PseudoOpcode ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT>


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Commute ) std :: swap ( Op0 , Op1 ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) && Op1 . hasOneUse ( ) && Op1 . getOperand ( <NUM_LIT> ) == Mask && Op1 . getOperand ( <NUM_LIT> ) == VL ) { unsigned ExtOpc = Op1 . getOpcode ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ; unsigned WOpc ; if ( ExtOpc == <STR_LIT> ) WOpc = IsAdd


<s> bool isU32Imm ( ) const { return isImm ( <NUM_LIT> , ( <NUM_LIT> <<


<s> bool <ISA_LIT>ExpandPseudo :: expandVSetVL ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { assert ( MBBI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & Desc = TII -> get ( <STR_LIT>


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo (


<s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MFI . hasVarSizedObjects ( ) && TRI -> needsStackRealignment (


<s> bool riscv_new_address_profitable_p ( rtx memref , rtx_insn * insn , rtx new_addr ) { addr_space_t as = MEM_ADDR_SPACE ( memref ) ; bool speed = optimize_bb_for_speed_p ( BLOCK_FOR_INSN ( insn ) ) ; int old_cost = address_cost ( XEXP ( memref , <NUM_LIT> ) , GET_MODE ( memref ) , as , speed ) ; int new_cost = address_cost ( new_addr , GET_MODE ( memref ) , as , speed ) ; return new_cost


<s> int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign


<s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( )


<s> unsigned int sew = get_sew ( vmode ) ; emit_insn ( gen_vsetvl ( Pmode , vl , RVV_VLMAX , gen_int_mode ( sew , Pmode ) , gen_int_mode ( get_vlmul

( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; if ( CallConv == CallingConv :: GHC && ! RVLocs . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( )


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK ==


<s> riscv_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } if ( MEM_P ( dest ) && ! riscv_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , reload_completed ) ) { XEXP ( dest , <NUM_LIT> ) = riscv_force_address ( XEXP ( dest , <NUM_LIT> ) , mode ) ; } if ( MEM_P ( src ) && ! riscv_legitimate_address_p ( mode , XEXP ( src , <NUM_LIT> )


<s> static unsigned calculate_sew ( vlmul_type vlmul , unsigned


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target

, MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const {


<s> if ( PrevElt ) { int64_t Diff = SignExtend64 ( Val - PrevElt -> first , EltSizeInBits ) ; if ( Diff % ( Idx - PrevElt -> second ) != <NUM_LIT> ) return None ; int64_t Step = Diff / ( Idx - PrevElt -> second ) ; if ( Step == <NUM_LIT> ) return None ; if ( ! SeqStep ) SeqStep = Step ; else if ( Step != SeqStep ) return None ; } if ( SeqStep ) { int64_t Addend = SignExtend64 ( Val - ( Idx * ( uint64_t ) * SeqStep ) , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( SeqAddend != Addend ) return None ; } PrevElt = std :: make_pair ( Val


<s> return VF == <NUM_LIT> ? <NUM_LIT> : ST -> getMaxInterleaveFactor (


<s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : if ( getParser ( ) . parseExpression ( Res ) )


<s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; auto ABIName = StringRef ( Options . ABIName ) ; if ( ABIName . endswith ( <STR_LIT> ) && ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT>


<s> StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case KindTy :: Register : Reg = o . Reg ; break ; case KindTy :: Immediate : Imm = o . Imm ; break ; case KindTy :: Token : Tok = o . Tok ; break ; case KindTy :: SystemRegister : SysReg = o . SysReg ; break ; case KindTy :: VectorRegister : VReg = o .


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl )


<s> std :: stringstream mode ; int mlen ; if ( lmul_log2 >= <NUM_LIT> ) mlen = sew / ( <NUM_LIT> << lmul_log2 ) ; else mlen = sew * ( <NUM_LIT> << - lmul_log2 ) ; mode << <STR_LIT> << mlen << <STR_LIT> ; return mode .


<s> SDValue V = OpIdx . value ( ) ; if ( ( unsigned ) OpIdx . index ( ) == EVLIdx ) { Ops . push_back ( DAG . getZExtOrTrunc ( V , DL , XLenVT ) ) ; continue ; } assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isFixedLengthVector ( ) ) { Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT


<s> SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Gather = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Vec , Idx , Mask , VL ) ; if ( ! VT . isFixedLengthVector ( ) ) return Gather ; return convertFromScalableVector ( VT , Gather ,


<s> if ( ! VT . isScalableVector ( ) ) return false ; EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return true ; } return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) { initAsmInfo ( )


<s> MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( HiReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; TII . loadRegFromStackSlot ( * BB , MI , DstReg , FI ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired <


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( Subtarget . isRV64 ( ) ) return <STR_LIT> ; else return <STR_LIT>


<s> case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & ,


<s> auto mode_sz = GET_MODE_SIZE ( mode ) ; if ( ! known_eq ( mem_sz , mode_sz ) ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; unsigned shamt = ( mem_mode == DImode ) ? <NUM_LIT> : <NUM_LIT> ; rtx base ; HOST_WIDE_INT offset ; split_plus ( XEXP ( mem , <NUM_LIT> ) , & base , & offset ) ; HOST_WIDE_INT imm2 = offset


<s> unsigned int calculate_ratio ( unsigned int sew , enum vlmul_type vlmul ) { unsigned int ratio ; switch ( vlmul ) { case LMUL_1 : ratio = sew ; break ; case LMUL_2 : ratio = sew / <NUM_LIT> ; break ; case LMUL_4


<s> BB -> addSuccessor ( LoopMBB ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned ReadAgainReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , HiReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , LoReg ) . addImm ( <STR_LIT> ( <STR_LIT> )


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; auto SpecialCapReg = <STR_LIT> ( Imm ) ; if ( SpecialCapReg ) O << SpecialCapReg -> Name ; else O


<s> bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = std :: string ( CPU ) ; std :: string TuneCPUName = std :: string ( TuneCPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT>


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK


<s> VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( C && C -> isAllOnesValue ( ) ) { VL = CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( isa < RegisterSDNode > ( N ) && cast < RegisterSDNode > ( N ) -> getReg ( ) == <STR_LIT> ) { VL = CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else { VL = N ; } return


<s> return :: getContainerForFixedLengthVector ( * this , VT , getSubtarget (


<s> assert ( <STR_LIT> == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return <STR_LIT> == MI . getOperand ( <NUM_LIT> )


<s> if ( SrcVT . isInteger ( ) ) { assert ( DstVT . isFloatingPoint ( ) && <STR_LIT> ) ; MVT InterimFVT = DstVT ; if ( SrcEltSize > ( <NUM_LIT> * DstEltSize ) ) { assert ( SrcEltSize == ( <NUM_LIT> * DstEltSize ) && <STR_LIT> ) ; assert ( DstVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; InterimFVT = <STR_LIT> ( <STR_LIT> , DstVT . getVectorElementCount ( ) ) ; } Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , InterimFVT , Src , Mask , VL ) ; if ( InterimFVT != DstVT ) { Src = Result ; Result = DAG . getNode ( <STR_LIT> , DL , DstVT , Src , Mask , VL ) ; } } else { assert ( SrcVT . isFloatingPoint ( ) && DstVT . isInteger ( ) && <STR_LIT> ) ; if ( DstEltSize == <NUM_LIT> ) { assert ( SrcEltSize >= <NUM_LIT> && <STR_LIT> ) ; MVT InterimIVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize ) , DstVT . getVectorElementCount ( ) ) ; Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , InterimIVT , Src , Mask , VL ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , InterimIVT , DAG . getUNDEF ( InterimIVT ) , SplatZero ) ; Result = DAG . getNode ( <STR_LIT> , DL , DstVT , Result , SplatZero , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; } else { MVT InterimIVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize / <NUM_LIT> ) , DstVT . getVectorElementCount ( ) ) ; Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , InterimIVT , Src , Mask , VL ) ; while ( InterimIVT != DstVT ) { SrcEltSize /= <NUM_LIT> ; Src = Result ; InterimIVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize / <NUM_LIT> ) , DstVT . getVectorElementCount ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , InterimIVT , Src , Mask , VL ) ; } } } } MVT VT = Op . getSimpleValueType ( ) ; if ( ! VT . isFixedLengthVector ( ) ) return Result ; return convertFromScalableVector ( VT , Result , DAG


<s> static void riscv_block_move_loop ( rtx dest , rtx src , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT bytes_per_iter ) { rtx label , src_reg , dest_reg , final_src , test ; unsigned HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; riscv_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; riscv_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , <NUM_LIT> , <NUM_LIT> ,


<s> Index = VPGN -> getIndex ( ) ; Mask = VPGN -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPGN -> getVectorLength ( ) ; LoadExtType = <STR_LIT> ; } else { auto * MGN = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; Index = MGN -> getIndex ( ) ; Mask = MGN -> getMask ( ) ; PassThru = MGN -> getPassThru ( ) ; LoadExtType = MGN -> getExtensionType ( ) ; } MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( LoadExtType == <STR_LIT> && <STR_LIT> ) ; ( void ) LoadExtType ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ; Mask = convertToScalableVector ( MaskVT ,


<s> const MCSubtargetInfo * STI = AF . getSubtargetInfo ( ) ; if ( ! STI -> getFeatureBits ( ) [ <STR_LIT> ] ) return false ; unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == <NUM_LIT> ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT> ; MCValue NopBytes = MCValue :: get ( Count ) ; Asm . getWriter ( ) . recordRelocation ( Asm , Layout

, & AF , Fixup , NopBytes , FixedValue ) ;


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedInt < N - <NUM_LIT> , <NUM_LIT>


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO

) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ObjectWriter ( raw_pwrite_stream & OS


<s> auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - FirstSPAdjustAmount ) ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } } } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg (


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize


<s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( )


<s> MVT getXLenVT ( ) const { return XLenVT


<s> static std :: unique_ptr < <ISA_LIT>Operand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: SystemRegister ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ; Op -> StartLoc = S ; Op -> IsRV64


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm ,


<s> if ( hasAVLReg ( ) && Other . hasAVLReg ( ) ) return getAVLReg ( ) == Other . getAVLReg ( ) ; if ( hasAVLImm ( ) && Other . hasAVLImm ( ) ) return getAVLImm ( ) == Other . getAVLImm ( ) ; return


<s> I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue Lo = N -> getOperand ( <NUM_LIT> ) ; SDValue Hi = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout ( ) , CurDAG -> getDataLayout ( )


<s> static SmallVector < CalleeSavedInfo , <NUM_LIT> > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , <NUM_LIT> > NonLibcallCSI ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= <NUM_LIT> ) NonLibcallCSI . push_back ( CS ) ; return


<s> auto & RAB = static_cast < <ISA_LIT>AsmBackend & > ( Layout -> getAssembler ( ) . getBackend ( ) ) ; if ( RAB . willForceRelocations ( ) ) return false ; MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsValue ( AUIPCLoc , * Layout ) ) return false ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE || findAssociatedFragment ( ) != AUIPCSRE -> findAssociatedFragment ( ) ) return false ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; if ( ! AUIPCSymbol ) return false ; const MCFixup * TargetFixup = getPCRelHiFixup ( ) ; if ( ! TargetFixup ) return false ; if ( ( unsigned ) TargetFixup -> getKind ( ) != <STR_LIT> ) return false ; MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( )

+ ( Fixup -> getOffset ( ) - AUIPCOffset ) ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionNoRelax (


<s> if ( riscv_compressed_reg_p ( regno ) )


<s> slot_address = riscv_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset . to_constant ( ) ) ; riscv_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case (

<STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> auto_vec < size_t > available_list ; for ( size_t i = <NUM_LIT> ; i < vector_exprs . length ( ) ; i ++ ) if ( info .

available_p ( * vector_exprs [ i ] ) ) available_list . safe_push ( i ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool


<s> inline static unsigned encodeSEW ( unsigned SEW ) { assert ( isValidSEW ( SEW ) && <STR_LIT>


<s> auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) { RTS . emitDirectiveOptionPop ( ) ; } AsmPrinter :: emitBasicBlockEnd ( MBB


<s> switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return


<s> if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return


<s> SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx


<s> IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = true ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * CallExpr = Func . getExpr


<s> static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT


<s> break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; case <NUM_LIT> : vtypei |= <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( vtypei ) ; return BB ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( )


<s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness ( )


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUIntN ( N , Imm ) && VK


<s> bool HasPassthru = Passthru && ! Passthru . isUndef ( ) ; if ( ! HasPassthru && ! Passthru ) Passthru = DAG . getUNDEF ( VT ) ; if ( VT . isFloatingPoint ( ) ) { if ( isOneConstant ( VL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Scalar , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Scalar , VL ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Scalar . getValueType ( ) . bitsLE (


<s> if ( reg_class_subset_p ( GR_REGS , rclass ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ; return


<s> TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; Val &= maskTrailingZeros < uint64_t > ( ShiftAmount ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( Val , IsRV64 , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } return


<s> static bool isValidOffset ( <STR_LIT> OffR , int64_t Val ) { assert ( selectOffset ( OffR , Val )


<s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; if ( ! lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , *

this ) ) EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , T


<s> bool speed = optimize_bb_for_speed_p ( BLOCK_FOR_INSN ( insn ) ) ; int old_cost = address_cost ( XEXP ( memref , <NUM_LIT> ) , GET_MODE ( memref ) ,


<s> poly_uint64 riscv_regmode_natural_size ( machine_mode mode ) { if ( ! riscv_vector_chunks . is_constant ( ) && riscv_v_ext_vector_mode_p ( mode ) ) return BYTES_PER_RISCV_VECTOR ; return


<s> static void riscv_emit_epilogue_components ( sbitmap components


<s> return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering ::


<s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( )


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target (


<s> static bool isConstantMask ( SDNode * Node , uint64_t & Mask ) { if ( Node -> getOpcode ( ) == <STR_LIT> && Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Mask = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; return true ; } return false


<s> bool vl_vtype_info :: same_vtype_p ( const vl_vtype_info & other ) const { return get_sew ( ) == other . get_sew ( ) && get_vlmul ( ) == other . get_vlmul ( ) && get_ta (

) == other . get_ta ( ) && get_ma ( ) == other . get_ma ( ) ;


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch (


<s> assert ( CapSize == ( getContext ( ) . getTargetTriple ( ) . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; emitCheriIntcapGeneric ( Expr , CapSize ,


riscv_builtins ) ) return error_mark_node ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Token ) ; Op -> Tok = Str ; Op -> StartLoc =


<s> Align getRequiredAlignment ( uint64_t Size , bool IsRV64 ) { if ( IsRV64 ) { return Align ( cc128_get_required_alignment ( Size ) ) ; } else


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) CPU = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> auto RegName = [ ] ( unsigned Reg ) { if ( Reg ) return <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; else return <STR_LIT> ; } ; switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case KindTy :: SpecialCapRegister : OS << <STR_LIT> << getSpecialCapReg


<s> MCOperand DestReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand TPReg = MI . getOperand ( <NUM_LIT> ) ; MCOperand SrcReg = MI . getOperand ( <NUM_LIT> ) ; assert ( TPReg . isReg ( ) && TPReg . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MCOperand SrcSymbol = MI . getOperand ( <NUM_LIT> ) ; assert ( SrcSymbol . isExpr ( ) && <STR_LIT> ) ; const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( SrcSymbol . getExpr ( ) ) ; assert ( Expr && Expr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_CINCOFFSET && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ]


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT>


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities ,

MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg (


<s> bool <ISA_LIT>AsmParser :: validateInstruction ( MCInst & Inst , OperandVector & Operands ) { const MCInstrDesc & MCID = MII . get ( Inst . getOpcode ( ) ) ; unsigned TargetFlags = ( MCID . TSFlags >> <STR_LIT> ) & <STR_LIT> ; if ( TargetFlags == <STR_LIT> ) return false ; unsigned DestReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; SMLoc Loc = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; if ( ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) ) { if ( TargetFlags != <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned Src1Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getNumOperands


<s> void addSImm5Plus1Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; assert ( IsConstant && <STR_LIT> ) ; ( void ) IsConstant ; Inst . addOperand ( MCOperand :: createImm ( Imm - <NUM_LIT>


<s> if ( C && C -> isNullValue ( ) ) VL = SDValue ( selectImm ( CurDAG , SDLoc ( N ) , <NUM_LIT> , Subtarget -> getXLenVT ( ) ) , <NUM_LIT> ) ; else VL = N ; return true


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return


<s> static rtx riscv_force_binary ( enum machine_mode mode , enum rtx_code code , rtx x ,


<s> inline static unsigned decodeVSEW ( unsigned VSEW ) { assert ( VSEW < <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> << (


<s> if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII


<s> static DecodeStatus DecodeVGRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr ::


<s> bool isRV32 ( ) const { return <ISA_LIT>ArchVersion


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : const MCFixup * T = cast < <ISA_LIT>MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT>


<s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ; return Res . getSymB ( ) ? getKind (


<s> memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; offset = crtl -> outgoing_args_size ; offset += RISCV_STACK_ALIGN ( get_frame_size ( ) ) ; frame -> frame_pointer_offset = offset ; if ( frame -> fmask ) offset += RISCV_STACK_ALIGN ( num_f_saved * UNITS_PER_FP_REG ) ; frame -> fp_sp_offset = offset - UNITS_PER_FP_REG ; if ( frame -> mask ) { unsigned x_save_size = RISCV_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + riscv_save_libcall_count ( frame -> mask ) ; if ( RISCV_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) frame -> save_libcall_adjustment = x_save_size ; offset += x_save_size ; } frame -> gp_sp_offset = offset - UNITS_PER_WORD ; frame -> hard_frame_pointer_offset = offset ; offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; frame -> arg_pointer_offset = offset ; offset += crtl -> args


<s> int n = <NUM_LIT> ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) { return <NUM_LIT> ; } if ( ! riscv_v_ext_vector_mode_p ( mode ) && mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> bool isCCallSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr


<s> bool <ISA_LIT>InsertVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasVInstructions ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; if ( HaveVectorOp ) { for ( const MachineBasicBlock & MBB : MF ) { WorkList . push ( & MBB


<s> return MCDisassembler :: Fail ; } return DecodeGPRRegisterClass ( Inst , RegNo , Address


<s> bool hasCompatibleVTYPE ( const VSETVLIInfo & Require ) const { if ( hasSameVTYPE ( Require ) ) return true ; if ( Require . MaskRegOp && hasSameVLMAX ( Require ) && TailAgnostic ==

Require . TailAgnostic && MaskAgnostic == Require . MaskAgnostic ) return true ;


<s> } } else { return false ; } auto setcc_inner = Dest . getOperand ( select ) . getOperand ( <NUM_LIT> ) ; auto reg_xxx = & Dest . getOperand ( select ) . getOperand ( <NUM_LIT> ) ; const SDValue * reg_out ; int inner_pos_constant_low_cc ; if ( setcc_inner . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { inner_pos_constant_low_cc = <NUM_LIT> ; reg_out = & setcc_inner . getOperand ( <NUM_LIT> ) ; } else if ( setcc_outer . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { reg_out = & setcc_inner . getOperand ( <NUM_LIT> ) ; inner_pos_constant_low_cc = <NUM_LIT> ; } else { return false ; } MemSDNode * mem_in = cast < MemSDNode > ( * reg_in ) ; MemSDNode * mem_out = cast < MemSDNode > ( * reg_out ) ; MemSDNode * mem_xxx = cast < MemSDNode > ( * reg_xxx ) ; if ( * ( mem_in -> getMemOperand ( ) ) != * ( mem_out -> getMemOperand ( ) ) || * ( mem_in -> getMemOperand ( ) ) != * ( mem_xxx -> getMemOperand ( ) ) ) { return false ; } int32_t inner_low_constant_cc = setcc_inner . getConstantOperandVal ( inner_pos_constant_low_cc ) ; if ( setcc_inner . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < CondCodeSDNode > ( * setcc_inner . getOperand ( <NUM_LIT> ) . getNode ( ) ) . get ( ) == <STR_LIT> ) { if ( ! unsign && inner_low_constant_cc != - low_constant_cc ) { return false ; } } else


<s> } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , StackSize , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode


<s> initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry


<s> MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } if ( isScalarMoveInstr ( MI ) && ( ( CurInfo . hasNonZeroAVL ( ) && NewInfo . hasNonZeroAVL ( ) ) || ( CurInfo . hasZeroAVL ( ) && NewInfo . hasZeroAVL ( ) ) ) && NewInfo . hasSameVLMAX ( CurInfo ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ; NeedInsertVSETVLI = false ; } } if ( NeedInsertVSETVLI ) insertVSETVLI ( MBB , MI , NewInfo , CurInfo ) ; CurInfo = NewInfo ; } } PrevVSETVLIMI = nullptr ; } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister (


<s> static void riscv_unique_section ( tree decl , int reloc ) { const char * prefix = NULL ; bool one_only = DECL_ONE_ONLY ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SRODATA : prefix = one_only ? <STR_LIT>


<s> split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) )


<s> return CurDAG -> getTargetConstant ( Imm


<s> return Kind == KindTy :: Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg .


<s> bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; if ( Res )


<s> bool <ISA_LIT>ExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; } return


<s> case <STR_LIT> : case <STR_LIT> : if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; else if ( VecVT == <STR_LIT> ) return <STR_LIT> ; break ; case <STR_LIT>


<s> return Kind == k_VectorList && VectorList . Count == NumRegs && ! VectorList


<s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; SDValue BN1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , BN1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT>


<s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) const { return isLegalMaskedGatherScatter (


<s> return MFI -> getUseLocalStackAllocationBlock ( ) && MFI


<s> return ( vector unsigned int ) __builtin_altivec_vmsumubm ( ( vector signed char ) a1 , ( vector signed char ) a2 , ( vector signed int


<s> gcc_assert ( MEM_P ( mem ) ) ; if ( GET_CODE ( XEXP ( mem , <NUM_LIT> )


<s> if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return ! I -> getDesc ( ) .


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment =


<s> if ( isNullFPScalarOrVectorConst ( N -> getOperand ( <NUM_LIT> ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( isNullFPScalarOrVectorConst ( N -> getOperand ( <NUM_LIT> ) ) ) return N ->


<s> SDLoc dl ( N ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LD -> getChain ( ) , LD -> getBasePtr ( ) } , MemVT , LD -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result . getValue (

<NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { return false


<s> dest = operands [ <NUM_LIT> ] ; vec = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; if ( TARGET_VSX ) { if ( zero_constant ( vec , mode ) ) return <STR_LIT> ; if ( TARGET_P8_VECTOR && vec == CONSTM1_RTX ( mode ) ) return <STR_LIT> ; if ( ( mode == V2DImode || mode == V1TImode ) && INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) == - <NUM_LIT> ) return ( TARGET_P8_VECTOR ) ? <STR_LIT> : <STR_LIT> ; } if ( TARGET_ALTIVEC ) { rtx splat_vec ; if ( zero_constant ( vec , mode ) ) return <STR_LIT> ; shift = vspltis_shifted ( vec ) ; if ( shift != <NUM_LIT> ) return <STR_LIT> ; splat_vec = gen_easy_altivec_constant ( vec ) ; gcc_assert ( GET_CODE ( splat_vec ) == VEC_DUPLICATE


<s> MVT <ISA_LIT>TargetLowering :: getSetCCResultType ( MVT VT ) const { return


<s> if ( DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) <= <NUM_LIT> ) return false ; if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type )

> ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) {


<s> OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; unsigned UsedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { if ( Op -> isImm ( ) ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) . addImm ( Op -> getImm ( ) ) ) ; else if ( Op -> isReg ( ) ) { if ( Op -> getReg ( ) != UsedRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) . addReg ( Op -> getReg ( ) ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } } auto TSym = OutContext . getOrCreateSymbol (


<s> ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) .

addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ;


<s> for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O << 't' ; else O <<


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5 ( SDValue N , SDValue & Base , SDValue & Offset ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TheTriple , const MCTargetOptions & Options ) { bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple .


<s> } if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , Acc , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } else if ( N -> getOpcode ( ) == <STR_LIT> && SearchSignedMulLong ( SDValue ( N , <NUM_LIT> ) , & Opc , A , B , false ) ) { if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT>


<s> bool Changed = false ; for ( auto & MBB : * MF ) { SmallVector < MachineInstr * , <NUM_LIT> > Starts ; SmallVector < MachineInstr * , <NUM_LIT> > Decs ; SmallVector < MachineInstr * , <NUM_LIT> > Ends ; SmallVector < MachineInstr * , <NUM_LIT> > EndDecs ; for ( auto & I : MBB ) { if ( isLoopStart ( I ) ) Starts . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Decs . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) Ends . push_back ( & I ) ; else if ( I . getOpcode ( ) == <STR_LIT> ) EndDecs . push_back ( & I ) ; } if ( Starts . empty ( ) && Decs . empty ( ) && Ends . empty ( )


<s> return ( __m128i ) __builtin_ia32_pmovusqd128_mask ( ( __v2di ) __A , ( __v4si ) _mm_undefined_si128 ( ) ,


<s> UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = (


<s> GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Val ) ; if ( ! GA ) return false ; const GlobalVariable * GV = dyn_cast_or_null < GlobalVariable > ( GA -> getGlobal ( ) ) ; if ( ! GV ) return false ; if ( ! GV -> hasAttribute ( <STR_LIT> ) ) return false ; assert ( PointerSize >= GV -> getAlign ( ) . valueOrOne ( ) . value


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isThumb1Only ( )


<s> unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } } return DecodeVMOVModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - imm ) ) ; return


<s> t2 = build1 ( GOTO_EXPR , void_type_node , lab_false ) ; t = build3 ( COND_EXPR , void_type_node , t , t2 , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; } if ( needed_intregs ) { t = fold_build_pointer_plus ( sav , gpr ) ; gimplify_assign ( int_addr , t , pre_p ) ; } if ( needed_sseregs ) { t = fold_build_pointer_plus ( sav , fpr ) ; gimplify_assign ( sse_addr , t , pre_p ) ; } if ( need_temp ) { int i , prev_size = <NUM_LIT> ; tree temp = create_tmp_var ( type , <STR_LIT> ) ; TREE_ADDRESSABLE ( temp ) = <NUM_LIT> ; t = build1 ( ADDR_EXPR , build_pointer_type ( type ) , temp ) ; gimplify_assign ( addr , t , pre_p ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( container , <NUM_LIT> ) ; i ++ ) { rtx slot = XVECEXP ( container , <NUM_LIT> , i ) ; rtx reg = XEXP ( slot , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( reg ) ; tree piece_type ; tree addr_type ; tree daddr_type ; tree src_addr , src ; int src_offset ; tree dest_addr , dest ; int cur_size = GET_MODE_SIZE ( mode ) ; gcc_assert ( prev_size <= INTVAL ( XEXP ( slot , <NUM_LIT> ) ) ) ; prev_size = INTVAL ( XEXP ( slot , <NUM_LIT> ) ) ; if ( prev_size + cur_size > size ) { cur_size = size - prev_size ; unsigned int nbits = cur_size * BITS_PER_UNIT ; if ( ! int_mode_for_size ( nbits , <NUM_LIT> ) . exists ( & mode ) ) mode = QImode ; } piece_type = lang_hooks . types . type_for_mode ( mode , <NUM_LIT> ) ; if ( mode == GET_MODE ( reg ) ) addr_type = build_pointer_type ( piece_type ) ; else addr_type = build_pointer_type_for_mode ( piece_type , ptr_mode , true ) ; daddr_type = build_pointer_type_for_mode ( piece_type , ptr_mode , true ) ; if ( SSE_REGNO_P ( REGNO ( reg ) ) ) { src_addr = sse_addr ; src_offset = ( REGNO ( reg ) - FIRST_SSE_REG ) * <NUM_LIT> ; } else { src_addr = int_addr ; src_offset = REGNO ( reg ) * <NUM_LIT> ; } src_addr = fold_convert ( addr_type , src_addr ) ; src_addr = fold_build_pointer_plus_hwi ( src_addr , src_offset ) ; dest_addr = fold_convert ( daddr_type , addr ) ; dest_addr = fold_build_pointer_plus_hwi ( dest_addr , prev_size ) ; if ( cur_size == GET_MODE_SIZE ( mode ) ) { src = build_va_arg_indirect_ref ( src_addr ) ; dest = build_va_arg_indirect_ref ( dest_addr ) ; gimplify_assign ( dest , src , pre_p ) ; } else { tree copy = build_call_expr ( builtin_decl_implicit ( BUILT_IN_MEMCPY ) , <NUM_LIT> , dest_addr , src_addr , size_int ( cur_size ) ) ; gimplify_and_add ( copy , pre_p ) ; } prev_size += cur_size ; } } if ( needed_intregs ) { t = build2 ( PLUS_EXPR , TREE_TYPE ( gpr ) , gpr , build_int_cst ( TREE_TYPE

( gpr ) , needed_intregs * <NUM_LIT> ) ) ;


<s> assert ( MBB . getParent ( ) && <STR_LIT> ) ; const MachineFunction & MF = * MBB . getParent (


<s> ForCodeSize = MF . getFunction ( ) ->


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForNode ( unsigned CC , bool Return , bool isVarArg ) const { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M ) ; return :: isPSHUFLWMask ( M , N -> getValueType ( <NUM_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDValue P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp ) { if ( <STR_LIT> ( N . getNode ( ) ) && N . hasOneUse ( ) && IsLegalAndProfitableToFold ( N . getNode ( ) , P . getNode ( ) , P . getNode ( ) ) ) return SelectAddr ( P , N . getOperand ( <NUM_LIT> ) , Base , Scale , Index , Disp ) ; return false


<s> static bool usePackedStack ( MachineFunction & MF ) { bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; bool CallConv = MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: GHC ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool FramAddressTaken = MF . getFrameInfo ( ) . isFrameAddressTaken ( ) ; if ( HasPackedStackAttr && BackChain )


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> ,


<s> pinsrh_1_u ( uint16x4_t s , uint16x4_t t ) { return __builtin_loongson_pinsrh_1_u ( s


<s> case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; std :: vector < EVT > ResTys ; bool is64BitVector = VT . is64BitVector ( ) ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back (


<s> Position . Address += Terminator . Size ; if ( AssumeRelaxed ) Position . Address += Terminator .