<s> } else if ( <STR_LIT> . contains ( Reg ) && Reg != <STR_LIT> ) { HiRegsToSave . insert ( Reg ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) && ! MF . getRegInfo ( ) . isLiveIn ( Reg ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs . insert ( Reg ) ; } for ( unsigned ArgReg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( ! MF . getRegInfo ( ) . isLiveIn ( ArgReg ) ) CopyRegs . insert ( ArgReg ) ; if ( ! LoRegsToSave . empty ( ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( LoRegsToSave . count ( Reg ) ) { bool isKill = ! MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( PushMIB ) ; SmallVector < unsigned , <NUM_LIT> > RegsToPush ; while ( HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { if ( HiRegsToSave . count ( * HiRegToSave ) ) { bool isKill = ! MF . getRegInfo (


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) .

addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ) ;


<s> GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } Register DstReg = VA .


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > &


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op ,


<s> else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } if ( builtin_sha1h_p ) op1 = GEN_INT ( TARGET_BIG_END ? <NUM_LIT> : <NUM_LIT> ) ; if ( builtin_sha1h_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) (


<s> static inline unsigned char getAM3Offset


<s> void EmitARM64WinCFIMachineFrame ( ) override { OS <<


<s> case MachineOperand :: MO_Register : case MachineOperand :: MO_Immediate : case MachineOperand :: MO_CImmediate : case MachineOperand :: MO_FPImmediate : return false ; case MachineOperand :: MO_MachineBasicBlock : return true ; case MachineOperand :: MO_FrameIndex : return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; const MCExpr * Expr = getMemOffset


<s> int align_log = floor_log2 ( GET_MODE_SIZE ( c -> mode ) ) ; insn = emit_insn_after ( gen_align ( GEN_INT ( align_log ) ) , insn ) ; } align = GET_MODE_SIZE ( c -> mode ) ; insn = emit_label_after ( c -> label , insn ) ; insn = mips16_emit_constants_1 ( c -> mode , c -> value , insn ) ; next = c -> next ; free ( c ) ; } emit_barrier_after (


<s> emit_insn ( gen_rtx_SET ( mask , gen_rtx_ASHIFT ( SImode , mask , off ) ) ) ; emit_insn ( gen_rtx_SET ( val , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , val ) ) ) ; oldval = gen_lowpart ( SImode , oldval ) ; emit_insn ( gen_rtx_SET ( oldv , gen_rtx_ASHIFT ( SImode , oldval , off ) ) ) ; newval = gen_lowpart_common ( SImode , newval ) ; emit_insn ( gen_rtx_SET ( newv , gen_rtx_ASHIFT ( SImode , newval , off ) ) ) ; emit_insn ( gen_rtx_SET ( oldv , gen_rtx_AND ( SImode , oldv , mask ) ) ) ; emit_insn ( gen_rtx_SET ( newv , gen_rtx_AND ( SImode , newv , mask ) ) ) ; rtx_code_label * end_label = gen_label_rtx ( ) ; rtx_code_label * loop_label = gen_label_rtx ( ) ; emit_label ( loop_label ) ; emit_insn ( gen_rtx_SET ( oldvalue , gen_rtx_IOR ( SImode , oldv , val ) ) ) ; emit_insn ( gen_rtx_SET ( newvalue , gen_rtx_IOR ( SImode , newv , val ) ) ) ; emit_move_insn ( bool_result , const1_rtx ) ; emit_insn ( gen_atomic_compare_and_swapsi_1 ( res , memsi , oldvalue , newvalue ) ) ; emit_cmp_and_jump_insns ( res , oldvalue , EQ , NULL , SImode , <NUM_LIT> , end_label ) ; emit_insn ( gen_rtx_SET ( resv , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , res ) ) ) ; emit_move_insn ( bool_result , const0_rtx ) ; cc = gen_compare_reg_1 ( NE , resv , val ) ; emit_insn ( gen_rtx_SET ( val , resv


<s> if ( ! isShiftedImm ( ) && ( ! isImm ( ) || ! isa < MCConstantExpr > ( getImm ( ) ) ) ) return DiagnosticPredicateTy :: NoMatch ; bool IsByte = std :: is_same < int8_t , typename std

:: make_signed < T > :: type > :: value ;


<s> return isDo ( Start ) ? Start -> getOperand ( <NUM_LIT> ) :


<s> void Emitter < CodeEmitter > :: emitSIBByte ( unsigned SS , unsigned Index ,


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue X = Node -> getOperand ( <NUM_LIT> ) ; SDValue OneVec = Node -> getOperand ( <NUM_LIT> ) ; APInt SplatVal ; if ( ! <STR_LIT> ( OneVec , SplatVal ) || ! SplatVal . isOneValue ( ) ) return false ; SDLoc DL ( Node ) ; SDValue OneConstant , AllOnesVec ; APInt Ones = APInt :: getAllOnesValue ( <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; OneConstant = CurDAG -> getConstant ( Ones , DL , <STR_LIT> ) ; insertDAGNode ( * CurDAG , X , OneConstant ) ; unsigned NumElts = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; AllOnesVec = CurDAG -> getSplatBuildVector ( <STR_LIT> ( <STR_LIT> , NumElts ) , DL , OneConstant ) ; insertDAGNode ( * CurDAG , X , AllOnesVec ) ; AllOnesVec = CurDAG -> getBitcast ( VT , AllOnesVec ) ; insertDAGNode ( * CurDAG , X , AllOnesVec ) ; unsigned NewOpcode = Node -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue NewNode = CurDAG -> getNode ( NewOpcode , DL , VT , X , AllOnesVec ) ; ReplaceNode ( Node , NewNode .


<s> bool IsImm8 = int8_t ( Imm ) == Imm ; bool IsImm16 = int16_t ( Imm & ~ <NUM_LIT> ) == Imm ; if ( std :: is_same < int8_t , std :: make_signed_t < T >> :: value || std :: is_same < int8_t , T > :: value ) return IsImm8 ||


<s> switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op


<s> unsigned getMaxSupportedInterleaveFactor ( )


<s> SDValue CC = getCCResult ( DAG , Glued . getNode ( ) ) ; if ( Op -> getNumValues ( ) == <NUM_LIT> ) return CC ; assert ( Op -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op -> getVTList ( ) , Glued , CC ) ; } unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _aand_i32 ( int * __A , int __B ) { __builtin_ia32_aand32 ( ( int * ) __A


<s> ++ ByValArg ; continue ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . isRegLoc ( ) ) { if ( ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) ) Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; else if ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; unsigned LocRegLo = VA . getLocReg ( ) ; unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; continue ; } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , DL , IsTailCall , DAG ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; bool IsPICCall = ( isN64 ( ) || IsPIC ) ; bool GlobalOrExternal = false , InternalLinkage = false ; SDValue CalleeLo ; EVT Ty = Callee . getValueType ( ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( IsPICCall ) { const GlobalValue * Val = G -> getGlobal ( ) ; InternalLinkage = Val -> hasInternalLinkage ( ) ; if ( InternalLinkage ) Callee = getAddrLocal ( G , Ty , DAG , isN32 ( ) || isN64 (


<s> SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_ROUND ( SDValue Op , SelectionDAG & DAG ) const { bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue In = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( SVT != <STR_LIT> && ! ( VT == <STR_LIT> && SVT == <STR_LIT> ) ) return Op ; return SDValue (


<s> static inline unsigned getShiftValue ( unsigned Imm ) { return Imm &


<s> return ( uint32x4_t ) __builtin_neon_vhsubuv4si ( ( int32x4_t ) __a , (


<s> rel_entry . targetRef ( ) . assign ( pFrag , pOffset ) ; if ( pType == llvm :: ELF :: R_<ISA_LIT>_64_RELATIVE || pSym == NULL ) rel_entry . setSymInfo ( NULL ) ; else rel_entry . setSymInfo ( pSym


<s> else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst ->


<s> if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) )


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( )


<s> if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , <NUM_LIT> ) ; return DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget . hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts


<s> if ( TARGET_DEBUG_ADDR ) { if ( SYMBOL_REF_P ( symbol ) ) fprintf ( stderr , <STR_LIT> , XSTR ( symbol , <NUM_LIT> ) ) ; else { fprintf ( stderr , <STR_LIT> , GET_RTX_NAME ( GET_CODE ( symbol ) ) ) ; debug_rtx ( symbol ) ; } } if ( ! can_create_pseudo_p ( ) ) df_set_regs_ever_live ( TOC_REGISTER , true ) ; tocreg = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; tocrel = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , symbol , tocreg ) , UNSPEC_TOCREL ) ; if ( TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ( ) ) return tocrel ; hi = gen_rtx_HIGH ( Pmode , copy_rtx ( tocrel ) ) ; if ( largetoc_reg != NULL


<s> unsigned regno2 = aarch64_get_next_set_bit ( components , regno + <NUM_LIT> ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || ( aarch64_simd_decl_p ( cfun -> decl ) && FP_REGNUM_P ( regno ) ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode


<s> if ( insn -> prefixPresent [ prefix ] == <NUM_LIT> && insn -> prefixLocations [ prefix ] == location ) return TRUE ; else return FALSE


<s> SDValue ElemV = N -> getOperand ( <NUM_LIT> ) ; auto * ElemN = dyn_cast < ConstantSDNode > ( ElemV ) ; if ( ! ElemN ) return false ; unsigned Elem = ElemN -> getZExtValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Elem >= VT . getVectorNumElements ( ) ) return false ; auto * Load = dyn_cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Load || ! Load -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( Load -> getMemoryVT ( ) . getSizeInBits ( ) != Load -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) return false ; SDValue Base , Disp , Index ; if ( ! selectBDVAddr12Only ( Load -> getBasePtr ( ) , ElemV , Base , Disp , Index ) || Index . getValueType ( ) != VT . changeVectorElementTypeToInteger ( ) ) return false ; SDLoc DL ( Load ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Base , Disp , Index , CurDAG -> getTargetConstant ( Elem , DL , <STR_LIT> ) , Load -> getChain ( ) } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , DL , VT , <STR_LIT> , Ops ) ; ReplaceUses ( SDValue ( Load , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) ) ; ReplaceNode ( N


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets =


<s> void <ISA_LIT>BaseInstrInfo :: getUnconditionalBranch ( MCInst & Branch , const MCSymbolRefExpr * BranchTarget ) const { if ( Subtarget . isThumb ( ) ) Branch . setOpcode ( <STR_LIT> ) ; else if ( Subtarget . isThumb2 ( ) ) Branch . setOpcode ( <STR_LIT> ) ; else Branch . setOpcode ( <STR_LIT> ) ; Branch . addOperand ( MCOperand :: CreateExpr ( BranchTarget ) ) ; Branch . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; Branch . addOperand ( MCOperand :: CreateReg (


<s> for ( unsigned i = <NUM_LIT> ; i != NElts ; ++


<s> inline vector signed short vec_mradds ( vector signed short a1 , vector signed short a2 , vector signed short a3 ) { return ( vector signed short ) __builtin_altivec_vmhraddshs ( ( vector signed short ) a1 , ( vector signed short ) a2 , ( vector


<s> return ( vector signed int ) __builtin_altivec_vcmpgtfp ( ( vector float


<s> return TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ; case MODE_V2DF : return <STR_LIT> ; case MODE_V4SF : return <STR_LIT> ; case MODE_OI : return TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ; case MODE_V4DF : return <STR_LIT> ; case MODE_V8SF : return <STR_LIT> ; default : break ; } case


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI


<s> unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand ::


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == <STR_LIT> ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; Register InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get (


<s> case <STR_LIT> : { unsigned EltSize = EltVT . getSizeInBits ( ) ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return false ; MVT OpEltVT = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . isInteger ( ) != OpEltVT . isInteger ( ) ) return false ; uint64_t Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Imm = ( Imm * OpEltVT . getSizeInBits ( ) ) / EltSize ; SDValue Op0 = DAG . getBitcast ( VT , Op . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Op0 . getNode ( ) ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; MVT Op1VT = <STR_LIT> ( EltVT , Op1 . getSimpleValueType ( ) . getSizeInBits ( ) / EltSize ) ; Op1 = DAG . getBitcast ( Op1VT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , DAG . getIntPtrConstant ( Imm , DL ) ) ) ; return true ; } case <STR_LIT> : { unsigned EltSize = EltVT . getSizeInBits ( ) ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return false ; MVT OpEltVT = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . isInteger ( ) != OpEltVT . isInteger ( ) ) return false ; uint64_t Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Imm = ( Imm * OpEltVT . getSizeInBits ( ) ) / EltSize ; SDValue Op0 = Op . getOperand


<s> inline unsigned getRegAsVR128 ( unsigned Reg ) { return VR128Regs [ getFirstReg ( Reg )


<s> for ( auto & LoopExitTerminator : LoopExit -> terminators ( ) ) { if ( LoopExitTerminator . getOpcode ( ) != <STR_LIT> ) continue ; MachineBasicBlock * LoopExit2 = LoopExitTerminator . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! blockIsBefore ( LoopExit2 , LoopExit ) && ( LoopExit2 == Preheader || blockIsBefore ( LoopExit2 , Preheader ) ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> ) ; CanMove = false ; break ; } } if ( CanMove ) { for ( auto It = LoopExit -> getIterator ( ) ; It != Preheader -> getIterator ( ) ; It ++ ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( Terminator . getOpcode ( ) != <STR_LIT> && Terminator . getOpcode ( ) !=


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . padShortFunctions ( ) ) return false ; TSM . init ( & MF . getSubtarget ( ) ) ; auto * PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; auto * MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; ReturnBBs . clear ( ) ; VisitedBBs . clear ( ) ; findReturns ( & MF . front ( ) ) ; bool MadeChange = false ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MachineBasicBlock * MBB = I -> first ; unsigned Cycles = I -> second ; bool OptForSize = llvm :: shouldOptimizeForSize ( MBB , PSI , MBFI ) ; if ( OptForSize ) continue ; if ( Cycles < Threshold


<s> return <ISA_LIT>Lowering . SelectAddressRegRegOnly ( N , Base , Index , *


<s> switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned MSubOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> )


<s> bool isMemDisp12 ( MemoryKind MemKind , RegisterKind


<s> if ( ! Subtarget -> has8MSecExt ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue > <NUM_LIT> ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV8MMainlineOps ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> ) ) return - <NUM_LIT> ; if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags , Subtarget -> hasDSP (


<s> } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool isIXAddr = usesIXAddr ( MI ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( noImmForm ) OperandBase = <NUM_LIT> ; else if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode ) ) ; OperandBase = <NUM_LIT> ; } else { OperandBase = OffsetOperandNo ; } unsigned StackReg = MI . getOperand ( FIOperandNum ) . getReg ( ) ; MI . getOperand ( OperandBase ) . ChangeToRegister ( StackReg , false ) ; MI . getOperand ( OperandBase + <NUM_LIT> ) . ChangeToRegister ( SReg , false , false


<s> if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t FPOffset = Offset - <NUM_LIT> * <NUM_LIT> ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; if ( TFI -> hasFP ( MF ) && isFrameOffsetLegal ( MI , <STR_LIT> , FPOffset ) ) return false ; if ( isFrameOffsetLegal ( MI , <STR_LIT> , Offset


<s> unsigned Opcode = I . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opcode ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , MRI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I ) ) return true ; DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; if ( selectLoadStoreOp ( I , MRI , MF ) ) return true ; if ( selectFrameIndexOrGep ( I , MRI , MF ) ) return true ; if ( selectGlobalValue ( I , MRI , MF ) ) return true ; if ( selectConstant ( I , MRI , MF ) ) return true ; if ( selectTrunc ( I , MRI , MF ) ) return true ; if ( selectZext ( I , MRI , MF ) ) return true ; if ( selectCmp ( I , MRI , MF ) ) return true ; if ( selectUadde ( I , MRI , MF ) ) return true ; if ( selectUnmergeValues ( I , MRI , MF ) ) return true ; if ( selectMergeValues ( I , MRI , MF ) ) return true ; if ( selectExtract ( I , MRI , MF ) ) return true ; if ( selectInsert ( I , MRI ,


<s> enum csky_inline_const_type trick_type ; rtx out_operands [ <NUM_LIT> ] ; char buf [ <NUM_LIT> ] ; char load_op [ <NUM_LIT> ] ; const char * dst_fmt ; HOST_WIDE_INT value = INTVAL ( operands [ <NUM_LIT> ] ) ; int ivalue = ( int ) value ; unsigned int uvalue = ( unsigned int ) value ; trick_type = try_csky_constant_tricks ( value , & x , & y ) ; gcc_assert ( trick_type != IC_UNINLINABLE ) ; out_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; out_operands [ <NUM_LIT> ] = GEN_INT ( x ) ; if ( trick_type != IC_SINGLE && trick_type != IC_APPEND_NOT ) out_operands [ <NUM_LIT> ] = GEN_INT ( y ) ; if ( mode == DImode && TARGET_BIG_ENDIAN ) dst_fmt = <STR_LIT> ; else dst_fmt = <STR_LIT> ; if ( CSKY_CONST_OK_FOR_I ( x ) ) sprintf ( load_op , <STR_LIT> , dst_fmt ) ; else if ( CSKY_CONST_OK_FOR_Uc ( x ) ) sprintf ( load_op , <STR_LIT> , dst_fmt ) ; else if ( CSKY_CONST_OK_FOR_MOVIH ( x ) ) sprintf ( load_op , <STR_LIT> , dst_fmt ) ; else { sprintf ( load_op , <STR_LIT> , dst_fmt ) ; gcc_unreachable ( ) ; } switch ( trick_type ) { case IC_SINGLE : strcpy ( buf , load_op ) ; break ; case IC_APPEND_NOT : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_ADDI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_SUBI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_BGENI_ADDI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_BGENI_SUBI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_BSETI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_MOVI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt ,


<s> bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasCLMUL = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasFMA3 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasMOVBE = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasPOPCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasAES = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && Model == <NUM_LIT> ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX


<s> output_asm_insn ( <STR_LIT> , & stub_label ) ; } else output_asm_insn ( <STR_LIT> , & addr ) ; return


<s> } else { rtx tmp ; emit_insn ( gen_load_tp_soft ( ) ) ; tmp = gen_rtx_REG ( SImode , <NUM_LIT>


<s> bool supportsEfficientVectorElementLoadStore (


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter ) ; new <ISA_LIT>TargetELFStreamer ( * S ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; return


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( IsVarArg ) { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( )


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int form_int ; enum rtx_code code ; if ( TREE_CODE ( form ) != INTEGER_CST ) { error ( <STR_LIT> ) ; return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCmode )


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( Is64Bit


<s> if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ; Ops . push_back ( * HiAdd ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeNode , <NUM_LIT> ) , HiMLALResult ) ; SDValue LoMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcNode , <NUM_LIT> ) , LoMLALResult ) ; SDValue resNode ( AddcNode , <NUM_LIT> ) ; return


<s> SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand ::


<s> } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool hasDominantValue = false ; bool isConstant = true ; DenseMap < SDValue , unsigned > ValueCounts ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; ValueCounts . insert ( std :: make_pair ( V , <NUM_LIT> ) ) ; unsigned & Count = ValueCounts [ V ] ; if ( ++ Count > ( NumElts / <NUM_LIT> ) ) { hasDominantValue = true ; Value = V ; } } if ( ValueCounts . size ( ) != <NUM_LIT> ) usesOnlyOneValue = false ; if ( ! Value . getNode ( ) && ValueCounts . size ( ) > <NUM_LIT> ) Value = ValueCounts . begin ( ) -> first ; if ( ValueCounts . size ( ) == <NUM_LIT> ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement && ! <STR_LIT> ( Value . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( hasDominantValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) { SDValue N ; if ( Value -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Value -> getOperand ( <NUM_LIT> ) ) ) { N = DAG . getNode ( <STR_LIT> , DL , VT , Value -> getOperand ( <NUM_LIT> ) , Value -> getOperand ( <NUM_LIT> ) ) ; } else N = DAG . getNode (


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT>


<s> if ( ! REG_P ( SET_DEST ( memop ) ) ) return false ; load_reg = SET_DEST ( memop ) ; for ( opno = <NUM_LIT> ; opno < recog_data . n_operands ; opno ++ ) { rtx operand = recog_data . operand [ opno ] ; if ( REG_P ( operand ) && reg_overlap_mentioned_p ( load_reg


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( hasStackRealignment ( MF ) && MFI . hasVarSizedObjects ( )


<s> return ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x

) || CONSTANT_ADDRESS_P ( x ) || flag_pic ) ;


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMemory ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm


<s> unsigned Register = DDDDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> MCSymbol * <ISA_LIT>_64MachoTargetObjectFile :: getCFIPersonalitySymbol ( const GlobalValue * GV , const TargetMachine & TM , MachineModuleInfo * MMI ) const { return TM . getSymbol


<s> static MachineBasicBlock * insertDivByZeroTrap ( MachineInstr * MI , MachineBasicBlock & MBB , const TargetInstrInfo & TII , bool Is64Bit ) { if ( NoZeroDivCheck ) return & MBB ; MachineBasicBlock :: iterator I ( MI ) ; MachineInstrBuilder MIB ; MachineOperand & Divisor = MI -> getOperand ( <NUM_LIT> ) ; MIB = BuildMI ( MBB , std :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor

. getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode ,


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) &&


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarryx_u32 ( unsigned char __CF , unsigned int __X , unsigned int __Y , unsigned int * __P ) { return __builtin_ia32_addcarryx_u32 ( __CF , __X , __Y


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setAlignment ( <NUM_LIT> ) ; } else CPEBB -> setAlignment ( getCPELogAlign ( & * CPEBB -> begin ( ) ) ) ; BBUtils -> adjustBBOffsetsAfter ( CPEBB ) ; assert ( ! BBIsJumpedOver ( CPEBB


<s> Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler ::


<s> return ( uint16x8_t ) __builtin_neon_vmvnv8hi (


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return &


<s> return tryCombineFixedPointConvert ( N , DCI , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return combineAcrossLanesIntrinsic ( <STR_LIT> , N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> ,


<s> void printMemRegReg ( const MachineInstr * MI , unsigned OpNo ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; printRegister ( MO , true ) ; O <<


<s> assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty

, Hi ) , DAG . getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ] && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList


<s> RM = TT . isOSDarwin ( ) ? Reloc :: PIC_ : Reloc :: DynamicNoPIC ; } X -> initMCCodeGenInfo ( RM , CM


<s> void DecodePUNPCKLQDQMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts )


<s> int getFramePointerOffset ( ) const { return FramePointerOffset


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> <ISA_LIT>FunctionInfo & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( const auto & Info : CSI ) { if ( ! ( MFI . getStackID ( Info . getFrameIdx ( ) ) == TargetStackID :: ScalableVector ) ) continue ; assert ( ! Info . isSpilledToReg ( ) && <STR_LIT> ) ; unsigned Reg = Info . getReg ( ) ; if ( ! static_cast < const <ISA_LIT>RegisterInfo & > ( TRI ) . regNeedsCFI ( Reg , Reg ) ) continue ; StackOffset Offset = StackOffset :: getScalable ( MFI . getObjectOffset ( Info . getFrameIdx ( ) ) ) - StackOffset :: getFixed ( AFI . getCalleeSavedStackSize ( MFI ) ) ; unsigned CFIIndex = MF . addFrameInst ( createCFAOffset ( TRI , Reg , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION )

) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ; else name = <STR_LIT> ; name += DLLExportedGlobals [ i ] -> getName ( ) ; if ( Subtarget -> isTargetWindows ( ) ) name += <STR_LIT> ; else name += <STR_LIT> ; OutStreamer . EmitBytes ( name ) ; } for ( unsigned i = <NUM_LIT> , e = DLLExportedFns . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ; else name = <STR_LIT> ; name += DLLExportedFns [ i ] -> getName ( ) ; OutStreamer . EmitBytes ( name ) ; } } } if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF


<s> int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MachineBasicBlock :: iterator B =


<s> static DecodeStatus DecodeCR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ,


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I != MBB . begin ( ) ) I -- ; else return Changed


<s> unsigned <ISA_LIT>RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank &


<s> if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_2 : Type = ELF :: R_TEERISC_32_PCREL ; break ; } }


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI .


<s> } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , <NUM_LIT> ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; rtx pcvr1 = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_pcvr1 ( pcvr1 , tmp ) ) ; rtx sub_target = simplify_gen_subreg ( V16QImode , target , mode , <NUM_LIT> ) ; rtx perm1 = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr1 ) ; emit_insn ( perm1 ) ; rs6000_expand_vector_set ( target , val , const0_rtx ) ; rtx pcvr2 = gen_reg_rtx (


<s> assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegacyLegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegacyLegalizeActions :: WidenScalar } , { <NUM_LIT> , LegacyLegalizeActions


<s> const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = is<ISA_LIT>64 ? G8RC : GPRC ; unsigned CountReg ; if ( TripCount -> isReg ( ) ) { const TargetRegisterClass * SrcRC = MF -> getRegInfo ( ) . getRegClass ( TripCount -> getReg ( ) ) ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned CopyOp = ( is<ISA_LIT>64 && SrcRC == GPRC ) ? ( unsigned ) <STR_LIT> : ( unsigned ) TargetOpcode :: COPY ; BuildMI ( * Preheader , InsertPos , dl , TII -> get ( CopyOp ) , CountReg ) . addReg ( TripCount -> getReg ( ) ) ; if ( TripCount -> isNeg ( ) ) { unsigned CountReg1 = CountReg ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , dl , TII -> get ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) , CountReg ) . addReg ( CountReg1 ) ; } } else { assert ( TripCount -> isImm ( ) && <STR_LIT> ) ; int64_t CountImm = TripCount -> getImm ( ) ; assert ( ! TripCount -> isNeg ( ) && <STR_LIT> ) ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( CountImm > <NUM_LIT> ) { BuildMI ( * Preheader , InsertPos , dl , TII -> get ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) , CountReg ) . addImm ( CountImm >> <NUM_LIT> ) ; unsigned CountReg1 = CountReg ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , dl , TII -> get ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) , CountReg ) .

addReg ( CountReg1 ) . addImm ( CountImm & <NUM_LIT> ) ;


<s> <STR_LIT> BlockMask = CreateVPTBlock ( MBIter , EndIter , DeadInstructions ) ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( unsigned ) BlockMask << <STR_LIT> ) ; if ( MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; for ( MachineInstr & MII : make_range ( VCMP -> getIterator ( ) , MI -> getIterator ( ) ) ) { MII . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; MII . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; } VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; } for ( MachineInstr * DeadMI : DeadInstructions ) DeadMI -> eraseFromParent (


<s> if ( load && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) return false ; if ( const_store && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) && INTVAL ( operands [ <NUM_LIT> ] ) != INTVAL ( operands [ <NUM_LIT> ] ) ) { if ( TARGET_THUMB2 ) { CLEAR_HARD_REG_SET ( regset ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ <NUM_LIT> ] = tmp ; } else if ( TARGET_ARM ) { int regno = REGNO ( operands [ <NUM_LIT> ] ) ; if ( ! peep2_reg_dead_p ( <NUM_LIT> , operands [ <NUM_LIT> ] ) ) { if ( regno % <NUM_LIT> == <NUM_LIT> ) return false ; SET_HARD_REG_SET ( regset ) ; CLEAR_HARD_REG_BIT ( regset , regno - <NUM_LIT> ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ <NUM_LIT> ] = tmp ; } else { CLEAR_HARD_REG_SET ( regset ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DImode , & regset ) ; if ( tmp != NULL_RTX ) { operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; } else { SET_HARD_REG_SET ( regset ) ; CLEAR_HARD_REG_BIT ( regset , regno % <NUM_LIT> == <NUM_LIT> ? regno + <NUM_LIT> : regno - <NUM_LIT> ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ regno % <NUM_LIT> == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] = tmp ; } } gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; emitLabelAtPos ( Symbol , Loc


<s> nextMBB -> transferSuccessors ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; DebugLoc dl = mInstr -> getDebugLoc ( ) ; assert ( mInstr -> getNumOperands ( ) < <ISA_LIT>AddrNumOperands + <NUM_LIT> && <STR_LIT> ) ; MachineOperand & destOper = mInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <ISA_LIT>AddrNumOperands ] ; int numArgs = mInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & mInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <ISA_LIT>AddrNumOperands - <NUM_LIT> ; int valArgIndx = lastAddrIndx + <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( t1 ) ; MIB . addReg ( t2 ) ; unsigned t3 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( cmovOpc ) , t3 ) ; MIB . addReg ( t2 ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl ,


<s> StringRef <STR_LIT> ( const Triple & TT , StringRef CPU ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . isMIPS32 ( )


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( ! Subtarget -> hasFP64 ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ,


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> static DecodeStatus DecodeCPU16RegsRegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Address , const void * Decoder ) {


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue * > ( GV ) , ACPV , MayNeedFarStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , const_cast < GlobalValue


<s> unsigned Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> ) O << '#' << Imm ; else O << getRegisterName ( Reg ) ; } else llvm_unreachable ( <STR_LIT>


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( DstReg ) ; const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( WideTy . getSizeInBits ( ) >= NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; assert ( ! NarrowTy . isVector ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( LaneIdxOp . getReg ( ) , MRI


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleFP ( <STR_LIT> Value , bool Is32BitABI ) { <ISA_LIT>TargetStreamer :: emitDirectiveModuleFP ( Value , Is32BitABI ) ; StringRef ModuleValue ; OS << <STR_LIT>


<s> bool isSysCR ( ) const { return Kind == k_SysCR


<s> auto CCNode = cast < ConstantSDNode > ( CMOV -> getOperand ( <NUM_LIT> ) ) ; auto CC = CCNode -> getAPIntValue ( ) . getLimitedValue ( ) ; SDValue CmpZ = CMOV -> getOperand ( <NUM_LIT> ) ; assert ( CmpZ -> getOpcode ( ) == <STR_LIT> ) ; SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * AndC = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC || ! AndC -> getAPIntValue ( ) . isPowerOf2 ( ) ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; APInt KnownZero , KnownOne ; computeKnownBits ( DAG , Y , KnownZero , KnownOne ) ; if ( ( OrCI & KnownZero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> getAPIntValue ( ) . logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ; } for ( unsigned BitInY = <NUM_LIT> , NumActiveBits = OrCI


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = false ; RegD = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegD , & isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ; else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD & <NUM_LIT> ) <<


<s> unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_SysCR : OS << <STR_LIT> << getSysCR ( ) ; break ; case k_Prefetch : { StringRef Name = getPrefetchName ( ) ; if ( ! Name . empty ( ) ) OS << <STR_LIT> << Name << <STR_LIT> ; else OS << <STR_LIT> << getPrefetch ( ) << <STR_LIT> ; break ; } case k_PSBHint : OS << getPSBHintName ( ) ; break ; case


<s> unsigned <ISA_LIT>InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return <NUM_LIT> ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return


<s> MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn (


<s> case V8SImode : case V4SImode : case V8SFmode : case V4SFmode : vec_mode = mode ; mode = GET_MODE_INNER ( mode ) ; imode = SImode ; lo = <NUM_LIT> , hi = lo < <NUM_LIT> ; break ; case V8DImode : case V4DImode : case V2DImode : case V8DFmode : case V4DFmode : case V2DFmode : vec_mode = mode ; mode = GET_MODE_INNER ( mode ) ; imode = DImode ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) lo = ( HOST_WIDE_INT ) <NUM_LIT> << shift , hi = - <NUM_LIT> ; else lo = <NUM_LIT> , hi = ( HOST_WIDE_INT ) <NUM_LIT> << ( shift - HOST_BITS_PER_WIDE_INT ) ; break ; case TImode : case TFmode : vec_mode = VOIDmode ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) { imode =


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa . mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA :


<s> void printi64mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI ,


<s> if ( DefMI -> getOpcode ( ) != <STR_LIT> || DefMI -> getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ; for ( auto I = DefMI ; I != FrameSetup ; ++ I ) if ( I -> getOpcode ( ) != <STR_LIT> ) return nullptr ; return DefMI


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Commute = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true


<s> bool isVecListDPairSpaced ( ) const { if ( Kind != k_VectorList ) return false ; if ( isSingleSpacedVectorList ( ) ) return false ; return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( VectorList . RegNum )


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( )


<s> return __builtin_mve_vcmpltq_sv16qi ( __a ,


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> void addSImm9Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Extract ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG .


<s> if ( flag_pic ) return <NUM_LIT> ; else if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI


<s> rel_entry . setType ( pType ) ; rel_entry . targetRef ( ) . assign ( pFrag , pOffset ) ; if ( pType == llvm :: ELF :: R_AARCH64_RELATIVE || pSym ==

NULL ) rel_entry . setSymInfo ( NULL ) ;


<s> if ( ! ImmToIdxMap . count ( ImmOpcode ) ) return <STR_LIT> ; return ImmToIdxMap . find (


<s> switch ( STI . getFeatureBits ( ) & ( <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) { case <STR_LIT> : fMode = MODE_16BIT ; break ; case <STR_LIT> : fMode = MODE_32BIT ; break ; case <STR_LIT> : fMode = MODE_64BIT


<s> if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ; return *


<s> static bool sh_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '.' || code == '#' || code == '@' || code == ',' || code == '$' ||


<s> if ( ValTy . getSizeInBits ( ) != Store . getMemSizeInBits ( ) ) return false ; if ( ! MRI . hasOneNonDBGUse ( Store . getValueReg ( ) ) ) return false ; auto MaybeCst = isConstantOrConstantSplatVector ( * MRI . getVRegDef ( Store . getValueReg ( ) ) , MRI ) ; return MaybeCst && MaybeCst -> isZero


<s> const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( )


<s> void addAdrpLabelOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) addExpr ( Inst , getImm ( ) ) ; else Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue


<s> static <ISA_LIT>Operand * createAccessReg ( unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindAccessReg , StartLoc , EndLoc ) ; Op -> AccessReg = Num ; return


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( RegNum ) ; O <<


<s> SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back


<s> static DecodeStatus DecodeSynciR6 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Immediate = SignExtend32 < <NUM_LIT>


<s> unsigned POTReg = getPOTBaseRegister ( ) ; if ( MF . getFunction ( ) . isPagerando ( ) ) { return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , POTReg , PtrVT ) ; } else { SDValue POTAddress = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; POTAddress = DAG . getNode ( <STR_LIT> , dl , PtrVT , POTAddress ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , POTReg , POTAddress ) ; SDValue Ops [ <NUM_LIT> ] = { POTAddress , Chain } ; return DAG . getMergeValues (


<s> Register VirtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } else { unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC )


<s> void scalar_chain :: add_to_queue ( unsigned insn_uid ) { if ( ! bitmap_set_bit ( queue


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 ,

V2 , Mask , Subtarget , DAG ) ) return V ;


<s> void <ISA_LIT>AsmBackend :: emitInstructionBegin ( MCObjectStreamer & OS , const MCInst & Inst , const MCSubtargetInfo & STI ) { CanPadInst = canPadInst ( Inst , OS ) ; if ( ! canPadBranches ( OS ) ) return ; if ( ! isMacroFused ( PrevInst , Inst ) ) PendingBA = nullptr ; if ( ! CanPadInst ) return ; if ( PendingBA && OS . getCurrentFragment ( ) -> getPrevNode ( ) == PendingBA ) { return ; } if ( needAlign ( Inst ) || ( ( AlignBranchType & <STR_LIT> ) && isFirstMacroFusibleInst ( Inst , * MCII )


<s> void <ISA_LIT>InstPrinter :: printPostIncOperand ( const MCInst * MI , unsigned OpNo , unsigned Imm , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> ) O << <STR_LIT> << Imm ; else O << getRegisterName ( Reg ) ; } else assert ( <NUM_LIT>


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> return ( vector float ) __builtin_altivec_vlogefp ( ( vector float )


<s> void <ISA_LIT>AsmPrinter :: EmitSled ( const MachineInstr & MI , SledKind Kind ) { if ( MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ) { MI . emitError ( <STR_LIT> <STR_LIT> ) ; return ; } static const int8_t NoopsInSledCount = <NUM_LIT> ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT>


<s> machine_mode sh_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( FP_REGISTER_P ( regno ) && ( mode == SFmode || mode == SCmode || ( ( mode == DFmode || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT> ) ) ) return mode ; return choose_hard_reg_mode ( regno , nregs


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveR19R20X ( int


<s> continue ; } if ( ParseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getTok


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterAsmInfo < <ISA_LIT>ELFTargetAsmInfo > Y ( The<ISA_LIT>Target


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> bool <ISA_LIT>InstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { return TargetInstrInfo :: verifyInstruction ( MI ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( Imm . Val ) ; uint32_t Bits ; A64Imms :: isLogicalImm ( RegWidth , CE -> getValue ( )


<s> return __builtin_mve_vaddq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a


<s> void iq2000_expand_eh_return ( rtx address ) { HOST_WIDE_INT gp_offset = cfun -> machine -> gp_sp_offset ; rtx scratch ; scratch = plus_constant ( Pmode ,


<s> const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else assert ( false


<s> add_reg_br_prob_note ( insn , profile_probability :: from_reg_br_prob_base ( prob )


<s> if ( ET == <STR_LIT> ) ET = <STR_LIT> ; unsigned Imm = <STR_LIT> ( ET , getShiftExtendAmount ( ) ) ; Inst . addOperand ( MCOperand :: createImm


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; Relocator :: DWord X = ( ( S + A ) | T ) - P ; if ( helper_check_signed_overflow ( X , <NUM_LIT> ) ) { return Relocator :: Overflow ; } else { pReloc . target ( ) = helper_insert_val_movw_movt_inst ( pReloc . target ( ) ,


<s> std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL


<s> if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF (


<s> bool IsLittleEndian = ! Subtarget . isLittle ( ) ; SDValue IfSet , IfClr , Cond ; bool IsConstantMask = false ; APInt Mask , InvMask ; if ( isVSplat ( Op0Op0 , Mask , IsLittleEndian ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; if ( isVSplat ( Op1Op0 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op1 ; else if ( isVSplat ( Op1Op1 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op0 ; IsConstantMask = true ; } if ( ! IfClr . getNode ( ) && isVSplat ( Op0Op1 , Mask , IsLittleEndian ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; if ( isVSplat ( Op1Op0 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op1 ; else if ( isVSplat ( Op1Op1 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op0 ; IsConstantMask = true ; } if ( ! IfClr . getNode ( ) ) { if ( isBitwiseInverse ( Op0Op0 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op0Op0 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr = Op1Op1 ; } else if ( isBitwiseInverse ( Op1Op1 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr = Op1Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op1 ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; IfClr = Op1Op1 ; } else if ( isBitwiseInverse ( Op1Op1 , Op0Op1 ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; IfClr = Op1Op0 ; } } if ( ! IfClr . getNode ( ) )


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv4sf (


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_M44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_L44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HH22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HM10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_HIX22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_LOX10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LDX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LE_HIX22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LE_LOX10 ; } return ELF


<s> break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( ResultReg ) ) ; ResultReg = MoveReg ; } return


<s> if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAddress ( ) && isAddressLdStPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseCCSelect ( ) && isCCSelectPair ( FirstMI


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == <STR_LIT> ) if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) .


<s> if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> ,


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_None : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCHI : FixupKind =


<s> return isFIBase ( ) || ( isRegBase ( ) && getReg


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) GlobalPrefix


<s> int64_t LoOffset = OffsetOp . getImm ( ) & <NUM_LIT> ; int64_t HiOffset = OffsetOp . getImm ( ) & ~ <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset += <NUM_LIT> ; bool IsLargeOffset = HiOffset != <NUM_LIT> ; if ( IsLargeOffset ) { bool Is32BitImm = ( HiOffset >> <NUM_LIT> ) == <NUM_LIT> ; if ( loadImmediate ( HiOffset , TmpReg , <STR_LIT> , Is32BitImm , true , IDLoc , Out , STI ) ) return ; } if ( BaseReg != <STR_LIT> && BaseReg != <STR_LIT> ) TOut . emitRRR ( isGP64bit ( ) ? <STR_LIT> : <STR_LIT> , TmpReg , TmpReg , BaseReg , IDLoc , STI ) ; TOut . emitRRI ( Inst . getOpcode ( ) , DstReg , TmpReg , LoOffset , IDLoc , STI ) ; } else { assert ( OffsetOp . isExpr ( ) && <STR_LIT> ) ; const MCExpr * ExprOffset = OffsetOp . getExpr ( ) ; MCOperand LoOperand = MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , ExprOffset , getContext ( ) ) ) ; MCOperand HiOperand = MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , ExprOffset , getContext ( ) ) ) ; if ( IsLoad ) TOut . emitLoadWithSymOffset ( Inst . getOpcode ( ) , DstReg , BaseReg , HiOperand , LoOperand , TmpReg , IDLoc , STI ) ; else TOut . emitStoreWithSymOffset ( Inst . getOpcode ( ) , DstReg , BaseReg , HiOperand , LoOperand , TmpReg , IDLoc


<s> bool systemSupportsUnalignedAccess ( ) const { return has<ISA_LIT>32r6 (


<s> return <ISA_LIT>_64ApplyFunctions [ pType ] .


<s> StringRef getPassName ( ) const override { return <STR_LIT>


( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || ! SYMBOL_REF_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) || ! CONST_INT_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; else { rtx sum = XEXP ( op , <NUM_LIT> ) ; HOST_WIDE_INT summand


<s> static void ix86_store_bounds ( rtx ptr , rtx slot , rtx bounds , rtx slot_no ) { rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , stack_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot )


<s> if ( MI -> isCall ( ) ) RegDefs . insert ( <STR_LIT> ) ; if ( MI -> isReturn ( ) ) RegUses . insert ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { const MachineOperand & MO = MI


<s> unsigned IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Locality = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned IsData = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool IsStream = ! Locality ; if ( Locality ) { assert ( Locality <= <NUM_LIT> &&


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; } case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_PLT : return ELF :: R_<ISA_LIT>_CALL ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_TLS_CALL ; default : return ELF :: R_<ISA_LIT>_CALL ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ELF :: R_<ISA_LIT>_JUMP24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVT_PREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP11 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP8 ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_THM_TLS_CALL ; default : return ELF :: R_<ISA_LIT>_THM_CALL ; } } } switch ( ( unsigned ) Fixup . getKind ( ) ) { default : Ctx . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS8 ; } case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS16 ; } case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_GOT : return ELF :: R_<ISA_LIT>_GOT_BREL ; case MCSymbolRefExpr :: VK_TLSGD : return ELF :: R_<ISA_LIT>_TLS_GD32 ; case MCSymbolRefExpr :: VK_TPOFF : return ELF :: R_<ISA_LIT>_TLS_LE32 ; case MCSymbolRefExpr :: VK_GOTTPOFF : return ELF :: R_<ISA_LIT>_TLS_IE32 ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS32 ; case MCSymbolRefExpr :: VK_GOTOFF : return ELF :: R_<ISA_LIT>_GOTOFF32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : return ELF :: R_<ISA_LIT>_TARGET1 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : return ELF :: R_<ISA_LIT>_TARGET2 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : return ELF :: R_<ISA_LIT>_SBREL32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : return ELF :: R_<ISA_LIT>_TLS_LDO32 ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_TLS_CALL ; case MCSymbolRefExpr ::


<s> MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO ,


<s> static bool isEndChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE


<s> return ( __m256i ) __builtin_ia32_blendmw_256_mask ( ( __v16hi ) __A , ( __v16hi )


<s> switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = fastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT>