<s> if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; TS . setUsesMicro<ISA_LIT>


<s> unsigned Opc = getStoreRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , false , false , isKill ) ; NewMIs . push_back (


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom


<s> unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned i = <NUM_LIT> , e = CSI . size ( ) ; for ( ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg (


<s> if ( st . hasV6Ops ( ) || <STR_LIT> . contains ( SrcReg ) || ! <STR_LIT> . contains ( DestReg ) ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ) . addReg ( DestReg , getDefRegState (


<s> for ( MachineInstr & BBI : MBB . instrs ( ) ) { unsigned Opc = BBI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { Register Acc = BBI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Acc ) && <STR_LIT> ) ; Candidates [ Acc - <STR_LIT> ] = & BBI ; } else if ( Opc == <STR_LIT> ) { Register Acc = BBI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Acc ) && <STR_LIT> ) ; if ( ! Candidates [ Acc - <STR_LIT> ] ) continue ; InstrsToErase . insert ( & BBI ) ; InstrsToErase . insert ( Candidates [ Acc - <STR_LIT> ] ) ; } else { for ( MachineOperand & Operand : BBI . operands ( ) ) { if ( ! Operand . isReg ( ) ) continue ; Register Reg = Operand . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Candidates [ Reg - <STR_LIT> ] = nullptr ; } } } for ( MachineInstr * MI : InstrsToErase


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( IsWin64 || ( F . getCallingConv ( ) == CallingConv :: Win64 ) ) return & <STR_LIT> ; else if ( Is64Bit ) return & <STR_LIT> ; bool hasHipeCC = ( F . getCallingConv ( ) == CallingConv :: HiPE ) ; if ( hasHipeCC ) return & <STR_LIT> ; return & <STR_LIT>


<s> bool Micro<ISA_LIT>SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMicro<ISA_LIT>Mode ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) || Subtarget ->


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<= ShiftVal ; } else { NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal , CmpVal , NewC . ICmpType ) ; if ( ! NewCCMask ) return ; } C . Opcode = <STR_LIT> ; C . Op0 = NewC .


<s> SDValue AddcOp0 = AddcNode -> getOperand ( <NUM_LIT> ) ; SDValue AddcOp1 = AddcNode -> getOperand ( <NUM_LIT> ) ; if ( AddcOp0 . getNode ( ) == AddcOp1 . getNode ( ) ) return SDValue ( ) ; assert ( AddcNode -> getNumValues ( ) == <NUM_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( AddeNode == NULL ) return SDValue ( ) ; if ( AddeNode -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( AddeNode -> getNumOperands ( ) == <NUM_LIT> && AddeNode -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( )


<s> if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( SrcReg ) ; SrcReg = TmpReg ; } unsigned DestReg ; unsigned Opc ; if ( <ISA_LIT>SubTarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; if ( IsSigned ) Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { DestReg = createResultReg ( & <STR_LIT> ) ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc = <STR_LIT> ; else Opc = <ISA_LIT>SubTarget -> hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; unsigned IntReg = <ISA_LIT>SubTarget -> hasSPE ( ) ? DestReg : <ISA_LIT>MoveToIntReg ( I , DstVT , DestReg , IsSigned ) ; if ( IntReg == <NUM_LIT> ) return false ; updateValueMap ( I , IntReg )


<s> for ( MachineInstr * MI : DefSrcs ) { if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & * I ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { MRI -> constrainRegClass ( NewReg , MRI -> getRegClass ( ( * I ) -> getReg ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << PrintReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg ( NewReg , <NUM_LIT> , * TRI ) ; } } Replacements [ MI ] = NewReg ; } } return Modified


<s> unsigned getCRSaveOffset ( ) const { return CRSaveOffset


<s> static unsigned int rx_pid_base_regnum ( void ) { if ( rx_pid_base_regnum_val == INVALID_REGNUM ) gcc_unreachable ( ) ; return


<s> static char * describe_cache ( unsigned l1_sizekb , unsigned l1_line , unsigned l1_assoc ATTRIBUTE_UNUSED , unsigned l2_sizekb ) { char l1size [ <NUM_LIT> ] , line [ <NUM_LIT> ] , l2size [ <NUM_LIT> ] ; sprintf ( l1size , <STR_LIT> , l1_sizekb ) ; sprintf ( line , <STR_LIT> ,


<s> return DAG . getNode ( <STR_LIT> , dl , DstVT , N0 ) ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG , Subtarget ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; return BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo (


<s> void setVarArgsFrameIndex ( int Index ) { VarArgsFrameIndex =


<s> void <ISA_LIT>VSXSwapRemoval :: formWebs ( ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( unsigned EntryIdx = <NUM_LIT> ; EntryIdx < SwapVector . size ( ) ; ++ EntryIdx ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> << SwapVector [ EntryIdx ] . VSEId << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! isVecReg ( Reg ) ) continue ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { SwapVector [ EntryIdx ] . MentionsPhysVR = <NUM_LIT> ; continue ; } if ( ! MO . isUse ( ) ) continue ; MachineInstr * DefMI = MRI -> getVRegDef ( Reg ) ; assert ( SwapMap . find ( DefMI ) != SwapMap . end ( ) && <STR_LIT> ) ; int DefIdx = SwapMap [ DefMI ] ; ( void ) EC -> unionSets ( SwapVector [ DefIdx ] . VSEId , SwapVector [ EntryIdx ] . VSEId ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ DefIdx ] . VSEId , SwapVector [ EntryIdx ] . VSEId ) ) ; DEBUG ( dbgs ( )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case ELF :: R_<ISA_LIT>_REL24 : case ELF :: R_<ISA_LIT>64_REL24_NOTOC : unsigned Other = cast < MCSymbolELF > ( Sym )


<s> return ( __A [ <NUM_LIT> ] != __B [ <NUM_LIT> ]


<s> static bool isFPSatMinMaxPattern ( Instruction * Inst , const APInt & Imm ) { if ( Imm . getBitWidth ( ) != <NUM_LIT> || Imm != APInt ::

getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) return false ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( ( Value & mask ) != <NUM_LIT> || ( Value >> shift ) > <NUM_LIT> ) return false ; return


<s> if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ; if ( TM . getCodeModel ( ) != CodeModel :: Small && ! Subtarget -> isTargetMachO ( ) ) return <NUM_LIT> ; unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; EVT DestEVT = TLI . getValueType ( GV -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return <NUM_LIT> ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( OpFlags & <STR_LIT> ) { return <NUM_LIT> ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; ResultReg = createResultReg (


<s> Tmp += ( is64BitMode ( ) ) ? <STR_LIT> : ( is32BitMode ( ) ) ? <STR_LIT> : ( is16BitMode ( ) ) ? <STR_LIT> : <STR_LIT> ; Op . setTokenValue ( Tmp ) ; Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MatchingInlineAsm , false ) ) ; Op . setTokenValue ( Base ) ; } } } if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfo ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( UnsizedMemOp && NumSuccessfulMatches > <NUM_LIT> && UnsizedMemOp


<s> assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg ) ) ; unsigned Imm = ( RegShiftedImm . ShiftImm ==

<NUM_LIT> ? <NUM_LIT> : RegShiftedImm . ShiftImm ) ;


<s> setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , SubVecTy ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( SI -> getPointerOperand ( ) , Int8Ptr ) ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , getSequentialMask ( Builder , NumSubElts * i , NumSubElts ) ) ) ; Ops . push_back ( Builder . getInt32 ( SI -> getAlignment ( ) )


<s> enum reg_class ret = rs6000_preferred_reload_class ( x , rclass ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , reg_class_names [ ret ] , reg_class_names [ rclass ] , GET_MODE_NAME ( GET_MODE ( x ) ) ) ; debug_rtx (


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> ) , Subtarget , DAG , SDLoc ( N ) ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N


<s> return ( __m256 ) __builtin_ia32_movsldup256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( )


<s> bool isSelectSupported ( SelectSupportKind Kind )


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && <STR_LIT> ) ; unsigned FPReg = getFPReg ( Op ) ; Op . setReg ( getSTReg ( FPReg ) ) ; if ( Op . isKill ( ) ) Kills [ NumKills ++ ] = FPReg ; } MachineBasicBlock :: iterator InsertPt = MI ; while ( NumKills ) freeStackSlotAfter ( InsertPt , Kills [ -- NumKills ] ) ; return ; } case <STR_LIT> : case <STR_LIT> : if ( isStackEmpty ( ) ) return ; unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && ( Op . isKill ( ) || getFPReg ( Op ) == FirstFPRegOp || MI -> killsRegister ( Op . getReg ( ) ) ) && <STR_LIT> ) ; if ( FirstFPRegOp == ~ <NUM_LIT> ) FirstFPRegOp = getFPReg ( Op ) ; else { assert ( SecondFPRegOp == ~ <NUM_LIT> && <STR_LIT> ) ; SecondFPRegOp = getFPReg ( Op ) ; } MI -> RemoveOperand ( i ) ; -- i , -- e ; } if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; unsigned NewReg = ( FirstFPRegOp + <NUM_LIT> ) % <NUM_LIT> ; duplicateToTop ( FirstFPRegOp , NewReg , MI ) ; FirstFPRegOp = NewReg ; } assert ( StackTop == <NUM_LIT> && <STR_LIT> ) ; if ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp ) { assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; moveToTop ( FirstFPRegOp , MI ) ; } assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; assert ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp && <STR_LIT> ) ; StackTop =


<s> MachineInstr & MI = * I ; unsigned NumOperands = MI . getDesc ( ) . getNumOperands ( ) ; assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Op0 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ; MI . dropDebugNumber ( ) ; if ( KillsOp0 ) freeStackSlotAfter ( I , Op0 ) ; if ( KillsOp1 && Op0 != Op1 )


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: DefaultMemSIOperand ( SMLoc Loc ) { unsigned basereg = is64BitMode ( ) ? <STR_LIT> : ( is32BitMode ( ) ? <STR_LIT> : <STR_LIT> ) ; const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , basereg , <NUM_LIT> , <NUM_LIT> , Loc , Loc


<s> const MCExpr * Val = getImm ( ) ; return static_cast < const MCConstantExpr * > ( Val ) ->


<s> sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_mult ( SImode , sel , GEN_INT ( <NUM_LIT> ) , sel , <NUM_LIT> ) ; t_1 = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; break ; case V4HImode : t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_2 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_3 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , IOR , t_2 , t_3 , t_2 , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_2 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_mult ( SImode , sel , GEN_INT ( <NUM_LIT> ) , sel , <NUM_LIT> ) ; t_1 = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; break ; case V8QImode : sel = expand_simple_binop ( DImode , AND , sel , GEN_INT ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( DImode , IOR , sel , t_1 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( DImode , AND , sel , GEN_INT ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX


<s> regno2 = REGNO ( reg2 ) ; if ( ! GP_REG_P ( regno1 ) || ! GP_REG_P ( regno2 ) ) return false ; pair = ( <NUM_LIT> << regno1 ) | ( <NUM_LIT> << regno2 ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( match ) ; i

++ ) if ( pair == match [ i ] ) return true ;


<s> vmlal_s8 ( int16x8_t a , int8x8_t b , int8x8_t c ) { int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> static int ia64_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED ,

reg_class_t rclass , bool in ATTRIBUTE_UNUSED ) {


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>leTarget , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>beTarget


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar ( b ) ) , <NUM_LIT> )


<s> if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT


<s> return ( TrueOpDepth + FalseOpDepth + <NUM_LIT>


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_SaveList : CSR_SVR32_ColdCC_SaveList ) ; } return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList

) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ;


<s> initializeMVELaneInterleavingPass ( * PassRegistry :: getPassRegistry ( )


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( )


<s> Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo (


<s> printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) .

getImm ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> case <STR_LIT> : case <STR_LIT> : Target = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( - <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Target = LastInst -> getOperand ( <NUM_LIT> ) .


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TargetTriple , StringRef Cpu , StringRef FeatureString , const TargetMachine & TM , const TargetOptions & , CodeModel :: Model , CodeGenOpt :: Level ) : <ISA_LIT>GenSubtargetInfo

( TargetTriple , Cpu , FeatureString ) , FrameLowering ( initializeSubtargetDependencies ( Cpu , FeatureString ) ) , InstrInfo ( ) {


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: parseRegForInlineAsmConstraint ( const StringRef & C , MVT VT ) const { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const TargetRegisterClass * RC ; std :: string Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } if ( ! R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget -> isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> ==


<s> const DataLayout & DL = CurDAG -> getDataLayout ( ) ; const TargetLowering * TLI = getTargetLowering ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= - ( <NUM_LIT> << Scale ) && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) ==


<s> return ( __m256i ) __builtin_ia32_pmulld256_mask ( ( __v8si ) __A , ( __v8si )


<s> O << <STR_LIT> ; printMemReference ( MI ,


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { if ( get<ISA_LIT>Subtarget ( ) . hasVSX ( ) ) addPass ( create<ISA_LIT>VSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None


<s> bool <ISA_LIT>AddressTypePromotion :: runOnFunction ( Function & F ) { if ( ! EnableAddressTypePromotion || F . isDeclaration ( ) ) return false ; Func = & F ; ConsideredSExtType = Type :: getInt64Ty ( Func -> getContext ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << Func -> getName ( ) << '\n' ) ; Instructions SExtInsts


<s> return ( vector signed int ) __builtin_altivec_vupklsh (


<s> bool isUImm1 ( ) const { return isUImm < <NUM_LIT> > (


<s> static unsigned computeBytesPoppedByCalleeForSRet ( const <ISA_LIT>Subtarget * Subtarget , CallingConv :: ID CC , ImmutableCallSite * CS ) { if ( Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT ( ) ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast || CC == CallingConv

:: GHC || CC == CallingConv :: HiPE ) return <NUM_LIT> ;


<s> printSImmOperand < <NUM_LIT> > ( MI , OpNum


<s> switch ( operand . encoding ) { default : debug ( <STR_LIT> ) ; return true ; case ENCODING_REG : translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; CASE_ENCODING_RM : CASE_ENCODING_VSIB : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case


<s> static DecodeStatus DecodeTS1AMI32 ( MCInst & MI , uint64_t insn , uint64_t Address , const void *


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeGV ( const GlobalValue * GV , MVT VT ) { if ( VT != <STR_LIT> || GV -> isThreadLocal ( ) ) return <NUM_LIT> ; bool IsIndirect = Subtarget -> isGVIndirectSymbol ( GV ) ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( ! Subtarget -> isTargetMachO ( ) && IsThreadLocal ) return <NUM_LIT> ; bool IsPositionIndependent = isPositionIndependent ( ) ; if ( Subtarget -> useMovt ( * FuncInfo . MF ) && ( Subtarget -> isTargetMachO ( ) || ! IsPositionIndependent ) ) { unsigned Opc ; unsigned char TF = <NUM_LIT> ; if ( Subtarget -> isTargetMachO ( ) ) TF = <STR_LIT> ; if ( IsPositionIndependent ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { unsigned Align = DL . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT>


<s> return ( __mmask64 ) __builtin_ia32_kandndi ( ( __mmask64 ) __A , ( __mmask64 )


<s> if ( TARGET_LOONGSON_MMI && VECTOR_MODE_P ( mode )


<s> Relocator :: Result call ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { if ( pReloc . symInfo ( ) -> isWeak ( ) && pReloc . symInfo ( ) -> isUndef ( ) && ! pReloc . symInfo ( ) -> isDyn ( ) && ! ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) ) { pReloc . target ( ) = <NUM_LIT> ; return Relocator :: OK ; } Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: Address P = pReloc . place ( ) ; if ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) S = helper_get_PLT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: DWord X = S


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> Ret += <STR_LIT> ; MinStackAlignBits = <NUM_LIT> ; } else if ( FS . find ( <STR_LIT> ) != StringRef :: npos ) { Ret += <STR_LIT> ; MinStackAlignBits = <NUM_LIT> ; } else if ( FS . find ( <STR_LIT> ) != StringRef :: npos ) { Ret += <STR_LIT> ; MinStackAlignBits = <NUM_LIT> ; } if ( ! ABI . IsN64 ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ABI . IsN64 ( ) || ABI . IsN32 ( ) ) Ret += <STR_LIT> + llvm :: utostr ( std :: max ( <NUM_LIT>


<s> MachineInstr * LoopEnd , * LoopPhi , * LoopStart , * LoopDec ; if ( ! findLoopComponents ( ML , MRI , LoopStart , LoopPhi , LoopDec , LoopEnd ) ) return false ; if ( LoopDec != LoopEnd || LoopStart -> getOpcode ( ) != <STR_LIT> ) return false ; SmallVector < MachineInstr * , <NUM_LIT> > VCTPs ; for ( MachineBasicBlock * BB : ML -> blocks ( ) ) for ( MachineInstr & MI : * BB ) if ( isVCTP ( & MI ) ) VCTPs . push_back ( & MI ) ; if ( VCTPs . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * FirstVCTP = * VCTPs . begin ( ) ; for ( MachineInstr * VCTP : VCTPs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VCTP ) ; if ( VCTP -> getOpcode ( ) != FirstVCTP -> getOpcode ( ) || VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) != FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } Register CountReg = FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! CountReg . isVirtual ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * Phi = LookThroughCOPY ( MRI -> getVRegDef ( CountReg ) , MRI ) ; if ( ! Phi || Phi -> getOpcode ( ) != TargetOpcode :: PHI || Phi -> getNumOperands ( ) != <NUM_LIT> || ( Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) && Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CountReg = Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == ML -> getLoopLatch ( ) ? Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) : Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = LoopStart -> getParent ( ) ; MachineBasicBlock :: iterator InsertPt = MBB -> getFirstTerminator ( ) ; for ( MachineInstr & Use : MRI -> use_instructions ( LoopStart -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( ( InsertPt != MBB -> end ( ) && ! DT -> dominates ( & * InsertPt , & Use ) ) || ! DT -> dominates ( ML -> getHeader ( ) , Use . getParent ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstrBuilder MI = BuildMI ( * MBB , InsertPt , LoopStart -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add

( LoopStart -> getOperand ( <NUM_LIT> ) ) . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) . addReg ( CountReg ) ;


<s> OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE (


<s> bool ExtraLoadRequired = Subtarget . GVRequiresExtraLoad ( GV , getTargetMachine ( ) , false ) ; SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> ,


<s> return ( __m128i ) __builtin_ia32_psubsw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> bool <ISA_LIT>TargetLowering :: isCommutativeBinOp ( unsigned Opcode


<s> rtx_insn * seq , * insn ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_reg_rtx ( Pmode ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( <NUM_LIT> ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ; insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) )


<s> case 'e' : result = result * <NUM_LIT> + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * <NUM_LIT> + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * <NUM_LIT> + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = <NUM_LIT> ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * <NUM_LIT> + ( unsigned ) ( XWINT


<s> } return LPCC :: ICC_GT ; case <STR_LIT> : return LPCC :: ICC_UGT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_MI ; return LPCC :: ICC_LT ; case <STR_LIT> : return LPCC :: ICC_ULT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_MI ; } return LPCC :: ICC_LE ; case <STR_LIT> : return LPCC :: ICC_ULE ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_PL ; return LPCC :: ICC_GE ; case <STR_LIT> : return LPCC :: ICC_UGE ; case <STR_LIT> : return LPCC :: ICC_NE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; const TargetRegisterClass * RC ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; } ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOLoad , ScaleFactor , MMO ) ; if ( VTIsi1 ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , ResultReg , true , <NUM_LIT>


<s> char buf [ <NUM_LIT> ] ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; } if ( TARGET_PROFILE_KERNEL && crtl -> profile ) { gcc_assert ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) ; gcc_assert ( ! TARGET_32BIT ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; if ( DEFAULT_ABI != ABI_ELFv2 && cfun -> static_chain_decl != NULL ) { asm_fprintf ( file , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] , reg_names [ <NUM_LIT>


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } } bool isFP = Op1 . getSimpleValueType (


<s> static DecodeStatus decodeS16ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeSImmOperand < <NUM_LIT> > ( Inst , Imm


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT


<s> auto Prepare = [ & ] ( ) { AllocaAddr = CreateAllocaInst ( Builder , Bitcast -> getParent ( ) ) ; I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II )


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL3 = I -> getDebugLoc ( ) ; MachineInstr * MItest = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> )


, V1 , V2 , Mask , Subtarget , DAG ) ) return V ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass


<s> static void replaceFI ( MachineFunction & MF , MachineBasicBlock :: iterator II , MachineInstr & MI , const DebugLoc & dl , unsigned FIOperandNum , int Offset , Register FrameReg ) { MI . getOperand ( FIOperandNum ) .


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg (

regno , false ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO


<s> return __builtin_ia32_ucomisdgt ( ( __v2df ) __A , ( __v2df )


<s> if ( type && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ; else return words


<s> bool isLROk = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; bool isSPOk = isPCOk || isLROk || ( Opc == <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> ||


<s> if ( ! fpr_size && gpr_reg_num > cfun -> va_list_gpr_size ) { gpr_reg_num = cfun -> va_list_gpr_size ; if ( reg_size == <NUM_LIT> && ( first_reg_offset & <NUM_LIT> ) ) gpr_reg_num ++ ; } gpr_size = ( gpr_reg_num * reg_size + <NUM_LIT> ) & ~ <NUM_LIT> ; } else if ( fpr_size ) offset = - ( int ) ( next_cum . fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD - ( int ) ( GP_ARG_NUM_REG * reg_size ) ; if ( gpr_size + fpr_size ) { rtx reg_save_area = assign_stack_local ( BLKmode , gpr_size + fpr_size , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( reg_save_area ) == MEM ) ; reg_save_area = XEXP ( reg_save_area , <NUM_LIT> ) ; if ( GET_CODE ( reg_save_area ) == PLUS ) { gcc_assert ( XEXP ( reg_save_area , <NUM_LIT> ) == virtual_stack_vars_rtx ) ; gcc_assert ( GET_CODE ( XEXP ( reg_save_area , <NUM_LIT> ) ) == CONST_INT ) ; offset += INTVAL ( XEXP ( reg_save_area , <NUM_LIT> ) ) ; } else gcc_assert ( reg_save_area == virtual_stack_vars_rtx ) ; } cfun -> machine -> varargs_save_offset = offset ; save_area = plus_constant ( Pmode , virtual_stack_vars_rtx , offset ) ; } } else { first_reg_offset = next_cum . words ; save_area = crtl -> args . internal_arg_pointer ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( type ) , type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area , first_reg_offset * reg_size ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD )


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction


<s> switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : const TargetRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF ) ; SDLoc dl ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp ) ; return false


<s> int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) )

, Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ;


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI =


<s> bool MemDefsUses :: getUnderlyingObjects ( const MachineInstr & MI , SmallVectorImpl < ValueType > & Objects ) const { if ( ! MI . hasOneMemOperand ( ) || ( ! ( * MI . memoperands_begin ( ) ) -> getValue ( ) && ! ( * MI . memoperands_begin ( ) ) -> getPseudoValue ( ) ) ) return false ; if ( const PseudoSourceValue * PSV = ( * MI . memoperands_begin ( ) ) -> getPseudoValue ( ) ) { if ( ! PSV -> isAliased ( MFI ) ) return false ; Objects . push_back ( PSV ) ; return true ; } const Value * V = ( * MI . memoperands_begin ( ) ) -> getValue ( ) ; SmallVector < Value * ,


<s> unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset


<s> bool <ISA_LIT>InstPrinter :: isV9 ( ) const


<s> initializeAnnotationsInferencePass ( Registry


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT>


<s> unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } return true ; } return false


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ,


<s> if ( Op0 . getOpcode ( ) != <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto BuildPSADBW = [ & ] ( SDValue Op0 , SDValue Op1 ) { SDValue Sad = createPSADBW ( DAG , Op0 , Op1 , DL , Subtarget ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , Sad . getValueSizeInBits ( ) / <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) >= ResVT . getSizeInBits ( ) ) Sad = DAG . getNode ( <STR_LIT> , DL , ResVT , Sad ) ; else Sad = DAG . getNode ( <STR_LIT> , DL , VT , Sad ) ; if ( VT . getSizeInBits ( ) > ResVT . getSizeInBits ( ) ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; Sad = DAG . getNode ( <STR_LIT> , DL , VT , Zero , Sad , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } return Sad ; } ; SDValue SadOp0 , SadOp1 ; if ( ! detectZextAbsDiff ( Op0 , SadOp0 , SadOp1 ) ) return SDValue ( ) ; Op0 = BuildPSADBW ( SadOp0 , SadOp1 ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && detectZextAbsDiff ( Op1 , SadOp0 , SadOp1


<s> return ( __mmask8 ) __builtin_ia32_ucmpw128_mask ( ( __v8hi ) __X , (


<s> static MCDisassembler * create<ISA_LIT>elDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext &


<s> bool isMem ( ) const override { return Kind


<s> inline SDValue getImm ( const SDNode *


<s> assert ( PI < <STR_LIT> :: NUM_PERSONALITY_INDEX && <STR_LIT> ) ; EmitByte ( <STR_LIT> :: EHT_COMPACT |


<s> THUMB_REGNO_MODE_OK_FOR_BASE_P ( REGNO ( X ) , MODE ) ( TARGET_THUMB \ ? THUMB_REG_MODE_OK_FOR_BASE_P ( X , MODE ) \ : ARM_REG_OK_FOR_BASE_P ( X ) ) ( TARGET_THUMB \ ? THUMB_REG_OK_FOR_INDEX_P ( X ) \ : ARM_REG_OK_FOR_INDEX_P ( X ) ) ( GET_CODE ( X ) == REG && ARM_REG_OK_FOR_BASE_P ( X ) ) ( GET_CODE ( X ) == REG && ARM_REG_OK_FOR_INDEX_P ( X ) ) do \ { \ HOST_WIDE_INT range ; \ enum rtx_code code = GET_CODE ( INDEX ) ; \ \ if ( TARGET_HARD_FLOAT && GET_MODE_CLASS ( MODE ) == MODE_FLOAT ) \ { \ if ( code == CONST_INT && INTVAL ( INDEX ) < <NUM_LIT> \ && INTVAL ( INDEX ) > - <NUM_LIT> \ && ( INTVAL ( INDEX ) & <NUM_LIT> ) == <NUM_LIT> ) \ goto LABEL ; \ } \ else \ { \ if ( ARM_INDEX_REGISTER_RTX_P ( INDEX ) \ && GET_MODE_SIZE ( MODE ) <= <NUM_LIT> ) \ goto LABEL ; \ if ( GET_MODE_SIZE ( MODE ) <= <NUM_LIT> && code == MULT \ && ( ! arm_arch4 || ( MODE ) != HImode ) ) \ { \ rtx xiop0 = XEXP ( INDEX , <NUM_LIT> ) ; \ rtx xiop1 = XEXP ( INDEX , <NUM_LIT> ) ; \ if ( ARM_INDEX_REGISTER_RTX_P ( xiop0 ) \ && power_of_two_operand ( xiop1 , SImode ) ) \ goto LABEL ; \ if ( ARM_INDEX_REGISTER_RTX_P ( xiop1 ) \ && power_of_two_operand ( xiop0 , SImode ) ) \ goto LABEL ; \ } \ if ( GET_MODE_SIZE ( MODE ) <= <NUM_LIT> \ && ( code == LSHIFTRT || code == ASHIFTRT \ || code == ASHIFT || code == ROTATERT ) \ && ( ! arm_arch4 || ( MODE ) != HImode ) ) \ { \ rtx op = XEXP ( INDEX , <NUM_LIT> ) ; \ if ( ARM_INDEX_REGISTER_RTX_P ( XEXP ( INDEX , <NUM_LIT> ) ) \ && GET_CODE ( op ) == CONST_INT && INTVAL ( op ) > <NUM_LIT> \ && INTVAL ( op ) <= <NUM_LIT> ) \ goto LABEL ; \ } \ \ range = ( (

MODE ) == HImode || ( MODE ) == QImode ) \ ? ( arm_arch4 ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; \ if ( code == CONST_INT && INTVAL ( INDEX ) < range \ && INTVAL ( INDEX ) > - range ) \ goto LABEL ; \ } \ }


<s> else stmt_cost = ix86_cost -> add ; break ; case TRUNC_DIV_EXPR : case CEIL_DIV_EXPR : case FLOOR_DIV_EXPR : case ROUND_DIV_EXPR : case TRUNC_MOD_EXPR : case CEIL_MOD_EXPR : case FLOOR_MOD_EXPR : case RDIV_EXPR : case ROUND_MOD_EXPR : case EXACT_DIV_EXPR : stmt_cost = ix86_division_cost ( ix86_cost , mode ) ; break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case ABSU_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } combined_fn cfn ; if ( ( kind == vector_stmt || kind == scalar_stmt ) && stmt_info && stmt_info -> stmt && ( cfn = gimple_call_combined_fn ( stmt_info -> stmt ) ) != CFN_LAST ) switch ( cfn ) { case CFN_FMA : stmt_cost = ix86_vec_cost ( mode , mode == SFmode ? ix86_cost -> fmass : ix86_cost -> fmasd ) ; break ; default : break ; } if ( ( kind == vec_construct || kind == vec_to_scalar ) && stmt_info && ( STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type || STMT_VINFO_TYPE ( stmt_info ) == store_vec_info_type ) && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) { stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost *= ( TYPE_VECTOR_SUBPARTS ( vectype ) + <NUM_LIT> ) ; } if ( stmt_cost == - <NUM_LIT> ) stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= <NUM_LIT> ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS || TARGET_TREMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ; if ( lhs_op && TREE_CODE ( TREE_TYPE ( lhs_op ) ) == INTEGER_TYPE ) retval = ( retval * <NUM_LIT> ) / <NUM_LIT> ; } cost [ where ] += retval ; return


<s> case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isImplicit ( ) ) continue ; RegList . push_back ( MO . getReg ( ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand (


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Ra , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> void printxmmwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , DImode , addr , i ) ; emit_move_insn ( mem , reg ) ; } } else val_reg = force_reg ( SImode , val_exp ) ; reg = ( use_strd_p ? gen_lowpart ( SImode , val_reg ) : val_reg ) ; for ( ; ( i + <NUM_LIT> <= length ) ; i += <NUM_LIT> ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; } if ( unaligned_access && i > <NUM_LIT> && ( i + <NUM_LIT> ) == length ) { addr = plus_constant ( Pmode , dst , i - <NUM_LIT> ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i - <NUM_LIT> ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; return true ; } if ( i + <NUM_LIT> <= length ) { reg = gen_lowpart ( HImode , val_reg ) ; addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , HImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( Lower . getExpr ( MI -> getOperand ( <NUM_LIT> ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addExpr ( Lower . getExpr ( MI -> getOperand ( <NUM_LIT> ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> ## <NUM_LIT> : LoweredMI = lowerRILow ( MI , <STR_LIT> )


<s> case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getTargetConstant ( x86cc , DL , <STR_LIT> ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Ins ) , DL , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getTargetConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT>


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; case <STR_LIT> : case <STR_LIT> : case


<s> return isMem ( ) && isa < MCConstantExpr > ( getMemOff (


<s> a = ( __vector signed char ) vec_splats ( __m1 ) ; b = ( __vector signed char ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ; return ( __m64 ) ( ( __vector long long


<s> DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( (


<s> return ( uint16x4_t ) __builtin_neon_vreinterpretv4hiv8qi (


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) { if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleAsInsertPS ( Op , V1 , V2 , Mask , DAG ) ) return V ; if ( ! isSingleSHUFPSMask ( Mask ) ) if ( SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BlendPerm ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG

. getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ;


<s> return ( __m256i ) __builtin_ia32_pternlogd256_mask ( ( __v8si ) __A , ( __v8si ) __B , ( __v8si ) __C , ( unsigned char ) __imm , ( __mmask8


<s> bool has<ISA_LIT>16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool hasNo<ISA_LIT>16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex )


<s> bool <ISA_LIT>SpeculationHardening :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) return false ; MisspeculatingTaintReg = <STR_LIT> ; MisspeculatingTaintReg32Bit = <STR_LIT> ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; RegsNeedingCSDBBeforeUse . resize ( TRI -> getNumRegs ( ) ) ; RegsAlreadyMasked . resize ( TRI -> getNumRegs ( ) ) ; UseControlFlowSpeculationBarrier = functionUsesHardeningRegister ( MF ) ; bool Modified = false ; if ( HardenLoads ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; for ( auto & MBB : MF ) Modified |= slhLoads ( MBB ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > EntryBlocks ; EntryBlocks . push_back ( & MF . front ( ) ) ; for ( const LandingPadInfo & LPI : MF . getLandingPads ( ) ) EntryBlocks . push_back ( LPI . LandingPadBlock ) ; for ( auto Entry : EntryBlocks ) insertSPToRegTaintPropagation ( Entry , Entry -> SkipPHIsLabelsAndDebug ( Entry -> begin ( ) ) ) ; for ( auto & MBB : MF ) Modified |= instrumentControlFlow ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler ::


<s> gcc_assert ( n == <NUM_LIT> ) ; timode_p =


<s> bool <ISA_LIT>InstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { bool Changed = onlyFoldImmediate ( UseMI , DefMI , Reg ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) DefMI . eraseFromParent ( ) ; return Changed


<s> if ( __builtin_expect ( status , _HTM_TRANSACTIONAL ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> else if ( ! TARGET_FPU && register_operand ( src , SFmode ) ) return <NUM_LIT> ; else if ( ! TARGET_FPU && TARGET_ARCH64 && register_operand ( src , DFmode ) ) return <NUM_LIT> ; else if ( return_p && TARGET_V9 && ! epilogue_renumber ( & pat , <NUM_LIT> ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) return <NUM_LIT> ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) && arith_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) ) return <NUM_LIT> ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) && arith_double_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) ) return <NUM_LIT> ; else if ( GET_CODE ( src ) == LO_SUM && ! TARGET_CM_MEDMID && ( ( register_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) && immediate_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) ) || (

TARGET_ARCH64 && register_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) && immediate_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) ) ) ) return <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SPFI ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MPI , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get


<s> if ( value == <NUM_LIT> ) { if ( currently_expanding_to_rtl ) { emit_insn ( gen_cmpgtsi_t ( force_reg ( SImode , CONST0_RTX ( SImode ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_mov_neg_si_t ( operands [ <NUM_LIT> ] , get_t_reg_rtx ( ) ) ) ; return true ; } emit_insn ( gen_ashrsi2_31 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } else if ( value >= <NUM_LIT> && value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashrsi2_16 ( wrk , operands [ <NUM_LIT> ] ) ) ; value -= <NUM_LIT> ; while ( value -- ) gen_ashift ( ASHIFTRT , <NUM_LIT> , wrk ) ; emit_move_insn ( operands [ <NUM_LIT> ] , wrk ) ; return true ; } else if ( value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode ) ; emit_move_insn ( wrk , operands [ <NUM_LIT> ] ) ; while ( value -- ) gen_ashift ( ASHIFTRT , <NUM_LIT> , wrk ) ; emit_move_insn ( operands [ <NUM_LIT> ]


<s> int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg ,


<s> HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ?


<s> assert ( ( N -> getNumValues ( ) <= Res -> getNumValues ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = N -> getNumValues ( ) ; I !=

E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ;


<s> bool disableMadd4 ( ) const { return DisableMadd4


<s> if ( ! CB -> getType ( ) -> isVoidTy ( ) ) Types . push_back ( CB -> getType ( ) ) ; auto IsSimpleTy = [ ] ( Type * Ty ) { return ! Ty -> isVectorTy ( ) && ! Ty -> isAggregateType ( ) ; } ; if ( all_of ( Types , IsSimpleTy ) ) continue ; if ( Function * NestedCallee = CB -> getCalledFunction ( ) ) { if ( NestedCallee -> isIntrinsic ( ) ) continue ; if ( ! areTypesABICompatible ( Caller , NestedCallee , Types ) ) return false ; } else { return false ; } } } return true


<s> if ( MFI . getStackID ( Info . getFrameIdx ( ) ) == TargetStackID :: SVEVector ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Offset = StackOffset :: getScalable ( MFI . getObjectOffset ( Info . getFrameIdx ( ) ) ) - StackOffset :: getFixed ( AFI -> getCalleeSavedStackSize ( MFI ) ) ; } else { Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( Info . getFrameIdx ( ) ) - getOffsetOfLocalArea ( ) ) ; } unsigned CFIIndex = MF . addFrameInst ( createCfaOffset (


<s> unsigned NewOpc = <NUM_LIT> ; if ( ( N0 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N0 ) ) && ( N1 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N1 ) ) ) { NewOpc = <STR_LIT> ; } else if ( ( N0 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N0 ) ) && ( N1 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N1 ) ) ) { NewOpc = <STR_LIT> ; } else if ( VT . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) { return SDValue ( ) ; } else { return Op ; } DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Op0 = SkipExtension ( N0 , DAG ) ; SDValue Op1 = SkipExtension ( N1 , DAG ) ; assert ( Op0 . getValueType ( ) . is64BitVector ( ) && Op1 . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( NewOpc , DL


<s> void <ISA_LIT>TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) F -> addParamAttr ( <NUM_LIT> , Attribute ::


<s> if ( rotr32 ( ~ <NUM_LIT> , RotAmt ) & Arg ) return - <NUM_LIT> ; return rotl32 ( Arg , RotAmt ) | ( ( RotAmt >>


<s> <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const MCExpr * OffsetExpr ; int64_t OffsetVal ; SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( Parser . parseExpression ( OffsetExpr ) || ! OffsetExpr -> evaluateAsAbsolute ( OffsetVal , getStreamer ( ) ) ) { reportParseError ( ExprLoc


<s> inline SDValue getI64Imm ( uint64_t Imm , const


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS4Operand ( const MachineInstr * MI ,


<s> assert ( ITState . CurPosition > <NUM_LIT> ) ; ITState . CurPosition -- ; unsigned TZ = countTrailingZeros ( ITState .


<s> void <ISA_LIT>InstPrinter :: printU5ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) .


<s> bool <ISA_LIT>TTIImpl :: useReductionIntrinsic ( unsigned Opcode , Type * Ty , TTI :: ReductionFlags Flags ) const { auto * VTy = cast < VectorType > ( Ty ) ; unsigned ScalarBits = Ty -> getScalarSizeInBits ( ) ; switch ( Opcode ) { case Instruction :: FAdd : case Instruction :: FMul


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset =


<s> gcc_assert ( cfun -> machine -> frame . laid_out ) ; return ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL || ( aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF && known_ge ( cfun -> machine -> frame . reg_offset [ LR_REGNUM


<s> void <ISA_LIT>InstPrinter :: printComplexRotationOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; O << <STR_LIT> << ( Val * Angle ) +


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> return ( uint8x16_t ) __builtin_neon_vbslv16qi ( ( int8x16_t ) __a , (


<s> if ( CallerF . getReturnType ( ) -> is<ISA_LIT>_FP80Ty ( ) && ! RetTy -> is<ISA_LIT>_FP80Ty ( ) ) return false ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; bool IsCalleeWin64 = Subtarget . isCallingConvWin64 ( CalleeCC ) ; bool IsCallerWin64 = Subtarget . isCallingConvWin64 ( CallerCC ) ; if ( IsCalleeWin64 != IsCallerWin64 ) return false ; if ( DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { if ( canGuaranteeTCO ( CalleeCC ) && CCMatch ) return true ; return false ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { if ( IsCalleeWin64 || IsCallerWin64 ) return false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , MF , RVLocs , C ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT> , RetCC_<ISA_LIT> ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeCallOperands ( Outs ,


<s> else if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( GP0Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp << <NUM_LIT> ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( GP0Regs [


<s> CommentString = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; WeakRefDirective = <STR_LIT> ; PrivateGlobalPrefix =


<s> if ( op == virtual_incoming_args_rtx || op == virtual_stack_vars_rtx || op == virtual_stack_dynamic_rtx || op == virtual_outgoing_args_rtx || op


<s> return Kind == k_VectorIndex && VectorIndex . Val


<s> if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD ) break ; if ( usesRegister ( p , CurInst ) == RU_Write ) { return CurInst ; } InstrDistance += TSM . computeInstrLatency ( & * CurInst ) ; Found = getPreviousInstr ( CurInst , MBB


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthVectorMLoadToSVE ( SDValue Op , SelectionDAG & DAG ) const { auto Load = cast < MaskedLoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SDValue Mask = convertFixedMaskToScalableVector ( Load -> getMask ( ) , DAG ) ; SDValue PassThru ; bool IsPassThruZeroOrUndef = false ; if ( Load -> getPassThru ( ) -> isUndef ( ) ) { PassThru = DAG . getUNDEF ( ContainerVT ) ; IsPassThruZeroOrUndef = true ; } else { if ( ContainerVT . isInteger ( ) ) PassThru = DAG . getConstant ( <NUM_LIT> ,


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( x , y


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case DFmode :


<s> if ( isExecuteOnlyFunction ( GO , SK , TM ) ) SK = SectionKind :: getExecuteOnly ( ) ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , SK


<s> if ( Subtarget -> isThumb ( ) ) O << <STR_LIT> ; if ( Subtarget -> isTargetELF ( ) ) { std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString != <STR_LIT> ) O << <STR_LIT> << CPUString << '\n' ; if ( Subtarget -> hasVFP2 ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( ! UnsafeFPMath ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( FiniteOnlyFPMath ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; else O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( Subtarget -> isAAPCS_ABI ( ) && FloatABIType == FloatABI :: Hard ) O <<


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options

, RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> <ISA_LIT>GenericDisassembler :: <ISA_LIT>GenericDisassembler ( DisassemblerMode mode ) : MCDisassembler ( ) , fMode ( mode


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ! isInt < <NUM_LIT> > ( ImmValue ) ; } return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm


<s> HOST_WIDE_INT offset ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? <NUM_LIT> : - info -> total_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { offset = info -> push_p ? <NUM_LIT> : - info -> total_size ; if ( FRAME_GROWS_DOWNWARD ) offset += info -> fixed_size + info -> vars_size + info -> parm_size ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = FRAME_GROWS_DOWNWARD ? info -> fixed_size + info -> vars_size + info -> parm_size : <NUM_LIT> ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = info -> total_size ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? info -> total_size : <NUM_LIT> ; else if ( from == RS6000_PIC_OFFSET_TABLE_REGNUM ) offset = <NUM_LIT> ; else gcc_unreachable ( ) ; return offset


<s> if ( satisfies_constraint_L ( addis_value ) ) { fuse_ops [ <NUM_LIT> ] = addis_value ; addis_str = <STR_LIT> ; } else if ( GET_CODE ( addis_value ) == PLUS ) { rtx op0 = XEXP ( addis_value , <NUM_LIT> ) ; rtx op1 = XEXP ( addis_value , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) && satisfies_constraint_L ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = op0 ; fuse_ops [ <NUM_LIT> ] = op1 ; addis_str = <STR_LIT> ; } } else if ( GET_CODE ( addis_value ) == HIGH ) { rtx value = XEXP ( addis_value , <NUM_LIT> ) ; if ( GET_CODE ( value ) == UNSPEC && XINT ( value , <NUM_LIT> ) == UNSPEC_TOCREL ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP (


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( )


<s> DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( const auto & Info : CSI ) { Register Reg = Info . getReg ( ) ; unsigned NewReg ; if ( static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) -> regNeedsCFI ( Reg , NewReg ) ) Reg = NewReg ; else continue ; StackOffset Offset ; if ( MFI . getStackID ( Info . getFrameIdx ( ) ) == TargetStackID


<s> int named_parm_regs , anon_parm_regs ; named_parm_regs = ( ROUND_REG ( * ca , mode ) + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes ( type ) ) :

ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) && Subtarget . isPICStyleGOT

( ) ) return MachineJumpTableInfo :: EK_Custom32 ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; bool IsAdd = N -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsAdd || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > PostShuffleMask ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG ,

Subtarget , IsAdd , PostShuffleMask ) ) {


<s> return ( ( vec_double2 ) ( si_rotqby ( ( qword ) ( a ) , si_from_int ( count ) )


<s> MachineInstrBuilder MIB ; unsigned Opc = ( ( FrameSize <= <NUM_LIT> ) && ! SaveS2 ) ? <STR_LIT> : <STR_LIT> ; if ( ! isUInt < <NUM_LIT> > ( FrameSize ) ) { unsigned Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; FrameSize = Base ; if ( isInt < <NUM_LIT> > ( Remainder ) ) BuildAddiuSpImm ( MBB , I , Remainder ) ; else adjustStackPtrBig ( SP , Remainder , MBB , I , <STR_LIT> , <STR_LIT> ) ; } MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; addSaveRestoreRegs ( MIB , CSI , RegState ::


<s> copyByValRegs ( SDValue Chain , DebugLoc DL , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , const <STR_LIT> & Flags , SmallVectorImpl < SDValue > & InVals , const Argument * FuncArg , const <ISA_LIT>CC & CC , const ByValArgInfo & ByVal ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned RegAreaSize = ByVal . NumRegs * CC . regSize ( ) ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; if ( RegAreaSize ) FrameObjOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( ( CC . numIntArgRegs ( ) - ByVal . FirstIdx ) * CC . regSize ( ) ) ; else FrameObjOffset = ByVal . Address ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; EVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = CC . intArgRegs ( ) [ ByVal . FirstIdx + I ] ; unsigned VReg = AddLiveIn ( MF , ArgReg , RC


<s> } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) .


<s> SDValue getGatherScatterScale ( SDValue Op ) { if ( auto * N = dyn_cast < MaskedGatherScatterSDNode > ( Op . getNode ( ) ) ) return N -> getScale ( ) ; if ( auto * N = dyn_cast < VPGatherScatterSDNode > ( Op .


<s> } } return false ; } switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrByteSize , PtrByteSize ) ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; const unsigned Offset = State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , <NUM_LIT> ) ; unsigned FReg = State . AllocateReg ( FPR ) ; if ( FReg ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , FReg , LocVT , LocInfo ) ) ; for ( unsigned I = <NUM_LIT> ; I < StoreSize ; I += PtrByteSize ) { if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { assert ( FReg && <STR_LIT> ) ; if ( State . isVarArg ( ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; } } else { State . addLoc ( FReg ? CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) : CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; break ; } } return false


<s> static void arm_unwind_emit ( FILE * asm_out_file , rtx insn ) { rtx pat ; if ( ! ARM_EABI_UNWIND_TABLES ) return ; if ( GET_CODE ( insn ) == NOTE || ! RTX_FRAME_RELATED_P ( insn ) ) return ; pat = find_reg_note ( insn , REG_FRAME_RELATED_EXPR


<s> unsigned Reg ; SMLoc SRegLoc , ERegLoc ; if ( ParseRegister ( Reg , SRegLoc , ERegLoc ) ) { Parser . eatToEndOfStatement ( ) ; Error ( SRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Parser . eatToEndOfStatement ( ) ; Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; if ( ! RegisterReqs . insert ( std :: make_pair ( Name , Reg ) ) . second ) { Error ( SRegLoc , <STR_LIT> + Name +