<s> if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset5 = State . AllocateStack ( <NUM_LIT> , <NUM_LIT>


<s> } if ( VT == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && ( CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT || CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . isFatPointer ( ) ) ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; const auto * CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; if ( LHS . getValueType ( ) . isFatPointer ( ) ) { LHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , LHS ) ; RHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , RHS ) ; } SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS ,


<s> MCInst CInst ; bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; if ( Res ) ++ <ISA_LIT>NumInstrsCompressed ; S . EmitInstruction ( ( Res ? CInst : Inst )


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O <<


<s> if ( ! ForceImmediate && parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc ( ) ,


<s> if ( UseMI && UseMI -> isImplicitDef ( ) ) { TailAgnostic = true ; if ( UsesMaskPolicy ) MaskAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) TailAgnostic = true ; } <STR_LIT> VLMul = <STR_LIT> ( TSFlags ) ; unsigned Log2SEW = MI . getOperand ( getSEWOpNum ( MI ) ) . getImm ( ) ; bool MaskRegOp = Log2SEW == <NUM_LIT> ; unsigned SEW = Log2SEW ? <NUM_LIT> << Log2SEW : <NUM_LIT> ; assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; bool StoreOp = MI . getNumExplicitDefs ( ) == <NUM_LIT> ; bool ScalarMovOp = isScalarMoveInstr ( MI ) ; if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ; if ( VLOp . isImm ( ) ) { int64_t Imm = VLOp . getImm ( ) ; if ( Imm == <STR_LIT> ) InstrInfo . setAVLReg ( <STR_LIT> ) ; else InstrInfo . setAVLImm ( Imm )


<s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; MVT EltVT = N . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; if ( ! ValidateImm ( SplatImm ) ) return false ; SplatVal = DAG . getTargetConstant ( SplatImm , SDLoc


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { auto * Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Load -> getChain ( ) } ,


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> bool hasStdExtZkne ( ) const { return HasStdExtZkne


<s> static DecodeStatus DecodeGPCRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return


<s> } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs


<s> if ( CONST_INT_P ( vl ) && ! satisfies_constraint_K ( vl ) ) return force_reg (


<s> } if ( ! LocVT . isVector ( ) && ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR16s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR32s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s ) ; else if ( ValVT . isVector ( ) ) { const TargetRegisterClass * RC = TLI . getRegClassFor ( ValVT ) ; if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) { Reg = State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( ArgVRs ) ; } } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM2s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM4s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM8s ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ! Reg ) { if ( IsRet ) return true ; LocInfo = CCValAssign :: Indirect ; Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = XLenVT ; } } else Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , Align ( XLen / <NUM_LIT> ) ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc (


<s> static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <STR_LIT> ; return RegNo ==


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , Subtarget . isRV64

( ) ? RetCC_<ISA_LIT>64 : RetCC_<ISA_LIT>32 ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I


<s> if ( RegNo > sizeof ( GPRDecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP (


<s> <ISA_LIT>MakeCompressibleOpt ( ) : MachineFunctionPass


<s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasStdExtV ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( )


<s> for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; codes [ i ] . value = trunc_int_for_mode ( codes [ i ] . value , mode ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } } riscv_emit_set ( dest , x


<s> MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc


<s> else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT> , S , Tok . getLoc ( ) ) ; else if ( Tok . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) op = <ISA_LIT>Operand :: createReg ( <ISA_LIT>Operand :: PCRReg , <STR_LIT>


<s> ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDLoc DL ( Op ) ; SDValue Val = DAG . getNode ( MaskOpc , DL , ContainerVT , Op1 , Op2 , VL ) ; if ( ! IsFixed ) return Val ; return convertFromScalableVector ( VT , Val , DAG


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) )


<s> int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> void vector_infos_manager :: create_bitmap_vectors ( void ) { vector_antic = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_transp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_comp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avin = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avout = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_kill = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; bitmap_vector_ones ( vector_transp , last_basic_block_for_fn ( cfun ) ) ; bitmap_vector_clear ( vector_antic , last_basic_block_for_fn


<s> if ( N . getOpcode ( ) != <STR_LIT> || ! N . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; SplatVal = N . getOperand


<s> else add_vundef_operand ( mask_mode ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx op2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( ! insn_operand_matches ( icode , opno + <NUM_LIT> , op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! insn_operand_matches ( icode , opno + <NUM_LIT> , op2 ) ) { if ( VECTOR_MODE_P ( GET_MODE ( op2 ) ) ) op2 = force_reg ( mode , op2 ) ; else op2 = force_reg ( GET_MODE_INNER ( mode ) , op2 ) ; } rtx comparison = gen_rtx_fmt_ee ( rcode , mask_mode , op1 , op2 ) ; if ( ! VECTOR_MODE_P ( GET_MODE ( op2 ) ) ) comparison = gen_rtx_fmt_ee ( rcode , mask_mode

, op1 , gen_rtx_VEC_DUPLICATE ( mode , op2 ) ) ;


<s> bool hasStdExtZvfh ( ) const { return


<s> set_new_first_and_last_insn ( NULL , NULL ) ; machine_mode mode ; FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_INT ) \ { \ if ( riscv_v_ext_vector_mode_p ( mode ) ) \ { \ rtx_insn * insn ; \ rtx src ; \ scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; \ \ start_sequence ( ) ; \ rtx addr = gen_reg_rtx ( Pmode ) ; \ rtx mem = gen_rtx_MEM ( inner_mode , addr ) ; \ expand_vector_broadcast ( mode , mem ) ; \ insn = get_last_insn ( ) ; \ src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; \ ASSERT_TRUE ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) ; \ ASSERT_TRUE ( \ rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; \ end_sequence ( ) ; \

\ start_sequence ( ) ; \ rtx reg = gen_reg_rtx ( inner_mode ) ; \ expand_vector_broadcast ( mode , reg ) ; \ insn = get_last_insn ( ) ; \ src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; \ ASSERT_TRUE ( REG_P ( XEXP ( src , <NUM_LIT> ) ) ) ; \ ASSERT_TRUE ( \ rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; \ end_sequence ( ) ; \ }


<s> return VPLegalization ( VPLegalization :: Legal , VPLegalization :: Legal


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo (


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS ,


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t


<s> unsigned MaskIdx = Log2_64 ( ShAmt ) ; if ( MaskIdx >= array_lengthof ( BitmanipMasks ) ) return None ; auto Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto ExpMask = BitmanipMasks [ MaskIdx ] & maskTrailingOnes < uint64_t > ( Width ) ; bool SHLExpMask = IsSHL ; if ( ! Mask ) { if ( Src . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { Mask = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SHLExpMask = !


<s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex (


<s> if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t


<s> if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple ::

riscv64 ) addPass ( create<ISA_LIT>SExtWRemovalPass ( ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectLoopDecrement ( SDValue LoopDecrement ) { return ( LoopDecrement -> getOpcode ( ) == <STR_LIT> && LoopDecrement -> getConstantOperandVal (


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; if ( shouldEnableVectorUnit ( MF ) ) { BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( )


<s> IntegerTypes = <STR_LIT> ; } else { IntegerTypes = <STR_LIT> ; } StringRef CapTypes = <STR_LIT> ; StringRef PurecapOptions = <STR_LIT> ; if ( FS . contains ( <STR_LIT> ) ) { if ( TT . isArch64Bit ( ) ) CapTypes = <STR_LIT> ; else CapTypes = <STR_LIT> ; <STR_LIT> ABI = <STR_LIT> ( Options . MCOptions . getABIName ( ) ) ; if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) PurecapOptions = <STR_LIT> ; } return ( <STR_LIT> + CapTypes + IntegerTypes + <STR_LIT>


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> )


<s> return ( tune_info -> memory_cost + memory_move_secondary_cost ( mode , rclass , in


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , getNonLibcallCSI ( CSI ) . size ( ) ) ; for ( const auto & Entry : CSI ) { int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RealStackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF


<s> auto & RAB = static_cast < <ISA_LIT>AsmBackend & > ( Layout -> getAssembler ( ) . getBackend ( ) ) ; if ( RAB . willForceRelocations ( ) ) return false ; MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsValue ( AUIPCLoc , * Layout ) ) return false ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE || findAssociatedFragment ( ) != AUIPCSRE -> findAssociatedFragment ( ) ) return false ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; if ( ! AUIPCSymbol ) return false ; const MCFixup * TargetFixup = getPCRelHiFixup (


<s> APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ; if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( )


<s> int getEhDataRegFI ( unsigned Reg ) const {


<s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGMask ( SDNode * Node , unsigned IntNo , bool IsStrided ) { SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( MaskedOff ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } else { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg (

getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ;


<s> emit_insn ( riscv_got_load_tls_gd ( a0 , sym ) ) ; insn = emit_call_insn ( gen_call_value ( result , func , const0_rtx , NULL ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return


<s> if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) { if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , <NUM_LIT> ) ) ) ) continue ; } if ( REG_N_REFS ( regno ) < <NUM_LIT> ) continue ; m -> get_or_insert ( regno


<s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ; } return Val


<s> assert ( ContainerVT . isScalableVector ( ) && <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue VL = VecVT . isFixedLengthVector ( ) ? DAG . getConstant ( VecVT . getVectorNumElements ( ) , DL , XLenVT ) : DAG . getTargetConstant ( <STR_LIT>


<s> return new <ISA_LIT>ExpandAtomicPseudo (


<s> builtin_types [ type ] . scalar_ptr = build_pointer_type ( eltype ) ; builtin_types [ type ] . scalar_const_ptr = build_const_pointer ( eltype ) ; if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return ; tree vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) <= <NUM_LIT> && known_eq ( tree_to_poly_uint64 ( TYPE_SIZE ( vectype ) ) , GET_MODE_BITSIZE ( mode ) ) ) ; vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = <NUM_LIT> ; TYPE_INDIVISIBLE_P ( vectype ) = <NUM_LIT> ; add_vector_type_attribute ( vectype , vector_types [ type ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ type ] =


<s> switch ( Opcode ) { default : break ; case <STR_LIT> : return true ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool isToken ( ) const override { return Kind


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm - <NUM_LIT> ) && VK


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>64Target


<s> void setLowSavedGPR ( unsigned Reg ) { LowSavedGPR =


<s> bool hasStdExtZksed ( ) const { return HasStdExtZksed


<s> <STR_LIT> FRM = <STR_LIT> ( SE -> getSymbol ( ) . getName ( ) ) ; assert ( FRM != <STR_LIT> && <STR_LIT>


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr


<s> unsigned RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : return isIntN ( <NUM_LIT> , SignExtend64 ( BrOffset +


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && ( Imm == <NUM_LIT>

) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t StackAlign = getStackAlignment ( ) ; if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI .


<s> static bool reg_available_p ( const insn_info * insn , const vector_insn_info & info ) { if ( info . has_avl_reg ( ) && ! info . get_avl_source ( ) ) return false ; insn_info * def_insn = info . get_avl_source ( ) -> insn ( ) ; if ( def_insn -> bb ( ) == insn -> bb ( ) ) return before_p ( def_insn


<s> unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr

:: VK_<ISA_LIT>_CAPTAB_PCREL_HI , SecondOpcode , IDLoc , Out ) ;


<s> return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT>


<s> FeatureBitStack . push_back ( getSTI ( ) . getFeatureBits ( )


<s> uint64_t Nop32Count = Count / <NUM_LIT> ; for ( uint64_t i = Nop32Count ; i != <NUM_LIT> ; -- i ) OW -> write32 ( <NUM_LIT> ) ; if ( HasStdExtC ) { uint64_t Nop16Count = ( Count - Nop32Count * <NUM_LIT> ) / <NUM_LIT> ; for ( uint64_t i = Nop16Count ; i != <NUM_LIT> ; -- i


<s> bool <ISA_LIT>InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( )


<s> static const struct riscv_tune_info * riscv_parse_tune ( const char * tune_string ) { const riscv_cpu_info * cpu = riscv_find_cpu ( tune_string ) ; if ( cpu ) tune_string = cpu -> tune ; for ( unsigned i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_tune_info_table ) ; i ++ ) if ( strcmp

( riscv_tune_info_table [ i ] . name , tune_string ) == <NUM_LIT> ) return riscv_tune_info_table + i ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>CleanupVSETVLIPass (


<s> if ( RegNo > array_lengthof ( FPR32DecoderTable ) ) return MCDisassembler :: Fail ; Register Reg = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> if ( TARGET_XTHEADCONDMOV && GET_MODE_CLASS ( mode ) == MODE_INT && reg_or_0_operand ( cons , mode ) && reg_or_0_operand ( alt , mode ) && GET_MODE ( op ) == mode && GET_MODE ( op0 ) == mode && GET_MODE ( op1 ) == mode && ( code == EQ || code == NE ) ) { riscv_expand_conditional_move_onesided ( dest , cons , alt , code , op0 , op1 ) ; return true ; } else if ( TARGET_SFB_ALU && mode == word_mode ) { riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; cons = force_reg ( GET_MODE ( dest ) ,


<s> SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * Target ; if ( ! isBranch ( I , Cond , Target ) ) break ; if ( ! Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++


<s> CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: Indirect : { SDValue SpillSlot = DAG . CreateStackTemporary ( Outs [ i ] . ArgVT ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; unsigned ArgIndex = Outs [ i ] . OrigArgIndex ; assert ( Outs [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Outs [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { SDValue PartValue = OutVals [ i + <NUM_LIT> ] ; unsigned PartOffset = Outs [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , SpillSlot , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , PartValue , Address , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; ++ i ; } ArgValue = SpillSlot ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) ArgValue = ByValArgs [ j ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT>


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( )


<s> return PhysReg == <STR_LIT> || PhysReg


<s> SDValue Or = N ; if ( Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Srl = Or . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Or . getOperand ( <NUM_LIT> ) ) ) { uint32_t VC1 = Or . getConstantOperandVal (


<s> case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ; else if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter


<s> const MCExpr * <ISA_LIT>MCAsmInfo :: getExprForFDESymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { if ( ! ( Encoding & dwarf :: DW_EH_PE_pcrel ) ) return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer ) ; MCContext & Ctx = Streamer .


<s> return ( reload_completed && known_eq ( cfun -> machine -> frame . total_size , <NUM_LIT> ) && !

cfun -> machine -> interrupt_handler_p ) ;


<s> unsigned getVarArgsFirstFPR ( ) const


<s> int <ISA_LIT>TTIImpl :: getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type

* Ty , TTI :: TargetCostKind CostKind ) {


<s> if ( FI < <NUM_LIT> ) Offset += StackOffset :: getFixed ( RVFI -> getLibCallStackSize ( ) ) ; } else if ( MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) { Offset += StackOffset :: get ( alignTo ( MFI . getStackSize ( ) - RVFI -> getCalleeSavedStackSize ( ) , <NUM_LIT> ) , RVFI -> getRVVStackSize ( ) ) ; } } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += StackOffset :: getFixed ( RVFI -> getVarArgsSaveSize ( ) ) ; if ( FI >= <NUM_LIT> ) Offset -= StackOffset :: getFixed ( RVFI -> getLibCallStackSize ( ) ) ; if ( MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) Offset -= StackOffset :: getFixed ( MFI . getStackSize ( ) ) ; } else { if ( MFI . getStackID ( FI ) == TargetStackID :: Default ) { if ( MFI . isFixedObjectIndex ( FI ) ) { Offset += StackOffset :: get ( MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) + RVFI -> getLibCallStackSize ( ) , RVFI ->


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y


<s> V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; assert ( Lane < ( int ) NumElts && <STR_LIT> ) ; SDValue Gather = DAG . getNode ( <STR_LIT> , DL , ContainerVT , V1 , DAG . getConstant ( Lane , DL , XLenVT ) , TrueMask , VL ) ; return convertFromScalableVector ( VT , Gather , DAG , Subtarget ) ; } } bool IsSelect = all_of ( enumerate ( SVN -> getMask ( ) ) , [ & ] ( const auto & MaskIdx ) { int MaskIndex = MaskIdx . value ( ) ; return MaskIndex < <NUM_LIT> || MaskIdx . index ( ) == ( unsigned ) MaskIndex % NumElts ; } ) ; assert ( ! V1 . isUndef ( ) && <STR_LIT> ) ; SmallVector < SDValue > MaskVals ; SmallVector < SDValue > GatherIndicesLHS , GatherIndicesRHS ; bool SwapOps = DAG . isSplatValue ( V2 ) && ! DAG . isSplatValue ( V1 ) ; bool InvertMask = IsSelect == SwapOps ; for ( int MaskIndex : SVN -> getMask ( ) ) { bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHSOrUndefIndex = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( IsLHSOrUndefIndex && MaskIndex >= <NUM_LIT> ? DAG . getConstant ( MaskIndex , DL , XLenVT ) : DAG . getUNDEF ( XLenVT ) ) ; GatherIndicesRHS . push_back ( IsLHSOrUndefIndex ? DAG . getUNDEF ( XLenVT ) : DAG . getConstant ( MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ; IndexVT = IndexVT . changeVectorElementType (


<s> if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; } if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , StackSize , MachineInstr :: FrameDestroy ) ; emitSCSEpilogue ( MF , MBB


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( Inst ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , IsRV64 , Res ) ; Res . push_back ( Inst ( <STR_LIT> , ShiftAmount ) ) ; if ( Lo12 ) Res . push_back ( Inst ( <STR_LIT>


<s> case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >>


<s> static inline VConstraintType getConstraint ( uint64_t


<s> } else if ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> )


<s> Op = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , SDLoc ( Op ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return getAddrPIC ( Op , DAG ) ; } llvm_unreachable ( <STR_LIT>


<s> bool isUImm8 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( )


<s> int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , IsRV64 , Res ) ; Res . push_back ( Inst ( <STR_LIT>


<s> bool hasStdExtZbe ( ) const { return HasStdExtZbe


<s> int Srcs [ ] = { - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i != Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int Pol = i % <NUM_LIT> ; int Src = Mask [ i ] / Size ; if ( Srcs [ Pol ] < <NUM_LIT> ) Srcs [ Pol ] = Src ; if ( Srcs [ Pol ] != Src ) return false ; int Elt = Mask [ i ] % Size ; if ( Elt != i / <NUM_LIT> ) return false ; } if ( Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] < <NUM_LIT> || Srcs [ <NUM_LIT> ] == Srcs [ <NUM_LIT> ] ) return false ; SwapSources = Srcs [ <NUM_LIT> ]


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg

, SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm


<s> unsigned n = riscv_save_libcall_count ( mask ) ; ssize_t bytes = snprintf ( s , sizeof


<s> if ( from == FRAME_POINTER_REGNUM ) src = cfun -> machine -> frame . frame_pointer_offset ; else if ( from == ARG_POINTER_REGNUM ) src =

cfun -> machine -> frame . arg_pointer_offset ;


<s> bool hasStdExtZba ( ) const { return HasStdExtZba


<s> bool <ISA_LIT>InstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { return


<s> auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && C -> isNullValue ( ) ) VL = SDValue ( selectImm ( CurDAG , SDLoc ( N ) , <NUM_LIT> , Subtarget -> getXLenVT ( ) ) , <NUM_LIT> ) ; else VL = N ; return true


<s> static bool scalar_move_insn_p ( rtx_insn *


<s> bool <ISA_LIT>ExpandPseudo :: expandAuipccInstPair ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI , unsigned FlagsHi , unsigned SecondOpcode ) { MachineFunction * MF = MBB . getParent ( ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; bool HasTmpReg = MI . getNumOperands ( ) > <NUM_LIT> ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TmpReg = MI . getOperand ( HasTmpReg ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( HasTmpReg ? <NUM_LIT> : <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( TmpReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor


<s> return Kind == KindTy :: Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg .


<s> bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch2Reg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , Scratch1Reg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Max : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Scratch2Reg ) . addReg ( IncrReg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: Min : { insertSext ( TII , DL , LoopHeadMBB , Scratch2Reg , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IncrReg ) . addReg ( Scratch2Reg ) . addMBB ( LoopTailMBB ) ; break ; } case AtomicRMWInst :: UMax : BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg


<s> static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) . to_constant (


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg =


<s> assert ( II -> ExtendedOperand < Op . getNumOperands ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Operands ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; SDValue & ScalarOp = Operands [ II -> ExtendedOperand ] ; if ( ScalarOp . getValueType ( ) == <STR_LIT> || ScalarOp . getValueType ( ) == <STR_LIT> || ScalarOp . getValueType ( ) == <STR_LIT> ) { ScalarOp = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , ScalarOp ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Operands ) ; } } } } switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getRegister ( <STR_LIT>


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple


<s> } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) , ValTy ) ; return true ; } } Base =


<s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( llvm :: any_of ( Regs , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ; } ) ) F . getContext ( ) . diagnose


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT


<s> if ( isRV32Only && ActiveFeatures [ <STR_LIT> ] ) return false ; if ( FeaturesRequired . none ( ) ) return true ; return ( FeaturesRequired & ActiveFeatures


<s> return hasStdExtV ( ) && getMinRVVVectorSizeInBits ( )


<s> EVT VT = Op . getValueType ( ) ; if ( VT == Subtarget . getXLenVT ( ) || ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) { SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; auto MatchOROfReverse = [ & ] ( SDValue Reverse , SDValue X ) { if ( Reverse . getOpcode ( ) == <STR_LIT> && Reverse . getOperand ( <NUM_LIT> ) == X && isa < ConstantSDNode > ( Reverse . getOperand ( <NUM_LIT> ) ) && isPowerOf2_32 ( Reverse . getConstantOperandVal ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , Reverse . getOperand ( <NUM_LIT> ) ) ; if ( ( Reverse . getOpcode ( ) == <STR_LIT> || Reverse . getOpcode ( ) == <STR_LIT> ) && Reverse . getOperand ( <NUM_LIT> ) == X && isa < ConstantSDNode > ( Reverse . getOperand ( <NUM_LIT> ) ) ) { uint64_t RotAmt = Reverse . getConstantOperandVal ( <NUM_LIT> ) ; if ( RotAmt == ( VT . getSizeInBits ( ) / <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( RotAmt , DL , VT ) ) ; } return SDValue ( ) ; } ; if ( SDValue V = MatchOROfReverse ( Op0 , Op1 ) ) return V ; if ( SDValue V = MatchOROfReverse ( Op1 , Op0 ) ) return V ; if ( Op0 . getOpcode ( ) != <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue OrOp0 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue OrOp1 = Op0 . getOperand ( <NUM_LIT> ) ; auto LHS = matchGREVIPat ( OrOp0 ) ; if ( ! LHS ) { std :: swap ( OrOp0 , OrOp1 ) ; LHS = matchGREVIPat ( OrOp0 ) ; } auto RHS = matchGREVIPat ( Op1 ) ; if ( LHS && RHS && LHS -> formsPairWith ( * RHS ) && LHS -> Op == OrOp1 ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS -> Op , DAG . getConstant ( LHS -> ShAmt


<s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_TPREL_HI || Kind == VK_<ISA_LIT>_TPREL_LO || Kind == VK_<ISA_LIT>_TPREL_ADD || Kind == VK_<ISA_LIT>_TLS_GOT_HI || Kind == VK_<ISA_LIT>_TLS_GD_HI || Kind == VK_<ISA_LIT>_CALL || Kind == VK_<ISA_LIT>_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return


<s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; if ( RVFI -> getRVVStackSize ( ) && ( ! hasFP ( MF

) || TRI -> hasStackRealignment ( MF ) ) ) {


<s> machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT ) ; gcc_assert ( reg_or_0_operand ( cons , mode ) ) ; gcc_assert ( reg_or_0_operand ( alt , mode ) ) ; riscv_emit_int_compare ( & code , & op0 , & op1 , true ) ; rtx cond = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; rtx tmp1 = gen_reg_rtx ( mode )


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> return getTM < <ISA_LIT>TargetMachine >


<s> APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq = generateInstSeq ( Chunk . getSExtValue ( ) , IsRV64 ) ; Cost += MatSeq . size (


<s> bool hasC910 ( ) const { return HasC910


<s> if ( ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm )


<s> StringRef Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . hasD ( ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; } else { assert ( Prefix ==


<s> MOFI -> initMCObjectFileInfo ( Ctx , PIC , LargeCodeModel ) ; return


<s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> )


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool selectRegAddr ( SDValue Addr , SDValue & Base ) { Base =


<s> tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode


<s> unsigned NF = Node -> getNumOperands ( ) - <NUM_LIT> ; if ( IsMasked ) -- NF ; MVT VT = Node -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ; ReplaceNode ( Node ,


<s> static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RM , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG

. getConstant ( Table , DL , XLenVT ) , Shift ) ;


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; IsRV64 = o . IsRV64 ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o


<s> bool <ISA_LIT>AsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( const MCAlignFragment & AF , unsigned & Size ) { const MCSubtargetInfo * STI = AF . getSubtargetInfo ( ) ; if ( ! STI -> getFeatureBits ( ) [ <STR_LIT> ] ) return false ; bool HasStdExtC = STI -> getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; if ( AF . getAlignment ( ) <= MinNopLen ) { return false ; }


<s> bool <ISA_LIT>AsmBackend :: relaxDwarfCFA ( MCDwarfCallFrameFragment & DF , MCAsmLayout & Layout , bool & WasRelaxed ) const { const MCExpr & AddrDelta = DF . getAddrDelta ( ) ; SmallVectorImpl < char > & Data = DF . getContents ( ) ; SmallVectorImpl < MCFixup > & Fixups = DF . getFixups ( ) ; size_t OldSize = Data . size ( ) ; int64_t Value ; bool IsAbsolute = AddrDelta . evaluateKnownAbsolute ( Value , Layout ) ; assert ( IsAbsolute && <STR_LIT> ) ; ( void ) IsAbsolute ; Data . clear ( ) ; Fixups . clear ( ) ; raw_svector_ostream OS ( Data ) ; assert ( Layout . getAssembler ( ) . getContext ( ) . getAsmInfo ( ) -> getMinInstAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value == <NUM_LIT> ) { WasRelaxed = OldSize != Data . size ( ) ; return true ; } auto AddFixups = [ & Fixups , & AddrDelta ] ( unsigned Offset , std :: pair < unsigned , unsigned > Fixup ) { const MCBinaryExpr & MBE = cast < MCBinaryExpr > ( AddrDelta ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getLHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getRHS ( ) , static_cast < MCFixupKind > ( std


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; } break ; } case <STR_LIT> : if ( Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) )


<s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg =


<s> { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; } return true


<s> switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; } Inst = std :: move


<s> if ( ! I ) return false ; unsigned MaskOpIdx = I -> MaskOpIdx ; if ( ! isa < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) || cast < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) -> getReg ( ) != <STR_LIT> ) return false ; const auto * Glued = N -> getGluedNode ( ) ; if ( ! Glued || Glued -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) || cast < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; SDValue MaskSetter = Glued -> getOperand ( <NUM_LIT> ) ; const auto IsVMSet = [ ] ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; } ; if ( ! MaskSetter -> isMachineOpcode ( ) || ! IsVMSet ( MaskSetter . getMachineOpcode ( ) ) ) return false ; Optional < unsigned > TailPolicyOpIdx ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MaskedMCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( <STR_LIT> ( MaskedMCID . TSFlags ) ) { TailPolicyOpIdx = N -> getNumOperands ( ) - <NUM_LIT> ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getConstantOperandVal ( * TailPolicyOpIdx ) != <STR_LIT> ) return false ; } const MCInstrDesc & UnmaskedMCID = TII -> get ( I -> UnmaskedPseudo ) ; assert ( ! <STR_LIT> ( UnmaskedMCID . TSFlags ) && <STR_LIT> ( UnmaskedMCID . TSFlags ) && ! <STR_LIT> ( UnmaskedMCID . TSFlags ) && <STR_LIT> ) ; ( void ) UnmaskedMCID ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> , E = N -> getNumOperands ( ) ;


<s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT>


<s> if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) { if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) ,


<s> } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( ) + ( Fixup -> getOffset ( ) - AUIPCOffset ) ) ; return true


<s> auto LHS = matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) ; auto RHS = matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) ; if ( LHS && RHS && LHS -> formsPairWith ( * RHS ) ) { SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS -> Op

, DAG . getConstant ( LHS -> ShAmt , DL , VT ) ) ;


<s> m_demands [ DEMAND_SEW ] = true ; if ( ! ignore_vlmul_insn_p ( insn -> rtl ( ) ) ) m_demands [ DEMAND_LMUL ] = true ; } if ( get_attr_ta ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_TAIL_POLICY ] = true ; if ( get_attr_ma ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_MASK_POLICY ] = true ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) return ; if ( scalar_move_insn_p ( insn -> rtl ( ) ) ) { if ( m_avl . has_non_zero_avl ( ) ) m_demands [ DEMAND_NONZERO_AVL ] = true ; if ( m_ta ) m_demands [ DEMAND_GE_SEW ] = true ; } if ( ! m_avl . has_avl_reg ( ) || vlmax_avl_p ( get_avl ( ) ) || ! m_avl . get_source ( ) ) return ; if ( ! m_avl . get_source ( ) -> insn ( ) -> is_real ( ) && ! m_avl . get_source ( ) -> insn ( ) -> is_phi ( ) ) return ; insn_info * def_insn = extract_single_source ( m_avl . get_source ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( N0 . getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT>


<s> assert ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) ; unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( AI -> getOrdering ( ) ) ) ; Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * LrwOpScwLoop = <STR_LIT> ( AI -> getModule ( ) , getIntrinsicForMaskedAtomicRMWBinOp ( XLen , AI -> getOperation ( ) ) , Tys ) ; if ( XLen == <NUM_LIT> ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value *


<s> bool riscv_split_symbol_type ( enum riscv_symbol_type symbol_type ) { if ( symbol_type == SYMBOL_TLS_LE ) return true ; if ( ! TARGET_EXPLICIT_RELOCS ) return false ; return symbol_type == SYMBOL_ABSOLUTE ||


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } else { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo ,

DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ;


<s> static bool expandOffset ( <ISA_LIT>AddressingMode & AM , bool IsBase , SDValue Op0 , ConstantSDNode * Op1 ) { int64_t TestOffset = AM . Offset + Op1 -> getSExtValue ( ) ; if ( selectOffset ( AM . OffR , TestOffset ) ) { AM . Base = Op0 ; AM . Offset =


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ( MCID . TSFlags & Flag ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) .


<s> SDValue <ISA_LIT>TargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue


<s> if ( pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ) return gen_int_mode ( TAIL_UNDISTURBED , Pmode ) ; return gen_int_mode ( get_prefer_tail_policy (


<s> return Kind == KindImm && inRange ( Imm , MinValue


<s> assert ( Subtarget . hasStdExtZbkb ( ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalarInteger ( ) || VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) || ! isPowerOf2_32 ( VT . getSizeInBits ( ) ) ) return SDValue ( ) ; SDLoc DL ( N )


<s> if ( count != <NUM_LIT> ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM


<s> ssize_t bytes = snprintf ( s , sizeof ( s ) , <STR_LIT> , n ) ; gcc_assert ( ( size_t ) bytes < sizeof ( s ) ) ; return s


<s> Operands . push_back ( Node -> getOperand ( CurOp ++ ) ) ; if ( IndexVT ) * IndexVT = Operands . back ( ) -> getSimpleValueType ( <NUM_LIT> ) ; } if ( IsMasked ) { SDValue Mask = Node -> getOperand ( CurOp ++ ) ; Chain = CurDAG -> getCopyToReg ( Chain , DL , <STR_LIT> , Mask , SDValue ( ) ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Operands . push_back ( CurDAG -> getRegister ( <STR_LIT> , Mask . getValueType ( ) ) ) ; } SDValue VL ; selectVLOp ( Node -> getOperand ( CurOp ++ ) , VL ) ; Operands . push_back ( VL ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDValue SEWOp = CurDAG -> getTargetConstant ( Log2_32 ( SEW ) , DL , XLenVT ) ; Operands . push_back ( SEWOp ) ; Operands . push_back ( Chain ) ; if ( Glue ) Operands . push_back ( Glue


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid


<s> ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } SelectCode ( Node


<s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount (


<s> if ( Addr . getOpcode ( ) == <STR_LIT> && expandOffset ( AM , true , SDValue ( )

, cast < ConstantSDNode > ( Addr ) ) ) {


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF ::


<s> { <STR_LIT> , riscv_d_handle_target_float_abi } , { NULL , NULL


<s> info = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; return ; } if ( fault_first_load_p ( insn -> rtl ( ) ) && info . update_fault_first_load_avl


<s> assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; assert ( V . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL (


<s> if ( SEWLMULRatioOnly ) return false ; if ( ! Strict && InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) { if ( SEW == InstrInfo . SEW ) return true ; } if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( hasCompatibleVTYPE ( InstrInfo , Strict ) )


<s> int FrameIdx = Entry . getFrameIdx ( ) ; int64_t Offset ; if ( FrameIdx < <NUM_LIT> ) Offset = FrameIdx * ( int64_t ) STI . getXLen ( ) / <NUM_LIT> ; else Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) - RVFI -> getLibCallStackSize ( ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RealStackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ( MF )


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG & DAG


<s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; if ( ! lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) )

EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Op . getSimpleValueType ( ) == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; normaliseSetCC ( LHS , RHS , CCVal ) ; SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC


<s> case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : return isIntN ( <NUM_LIT> , SignExtend64 ( BrOffset + <NUM_LIT> ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > createVType ( APInt Sew , APInt Lmul , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VType ) ; Sew . ashrInPlace


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL ,


<s> static rtx riscv_swap_instruction ( rtx inst ) { gcc_assert ( GET_MODE ( inst ) == SImode ) ; if ( BYTES_BIG_ENDIAN ) inst = expand_unop ( SImode , bswap_optab , inst , gen_reg_rtx ( SImode ) ,


<s> } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT


<s> SDValue <ISA_LIT>TargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; if ( isPositionIndependent ( ) ) report_fatal_error (


<s> unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize , MachineInstr ::


<s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( IsCapMode ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( IsCapMode ? <STR_LIT> : <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case


<s> MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; unsigned RegLo = VA . getLocReg ( ) ; unsigned RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi


<s> return ( bool ) ( get_prefer_tail_policy ( ) & <NUM_LIT> || ( get_prefer_tail_policy ( ) >> <NUM_LIT> &


<s> static unsigned second_ratio ( const vector_insn_info & , const vector_insn_info & info2 ) { return info2 . get_ratio


<s> const avl_info & get_avl_info ( ) const { return


<s> unsigned getPCImmEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO .


<s> return new TargetPassConfig ( this , PM


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { PointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString =


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode =


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , NameLoc , isRV64 ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands , Name ) ) return true ; unsigned OperandIdx = <NUM_LIT> ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) return true ; ++ OperandIdx ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex


<s> } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( IsScalableVector ) { bool UseVMV_V_V = false ; MachineBasicBlock :: const_iterator DefMBBI ; unsigned DefExplicitOpNum ; unsigned VIOpc ; if ( isConvertibleToVMV_V_V ( STI , MBB , MBBI , DefMBBI , LMul ) ) { UseVMV_V_V = true ; DefExplicitOpNum = DefMBBI -> getNumExplicitOperands ( ) ; switch ( LMul ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; VIOpc = <STR_LIT> ; break ; } } bool UseVMV_V_I = false ; if ( UseVMV_V_V && ( DefMBBI -> getOpcode ( ) == VIOpc ) ) { UseVMV_V_I = true ; Opc = VIOpc ; } if ( NF == <NUM_LIT> ) { auto MIB = BuildMI ( MBB , MBBI , DL , get ( Opc ) ,


<s> void <ISA_LIT>InstPrinter :: printVTypeImm ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Ediv = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Sew = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lmul = Imm & <NUM_LIT> ; Sew = <NUM_LIT> << ( Sew + <NUM_LIT> ) ; Lmul = <NUM_LIT> << Lmul ; Ediv = <NUM_LIT> << Ediv ; O << <STR_LIT> << Sew ; O << <STR_LIT> << Lmul ; O << <STR_LIT> << Ediv


<s> virtual gimple * fold ( gimple_folder &


<s> if ( ST -> hasVInstructions ( ) ) return <NUM_LIT> ; return


<s> if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned


<s> Target & llvm :: getThe<ISA_LIT>64Target (


<s> if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; if ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) curr_prob = profile_probability ::


<s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return ( ( MFI . hasVarSizedObjects ( ) || RVFI -> hasSpillVRs ( ) ) && TRI -> needsStackRealignment


<s> for ( unsigned i = <NUM_LIT> , e = GEP -> getNumOperands ( ) ; i != e ; ++ i , ++ GTI ) { if ( ! Ops [ i ] -> getType ( ) -> isVectorTy ( ) ) continue ; if ( VecOperand ) return std :: make_pair ( nullptr , nullptr ) ; VecOperand = i ; TypeSize TS = DL -> getTypeAllocSize ( GTI . getIndexedType ( ) ) ; if ( TS . isScalable ( ) ) return std :: make_pair ( nullptr , nullptr ) ; TypeScale = TS . getFixedSize ( ) ; } if ( ! VecOperand ) return std :: make_pair ( nullptr , nullptr ) ; Value * VecIndex = Ops [ * VecOperand ] ; Type * VecIntPtrTy = DL -> getIntPtrType ( GEP -> getType ( ) ) ; if ( VecIndex -> getType ( ) != VecIntPtrTy ) return std :: make_pair ( nullptr , nullptr ) ; Value * Stride ; BinaryOperator * Inc ; PHINode * BasePhi ; if ( ! matchStridedRecurrence ( VecIndex , L , Stride , BasePhi , Inc , Builder ) ) return std :: make_pair ( nullptr , nullptr ) ; assert ( BasePhi -> getNumIncomingValues ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned IncrementingBlock = BasePhi -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; assert ( BasePhi -> getIncomingValue ( IncrementingBlock ) == Inc && <STR_LIT> ) ; Builder . SetInsertPoint ( GEP ) ; Ops [ * VecOperand ] = BasePhi ; Type * SourceTy = GEP


<s> SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL ,