<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = getFrameRegister ( MF ) ; int64_t Offset = ( TFI -> getFrameIndexOffset ( MF , FrameIndex ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) { MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr


<s> if ( tm . getTargetTriple ( ) . isMacOSX ( ) ) return

new <ISA_LIT>DarwinAsmPrinter ( tm , std :: move ( Streamer ) ) ;


<s> unsigned <ISA_LIT>16InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int &


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSORegImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits =


<s> if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT>


<s> if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT>


<s> EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! TLI . isTypeLegal ( DstVT ) ) return false ; unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT . SimpleTy == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT>


<s> if ( lane < low || lane >= high ) { if ( exp ) error_at ( EXPR_LOCATION ( exp ) , <STR_LIT>

, desc , lane , low , high - <NUM_LIT> ) ;


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; } else { RC = Opc != <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; } Register SrcReg = Src . getReg ( ) ; if ( Opc != <STR_LIT> ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; if ( Register :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( Register :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister


<s> ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr * MI = MBBI ; if ( ! MI -> isDebugValue ( ) ) ++ Count ; if ( MI -> mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) { StoreI = MBBI ; return true ; } if ( MI -> isCall ( ) ) return false ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return


<s> return Pmode ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ; return


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>BETarget , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler (

TheThumbLETarget , createThumbDisassembler ) ;


<s> if ( TARGET_64BIT ) d_add_builtin_version ( <STR_LIT> ) ; else d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_SOFT_FLOAT )


<s> MachineInstr & MI = * I ; const DebugLoc & dl = MI . getDebugLoc ( ) ; ASSERT_SORTED ( PopTable ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> ) I -> RemoveOperand (


<s> case <STR_LIT> : case <STR_LIT> : return performAddSubLongCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : { SDValue RV = performSelectCombine ( N , DCI ) ; if ( ! RV . getNode ( ) ) RV = performAcrossLaneMinMaxReductionCombine ( N , DAG , Subtarget ) ; return RV ; } case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case


<s> return emitAddSub_ri ( false , RetVT , LHSReg , LHSIsKill , Imm


<s> StringRef Option ; if ( Parser . parseIdentifier ( Option ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { return Error ( L , <STR_LIT> ) ; } setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> Op -> SysReg . MRSReg = MRSReg ; Op -> SysReg . MSRReg = MSRReg ; Op -> SysReg . PStateField = PStateField ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> StringRef getPassName ( ) const override { return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DAG ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> addPass ( & EarlyIfConverterID ) ; return


<s>
if
(
!
OddRegUsed
&&
!
EvenRegUsed
)
{
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
UnspilledCSGPRs
.
push_back
(
OddReg
)
;
UnspilledCSGPRs
.
push_back
(
EvenReg
)
;
}
else
{
UnspilledCSFPRs
.
push_back
(
OddReg
)
;
UnspilledCSFPRs
.
push_back
(
EvenReg
)
;
}
continue
;
}
unsigned
Reg
=
<STR_LIT>
;
if
(
OddRegUsed
^
EvenRegUsed
)
{
Reg
=
OddRegUsed
EvenReg
:
OddReg
;
MRI
->
setPhysRegUsed
(
Reg
)
;
}
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
OddReg
,
RegInfo
)
)
;
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
EvenReg
,
RegInfo
)
)
;
assert
(
(
(
OddReg
==
<STR_LIT>
&&
EvenReg
==
<STR_LIT>
)
||
(
RegInfo
->
getEncodingValue
(
OddReg
)
+
<NUM_LIT>
==
RegInfo
->
getEncodingValue
(
EvenReg
)
)
)
&&
<STR_LIT>
)
;
if
(
<STR_LIT>
.
contains
(
OddReg
)
)
{
NumGPRSpilled
+=
<NUM_LIT>
;
if
(
Reg
!=
<STR_LIT>
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
ExtraCSSpill
=
true
;
}
else
NumFPRSpilled
+=
<NUM_LIT>
;
CanEliminateFrame
=
false
;
}
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
CFSize
=
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
(
NumGPRSpilled
+
NumFPRSpilled
)
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
CFSize
<<
<STR_LIT>
)
;
bool
BigStack
=
(
CFSize
>=
<NUM_LIT>
)
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
&&
!
ExtraCSSpill
)
{
assert
(
(
(
UnspilledCSGPRs
.
size
(
)
&
<NUM_LIT>
)
==
<NUM_LIT>
)
&&
<STR_LIT>
)
;
unsigned
Count


<s> Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) ) ; } else if ( Tagged ) { StackOffset SPOffset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) ) ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm << <STR_LIT> ; else if ( OffImm > <NUM_LIT> ) O


<s> if ( CM ) return * CM ; return CodeModel ::


<s> NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( Br . MI , DestBB , MaxOffs ) ) { Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBSizes [ MBB -> getNumber ( ) ] -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , - <NUM_LIT> ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = GetOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; unsigned DestOffset = BBOffsets [ DestBB -> getNumber ( ) ] ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = llvm :: getInstrPredicate ( CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) { MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; MachineInstr * NewBR = BuildMI ( * MBB , CmpMI , Br . MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg ) . addMBB ( DestBB , Br . MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) ; CmpMI -> eraseFromParent ( ) ; Br . MI -> eraseFromParent ( ) ; Br . MI = NewBR ; BBSizes [ MBB -> getNumber ( ) ] -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , - <NUM_LIT> ) ; ++


<s> EmitInstrRegReg ( MovOpc , <STR_LIT> , <STR_LIT> ) ; EmitMovFPIntPair ( MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; break ; case DSig : EmitMovFPIntPair ( MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; break ; case DDSig : EmitMovFPIntPair ( MovOpc , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , LE ) ; EmitMovFPIntPair ( MovOpc , <STR_LIT> , <STR_LIT> ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) ) ; RetAddrOffset =


<s> bool isCOP2Asm ( ) const { return Kind == k_Register && Reg . Kind


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( isUnsupportedFloatingType ( VT ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , SDLoc ( Op ) ) . first ; } return Op


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv2di (


<s> DecodeStatus <ISA_LIT>64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>6432 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT>


<s> static SDValue PerformUMLALCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasV6Ops ( ) || ! Subtarget -> hasDSP ( ) ) return SDValue ( ) ; SDNode * AddcNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * AddeNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( AddcNode -> getOpcode ( ) == <STR_LIT> ) && ( AddeNode -> getOpcode ( ) == <STR_LIT> ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == AddcNode ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) } ) ; else return SDValue (


<s> default : return SDValue ( ) ; case <STR_LIT> : { SDValue CountInput = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Cntlzw = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CountInput ) , <NUM_LIT> ) ; SDValue SHLOps [ ] = { Cntlzw , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; SDValue Sldi = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SHLOps ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Sldi , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Xor = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Clz = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor ) , <NUM_LIT> ) ; SDValue ShiftOps [ ] = { Clz , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; SDValue Shift = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ShiftOps ) , <NUM_LIT> ) ; SDValue Xori = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Shift , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT>


<s> return decodeBDVAddr12Operand ( Inst ,


<s> return ( __m128i ) __builtin_ia32_loaddqusi128_mask ( ( const int * ) __P , ( __v4si )


<s> SDValue MultLo = ADDCNode -> getOperand ( <NUM_LIT> ) ; SDNode * MultNode = MultHi . getNode ( ) ; unsigned MultOpc = MultHi . getOpcode ( ) ; if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDLoc DL ( ADDENode ) ; SDValue ACCIn = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , ADDCNode -> getOperand ( <NUM_LIT> ) , ADDENode -> getOperand ( <NUM_LIT> ) ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MAdd = CurDAG -> getNode ( MultOpc , DL , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ACCIn ) ; if ( ! SDValue ( ADDCNode , <NUM_LIT> ) . use_empty ( ) ) { SDValue LoOut = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , MAdd ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( ADDCNode , <NUM_LIT> ) , LoOut ) ; } if ( ! SDValue ( ADDENode , <NUM_LIT> )


<s> } HasHazard = MI . mayStore ( ) && ( OrigSeenLoad || OrigSeenStore ) ; HasHazard |= MI . mayLoad ( ) || OrigSeenStore ; SeenNoObjLoad |= MI . mayLoad ( ) ; SeenNoObjStore |= MI . mayStore


<s> return ( __m128d ) __builtin_ia32_reducepd128_mask ( ( __v2df ) __A , __B , (


<s> assert ( offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; return offset / <NUM_LIT>


<s> if ( mode == TFmode && ! ( TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( mode == TImode ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 , mode ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; if ( reload_in_progress && GET_CODE ( rs1 ) == HIGH && XEXP ( rs1 , <NUM_LIT> ) == imm1 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ; else return <NUM_LIT> ; if ( GET_CODE ( rs1 ) == SUBREG ) rs1 = SUBREG_REG ( rs1 ) ; if ( ! REG_P ( rs1 ) ) return <NUM_LIT> ; if ( rs2 ) { if ( GET_CODE ( rs2 ) == SUBREG ) rs2 = SUBREG_REG ( rs2 ) ; if ( ! REG_P ( rs2 ) ) return <NUM_LIT> ; } if ( strict ) { if ( ! REGNO_OK_FOR_BASE_P ( REGNO ( rs1 ) ) || ( rs2 && ! REGNO_OK_FOR_BASE_P ( REGNO ( rs2 ) ) ) ) return <NUM_LIT> ; } else { if ( ( ! SPARC_INT_REG_P ( REGNO ( rs1 ) ) && REGNO ( rs1 ) != FRAME_POINTER_REGNUM && REGNO ( rs1 ) < FIRST_PSEUDO_REGISTER ) || ( rs2 && ( ! SPARC_INT_REG_P ( REGNO ( rs2 ) ) && REGNO ( rs2 ) !=

FRAME_POINTER_REGNUM && REGNO ( rs2 ) < FIRST_PSEUDO_REGISTER ) ) ) return <NUM_LIT> ;


<s> enum insn_code icode = aarch64_memtag_builtin_data [ fcode - AARCH64_MEMTAG_BUILTIN_START - <NUM_LIT> ] . icode ; rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; machine_mode mode0 = GET_MODE ( op0 ) ; op0 = force_reg ( mode0 == VOIDmode ? DImode : mode0 , op0 ) ; op0 = convert_to_mode ( DImode , op0 , true ) ; switch ( fcode ) { case AARCH64_MEMTAG_BUILTIN_IRG : case AARCH64_MEMTAG_BUILTIN_GMI : case AARCH64_MEMTAG_BUILTIN_SUBP : case AARCH64_MEMTAG_BUILTIN_INC_TAG : { if ( ! target || GET_MODE ( target ) != DImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , DImode ) ) target = gen_reg_rtx ( DImode ) ; if ( fcode == AARCH64_MEMTAG_BUILTIN_INC_TAG ) { rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , QImode ) ) { pat = GEN_FCN ( icode ) ( target , op0 , const0_rtx , op1 ) ; break ; } error_at ( EXPR_LOCATION ( exp ) ,


<s> return ( SMO . getType ( ) == MachO :: S_CSTRING_LITERALS || SMO . getType ( ) == MachO :: S_4BYTE_LITERALS || SMO . getType ( ) == MachO :: S_8BYTE_LITERALS || SMO . getType ( ) == MachO :: S_16BYTE_LITERALS || SMO . getType ( ) == MachO :: S_LITERAL_POINTERS || ( SMO . getSegmentName ( ) == <STR_LIT> && ( SMO . getSectionName ( ) == <STR_LIT> || SMO . getSectionName ( ) == <STR_LIT> ) ) || ( SMO . getSegmentName ( ) == <STR_LIT> && ( SMO . getSectionName ( ) == <STR_LIT> || SMO .

getSectionName ( ) == <STR_LIT> || SMO . getSectionName ( ) == <STR_LIT> ) ) ) ;


<s> bool hasCLMUL ( ) const { return HasCLMUL


<s> static void ix86_check_avx256_stores ( rtx dest , const_rtx , void *


<s> else CPUName = <STR_LIT> ; } InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment


<s> bool <ISA_LIT>ShortenInst :: shortenIIF ( MachineInstr & MI , unsigned LLIxL , unsigned LLIxH ) { Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned thisSubRegIdx = ( <STR_LIT> . contains ( Reg ) ? <STR_LIT> : <STR_LIT> ) ; unsigned otherSubRegIdx = ( thisSubRegIdx == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned GR64BitReg = TRI -> getMatchingSuperReg ( Reg , thisSubRegIdx , & <STR_LIT> ) ; Register OtherReg = TRI -> getSubReg ( GR64BitReg , otherSubRegIdx


<s> unsigned OffsetStride = getOffsetStride ( Opc ) ; if ( OffsetStride == <NUM_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> if ( sh_cfun_interrupt_handler_p ( ) && ! regs_ever_live


<s> break ; case <STR_LIT> : RC = Subtarget . hasFPUv2SingleFloat ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : RC = Subtarget . hasFPUv2DoubleFloat ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; return convertLocVTToValVT ( DAG , Val , VA ,


<s> unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MBBI != FirstMBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm ( <NUM_LIT> ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && TM . getSubtarget < <ISA_LIT>Subtarget


<s> getBDLAddr12Len8Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT>


<s> DECL_FIELD_CONTEXT ( num ) = record ; reg = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , build_array_type ( ptr_type_node , build_index_type ( build_int_2 ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; DECL_FIELD_CONTEXT ( reg ) = record ; TREE_CHAIN ( reg ) = num ; ap = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) ,


<s> static __inline vec_ullong2 spu_cmpabsgt ( vec_double2 a , vec_double2 b ) { return ( ( vec_ullong2 ) ( si_dfcmgt ( ( qword ) ( a ) , ( qword ) (


<s> return __builtin_arm_shsub16 ( __a ,


<s> unsigned A15SDOptimizer :: getDPRLaneFromSPR ( unsigned SReg ) { unsigned DReg = TRI -> getMatchingSuperReg ( SReg , <STR_LIT> , & <STR_LIT> ) ; if ( DReg != <STR_LIT>


<s> MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , TempReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB


<s> else if ( gr_size > UNITS_PER_WORD ) int_regs += gr_size / UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( arg . mode , gen_rtvec_v ( i , loc ) ) ; } else if ( arg . mode == TFmode || arg . mode == TCmode || ! FLOAT_MODE_P ( arg . mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) { int byte_size = arg . promoted_size_in_bytes ( ) ; if ( BYTES_BIG_ENDIAN && ( arg . mode == BLKmode || arg . aggregate_type_p ( ) ) && byte_size < UNITS_PER_WORD && byte_size > <NUM_LIT> ) { rtx gr_reg = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , ( basereg + cum -> words + offset ) ) , const0_rtx ) ; return gen_rtx_PARALLEL ( arg . mode , gen_rtvec ( <NUM_LIT> , gr_reg ) ) ; } else return gen_rtx_REG ( arg . mode , basereg + cum -> words + offset ) ; } else if ( cum -> prototype ) { if ( arg . named ) return gen_rtx_REG ( arg . mode , FR_ARG_FIRST + cum -> fp_regs ) ; else if ( BYTES_BIG_ENDIAN && arg . mode == SFmode ) return gen_rtx_PARALLEL ( arg . mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , basereg + cum -> words + offset ) , const0_rtx ) ) ) ; else return gen_rtx_REG ( arg . mode , basereg + cum -> words + offset ) ; } else { machine_mode inner_mode = ( BYTES_BIG_ENDIAN && arg . mode == SFmode ) ? DImode : arg . mode ; rtx fp_reg = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( arg . mode , ( FR_ARG_FIRST + cum -> fp_regs ) ) , const0_rtx ) ; rtx gr_reg = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( inner_mode , ( basereg + cum -> words + offset )


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , ReturnRegsCount ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSAlignGapSize ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , NumAlignedDPRCS2Regs ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex

( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address , Address + imm + <NUM_LIT> , Decoder ) ; return


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string upperCase = Tok . getString ( ) . str ( ) ; std :: string lowerCase = LowercaseString ( upperCase ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) return - <NUM_LIT> ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex


<s> if ( cast < TruncInst > ( I ) -> getDestTy ( ) -> getIntegerBitWidth ( ) == BitWidth ) isNarrow = IsNarrowSequence < BitWidth > ( Val , VL ) ; } else if ( match ( V , m_Add ( m_Value ( LHS ) , m_Value ( RHS ) ) ) ) { isNarrow = false ; } else if ( match ( V , m_ZExtOrSExt ( m_Value ( Val ) ) ) ) { if ( cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) == BitWidth ) isNarrow = true ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << cast < CastInst > ( I ) -> getSrcTy ( ) -> getIntegerBitWidth ( ) ) ; if ( match ( Val , m_Load ( m_Value ( Val ) ) ) ) { auto * Ld = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Ld -> dump ( ) ) ; VL . push_back ( Ld ) ; isNarrow = true ; } else if ( ! isa < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) VL . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } if ( isNarrow ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; VL . push_back ( I )


<s> assert ( Inst . getOperand ( OpNum - <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( OpNum < <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( )

== <STR_LIT> ) && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) {


<s> rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> int Cc = ConvertCcString ( Format ) ; if ( Cc == - <NUM_LIT> ) { return Error ( NameLoc , <STR_LIT> ) ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Mnemonic ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQQuadNode ( SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> ,


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >=


<s> if ( ( int64_t ) Value < <NUM_LIT> ) { Value = - Value ; opc = <NUM_LIT> ; } uint32_t out = ( opc << <NUM_LIT> ) ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint64_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> & ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : { Value = Value - <NUM_LIT> ; Value >>= <NUM_LIT> ; uint32_t out = <NUM_LIT> ; bool I = Value & <NUM_LIT> ; bool J1 = Value & <NUM_LIT> ; bool J2 = Value & <NUM_LIT> ; J1 ^= I ; J2 ^= I ; out |= I << <NUM_LIT> ; out |= ! J1 << <NUM_LIT> ; out |= ! J2 << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint64_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : { Value = Value - <NUM_LIT> ; Value >>= <NUM_LIT> ; uint64_t out = <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) >> <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; out |= ( Value & <NUM_LIT> ) ; uint32_t swapped = ( out & <NUM_LIT> ) >> <NUM_LIT> ; swapped |= ( out & <NUM_LIT> ) << <NUM_LIT> ; return swapped ; } case <STR_LIT> : { unsigned isNeg = ( int64_t ( Value - <NUM_LIT> ) < <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; uint32_t Binary = <NUM_LIT> ; Value = <NUM_LIT> & ( ( Value - <NUM_LIT> ) >> <NUM_LIT> ) ; Binary = ( Value &


<s> static inline const MachineInstrBuilder & addConstantPoolReference ( const MachineInstrBuilder & MIB , unsigned CPI ,

unsigned GlobalBaseReg , unsigned char OpFlags ) {


<s> FunctionPass * llvm :: create<ISA_LIT>FixupSetCC ( ) { return new <ISA_LIT>FixupSetCCPass ( )


<s> static __inline unsigned short si_to_ushort ( qword q ) { union { qword q ; unsigned short s [ <NUM_LIT> ] ; } x


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT>


<s> uint64_t StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; if ( needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) Offset += SlotSize ; else { unsigned Align = MF . getFrameInfo ( ) -> getObjectAlignment ( FI ) ; assert ( ( - ( Offset + StackSize ) ) % Align == <NUM_LIT> ) ; Align = <NUM_LIT> ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF )


<s> MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( TRI -> getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst


<s> return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op


<s> if ( ArgOffset > LinkageSize + ParamAreaSize ) UseMemory = true ; if ( ! Flags . isByVal ( ) ) { if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ( HasQPX && ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) ) ) if ( AvailableFPRs > <NUM_LIT> ) { -- AvailableFPRs ; return false ; } if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) if ( AvailableVRs > <NUM_LIT> ) { -- AvailableVRs ; return


<s> if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_64_Win64 ) ) return & <STR_LIT> ; else if ( Is64Bit ) return & <STR_LIT> ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC )


<s> bool legitimate_indirect_address_p ( rtx x , int strict ) { return GET_CODE ( x ) == REG && INT_REG_OK_FOR_BASE_P ( x


<s> return __builtin_mve_vld1q_uv16qi ( ( __builtin_neon_qi * ) __base


<s> if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return


<s> Inst . addOperand ( MCOperand :: CreateImm


<s> std :: vector < Forward > & getForwardedMustTailRegParms ( ) { return ForwardedMustTailRegParms


<s> return ( c == SH_SYMBIAN_FLAG_CHAR [ <NUM_LIT> ] ) ? strlen ( DLL_EXPORT_PREFIX ) :


<s> AM . Scale = <NUM_LIT> ; AM . IndexReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } else { AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } getAddressOperands ( AM , SDLoc ( N ) , Base , Scale , Index , Disp ,


<s> if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> )


<s> unsigned Reg , Imm12 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) || ( MO . getReg ( ) == <STR_LIT> && MO2 . isExpr ( ) ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; isAdd =


<s> bool <ISA_LIT>SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction (


<s> assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { if ( loadAndAddSymbolAddress ( ImmOp . getExpr ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ; return false ; } if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ; return


<s> MachineInstrBuilder MIB = emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , LowOpcode , Size , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , <NUM_LIT> ) ) MIB . add ( MO ) ; MI . eraseFromParent ( )


<s> if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; return SDValue (


<s> static bool rs6000_debug_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { bool ret = rs6000_can_change_mode_class ( from , to , rclass ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( from ) , GET_MODE_NAME


<s> fputs ( <STR_LIT> , asm_out_file ) ; toc_initialized = <NUM_LIT> ; } fprintf ( asm_out_file , <STR_LIT> , ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> ) ) ; } else fputs ( <STR_LIT> , asm_out_file


<s> LowOverheadLoop ( MachineLoop * ML , MachineLoopInfo * MLI , ReachingDefAnalysis * RDA ) : ML


<s> void <ISA_LIT>DAGToDAGISel :: SelectStore ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; ReplaceNode ( N , St


<s> Op -> Kind = Memory ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetIsReg = OffsetIsReg ; Op -> Mem . Offset = Offset ; Op -> Mem . OffsetRegNum = OffsetRegNum ; Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc =


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream &


<s> if ( INTVAL ( startop ) > <NUM_LIT> && INTVAL ( startop ) < <NUM_LIT> && INTVAL ( sizeop ) > <NUM_LIT> && INTVAL ( sizeop ) + INTVAL ( startop ) < <NUM_LIT> && INTVAL ( shiftop ) > <NUM_LIT> && INTVAL ( sizeop ) + INTVAL ( shiftop ) < <NUM_LIT> && ( <NUM_LIT> - ( INTVAL ( shiftop ) & <NUM_LIT> ) ) >= INTVAL ( sizeop ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = NumStores ; i != e ; ++ i ) { if ( LoadValue == StoreValue [ i ] && LoadOffset == StoreOffset [ i ] ) return true ; if ( StoreValue [ i ]


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; auto IsFreeTruncation = [ VT ] ( SDValue Op ) { unsigned TruncSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; return <STR_LIT> ( Op . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! Src . hasOneUse (


<s> SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( Op . getOpcode ( ) , false ) ; auto ArithmeticShiftRight64 = [ & ] ( uint64_t ShiftAmt ) { assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; MVT ExVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) * <NUM_LIT> ) ; SDValue Ex = DAG . getBitcast ( ExVT , R ) ; if ( ShiftAmt == <NUM_LIT> && Subtarget . hasSSE42 ( ) ) { assert ( ( VT != <STR_LIT> || Subtarget . hasInt256 ( ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , R ) ; } if ( ShiftAmt >= <NUM_LIT> ) { SDValue Upper = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , <NUM_LIT> , DAG ) ; SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , ShiftAmt - <NUM_LIT> , DAG ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } else { SDValue Upper = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , ShiftAmt , DAG ) ; SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; Lower = DAG . getBitcast ( ExVT , Lower ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return DAG . getBitcast ( VT , Ex ) ; } ; APInt APIntShiftAmt ; if ( ! isConstantSplat ( Amt , APIntShiftAmt ) ) return SDValue ( ) ; if ( APIntShiftAmt . uge ( VT . getScalarSizeInBits ( ) ) ) return DAG . getUNDEF ( VT ) ; uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; if ( SupportedVectorShiftWithImm ( VT , Subtarget , Op . getOpcode ( ) ) ) return getTargetVShiftByConstNode ( <ISA_LIT>Opc , dl ,


<s> LazyPtr = ( intptr_t ) emitGlobalValueIndirectSym ( ( GlobalValue * ) F , Fn , JCE ) ; if ( F ) DOUT << <STR_LIT> << LazyPtr << <STR_LIT> << F -> getName ( ) << <STR_LIT> ; else DOUT << <STR_LIT> << LazyPtr << <STR_LIT> << Fn << <STR_LIT> ; } JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) JCE . getCurrentPCValue ( ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( <NUM_LIT> ) ; JCE . emitWordLE ( LazyPtr - ( Addr + <NUM_LIT> + <NUM_LIT> ) ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> ) ; } else


<s> TargetTransformInfo :: getAnalysisUsage ( AU )


<s> temp . val [ <NUM_LIT> ] = vcombine_s32 ( val . val [ <NUM_LIT> ] , vcreate_s32 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s32 ( val . val [ <NUM_LIT> ] , vcreate_s32 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s32 ( val . val [ <NUM_LIT> ] , vcreate_s32 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) temp .


<s> bool ix86_force_load_from_GOT_p ( rtx x , bool call_p ) { return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && ( ( ! call_p && ( ! ix86_direct_extern_access || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) ) || ( SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( <STR_LIT> ,

DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) ) ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ;


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( * Caller ) . useAVX512Regs ( ) == TM . getSubtarget < <ISA_LIT>Subtarget > ( * Callee ) . useAVX512Regs ( ) ) return true ; return llvm :: none_of ( Args , [ ] ( Argument * A ) { auto * EltTy = cast < PointerType > ( A -> getType ( ) ) -> getElementType ( ) ; return EltTy -> isVectorTy ( ) || EltTy -> isAggregateType ( ) ; } )


<s> if ( isCall ) break ; const AllocaInst * A = cast < AllocaInst > ( V ) ; DenseMap < const AllocaInst * , int > :: iterator SI = StaticAllocaMap . find ( A ) ; if ( SI != StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( isCall ) break ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt32 ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM , isCall ) ; } } break ; } case Instruction :: GetElementPtr : { if ( isCall ) break ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { Value * Op = * i ; if ( const StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; Disp += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; } else if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! getTargetMachine ( ) -> symbolicAddressesAreRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) ; if ( IndexReg == <NUM_LIT> ) return false ; } else goto unsupported_gep ; } } if ( ! isInt32 ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t


<s> auto_sbitmap tmpset ( isa_num_bits ) ; static const enum isa_feature fpu_bitlist [ ] = { ISA_ALL_FPU_INTERNAL , isa_nobit } ; arm_initialize_isa ( isa_all_fpubits , fpu_bitlist ) ; for ( unsigned int i = <NUM_LIT> ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( fpubits , all_fpus [ i ] . isa_bits ) ; bitmap_and_compl ( tmpset , isa_all_fpubits , fpubits ) ; bitmap_clear ( isa_all_fpubits ) ; bitmap_copy ( isa_all_fpubits


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const { return TLI


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , <STR_LIT> ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG .

getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isMem = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; if ( StackAdj ) { bool Is64Bit = STI -> is64Bit ( ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 ( ) || STI -> isTargetNaCl64 ( ) ; bool UseLEAForSP = STI -> useLeaForSP ( ) && <ISA_LIT>FL -> canUseLEAForSPInEpilogue ( * MBB . getParent ( ) ) ; unsigned StackPtr = TRI -> getStackRegister ( ) ; StackAdj += <ISA_LIT>FrameLowering :: mergeSPUpdates ( MBB , MBBI , StackPtr , true ) ; <ISA_LIT>FrameLowering :: emitSPUpdate ( MBB , MBBI , StackPtr , StackAdj , Is64Bit , Uses64BitFramePtr , UseLEAForSP , * TII , * TRI ) ; } bool IsWin64 = STI -> isTargetWin64 ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode


<s> int mep_legitimize_reload_address ( rtx * x , machine_mode mode , int opnum , int type_i , int ind_levels ATTRIBUTE_UNUSED ) { enum reload_type type = ( enum reload_type ) type_i ; if ( GET_CODE ( * x ) == PLUS && GET_CODE ( XEXP ( * x , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( * x , <NUM_LIT> ) ) == REG ) { push_reload ( * x , NULL_RTX , x , NULL , GENERAL_REGS , mode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; return <NUM_LIT> ; } if ( GET_CODE ( * x ) == PLUS && GET_CODE ( XEXP ( * x , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( * x , <NUM_LIT> ) ) == CONST_INT ) { char e = mep_section_tag ( XEXP ( * x , <NUM_LIT> ) ) ; if ( e != 't' && e !=


<s> case <STR_LIT> : case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) , CmpLHS ; unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; SDNode * Result = CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return std :: make_pair ( true


<s> return ( vector signed int ) __builtin_altivec_vmsummbm ( ( vector signed char ) a1 , (

vector signed char ) a2 , ( vector signed int ) a3 ) ;


<s> void printAbsAddrOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { O << ( int ) MI -> getOperand ( OpNo ) . getImm


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue Res = tryCombineToBFI ( N , DCI , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; Res = tryCombineToLargerBFI ( N , DCI , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; Res = tryCombineToEXTR ( N , DCI ) ; if ( Res . getNode ( ) ) return Res ; if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT . isVector ( ) && DAG .

getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) {


<s> uint64_t currTextBegin = currTextFrag -> getParent ( ) -> getSection ( ) . addr ( ) + currTextFrag -> getOffset ( ) ; if ( currTextBegin > prevTextEnd ) { RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . insert ( it , frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef :: Create ( * frag , <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( CreateLocalSymbolToFragmentEnd ( pModule , * prevTextFrag ) ) ; addExtraRelocation ( reloc ) ; } prevTextEnd = currTextBegin + currTextFrag -> size ( ) ; prevTextFrag = currTextFrag ; ++ it ; } RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . push_back ( frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) ,


<s> Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned reglist = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( fieldFromInstruction ( Insn ,


<s> if ( RegNo != <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ RegNo ] ) ) ; return MCDisassembler


<s> if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EVT = ( <STR_LIT> ) ( VT . getSimpleVT ( ) + <NUM_LIT> ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; MVT MaskVT = <STR_LIT> ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> >


<s> static ReverseIter getNonDebugInstr ( ReverseIter B , const ReverseIter &


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) { return Op ; } RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Ops , CallOptions , SDLoc ( Op


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm ::


<s> <STR_LIT> CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( CC == <STR_LIT> && getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; return CC


<s> bool <ISA_LIT>InstructionSelector :: selectGlobalValue ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_GLOBAL_VALUE ) && <STR_LIT> ) ; auto GV = I . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) { return false ; } if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; <ISA_LIT>AddressMode AM ; AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg =


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? <NUM_LIT> : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; unsigned Width ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveAbiVersion ( SMLoc L ) { int64_t AbiVersion ; if ( check ( getParser ( ) . parseAbsoluteExpression ( AbiVersion ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement )


<s> if ( MBB . isReturnBlock ( ) && ( & MBB ) != RestoreBlock ) createTailCallBranchInstr ( MBB ) ; } } if ( CSI . empty ( ) && ! needsFP ( MF ) ) { addScavengingSpillSlot ( MF , RS ) ; return ; } unsigned MinGPR = <STR_LIT> ; unsigned MinG8R = <STR_LIT> ; unsigned MinFPR = <STR_LIT> ; unsigned MinVR = <STR_LIT> ; bool HasGPSaveArea = false ; bool HasG8SaveArea = false ; bool HasFPSaveArea = false ; bool HasVRSAVESaveArea = false ; bool HasVRSaveArea = false ; SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { HasGPSaveArea = true ; GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - TRI -> getEncodingValue ( MinFPR ) +


<s> assert ( BitSize == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; for ( unsigned Shift = <NUM_LIT> ; Shift < BitSize ; Shift += <NUM_LIT> ) { uint64_t ShiftedMask = ( <NUM_LIT> << Shift ) ; uint64_t ZeroChunk = UImm & ~ ShiftedMask ; uint64_t OneChunk = UImm | ShiftedMask ; uint64_t RotatedImm = ( UImm << <NUM_LIT> ) | ( UImm >> <NUM_LIT> ) ; uint64_t ReplicateChunk = ZeroChunk | ( RotatedImm & ShiftedMask ) ; if ( <STR_LIT> ( ZeroChunk , BitSize , Encoding ) || <STR_LIT> ( OneChunk , BitSize , Encoding ) || <STR_LIT> ( ReplicateChunk , BitSize , Encoding ) ) { Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; const unsigned Imm16 = getChunk ( UImm , Shift / <NUM_LIT> ) ; Insn . push_back ( { <STR_LIT> , Imm16 ,


<s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Mnemonic ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex (


<s> else if ( cpu_unit_reservation_p ( state , _1mib_ ) ) return <NUM_LIT> ; else if ( cpu_unit_reservation_p ( state , _1mbb_ ) ) return <NUM_LIT> ; else if ( cpu_unit_reservation_p ( state , _1bbb_ ) ) return <NUM_LIT> ; else if ( _1mmf_ >= <NUM_LIT> && cpu_unit_reservation_p ( state , _1mmf_ ) ) return <NUM_LIT> ; else if ( cpu_unit_reservation_p ( state , _1mfi_ ) ) return <NUM_LIT> ; else if ( cpu_unit_reservation_p ( state , _1mfb_ ) ) return <NUM_LIT> ; else if ( cpu_unit_reservation_p ( state , _1mlx_ ) ) return <NUM_LIT> ; else gcc_unreachable ( ) ; default : gcc_unreachable ( )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr


<s> const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( TRI -> getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode (


<s> if ( Alignment ) return Len / Alignment <= <NUM_LIT> ; else return Len


<s> v4sf vh = * ( v4sf * ) fvh ; return __builtin_sh_media_FIPR_S ( vg


<s> if ( is16BitMode ( ) ) return <NUM_LIT> ; if ( is32BitMode ( ) ) return <NUM_LIT> ; if ( is64BitMode ( ) ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT>


<s> Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back (


<s> BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; SDValue BitMask = DAG . getConstant ( - <NUM_LIT> , dl , ExtVT ) ; BitMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , BaseShAmt , Subtarget , DAG ) ; if ( Opcode != <STR_LIT> ) BitMask = getTargetVShiftByConstNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , <NUM_LIT> , DAG ) ; BitMask = DAG . getBitcast ( VT , BitMask ) ; BitMask = DAG . getVectorShuffle ( VT , dl , BitMask , BitMask , SmallVector < int , <NUM_LIT> > ( NumElts , <NUM_LIT> ) ) ; SDValue Res = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , DAG . getBitcast ( ExtVT , R ) , BaseShAmt , Subtarget , DAG ) ; Res = DAG . getBitcast ( VT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , BitMask ) ; if ( Opcode == <STR_LIT> ) { SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , ExtVT ) ; SignMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , SignMask , BaseShAmt , Subtarget , DAG ) ; SignMask = DAG . getBitcast ( VT , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; } return Res ; } } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = <NUM_LIT> / Amt . getScalarValueSizeInBits ( ) ; std :: vector < SDValue > Vals ( Ratio


| __C , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> , __R ) ;


<s> if ( ScalarType . isFloatingPoint ( ) ) { unsigned ScalarSize = ScalarType . getSizeInBits ( ) ; assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned MaskVal = ( ScalarSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Mask = DAG . getConstant ( MaskVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Vec256 = DAG . getNode ( <STR_LIT> , dl , CastVT


<s> break ; case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> : ( RC == & <STR_LIT> ? & <STR_LIT> : RC ) ) ; return FastISel :: fastEmitInst_rr ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Op1


<s> BuildMI ( & MBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; addRegOffset ( BuildMI ( & MBB , DebugLoc ( ) , TII -> get (

<STR_LIT> ) ) , <STR_LIT> , false , <NUM_LIT> ) ;


<s> N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0


<s> int had_to_push_lr ; rtx eh_ofs = cfun -> machine -> eh_epilogue_sp_ofs ; if ( return_used_this_function ) return <STR_LIT> ; for ( regno = <NUM_LIT> ; regno <= LAST_LO_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] && ! ( TARGET_SINGLE_PIC_BASE && ( regno == arm_pic_register ) ) ) live_regs_mask |= <NUM_LIT> << regno ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; regno ++ ) { if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] && ! ( TARGET_SINGLE_PIC_BASE && ( regno == arm_pic_register ) ) ) high_regs_pushed ++ ; } if ( high_regs_pushed ) { int mask = live_regs_mask ; int next_hi_reg ; int size ; int mode ; if ( current_function_return_rtx != <NUM_LIT> ) mode = GET_MODE ( current_function_return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; size = GET_MODE_SIZE ( mode ) ; if ( size < <NUM_LIT> ) mask |= <NUM_LIT> << <NUM_LIT> ; if ( mask == <NUM_LIT> ) internal_error ( <STR_LIT> ) ; for ( next_hi_reg = <NUM_LIT> ; next_hi_reg < <NUM_LIT> ; next_hi_reg ++ ) if ( regs_ever_live [ next_hi_reg ] && ! call_used_regs [ next_hi_reg ] && ! ( TARGET_SINGLE_PIC_BASE && ( next_hi_reg == arm_pic_register ) ) ) break ; while ( high_regs_pushed


<s> ret = rs6000_legitimize_address ( x , oldx , mode ) ; insns = get_insns ( ) ; end_sequence ( ) ; if ( ret != x ) { fprintf ( stderr , <STR_LIT> <STR_LIT> , GET_MODE_NAME ( mode ) , GET_RTX_NAME ( GET_CODE ( x )

) , GET_RTX_NAME ( GET_CODE ( ret ) ) ) ;


<s> static bool getMCRDeprecationInfo ( MCInst & MI , MCSubtargetInfo & STI , std :: string & Info ) { if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { Info =


<s> if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ?


<s> assert ( NarrowTy . isScalar ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( LaneIdxOp . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value ; MachineIRBuilder MIRBuilder ( I ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; MachineInstr * Extract = emitExtractVectorElt ( DstReg , DstRB , NarrowTy , SrcReg , LaneIdx , MIRBuilder ) ; if ( ! Extract


<s> case MOD : if ( mode == SFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case UDIV : case UMOD : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case SIGN_EXTEND : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ZERO_EXTEND : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case CONST_INT : * total = <NUM_LIT> ; break ; case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case CONST : { rtx offset = const0_rtx ; rtx symref = eliminate_constant_term ( XEXP ( x , <NUM_LIT> ) , & offset ) ; if ( GET_CODE ( symref ) == LABEL_REF ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_CODE ( symref ) != SYMBOL_REF ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( INTVAL ( offset ) < - <NUM_LIT> || INTVAL ( offset ) > <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( SYMBOL_REF_FLAG ( symref ) ? <NUM_LIT> : <NUM_LIT> ) ; break ; } case SYMBOL_REF : * total = COSTS_N_INSNS ( SYMBOL_REF_FLAG ( x )


<s> Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx + <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI


<s> static unsigned encodeVFPRm ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegM ) ; RegM = get<ISA_LIT>RegisterNumbering ( RegM ) ; if ( ! isSPVFP ) { Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT>


<s> bool sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( sh_cfun_interrupt_handler_p ( ) && ! df_regs_ever_live_p ( new_reg ) ) return false ; return true


<s> AddDefaultPred ( BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg0 ) . addReg ( ScratchReg0 ) . addImm ( <NUM_LIT> * TlsOffset ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg0 ) . addReg ( ScratchReg0 ) . addImm ( <NUM_LIT> ) ) ; AddDefaultPred ( BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg0 ) . addReg ( ScratchReg1 ) ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( postStackMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg0 ) . addImm ( AlignedStackSize ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg1 ) . addImm ( AlignTo<ISA_LIT>Constant ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( ScratchReg0 ) . addReg ( ScratchReg1 ) ; AddDefaultPred ( BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( postStackMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) . addReg ( ScratchReg0 ) . addReg ( ScratchReg1 ) ; postStackMBB -> addSuccessor ( & prologueMBB ) ; allocMBB -> addSuccessor ( postStackMBB ) ; checkMBB -> addSuccessor ( postStackMBB


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry (


<s> setLibcallName ( L , Name ) ; NoHelperNeeded . insert (


<s> if ( Subtarget -> isCallingConvWin64 ( CallConv ) ) { static const MCPhysReg GPR64ArgRegsWin64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return makeArrayRef ( std :: begin ( GPR64ArgRegsWin64 ) , std :: end ( GPR64ArgRegsWin64 ) ) ; } static const MCPhysReg GPR64ArgRegs64Bit [ ] =


<s> bool <ISA_LIT>RegisterInfo :: cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MFI -> hasCalls ( ) || ( MF . getTarget ( ) . Options

. DisableFramePointerElim ( MF ) && MFI -> adjustsStack ( ) ) ) return true ;


<s> Op -> FPImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> unsigned short Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned short


<s> if ( ( TARGET_PORTABLE_RUNTIME || ! TARGET_GAS || ! TARGET_SOM ) &&

! IN_NAMED_SECTION_P ( cfun -> decl ) ) {


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant

, const MCAsmInfo & MAI , const MCSubtargetInfo & STI ) {


<s> static __inline__ void \ NAME ( TYPE * _PTR , TYPE _VALUE ) \ { \ __asm__ volatile ( OPCODE <STR_LIT> \ : <STR_LIT>

( _PTR [ <NUM_LIT> ] ) \ : <STR_LIT> ( _VALUE ) , <STR_LIT> ( FC ) ) ; \ return ; \ }


<s> unsigned getIncomingArgSize ( ) const { return


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT . first * <NUM_LIT>


<s> for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = MaybeAlign ( cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Type * VecTy = cast < StructType > ( I . getType ( ) ) -> getElementType ( <NUM_LIT> ) ; unsigned Factor = Intrinsic == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( VecTy -> getContext ( ) , <STR_LIT> , Factor * <NUM_LIT> ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( VecTy -> getScalarSizeInBits ( ) / <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT>


<s> if ( getTargetMachine ( ) . getOptLevel ( ) != <NUM_LIT> && HasAtomicCmpXchg ) return


<s> void printdwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo ,


<s> assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT>


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg (


<s> NewMBB -> splice ( NewMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; return


<s> StringRef Suffix = getCPUSuffix ( Subtarget ) ; auto GenericName = Func . getName ( ) . str ( ) ; std :: string MASSVEntryName = GenericName + Suffix . str


<s> void insert ( unsigned BBNum , BasicBlockInfo BBI ) { BBInfo . insert ( BBInfo . begin ( ) + BBNum , BBI


<s> if ( ! MO . isReg ( ) ) { emitConstPoolAddress ( MO . getIndex ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; if ( Imm12 == INT32_MIN ) Imm12 = <NUM_LIT> ; bool isAdd = true ; if ( Imm12 < <NUM_LIT> ) { Imm12 = - Imm12


<s> if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [


<s> } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch64_bti_j_insn_p ( next ) ) continue ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch64_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = gen_bti_c ( )


<s> StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } if ( is<ISA_LIT>64 ( ) && ( CPU == <STR_LIT> || CPU == <STR_LIT> ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( ! is<ISA_LIT>64 ( ) && CPU == <STR_LIT> ) { Error ( L , <STR_LIT>


<s> explicit <ISA_LIT>AdvSIMDScalar ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>AdvSIMDScalarPass ( * PassRegistry :: getPassRegistry ( )


<s> SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; return SDValue ( Res , <NUM_LIT> ) ; } unsigned isDev = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! isDev ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; unsigned Op1 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op2 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op3 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Op4 = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ! Op1 && ! Op2 && ! Op3 && Op4 ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; if ( Op1 && ! Op2 && ! Op3 && ! Op4 ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ,


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return MCDisassembler :: Success


<s> } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) UseFP = true ; } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void ) Subtarget ; assert ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) && <STR_LIT> ) ; UseFP = true ; } else { if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return


<s> if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & * I ) ) { Sub = & * I ; break ; } if ( I == B ) return false ; } if ( ! MI && ! Sub ) return false ; if ( ! MI ) MI = Sub ; if ( isPredicated ( * MI ) ) return false ; SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) { if ( IsInstrVSel ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg

( D1 , getUndefRegState ( SrcIsUndef ) ) ;