<s> if ( SplatBitSize > <NUM_LIT> ) { MVT CVT = VT . getScalarType ( ) ; Constant * VecC = getConstantVector ( VT , SplatValue , SplatBitSize , * Ctx ) ; SDValue VCP = DAG . getConstantPool ( VecC , PVT ) ; unsigned NumElm = SplatBitSize / VT . getScalarSizeInBits ( ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( VCP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( <STR_LIT> ( CVT , NumElm ) , dl , DAG . getEntryNode ( ) , VCP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Brdcst = DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; return DAG . getBitcast ( VT , Brdcst ) ; } } } if ( ! Ld || NumElts - NumUndefElts != <NUM_LIT> ) return SDValue ( ) ; unsigned ScalarSize = Ld . getValueSizeInBits ( ) ; if ( ! ( UndefElements [ <NUM_LIT> ] || ( ScalarSize != <NUM_LIT> && ScalarSize != <NUM_LIT> ) ) ) return SDValue ( ) ; } bool ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; if ( ! ConstSplatVal && ! IsLoad && ! BVOp -> isOnlyUserOf ( Ld . getNode ( ) ) ) return SDValue ( ) ; unsigned ScalarSize = Ld . getValueSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; bool OptForSize = DAG . shouldOptForSize ( ) ; if ( ConstSplatVal && ( Subtarget . hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget . hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; MaybeAlign Alignment ( cast < ConstantPoolSDNode > ( CP ) -> getAlignment


<s> unsigned ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature =


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out ) { return CustomExpandInstNaCl<ISA_LIT> ( Inst , Out ,


<s> bool <ISA_LIT>XPLINKFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; <STR_LIT> SpillGPRs = ZFI -> getSpillGPRRegs ( ) ; DebugLoc DL ; if ( SpillGPRs . LowGPR ) { assert ( SpillGPRs . LowGPR != SpillGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , SpillGPRs . LowGPR , false ) ; addSavedGPR ( MBB , MIB , SpillGPRs . HighGPR , false ) ; MIB . addReg ( Regs . getStackPointerRegister ( )


<s> virtual bool gate ( function * ) { need_endbr = ( flag_cf_protection & CF_BRANCH ) !=


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * TargetBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( HasCondBranch ) FBB = TargetBB ; else TBB = TargetBB ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * TargetBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; TBB = TargetBB ; Cond . push_back ( MI . getOperand ( <NUM_LIT> )


<s> return StringSwitch < bool > ( Name . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true

) . Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRI ( SDValue Op , SDValue & Addr , SDValue & Base , SDValue & Disp ) { <ISA_LIT>RRIAddressMode AM ( true ) ; bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM , false ) ) return false ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM . BaseType == <STR_LIT>


<s> unsigned <ISA_LIT>CodeEmitter :: getJumpTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return


<s> while ( ( ( val <<= <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) ++ i ; return i ; } if ( ( val & <NUM_LIT> ) == <NUM_LIT> || ( val & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; i =


<s> error_at ( location , <STR_LIT> <STR_LIT> , fndecl , first_argno + <NUM_LIT> , get_scalar_type_name ( expected_type ) , argno + <NUM_LIT> , get_scalar_type_name ( actual_type ) ) ; return false


<s> return ( ( qword ) ( vec_rl ( ( vec_uint4 ) ( a ) , vec_splat (

( vec_uint4 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> break ; case E_VOIDmode : gcc_assert ( ! convert_p ) ; break ; default : gcc_unreachable ( ) ; } if ( ! v4sf_const0 ) v4sf_const0 = gen_reg_rtx ( V4SFmode ) ; rtx zero ; machine_mode dest_vecmode ; switch ( dest_mode ) { case E_HFmode : dest_vecmode = V8HFmode ; zero = gen_rtx_SUBREG ( V8HFmode , v4sf_const0 , <NUM_LIT> ) ; break ; case E_SFmode : dest_vecmode = V4SFmode ; zero = v4sf_const0 ; break ; case E_DFmode : dest_vecmode = V2DFmode ; zero = gen_rtx_SUBREG ( V2DFmode , v4sf_const0 , <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ; } src = gen_rtx_VEC_DUPLICATE ( dest_vecmode , src ) ; src = gen_rtx_VEC_MERGE ( dest_vecmode , src , zero , GEN_INT ( HOST_WIDE_INT_1U ) ) ; rtx vec = gen_reg_rtx


<s> if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL -> getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mang -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym =


<s> bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back (


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( )


<s> else if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveTLSDescCall ( DirectiveID


<s> if ( ! areOperandsOfVmullHighP64 ( II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ) return false ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 -> getOperand ( <NUM_LIT> ) , Ext2 -> getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; ShuffleVectorInst * Shuffle = dyn_cast < ShuffleVectorInst > ( Op ) ; if ( ! Shuffle || ! Shuffle -> isZeroEltSplat ( ) ) continue ; Value * ShuffleOperand = Shuffle -> getOperand ( <NUM_LIT> ) ; InsertElementInst * Insert = dyn_cast < InsertElementInst > ( ShuffleOperand ) ; if ( ! Insert ) continue ; Instruction * OperandInstr = dyn_cast < Instruction > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! OperandInstr ) continue ; ConstantInt * ElementConstant = dyn_cast < ConstantInt > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! ElementConstant || ElementConstant -> getZExtValue ( ) != <NUM_LIT> )


<s> SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHAllocStack ( SMLoc L ) { int64_t Size ; if ( parseImmExpr ( Size ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFIAllocStack ( Size ) ; return


<s> if ( Info . RegClass == <STR_LIT> || Info . RegClass == <STR_LIT> ) return <NUM_LIT> ; if ( Info . RegClass == <STR_LIT>


<s> static bool aarch64_vector_data_mode_p ( machine_mode mode ) { return aarch64_classify_vector_mode ( mode )


<s> if ( Kind != k_VectorList ) return false ; return VectorList . Count


<s> } assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI


<s> d = vec_xor ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b ) ) ; return ( ( qword ) ( vec_nor (


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) for ( std :: map < const char * , const llvm :: <STR_LIT> * > :: const_iterator it = <ISA_LIT>FI -> StubsNeeded . begin ( ) ; it != <ISA_LIT>FI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: <STR_LIT> * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) )


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; return AM . Scale == <NUM_LIT> || AM .


<s> bool <ISA_LIT>TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < <NUM_LIT> || DataSize > <NUM_LIT> ||

! isPowerOf2_32 ( DataSize ) ) return false ;


<s> case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Op = <STR_LIT> ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Op = <STR_LIT> ; bool writeback = ( P == <NUM_LIT> ) || ( W == <NUM_LIT> ) ; unsigned idx_mode = <NUM_LIT> ; if ( P && writeback ) idx_mode = <STR_LIT> ; else if ( ! P && writeback ) idx_mode = <STR_LIT> ; if ( writeback && ( Rn == <NUM_LIT> || Rn == Rt ) ) S = MCDisassembler :: SoftFail ; if ( reg ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Opc = <STR_LIT> ; switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; } unsigned amt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Opc == <STR_LIT> && amt == <NUM_LIT> ) Opc = <STR_LIT> ; unsigned imm = <STR_LIT> ( Op , amt , Opc , idx_mode ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; } else { Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; unsigned tmp = <STR_LIT> ( Op , imm , <STR_LIT> , idx_mode ) ; Inst . addOperand ( MCOperand :: CreateImm ( tmp ) ) ; } if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TopPart , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TopPart = CurDAG -> getCopyToReg ( TopPart , dl , <STR_LIT> , TopPart , SDValue ( ) ) . getValue ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue MulLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue MulRHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , CurDAG -> getRegister ( <STR_LIT>

, <STR_LIT> ) , SDValue ( Mul , <NUM_LIT> ) ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder ,


<s> case CmpInst :: ICMP_SGT : return <STR_LIT> ; case CmpInst :: ICMP_SGE : return <STR_LIT> ; case CmpInst :: ICMP_SLT : return <STR_LIT> ; case CmpInst :: ICMP_SLE : return <STR_LIT> ; case CmpInst :: ICMP_UGT : return <STR_LIT> ; case CmpInst :: ICMP_UGE : return <STR_LIT> ; case CmpInst :: ICMP_ULT : return <STR_LIT> ; case CmpInst ::


<s> return ( uint8x8_t ) ( ( __a & __b )


<s> static const TypeConversionCostTblEntry NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) ,

SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ;


<s> static bool IsCallReturnTwice ( llvm :: MachineOperand & MOp ) { if ( ! MOp . isGlobal ( ) ) return false ; auto * CalleeFn = dyn_cast < Function > ( MOp . getGlobal ( ) ) ; if ( ! CalleeFn ) return false ; AttributeList Attrs = CalleeFn -> getAttributes (


<s> unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT>


<s> __o = __builtin_aarch64_ld2rv2df ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregoiv2df (


<s> pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue BV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , BV ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Op = DAG . getVectorShuffle ( <STR_LIT> , dl , Op , DAG . getUNDEF ( <STR_LIT> ) , & ShufMask [ <NUM_LIT> ] ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , dl , OpLo , Undef , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( <STR_LIT> ,


<s> if ( TYPE_CANONICAL ( totype ) != NULL_TREE ) totype = TYPE_CANONICAL ( totype ) ; machine_mode frommode = TYPE_MODE ( fromtype ) ; machine_mode tomode = TYPE_MODE ( totype ) ; if ( frommode != tomode ) { if ( frommode == XOmode ) return N_ ( <STR_LIT> ) ; if ( tomode == XOmode ) return N_ ( <STR_LIT> ) ; if ( frommode == OOmode ) return N_ ( <STR_LIT> ) ; if ( tomode == OOmode ) return N_


<s> void <ISA_LIT>16InstrInfo :: loadRegFromStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand


<s> assert ( MCE && <STR_LIT> ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( encoding


<s> if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { unsigned AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Align ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg ) . addMemOperand ( MMO ) ; } else if ( CM == CodeModel :: Small || ! STI . is64Bit ( ) ) { unsigned PICBase = <NUM_LIT> ; if ( OpFlag == <STR_LIT>


<s> virtual const TargetRegisterInfo & getRegisterInfo ( )


<s> static unsigned int arm_function_arg_boundary ( machine_mode mode , const_tree type


<s> case <STR_LIT> : if ( <STR_LIT> ( OffVal ) == <STR_LIT> ) return false ; OffVal = <STR_LIT> ( OffVal ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : assert ( ( Fixup & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( ( ( OffVal * Scale + Fixup ) & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; OffVal += Fixup / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( OffVal <= Mask ) { if ( Updt ) MI -> getOperand ( ImmIdx ) . setImm ( OffVal ) ; return


<s> switch ( Op0 . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue NewLoad [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> , ie = Op0 . getNumOperands ( ) ; i != ie ; ++ i ) { SDValue LdOp = Op0 . getOperand ( i ) ; if ( LdOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( LdOp ) ; SDValue LoadOps [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) } ; NewLoad [ i ] = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LoadOps ,

LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;


<s> static DecodeStatus DecodeVMOVSRR ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) )


<s> SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT>

, <STR_LIT> ) , AhiBlo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> static MCDisassembler * create<ISA_LIT>elDisassembler ( const Target &


<s> return __builtin_mve_vrndpq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a ,


<s> if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; } if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL ,


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( ) { AlignmentIsInBytes = false ; Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; LCOMMDirectiveType = LCOMM :: NoAlignment ; HasLEB128 = true ; SupportsDebugInformation = true ; if ( Enable<ISA_LIT>EHABI ) ExceptionsType =


<s> void <ISA_LIT>RegisterInfo :: lowerVRSAVESpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> if ( Subtarget -> isTargetMachO ( ) ) { bool IsIndirect = ( TargetFlags & <STR_LIT> ) && Subtarget -> isGVIndirectSymbol ( GV ) ; if ( ! IsIndirect ) return getSymbol ( GV ) ; MCSymbol * MCSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> isThreadLocal ( ) ? MMIMachO . getThreadLocalGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; return MCSym ; } else if ( Subtarget -> isTargetCOFF ( ) ) { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & ( <STR_LIT> | <STR_LIT> ) ) ; if ( ! IsIndirect ) return getSymbol ( GV ) ; SmallString < <NUM_LIT> > Name ; if ( TargetFlags & <STR_LIT> ) Name


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget >


<s> Streamer . visitUsedExpr ( * getSubExpr (


<s> loongarch_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { loongarch_block_move_loop ( dest , src , INTVAL ( length ) , LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return


<s> assert ( VT != <STR_LIT> && <STR_LIT> ) ; if ( HasSSE2 && VT == <STR_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT>


<s> if ( t2MiscCtrlInstr ( insn ) ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns


<s> SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( <STR_LIT> ) ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI . CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( Subtarget . isSVR4ABI ( ) && ( SavedRegs . test ( <STR_LIT> ) || SavedRegs . test ( <STR_LIT>

) || SavedRegs . test ( <STR_LIT> ) ) ) {


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( EnableStackPointerTest ) { addPass ( createStackPointerTester ( get<ISA_LIT>TargetMachine ( ) ) ) ; } return false


<s> processFunctionBeforeFrameFinalized ( MachineFunction &


<s>
<ISA_LIT>FunctionInfo
*
AFI
=
MF
.
getInfo
<
<ISA_LIT>FunctionInfo
>
(
)
;
unsigned
UnspilledCSGPR
=
<STR_LIT>
;
unsigned
UnspilledCSGPRPaired
=
<STR_LIT>
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
unsigned
BasePointerReg
=
RegInfo
->
hasBasePointer
(
MF
)
RegInfo
->
getBaseRegister
(
)
:
(
unsigned
)
<STR_LIT>
;
unsigned
SpillEstimate
=
SavedRegs
.
count
(
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
++
i
)
{
unsigned
Reg
=
CSRegs
[
i
]
;
unsigned
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
Reg
==
BasePointerReg
)
SpillEstimate
++
;
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
SpillEstimate
++
;
}
SpillEstimate
+=
<NUM_LIT>
;
unsigned
StackEstimate
=
MFI
.
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
SpillEstimate
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
StackEstimate
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
unsigned
ExtraCSSpill
=
<NUM_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
++
i
)
{
const
unsigned
Reg
=
CSRegs
[
i
]
;
if
(
Reg
==
BasePointerReg
)
SavedRegs
.
set
(
Reg
)
;
bool
RegUsed
=
SavedRegs
.
test
(
Reg
)
;
unsigned
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<


<s> RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < ThumbLETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < ThumbBETargetMachine > B ( getTheThumbBETarget


<s> if ( ( ( FlagI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( FlagI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( FlagI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) || ( FlagI -> getOpcode ( ) == <STR_LIT> && OI -> getOpcode ( ) == <STR_LIT> ) ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( )

== SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ;


<s> } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS ,


<s> if ( ! Section ) { getStreamer ( ) . initSections ( false , getSTI ( ) ) ; Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } assert ( Section && <STR_LIT>


<s> if ( isBigEndian ) { insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; } else { insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] <<


<s> if ( ValTy -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned VF = ValTy -> getVectorNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumVectorRegs ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost


<s> if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , <NUM_LIT> ) ) ) term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateBarrier ( unsigned Val , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return


<s> return ( SetCCOpcode != <STR_LIT> ) && ( SetCCOpcode !=


<s> unsigned <ISA_LIT>TTI :: getMaxInterleaveFactor ( ) const { if ( ST -> isAtom ( ) )


<s> unsigned RegNo = getRegPair ( ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo


<s> return ( __mmask64 ) __builtin_ia32_kadddi ( ( __mmask64 )


<s> emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; } MI . setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI . tieOperands ( <NUM_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( coproc == <NUM_LIT> || coproc == <NUM_LIT> ) return MCDisassembler :: Fail ; break ; default : break ; } Inst . addOperand ( MCOperand :: CreateImm ( coproc ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( CRd ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm = <STR_LIT> ( U ? <STR_LIT> : <STR_LIT> , imm ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm |= U << <NUM_LIT> ; default : Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return lookup_attribute ( <STR_LIT> , attributes )


<s> unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ,


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec . getValueType ( ) ; SDValue Node = DAG . getNode ( <STR_LIT> , DL , WideTy , WideVec , Op . getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: isRunOfOnes ( unsigned Val , unsigned & MB , unsigned & ME ) { if ( isShiftedMask_32 ( Val ) ) { MB = countLeadingZeros ( Val ) ; ME = countLeadingZeros ( ( Val - <NUM_LIT> ) ^


<s> static alias_set_type ix86_GOT_alias_set ( void ) { static alias_set_type set = - <NUM_LIT> ; if ( set == - <NUM_LIT> ) set = new_alias_set ( ) ; return set


<s> auto * ElseMBB = CreateMBB ( ) ; MF -> insert ( InsPt , ElseMBB ) ; MBB = ElseMBB ; MBBI = MBB -> end ( ) ; } ; auto EmitCondJumpTarget = [ & ] ( unsigned CC , unsigned Target ) { auto * ThenMBB = CreateMBB ( ) ; TargetMBBs . push_back ( { ThenMBB , Target } ) ; EmitCondJump ( CC , ThenMBB ) ; } ; auto EmitTailCall = [ & ] ( unsigned Target ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( JTInst -> getOperand ( <NUM_LIT> + <NUM_LIT> * Target ) ) ; } ; std :: function < void ( unsigned , unsigned ) > EmitBranchFunnel = [ & ] ( unsigned FirstTarget , unsigned NumTargets ) { if ( NumTargets == <NUM_LIT> ) { EmitTailCall ( FirstTarget ) ; return ; } if ( NumTargets == <NUM_LIT> ) { CmpTarget ( FirstTarget + <NUM_LIT> ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget ) ; EmitTailCall ( FirstTarget + <NUM_LIT> ) ; return ; } if ( NumTargets < <NUM_LIT> ) { CmpTarget ( FirstTarget + <NUM_LIT> ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget + <NUM_LIT> ) ; EmitBranchFunnel ( FirstTarget + <NUM_LIT> , NumTargets - <NUM_LIT> ) ; return ; } auto * ThenMBB = CreateMBB ( ) ; CmpTarget ( FirstTarget + ( NumTargets / <NUM_LIT> ) ) ; EmitCondJump ( <STR_LIT> , ThenMBB ) ; EmitCondJumpTarget ( <STR_LIT> , FirstTarget + ( NumTargets / <NUM_LIT> ) ) ; EmitBranchFunnel ( FirstTarget + ( NumTargets / <NUM_LIT> ) + <NUM_LIT> , NumTargets - ( NumTargets / <NUM_LIT> ) - <NUM_LIT> ) ; MF -> insert ( InsPt , ThenMBB ) ; MBB = ThenMBB ; MBBI = MBB -> end


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> SelectionDAG & DAG = DCI . DAG ; if ( N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return SDValue (


<s> if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return SDValue ( ) ; SDValue ShiftRight = N -> getOperand ( <NUM_LIT> ) , Mask = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftRightOpc = ShiftRight . getOpcode ( ) ; if ( ShiftRightOpc != <STR_LIT> && ShiftRightOpc != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * CN ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( ShiftRight . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N ->


<s> bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = <NUM_LIT> ; bool FoundSrcOperand = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ) { FoldAsLoadDefReg =


) return new Darwin<ISA_LIT>AsmBackend ( T ) ;


<s> void <ISA_LIT>PassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( create<ISA_LIT>VSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( create<ISA_LIT>MIPeepholePass (


<s> return ( __m256i ) __builtin_ia32_mpsadbw256 ( ( __v32qi ) __X , (


<s> MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_MCSymbol : MCOp = LowerSymbolOperand ( MO , MO . getMCSymbol ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , Printer . GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , Printer . GetCPISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = LowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; } return


<s> static DecodeStatus DecodeSORegImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift =


<s> if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == <NUM_LIT> && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , <STR_LIT> ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_call_expr ( builtin_decl_implicit ( BUILT_IN_MEMCPY ) , <NUM_LIT> , dest_addr , addr , size_int ( rsize ) ) ; TREE_ADDRESSABLE ( tmp ) = <NUM_LIT> ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold_build_pointer_plus_hwi ( incr


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; --


<s> if ( VRM -> hasShape ( VirtReg ) ) return VRM -> getShape ( VirtReg ) ; const MachineOperand & Def = * MRI -> def_begin ( VirtReg ) ; MachineInstr * MI = const_cast < MachineInstr * > ( Def . getParent ( ) ) ; unsigned OpCode = MI -> getOpcode ( ) ; switch ( OpCode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MO2 = MI


<s> __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmpge ( a ,


<s> const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch


<s> Value * <ISA_LIT>TargetLowering :: getSDagStackGuard ( const Module & M


<s> if ( MI -> modifiesRegister ( BaseReg , TRI ) ) return false ; if ( TII -> isLdStPairSuppressed ( MI ) ) return false ; return


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return


<s> } else if ( isa < MCSymbolRefExpr > ( getImm ( ) ) ) { const MCSymbolRefExpr * SymbolRefExpr = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr && SymbolRefExpr -> getKind ( ) == MCSymbolRefExpr :: VK_None ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ShifterImmediate ) ; Op -> ShifterImm . isASR = isASR ; Op -> ShifterImm . Imm =


<s> TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; TmpInst . setLoc ( IDLoc


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindToken , Loc , Loc ) ; Op -> Token . Data = Str . data ( ) ; Op -> Token . Length = Str .


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG , SDLoc dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( <ISA_LIT>SubTarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && <ISA_LIT>SubTarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( FI ) ; SDValue Chain ; if ( i32Stack ) { MachineFunction & MF = DAG .


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: mips , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mipsel , true > Y ( The<ISA_LIT>elTarget , <STR_LIT> ,


<s> if ( special != SH_NONE && insn_entry [ uid ] . contains_subreg ) insn_entry [ uid ] . is_swappable = <NUM_LIT> ; else if ( special != SH_NONE ) insn_entry [ uid ] . special_handling = special ; else if ( insn_entry [ uid ] . contains_subreg ) insn_entry [ uid ] . special_handling = SH_SUBREG ; } } } } if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; dump_swap_insn_table ( insn_entry ) ; } unsigned e = get_max_uid ( ) , i ; for ( i = <NUM_LIT> ; i < e ; ++ i ) { if ( ! insn_entry [ i ] . is_relevant ) continue ; swap_web_entry * root = ( swap_web_entry * ) ( & insn_entry [ i ] ) -> unionfind_root ( ) ; if ( insn_entry [ i ] . is_live_in || insn_entry [ i ] . is_live_out || ( insn_entry [ i ] . contains_subreg && insn_entry [ i ] . special_handling != SH_SUBREG ) || insn_entry [ i ] . is_128_int || insn_entry [ i ] . is_call || ! ( insn_entry [ i ] . is_swappable || insn_entry [ i ] . is_swap ) ) root -> web_not_optimizable = <NUM_LIT> ; else if ( ( insn_entry [ i ] . is_load || insn_entry [ i ] . is_store ) && ! insn_entry [ i ] . is_swap && ! insn_entry [ i ] . is_swappable ) root -> web_not_optimizable = <NUM_LIT> ; else if ( insn_entry [ i ] . is_load && insn_entry [ i ] . is_swap ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! chain_contains_only_swaps ( insn_entry , link , FOR_LOADS ) ) { root -> web_not_optimizable = <NUM_LIT> ; break ; } } } else if ( insn_entry [ i ] . is_store && insn_entry [ i ] .


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue (


<s> unsigned int pure_scalable_type_info :: num_pr ( ) const { unsigned int res


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op .


<s> rtx x = widen_memory_access ( mem1 , mode , <NUM_LIT> ) ; MEM_NOTRAP_P ( x ) = MEM_NOTRAP_P ( mem1 ) && MEM_NOTRAP_P


<s> if ( ! isa < ConstantSDNode > ( N ) ) return false ; int64_t MulImm = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; if ( MulImm >= <NUM_LIT> && MulImm <= Max ) { MulImm *= Scale ; Imm = CurDAG -> getTargetConstant ( MulImm , SDLoc (


<s> return STI . getTargetTriple ( ) . getArch ( )


<s> assert ( ( CallTarget & <NUM_LIT> ) == CallTarget && <STR_LIT> ) ; unsigned ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = Opers . getMetaOper ( PatchPointOpers :: NBytesPos ) . getImm ( ) ; assert ( NumBytes >= EncodedBytes &&


<s> switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_subs_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_subs ( a


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _enqcmds ( void * __P , const void * __Q ) { return __builtin_ia32_enqcmds ( __P


<s> unsigned <ISA_LIT>InstrInfo :: GetInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode


<s> else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; else if ( ( FirstOpcode == <STR_LIT> || ( FirstOpcode == <STR_LIT> && FirstMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; return false


<s> if ( isWin64 ( ) ) { int HomeOffset = FrameLowering . getOffsetOfLocalArea ( ) + <NUM_LIT> ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , NumIntRegs * <NUM_LIT> + HomeOffset , false ) ) ; if ( NumIntRegs < <NUM_LIT> ) FuncInfo -> setVarArgsFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) ) ; } else { FuncInfo -> setVarArgsGPOffset ( NumIntRegs * <NUM_LIT> ) ; FuncInfo -> setVarArgsFPOffset ( ArgGPRs . size ( ) * <NUM_LIT> + NumXMMRegs * <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateStackObject ( ArgGPRs . size ( ) * <NUM_LIT> + ArgXMMs . size ( ) * <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { TheMachineFunction . getRegInfo ( ) . addLiveIn ( Reg ) ; LiveXMMRegs . push_back ( DAG . getRegister ( Reg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Offset = FuncInfo -> getVarArgsGPOffset ( ) ; for ( SDValue Val : LiveGPRs ) { SDValue FIN = DAG . getNode ( <STR_LIT> , DL , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) , RSFIN , DAG . getIntPtrConstant ( Offset , DL ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FuncInfo -> getRegSaveFrameIndex ( ) , Offset ) ) ; MemOps . push_back ( Store ) ; Offset += <NUM_LIT> ; } if ( ! LiveXMMRegs . empty (


<s> sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return BB


<s> return DAG . getMaskedStore ( MINode -> getChain ( ) , DL , Data , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , MINode -> getMemoryVT (

) , MINode -> getMemOperand ( ) , <STR_LIT> , false , false ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << MI -> getOperand ( OpNum ) . getImm ( ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q'


<s> bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL ,


<s> unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubReg1 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned SubReg2 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI -> getOperand ( <NUM_LIT> ) .


<s> dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] - bb . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] - bb . d [ <NUM_LIT> ] ; return ( ( qword ) ( dd . v


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> case E_TFmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; r3 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r3 = gen_rtx_EXPR_LIST ( VOIDmode , r3 , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1 , r3 ) ) ; case E_TCmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; r3 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r3 = gen_rtx_EXPR_LIST ( VOIDmode , r3 , GEN_INT


<s> EVT VT = Op . getValueType ( ) ; MFI . setFrameAddressIsTaken ( true ) ; if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { int FrameAddrIndex = FuncInfo -> getFAIndex ( ) ; if ( ! FrameAddrIndex ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; FrameAddrIndex = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ; } return DAG . getFrameIndex ( FrameAddrIndex , VT ) ; } unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; SDLoc dl ( Op ) ; unsigned Depth = Op .


<s> SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand (

<NUM_LIT> ) , FIdx , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> if ( Kind != k_Immediate && Kind != k_PostIndexRegister ) return false ; if ( Kind == k_PostIndexRegister ) return PostIdxReg


<s> int CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> set = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; set2 = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; } else return <NUM_LIT> ; if ( GET_CODE ( set ) != REG || REGNO ( set ) != FLAGS_REG ) return <NUM_LIT> ; if ( ! reg_overlap_mentioned_p ( set , PATTERN ( insn ) ) ) return <NUM_LIT> ; if ( set2 && reg_overlap_mentioned_p ( set2 , PATTERN ( insn ) )


<s> } if ( NextMIIt -> isDebugInstr ( ) ) { if ( User ) { assert ( NextMIIt -> isDebugValue ( ) && <STR_LIT> ) ; DbgValues . push_back ( & * NextMIIt ) ; } } else if ( User || ++ Count > <NUM_LIT> ) break ; } MachineInstr * LastMI = Selects . back ( ) ; bool CCKilled = ( LastMI -> killsRegister ( <STR_LIT> ) || checkCCKill ( * LastMI , MBB ) ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockAfter ( LastMI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; if ( ! CCKilled ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; createPHIsForSelects ( Selects , StartMBB , FalseMBB , MBB ) ; for ( auto SelMI : Selects ) SelMI -> eraseFromParent ( ) ; MachineBasicBlock :: iterator InsertPos = MBB -> getFirstNonPHI


<s> bool IsSmallMemAccess ( unsigned AccessSize ) { return AccessSize < <NUM_LIT>


<s> if ( VT == <STR_LIT> ) Op = Op8 ; else if ( VT == <STR_LIT> ) Op = Op16 ; else if ( VT == <STR_LIT> ) Op = Op32 ; else if ( VT == <STR_LIT> ) Op = Op64 ; else llvm_unreachable ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < AN -> getNumOperands ( ) ; ++ i ) Ops . push_back ( AN -> getOperand ( i ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( AN -> getOrdering ( ) , <STR_LIT> ) ) ; Ops . push_back ( AN ->


<s> bool <ISA_LIT>TTIImpl :: hasBranchDivergence ( ) { return


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , Vec


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT>


<s> <STR_LIT> CheriPurecapISA_EXT ( const <ISA_LIT>ABIInfo & ABI ) const { CheriCapabilityTableABI CTA = ABI . CapabilityTableABI ( ) ; if ( ( int ) CTA == <NUM_LIT> ) return <STR_LIT> ; switch ( CTA ) { case CheriCapabilityTableABI :: PLT : return <STR_LIT> ; case CheriCapabilityTableABI


<s> unsigned getHighSavedGPR ( ) const { return HighSavedGPR


<s> bool <ISA_LIT>TargetLowering :: directMoveIsProfitable ( const SDValue & Op ) const { SDNode * Origin = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Origin -> getOpcode ( ) != <STR_LIT> ) return true ; MachineMemOperand * MMO = cast < LoadSDNode > ( Origin ) ->


<s> MachineInstr & Last = * * I2 ; int64_t AddrDispShift ; assert ( calcInstrDist ( First , Last ) > <NUM_LIT> && <STR_LIT> ) ; if ( ! isReplaceable ( First , Last , AddrDispShift ) ) { ++ I2 ; continue ; } for ( auto UI = MRI -> use_begin ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags , MI . getOpcode ( ) ) + <STR_LIT> ( Desc ) ; MO . setReg ( First . getOperand ( <NUM_LIT> ) .


<s> replaceb = int_rtx ; } else { offset_rtx = int_rtx ; replacea = NULL_RTX ; replaceb = NULL_RTX ; } reg = gen_rtx_REG ( mode , regno ) ; addr = gen_rtx_PLUS ( Pmode , frame_reg , offset_rtx ) ; mem = gen_rtx_MEM ( mode , addr ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; insn = emit_move_insn ( mem


<s> char buf [ <NUM_LIT> ] ; fprintf ( file , <STR_LIT> , directive ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , value ) ; assemble_name ( file , buf ) ; fprintf ( file ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectPostStore ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys


<s> bool <ISA_LIT>CallEntry :: isAliased ( const MachineFrameInfo * ) const { return false


<s> const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; <ISA_LIT>FunctionInfo * FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; BitVector Spilled ( TRI -> getNumRegs ( ) ) ; VSRContainingGPRs . clear ( ) ; llvm :: for_each ( CSI , [ & ] ( const CalleeSavedInfo & Info ) { if ( Info . isSpilledToReg ( ) ) { auto & SpilledVSR = VSRContainingGPRs . FindAndConstruct ( Info . getDstReg ( ) ) . second ; assert ( SpilledVSR . second == <NUM_LIT> && <STR_LIT> ) ; if ( SpilledVSR . first == <NUM_LIT> ) SpilledVSR . first = Info . getReg ( ) ; else SpilledVSR . second = Info . getReg ( ) ; } } ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = <STR_LIT> <= Reg && Reg <= <STR_LIT> ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! Subtarget . is32BitELFABI ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { unsigned Dst = CSI [ i ] . getDstReg ( ) ; if ( Spilled [ Dst ] ) continue ; if ( VSRContainingGPRs [ Dst ] . second != <NUM_LIT> ) { assert ( Subtarget . hasP9Vector (


<s> return <NUM_LIT> ; case <STR_LIT> : Op = OR ; break ; case <STR_LIT> : Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . getSimpleVT ( ) . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I16 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI32 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI32 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I32 ] ; break ; case <STR_LIT> : Opc = AtomicOpcTbl [ Op ] [ I64 ] ; if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI64 ] ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ ConstantI64 ] ; } break ; } assert ( Opc != <NUM_LIT> && <STR_LIT> ) ; SDValue Ret ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode


<s> switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } default : return false ; } return false


<s> bool isShiftedImm ( ) const { return Kind


<s> return ( __m512i ) __builtin_ia32_pbroadcastd512_gpr_mask ( __A , (


<s> unsigned SrcReg , DstReg ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { SrcReg = DstReg = <STR_LIT> ; } else { SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> mayStore ( ) ) { assert ( DstReg == <STR_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; unsigned Pad = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isImplicit ( ) ) continue ; if ( MO . isUndef ( ) ) { assert ( RegList . empty ( ) && <STR_LIT> ) ; Pad += <NUM_LIT> ; continue ; } RegList . push_back ( MO . getReg ( ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } if ( MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: <ISA_LIT> ) { ATS . emitRegSave ( RegList , Opc == <STR_LIT> ) ; if ( Pad ) ATS . emitPad ( Pad ) ; } } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT>


<s> static bool mips_use_shadow_register_set_p (


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; return parseDirectiveLOH ( IDVal , Loc


<s> for ( cpu = & cpu_table [ <NUM_LIT> ] ; cpu -> name ; ++ cpu ) if ( ! strcmp ( sel -> string , cpu -> name ) ) { if ( sel -> set_tune_p ) sparc_cpu = cpu -> processor ; if ( sel -> set_arch_p ) { target_flags &= ~ cpu -> disable ; target_flags |= cpu -> enable ; } break ; } if ( ! cpu -> name ) error ( <STR_LIT> , sel -> string , sel -> name ) ; } } if ( fpu_option_set ) target_flags = ( target_flags & ~ MASK_FPU ) | fpu ; if ( ! TARGET_FPU ) target_flags &= ~ MASK_VIS ; if ( TARGET_VIS || TARGET_ARCH64 ) { target_flags |= MASK_V9 ; target_flags &= ~ ( MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE ) ; } if ( TARGET_V9 && TARGET_ARCH32 ) target_flags |= MASK_DEPRECATED_V8_INSNS ; if ( ! TARGET_V9 || TARGET_ARCH64 ) target_flags &= ~ MASK_V8PLUS ; if ( TARGET_ARCH32 ) target_flags &= ~ MASK_STACK_BIAS ; if ( align_functions == <NUM_LIT> && ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 ) ) align_functions = <NUM_LIT> ; if ( flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN ) flag_pcc_struct_return = ( TARGET_ARCH64 ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! TARGET_ARCH64 ) targetm . asm_out . unaligned_op . di = NULL ; sparc_init_modes ( ) ; sparc_sr_alias_set = new_alias_set ( ) ; struct_value_alias_set = new_alias_set ( ) ; init_machine_status = sparc_init_machine_status ; switch ( sparc_cpu ) { case PROCESSOR_V7 : case PROCESSOR_CYPRESS : sparc_costs = & cypress_costs ; break ; case PROCESSOR_V8 : case PROCESSOR_SPARCLITE : case PROCESSOR_SUPERSPARC : sparc_costs = & supersparc_costs ; break ; case PROCESSOR_F930 : case PROCESSOR_F934 : case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : sparc_costs = & hypersparc_costs ; break ; case PROCESSOR_SPARCLET : case PROCESSOR_TSC701 : sparc_costs = & sparclet_costs ; break ; case PROCESSOR_V9 : case PROCESSOR_ULTRASPARC : sparc_costs = & ultrasparc_costs ; break ; case PROCESSOR_ULTRASPARC3 : sparc_costs = &


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode2Operands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands


<s> unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfaRegister ( nullptr , SP ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm )


<s> NewBB -> getParent ( ) -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = llvm :: lower_bound ( WaterList , NewBB , compareMbbNumbers ) ; WaterList . insert ( IP , NewBB


<s> const GlobalValue * GV = N -> getGlobal ( ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( ! isPositionIndependent ( ) ) { if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , GA ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> Vec [ Pos ] = elem ; Pos = ( ( ( Pos ^ <NUM_LIT> ) + <NUM_LIT>


<s> Target & getThe<ISA_LIT>Target ( ) { static Target


<s> MCRegister Res = get<ISA_LIT>SubSuperRegisterOrZero ( Reg , Size , High ) ; assert ( Res != <STR_LIT> && <STR_LIT> ) ; return Res


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; assert ( TheTriple . isOSBinFormatELF ( ) &&


<s> Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { convertTo ( DL , <STR_LIT> , Op0 ) , convertTo ( DL , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , DL , <STR_LIT> ) } ; SDValue New = convertTo ( DL , VT , SDValue ( CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) , <NUM_LIT> ) ) ; ReplaceNode ( N , New .


<s> MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB ( MBBOpnd ) ; if ( Br -> hasDelaySlot ( ) ) { assert ( Br -> isBundledWithSucc ( ) ) ; MachineBasicBlock :: instr_iterator II = Br . getInstrIterator ( ) ; MIBundleBuilder ( & * MIB ) . append ( ( ++ II ) ->


<s> if ( VariableMask ) { auto * MaskTy = FixedVectorType :: get ( Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , VF ) ; MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; InstructionCost ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; InstructionCost BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } InstructionCost MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; InstructionCost InsertExtractCost = <NUM_LIT>


<s> <ISA_LIT>TargetMachine :: registerAsmPrinter (


<s> if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; int Cost = <ISA_LIT>TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ?

static_cast < int > ( TTI :: TCC_Free ) : Cost ;


<s> { <NUM_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> }


<s> SDValue V = Insert128BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , dl ) ; return Insert128BitVector ( V , V2 , NumElems


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; int reg_size = TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ; int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn )


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , bool IsLittleEndian , uint8_t


<s> static bool hasSameArgumentList ( const Function * CallerFn , ImmutableCallSite * CS ) { if ( CS -> arg_size ( ) != CallerFn -> arg_size ( ) ) return false ; ImmutableCallSite :: arg_iterator CalleeArgIter = CS -> arg_begin (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv ::


<s> bool isPICBase = false ; for ( MachineRegisterInfo :: def_instr_iterator I = MRI . def_instr_begin ( BaseReg ) , E = MRI . def_instr_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = & * I ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true


<s> SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent (


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_SJLJ_LONGJMP ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc DL = Op


<s> const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx


<s> Register stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr ; R2 = CurDAG -> getRegister ( <STR_LIT> , TLI -> getPointerTy ( ) ) ; return true


<s> virtual void emitLocalEntry ( MCSymbol * S , const


<s> return ( vector unsigned char ) __builtin_altivec_vmrglb ( ( vector signed char


<s> static inline bool isOptNone ( const MachineFunction & MF ) { return MF . getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeNone ) || MF . getTarget ( )

. getOptLevel ( ) == CodeGenOpt :: None ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) ,


<s> if ( isRIPRelative ( Inst , MCII ) ) return false ; <STR_LIT> FIK = <STR_LIT> ( Inst . getOpcode (


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) { const TargetRegisterClass * UseRC = ( RC == &


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseACC64DSP ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegs ( Operands , ( int


<s> if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; if ( ! Op -> hasOneUse ( ) ) return SDValue ( ) ; SDNode * N = Op . getNode ( ) ; SDLoc DL ( N ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; DenseMap < SDValue , unsigned > VecInMap ; SmallVector < SDValue , <NUM_LIT> > VecIns ; EVT VT = <STR_LIT> ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVectorImpl < SDValue > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) )


<s> bool <ISA_LIT>FunctionInfo :: needsDwarfUnwindInfo ( ) const { if ( ! NeedsDwarfUnwindInfo ) NeedsDwarfUnwindInfo = MF . needsFrameMoves ( ) && ! MF

. getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ;


<s> rtx lr = gen_rtx_REG ( Pmode , LR_REGNUM ) ; emit_move_insn ( lr , val ) ; emit_insn ( GEN_FCN ( CODE_FOR_xpaclri )


<s> RegBegin = TRI -> getSubReg ( RegBegin , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( RegBegin ) ; unsigned RegOps = OpNum + <NUM_LIT> ; while ( MI -> getOperand ( RegOps ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( RegOps ) . getReg ( ) ) ; RegOps ++ ; } O << <STR_LIT> ; return false ; } case 'R' : case 'Q' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; unsigned RC ; InlineAsm :: hasRegClassConstraint ( Flags , RC ) ; if ( RC == <STR_LIT> ) { if ( NumVals != <NUM_LIT> ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! MO . isReg ( ) ) return true ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; unsigned Reg = TRI -> getSubReg ( MO . getReg ( ) , ExtraCode [ <NUM_LIT> ] == 'Q' ? <STR_LIT> : <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = ExtraCode [ <NUM_LIT> ] == 'Q' ? OpNum : OpNum + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } case 'e' : case 'f' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) return true ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; unsigned SubReg = TRI -> getSubReg ( Reg , ExtraCode [ <NUM_LIT> ] == 'e' ? <STR_LIT> : <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( SubReg ) ; return false ; } case 'h' : return true ; case 'H'


<s> int64_t Shift = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT>


<s> MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( Op0 != Op1 && KillsOp1 ) { freeStackSlotAfter ( I ,


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm


<s> <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; Register Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill


<s> bool <ISA_LIT>TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal )


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPic0 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Pic = false ; Flags &= ~ ELF ::


<s> MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI . getDesc ( ) . getNumOperands ( ) + <NUM_LIT> - MI . getDesc ( ) . getSize ( ) && <STR_LIT> <STR_LIT> ) ; MI . setDesc ( * MCID ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; if ( Subtarget -> isThumb1Only ( ) ) { for ( unsigned c = MCID -> getNumOperands ( ) - <NUM_LIT> ; c -- ; ) { MI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . removeOperand ( <NUM_LIT> ) ; } for ( unsigned i = MI . getNumOperands ( ) ; i -- ; ) { const MachineOperand & op = MI . getOperand ( i ) ; if ( op . isReg ( ) && op . isUse ( ) ) { int DefIdx = MCID -> getOperandConstraint ( i , MCOI :: TIED_TO ) ; if ( DefIdx != - <NUM_LIT> ) MI . tieOperands ( DefIdx , i ) ; } } MI . addOperand ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; ccOutIdx = <NUM_LIT> ; } else ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; } else ccOutIdx = MCID ->