<s> unsigned <ISA_LIT>ABIInfo :: GetNullPtr


<s> unsigned Opc = BBI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) continue ; if ( ! BBI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) continue ; assert ( BBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BBI -> dump ( ) ; ) ; Register Reg = BBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = BBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand * DeadOrKillToUnset = nullptr ; if ( BBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { DeadOrKillToUnset = & BBI -> getOperand ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * BBI << <STR_LIT> ) ; } for ( auto AfterBBI = std :: next ( BBI ) ; AfterBBI != MBB . instr_end ( ) ; ++ AfterBBI ) { int KillIdx = AfterBBI -> findRegisterUseOperandIdx ( Reg , true , TRI ) ; if ( KillIdx != - <NUM_LIT> ) { assert ( ! DeadOrKillToUnset && <STR_LIT> ) ; DeadOrKillToUnset = & AfterBBI -> getOperand ( KillIdx ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; } if ( ! AfterBBI -> modifiesRegister ( Reg , TRI ) ) continue ; assert ( DeadOrKillToUnset && <STR_LIT> ) ; if ( AfterBBI -> getOpcode ( ) != Opc ) break ; assert ( AfterBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( ! AfterBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) || AfterBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != Imm ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * DeadOrKillToUnset -> getParent ( ) ) ; if ( DeadOrKillToUnset -> isDef ( ) ) DeadOrKillToUnset -> setIsDead ( false ) ; else DeadOrKillToUnset -> setIsKill ( false ) ; DeadOrKillToUnset = AfterBBI -> findRegisterDefOperand ( Reg , true , true , TRI ) ; if ( DeadOrKillToUnset ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; InstrsToErase . insert ( & * AfterBBI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AfterBBI -> dump ( ) ) ; } } for ( MachineInstr * MI : InstrsToErase ) { MI -> eraseFromParent


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , PtrVT , Offset ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , PtrVT


<s> report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( Chain , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; <STR_LIT> opcode =


<s> static const MachineOperand & getLoadStoreBaseOp ( const


<s> if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . ashr ( ShiftAmt ) , dl


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; } else


<s> if ( SrcVT . isVector ( ) ) return SDValue ( ) ; assert ( SrcVT . getSimpleVT ( ) <= <STR_LIT> && SrcVT . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ; } DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ::

getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ;


<s> Func = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getEntryNode ( ) , DescAddr ) ; SDValue Glue ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DescAddr , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * A64RI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = A64RI -> getTLSDescCallPreservedMask ( ) ; std :: vector < SDValue > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Func ) ; Ops . push_back ( SymAddr ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( Glue )


<s> if ( mips_hard_regno_mode_ok ( ST_REG_FIRST , mode ) ) size = MIN ( size , <NUM_LIT> ) ; left &= ~ reg_class_contents [ ST_REGS ] ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( mips_hard_regno_mode_ok ( FP_REG_FIRST , mode ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) size = MIN ( size , UNITS_PER_MSA_REG ) ; else size = MIN ( size , UNITS_PER_FPREG ) ; } left &= ~ reg_class_contents [ FP_REGS ] ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - <NUM_LIT> ) /


<s> MIRBuilder . buildUnmerge ( VRegs , ArgsReg ) ; setLeastSignificantFirst ( VRegs ) ; if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ; return true


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> getFrameLowering ( ) -> getTOCSaveOffset ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; } } else if ( CalleeMO . isGlobal


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << formatImm ( Op . getImm ( ) *


<s> } assert ( WidenedMask . size ( ) == <NUM_LIT> ) ; bool IsInsert = true ; int V2Index = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( WidenedMask [ i ] >= - <NUM_LIT> ) ; if ( WidenedMask [ i ] < <NUM_LIT> ) continue ; if ( WidenedMask [ i ] < <NUM_LIT> ) { if ( WidenedMask [ i ] != i ) { IsInsert = false ; break ; } } else { if ( V2Index >= <NUM_LIT> || WidenedMask [ i ] != <NUM_LIT> ) { IsInsert = false ; break ; } V2Index = i ; } } if ( IsInsert && V2Index >= <NUM_LIT> ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue Subvec = DAG . getNode ( <STR_LIT> , DL , SubVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return insert128BitVector ( V1 , Subvec , V2Index * <NUM_LIT> , DAG , DL ) ; } SDValue Ops [ <NUM_LIT> ] = { DAG . getUNDEF ( VT ) , DAG . getUNDEF ( VT ) } ; unsigned PermMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( WidenedMask [ i ] >= - <NUM_LIT> ) ; if ( WidenedMask [ i ] < <NUM_LIT> ) continue ; SDValue Op = WidenedMask [ i ] >=


<s> auto Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT LoadVT = ContainerVT ; EVT MemVT = Load -> getMemoryVT ( ) ; auto Pg = getPredicateForFixedLengthVector ( DAG , DL , VT ) ; if ( VT . isFloatingPoint ( ) && Load -> getExtensionType ( ) == <STR_LIT> ) { LoadVT = ContainerVT . changeTypeToInteger ( ) ; MemVT = MemVT . changeTypeToInteger ( ) ; } SDValue NewLoad = DAG . getMaskedLoad ( LoadVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Pg , DAG . getUNDEF ( LoadVT ) , MemVT , Load -> getMemOperand ( ) , Load -> getAddressingMode ( ) , Load -> getExtensionType ( ) ) ; SDValue Result


<s> return __builtin_mve_vqsubq_sv16qi ( __a ,


<s> case PROCESSOR_SUPERSPARC : cost = supersparc_adjust_cost ( insn , dep_type , dep , cost ) ; break ; case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : cost = hypersparc_adjust_cost ( insn , dep_type


<s> static void rs6000_secondary_reload_fail ( int line , rtx reg , rtx mem , rtx scratch , bool store_p ) { rs6000_secondary_reload_trace ( line , reg , mem , scratch , store_p ) ; gcc_unreachable (


<s> bool requiresRegisterScavenging ( const MachineFunction & MF


<s> rtx offset = NULL_RTX ; bool writeback = false ; bool ldp = false ; if ( ! INSN_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( get_load_info ( insn , loop , & dest , & base , & offset , & writeback , & ldp ) ) { tag_insn_info * i = new tag_insn_info ( insn , dest , base


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , <NUM_LIT> , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; int Offset = M -> getStackProtectorGuardOffset ( ) ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; StringRef GuardReg = M -> getStackProtectorGuardReg ( ) ; if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; else if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; return SegmentOffset ( IRB ,


<s> __o = __builtin_aarch64_ld3rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregciv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregciv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregciv4hi ( __o , <NUM_LIT> ) ; return ret


<s> const <ISA_LIT>Subtarget * <ISA_LIT>BaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( )


<s> r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , r12 ) ; } call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ]


<s> vld4_dup_u16 ( const uint16_t * __a ) { uint16x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o ,


<s> <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; bool Hash = getLexer ( ) . is ( AsmToken :: Hash ) ; if ( ! Hash && getLexer ( ) . isNot ( AsmToken :: Integer ) ) { if ( ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> || ShOp == <STR_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail


<s> int LEONMachineFunctionPass :: GetRegIndexForOperand ( MachineInstr & MI , int OperandIndex ) { if ( MI . getNumOperands ( ) > <NUM_LIT> ) { if ( OperandIndex == LAST_OPERAND ) { OperandIndex = MI . getNumOperands ( ) - <NUM_LIT> ; } if ( MI . getNumOperands ( ) > ( unsigned ) OperandIndex && MI . getOperand ( OperandIndex ) . isReg ( ) ) { return ( int ) MI . getOperand ( OperandIndex ) . getReg


<s> void addCheriAsmRegOperands ( MCInst & Inst , unsigned N


<s> return ( uint16x8_t ) __builtin_neon_vcvtmuv8hf


<s> Value * <ISA_LIT>TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia (


<s> getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { return Error ( L , <STR_LIT> ) ; } setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> SDValue Lane = Op1 . getOperand ( <NUM_LIT> ) ; EVT ResTy = N -> getValueType ( <NUM_LIT> ) ; EVT VecResTy ; SDLoc DL ( N ) ; assert ( Vec . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Vec . getValueType ( ) == <STR_LIT> ) VecResTy = <STR_LIT> ; else if ( Vec . getValueType ( ) == <STR_LIT> ) VecResTy = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Convert = DAG . getNode ( <STR_LIT> , DL , VecResTy , IID , Vec , Shift ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , Convert , Lane ) ; } return SDValue


<s> void relaxInstruction ( const MCInst & , llvm :: MCInst & ) const { llvm_unreachable (


<s> static DecodeStatus DecodeMISCRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler ::


<s> void <ISA_LIT>InstPrinter :: printPrefetchOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned prfop = MI -> getOperand ( OpNum ) . getImm (


<s> static void tryAddingPcLoadReferenceComment ( uint64_t Address , uint64_t Value , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; LLVMSymbolLookupCallback SymbolLookUp = Dis ->


<s> if ( isNullConstant ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; SDValue BR ; if ( CC == <STR_LIT> ) BR = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Chain , LHS , Dest ) ; else BR = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Chain , LHS , Dest ) ; DCI . CombineTo ( N , BR


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { VMask , Base , Scale , Index , Disp ,


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return <NUM_LIT> ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return false ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find (


<s> VPTBlock ( MachineInstr * MI , SetVector < MachineInstr * > & Preds ) { VPST = std :: make_unique < PredicatedMI


<s> unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; DebugLoc DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , TII . get ( MFLoOpc ) , VR0 ) . addReg ( Src ) ; TII . storeRegToStack ( MBB , I , VR0 , true , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( MFHiOpc ) , VR1 ) . addReg ( Src , SrcKill ) ; TII . storeRegToStack ( MBB , I , VR1 , true , FI


<s> p = stub_head ; while ( p != NULL ) { if ( p -> name [ <NUM_LIT> ] == * name && ! strcmp ( p -> name , name ) ) return ; p = p -> next ; } p = ggc_alloc < stub_list > ( ) ; p -> next = stub_head ; p -> name =


<s> if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == <NUM_LIT> || ( AM . Scale > <NUM_LIT> && ( uint64_t )


<s> switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Release : return nullptr


<s> else return <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; } else if ( reg_classes_intersect_p ( to , from ) ) return mode == TFmode ? <NUM_LIT> : <NUM_LIT> ; else return ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode ,


<s> Function * Intrinsic = <STR_LIT> ( F -> getParent ( ) , IntID , Types ) ; return CallInst :: Create ( Intrinsic -> getFunctionType ( ) , Intrinsic ,


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , Align Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; Cost += Factor * ( LT . first - <NUM_LIT> ) ; return Cost


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : Size - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ i ] < Size ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int Scale = <NUM_LIT> / Mask . size ( ) ; if ( Subtarget -> hasSSSE3 ( ) ) { Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo , DAG . getConstant ( Rotation * Scale , <STR_LIT> ) ) ) ; } int LoByteShift = <NUM_LIT> - Rotation * Scale ; int HiByteShift = Rotation * Scale ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; SDValue Part0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Part1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg (


<s> const SDNodeFlags Flags = N -> getFlags ( ) ; if ( Flags . hasVectorReduction ( ) ) { if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; if ( SDValue MAdd = combineLoopMAddPattern ( N , DAG , Subtarget ) ) return MAdd ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) &&

isHorizontalBinOp ( Op0 , Op1 , true ) ) {


<s> if ( ! SelectAddr ( Node , Ptr , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return <NUM_LIT> ; enum AtomicOpc Op ; switch ( Node -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : Op = OR ; break ; case <STR_LIT> : Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . getSimpleVT ( ) . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I16 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI32 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI32 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I32 ] ; break ; case <STR_LIT> : Opc = AtomicOpcTbl [ Op ] [ I64 ] ; if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI64 ] ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ ConstantI64 ] ; } break ; } assert ( Opc != <NUM_LIT> && <STR_LIT> ) ; SDValue Ret ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; if ( isUnOp ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Val , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops )


<s> if ( Ty -> isBFloatTy ( ) && ST -> hasBF16 ( ) ) return true ; if ( Ty -> isHalfTy ( ) || Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) return true ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) return true ; return


_mm512_load_epi64 ( void const * __P ) {


<s> if ( Region . readBytes ( Address , <NUM_LIT> , bytes ) == - <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb232 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } } MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFPV832 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address ,


<s> return ( uint16x4_t ) __builtin_neon_vqadduv4hi ( ( int16x4_t ) __a ,


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF


<s> unsigned Thumb2InstrInfo :: getUnindexedOpcode ( unsigned


<s> if ( GET_CODE ( symplt ) == UNSPEC && ( XINT ( symplt , <NUM_LIT> ) == UNSPEC_PLT || XINT ( symplt , <NUM_LIT> ) == UNSPEC_PCREL ) ) return XVECEXP ( symplt , <NUM_LIT> , <NUM_LIT> ) ; } } else if ( TARGET_SHMEDIA && ( XINT ( y , <NUM_LIT> ) == UNSPEC_EXTRACT_S16 || XINT ( y , <NUM_LIT> ) == UNSPEC_EXTRACT_U16 ) ) { rtx offset = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; x = gen_rtx_PLUS ( Pmode , XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) , offset ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x


<s> const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , RA ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , SP ) . addReg ( SP )


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg , getDefRegState ( true ) | getDeadRegState ( RegDeadKill ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) | getUndefRegState ( BaseUndef ) ) ; MIB . addImm ( Offset ) . addImm ( Pred


<s> rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > <NUM_LIT> ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = <NUM_LIT> << ( <NUM_LIT> - shift_amount - <NUM_LIT> ) ; and_constant = ( code == ASHIFT ? <NUM_LIT> - ( <NUM_LIT> << shift_amount ) : ( <NUM_LIT> << ( <NUM_LIT> - shift_amount ) ) - <NUM_LIT> ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode =


<s> if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned Reg = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; isKill = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( NewOffset == Offset + ( int ) Size && ( ( isAM4 && RegNum > PRegNum ) || RegNum == PRegNum + <NUM_LIT> ) ) { Offset += Size ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; PRegNum = RegNum ; } else { if ( MergeOps ( MBB , ++ Loc , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Regs ) ) { Merges . push_back ( prior ( Loc ) ) ; for ( unsigned j = SIndex ; j < i ; ++ j ) { MBB . erase ( MemOps [ j ] . MBBI ) ; MemOps [ j ] . Merged = true ; } } MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > Pos ) { Pos = MemOps [ i ] . Position ; Loc = MemOps [ i ] . MBBI ; } } bool BaseKill = Loc -> findRegisterUseOperandIdx ( Base , true ) != - <NUM_LIT> ; if ( MergeOps ( MBB , ++ Loc , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs ) ) { Merges . push_back ( prior


<s> return isLowringToMASSSafe ( Op ) && Flags . hasNoSignedZeros ( ) && Flags

. hasNoNaNs ( ) && Flags . hasNoInfs ( ) ;


<s> if ( MI -> getOperand ( OpNo ) . isReg ( ) ) printMemRegReg ( MI , OpNo ) ; else printMemRegImm ( MI , OpNo ) ; return


<s> Imm >>= shift ; if ( ! isAdd ) Imm = - ( uint32_t ) Imm ; Imm &= <NUM_LIT> ; if ( isAdd ) Imm |= <NUM_LIT> ; assert ( Qm < <NUM_LIT> && <STR_LIT> ) ; return ( Qm << <NUM_LIT> )


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = mode_for_int_vector ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSysCROperand ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; if ( getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Tok = getTok ( ) . getIdentifier ( ) ; if ( Tok [ <NUM_LIT> ] != 'c' && Tok [ <NUM_LIT> ] != 'C' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , <NUM_LIT> ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , a_tramp , Pmode , plus_constant (

Pmode , a_tramp , TRAMPOLINE_SIZE ) , Pmode ) ;


<s> case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand ::


<s> MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> unsigned rt = Is64BitMode ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( RelocOp -> getIndex ( ) , rt , RelocOp -> getOffset ( ) , PCAdj ) ; } else if ( RelocOp -> isJTI ( ) ) { unsigned rt = Is64BitMode ? <STR_LIT> : <STR_LIT> ; emitJumpTableAddress ( RelocOp -> getIndex ( ) , rt , PCAdj ) ; } else { assert ( <NUM_LIT> &&


<s> return __builtin_neon_vcmla270v8hf ( __r ,


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS << <STR_LIT>


<s> else O << <STR_LIT> ; break ; case <STR_LIT> : if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << LowercaseString ( getRegisterName ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : O << ( short int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; default : Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg + <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if ( restrict_addressing_modes_for_nacl ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return


<s> static bool isLDSTRO ( InsnType insn


<s> case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL


<s> SupportsDebugInformation = true ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AscizDirective =


<s> std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( InsertMask && isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SH = ( SHOpc == <STR_LIT> ) ? Value : <NUM_LIT>


<s> <STR_LIT> ET = getShiftExtendType ( ) ; bool IsSigned = ET == <STR_LIT> || ET == <STR_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( IsSigned ) ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNo , raw_ostream & O , const char * Modifier ) { const MCOperand & RegOp = MI -> getOperand ( OpNo ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( OffsetOp . isImm ( ) ) { O << OffsetOp . getImm ( ) ; } else { assert ( OffsetOp . isExpr ( ) && <STR_LIT> ) ; printExpr ( OffsetOp . getExpr ( ) , O ) ; } assert ( RegOp . isReg ( )


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI ) : MCELFStreamer ( Context ,


<s> addPass ( & EarlyIfConverterID ) ; return


<s> bool useNEONForSinglePrecisionFP ( )


<s> int DataWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( ( DataWidth < <NUM_LIT> ) || ( Consecutive == <NUM_LIT> ) ) return false ; if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( )


<s> SDValue CarryIn = Op . getOperand ( <NUM_LIT> ) ; SDVTList VTList = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue NotRHS = DAG . getNOT (


<s> SDValue Sad = createPSADBW ( DAG , SadOp0 , SadOp1 , DL , Subtarget ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , Sad . getValueSizeInBits ( ) / <NUM_LIT> ) ; Sad = DAG . getNode ( <STR_LIT> , DL , ResVT , Sad ) ; if ( VT . getSizeInBits ( ) > ResVT . getSizeInBits ( ) ) { assert ( VT . getSizeInBits ( ) % ResVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumConcats = VT . getSizeInBits ( ) / ResVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcats , DAG . getConstant ( <NUM_LIT> , DL


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None

) addPass ( create<ISA_LIT>OptimizeLEAs ( ) ) ;


<s> SDValue Base , Offset ; switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ; return false ; case InlineAsm :: Constraint_m : if ( selectAddrRegImm16 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ; return false ; case InlineAsm :: Constraint_R : if ( selectAddrRegImm9 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ; return false ; case InlineAsm :: Constraint_ZC : if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { if ( selectAddrRegImm12 ( Op ,


<s> case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = false ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case <STR_LIT> : Is64Bit = true ; return <STR_LIT> ; case


<s> SmallVector < MachineInstr * , <NUM_LIT> > Killed ; SmallVector < MachineInstr * , <NUM_LIT> > Dead ; if ( auto * Def = RDA -> getReachingMIDef ( LoLoop . Start , LoLoop . Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Visited ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Remove ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { LoLoop . Start , LoLoop . Dec , LoLoop . End , LoLoop . VCTP , LoLoop . InsertPt } ; SmallVector < MachineInstr * , <NUM_LIT> > Chain = { Def } ; while ( ! Chain . empty ( ) ) { MachineInstr * MI = Chain . back ( ) ; Chain . pop_back ( ) ; if ( IsSafeToRemove ( MI , RDA , Visited , Remove , Ignore ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . getReg ( ) == <NUM_LIT> ) continue ; if ( auto * Op = RDA -> getReachingMIDef ( MI , MO . getReg ( ) ) ) Chain . push_back ( Op ) ; } Ignore . insert ( MI ) ; } } LoLoop . ToRemove . insert ( Remove . begin ( ) , Remove . end ( ) ) ; } } MachineInstr * InsertPt = LoLoop . InsertPt ; MachineInstr * Start = LoLoop .


<s> std :: tie ( CallerAssignFnFixed , CallerAssignFnVarArg ) = getAssignFnsForCC ( CallerCC , TLI ) ; <ISA_LIT>IncomingValueAssigner CalleeAssigner ( CalleeAssignFnFixed , CalleeAssignFnVarArg ) ; <ISA_LIT>IncomingValueAssigner CallerAssigner ( CallerAssignFnFixed , CallerAssignFnVarArg ) ; if ( ! resultsCompatible ( Info , MF , InArgs , CalleeAssigner , CallerAssigner ) ) return false ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF ,


<s> } return false ; } ; if ( ! Disp ) { if ( ! isAtMemOperand ( ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( Disp , EndLoc ) ) return true ; assert ( ! isa < <ISA_LIT>MCExpr > ( Disp ) && <STR_LIT> ) ; } else { Disp = MCConstantExpr :: create ( <NUM_LIT> , Parser . getContext ( ) ) ; } } if ( ! parseOptionalToken ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , StartLoc , EndLoc ) ) ; else Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , StartLoc , EndLoc ) ) ; return false ; } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc BaseLoc = getLexer ( ) . getLoc ( ) ; const MCExpr * E ; StringRef ErrMsg ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) && getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseExpression ( E , EndLoc ) || check ( ! isa < <ISA_LIT>MCExpr > ( E ) , BaseLoc , <STR_LIT> ) ) return true ; BaseReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) return Error ( BaseLoc , <STR_LIT> , SMRange ( BaseLoc , EndLoc ) ) ; } if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( E , EndLoc ) ) return true ; if ( ! isa < <ISA_LIT>MCExpr > ( E ) ) { int64_t ScaleVal ; if ( ! E -> evaluateAsAbsolute ( ScaleVal , getStreamer ( ) . getAssemblerPtr ( ) ) ) return Error ( Loc , <STR_LIT> ) ; if ( ScaleVal != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } else { IndexReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( IndexReg == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { int64_t


<s> bool isTargetIOS ( ) const { return TargetTriple . getOS (


<s> <STR_LIT> Cond = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( SDValue V = performSetCCPunpkCombine ( N , DAG ) ) return V ; if ( Cond == <STR_LIT> && isZerosVector ( RHS . getNode ( ) ) && LHS -> getOpcode ( ) == <STR_LIT> && LHS -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) ) { if ( LHS -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && LHS -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) == Pred ) return LHS -> getOperand ( <NUM_LIT> ) ; if ( isAllActivePredicate ( DAG , Pred ) ) return LHS ->


<s> MCAsmBackend * llvm :: create<ISA_LIT>LEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU ,


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS


<s> if ( MatchAddressRecursively ( N , AM , <NUM_LIT> ) ) return true ; if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr ) { AM . Base_Reg = AM . IndexReg ; AM . Scale


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM , Reloc :: Model RM , bool JIT ) { if ( CM


<s> if ( ! VT . isSimple ( ) || ! VT . isInteger ( ) || VT . isVector ( ) ) return false ; unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ; return VTSize == <NUM_LIT> || VTSize == <NUM_LIT> ||


<s> return SelectAddrModeIndexed ( N , <NUM_LIT> ,


<s> case <STR_LIT> : SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const Value * Cond = SI -> getCondition ( ) ; bool NeedTest = true ; <STR_LIT> CC = <STR_LIT> ; if ( foldXALUIntrinsic ( CC , I , Cond ) ) NeedTest = false ; unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( NeedTest ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , CondReg , CondIsKill , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; emitICmp_ri ( <STR_LIT> , ANDReg , true , <NUM_LIT> ) ; } unsigned TrueReg = getRegForValue ( SI -> getTrueValue ( ) ) ; bool TrueIsKill = hasTrivialKill ( SI -> getTrueValue ( ) ) ; unsigned FalseReg = getRegForValue ( SI -> getFalseValue ( ) ) ; bool FalseIsKill = hasTrivialKill ( SI -> getFalseValue ( ) ) ; if ( ! TrueReg || ! FalseReg ) return false ; unsigned ResultReg = fastEmitInst_rri ( SelectOpc , RC , TrueReg , TrueIsKill , FalseReg


<s> Res = V ; } else { Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; } MCBinaryExpr :: Opcode Opcode ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; case AsmToken :: RBrac : getLexer ( ) . Lex ( ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return MatchOperand_Success ; case AsmToken :: Plus : Opcode = MCBinaryExpr :: Add ; break ; case AsmToken :: Minus : Opcode = MCBinaryExpr :: Sub ; break ; } getLexer ( ) . Lex ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: RBrac ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return MatchOperand_Success


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) ,


<s> unsigned i ; for ( i = <NUM_LIT> ; i != <NUM_LIT> && SVOp -> getMaskElt ( i ) < <NUM_LIT> ; ++ i ) ; if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; bool isLE = DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ; if ( ( ShuffleKind == <NUM_LIT> && ! isLE ) || ( ShuffleKind == <NUM_LIT> && isLE ) ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else if ( ShuffleKind ==


<s> switch ( Opcode ) { default : return DAG . getNode ( Opcode , dl , VT , Ops ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } SmallVector < SDValue , <NUM_LIT> > NewOps = {


<s> SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ,


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: addFullAddress ( const MachineInstrBuilder & MIB


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT>


<s> int <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { if ( IsPairwiseForm ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy =


<s> if ( ! MLxEntryMap . insert ( std :: make_pair ( <ISA_LIT>_MLxTable [ i ] . MLxOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ; MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . AddSubOpc


<s> return ( __m128i ) __builtin_ia32_cvttpd2udq128_mask ( ( __v2df ) __A , ( __v4si ) _mm_setzero_si128 ( ) , (


<s> } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( strong_zero_p ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , rval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x


<s> if ( MatchEvenMask ) CompactionMask = CompactionMaskEven ; else if ( MatchOddMask ) CompactionMask = CompactionMaskOdd ; else return SDValue ( ) ; SDValue UndefNode = DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Op0 = DAG . getVectorShuffle ( VT , dl , SVOp -> getOperand ( <NUM_LIT> ) , UndefNode , CompactionMask ) ; SDValue Op1 = DAG . getVectorShuffle ( VT , dl , SVOp -> getOperand ( <NUM_LIT> ) , UndefNode , CompactionMask ) ; static const int UnpackMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; addPass ( &


<s> assert ( MF . getName ( ) . startswith ( getThunkPrefix ( ) ) ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ & MF ] ( auto T ) { return T . Name == MF . getName ( ) ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; Register ThunkReg = ThunkIt -> Reg ; bool isThumb = ThunkIt -> isThumb ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear


<s> MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; unsigned ZExtCondReg = <NUM_LIT> ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( CI -> hasOneUse ( ) && CI -> getParent ( ) == I -> getParent ( ) ) { ZExtCondReg = createResultReg ( & <STR_LIT> ) ; if ( ! emitCmp ( ZExtCondReg , CI ) ) return false ; } } if ( ZExtCondReg == <NUM_LIT> ) { unsigned CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT> ) return


<s> static void InsertReturnAddressAuth ( MachineFunction & MF , MachineBasicBlock & MBB ) { if ( ! ShouldSignReturnAddress ( MF ) ) return ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB .


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - <NUM_LIT> , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass (


<s> unsigned Opcode = Node -> getOpcode ( ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } if ( trySelect ( Node ) ) return ; switch ( Opcode ) { default : break ; case <STR_LIT>


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectLoadFp64 ( SDNode * N ) { <STR_LIT> NVT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) . SimpleTy ; if ( ! Subtarget . is<ISA_LIT>1 ( ) || NVT != <STR_LIT> ) return NULL ; LoadSDNode * LN = cast < LoadSDNode > ( N ) ; if ( LN -> getExtensionType ( ) != <STR_LIT> || LN -> getAddressingMode ( ) != <STR_LIT> ) return NULL ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset0 , Offset1 , Base ; if ( ! SelectAddr ( N1 , Offset0 , Base ) || N1 . getValueType ( ) != <STR_LIT> ) return NULL ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N ) ->


<s> if ( ExtraCode [ <NUM_LIT> ] == 'N' && ! ExtraCode [ <NUM_LIT> ] && MO . isReg ( ) && <STR_LIT> . contains ( MO . getReg ( ) ) ) MCOp = MCOperand :: createReg ( MRI . getSubReg ( MO . getReg ( ) , <STR_LIT> ) ) ; else return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; } else { <ISA_LIT>MCInstLower Lower ( MF -> getContext ( )


<s> static int aarch64_register_move_cost ( machine_mode mode , reg_class_t from_i , reg_class_t to_i ) { enum reg_class from = ( enum reg_class ) from_i ; enum reg_class to = ( enum reg_class ) to_i ; const struct cpu_regmove_cost * regmove_cost = aarch64_tune_params . regmove_cost ; if ( to == TAILCALL_ADDR_REGS || to == POINTER_REGS ) to = GENERAL_REGS ; if ( from == TAILCALL_ADDR_REGS || from == POINTER_REGS ) from = GENERAL_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && hard_reg_set_subset_p ( reg_class_contents [ from_i ] , reg_class_contents [ FFR_REGS ] ) ) return <NUM_LIT> ; if ( ( from == GENERAL_REGS && to == STACK_REG ) || ( to == GENERAL_REGS && from == STACK_REG


<s> default : changeFPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS )


<s> case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable (


<s> bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) ITStates . push_back ( CCBits ) ; else ITStates . push_back ( CCBits ^


<s> void <ISA_LIT>Relocator :: applyDebugStringOffset ( Relocation & pReloc


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2div4sf (


<s> case <NUM_LIT> : OutStreamer -> EmitDTPRel32Value ( Value ) ; break ; case <NUM_LIT> : OutStreamer -> EmitDTPRel64Value


<s> InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; LoadedVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , LoadedVal , SubReg ) , <NUM_LIT> ) ; } ReplaceUses ( SDValue ( N , <NUM_LIT> )


<s> unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get ( AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insertAfter ( MachineBasicBlock :: iterator ( MI ) , CallseqEnd ) ; return BB


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeImm5S ( SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm ) { if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand


<s> int InstrDistance = <NUM_LIT> ; MachineBasicBlock :: iterator CurInst ; static const int INSTR_DISTANCE_THRESHOLD = <NUM_LIT> ; CurInst = I ; bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I !=


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Tmp = DAG . getConstantFP ( APF , dl , <STR_LIT> ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Tmp ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSelectCC ( dl , Op . getOperand ( <NUM_LIT> ) , Tmp , True , False , <STR_LIT> ) ; } } return SDValue ( ) ; } if ( Subtarget . hasDirectMove ( ) && Subtarget . is<ISA_LIT>64 ( ) ) return LowerFP_TO_INTDirectMove (


<s> LowOverheadLoop ( MachineLoop & ML , MachineLoopInfo & MLI , ReachingDefAnalysis & RDA , const TargetRegisterInfo & TRI , const <ISA_LIT>BaseInstrInfo & TII ) : ML ( ML ) , MLI ( MLI ) , RDA ( RDA ) , TRI ( TRI ) , TII ( TII ) , TPNumElements ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) { MF = ML . getHeader ( ) -> getParent ( ) ; if ( auto * MBB = ML . getLoopPreheader ( ) ) Preheader = MBB ; else if ( auto * MBB = MLI . findLoopPreheader ( & ML , true ) ) Preheader = MBB ; VPTState :: reset (


<s> if ( ATIndex == <NUM_LIT> ) { reportParseError ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned AT = getReg ( ( isGP64bit ( ) ) ? <STR_LIT> : <STR_LIT> , ATIndex ) ; return AT


<s> static DecodeStatus DecodeThumbCmpBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler ::


__C , const int __imm , const int __R ) {


<s> DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ; return true


<s> mode [ <NUM_LIT> ] = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; for ( i = <NUM_LIT> ; i < argcount ; i ++ ) { arg [ i ] = CALL_EXPR_ARG ( exp , i ) ; op [ i ] = expand_normal ( arg [ i ] ) ; mode [ i ] = insn_data [ icode ] . operand [ i ] . mode ; if ( code [ i ] == CONST_INT && GET_CODE ( op [ i ] ) != CONST_INT ) error ( <STR_LIT> , i + <NUM_LIT> ) ; if ( code [ i ] == REG && ! ( * insn_data [ icode ] . operand [ i ] . predicate ) ( op [ i ] , mode [ i ] ) ) op [ i ] = copy_to_mode_reg ( mode [ i ] , op [ i ] ) ; } if ( insn_data [ icode ] . operand [ <NUM_LIT> ] . constraint [ <NUM_LIT> ] == '=' ) { if ( target == <NUM_LIT> || GET_MODE ( target ) != mode [ <NUM_LIT> ] || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , mode [ <NUM_LIT> ] ) ) target = gen_reg_rtx ( mode [ <NUM_LIT> ] ) ; } else target = <NUM_LIT> ; switch ( argcount ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target ) ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> } else if ( TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx tmp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } else { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( vreg , tmp ) ; } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_conversion_insns ( seq , insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , REGNO ( vreg ) , DF_REF_INSN_UID ( ref ) ) ; } for ( ref = DF_REG_USE_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { replace_with_subreg_in_insn ( DF_REF_INSN ( ref ) , reg


<s> } else continue ; CountedExitBlock = * I ; ExitCount = EC ; break ; } if ( ! CountedExitBlock ) return MadeChange ; BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader || mightUseCTR ( TT , Preheader ) ) Preheader = InsertPreheaderForLoop ( L , this ) ; if ( ! Preheader ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ) ; MadeChange = true ; SCEVExpander SCEVE ( * SE , Preheader -> getModule ( ) -> getDataLayout ( ) , <STR_LIT> ) ; LLVMContext & C = SE -> getContext ( ) ; Type * CountType = TT . isArch64Bit ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; if ( ! ExitCount -> getType ( ) -> isPointerTy ( ) && ExitCount -> getType ( ) != CountType ) ExitCount = SE -> getZeroExtendExpr ( ExitCount , CountType ) ; ExitCount = SE -> getAddExpr ( ExitCount , SE -> getOne ( CountType ) ) ; Value * ECValue = SCEVE . expandCodeFor ( ExitCount , CountType , Preheader -> getTerminator ( ) ) ; IRBuilder < > CountBuilder ( Preheader -> getTerminator ( ) ) ; Module * M = Preheader -> getParent ( ) -> getParent ( ) ; Value * MTCTRFunc = <STR_LIT> ( M , <STR_LIT> , CountType ) ; CountBuilder . CreateCall ( MTCTRFunc , ECValue ) ; IRBuilder < > CondBuilder ( CountedExitBranch ) ; Value * DecFunc = <STR_LIT> ( M , <STR_LIT> ) ; Value * NewCond = CondBuilder . CreateCall ( DecFunc , { } ) ; Value * OldCond = CountedExitBranch -> getCondition ( ) ; CountedExitBranch -> setCondition ( NewCond


<s> if ( IsConstantInSmallSection ( C , * TM )


<s> if ( PPC405_ERRATUM77 ) { fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; } switch ( rs6000_sdata ) { case SDATA_NONE : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_DATA : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n'


<s> SDValue Mask = And -> getOperand ( <NUM_LIT> ) ; if ( Mask -> getOpcode ( ) == <STR_LIT> ) Mask = Mask -> getOperand ( <NUM_LIT> ) ; if ( Mask -> getOpcode ( ) != <STR_LIT> || Mask . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isAllOnesConstant ( Mask -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( Mask -> getOperand ( <NUM_LIT> ) ) && isAllOnesConstant ( Mask -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( Mask -> getOperand ( <NUM_LIT> ) ) ) return And -> getOperand ( <NUM_LIT> ) ; return SDValue ( ) ; } ; SDLoc dl ( N ) ; if ( SDValue Op0 = IsSignExt ( N0 ) ) { if ( SDValue Op1 = IsSignExt ( N1 ) ) { SDValue New0a = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) ; SDValue New1a = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( Op . getValueType ( ) . isScalableVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return SDValue (


<s> RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = <NUM_LIT> ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != <NUM_LIT> ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode


<s> assert ( m_pDynamic != NULL ) ; return *


<s> if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) ==


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> for ( auto & Arg : I -> operands ( ) ) { ArgListEntry Entry ; Entry . Val = Arg ; Entry . Ty = Arg -> getType ( ) ; Args . push_back ( Entry ) ; } CallLoweringInfo CLI ; CLI . setCallee ( TLI . getLibcallCallingConv ( LC ) , I -> getType ( ) , TLI . getLibcallName ( LC ) , std :: move ( Args ) ) ; if ( ! lowerCallTo ( CLI ) ) return false ; updateValueMap ( I , CLI


<s> bool <ISA_LIT>TTIImpl :: supportsEfficientVectorElementLoadStore ( ) const { return


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeS4Operand ( const MCInst * MI , unsigned Op , raw_ostream &


<s> auto Res = tryParseSVERegister ( RegNum , Kind , RegKind :: SVEPredicateVector ) ; if ( Res != MatchOperand_Success ) return Res ; unsigned ElementWidth = StringSwitch < unsigned > ( Kind . lower ( ) ) . Case ( <STR_LIT> , - <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! ElementWidth ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: SVEPredicateVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Slash ) ) return MatchOperand_Success ; if ( ! Kind . empty ( ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; auto Pred = Parser . getTok ( ) . getString ( ) . lower ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) { Error ( getLoc ( ) ,


<s> unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegLst == <NUM_LIT> ) return MCDisassembler :: Fail ; RegNum = RegLst & <NUM_LIT> ; if ( RegNum > <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) Inst . addOperand (

MCOperand :: createReg ( Regs [ i ] ) ) ;


<s> RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumbeb , true > B ( getTheThumbBETarget ( ) , <STR_LIT> , <STR_LIT> ,


<s> if ( vr4130_swap_insns_p ( ready [ nready - <NUM_LIT> ] , ready [ nready - <NUM_LIT> ] ) ) mips_promote_ready ( ready , nready


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ; return VectorList . Count == <NUM_LIT> && VectorList


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( TRI -> getAliasSet ( Reg ) [ <NUM_LIT> ] ) << ( ( ( Reg % <NUM_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; return false ; } return true ; case 'B' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ~ ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ( MI -> getOperand ( OpNum ) . getImm ( ) & <NUM_LIT> ) ; return false ; case 'M' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned RegBegin = MO .


<s> return __builtin_loongson_punpckhbh_u ( s ,


<s> static bool isVectorShift ( SDValue Op , SDValue Mask , SelectionDAG & DAG , bool & isLeft , SDValue & ShVal , unsigned & ShAmt ) { unsigned NumElems = Mask . getNumOperands ( ) ; isLeft = true ; unsigned NumZeros = getNumOfConsecutiveZeros ( Op , Mask , NumElems , true , DAG ) ; if ( ! NumZeros ) { isLeft = false ; NumZeros = getNumOfConsecutiveZeros ( Op , Mask , NumElems , false , DAG ) ; if ( ! NumZeros ) return false ; } bool SeenV1 = false ; bool SeenV2 = false ; for ( unsigned i = NumZeros ; i < NumElems ; ++ i ) { unsigned Val = isLeft ? ( i - NumZeros ) : i ; SDValue Idx = Mask . getOperand ( isLeft ? i : ( i - NumZeros ) ) ; if ( Idx . getOpcode ( ) == <STR_LIT> ) continue ; unsigned Index = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( Index < NumElems ) SeenV1 = true ; else { Index -= NumElems


<s> static bool CC_<ISA_LIT>_AAPCS_VFP_Custom_f16 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo ,

<STR_LIT> ArgFlags , CCState & State ) {


<s> assert ( M . getSimpleValueType ( ) . SimpleTy == C . getSimpleValueType ( ) . SimpleTy && <STR_LIT> ) ; return OR ( XOR ( ADD ( AND ( M , C ) , C )


<s> SMLoc S , E ; std :: unique_ptr < <ISA_LIT>Operand > LHS ; if ( parse<ISA_LIT>AsmOperand ( LHS ) != MatchOperand_Success ) return MatchOperand_NoMatch ; if ( LHS -> isImm ( ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , std :: move ( LHS ) ) ) ; return MatchOperand_Success ; } if ( ! LHS -> isIntReg ( ) ) { Error ( LHS -> getStartLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } AsmToken Tok = getLexer ( ) . getTok ( ) ; if ( Tok . is ( AsmToken :: Plus ) || Tok . is ( AsmToken :: Minus ) ) { ( void ) Parser . parseOptionalToken ( AsmToken :: Plus ) ; std :: unique_ptr < <ISA_LIT>Operand > RHS ; if ( parse<ISA_LIT>AsmOperand ( RHS ) != MatchOperand_Success ) return MatchOperand_NoMatch ; if ( RHS -> isReg ( ) && ! RHS -> isIntReg ( ) ) { Error ( RHS -> getStartLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( RHS -> isImm ( ) ? <STR_LIT> ( LHS -> getReg ( ) , std :: move ( RHS ) ) : <STR_LIT> ( LHS -> getReg ( ) , std :: move ( RHS ) ) ) ; return MatchOperand_Success ; } Operands . push_back ( <STR_LIT> ( LHS -> getReg ( ) , S ,


<s> return ( vector signed int ) __builtin_altivec_vcmpgefp ( ( vector float


<s> static SDValue lowerShuffleWithSSE4A ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , SelectionDAG & DAG ) { uint64_t BitLen , BitIdx ; if ( matchShuffleAsEXTRQ ( VT , V1 , V2 , Mask , BitLen , BitIdx , Zeroable ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , DAG . getTargetConstant ( BitLen , DL , <STR_LIT> ) , DAG . getTargetConstant ( BitIdx , DL , <STR_LIT> ) ) ; if ( matchShuffleAsINSERTQ ( VT , V1 , V2 , Mask , BitLen , BitIdx ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ? V1 : DAG . getUNDEF ( VT ) , V2 ? V2 : DAG . getUNDEF ( VT ) ,


<s> Value * <ISA_LIT>IREmitter :: visitUMLAL ( const SDNode


<s> return ( __m64 ) __builtin_ia32_pfpnacc ( ( __v2sf )


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Scalar . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) ) Scalar = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scalar ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> )


<s> unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) .

addOperand ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ;


<s> SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp2 . getNode ( ) ) return SDValue ( ) ; Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , Cmp , Cmp2 ) ; } Cmp = DAG . getSExtOrTrunc ( Cmp ,


<s> addPass ( create<ISA_LIT>RetpolineThunksPass (


<s> gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT &&

code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ;


<s> if ( TM . getTargetTriple ( ) . isOSBinFormatELF


<s> MCAsmBackend * llvm :: create<ISA_LIT>BEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple &


<s> typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_subv2si3 ( ( v2si ) mm


<s> if ( CurrI -> isDebugInstr ( ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> ; CurrI -> dump ( ) ) ; continue ; } if ( CurrI -> isBundle ( ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> ; CurrI -> dump ( ) ) ; RegDU . update ( * CurrI , <NUM_LIT> , CurrI -> getNumOperands ( ) ) ; continue ; } if ( terminateSearch ( * CurrI ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> ; CurrI -> dump ( ) ) ; break ; } assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; if ( InMicro<ISA_LIT>Mode && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler = CurrI ; LLVM_DEBUG ( dbgs ( )


<s> bool isS16Imm ( ) const { return isImm ( - <NUM_LIT>


<s> I = -- MBB . end ( ) ; return true ; } else return false ; } -- I ; return true


<s> void <ISA_LIT>DAGToDAGISel :: InsertVRSaveCode ( MachineFunction & Fn ) { bool HasVectorVReg = false ; for ( unsigned i = <NUM_LIT> , e = RegInfo -> getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RegInfo -> getRegClass ( Reg ) == & <STR_LIT> ) { HasVectorVReg = true ; break ; } } if ( ! HasVectorVReg ) return ; unsigned InVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; unsigned UpdatedVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & EntryBB = * Fn . begin ( ) ; DebugLoc dl ; MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) ,


<s> } } } if ( CC == <STR_LIT> ) { SDValue Flags ; <STR_LIT> CC0 , CC1 ; bool isAndSetCC ; if ( checkBoolTestAndOrSetCCCombine ( Cond , CC0 , CC1 , Flags , isAndSetCC ) ) { if ( isAndSetCC ) { std :: swap ( FalseOp , TrueOp ) ; CC0 = <STR_LIT> ( CC0 ) ; CC1 = <STR_LIT> ( CC1 ) ; } SDValue LOps [ ] = { FalseOp , TrueOp , DAG . getConstant ( CC0 , DL , <STR_LIT> ) , Flags } ; SDValue LCMOV = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , LOps ) ; SDValue Ops [ ] = { LCMOV , TrueOp , DAG . getConstant ( CC1 , DL , <STR_LIT> ) , Flags } ; SDValue CMOV = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; return CMOV ; } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && Cond . getOpcode ( ) == <STR_LIT> && isNullConstant ( Cond . getOperand ( <NUM_LIT> ) ) ) { SDValue Add = TrueOp ; SDValue Const = FalseOp ; if ( CC == <STR_LIT> ) std :: swap ( Add , Const ) ; if ( Const == Cond . getOperand ( <NUM_LIT> ) ) Const = Cond . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Const ) && Add . getOpcode ( ) == <STR_LIT> && Add . hasOneUse ( ) && isa < ConstantSDNode > ( Add . getOperand ( <NUM_LIT> ) ) && ( Add . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Add . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && Add . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) == Cond . getOperand ( <NUM_LIT> ) ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Diff = DAG . getNode ( <STR_LIT> , DL , VT , Const , Add . getOperand ( <NUM_LIT> ) ) ; SDValue CMov = DAG . getNode ( <STR_LIT> , DL , VT , Diff , Add . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Cond ) ; return DAG . getNode ( <STR_LIT> , DL , VT , CMov , Add . getOperand ( <NUM_LIT> ) ) ; } } return SDValue (


<s> xops [ <NUM_LIT> ] = gen_rtx_MEM ( Pmode , gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; SYMBOL_REF_FLAGS ( xops [ <NUM_LIT> ] ) |= SYMBOL_FLAG_LOCAL ; output_asm_insn ( <STR_LIT> , xops ) ; return <STR_LIT> ; } xops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , GOT_SYMBOL_NAME ) ; if ( ! flag_pic ) { if ( TARGET_MACHO ) gcc_unreachable ( ) ; xops [ <NUM_LIT> ] = gen_rtx_LABEL_REF ( Pmode , label ? label : gen_label_rtx ( ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER (

XEXP ( xops [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ;