<s> if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> << CFARegisterOffset << <STR_LIT> << RegOffsets [ <NUM_LIT> ] << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } uint32_t CompactUnwindEncoding = CU :: UNWIND_<ISA_LIT>_MODE_FRAME ; switch ( StackAdjust ) { case <NUM_LIT> : break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; default : DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } static struct { unsigned Reg ; unsigned Encoding ; } GPRCSRegs [ ] = { { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R6 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R5 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R4 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R12 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R11 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R10 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R9 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R8 } } ; int CurOffset = - <NUM_LIT> - StackAdjust ; for ( auto CSReg : GPRCSRegs ) { auto Offset = RegOffsets . find ( CSReg . Reg ) ; if ( Offset == RegOffsets . end ( ) ) continue ; int RegOffset = Offset -> second ; if ( RegOffset != CurOffset - <NUM_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << MRI . getName ( CSReg . Reg ) << <STR_LIT> << RegOffset << <STR_LIT> << CurOffset << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } CompactUnwindEncoding |= CSReg . Encoding ; CurOffset -= <NUM_LIT> ; } if ( FloatRegCount == <NUM_LIT> ) return CompactUnwindEncoding ; CompactUnwindEncoding &= ~ CU :: UNWIND_<ISA_LIT>_MODE_MASK ; CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_MODE_FRAME_D ; if ( FloatRegCount > <NUM_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << FloatRegCount << <STR_LIT> ) ; return CU ::


<s> if ( GET_CODE ( x ) == SYMBOL_REF && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { tree tr = SYMBOL_REF_DECL (


<s> bool <ISA_LIT>Subtarget :: GVRequiresRegister ( const GlobalValue * GV , const TargetMachine & TM , bool isDirectCall ) const { if ( GVRequiresExtraLoad ( GV , TM , isDirectCall ) ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return ! isDirectCall && ( GV -> hasLocalLinkage ( ) || GV -> hasExternalLinkage


<s> if ( auto LI = dyn_cast < LoadInst > ( I ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && LI -> getAlignment ( ) >= <NUM_LIT> ; if ( auto SI = dyn_cast < StoreInst > ( I ) ) return SI -> getValueOperand ( ) -> getType ( ) ->

getPrimitiveSizeInBits ( ) == <NUM_LIT> && SI -> getAlignment ( ) >= <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: shouldSplatInsEltVarIndex ( EVT VT


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Pred ) ; Ops . push_back


<s> if ( ! isTailPredicate ( Predicate , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Predicate << <STR_LIT> ) ; Predicates . insert ( Predicate ) ; InsertVCTPIntrinsic ( Predicate , NewPredicates , VecTy , NumElements ) ; } ClonedVCTPInExitBlock = Cleanup ( NewPredicates ,


<s> bool hasLegalDstDomain ( ) const { return ! LegalDstDomains . empty ( )


<s> case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addMemOperand ( MMO ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDefaultPred ( MIB . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT>


<s> return ! ST -> isTargetDarwin ( ) && ! ST -> hasMVEFloatOps


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> )

. Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld ,


<s> if ( ( DataWidth < <NUM_LIT> ) || ( Consecutive == <NUM_LIT> ) ) return false ; if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( ) ) return true ; return false


<s> if ( ! CSKY_ISA_FEATURE ( E2 ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , input ) ; input = operands [ <NUM_LIT> ] ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( mask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) { emit_insn ( gen_bclri ( operands [ <NUM_LIT> ] , input , GEN_INT ( i ) ) ) ; input = operands [ <NUM_LIT> ] ; } return true ; } for ( i = ( CSKY_ISA_FEATURE ( E2 ) ? <NUM_LIT> : <NUM_LIT> ) ; i < <NUM_LIT> ; i ++ ) { if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == mask ) { if ( CSKY_ISA_FEATURE ( <NUM_LIT> ) ) emit_insn ( gen_cskyv2_extzv ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , GEN_INT ( i ) , const0_rtx ) ) ; else { rtx shift = GEN_INT ( <NUM_LIT> - i ) ; rtx reg = ( reload_completed ? operands [ <NUM_LIT> ] : gen_reg_rtx ( SImode ) ) ; emit_insn ( gen_ashlsi3 ( reg , operands [ <NUM_LIT> ] , shift ) ) ; emit_insn ( gen_lshrsi3 ( operands [ <NUM_LIT> ] , reg , shift ) ) ; } return true ; } else if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == ~ mask ) { rtx shift = GEN_INT ( i ) ; rtx reg = ( reload_completed ? operands [ <NUM_LIT> ] : gen_reg_rtx ( SImode ) ) ; emit_insn ( gen_lshrsi3 ( reg , operands [ <NUM_LIT> ] , shift ) ) ; emit_insn ( gen_ashlsi3 ( operands [ <NUM_LIT> ] , reg , shift ) ) ; return true ; } } if ( ! reload_completed && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) { rtx reg = copy_to_mode_reg ( SImode , not_value ) ; if ( CSKY_ISA_FEATURE ( E2 ) ) emit_insn ( gen_cskyv2_andnsi3 ( operands [ <NUM_LIT> ] , reg , operands [ <NUM_LIT> ] ) ) ; else { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_ck801_andnsi3 ( operands [ <NUM_LIT> ] , reg , operands [ <NUM_LIT> ] ) ) ; } return true ; } if ( reload_completed ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; } else operands [ <NUM_LIT> ] = copy_to_mode_reg ( SImode , operands [ <NUM_LIT> ]


<s> static SDValue PerformSTORECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { StoreSDNode * St = cast < StoreSDNode > ( N ) ; if ( St -> isVolatile ( ) ) return SDValue ( ) ; SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( Subtarget -> hasNEON ( ) ) if ( SDValue Store = PerformTruncatingStoreCombine ( St , DCI . DAG ) ) return Store ; if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( SDValue NewToken = PerformSplittingToNarrowingStores ( St , DCI . DAG ) ) return NewToken ; if ( SDValue NewChain = PerformExtractFpToIntStores ( St , DCI . DAG ) ) return NewChain ; } if ( ! <STR_LIT> ( St ) ) return SDValue ( ) ; if ( StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> && StVal . getNode ( ) -> hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand ( <NUM_LIT> ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , IntVec . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , FloatVT , IntVec ) ; SDValue ExtElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , StVal . getOperand ( <NUM_LIT> ) ) ; dl = SDLoc ( N ) ; SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> unsigned int i , fcode = ARM_BUILTIN_CDE_PATTERN_START ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cde_builtin_data ) ; i ++ , fcode ++ ) { if ( ! TARGET_MAYBE_HARD_FLOAT && fcode >= ARM_BUILTIN_vcx1si ) break ; if ( ! TARGET_HAVE_MVE && fcode >= ARM_BUILTIN_vcx1qv16qi ) break ; arm_builtin_cde_datum * cde = & cde_builtin_data [ i


<s> if ( Size < <NUM_LIT> || Size > <NUM_LIT> ) return false ; unsigned R0 = RegList . List -> front ( ) ; unsigned R1 = RegList . List -> back ( ) ; if ( ! ( ( R0 == <STR_LIT> && R1 == <STR_LIT> ) || ( R0 == <STR_LIT> && R1 == <STR_LIT> ) ) ) return false ; int PrevReg = * RegList . List -> begin ( ) ; for ( int i = <NUM_LIT> ; i < Size - <NUM_LIT> ; i ++ ) { int Reg = ( * ( RegList . List ) ) [


<s> PHINode * Q = PHINode :: Create ( Int32Ty , P -> getNumIncomingValues ( ) , P -> getName ( ) , P ) ; for ( unsigned i = <NUM_LIT> ; i < P -> getNumOperands ( ) ; ++ i ) Q -> addIncoming ( Zero , P -> getIncomingBlock ( i ) ) ; return Q ; } Argument * A = dyn_cast < Argument > ( V ) ; Instruction * I = dyn_cast < Instruction > ( V ) ; assert ( ( A || I ) && <STR_LIT> ) ; auto InstPt = A ? & * A -> getParent ( ) -> getEntryBlock (


<s> unsigned FnSize = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) FnSize += TII


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Res = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT>


<s> unsigned Size = StringSwitch < unsigned > ( OpStr ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT>

, <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , - <NUM_LIT> ) . Default ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Op . dump ( ) ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerWRITE_REGISTER ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerPOT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( )


<s> bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || ( Op . getValueType ( ) != <STR_LIT> && Op . getValueType ( ) != <STR_LIT> ) ) return ; Op = SDValue ( DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Op , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> void <ISA_LIT>SEInstrInfo :: storeRegToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc =


<s> case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Value ) ; AddValueSymbolsImpl ( BE -> getLHS ( ) , Asm ) ; AddValueSymbolsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : Asm -> getOrCreateSymbolData ( cast < MCSymbolRefExpr > (


<s> case scalar_store : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_store [ <NUM_LIT> ] : ix86_cost -> int_store [ <NUM_LIT> ] ) / <NUM_LIT> ; case vector_stmt : return ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op , true ) ; case vector_load : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_load [ index ] ) / <NUM_LIT> , true ) ; case vector_store : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_store [ index ] ) / <NUM_LIT> , true ) ; case vec_to_scalar : case scalar_to_vec : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case unaligned_load : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / <NUM_LIT> , true ) ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / <NUM_LIT> , true ) ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / <NUM_LIT> , true ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / <NUM_LIT> , true ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case vec_construct : { int cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , false ) ; if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) cost += ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; else if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) cost += <NUM_LIT> * ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; return cost ; } default : gcc_unreachable (


<s> bool <ISA_LIT>InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } if ( Constraint [ <NUM_LIT> ] == '{' ) { if ( Constraint [ <NUM_LIT> ] == 'r' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'f' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint ,


<s> virtual bool isConditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst


<s> assert ( ExtElt -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> Opc ; SDValue Rdx = DAG . matchBinOpReduction ( ExtElt , Opc , { <STR_LIT> , <STR_LIT> } , true ) ; if ( ! Rdx ) return SDValue ( ) ; SDValue Index = ExtElt -> getOperand ( <NUM_LIT> ) ; assert ( isNullConstant ( Index ) && <STR_LIT> ) ; EVT VT = ExtElt -> getValueType ( <NUM_LIT> ) ; EVT VecVT = Rdx . getValueType ( ) ; if ( VecVT . getScalarType ( ) != VT ) return SDValue ( ) ; SDLoc DL ( ExtElt ) ; if ( ExperimentalVectorWideningLegalization && VecVT == <STR_LIT> ) { Rdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Rdx , DAG . getUNDEF ( VecVT ) ) ; Rdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Rdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Rdx = DAG . getBitcast ( <STR_LIT> , Rdx ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Rdx , Index ) ; } if ( ( VecVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> || ! isPowerOf2_32 ( VecVT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( VT == <STR_LIT> ) { while ( Rdx . getValueSizeInBits ( ) > <NUM_LIT> ) { unsigned HalfSize = VecVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned HalfElts = VecVT . getVectorNumElements ( ) / <NUM_LIT> ; SDValue Lo = extractSubVector ( Rdx , <NUM_LIT>


<s> ( RC == & <STR_LIT> ? & <STR_LIT> : RC ) ) ; return FastISel :: FastEmitInst_rr ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Op1 ,


<s> static SDValue combineShift ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftLeft ( N ,


<s> const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v2s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( auto BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) { for ( auto Ty : { s32 , s64 , v2s32 , v4s32 , v2s64 } ) setAction ( BinOp , Ty , Legal ) ; for ( auto Ty : { s8 , s16 } ) setAction ( BinOp , Ty , WidenScalar ) ; } for ( auto BinOp : { G_SHL , G_LSHR , G_ASHR , G_SDIV , G_UDIV } ) for ( auto Ty : { s32 , s64 } ) setAction ( BinOp , Ty , Legal ) ; for ( auto BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , s64 } ) setAction ( BinOp


<s> return ( __m128i ) __builtin_ia32_pbroadcastd128_gpr_mask ( __A , ( __v4si ) _mm_setzero_si128 ( )


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm ( ) ,


<s> TargetRegistry :: RegisterMCCodeGenInfo ( * T , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , createMachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } for ( Target * T : { & The<ISA_LIT>leTarget , & TheARM64Target } ) TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend (


<s> _Unwind_Word _Unwind_GetCFA ( _Unwind_Context * context ) { return ( ( phase1_vrs * ) context


<s> static bool loongarch_valid_pointer_mode ( scalar_int_mode mode ) { return mode == SImode || (


<s> using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <NUM_LIT> ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_SEXT : case G_ZEXT : OperandsMapping = & <STR_LIT> [ <NUM_LIT> ] ; break ; case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <NUM_LIT> ]


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> const __v8hu shmax = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v8hu result ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; shmask = rshift <= shmax ; result = vec_vsrh ( ( __v8hu ) __A , rshift ) ; result = vec_sel ( shmask , result , shmask ) ; return ( __m128i )


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( CC ) { default : break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , RHS , LHS , CC ) ; break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , LHS , RHS , CC ) ; break ; } if ( NegateFCC ( LHS , RHS , CC ) ) std :: swap ( TrueV , FalseV ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; ++ i ) { ShuffleMask . push_back ( <NUM_LIT> * i +


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea1Size ( ) ) ; } if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB


<s> static DecodeStatus DecodeF8RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst ,


<s> auto BHR = TargetInstrInfo :: CreateTargetMIHazardRecognizer ( II , DAG ) ; MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ; return


<s> unsigned StackAlign = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack ( MF )


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & Ops [ <NUM_LIT> ] , Ops . size


<s> if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t )


<s> if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder


<s> Value * <ISA_LIT>IREmitter :: visitWIN_ALLOCA ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } unsigned Alignment = <NUM_LIT> ; if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = ( * LoadMI -> memoperands_begin ( ) ) -> getAlignment ( ) ; else switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; SmallVector < MachineOperand , <ISA_LIT>AddrNumOperands > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const Type * Ty ; if ( LoadMI -> getOpcode ( ) == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( LoadMI -> getOpcode ( ) == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; Constant * C = LoadMI -> getOpcode ( ) ==

<STR_LIT> ? Constant :: getAllOnesValue ( Ty ) :


<s> void setReg ( unsigned Reg ) { assert ( isRegBase ( ) &&


<s> if ( Size == <NUM_LIT> ) return & <STR_LIT> [ <STR_LIT> ] ; MappingID = CustomMappingID ; return & <STR_LIT>


<s> if ( Triple ( TM . getTargetTriple ( ) ) . isOSNaCl ( ) ) { int Dummy ; if ( terminateSearch ( * I ) || ( IsDangerousLoad ( * I , & Dummy ) || IsDangerousStore ( * I , & Dummy ) || I -> modifiesRegister ( <STR_LIT> , TM . getRegisterInfo ( ) ) ) ) break ; } else { if ( terminateSearch ( * I ) ) break ; } assert ( ( ! I -> isCall ( ) && ! I -> isReturn ( ) && ! I -> isBranch ( ) ) && <STR_LIT> ) ; if ( delayHasHazard ( * I , RegDU , IM ) ) continue ; Filler = I ; return


<s> if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? <STR_LIT>


<s> void setGlobalValue ( const GlobalValue * G ) { GV =


<s> gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && mode == GET_MODE ( pred1 [ <NUM_LIT> ] ) && aarch64_sve_gp_strictness ( pred1 [ <NUM_LIT> ] , SImode ) ) ; return ( pred1 [ <NUM_LIT> ] == CONSTM1_RTX ( mode ) || INTVAL ( pred1 [


<s> gcc_assert ( code == EQ || code == NE ) ; tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_XOR ( mode , op0 , op1 ) ) ) ; tmp = gen_lowpart ( p_mode , tmp ) ; emit_insn ( gen_rtx_SET ( gen_rtx_REG ( CCmode , FLAGS_REG ) , gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , tmp , tmp ) , UNSPEC_PTEST ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , flag , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; return ; } switch ( mode ) { case SFmode : case DFmode : case XFmode : case QImode : case HImode : case SImode : simple : tmp = ix86_expand_compare ( code , op0 , op1 ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; return ; case DImode : if ( TARGET_64BIT ) goto simple ; if ( ! optimize_insn_for_size_p ( ) && TARGET_STV && ( code == EQ || code == NE ) ) { op0 = force_reg ( mode , gen_rtx_XOR ( mode , op0 , op1 ) ) ; op1 = const0_rtx ; } case TImode : { rtx lo [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ; rtx_code_label * label2 ; enum rtx_code code1 , code2 , code3 ; machine_mode submode ; if ( CONSTANT_P ( op0 ) && ! CONSTANT_P ( op1 ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } split_double_mode ( mode , & op0 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; split_double_mode ( mode , & op1 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; submode = mode == DImode ? SImode : DImode ; if ( ( code == EQ || code == NE ) && ( ! optimize_insn_for_size_p ( ) || hi [ <NUM_LIT> ] == const0_rtx || lo [ <NUM_LIT> ] == const0_rtx ) ) { rtx xor0 , xor1 ; xor1 = hi [ <NUM_LIT> ] ; if ( hi [ <NUM_LIT> ] != const0_rtx ) xor1 = expand_binop ( submode , xor_optab , xor1 , hi [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; xor0 = lo [ <NUM_LIT> ] ; if ( lo [ <NUM_LIT> ] != const0_rtx ) xor0 = expand_binop ( submode , xor_optab , xor0 , lo [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp = expand_binop ( submode , ior_optab , xor1 , xor0 , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN


<s> static SDValue combineKSHIFT ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getAllOnes ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , DCI ) ) return SDValue (


<s> SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B . getOperand ( <NUM_LIT> ) ; if ( NegC ) C = C . getOperand ( <NUM_LIT> ) ; unsigned Opcode ; if ( ! NegMul ) Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , dl ,


<s> bool mips_small_data_pattern_p ( rtx op ) { return mips_small_data_pattern_1 ( op , SYMBOL_CONTEXT_LEA


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr


<s> __arm_sqrshrl ( int64_t value , int32_t shift ) { return __builtin_mve_sqrshrl_sat64_di ( value , shift


<s> if ( N -> getNumOperands ( ) == <NUM_LIT> ) return PerformVMOVDRRCombine ( N


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize

, MCInst & MI , const MCDisassembler * Decoder ) {


<s> end_sequence ( ) ; push_topmost_sequence ( ) ; for ( scan = get_insns ( ) ; scan != NULL_RTX ; scan = NEXT_INSN ( scan ) ) if ( NOTE_P ( scan ) && NOTE_LINE_NUMBER ( scan ) == NOTE_INSN_FUNCTION_BEG ) break ; if ( scan == NULL_RTX ) scan = get_insns ( ) ; insn = emit_insn_after ( insn , scan ) ; pop_topmost_sequence ( ) ; } return cfun -> machine


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterAsmParser < <ISA_LIT>ATTAsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterAsmParser < <ISA_LIT>ATTAsmParser > Y ( The<ISA_LIT>_64Target


<s> ReachableNodes . clear ( ) ; std :: function < void ( const Node * , bool ) > FindReachableNodes = [ & ] ( const Node * N , bool FirstNode ) { if ( ! FirstNode ) ReachableNodes . insert ( * N ) ; for ( const Edge & E : N -> edges ( ) ) { const Node * Dest = E . getDest ( ) ; if ( MachineGadgetGraph :: isCFGEdge ( E ) && ! ElimEdges . contains ( E ) && ! ReachableNodes . contains ( * Dest ) ) FindReachableNodes ( Dest , false ) ; } } ; FindReachableNodes ( & RootN , true ) ; for ( const Edge & E : RootN . edges ( ) ) { if ( MachineGadgetGraph :: isGadgetEdge ( E ) ) { if ( ReachableNodes . contains ( * E . getDest ( ) ) ) { ++ RemainingGadgets ; } else { ElimEdges . insert ( E ) ; } } } } return RemainingGadgets


<s> MaskInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; MaskInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; MaskInst . addOperand ( MCOperand :: CreateReg


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2


<s> bool isSrcIdx16 ( ) const { return isMem16 ( ) && isSrcIdx ( )


<s> static void initTIs ( Module & M , std :: tuple

< ThunkInserterT ... > & ThunkInserters ) {


<s> if ( NeedsDwarfCFI ) { unsigned DwarfStackPtr = TRI -> getDwarfRegNum ( Is64Bit ? <STR_LIT> : <STR_LIT> , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfa ( nullptr , DwarfStackPtr , - SlotSize ) ) ; -- MBBI ; } } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , DL , NumBytes , true ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaOffset ( nullptr , - CSSize - SlotSize ) ) ; } -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { MBBI = FirstCSPop ; int64_t Offset = - CSSize - SlotSize ; while ( MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator PI = MBBI ; unsigned Opc = PI -> getOpcode ( ) ; ++ MBBI ; if ( Opc == <STR_LIT> || Opc ==


<s> op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ <NUM_LIT> ] , sel [ <NUM_LIT> ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode )


<s> unsigned <ISA_LIT>InstrInfo :: getMachineOutlinerMBBFlags ( MachineBasicBlock & MBB ) const { unsigned Flags = <NUM_LIT> ; if ( std :: any_of ( MBB . begin ( ) , MBB . end ( ) , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ; assert ( MBB . getParent ( ) -> getRegInfo ( ) . tracksLiveness ( ) && <STR_LIT> ) ; LiveRegUnits LRU ( getRegisterInfo ( ) ) ; LRU . addLiveOuts (


<s> if ( ! ImmInRange ( MI , Entry ) ) return false ; if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! IsSP ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ; return ReplaceInstruction ( MI , Entry


<s> return ( __m128i ) __builtin_ia32_movdquhi128_mask ( ( __v8hi ) __A , ( __v8hi ) __W , (


<s> inline static AluCode isdTo<ISA_LIT>AluCode ( <STR_LIT> Node_type ) { switch ( Node_type ) { case <STR_LIT> : return AluCode :: ADD ; case <STR_LIT> : return AluCode :: ADDC ; case <STR_LIT> : return AluCode :: SUB ; case <STR_LIT> : return AluCode :: SUBB ; case <STR_LIT> : return AluCode :: AND ; case <STR_LIT> : return AluCode :: OR ; case <STR_LIT> : return AluCode :: XOR ; case <STR_LIT> : return AluCode :: SHL ; case <STR_LIT> : return AluCode :: SRL ; case <STR_LIT> : return AluCode :: SRA


<s> unsigned Register = GPR32DecoderTable [ RegNo ] ; if ( Register == <STR_LIT> ) Register = <STR_LIT> ; Inst . addOperand ( MCOperand ::


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } const RegisterBank * OpBank = RBI . getRegBank ( MO . getReg ( ) , MRI , TRI ) ; if ( ! OpBank ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( PrevOpBank && OpBank != PrevOpBank ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } PrevOpBank = OpBank ; } return false


<s> DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) . getSimpleVT ( ) , DAG . getConstant ( <NUM_LIT> , Op . getValueType ( ) . getSimpleVT ( ) ) , Op


<s> MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . init ( * TRI ) ; DomBBUsedRegs . init ( * TRI ) ; OptBBClobberedRegs . init ( * TRI ) ; OptBBUsedRegs . init ( *


<s> ( void ) BitWidth ; assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; KnownBits Known ; CurDAG -> computeKnownBits ( Op , Known ) ; uint64_t NonZeroBits = ( ~ Known . Zero ) . getZExtValue ( ) ; uint64_t AndImm ; if ( isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , AndImm ) ) { assert ( ( ~ APInt ( BitWidth , AndImm ) & ~ Known . Zero ) == <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( ! BiggerPattern && ! Op . hasOneUse ( ) ) return false ; uint64_t ShlImm ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShlImm )


<s> return ( __m128d ) __builtin_ia32_cmpnltsd ( ( __v2df ) __A , ( __v2df )


<s> if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ; return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber (


<s> fputs ( <STR_LIT> , stream ) ; assemble_name ( stream , name ) ; fputs ( <STR_LIT> , stream


<s> void <ISA_LIT>MemAluCombiner :: insertMergedInstruction ( MachineBasicBlock * BB , const MbbIterator & MemInstr , const MbbIterator & AluInstr , bool Before ) { MachineOperand Dest = MemInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand Base = MemInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand MemOffset = MemInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand AluOffset = AluInstr -> getOperand ( <NUM_LIT> ) ; assert ( ( AluOffset . isReg ( ) || AluOffset . isImm ( ) ) && <STR_LIT> ) ; LPAC :: AluCode AluOpcode = mergedAluCode ( AluInstr -> getOpcode ( ) ) ; unsigned NewOpc = mergedOpcode ( MemInstr -> getOpcode ( ) , AluOffset . isImm ( ) ) ; assert ( AluOpcode != LPAC :: UNKNOWN && <STR_LIT> ) ; assert ( NewOpc != <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder InstrBuilder = BuildMI ( * BB , MemInstr , MemInstr -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) ; InstrBuilder . addReg ( Dest . getReg ( ) , getDefRegState ( true ) ) ; InstrBuilder . addReg ( Base . getReg ( ) , getKillRegState ( true ) ) ; if ( AluOffset . isReg ( ) ) InstrBuilder . addReg ( AluOffset . getReg ( ) ) ; else if ( AluOffset . isImm ( ) ) InstrBuilder . addImm ( AluOffset . getImm ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; if ( Before || ! isZeroOperand ( MemOffset ) ) InstrBuilder . addImm (


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) <<

std :: setfill ( '0' ) << Binary << std :: dec << <STR_LIT> ;


<s> return __builtin_mve_vmovlbq_uv8hi (


<s> return ( uint8x8_t ) __builtin_aarch64_sqshrun_nv8hi (


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT


<s> const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; for ( auto Ty : { p0 , s1 , s8 , s16 , s32 } ) LegacyInfo . setAction ( { G_IMPLICIT_DEF , Ty } , LegacyLegalizeActions :: Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) LegacyInfo . setAction ( { G_PHI , Ty } , LegacyLegalizeActions :: Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s8 , s16 , s32 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; for ( unsigned Op : { G_UADDE } ) { LegacyInfo . setAction ( { Op , s32 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { Op , <NUM_LIT> , s1 } , LegacyLegalizeActions :: Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) LegacyInfo . setAction ( { MemOp , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { MemOp , <NUM_LIT> , p0 } , LegacyLegalizeActions :: Legal ) ; } LegacyInfo . setAction ( { G_FRAME_INDEX , p0 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_GLOBAL_VALUE , p0 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_PTR_ADD , p0 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_PTR_ADD , <NUM_LIT> , s32 } , LegacyLegalizeActions :: Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT>


<s> } assert ( SVT == <STR_LIT> && <STR_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getUNDEF ( SVT ) ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , DL , { VT , <STR_LIT> } , { Op -> getOperand ( <NUM_LIT> ) , Res } ) ; return DAG . getNode ( <STR_LIT> , DL


<s> assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned FIOperandNum = <NUM_LIT> ; while ( ! MI -> getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI -> getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo ) . getImm ( ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; unsigned StackEst = <ISA_LIT>FI -> determineFrameLayout ( MF , false , true ) ; if ( ! StackEst


<s> Op -> MatrixTileList . RegMask = RegMask ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> initialize<ISA_LIT>LoopDataPrefetchPass ( * PassRegistry ::


<s> MachineInstrBuilder emitInstStore ( unsigned Opc , unsigned SrcReg , unsigned MemReg , int64_t MemOffset ) { return emitInst ( Opc ) . addReg ( SrcReg ) . addReg


<s> Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : ThumbBit = <NUM_LIT> ; break ; } if ( Type == MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ) { uint32_t OtherHalf = MovtBit ? ( FixedValue & <NUM_LIT> ) : ( ( FixedValue & <NUM_LIT> ) >> <NUM_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( OtherHalf << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel

<< <NUM_LIT> ) | MachO :: R_SCATTERED ) ;


<s> else rshift = vec_splats ( ( unsigned short ) __B ) ; } result = vec_vsrah ( ( __v8hi ) __A , rshift ) ; return ( __m128i


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; emitNops ( Num ) ; return ; } emitSled ( MI , SledKind :: FUNCTION_ENTER


<s> if ( ! VCTP ) { VCTP = MI ; FoundOneVCTP =


<s> unsigned HI = ( Ty == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue DivRem = DAG . getNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue InGlue = DivRem ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , DL , LO , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N ,


<s> SDValue Hi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlign ( ) , N -> getOffset ( ) , OpFlagHi ) ; SDValue Lo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlign ( ) , N -> getOffset ( ) , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo ) ; return


<s> SDValue <ISA_LIT>DAGToDAGISel :: createQTuple ( ArrayRef < SDValue > Regs ) { static unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs , SubRegs


<s> return combineExtract ( SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , VecVT ,

Op0 , IndexN -> getZExtValue ( ) , DCI , false ) ;


<s> static machine_mode hfa_element_mode ( const_tree type , bool nested ) { machine_mode element_mode = VOIDmode ; machine_mode mode ; enum tree_code code = TREE_CODE ( type ) ; int know_element_mode = <NUM_LIT> ; tree t ; if ( ! nested && ( ! TYPE_SIZE ( type ) || integer_zerop ( TYPE_SIZE ( type ) ) ) ) return VOIDmode ; switch ( code ) { case VOID_TYPE : case INTEGER_TYPE : case ENUMERAL_TYPE : case BOOLEAN_TYPE : case POINTER_TYPE : case OFFSET_TYPE : case REFERENCE_TYPE : case METHOD_TYPE : case LANG_TYPE : case FUNCTION_TYPE : return VOIDmode ; case COMPLEX_TYPE : if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_COMPLEX_FLOAT && TYPE_MODE ( type ) != TCmode ) return GET_MODE_INNER ( TYPE_MODE ( type ) ) ; else return VOIDmode ; case REAL_TYPE : if ( nested && TYPE_MODE ( type ) != TFmode ) return TYPE_MODE ( type ) ; else return VOIDmode ; case ARRAY_TYPE : return hfa_element_mode ( TREE_TYPE ( type ) , <NUM_LIT> ) ; case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE


<s> const Edge * edges_begin ( ) const { return edges ( ) .


<s> if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel ::


<s> return ( uint8x16_t ) ( __a == <NUM_LIT>


<s> while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= selectMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; } return Modified


<s> return Create ( VK_<ISA_LIT>_HA , Expr , Ctx


<s> if ( ReverseCSRRestoreSeq ) MBB . splice ( FirstSPPopI , &


<s> if ( ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) || DefMI -> getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ; for ( auto I = DefMI ; I != FrameSetup ; ++ I ) if ( I -> isLoadFoldBarrier ( ) ) return nullptr ; return DefMI


<s> case <NUM_LIT> : break ; } return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> + OpOffset , <NUM_LIT> + OpOffset ) ; } case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) )


<s> static bool isSWTestOp ( SDValue N ) { if ( N . getOpcode ( ) == <STR_LIT> ) return true ; if ( N . getNumOperands ( ) < <NUM_LIT> || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; switch ( N . getConstantOperandVal ( <NUM_LIT> ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s>
if
(
ErrorInfo
&
Mask
)
OS
<<
' '
<<
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
Mask
<<=
<NUM_LIT>
;
}
return
Error
(
IDLoc
,
OS
.
str
(
)
,
SMRange
(
)


<s> void i386_pe_encode_section_info ( tree decl , rtx rtl , int first ) { rtx symbol ; int flags ; default_encode_section_info ( decl , rtl , first ) ; if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( symbol )


<s> if ( val == <NUM_LIT> || val == <NUM_LIT>

|| val == <NUM_LIT> ) return <NUM_LIT> ;


<s> SDLoc DL ( N ) ; int FI = cast < FrameIndexSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; SDValue FiOp = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; int TagOffset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * Out = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { FiOp , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( TagOffset , DL , <STR_LIT> ) } ) ; ReplaceNode ( N , Out ) ; return true


<s> unsigned getRegOpcode ( ) const { return I


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create


<s> int i ; for ( i = ( CSKY_LAST_MINI_REGNUM + <NUM_LIT> ) ; i < <NUM_LIT> ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) || ! TARGET_HIGH_REGISTERS ) { int i ; for ( i = CSKY_FIRST_HIGH_REGNUM ; i <= CSKY_LAST_HIGH_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) { fixed_regs [ CSKY_LR_REGNUM ] = <NUM_LIT> ; call_used_regs [ CSKY_LR_REGNUM ] = <NUM_LIT> ; } if ( ! TARGET_DSP ) { fixed_regs [ CSKY_HI_REGNUM ] = <NUM_LIT> ; call_used_regs [ CSKY_HI_REGNUM ] = <NUM_LIT> ; fixed_regs [ CSKY_LO_REGNUM ] = <NUM_LIT> ; call_used_regs [ CSKY_LO_REGNUM ] = <NUM_LIT> ; } if ( ! TARGET_HARD_FLOAT


<s> case 'd' : RC = & <STR_LIT> ; break ; case 'q' : RC = & <STR_LIT> ; break ; case 'z' : RC = & <STR_LIT> ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , <STR_LIT> , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; if ( <STR_LIT> . contains ( Reg ) ) return printAsmMRegister ( MO , 't' , O ) ; unsigned AltName = <STR_LIT> ; const TargetRegisterClass * RegClass ; if ( <STR_LIT> . contains ( Reg ) ) { RegClass = & <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { RegClass = & <STR_LIT> ; } else { RegClass = & <STR_LIT> ; AltName = <STR_LIT> ; } return printAsmRegInClass ( MO , RegClass , AltName


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> if ( STI -> has<ISA_LIT>2 ( ) ) return false ; return handleSlot ( [ this ] ( auto & I ) -> bool { return TII -> HasLoadDelaySlot ( I ) ; } , [ this ] ( auto & IInSlot , auto & I ) -> bool { return TII -> SafeInLoadDelaySlot ( IInSlot , I ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty ,


<s> if ( Rt == <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( ( Rt & <NUM_LIT> ) == <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( Rt2 != Rt + <NUM_LIT> ) { if ( Load ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; else return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; } } if ( ! <ISA_LIT>Mode &&


<s> static DecodeStatus decodeImmShiftOpValue ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( Log2 ( Imm ) ) ) ; return MCDisassembler :: Success


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned

, MachineMemOperand :: Flags , bool * Fast ) const {


<s> unsigned add = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && !


<s> SDValue Input = OrigSToV . getOperand ( <NUM_LIT> ) ; if ( Input . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( Input . getOperand ( <NUM_LIT> ) ) ; SDValue OrigVector = Input . getOperand ( <NUM_LIT> ) ; if ( Idx && VT == OrigVector . getValueType ( ) ) { SmallVector < int , <NUM_LIT> > NewMask ( VT . getVectorNumElements ( ) , - <NUM_LIT> ) ; NewMask [ VT . getVectorNumElements ( ) / <NUM_LIT> ] = Idx -> getZExtValue ( ) ; return DAG . getVectorShuffle ( VT , dl , OrigVector , OrigVector ,


<s> bool HasMultipleSuccs = false ; BB2BrMap BrMap ; std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; auto * Fn = MBB . getParent ( ) ; for ( MachineBasicBlock * Pred : SuccBB -> predecessors ( ) ) if ( ! examinePred ( * Pred , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * Fn ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else


<s> bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ^ is_swapped ] ; high = nelt / <NUM_LIT> ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d


<s> U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . addOperand ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i )


<s> if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) . addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ; auto TBL2 = MIRBuilder . buildInstr ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { RegSeq , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * RegSeq , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( * TBL2 , TII , TRI , RBI ) ; I . eraseFromParent (


<s> void <ISA_LIT>DAGToDAGISel :: SelectLoadLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT>


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> )


<s> bool csky_simple_addr_operand_p ( rtx op ) { struct csky_address addr ; if ( ! decompose_csky_address ( op , & addr ) ) return false ; if ( addr . disp && GET_CODE ( addr .


<s> <ISA_LIT>TargetStreamer & ATS = static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ; ATS . finishAttributeSection ( ) ; MCELFStreamer :: FinishImpl (


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { switch ( MO . getTargetFlags ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; } return Printer . GetGlobalValueSymbol ( MO . getGlobal


<s> if ( isPositionIndependent ( ) || STI . isROPI ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( isPositionIndependent ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . FPDenormalMode == FPDenormal :: PreserveSign ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . FPDenormalMode == FPDenormal :: PositiveZero ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else { if ( ! STI . hasVFP2Base ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3Base ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( checkFunctionsAttributeConsistency ( * MMI -> getModule ( ) , <STR_LIT> , <STR_LIT> ) || TM . Options . NoTrappingFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT>


<s> if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize , <STR_LIT> , MachineInstr :: NoFlags ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister = <STR_LIT> ; bool HasFP = hasFP ( MF ) ; for ( auto & I : MFI . getCalleeSavedInfo ( ) ) { unsigned Reg = I . getReg ( ) ; if ( is<ISA_LIT>LowRegister ( Reg ) && ! ( HasFP && Reg == FramePtr ) ) { ScratchRegister = Reg ; break ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } } if ( needPopSpecialFixUp ( MF ) ) { bool Done = emitPopSpecialFixUp ( MBB , true ) ; ( void ) Done ; assert ( Done &&


<s> } MachineBasicBlock :: iterator LastCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> getDesc ( ) . isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( CSSize ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; MBBI = prior ( LastCSPop ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else { BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { bool isMem = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; MBBI = prior ( MBB . end ( )


<s> return ( Subtarget . getFeatureBits ( ) & <STR_LIT> )


<s> bool isNEONi32vmov ( ) const { if ( isNEONByteReplicate ( <NUM_LIT> ) ) return false ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr


<s> if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return <NUM_LIT> ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Register ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg

) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> parms . nregs += intslots ; } nregs = parms . nregs ; if ( nregs == <NUM_LIT> ) { if ( typesize <= <NUM_LIT> ) { return gen_rtx_REG ( mode , regbase ) ; } else { nregs = ( typesize + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; } if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs != <NUM_LIT> ) ; parms . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( parms . stack + nregs ) ) ; if ( parms . stack ) XVECEXP ( parms . ret , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; parms . nregs = <NUM_LIT> ; parms . intoffset = <NUM_LIT> ; function_arg_record_value_2 ( type , <NUM_LIT> , & parms , false ) ; function_arg_record_value_3 ( typesize * BITS_PER_UNIT , &


<s> const unsigned * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] =


<s> return StringRef ( PSBHint . Data , PSBHint . Length


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) ) , AM ) . addImm ( CI -> getSExtValue ( ) ) ; return true


<s> return __builtin_aarch64_ld1v4hi ( ( const __builtin_aarch64_simd_hi *


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , DebugLoc dl , SelectionDAG & DAG ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s>
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
ErrorInfo
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
uint64_t
ErrorInfoMissingFeature
=
<NUM_LIT>
;
unsigned
Match
[
<NUM_LIT>
]
;
for
(
unsigned
I
=
<NUM_LIT>
,
E
=
array_lengthof
(
Match
)
;
I
!=
E
;
++
I
)
{
Tmp
.
back
(
)
=
Suffixes
[
I
]
;
Match
[
I
]
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
;
if
(
Match
[
I
]
==
Match_MissingFeature
)
ErrorInfoMissingFeature
=
ErrorInfoIgnore
;
}
Op
.
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
std
::
count
(
std
::
begin
(
Match
)
,
std
::
end
(
Match
)
,
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg


<s> Type * RetTy = Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Type * RetTyABI = RetTy ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue RetPtr ; if ( RetTy -> isFP128Ty ( ) ) { ArgListEntry Entry ; int RetFI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; RetPtr = DAG . getFrameIndex ( RetFI , getPointerTy ( ) ) ; Entry . Node = RetPtr ; Entry . Ty = PointerType :: getUnqual ( RetTy ) ; if ( ! Subtarget -> is64Bit ( ) ) Entry . isSRet = true ; Entry . isReturned = false ; Args . push_back ( Entry ) ; RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI (


<s> bool <ISA_LIT>InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > &


<s> bCustomSegment = true ; break ; case GlobalValue :: DLLExportLinkage : DLLExportedGVs . insert ( name ) ; case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << <STR_LIT> ; case GlobalValue :: InternalLinkage : SwitchToSection ( TAI -> getDataSection ( ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ! bCustomSegment ) EmitAlignment ( Align , I ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) O << name << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> << I -> getName ( ) ; O << '\n' ; EmitGlobalConstant ( C ) ; if ( bCustomSegment ) O << name << <STR_LIT> ; } if ( ! DLLExportedGVs . empty ( ) || ! DLLExportedFns . empty ( ) ) { SwitchToDataSection ( <STR_LIT> )


<s> } else { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( llvm :: prior ( MachineFunction :: iterator ( NewIsland ) ) ) ; unsigned ID = createPICLabelUId ( ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex ( ID


<s> uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t MaxAlign = calculateMaxStackAlign ( MF ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( RetOpcode && * RetOpcode == <STR_LIT> ) { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; TargetMBB = MBBI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( RetOpcode && * RetOpcode == <STR_LIT> ) { NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = alignTo ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode


<s> InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , true , End ) ) return <NUM_LIT> ; if ( ! Info . isKind (


<s> if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext (


<s> if ( Kind != SK_Reverse ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; static const CostTblEntry < <STR_LIT> > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } ,


<s> int FI = Addr . getFI ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI , Offset ) , Flags , MFI . getObjectSize (

FI ) , MFI . getObjectAlignment ( FI ) ) ;


<s> static tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedCompressStore ( Type * DataTy ) { return isLegalMaskedExpandLoad ( DataTy


<s> AFI -> setAlign ( <NUM_LIT> ) ; if ( ( Offset + MBBSize ) % <NUM_LIT> != <NUM_LIT> ) MBBSize += <NUM_LIT> ; continue ; default : continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( I ) ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned TSFlags = I -> getDesc ( ) . TSFlags ; switch ( TSFlags & <STR_LIT> ) { default : if ( I -> getOpcode ( ) == <STR_LIT> ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Bits = <NUM_LIT> ; break ; } assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; CPUsers . push_back ( CPUser ( I , CPEMI


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget ( ) ) , TII ( * TM . getInstrInfo ( ) ) , TLI ( * TM . getTargetLowering ( ) ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb2 = AFI -> isThumbFunction ( ) ; Context = & funcInfo . Fn ->


<s> const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated (


<s> if ( code == '@' || code == '#' || code == '*' || code == '^' ) return true ; return false


<s> if ( ResourcesCost != <NUM_LIT> ) dbgs ( ) <<


<s> emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , <NUM_LIT> ) ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , <NUM_LIT> ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , <NUM_LIT> ) ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( gen_rtx_MEM ( DImode , tramp ) )


<s> if ( Value . getOpcode ( ) == <STR_LIT> || Value . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Value ) ; return DAG . getBuildVector ( VT , DL


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; MCFixupKind Kind = static_cast < MCFixupKind > (


<s> uint16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> } std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , MachinePointerInfo ( ) ,


<s> return ( __m128i ) __builtin_ia32_pmovsdw128_mask ( ( __v4si ) __A ,


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } Base =


<s> addPass ( create<ISA_LIT>ProtectJTSupport (


<s> O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'y' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; if ( ! isPowerOf2_64 ( MO . getImm ( ) ) ) return true ; O << Log2_64 ( MO . getImm ( ) ) ; return false ; case 'z' : if ( MO . getType ( ) == MachineOperand :: MO_Immediate && MO . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; return false ; } break ; case 'D' : case 'L' : case 'M' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum : OpNum + <NUM_LIT> ; break ; case 'D' : RegOp = OpNum + <NUM_LIT> ; } if ( RegOp >= MI -> getNumOperands (


<s> if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , U . getMaxDisp ( ) + <NUM_LIT> , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; dumpBBs ( ) ; DEBUG ( MF -> dump ( ) ) ; llvm_unreachable ( <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val != <NUM_LIT> ) return false ; } bool HasHi = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val != <NUM_LIT> ) return false ; HasHi = true ; } return


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( ! Subtarget -> hasFP64 ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) .


<s> return ( __mmask8 ) __builtin_ia32_pcmpgtq512_mask ( ( __v8di ) __A , ( __v8di )


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned MaskVal = ( ScalarSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Mask = DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Vec256 = DAG . getBitcast ( CastVT , Vec256 ) ; Vec256 = DAG . getNode ( <STR_LIT> , dl , CastVT , Result , Vec256 , Mask ) ; return DAG . getBitcast ( ResultVT , Vec256 ) ; } return InsertSubVector ( Result , Vec , IdxVal


<s> if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT>


<s> gcc_assert ( GET_CODE ( x ) == SYMBOL_REF && nds32_indirect_call_referenced_p ( x ) ) ; addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , symbol ) , UNSPEC_ICT ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sethi ( reg , addr ) ) ; x = gen_const_mem ( SImode , gen_rtx_LO_SUM ( Pmode


<s> else { bool is_fastcall , is_thiscall ; int regparm ; is_fastcall = ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( cfun -> decl ) ) ) != NULL ) ; is_thiscall = ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( cfun -> decl ) ) ) != NULL ) ; regparm = ix86_function_regparm ( TREE_TYPE ( cfun -> decl ) , cfun -> decl ) ; if ( is_fastcall ) { if ( DECL_STATIC_CHAIN ( cfun -> decl ) ) { sorry ( <STR_LIT> <STR_LIT> ) ; return INVALID_REGNUM ; } return AX_REG ; } else if ( is_thiscall ) { if ( ! DECL_STATIC_CHAIN ( cfun -> decl ) ) return DX_REG ; return AX_REG ; } else if ( regparm < <NUM_LIT> ) { if ( ! DECL_STATIC_CHAIN ( cfun -> decl ) ) return CX_REG ; else { if ( regparm >= <NUM_LIT> ) { sorry ( <STR_LIT> <STR_LIT> ) ; return INVALID_REGNUM ; } return DX_REG ; } } else { sorry ( <STR_LIT> ) ; return


<s> fix -> backwards = get_attr_neg_pool_range ( insn ) ; fix -> minipool = NULL ; gcc_assert ( fix -> forwards || fix -> backwards ) ; if ( ARM_DOUBLEWORD_ALIGN && fix -> fix_size >= <NUM_LIT> ) minipool_pad = <NUM_LIT> ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , GET_MODE_NAME ( mode ) , INSN_UID ( insn ) , ( unsigned long ) address , - <NUM_LIT> * ( long ) fix -> backwards , ( long ) fix -> forwards ) ; arm_print_value ( dump_file , fix -> value ) ; fprintf ( dump_file , <STR_LIT> ) ; } fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail ->


<s> if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , <NUM_LIT> ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , <NUM_LIT> ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , <NUM_LIT>


<s> if ( BASE_REGISTER_P ( xfoo1 , strict ) ) return ! flag_pic || mode == QImode ; if ( flag_pic && symbolic_operand ( xfoo0 , SImode ) ) return


<s> MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr