<s> bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; std :: map < unsigned , Chain * > ActiveChains ; std :: set < Chain * > AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto * I : AllChains ) EC . insert ( I ) ; for ( auto * I : AllChains ) { for ( auto * J : AllChains ) { if ( I != J && I -> rangeOverlapsWith ( J ) ) EC . unionSets ( I , J ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( Cs ) ; } std :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front ( ) ) ; } ) ; int Parity = <NUM_LIT> ; for ( auto & I : V ) Changed |= colorChainSet ( I , MBB , Parity ) ; for ( auto * C : AllChains ) delete C ; return Changed


<s> RLo = DAG . getNode ( <STR_LIT> , dl , ExVT , RLo , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; RHi = DAG . getNode ( <STR_LIT> , dl , ExVT , RHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RLo , RHi ) ; } if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && ! Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; MVT MulVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( Subtarget . hasSSE41 ( ) && DAG . ComputeNumSignBits ( A ) > <NUM_LIT> && DAG . ComputeNumSignBits ( B ) > <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getBitcast ( MulVT , A ) , DAG . getBitcast ( MulVT , B ) ) ; } APInt LowerBitsMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool ALoIsZero = DAG . MaskedValueIsZero ( A , LowerBitsMask ) ; bool BLoIsZero = DAG . MaskedValueIsZero ( B , LowerBitsMask ) ; APInt UpperBitsMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool AHiIsZero = DAG . MaskedValueIsZero ( A , UpperBitsMask ) ; bool BHiIsZero = DAG . MaskedValueIsZero ( B , UpperBitsMask ) ; SDValue Alo = DAG . getBitcast ( MulVT , A ) ; SDValue Blo = DAG . getBitcast ( MulVT , B ) ; SDValue Zero = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue AloBlo = Zero ; if ( ! ALoIsZero && ! BLoIsZero ) AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , Alo , Blo ) ; SDValue AloBhi =


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter


<s> virtual const char * getPassName ( ) const { return


<s> return ( hi19 << <NUM_LIT> ) | ( lo2 << <NUM_LIT>


<s> print_reg ( gen_rtx_REG ( DImode , regno ) , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , alloc_offset - seh -> reg_offset [ regno ] ) ; } if ( seh -> cfa_reg != stack_pointer_rtx ) { offset = alloc_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; gcc_assert ( IN_RANGE ( offset , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , f ) ; print_reg ( seh -> cfa_reg , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } if ( crtl -> accesses_prior_frames ) { offset = seh -> sp_offset - alloc_offset ; if ( offset > <NUM_LIT> && offset < SEH_MAX_FRAME_SIZE ) fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } fputs ( <STR_LIT> , f


<s> if ( IsPextr ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnes ( VT . getSizeInBits ( ) ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( ( InputVector . getOpcode ( ) == <STR_LIT> || InputVector . getOpcode ( ) == <STR_LIT> ) && InputVector . getOperand ( <NUM_LIT> ) == EltIdx ) { assert ( SrcVT == InputVector . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Scl = InputVector . getOperand ( <NUM_LIT> ) ; Scl = DAG . getNode ( <STR_LIT> , dl , SrcVT . getScalarType ( ) , Scl ) ; return DAG . getZExtOrTrunc ( Scl , dl , VT ) ; } return SDValue ( ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue VPDPBUSD = combineVPDPBUSDPattern ( N , DAG , Subtarget ) ) return VPDPBUSD ; if ( SDValue Cmp = combinePredicateReduction ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineMinMaxReduction ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = combineArithReduction ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = scalarizeExtEltFP ( N , DAG , Subtarget ) ) return V ; if ( SrcVT . getScalarType ( ) == <STR_LIT> ) { bool IsVar = ! CIdx ; SmallVector < SDNode * , <NUM_LIT> > BoolExtracts ; unsigned ResNo = InputVector . getResNo ( ) ; auto IsBoolExtract = [ & BoolExtracts , & ResNo , & IsVar ] ( SDNode * Use ) { if ( Use -> getOpcode ( ) == <STR_LIT> && Use -> getOperand ( <NUM_LIT> ) . getResNo ( ) == ResNo && Use -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { BoolExtracts . push_back ( Use


<s> return new pass_mips_machine_reorg2 (


<s> if ( a & <NUM_LIT> ) c += b ; a >>= <NUM_LIT> ; b <<= <NUM_LIT> ; } return


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex ,


<s> void rs6000_secondary_reload_inner ( rtx reg , rtx mem , rtx scratch , bool store_p ) { int regno = true_regnum ( reg ) ; machine_mode mode = GET_MODE ( reg ) ; addr_mask_type addr_mask ; rtx addr ; rtx new_addr ; rtx op_reg , op0 , op1 ; rtx and_op ; rtx cc_clobber ; rtvec rv ; if ( regno < <NUM_LIT> || regno >= FIRST_PSEUDO_REGISTER || ! MEM_P ( mem ) || ! base_reg_operand ( scratch , GET_MODE ( scratch ) ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; if ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) addr_mask = reg_addr [ mode ] . addr_mask [ RELOAD_REG_GPR ] ; else if ( IN_RANGE ( regno , FIRST_FPR_REGNO , LAST_FPR_REGNO ) ) addr_mask = reg_addr [ mode ] . addr_mask [ RELOAD_REG_FPR ] ; else if ( IN_RANGE ( regno , FIRST_ALTIVEC_REGNO , LAST_ALTIVEC_REGNO ) ) addr_mask = reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] ; else rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; if ( ( addr_mask & RELOAD_REG_VALID ) == <NUM_LIT> ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; if ( TARGET_DEBUG_ADDR ) rs6000_secondary_reload_trace ( __LINE__ , reg , mem , scratch , store_p ) ; new_addr = addr = XEXP ( mem , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case PRE_INC : case PRE_DEC : op_reg = XEXP ( addr , <NUM_LIT> ) ; if ( ! base_reg_operand ( op_reg , Pmode ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; if ( ( addr_mask & RELOAD_REG_PRE_INCDEC ) == <NUM_LIT> ) { emit_insn ( gen_add2_insn ( op_reg , GEN_INT ( GET_MODE_SIZE ( mode ) ) ) ) ; new_addr = op_reg ; } break ; case PRE_MODIFY : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! base_reg_operand ( op0 , Pmode ) || GET_CODE ( op1 ) != PLUS || ! rtx_equal_p ( op0 , XEXP ( op1 , <NUM_LIT> ) ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; if ( ( addr_mask & RELOAD_REG_PRE_MODIFY ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; new_addr = reg ; } break ; case AND : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT>


<s> if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . BaseRegNum == <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return false ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val == INT32_MIN ) || ( Val


<s> static inline MemOpKey getTombstoneKey ( ) { return MemOpKey ( PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( )

, PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) ) ;


<s> auto * GA = dyn_cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! GA ) return false ; Optional < ConstantRange > CR = GA -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ; if ( ! CR ) return Width == <NUM_LIT> && TM . getCodeModel ( ) ==


<s> Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; return ( Rn << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO1 . getReg


<s> FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { bitmap_set_bit ( components , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; unsigned regno2 = multiple_p ( offset , <NUM_LIT> ) ? regno +


<s> unsigned int ix86_local_alignment ( tree exp , machine_mode mode , unsigned int align , bool may_lower ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( may_lower && ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ( ! TYPE_USER_ALIGN ( type ) && ! TYPE_ATOMIC ( strip_array_types ( type ) ) ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE (

type ) ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getFGRH32Reg (


<s> return __aarch64_vset_lane_any ( * __src ,


<s> } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getVectorElementType ( ) , BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i ]


<s> bool hasMP = featureBits [ <STR_LIT> ] ; bool hasV7Ops = featureBits [ <STR_LIT> ] ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : if ( ! hasV7Ops || ! hasMP ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } unsigned addrmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> ,


<s> return ( __m256 ) __builtin_ia32_cvtpd2ps512_mask ( ( __v8df ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , (


<s> break ; case <STR_LIT> : case <STR_LIT> : UsedFlags . Z = true ; case <STR_LIT> : case <STR_LIT> : UsedFlags . C = true ; break ; case <STR_LIT> : case <STR_LIT> : UsedFlags . N = true ; break ; case <STR_LIT> : case <STR_LIT> : UsedFlags . V = true ; break ; case


<s> return Is<ISA_LIT>64 && IsLittleEndian


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask


<s> unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm32 ) ) ; return MCDisassembler ::


<s> unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> ,

V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;


<s> static DecodeStatus DecodeQPairRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeRegisterClassByID ( Inst , RegNo ,


<s> static unsigned char csky_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( rclass == V_REGS ) return <NUM_LIT> ; else return CSKY_NUM_REGS (


<s> } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == & * MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= Align . value ( ) ; EndInsertOffset -= Align . value ( ) ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = & * MI ; } -- MI ; if ( LastIT ) { Register PredReg ; <STR_LIT> CC = getITInstrPredicate ( * MI , PredReg ) ; if ( CC != <STR_LIT> ) MI = LastIT ; } if ( STI -> isTargetWindows ( ) && isThumb && MI -> getOpcode ( ) == <STR_LIT> && ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) { -- MI ; assert ( MI -> getOpcode ( ) == <STR_LIT> && ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) ; } Register PredReg ; assert ( ! isThumb || getITInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) ; NewMBB = splitBlockBeforeInstr ( &


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: JITDefault ) RM = Reloc :: Static ; else if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> initMCCodeGenInfo ( RM ,


<s> SDValue rdx = DAG . getCopyFromReg ( rax . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , rax . getValue ( <NUM_LIT> ) ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rax , Tmp ) , rdx . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops ,


<s> set_offset ( XER_REGNO , m64 -> xer + <NUM_LIT> ) ; set_offset ( LINK_REGISTER_REGNUM , m64 -> lr + <NUM_LIT> ) ; set_offset ( COUNT_REGISTER_REGNUM , m64 -> ctr + <NUM_LIT> ) ; if ( is_vector ) set_offset ( VRSAVE_REGNO , & m64 -> vrsave ) ; if ( m64 -> exception == <NUM_LIT> || m64 -> exception == <NUM_LIT> || m64 -> exception == <NUM_LIT> || ( m64 -> exception == <NUM_LIT> && ! ( m64 -> srr1 & <NUM_LIT> ) ) ) return_addr = m64 -> srr0 + <NUM_LIT> ; else return_addr = m64 -> srr0 ; } else { struct gcc_mcontext32 * m = uctx -> mcontext ; int i ; float_vector_state = & m -> fvs ; new_cfa = m -> gpr [ <NUM_LIT> ] ; set_offset ( CR2_REGNO , & m -> cr ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) set_offset ( i , m -> gpr + i ) ; set_offset ( XER_REGNO , & m -> xer ) ; set_offset ( LINK_REGISTER_REGNUM , & m -> lr ) ; set_offset ( COUNT_REGISTER_REGNUM , & m -> ctr ) ; if ( is_vector ) set_offset ( VRSAVE_REGNO , & m -> vrsave ) ; if ( m -> exception == <NUM_LIT> || m -> exception == <NUM_LIT> || m -> exception == <NUM_LIT> || ( m -> exception == <NUM_LIT> && ! ( m -> srr1 & <NUM_LIT> ) ) ) return_addr = m -> srr0 + <NUM_LIT> ; else return_addr = m


<s> return ( __mmask16 ) __builtin_ia32_ucmpd512_mask ( ( __v16si ) __X , ( __v16si )


<s> FunctionPass * llvm :: create<ISA_LIT>A53Fix835769 ( ) { return new <ISA_LIT>A53Fix835769 (


<s> static SDValue lowerV8F64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp ->


<s> if ( TM . getSubtargetImpl ( ) -> isDarwin ( ) )

return new TargetLoweringObjectFileMachO ( ) ;


<s> return ( __m128i ) __builtin_ia32_pbroadcastq128_gpr_mask ( __A , ( __v2di )


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT>


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( ! <STR_LIT> . contains ( Reg ) && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; } } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeFrameSize


<s> Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; MVT VT = ArgVT . getSimpleVT ( ) . SimpleTy ; if ( VT . isFloatingPoint ( ) && ! Subtarget -> hasFPARMv8 ( ) ) return false ; if ( VT . isVector ( ) && ( ! Subtarget -> hasNEON ( ) || ! Subtarget -> isLittleEndian ( ) ) ) return false ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) ++ GPRCnt ; else if ( ( VT >= <STR_LIT> && VT <= <STR_LIT> ) || VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ++ FPRCnt ; else return false ; if ( GPRCnt > <NUM_LIT> || FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg Registers [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; VT = <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ FPRIdx ++ ] ; RC = &


<s> virtual SMLoc getEndLoc ( ) const LLVM_OVERRIDE { return EndLoc


<s> unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & JmpMBB = * JmpI . getParent ( ) ; insertTest ( JmpMBB , JmpI . getIterator ( ) , JmpI . getDebugLoc ( ) , CondReg ) ; JmpI . getOperand ( <NUM_LIT> ) . setImm ( Inverted ? <STR_LIT> : <STR_LIT> ) ; JmpI . findRegisterUseOperand ( <STR_LIT> ) ->


<s> Triple TheTriple ( TT ) ; MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; JumpTableEntryIndices . clear ( ) ; JumpTableUserIndices . clear ( ) ; ImmBranches . clear ( ) ; PushPopMIs . clear ( ) ; T2JumpTables . clear (


<s> std :: vector < std :: pair < uint64_t , uint64_t >> Result ; for ( uint64_t Byte = <NUM_LIT> , End = PltContents . size ( ) ; Byte + <NUM_LIT> < End ; ) { if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] == <NUM_LIT> ) { uint32_t Imm = <STR_LIT> :: read32le ( PltContents . data ( ) + Byte + <NUM_LIT> ) ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte , GotPltSectionVA + Imm ) ) ; Byte += <NUM_LIT> ; } else if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] == <NUM_LIT> ) { uint32_t Imm = <STR_LIT> :: read32le ( PltContents . data ( ) + Byte


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValueLsl2MMR6 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * FixupExpression = MCBinaryExpr :: createAdd ( MO . getExpr ( ) , MCConstantExpr :: create (


<s> return ( int32x4_t ) __builtin_neon_vld1v4si ( ( const __builtin_neon_si


<s> for ( const Function & F : M ) { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; unsigned FDir = STI . getDarwinDirective ( ) ; Directive = Directive > FDir ? FDir : STI . getDarwinDirective ( ) ; if ( STI . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; } assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; assert ( Directive < array_lengthof ( CPUDirectives ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPUDirectives [ Directive ] ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS ,


<s> poly8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> } } MVT VecTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && MMO -> getAlign ( ) >= Align ( <NUM_LIT> ) && VecTy . getScalarSizeInBits ( ) <= <NUM_LIT> ) { return SDValue ( ) ; } SDValue LoadOps [ ] = { Chain , Base } ; SDValue Load = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LoadOps , <STR_LIT> , MMO ) ; DCI . AddToWorklist ( Load . getNode ( ) ) ; Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Swap = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , Load ) ; DCI . AddToWorklist ( Swap . getNode ( ) ) ; if ( VecTy != <STR_LIT> ) { SDValue N = DAG . getNode ( <STR_LIT> , dl , VecTy ,


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . GetStackPtr ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT>


<s> else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = <NUM_LIT> ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( ignore_outlined && cfun -> machine -> call_ms2sysv ) { unsigned count = cfun -> machine -> call_ms2sysv_extra_regs + xlogue_layout :: MIN_REGS ; if ( xlogue_layout :: is_stub_managed_reg ( regno , count ) ) return false ; } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] &&

( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ;


<s> return __builtin_loongson_pcmpeqb_u ( s


<s> unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; copy0MBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent


<s> unsigned BrOffset = getInstrOffset ( MI ) ; unsigned DestOffset = BlockInfo [ DestBB -> getNumber ( ) ] . Offset ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << MaxOffs << <STR_LIT> << getInstrOffset ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> <<

int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ;


<s> default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) )


<s> else byte = <NUM_LIT> ; if ( REG_P ( op ) ) { if ( FP_REG_P ( REGNO ( op ) ) ) return gen_rtx_REG ( word_mode , high_p ? REGNO ( op ) + <NUM_LIT> : REGNO ( op ) ) ; if ( ACC_HI_REG_P ( REGNO ( op ) ) ) return gen_rtx_REG ( word_mode , high_p ? REGNO ( op ) : REGNO ( op ) + <NUM_LIT> ) ; } if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode ,


<s> static bool csky_class_likely_spilled_p ( reg_class_t rclass ) { if ( ( TARGET_MINI_REGISTERS && rclass == MINI_REGS ) || rclass == C_REGS


<s> RtMI = & * Paired ; Rt2MI = & * I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = & * I ; Rt2MI = & * Paired ; } int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( TII -> isUnscaledLdSt ( RtMI -> getOpcode ( ) ) ) { assert ( ! ( OffsetImm % getMemScale ( * RtMI ) ) && <STR_LIT> ) ; OffsetImm /= getMemScale ( * RtMI ) ; } MachineInstrBuilder MIB ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineOperand RegOp0 = getLdStRegOp ( * RtMI ) ; MachineOperand RegOp1 = getLdStRegOp ( * Rt2MI ) ; if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { unsigned Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * Paired ) ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW )

. addReg ( DstRegX , RegState :: Define ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) || isUInt


<s> unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode ( I -> getOpcode ( ) ) : getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB ; if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) DEBUG ( dbgs ( )


<s> DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; MIIt = skipDebugInstructionsForward ( ++ MIIt , MIItEnd ) ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg

= RegRewriteTable [ FalseReg ] . second ;


<s> void <ISA_LIT>HazardRecognizer :: Reset ( ) { LastMI =


<s> return ( isRegInClass ( Reg , & <STR_LIT> ) || isRegInClass (


<s> for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF -> getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( LogAlign ) ; unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> mayStore ( ) && hasStoreToStackSlot


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> if ( isLegalAddressingMode ( AM , Ty , AS ) ) return AM . Scale !=


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Modified =


<s> Value * <ISA_LIT>IREmitter :: visitBSF ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return nullptr ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) { Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; } SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ]


<s> return ( __m256i ) __builtin_ia32_vpdpwssds_v8si ( ( __v8si ) __A , ( __v8si )


<s> if ( Idx . sge ( - <NUM_LIT> ) && Idx . slt ( Ty . getVectorMinNumElements ( ) ) ) return Op ; return SDValue (


<s> unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize < <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( uint32_t ( ~ <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ) ; else if ( BitSize == <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( ~ uint32_t ( <NUM_LIT> ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> return parseSetArchDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFpDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetOddSPRegDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoOddSPRegDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPopDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetPushDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>0Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString


<s> void <ISA_LIT>TargetWinCOFFStreamer ::


<s> unsigned getImmMinusOneOpValue ( const MachineInstr & MI , unsigned Op


<s> int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI .


<s> void <ISA_LIT>PostRASchedStrategy :: leaveMBB ( ) { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; ) ; advanceTo ( MBB ->


<s> ImmutablePass * llvm :: create<ISA_LIT>TargetTransformInfoPass ( const <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>TTI ( TM )


<s> unsigned <ISA_LIT>_MC :: getDwarfRegFlavour ( const Triple & TT , bool isEH ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return DWARFFlavour :: <ISA_LIT>_64 ; if ( TT . isOSDarwin ( ) ) return isEH ? DWARFFlavour :: <ISA_LIT>_32_DarwinEH : DWARFFlavour :: <ISA_LIT>_32_Generic ; if ( TT . isOSCygMing ( ) ) return DWARFFlavour ::


<s> } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) ) return true ; } } return false


<s> HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasLDBRX = false ; IsBookE =


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ObjectWriter ( uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ObjectWriter >


<s> FoldAsLoadDefReg = <NUM_LIT> ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = <NUM_LIT> ; bool FoundSrcOperand = false ; for ( unsigned i = <NUM_LIT> , e = MI . getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg !=


<s> return new NOPInsertionPass ( is64Bit


<s> MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; Labels . clear


<s> return __builtin_ia32_aesencwide128kl_u8 ( ( __v2di * ) __A , ( __v2di * )


<s> static const uint16_t SCvtOpc [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , } ; static const uint16_t UCvtOpc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false ; MVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( DstVT ) ; Register ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; Register ResultReg = fastEmitInst_rr ( Opcode , RC , ImplicitDefReg , OpReg ) ; updateValueMap ( I , ResultReg ) ; return


<s> void addUImm6Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst ,


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx

) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ;


<s> unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm8 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; const FeatureBitset & FeatureBits = Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ; DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( imm8 ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( imm8 == <NUM_LIT> && pred != <NUM_LIT> && ( ( FeatureBits [ <STR_LIT> ] ) != <NUM_LIT> ) ) S = MCDisassembler :: SoftFail ; return S


<s> unsigned Emitter < CodeEmitter > :: getMachineSoImmOpValue ( unsigned SoImm ) { int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ; return


<s> default : break ; case MCK_DFPRegs : if ( ! Op -> isFloatReg ( ) || <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( <STR_LIT> ( Op ) ) return MCTargetAsmParser ::


<s> ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI -> mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) continue ; MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) .


<s> addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses (


<s> static const char * aarch64_get_multilib_abi_name ( void )


<s> int cost ; if ( TARGET_THUMB ) { switch ( code ) { case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; default : * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND ) ) { * total = <NUM_LIT> ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = <NUM_LIT> ; return true ; } if ( mode == DImode ) { cost = <NUM_LIT> ; nonreg_cost = <NUM_LIT> ; } else { cost = <NUM_LIT> ; nonreg_cost =


<s> return __builtin_mve_vcmpneq_uv8hi ( __a ,


<s> assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { expandLoadAddressSym ( Inst , IDLoc , Instructions ) ; return false ; } const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back


<s> uint16_t validDomains = <NUM_LIT> ; if ( domain ) { if ( lookup ( MI . getOpcode ( ) , domain , ReplaceableInstrs ) ) { validDomains = <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = <NUM_LIT> ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = Subtarget . hasDQI ( ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( const uint16_t * table = lookupAVX512 ( opcode , domain ,


<s> bool sh2a_function_vector_p ( tree func ) { tree list ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; list = SH_ATTRIBUTES ( func ) ; while ( list ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return true ; list = TREE_CHAIN


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == Immediate ) Inst . addOperand ( MCOperand :: CreateImm ( getImm


<s> unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } const Function & CF = OF . Candidates . front ( ) . getMF ( ) -> getFunction ( ) ; bool ShouldSignReturnAddr = false ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { StringRef Scope = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) ShouldSignReturnAddr = true ; else if ( Scope . equals ( <STR_LIT> ) && ! IsLeafFunction ) ShouldSignReturnAddr = true ; } bool ShouldSignReturnAddrWithAKey = true ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { const StringRef Key = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( ( Key . equals_lower ( <STR_LIT> ) || Key . equals_lower ( <STR_LIT> ) ) && <STR_LIT> ) ; ShouldSignReturnAddrWithAKey = Key . equals_lower ( <STR_LIT> ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) { signOutlinedFunction ( MF , MBB , ShouldSignReturnAddr , ShouldSignReturnAddrWithAKey ) ; return ; } if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg


<s> MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , SadVecVT , V , Zeros ) ; return DAG . getBitcast ( VT , V ) ; } if ( EltVT == <STR_LIT> ) { SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue V32 = DAG . getBitcast ( VT , V ) ; SDValue Low = DAG . getNode ( <STR_LIT> , DL , VT , V32 , Zeros ) ; SDValue High = DAG . getNode ( <STR_LIT> , DL , VT , V32 , Zeros ) ; Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; Low = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , Low ) , Zeros ) ; High = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , High ) , Zeros ) ; MVT ShortVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ShortVecVT , Low ) , DAG . getBitcast ( ShortVecVT , High ) ) ; return DAG . getBitcast ( VT , V ) ; } assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; SDValue ShifterV = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( VT , V ) , ShifterV ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ByteVecVT , Shl ) , DAG . getBitcast ( ByteVecVT , V ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast


<s> SDValue MulVal = DAG . getNode ( <STR_LIT> , DL , VT , N0 , MulOper ) ; return DAG . getNode ( AddSubOpc , DL , VT , N0 , MulVal ) ; } if ( ! isa < ConstantSDNode > ( N1 ) ) return SDValue ( ) ; ConstantSDNode * C = cast < ConstantSDNode > ( N1 ) ; const APInt & ConstValue = C -> getAPIntValue ( ) ; if ( IsSVECntIntrinsic ( N0 ) || ( N0 -> getOpcode ( ) == <STR_LIT> && ( IsSVECntIntrinsic ( N0 -> getOperand ( <NUM_LIT> ) ) ) ) ) if ( ConstValue . sge ( <NUM_LIT> ) && ConstValue . sle ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned TrailingZeroes = ConstValue . countTrailingZeros ( ) ; if ( TrailingZeroes ) { if ( N0 -> hasOneUse ( ) && ( isSignExtended ( N0 . getNode ( ) , DAG ) || isZeroExtended ( N0 . getNode ( ) , DAG ) ) ) return SDValue ( ) ; if ( N -> hasOneUse ( ) && ( N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> || N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; } APInt ShiftedConstValue = ConstValue . ashr ( TrailingZeroes ) ; unsigned ShiftAmt ; bool ShiftValUseIsN0 = true ; bool NegateResult = false ; if ( ConstValue . isNonNegative ( ) ) { APInt SCVMinus1 = ShiftedConstValue - <NUM_LIT> ; APInt CVPlus1 = ConstValue + <NUM_LIT> ; if ( SCVMinus1 . isPowerOf2 ( ) ) { ShiftAmt = SCVMinus1 . logBase2 ( ) ; AddSubOpc = <STR_LIT> ; } else if ( CVPlus1 . isPowerOf2 ( ) ) { ShiftAmt = CVPlus1 . logBase2 ( ) ; AddSubOpc = <STR_LIT> ; } else return SDValue ( ) ; } else { APInt CVNegPlus1 = - ConstValue + <NUM_LIT> ; APInt CVNegMinus1 = - ConstValue - <NUM_LIT> ; if ( CVNegPlus1 . isPowerOf2 (


<s> Size = Msbd + <NUM_LIT> - Pos ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm


<s> word_type neg = <NUM_LIT> ; SItype res ; if ( a < <NUM_LIT> ) { a = - a ; neg = ! neg ; } if ( b < <NUM_LIT> ) { b = - b ; neg = ! neg ; } res = udivmodsi4 ( a


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRI ( SDValue & Addr , SDValue & Base , SDValue & Disp ) { <ISA_LIT>RRIAddressMode AM ( true ) ; bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr ,


<s> rtx insn ; if ( ! TARGET_64BIT ) insn = emit_insn ( gen_pro_epilogue_adjust_stack_1 ( dest , src , offset ) ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = emit_insn ( gen_pro_epilogue_adjust_stack_rex64 ( dest , src , offset ) ) ; else { rtx r11 ; gcc_assert ( style ) ; r11 = gen_rtx_REG ( DImode , FIRST_REX_INT_REG + <NUM_LIT>


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , NULL ) ; else return


<s> return false ; } if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; <ISA_LIT>AddressMode AM ; AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc = getLeaOP ( Ty , STI ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; return constrainSelectedInstRegOperands ( I , TII


<s> while ( curr != t -> rbt_nil ) { int cmp = strcmp ( str , curr -> str ) ; if ( cmp < <NUM_LIT> ) curr =


<s> bool isFPCopy ( MachineInstr * MI ) { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) .


<s> cl_target_option_save ( & cl_opts , opts , opts_set ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , opts_set , false ) ; arm_option_check_internal ( opts ) ; arm_option_reconfigure_globals ( ) ; arm_options_perform_arch_sanity_checks ( ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ,


<s> LegacyLegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegacyLegalizeActions :: Unsupported } , { <NUM_LIT> , LegacyLegalizeActions :: WidenScalar } , { <NUM_LIT> , LegacyLegalizeActions :: Unsupported } , { <NUM_LIT> , LegacyLegalizeActions :: WidenScalar } , { <NUM_LIT> , LegacyLegalizeActions :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> , LegacyLegalizeActions :: Unsupported } ) ; return


<s> GlobalAddressSDNode * GlobalAddr = cast < GlobalAddressSDNode > ( Op . getNode ( ) ) ; SDValue TargetAddr = DAG . getTargetGlobalAddress ( GlobalAddr -> getGlobal ( ) , Op , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , Op , VT , TargetAddr


<s> DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , OffsetBitSize == <NUM_LIT> ? & NewImm : nullptr ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAdduOp ( ) ) , Reg ) . addReg ( FrameReg ) . addReg (


<s> return ( uint64x2_t ) __builtin_aarch64_lceiluv2dfv2di ( __a )


<s> Op -> RegShiftedReg . ShiftTy = ShTy ; Op -> RegShiftedReg . SrcReg = SrcReg ; Op -> RegShiftedReg . ShiftReg = ShiftReg ; Op -> RegShiftedReg . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> bool <ISA_LIT>BaseRegisterInfo :: cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> void addImm0_508s4Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > (


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const


<s> FileOut . close ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( EmitDotOnly ) return false ; } int FencesInserted ; if ( ! OptimizePluginPath . empty ( ) ) { if ( ! OptimizeDL . isValid ( ) ) { std :: string ErrorMsg ; OptimizeDL = llvm :: sys :: DynamicLibrary :: getPermanentLibrary ( OptimizePluginPath . c_str ( ) , & ErrorMsg ) ; if ( ! ErrorMsg . empty ( ) ) report_fatal_error ( <STR_LIT> + ErrorMsg + '\"' ) ; OptimizeCut = ( OptimizeCutT ) OptimizeDL . getAddressOfSymbol ( <STR_LIT> ) ; if ( ! OptimizeCut ) report_fatal_error ( <STR_LIT> ) ; } FencesInserted = hardenLoadsWithPlugin ( MF , std :: move ( Graph ) ) ; } else { FencesInserted = hardenLoadsWithHeuristic ( MF , std


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = llvm :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr ::


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemNoOffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addPostIdxRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> bool function_resolver :: require_vector_type ( unsigned int argno , vector_type_index type ) { tree expected = acle_vector_types [ <NUM_LIT> ] [ type ] ; tree actual = get_argument_type ( argno ) ; if ( ! matches_type_p (


<s> I != MBB -> livein_end ( ) ; ) { MCPhysReg Reg = I -> PhysReg ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { Mask |= <NUM_LIT> << ( Reg - <STR_LIT> ) ; if ( RemoveFPs ) { I = MBB -> removeLiveIn (


<s> uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum +


<s> switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT ANDVT = VT . is128BitVector ( ) ?


<s> switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( )


<s> break ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; DEBUG ( CRI . MI -> getParent ( ) -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; SplitBefore -> dump ( ) ) ; MachineInstr * Branch = MRI -> use_nodbg_begin ( CRI . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getParent ( ) ; MachineBasicBlock * MBB = SplitBefore -> getParent ( ) ; auto FirstTerminator = MBB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator FirstInstrToMove = UsingDef1 ? CRI . TrueDefs . first : CRI . TrueDefs . second ; MachineBasicBlock :: iterator SecondInstrToMove = UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second ; MBB -> splice ( FirstTerminator , MBB , FirstInstrToMove ) ; if ( FirstInstrToMove != SecondInstrToMove ) MBB -> splice ( FirstTerminator , MBB , SecondInstrToMove ) ; MBB -> splice ( FirstTerminator , MBB , CRI . MI ) ; unsigned Opc = CRI . MI -> getOpcode ( ) ; bool InvertOrigBranch , InvertNewBranch , TargetIsFallThrough ; computeBranchTargetAndInversion ( Opc , Branch -> getOpcode ( ) , UsingDef1 , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough ) ; MachineInstr * SplitCond = UsingDef1 ? CRI . CopyDefs . second : CRI . CopyDefs . first ; DEBUG ( dbgs ( ) << <STR_LIT> << ( InvertNewBranch ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( TargetIsFallThrough ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Branch -> dump ( ) ) ; BlockSplitInfo BSI { Branch , SplitBefore , SplitCond , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough , MBPI , CRI . MI , UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second } ; bool Changed = splitMBB ( BSI ) ; if ( Changed ) { bool Input1CRlogical = CRI . TrueDefs . first && isCRLogical ( * CRI . TrueDefs . first ) ; bool Input2CRlogical = CRI . TrueDefs . second && isCRLogical ( * CRI . TrueDefs . second ) ; if ( Input1CRlogical ) AllCRLogicalOps . push_back ( createCRLogicalOpInfo ( * CRI . TrueDefs . first ) ) ; if ( Input2CRlogical ) AllCRLogicalOps . push_back ( createCRLogicalOpInfo ( * CRI . TrueDefs . second


<s> unsigned getScratchReg ( ) { for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( ! isLive ( i ) ) return i ; llvm_unreachable (


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _wrssq ( unsigned long long __B , void * __C ) { __builtin_ia32_wrssq ( __B ,


<s> bool ret = rs6000_rtx_costs ( x , code , outer_code , opno , total , speed ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_RTX_NAME ( code ) , GET_RTX_NAME ( outer_code ) , opno , * total , speed ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( x ) ; return


<s> return isUInt < <NUM_LIT> > ( static_cast < int32_t > ( Value ) ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return


<s> if ( VT == <STR_LIT> || ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT . getSimpleVT ( ) ==


<s> unsigned RR = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src ) ; if ( RR != <NUM_LIT>


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName


<s> unsigned Idx = <NUM_LIT> ; bool isThumb = false ; if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) Idx = <NUM_LIT> ; else if ( Len >= <NUM_LIT> && TT . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { isThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } bool NoCPU = CPU == <STR_LIT> || CPU . empty ( ) ; std :: string <ISA_LIT>ArchFeature ; if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'e' && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 's' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) )


<s> if ( TT . getSubArch ( ) == llvm :: Triple :: <ISA_LIT>SubArch_r6 ) { if ( TT . isMIPS32 ( ) ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } else if ( TT . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_cheri128 ) { CPU = <STR_LIT> ; } else if ( TT . getEnvironment ( ) == Triple :: CheriPurecap ) { CPU = <STR_LIT> ; } else { if ( TT . isMIPS32 ( ) ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } } return CPU


<s> if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> )


<s> static void ix86_add_cfa_restore_note ( rtx_insn * insn , rtx reg , HOST_WIDE_INT cfa_offset ) { if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> return __builtin_mve_vrshrq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> return ( uint8x8_t ) __builtin_neon_vget_lowv16qi (


<s> StringRef getPassName ( ) const override { return


<s> static ArrayRef < MCPhysReg > get64BitArgumentXMMs ( MachineFunction & MF , CallingConv :: ID CallConv , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Subtarget . is64Bit ( ) ) ; if ( Subtarget . isCallingConvWin64 ( CallConv ) ) { return None ; } bool isSoftFloat = Subtarget . useSoftFloat ( ) ; if ( isSoftFloat || ! Subtarget . hasSSE1 ( ) ) return None ; static const MCPhysReg XMMArgRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return makeArrayRef ( std :: begin ( XMMArgRegs64Bit ) , std ::


<s> bool IsV1Zeroable = true ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( i != V2Index && ! Zeroable [ i ] ) { IsV1Zeroable = false ; break ; } SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ; if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = -


<s> RTLIB :: Libcall LC = getDivRemLibcall ( N , N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( N , DAG . getContext ( ) , Subtarget ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; SDValue Callee = DAG . getExternalFunctionSymbol ( getLibcallName ( LC ) ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , N , InChain ) ; CallLoweringInfo CLI ( DAG ) ; CLI . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS , RetTy , Callee , std :: move ( Args

) ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) . setDebugLoc ( SDLoc ( N ) ) ;


<s> EVT VT = Op0 . getValueType ( ) ; if ( VT != Op1 . getValueType ( ) || ! VT . isSimple ( ) || ! VT . isInteger ( ) ) return SDValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == VT && supportedVectorShiftWithImm ( VT . getSimpleVT ( ) , Subtarget , <STR_LIT> ) ) { SDValue X , Y ; if ( Op1 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isAllOnesOrAllOnesSplat ( Op1 . getOperand ( <NUM_LIT> ) ) ) { X = Op1 . getOperand ( <NUM_LIT> ) ; Y = Op0 ; } else if ( Op0 . hasOneUse ( ) && Op0 . getOpcode ( ) == <STR_LIT> && isAllOnesOrAllOnesSplat ( Op0 . getOperand ( <NUM_LIT> ) ) ) { X = Op0 . getOperand ( <NUM_LIT> ) ; Y = Op1 ; } if ( X && Y ) { SDLoc DL ( N ) ; SDValue Sra = getTargetVShiftByConstNode ( <STR_LIT> , DL , VT . getSimpleVT ( ) , X , VT . getScalarSizeInBits ( ) - <NUM_LIT> , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Sra , Y ) ; } } APInt SplatVal ; if ( ! <STR_LIT> ( Op1 . getNode ( ) , SplatVal ) || ! SplatVal . isMask ( ) ) return SDValue ( ) ; if ( isBitwiseNot ( Op0 ) ) return SDValue ( ) ; if ( ! supportedVectorShiftWithImm ( VT . getSimpleVT ( ) , Subtarget , <STR_LIT> ) ) return SDValue ( ) ; unsigned EltBitWidth = VT . getScalarSizeInBits ( ) ; if ( EltBitWidth != DAG . ComputeNumSignBits ( Op0 ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned ShiftVal = SplatVal . countTrailingOnes ( ) ; SDValue ShAmt = DAG . getTargetConstant ( EltBitWidth - ShiftVal , DL , <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL ,


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo &


<s> void addDupAlignedMemory64Operands ( MCInst & Inst


<s> return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type )


<s> assert ( ISD && <STR_LIT> ) ; if ( ST -> hasVSX ( ) && Val -> getScalarType ( ) -> isDoubleTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ; return BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ; } else if ( ST -> hasQPX ( ) && Val -> getScalarType ( ) -> isFloatingPointTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ; return BaseT :: getVectorInstrCost ( Opcode , Val ,


<s> MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg (


<s> } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Flipped = DAG . getBitcast


<s> if ( HasSoftFloat ) HasVector = false ; if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; } return *


<s> if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( )


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] )


<s> int RegNum = - <NUM_LIT> ; APInt IntVal ( <NUM_LIT> , - <NUM_LIT> ) ; if ( ! DefSymbol . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) ) RegNum = matchRegisterByNumber ( IntVal . getZExtValue ( ) , is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; else { switch ( Kind ) { case <STR_LIT> : case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) , FP_FORMAT_D ) ; break ; case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) , FP_FORMAT_S ) ; break ; case <STR_LIT> : case <STR_LIT> : default : RegNum = matchRegisterName ( DefSymbol . substr ( <NUM_LIT> ) , is<ISA_LIT>64 ( ) ) ; break ; } } if ( RegNum > - <NUM_LIT> ) { Parser . Lex ( ) ; <ISA_LIT>Operand * op = <STR_LIT> ( RegNum , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind (


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; assert ( Opc && <STR_LIT>


<s> rtx d30v_expand_builtin_saveregs ( ) { int offset = UNITS_PER_WORD * ( GPR_ARG_LAST + <NUM_LIT> - GPR_ARG_FIRST ) ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , offset


<s> case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this ) ; case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( )


<s> SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , N0 ) ; SDValue Ops [ ] = { N0 , Neg , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE41 ( ) ) { SDLoc DL ( Op )


<s> } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; if ( ! MBB . isLiveIn ( <STR_LIT> )


<s> if ( type == TYPE_SUFFIX_u32 || type == TYPE_SUFFIX_u64 ) return type_suffixes [ type ] . vector_type ; error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , <STR_LIT> , <STR_LIT> ) ; return NUM_VECTOR_TYPES


<s> assert ( RegNo < N && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Regs [ RegNo ] ) ) ; return MCDisassembler ::


<s> void <ISA_LIT>ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel


<s> if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT>


<s> int normal_length ; shorten_branches ( get_insns ( ) ) ; normal_length = ( TARGET_MIPS16 ? <NUM_LIT> : <NUM_LIT> ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( JUMP_P ( subinsn ) && get_attr_length ( subinsn )

> normal_length && ( any_condjump_p ( subinsn ) || any_uncondjump_p ( subinsn ) ) ) return true ;


<s> void <ISA_LIT>TargetStreamer :: emitPad ( int64_t


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx


<s> assert ( Op . getValueType ( ) . isScalableVector ( ) && isTypeLegal ( Op . getValueType ( ) ) && <STR_LIT> ) ; if ( isTypeLegal ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) && Op . getNumOperands ( ) == <NUM_LIT> ) return Op ; return SDValue


<s> __vector unsigned int a , b ; __vector unsigned int c , d ; static const __vector unsigned int float_exp_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int )


<s> static __inline void si_hgt ( qword a , qword b ) { union { vector signed int v ; signed int i [ <NUM_LIT> ] ; } aa , bb ; aa . v = ( vector signed int ) ( a


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get (

<STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ;


<s> MemOp = DAG . getMemcpy ( Chain , dl , PtrOff , Arg , SizeNode , Flags . getByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; } else { MemOp = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; Ops . push_back ( DAG . getRegisterMask ( TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag


<s> } SmallVector < <ISA_LIT>_IMM :: ImmInsnModel , <NUM_LIT> > Insn ; <ISA_LIT>_IMM :: expandMOVImm ( Imm , BitSize , Insn ) ; assert ( Insn . size ( ) != <NUM_LIT> ) ; SmallVector < MachineInstrBuilder , <NUM_LIT> > MIBS ; for ( auto I = Insn . begin ( ) , E = Insn . end ( ) ; I != E ; ++ I ) { bool LastItem = std :: next ( I ) == E ; switch ( I -> Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : { Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg


<s> fmask |= ( ( <NUM_LIT> << FP_INC ) - <NUM_LIT> ) << ( regno - FP_REG_FIRST ) ; } } gp_reg_rounded = MIPS_STACK_ALIGN ( gp_reg_size ) ; total_size += gp_reg_rounded + MIPS_STACK_ALIGN ( fp_reg_size ) ; total_size += current_function_pretend_args_size ; total_size += MIPS_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; cfun -> machine -> frame . total_size = total_size ; cfun -> machine -> frame . var_size = var_size ; cfun -> machine -> frame . args_size = args_size ; cfun -> machine -> frame . cprestore_size = cprestore_size ; cfun -> machine -> frame . gp_reg_size = gp_reg_size ; cfun -> machine -> frame . fp_reg_size = fp_reg_size ; cfun -> machine -> frame . mask = mask ; cfun -> machine -> frame . fmask = fmask ; cfun -> machine -> frame . initialized = reload_completed ; cfun -> machine -> frame . num_gp = gp_reg_size / UNITS_PER_WORD ; cfun -> machine -> frame . num_fp = fp_reg_size / ( FP_INC * UNITS_PER_FPREG ) ; if ( mask


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo


<s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasSVE ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors ( ) ) return false ; return isElementTypeLegalForScalableVector ( DataType -> getScalarType (


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature (


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrAddiuOp ( )


<s> return ( __m512d ) __builtin_ia32_getexppd512_mask ( ( __v8df ) __A , ( __v8df ) _mm512_setzero_pd ( )


<s> } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState


<s> SDValue Vec ; if ( Size == <NUM_LIT> ) { if ( HasInt256 ) { SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( Size == <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable


<s> bool loongarch_split_move_p ( rtx dest , rtx src ) { unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == <NUM_LIT> && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == <NUM_LIT> ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return size >


<s> if ( ST -> isMisaligned128StoreSlow ( ) && Opcode == Instruction :: Store && LT . second . is128BitVector ( ) && ( ! Alignment || * Alignment < Align ( <NUM_LIT> ) ) ) { const int AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( useNeonVector ( Ty ) && cast < VectorType > ( Ty ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ProfitableNumElements ; if ( Opcode == Instruction :: Store ) ProfitableNumElements = <NUM_LIT> ; else ProfitableNumElements = <NUM_LIT> ; if ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) <


<s> unsigned int align ; unsigned int flags = default_section_type_flags_1 ( decl , name , reloc , <NUM_LIT> ) ; if ( flags & SECTION_CODE ) align =


<s> StringRef Sym ; if ( const GlobalAddressSDNode * G = dyn_cast_or_null < const GlobalAddressSDNode > ( TargetAddr ) ) { Sym = G -> getGlobal ( ) -> getName ( ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( TargetAddr ) ) { Sym = ES -> getSymbol ( ) ; } if ( Sym . empty ( ) ) return ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; MCSymbol * S = MF -> getContext ( ) . getOrCreateSymbol ( Sym ) ; MI . addOperand ( MachineOperand :: CreateMCSymbol ( S , <STR_LIT>


<s> if ( Origin -> getOpcode ( ) != <STR_LIT> ) return true ; MachineMemOperand * MMO = cast < LoadSDNode > ( Origin ) -> getMemOperand ( ) ; if ( ! Subtarget . hasP9Vector ( ) && MMO -> getSize ( ) <= <NUM_LIT> ) return true ; for ( SDNode :: use_iterator UI = Origin -> use_begin ( ) , UE = Origin -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . get ( ) . getResNo ( ) !=


<s> if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ; return


<s> vld4q_dup_f32 ( const float32_t * __a ) { float32x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf (


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber


<s> static int ia64_spec_check_src_p ( rtx src ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) { rtx t ; t = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( t ) == NE ) { t = XEXP ( t , <NUM_LIT> ) ; if ( GET_CODE ( t ) == UNSPEC ) { int code ; code = XINT ( t , <NUM_LIT> ) ; if ( code == UNSPEC_LDCCLR || code == UNSPEC_LDCNC || code == UNSPEC_CHKACLR || code == UNSPEC_CHKANC || code == UNSPEC_CHKS ) { gcc_assert ( code != <NUM_LIT> ) ; return code ; } } } } return <NUM_LIT>


<s> static const std :: pair < unsigned , std :: pair < unsigned , unsigned >> VFMKMap [ ] = { { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , } ; unsigned Opcode = MI . getOpcode ( ) ; const auto * Found = llvm :: find_if ( VFMKMap , [ & ] ( auto P ) { return P . first == Opcode ; } ) ; if ( Found == std :: end ( VFMKMap


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ; } else if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr