<s> AVAIL ( hard_float , TARGET_HARD_FLOAT ) { CODE_FOR_riscv_ ## INSN , <STR_LIT> NAME , \ BUILTIN_TYPE , FUNCTION_TYPE , riscv_builtin_avail_ ## AVAIL } RISCV_BUILTIN ( INSN , # INSN , RISCV_BUILTIN_DIRECT , FUNCTION_TYPE , AVAIL ) RISCV_BUILTIN ( INSN , # INSN , RISCV_BUILTIN_DIRECT_NO_TARGET , \ FUNCTION_TYPE , AVAIL ) RISCV_ATYPE_ ## A RISCV_ATYPE_ ## A , RISCV_ATYPE_ ## B static const struct riscv_builtin_description riscv_builtins [ ] = { DIRECT_BUILTIN ( frflags , RISCV_USI_FTYPE , hard_float ) , DIRECT_NO_TARGET_BUILTIN ( fsflags , RISCV_VOID_FTYPE_USI , hard_float ) } ; static GTY ( ( ) ) tree riscv_builtin_decls [ ARRAY_SIZE ( riscv_builtins ) ] ; static GTY ( ( ) ) int riscv_builtin_decl_index [ NUM_INSN_CODES ] ; riscv_builtin_decls [ riscv_builtin_decl_index [ ( CODE ) ] ] static tree riscv_build_function_type ( enum riscv_function_type type ) { static tree types [ ( int ) RISCV_MAX_FTYPE_MAX ] ; if ( types [ ( int ) type ] == NULL_TREE ) switch ( type ) { case RISCV_FTYPE_NAME ## NUM ARGS : \ types [ ( int ) type ] \ = build_function_type_list ( RISCV_FTYPE_ATYPES ## NUM ARGS , \ NULL_TREE ) ; \ break ; default : gcc_unreachable ( ) ; } return types [ ( int ) type ] ; } void riscv_init_builtins ( void ) { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ]


<s> void <ISA_LIT>Operand :: print ( raw_ostream &


<s> if ( Pmode == DImode ) return gen_tls_add_tp_ledi ( dest , base , tp , sym ) ; else return gen_tls_add_tp_lesi ( dest ,


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB


<s> ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDLoc DL ( Op ) ; SDValue Val = DAG . getNode ( MaskOpc , DL , ContainerVT


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation =


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL ) const { if ( FBB ) { unsigned count = InsertBranchAtInst ( MBB , MBB . end ( ) , TBB , Cond , DL ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; count ++


<s> const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) .

addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;


<s> static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp ,


<s> SequenceMBBI != E ; ++ SequenceMBBI ) { if ( SequenceMBBI -> isDebugInstr ( ) ) continue ; else if ( isSelectPseudo ( * SequenceMBBI ) ) { if ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != LHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != RHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != CC || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; LastSelectPseudo = & * SequenceMBBI ; SequenceMBBI -> collectDebugValues ( SelectDebugValues ) ; SelectDests . insert ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { if ( SequenceMBBI -> hasUnmodeledSideEffects ( ) || SequenceMBBI -> mayLoadOrStore ( ) ) break ; if ( llvm :: any_of ( SequenceMBBI -> operands ( ) , [ & ] ( MachineOperand & MO ) { return MO . isReg ( ) && MO . isUse ( ) && SelectDests . count ( MO . getReg ( ) ) ; } ) ) break ; } } const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; BuildMI ( HeadMBB , DL , TII . getBrCond ( CC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) )


<s> case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ; else if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_addr_const ( file , riscv_strip_unspec_address


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIP ( SDValue Dest , SDValue & SRC1 , SDValue


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) )


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr


<s> return gen_rtx_REG ( Pmode , get_avl_source ( ) -> regno


<s> case FK_Data_8 : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value


<s> I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( )


<s> bool isSImm5Plus1 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr ::


<s> unsigned bne = RC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned zero = RC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , DL , TII -> get ( bne ) ) . addMBB ( sinkMBB ) . addReg ( zero ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * copy0MBB , copy0MBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , VReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , VReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * copy0MBB , copy0MBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , VReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( VReg ) . addMBB ( copy0MBB ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg


<s> <ISA_LIT>SExtWRemoval ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>SExtWRemovalPass ( * PassRegistry :: getPassRegistry


<s> Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Store -> getChain ( ) , IntID , Val , Store -> getBasePtr ( ) , Mask , VL } , Store -> getMemoryVT ( ) , Store


<s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK ==


<s> bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegVR = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success ; } if ( IsRegVR && ( Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8 ) ) { Op . Reg . RegNum = convertVRToVRMx ( * getContext ( ) . getRegisterInfo ( ) , Reg , Kind ) ; if ( Op . Reg . RegNum

== <NUM_LIT> ) return Match_InvalidOperand ;


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI

) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> static rtx_insn * riscv_sr_match_epilogue ( void ) { rtx_insn * insn , * start ; for ( insn = get_insns ( ) ; insn != NULL ; insn = NEXT_INSN ( insn ) ) if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_EPILOGUE_BEG ) { insn = NEXT_INSN ( insn ) ; break ; } if ( insn == NULL ) return NULL ; start = insn ; if ( INSN_CODE ( insn ) != CODE_FOR_stack_tiesi && INSN_CODE ( insn ) != CODE_FOR_stack_tiedi ) return NULL ; insn = NEXT_INSN ( insn ) ; if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == USE


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser >


<s> static uint8_t compressedLDSTOffsetMask ( unsigned Opcode ) { return <NUM_LIT> << log2LdstWidth


<s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT VecVT = Op . getSimpleValueType ( ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; int64_t ImmValue = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SDValue DownOffset , UpOffset ; if ( ImmValue >= <NUM_LIT> ) { DownOffset = DAG . getConstant ( ImmValue , DL , XLenVT ) ; UpOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax ,


<s> if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_32 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64 ) . Default ( - <NUM_LIT> ) ; if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind

> ( FirstLiteralRelocationKind + Type ) ;


<s> bool hasVInstructionsF64 ( ) const { return HasStdExtV || ( HasStdExtZve64d && HasStdExtD


<s> bool Unsigned = false ; if ( ! isInt < <NUM_LIT> > ( Val ) ) { ShiftAmount = findFirstSet ( ( uint64_t ) Val ) ; Val >>= ShiftAmount ; if ( ShiftAmount > <NUM_LIT> && ! isInt < <NUM_LIT> > ( Val ) ) { if ( isInt < <NUM_LIT> > ( ( uint64_t ) Val << <NUM_LIT> ) ) { ShiftAmount -= <NUM_LIT> ; Val = ( uint64_t ) Val << <NUM_LIT> ; } else if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Val << <NUM_LIT> ) && ActiveFeatures [ <STR_LIT> ] ) { ShiftAmount -= <NUM_LIT> ; Val = ( ( uint64_t ) Val << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } } if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Val ) && ! isInt < <NUM_LIT> > ( ( uint64_t ) Val ) && ActiveFeatures [ <STR_LIT> ] ) { Val = ( ( uint64_t ) Val ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } } generateInstSeqImpl ( Val , ActiveFeatures ,


<s> if ( isZeroOrAllOnes ( TrueVal , AllOnes ) ) { SwapSelectOps = false ; NonConstantVal = FalseVal ; } else if ( isZeroOrAllOnes ( FalseVal , AllOnes ) ) { SwapSelectOps = true ; NonConstantVal = TrueVal ; } else return SDValue ( ) ; TrueVal = OtherOp ; FalseVal = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , OtherOp , NonConstantVal ) ; if ( SwapSelectOps ) std :: swap ( TrueVal , FalseVal


<s> OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; if ( Result == MatchOperand_Success ) return false ; if ( Result == MatchOperand_ParseFail ) return true ; if ( parseRegister ( Operands , true ) == MatchOperand_Success ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; } return


<s> return ( Subtarget . hasStdExtZbb ( ) || Subtarget . hasStdExtZbp ( ) || Subtarget . hasStdExtZbkb ( ) )


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( )


<s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; } unsigned BaseOpc ; <STR_LIT> CC ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : { SDValue TrueMask = DAG . getNode ( <STR_LIT> , DL , ContainerVT , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Vec , TrueMask , VL ) ; Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; CC = <STR_LIT> ; BaseOpc = <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , Mask , VL ) ; CC = <STR_LIT> ; BaseOpc = <STR_LIT> ; break ; case <STR_LIT>


getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ;


<s> switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info ->


<s> bool isUImm3 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK ==


<s> SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Src . getSimpleValueType ( ) ; SDValue Mask , VL ; if ( IsVPTrunc ) { Mask = Op . getOperand ( <NUM_LIT> ) ; VL = Op . getOperand ( <NUM_LIT> ) ; } MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; if ( IsVPTrunc ) { MVT MaskContainerVT = getContainerForFixedLengthVector ( Mask . getSimpleValueType ( ) ) ; Mask = convertToScalableVector ( MaskContainerVT , Mask , DAG , Subtarget ) ; } } if ( ! IsVPTrunc ) { std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL ,


<s> return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent : return PtrIsCap ? <STR_LIT> :


<s> bool <ISA_LIT>ExpandPseudo :: expandAuipcInstPair ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI , unsigned FlagsHi , unsigned SecondOpcode ) { MachineFunction * MF = MBB . getParent ( ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , FlagsHi ) ; BuildMI ( NewMBB , DL , TII -> get ( SecondOpcode ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( NewMBB ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * NewMBB ) ; NextMBBI = MBB . end


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT>


<s> unsigned int ratio = calculate_ratio ( sew , vlmul ) ; if ( ! optimize ) emit_hard_vlmax_vsetvl ( vmode , vl ) ; else emit_insn ( gen_vlmax_avl ( Pmode , vl , gen_int_mode ( ratio , Pmode )


<s> return std :: tie ( VLMul , SEW , TailAgnostic , MaskAgnostic ) == std :: tie ( Other . VLMul , Other . SEW ,

Other . TailAgnostic , Other . MaskAgnostic ) ;


<s> create_fixed_operand ( & m_ops [ opno ++


<s> static uint8_t compressedLDSTOffsetMask ( unsigned Opcode ) { return <NUM_LIT> << log2LdstWidth ( Opcode


<s> return new <ISA_LIT>ConstantPoolValue ( GV


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> ,


<s> rtx insn ; bool need_barrier_p = known_ne ( get_frame_size ( ) + cfun -> machine -> frame . arg_pointer_offset , <NUM_LIT> ) ; if ( cfun -> machine -> naked_p ) { gcc_assert ( style == NORMAL_RETURN ) ; emit_jump_insn ( gen_return ( ) ) ; return ; } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; poly_int64 adjust_offset = - frame -> hard_frame_pointer_offset ; rtx adjust = NULL_RTX ; if ( ! adjust_offset . is_constant ( ) ) { rtx tmp1 = RISCV_PROLOGUE_TEMP ( Pmode ) ; rtx tmp2 = RISCV_PROLOGUE_TEMP2 ( Pmode ) ; riscv_legitimize_poly_move ( Pmode , tmp1 , tmp2 , gen_int_mode ( adjust_offset , Pmode ) ) ; adjust = tmp1 ; } else { if ( ! SMALL_OPERAND ( adjust_offset . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( adjust_offset . to_constant ( ) ) ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } else adjust = GEN_INT ( adjust_offset . to_constant ( ) ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , gen_int_mode ( - frame -> hard_frame_pointer_offset , Pmode ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( known_gt ( step1 , <NUM_LIT> ) ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; if ( ! step1 . is_constant ( ) ) { poly_int64 scalable_frame


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi ,


<s> unsigned opcode = issub ? ( unsign ? <STR_LIT> : <STR_LIT> ) : ( unsign ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder paddrnMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; paddrnMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; paddrnMI . addOperand ( MI . getOperand ( reg1 ) ) ; paddrnMI . addOperand ( MI . getOperand ( reg2 ) ) ; paddrnMI . addImm ( n2 ) ; } else { MachineInstrBuilder sra = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; sra . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; sra . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; sra . addImm ( n2 ) ; MachineInstrBuilder addsub = BuildMI ( * BB , sra . getInstr ( ) , DL , TII -> get ( <STR_LIT> ) ) ; addsub . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; addsub . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; addsub . addImm ( n1 ) ; MachineInstrBuilder add = BuildMI ( * BB , addsub . getInstr ( ) , DL , TII -> get ( issub ?


<s> static void riscv_save_restore_reg ( enum machine_mode mode , int regno , HOST_WIDE_INT offset , riscv_save_restore_fn fn ) { rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode ,


<s> if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned


<s> MCRegister Reg = <STR_LIT> ; switch ( RegNo ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : Reg = <STR_LIT> ; break ; case <NUM_LIT> : break ; } Inst . addOperand ( MCOperand ::


<s> case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ; Tail . getOperand ( <NUM_LIT> ) . setReg ( HiLUI . getOperand ( <NUM_LIT>


<s> case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> :


<s> unsigned ZERO = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( const auto & I : CSI ) { int64_t Offset = MFI -> getObjectOffset ( I . getFrameIdx ( ) ) ; unsigned Reg = I . getReg ( ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( <ISA_LIT>FI -> getCallsEhReturn ( ) ) { const TargetRegisterClass * RC = & <STR_LIT> ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ;


<s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK ==


<s> assert ( ( ( frontOperand . isReg ( ) && backOperand . isReg ( ) ) || ( frontOperand . isImm ( ) && backOperand . isImm ( ) ) ) && <STR_LIT> ) ; if ( order ) { if ( frontOperand . isReg ( ) && backOperand . isReg ( ) && backOperand . getReg ( ) != <STR_LIT> && frontOperand . getReg ( ) != backOperand . getReg ( ) ) return false ; } else { if ( frontOperand . isReg ( ) && backOperand . isReg ( ) && frontOperand . getReg ( ) != backOperand . getReg ( ) ) return false ; } if ( frontOperand . isImm ( ) && backOperand . isImm ( ) && ! ( frontOperand . getImm ( ) == backOperand . getImm ( ) ) ) return false ; } return true


<s> int zero_extend_p ; temp_reg = gen_reg_rtx ( word_mode ) ; zero_extend_p = ( LOAD_EXTEND_OP ( mode ) == ZERO_EXTEND ) ; emit_insn ( gen_extend_insn ( temp_reg , src , word_mode , mode , zero_extend_p ) ) ; riscv_emit_move ( dest , gen_lowpart ( mode , temp_reg ) ) ; return true ; } if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { rtx reg ; if ( GET_CODE ( src ) == CONST_INT ) { machine_mode promoted_mode = mode ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) . to_constant ( ) < UNITS_PER_WORD ) promoted_mode = word_mode ; if ( splittable_const_int_operand ( src , mode ) ) { reg = gen_reg_rtx ( promoted_mode ) ; riscv_move_integer ( reg , reg , INTVAL ( src ) , mode , FALSE ) ; } else reg = force_reg ( promoted_mode , src ) ; if ( promoted_mode != mode ) reg = gen_lowpart ( mode , reg ) ; } else reg = force_reg ( mode , src ) ; riscv_emit_move ( dest


<s> rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { riscv_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest ,


<s> if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O


<s> expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandCIncOffsetTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc (


<s> set_optab_libfunc ( smul_optab , HFmode , NULL ) ; set_optab_libfunc ( neg_optab , HFmode , NULL ) ; set_optab_libfunc ( sub_optab , HFmode , NULL ) ; set_optab_libfunc ( eq_optab , HFmode , NULL ) ; set_optab_libfunc ( ne_optab , HFmode , NULL ) ; set_optab_libfunc ( lt_optab , HFmode , NULL ) ; set_optab_libfunc ( le_optab , HFmode , NULL ) ; set_optab_libfunc ( ge_optab , HFmode , NULL


<s> ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable (


<s> SDValue NewOp2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOp1 , NewOp2 ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType


<s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI .

isFrameAddressTaken ( ) || RVFI -> hasSpillVRs ( ) ;


<s> unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> <NUM_LIT> , <NUM_LIT> ) ; rtx hi = gen_reg_rtx ( mode ) , lo = gen_reg_rtx ( mode ) ; riscv_move_integer ( hi , hi , hival , mode , FALSE ) ; riscv_move_integer ( lo , lo , loval , mode , FALSE ) ; hi = gen_rtx_fmt_ee ( ASHIFT , mode , hi , GEN_INT ( <NUM_LIT> ) ) ; hi = force_reg ( mode , hi ) ; return gen_rtx_fmt_ee ( PLUS , mode , hi ,


<s> void <ISA_LIT>InstPrinter :: printUimm32contig0Operand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O <<


<s> MCInst UncompressedMI ; if ( PrintAliases && ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( ! PrintAliases || NoAliases || ! printAliasInstr ( NewMI , Address , STI ,

O ) ) printInstruction ( NewMI , Address , STI , O ) ;


<s> SDLoc DL ( N ) ; if ( <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; if ( IsLocal && CanDeriveFromPcc ) { return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; } SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; return Load ; } if ( isPositionIndependent ( ) ) { SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; if ( IsLocal ) return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MemOp = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , LLT ( Ty . getSimpleVT ( ) ) , Align ( Ty . getFixedSizeInBits ( ) / <NUM_LIT> ) ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load . getNode ( ) ) , { MemOp } ) ; return Load ; } switch ( getTargetMachine ( ) .


<s> copyPhysReg ( MBB , MBBI , DL , DstReg ,

SrcReg , KillSrc , MachineInstr :: NoFlags ) ;


<s> return static_cast < VLMUL > ( ( TSFlags & VLMulMask ) >> VLMulShift


<s> Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ; return true


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( &


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex


<s> FunctionPass * create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo (


<s> if ( Name . getAsInteger ( <NUM_LIT> , Sew ) ) goto MatchFail ; if ( ! <ISA_LIT>VType :: isValidSEW ( Sew ) ) goto MatchFail ; Name = VTypeIElements [ <NUM_LIT> ] . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) goto MatchFail ; bool Fractional = Name . consume_front ( <STR_LIT> ) ; unsigned Lmul ; if ( Name . getAsInteger ( <NUM_LIT> , Lmul ) ) goto MatchFail ; if ( ! <ISA_LIT>VType :: isValidLMUL ( Lmul , Fractional ) ) goto MatchFail ; Name = VTypeIElements [ <NUM_LIT> ] . getIdentifier ( ) ; bool TailAgnostic ; if ( Name == <STR_LIT> ) TailAgnostic = true ; else if ( Name == <STR_LIT> ) TailAgnostic = false ; else goto MatchFail ; Name = VTypeIElements [ <NUM_LIT> ] . getIdentifier ( ) ; bool MaskAgnostic ; if ( Name == <STR_LIT> ) MaskAgnostic = true ; else if ( Name == <STR_LIT> ) MaskAgnostic = false ; else goto MatchFail ; unsigned LmulLog2 = Log2_32 ( Lmul ) ; <STR_LIT> VLMUL = static_cast < <STR_LIT> > ( Fractional ? <NUM_LIT> - LmulLog2 : LmulLog2 ) ; unsigned VTypeI = <ISA_LIT>VType :: encodeVTYPE ( VLMUL , Sew , TailAgnostic , MaskAgnostic ) ; Operands . push_back ( <ISA_LIT>Operand :: createVType ( VTypeI , S , isRV64 ( ) ) ) ; return MatchOperand_Success ; } MatchFail : while ( ! VTypeIElements . empty ( ) ) getLexer ( ) . UnLex ( VTypeIElements . pop_back_val ( ) ) ; return MatchOperand_NoMatch


<s> assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) doLocalPrepass ( MBB ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) { HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; BlockData & BBInfo = BlockInfo [ MBB . getNumber ( ) ] ; BBInfo . Exit = BBInfo . Change ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> << BBInfo . Exit << <STR_LIT> ) ; } if ( ! HaveVectorOp ) { BlockInfo . clear ( ) ; return false ; } for ( const MachineBasicBlock & MBB : MF ) { WorkList . push ( & MBB ) ; BlockInfo [ MBB . getNumber ( ) ] . InQueue = true ; } while ( ! WorkList . empty ( ) ) { const MachineBasicBlock & MBB = * WorkList . front ( ) ; WorkList . pop ( ) ; computeIncomingVLVTYPE ( MBB ) ; } for ( MachineBasicBlock & MBB : MF ) doPRE ( MBB ) ; for ( MachineBasicBlock & MBB : MF ) emitVSETVLIs ( MBB ) ; for ( MachineBasicBlock & MBB : MF ) doLocalPostpass ( MBB ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { Register VRegDef = MI . getOperand ( <NUM_LIT> ) .


<s> vwrite_csr ( enum RVV_CSR csr , unsigned long value ) { switch ( csr ) { case RVV_VSTART : __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( value ) : <STR_LIT> ) ; break ; case RVV_VXSAT : __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( value


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget . is64Bit ( ) && ! isPositionIndependent ( ) && getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) { return MachineJumpTableInfo ::


<s> } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else llvm_unreachable ( <STR_LIT>


<s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> )


<s> lowerADD ( SDValue Op , SelectionDAG &


<s> assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> return ggc_cleared_alloc < machine_function >


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm (


<s> } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; bool IsLegalInsert = Subtarget . is64Bit ( ) || Val . getValueType ( ) != <STR_LIT> ; if ( ! IsLegalInsert && isa < ConstantSDNode > ( Val ) ) { const auto * CVal = cast < ConstantSDNode > ( Val ) ; if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) { IsLegalInsert = true ; Val = DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ; } } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ValInVec ; if ( IsLegalInsert ) { unsigned Opc = VecVT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; if ( isNullConstant ( Idx ) ) { Vec = DAG . getNode ( Opc , DL , ContainerVT , Vec , Val , VL ) ; if ( ! VecVT . isFixedLengthVector ( ) ) return Vec ; return convertFromScalableVector ( VecVT , Vec , DAG , Subtarget ) ; } ValInVec = DAG . getNode ( Opc , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Val , VL ) ; } else { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ValLo = DAG . getNode ( <STR_LIT> , DL ,


<s> memcpy ( m_old_have_regs_of_mode , have_regs_of_mode , sizeof ( have_regs_of_mode ) ) ; for ( int i = <NUM_LIT> ; i < NUM_MACHINE_MODES ; ++ i ) if ( riscv_v_ext_vector_mode_p ( ( machine_mode ) i ) ) have_regs_of_mode [


<s> MVT FloatVT = <STR_LIT> ( FloatEltVT , VT . getVectorElementCount ( ) ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( FloatVT ) && <STR_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ; Src = DAG . getNode ( <STR_LIT> , DL , VT , Src , Neg ) ; } SDValue FloatVal = DAG . getNode ( <STR_LIT> , DL , FloatVT , Src ) ; EVT IntVT = FloatVT . changeVectorElementTypeToInteger ( ) ; SDValue Bitcast = DAG . getBitcast ( IntVT , FloatVal ) ; unsigned ShiftAmt = FloatEltVT == <STR_LIT> ?


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseCSRSystemRegister ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : { if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; auto * CE = dyn_cast < MCConstantExpr > ( Res ) ; if ( CE ) { int64_t Imm = CE -> getValue ( ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) if ( ( SysReg = <STR_LIT> ( Identifier ) ) ) Warning ( S , <STR_LIT> + Identifier + <STR_LIT> + SysReg -> Name + <STR_LIT> ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( Identifier , S , SysReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ; } Twine Msg = <STR_LIT> <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Percent : { Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> )


<s> static bool riscv_cannot_copy_insn_p ( rtx_insn * insn )


<s> bool supportsScalableVectors ( ) const { return ST -> hasStdExtV ( )


<s> static bool ignore_vlmul_insn_p ( rtx_insn * rinsn ) { return get_attr_type ( rinsn ) == TYPE_VIMOVVX || get_attr_type ( rinsn ) == TYPE_VFMOVVF ||

get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV ;


<s> } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Imm = VT . getSizeInBits ( ) - <NUM_LIT> ; if ( Op . getOpcode ( ) == <STR_LIT> ) Imm &= ~ <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Imm , DL , Subtarget . getXLenVT ( ) ) ) ; } case <STR_LIT> : { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! VT . isVector ( ) ) return Op ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTrunc ( Op , DAG ) ; EVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; SDValue Result = Src ; LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = SrcVT . getVectorElementCount ( ) ; do { SrcEltVT = EVT :: getIntegerVT ( Context , SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT ResultVT = EVT :: getVectorVT ( Context , SrcEltVT , Count ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResultVT , Result ) ; } while ( SrcEltVT != DstEltVT ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , <NUM_LIT> ) ; case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , - <NUM_LIT> ) ; case <STR_LIT> : return lowerSPLATVECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG


<s> void <ISA_LIT>AsmPrinter :: emitEndOfAsmFile ( Module & M ) { <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) )


<s> int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , FI , SrcRC , RI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand


<s> for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) { APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ; InstSeq MatSeq = generateInstSeq ( Chunk . getSExtValue ( ) , ActiveFeatures ) ; Cost += getInstSeqCost ( MatSeq , HasRVC ) ; } return std :: max ( <NUM_LIT>


<s> if ( ! hasSameAVL ( Require ) ) return false ; if ( ! Require . StoreOp && ( TailAgnostic != Require . TailAgnostic ||

MaskAgnostic != Require . MaskAgnostic ) ) return false ;


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT>


<s> case KindTy :: Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy ::


<s> if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ; return true


<s> Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != (


<s> case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : if ( checkPseudoAddTPRel ( Inst , Operands ) ) return true ; } emitToStreamer ( Out , Inst


<s> if ( riscv_abi == ABI_ILP32E ) { for ( int r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) call_used_regs [ r ] = <NUM_LIT> ; } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ; } if ( ! TARGET_VECTOR


<s> SDValue VL ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; SDVTList VTs = DAG . getVTList (


<s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( ) )


<s> Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ; } case <STR_LIT> : { switch ( N -> getConstantOperandVal ( <NUM_LIT> ) ) { default : break ; case <STR_LIT> : SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; EVT ValueVTs [ ] = { Subtarget . getXLenVT ( ) , N -> getValueType ( <NUM_LIT> ) } ; SDValue v = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , DAG . getVTList ( ValueVTs )


<s> MachineFunctionProperties getRequiredProperties ( ) const


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = TM .


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT>

, VK_<ISA_LIT>_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; if ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) curr_prob = profile_probability :: always ( ) ; if ( EXIT_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) continue ; gcc_assert ( curr_prob . initialized_p ( ) ) ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & new_prob = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . probability ; if ( ! new_prob . initialized_p ( ) )

new_prob = curr_prob * e -> probability ;


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; bool Unsigned = false ; if ( ShiftAmount > <NUM_LIT> && ! isInt


<s> riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info . fpr_offset


<s> OperandMatchResultTy parsePairFP64 ( OperandVector &


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end


<s> bool riscv_gpr_save_operation_p ( rtx op ) { unsigned len = XVECLEN ( op , <NUM_LIT> ) ; if ( len > ARRAY_SIZE ( gpr_save_reg_order ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < len ; i ++ ) { rtx elt = XVECEXP ( op , <NUM_LIT> , i ) ; if ( i == <NUM_LIT> ) { if ( GET_CODE ( elt ) != UNSPEC_VOLATILE || GET_CODE ( XVECEXP ( elt , <NUM_LIT> , <NUM_LIT> ) ) != CONST_INT || XINT ( elt ,

<NUM_LIT> ) != UNSPECV_GPR_SAVE ) return false ;


<s> for ( auto Inner : * ML ) { Changed |= ProcessLoop ( Inner , MF ) ; } return Changed ; } auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock * BB = Preheader ; while ( BB != Latch ) { assert ( BB -> succ_size ( ) <= <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock * Next = * BB -> succ_begin ( ) ; if ( BB -> succ_size ( ) == <NUM_LIT> ) { hwlp = false ; for ( auto & MI : BB -> terminators ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { hwlp = true ; if ( Next == MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) { Next = * BB -> succ_rbegin ( ) ; } break ; } } assert ( hwlp && <STR_LIT> ) ; } if ( ! BB -> isLayoutSuccessor ( Next ) ) { MachineBasicBlock * OldPred = Next -> getPrevNode ( ) ; MachineBasicBlock * OldSucc1 = Next -> getNextNode ( ) ; MachineBasicBlock * OldSucc2 = BB -> getNextNode ( ) ; Next -> moveAfter ( BB ) ; OldPred -> updateTerminator ( Next ) ; Next -> updateTerminator ( OldSucc1 ) ; BB -> updateTerminator ( OldSucc2


<s> static poly_uint16 riscv_convert_vector_bits ( void ) { if ( TARGET_MIN_VLEN > <NUM_LIT> ) { riscv_bytes_per_vector_chunk = <NUM_LIT> ; } else { riscv_bytes_per_vector_chunk = <NUM_LIT>


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType


<s> bool getFeatureBits ( uint64_t Feature ) { return getSTI ( ) . getFeatureBits ( ) [ Feature


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) && ( VT . isScalableVector ( ) || Subtarget . useRVVForFixedLengthVectors ( )

) ) return EVT :: getVectorVT ( Context , <STR_LIT> , VT . getVectorElementCount ( ) ) ;


<s> static unsigned get_sew ( machine_mode mode ) { unsigned int sew = GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? <NUM_LIT>

: GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ;


<s> void <ISA_LIT>AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand SourceReg = Inst . getOperand ( <NUM_LIT> ) ; unsigned SecondOpcode = SignExtend ? <STR_LIT> :


<s> bool useSaveRestoreLibCalls ( ) const { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize ==

<NUM_LIT> && ! MF . getFrameInfo ( ) . hasTailCall ( ) ;


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ,


<s> bool WritesElement0 = TSFlags & <STR_LIT> ; <ISA_LIT>VLMUL VLMul = static_cast < <ISA_LIT>VLMUL > ( ( TSFlags & <STR_LIT> ) >> <STR_LIT> ) ; return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , WritesElement0 ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI


<s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI


<s> return <ISA_LIT>VType :: encodeVTYPE ( VLMul , SEW , TailAgnostic , MaskAgnostic


<s> return isImm ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT>


<s> void setIncomingArgSize ( unsigned Size ) { IncomingArgSize = Size


<s> for ( const auto & MFE : ModuleFlags ) { StringRef Key = MFE . Key -> getString ( ) ; if ( Key == <STR_LIT> ) { SSThreshold = mdconst :: extract < ConstantInt > (


<s> return isPowerOf2_32 ( LMUL ) && LMUL <= <NUM_LIT> && ( ! Fractional || LMUL !=


<s> FOR_ALL_BB_FN ( bb , fn ) { regno_map *


<s> static SDValue convertLocVTToValVT ( SelectionDAG & DAG , SDLoc DL , CCValAssign & VA , SDValue Chain , SDValue Value ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , Value , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; else assert ( VA . getLocInfo ( ) == CCValAssign :: Full &&


<s> struct riscv_arg_info arg ; riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode ,


<s> if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ; if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; return simplify_gen_subreg ( word_mode , op ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr


<s> memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT : return riscv_pass_fpr_pair ( mode , fregno , GET_MODE_INNER ( mode ) , <NUM_LIT> , fregno + <NUM_LIT> , GET_MODE_INNER (

mode ) , GET_MODE_UNIT_SIZE ( mode ) ) ;


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT ValVT = VA . getValVT ( ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( IsVarArg ) { auto ArgRegs = IsRV32 ? RV32IntRegs : RV64IntRegs ; unsigned NumRegs = llvm :: <STR_LIT> ; unsigned Idx = CCInfo . getFirstUnallocated ( ArrayRef < MCPhysReg > ( ArgRegs , <NUM_LIT> ) ) ; unsigned RegSize = IsRV32 ? <NUM_LIT> : <NUM_LIT> ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = RoundUpToAlignment ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < NumRegs ; ++ I , VaArgOffset += RegSize ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset ,


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> :


<s> if ( ! Subtarget . useRVVForFixedLengthVectors ( ) ) return false ; if ( VT . getFixedSizeInBits ( ) > <NUM_LIT> * <NUM_LIT> ) return false ; unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; switch ( VT . getVectorElementType ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT>


<s> const <ISA_LIT>TargetLowering * getTLI ( )


<s> error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value :


<s> init_adjust_machine_modes ( ) ; init_derived_machine_modes ( ) ; reinit_regs ( ) ; init_optabs (


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT>


<s> if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std :: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ; return PowerOf2Floor ( Min < <NUM_LIT> ? <NUM_LIT>


<s> if ( Pmode == DImode ) return gen_got_load_tls_iedi ( dest , sym ) ; else return gen_got_load_tls_iesi ( dest , sym


<s> Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; if ( std :: none_of ( CSI . begin ( ) , CSI . end ( ) , [ & ] ( CalleeSavedInfo & CSR ) { return CSR . getReg ( ) == RAReg ; } ) ) return ; Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const <ISA_LIT>InstrInfo * TII = STI .


<s> static unsigned getSCForRMW32 ( bool PtrIsCap , AtomicOrdering Ordering ) { switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT>


<s> step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ; if ( step2 >


<s> DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * LoopHeadMBB ) ; computeAndAddLiveIns ( LiveRegs ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; unsigned BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset ( Offset ) ; Tail . addOperand ( ImmOp ) ; Tail . getOperand ( <NUM_LIT> ) . setReg ( HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DeadInstrs . insert ( & LoADDI ) ; return true ; } break


<s> static Target The<ISA_LIT>64Target ; return


<s> OperandMatchResultTy parseGR64 ( OperandVector &


<s> unsigned OperandIdx = <NUM_LIT> ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , shouldForceImediateOperand ( Name , OperandIdx ) ) ) return true ; ++ OperandIdx ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( )


<s> if ( src_code == CONST_INT ) { if ( SMALL_OPERAND ( INTVAL ( src ) ) || LUI_OPERAND ( INTVAL ( src ) ) ) return <STR_LIT> ; if ( TARGET_ZBS && SINGLE_BIT_MASK_OPERAND ( INTVAL ( src ) ) ) return <STR_LIT> ; abort ( ) ; } if ( src_code == HIGH ) return <STR_LIT> ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return <STR_LIT> ; case SYMBOL_ABSOLUTE : return <STR_LIT> ; case SYMBOL_PCREL : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT>


<s> for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = <NUM_LIT> ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) FrameOverhead = <NUM_LIT> ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , FrameOverhead , MachineOutlinerDefault


<s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK


<s> inline bool registered_function_hasher :: equal ( value_type value ,


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC


<s> std :: vector < std :: string > FeatureVector ; <STR_LIT> ( FeatureVector , STI . getFeatureBits ( ) ) ; auto ParseResult = llvm :: <STR_LIT> ( XLen , FeatureVector ) ; if ( ! ParseResult ) { consumeError ( ParseResult . takeError ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; } else { auto & ISAInfo = *


<s> } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override ; void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override ; bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -=


<s> if ( Hi20 ) Res . push_back ( Inst ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> )


<s> return new yaml :: <ISA_LIT>MachineFunctionInfo


<s> OperandMatchResultTy parseFP32 ( OperandVector & Operands )


<s> if ( IsRV64 ) { return Align ( cc128_get_required_alignment ( Size ) ) ; } else { return Align ( cc64_get_required_alignment ( Size


<s> for ( int i = <NUM_LIT> ; i < NUM_MACHINE_MODES ; ++ i ) if ( riscv_v_ext_vector_mode_p (

( machine_mode ) i ) ) have_regs_of_mode [ i ] = true ;


<s> const char * riscv_output_return ( ) { if ( cfun -> machine -> naked_p ) return <STR_LIT> ; return <STR_LIT>


<s> for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) { APInt Chunk = Val . ashr ( ShiftVal


<s> bool isGPRPF64AsFPR ( ) const { return isGPR ( ) && IsGPRAsFPR && ! IsRV64 && ! ( ( Reg . RegNum


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT>


<s> static rtx riscv_emit_set ( rtx target , rtx src ) { emit_insn ( gen_rtx_SET ( target , src


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , IsVarArg , MF , RetLocs , * DAG . getContext ( ) ) ; if ( Subtarget . isRV64 ( ) ) RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; else RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Glue ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E


<s> return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && IN_RANGE ( INTVAL ( elt )


<s> int64_t NumOfVReg = Amount / <NUM_LIT> ; Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) ; assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ; if ( isPowerOf2_32 ( NumOfVReg ) ) { uint32_t ShiftAmount = Log2_32 ( NumOfVReg ) ; if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , N ) . addReg ( <STR_LIT> ) . addImm ( NumOfVReg ) ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtM ( ) ) MF . getFunction ( ) . getContext

( ) . diagnose ( DiagnosticInfoUnsupported {


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum


<s> bool IsRV64 = ActiveFeatures [ <STR_LIT> ] ; if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; bool Unsigned = false ; if ( ShiftAmount > <NUM_LIT> && ! isInt <


<s> switch ( VLMUL ) { case <STR_LIT> :: LMUL_RESERVED : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :: LMUL_1 : case <STR_LIT> :: LMUL_2 : case <STR_LIT> :: LMUL_4 : case <STR_LIT> :: LMUL_8 : { unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ; } case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F8 : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType ) ) OS << <STR_LIT> ; else OS


<s> <ISA_LIT>MCExpr :: VariantKind <ISA_LIT>MCExpr :: getVariantKindForName ( StringRef name ) { return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI )

. Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn (


<s> for ( llvm :: MachineBasicBlock :: iterator instr : MBB ) { if ( isVsetvli ( * instr ) ) { if ( firstEffectiveVSETVLI == nullptr ) firstEffectiveVSETVLI = & ( * instr ) ; else if ( ( lastEffectiveVSETVLI == nullptr && ! isSameVsetvli ( * firstEffectiveVSETVLI , * instr , true ) ) || ( lastEffectiveVSETVLI && ! isSameVsetvli ( * instr , * lastEffectiveVSETVLI ) ) ) lastEffectiveVSETVLI = & ( * instr ) ; else redundancyVSETVLI . push_back ( & ( * instr ) ) ; } } lastEffectiveVSETVLI = lastEffectiveVSETVLI == nullptr ? firstEffectiveVSETVLI :


<s> { MO_CALL , <STR_LIT> } , { MO_PLT , <STR_LIT> } , { MO_LO , <STR_LIT> } , { MO_HI , <STR_LIT> } , { MO_PCREL_LO , <STR_LIT> } , { MO_PCREL_HI , <STR_LIT> } , { MO_GOT_HI , <STR_LIT> } , { MO_TPREL_LO , <STR_LIT> } , { MO_TPREL_HI , <STR_LIT> } , { MO_TPREL_ADD , <STR_LIT> } , { MO_TLS_GOT_HI , <STR_LIT> } , { MO_TLS_GD_HI , <STR_LIT> } , { MO_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_TPREL_CINCOFFSET , <STR_LIT> } , { MO_TLS_IE_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_TLS_GD_CAPTAB_PCREL_HI , <STR_LIT> } , { MO_CCALL , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>64Target


<s> if ( Op . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Mask = Op . getConstantOperandVal ( <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return None ; bool IsSHL = Op . getOpcode ( ) == <STR_LIT> ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return None ; uint64_t ShAmt = Op . getConstantOperandVal ( <NUM_LIT> ) ; unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ShAmt >= Width || ! isPowerOf2_64 ( ShAmt ) ) return None ; if ( BitmanipMasks . size ( ) == <NUM_LIT> && ShAmt >= ( Width / <NUM_LIT> ) ) return None ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; bool SHLExpMask = IsSHL ; if ( ! Mask ) { if ( Src . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { Mask = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SHLExpMask = !


<s> Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , NameLoc , isRV64 ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT>


<s> for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T


<s> static bool requiresFixups ( MCContext & C , const MCExpr * Value , const MCExpr * & LHS , const MCExpr * & RHS ) { const auto * MBE = dyn_cast < MCBinaryExpr > ( Value ) ; if ( MBE == nullptr ) return false ; MCValue E ; if ( ! Value -> evaluateAsRelocatable ( E , nullptr , nullptr ) ) return false ; if ( E . getSymA ( ) == nullptr || E . getSymB ( ) == nullptr ) return false ; const auto & A = E . getSymA ( ) -> getSymbol ( ) ; const auto & B = E . getSymB ( ) -> getSymbol ( ) ; LHS = MCBinaryExpr :: create ( MCBinaryExpr :: Add , MCSymbolRefExpr :: create ( & A , C ) , MCConstantExpr :: create ( E . getConstant ( ) , C ) , C ) ; RHS = E . getSymB (


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; else { if ( Offset . getFixed ( ) ) { Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addImm ( Offset . getFixed ( ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } } } else { assert ( ScalableFactorRegister && <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> && ! Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return ; } Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , VL ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; if ( IsRVVSpill && Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL ) . addImm ( Offset . getFixed ( ) ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VL , false , false , true ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; } auto ZvlssegInfo = TII -> isRVVSpillForZvlsseg ( MI . getOpcode ( ) ) ; if ( ZvlssegInfo ) { Register VL = MRI . createVirtualRegister ( &


<s> static const char * getName ( ) { return


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . getXLen ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! DCI . isBeforeLegalize ( ) ) break ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || RHS -> getOpcode ( ) == <STR_LIT> || ( RHS -> getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) <= <NUM_LIT> ) ) break ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , RHS , DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ) ) ; return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , LHS . getValueType ( ) , LHS , NewRHS ) ) ; } case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) break ; if ( ! isVariableShift ( Src ) && ! ( Subtarget . hasStdExtM ( ) && isVariableSDivUDivURem ( Src ) ) ) break ; SDLoc DL ( N ) ; return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , DL ,


<s> function_builder :: function_builder ( ) { m_direct_overloads = lang_GNU_CXX ( ) ; gcc_obstack_init ( & m_string_obstack )


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool IsStrict = N -> isStrictFPOpcode ( ) ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDValue Op0 = IsStrict ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case


<s> assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Min = RVVVectorBitsMin ; if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std

:: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( )


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass *


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> >


<s> Inst . addOperand ( MCOperand :: createReg (


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT


<s> case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case ( <STR_LIT> | <STR_LIT> ) : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT>


<s> break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; } } return true


<s> return SECONDARY_MEMORY_NEEDED ( from , to , mode


<s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; return gimple_folder ( rfn . instance , rfn . decl , gsi , stmt ) . fold