<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { MCInst Inst ; SmallVector < MCInst , <NUM_LIT> > Instructions ; unsigned MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( MatchResult ) { case Match_Success : { switch ( Inst . getOpcode ( ) ) { default : Inst . setLoc ( IDLoc ) ; Instructions . push_back


<s> LLT NewTy = LLT :: scalar ( <NUM_LIT> ) ; Register PtrReg = Store . getPointerReg ( ) ; auto Zero = B . buildConstant ( NewTy , <NUM_LIT> ) ; auto HighPtr = B . buildPtrAdd ( MRI . getType ( PtrReg ) , PtrReg , B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) ) ; auto & MF = * MI . getMF ( ) ; auto * LowMMO = MF . getMachineMemOperand ( & Store . getMMO ( ) , <NUM_LIT> , NewTy ) ; auto * HighMMO = MF . getMachineMemOperand ( & Store . getMMO ( ) , <NUM_LIT> , NewTy ) ; B . buildStore ( Zero , PtrReg , *


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; else GVSym = Mang -> getSymbol ( GV ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * GVSym ; else O << '(' << * GVSym << ')' ; printOffset ( MO . getOffset ( ) , O ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const MCSymbol * SymToPrint ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) , true ) ; } SymToPrint = StubSym . getPointer ( ) ; }


<s> CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; } return


<s> assert ( <NUM_LIT> * SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } assert ( SrcVT . getSizeInBits ( ) == <NUM_LIT> * VT . getSizeInBits ( ) ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; unsigned Imm = Src . MinElt * getExtFactor ( VEXTSrc1 ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy ) continue ; assert ( ShuffleVT . getVectorElementType ( ) == SmallestEltTy ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , ShuffleVT , Src . ShuffleVec ) ; Src . WindowScale = SrcEltTy . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; Src . WindowBase *= Src . WindowScale ; } DEBUG ( for ( auto Src : Sources ) assert ( Src . ShuffleVec . getValueType ( ) == ShuffleVT ) ; ) ; SmallVector < int , <NUM_LIT> > Mask ( ShuffleVT . getVectorNumElements ( ) , - <NUM_LIT> ) ; int BitsPerShuffleLane = ShuffleVT . getScalarSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) { SDValue Entry = Op . getOperand (


<s> return __builtin_mve_vorrq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a , __b ,


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT


<s> unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , Madd , Zero ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> void <ISA_LIT>TargetELFStreamer :: finishAttributeSection ( ) { <ISA_LIT>ELFStreamer & S = getStreamer ( ) ; if ( FPU != <STR_LIT> ) emitFPUDefaultAttributes ( ) ; if ( Arch != <STR_LIT> :: INVALID ) emitArchDefaultAttributes ( ) ; if ( S . Contents . empty ( ) ) return ; auto LessTag = [ ] ( const MCELFStreamer :: AttributeItem & LHS , const MCELFStreamer :: AttributeItem & RHS ) -> bool { return ( RHS . Tag != <STR_LIT> ) && ( ( LHS . Tag == <STR_LIT> ) || ( LHS . Tag < RHS . Tag ) ) ; } ; llvm :: sort ( S .


<s> temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hf ( __o , ( float16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hf ( __o , ( float16x8_t ) temp . val


<s> static __inline unsigned long long sh_media_MSHFHI_L ( unsigned long long mm , unsigned long long mn ) { typedef float v2si __attribute__ ( ( mode


<s> unsigned <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Opcode == Instruction :: Store && Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Src -> isVectorTy ( ) && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) && Src -> getVectorNumElements ( ) < <NUM_LIT> ) { unsigned NumVecElts = Src -> getVectorNumElements ( ) ; unsigned NumVectorizableInstsToAmortize = NumVecElts * <NUM_LIT> ; return NumVectorizableInstsToAmortize * NumVecElts * <NUM_LIT> ; } return LT


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperandNo ( & MO ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) !=

MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc DL ( N ) ; Base = Mgs -> getBasePtr ( ) ; Index = Mgs -> getIndex ( ) ; unsigned ScalarSize = Mgs -> getValue ( ) . getScalarValueSizeInBits ( ) ; Scale = getI8Imm ( ScalarSize / <NUM_LIT> , DL ) ; if ( isa < ConstantSDNode > ( Base ) ) { assert ( cast < ConstantSDNode > ( Base ) -> isNullValue ( ) && <STR_LIT> ) ; Scale = getI8Imm ( <NUM_LIT> , DL ) ; Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } if ( AM . Segment . getNode ( ) )


<s> return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ; MBB -> addSuccessor ( JoinMBB ) ; MI -> eraseFromParent ( )


<s> case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) <<


<s> if ( nds32_expand_setmem_unroll ( dstmem , size , value , align , expected_align , expected_size ) ) return true ; return nds32_expand_setmem_loop ( dstmem , size ,


<s> bool runOnMachineFunction ( MachineFunction & F ) override { <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo >


<s> EVT VT = Op . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ,


<s> void addThumbBranchTargetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> void addPrefetchOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getPrefetch


<s> N0 = LowerSDIV_v4i16 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i16 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N0 ) ; return N0 ; } N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N1 , N1 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl ,


<s> EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP -


<s> static DecodeStatus DecodeSimm19Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler *


<s> return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand ::


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! isN64 ( ) ) return


<s> void <ISA_LIT>CodeEmitter :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , TID ) ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; Binary |= <NUM_LIT>


<s> if ( HasLo ) { Lo = CurDAG -> getMachineNode ( <STR_LIT> , dl , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) Hi = CurDAG -> getMachineNode ( <STR_LIT> , dl


<s> if ( EltSize * NumElems != <NUM_LIT> || NumElems < <NUM_LIT> ) return ScalarCost ; if ( Alignment < EltSize / <NUM_LIT> ) return ScalarCost ; if ( EltSize == <NUM_LIT> ) return VectorCost ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return ScalarCost ; if ( auto BC = dyn_cast < BitCastInst > ( Ptr ) ) Ptr = BC -> getOperand ( <NUM_LIT> ) ; if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) return ScalarCost ; unsigned Scale = DL . getTypeAllocSize ( GEP -> getResultElementType ( ) ) ; if ( Scale != <NUM_LIT> && Scale * <NUM_LIT> !=


<s> if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isAClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> ,


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT>


<s> if ( M < <NUM_LIT> ) { assert ( isUndefOrZero ( M ) && <STR_LIT> ) ; if ( SM_SentinelUndef == M ) KnownUndef . setBit ( i ) ; if ( SM_SentinelZero == M ) KnownZero . setBit ( i ) ; continue ; } unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { KnownUndef . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( ) ) KnownUndef . setBit ( i ) ; else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) ) ) KnownZero . setBit ( i ) ; continue ; } if ( IsSrcConstant [ SrcIdx ] ) { if ( UndefSrcElts [ SrcIdx ] [ M ] ) KnownUndef . setBit ( i ) ; else if ( SrcEltBits [ SrcIdx ] [ M ] == <NUM_LIT> ) KnownZero . setBit ( i ) ; } } assert ( VT . getVectorNumElements ( ) == ( unsigned ) Size && <STR_LIT> ) ; return true


<s> return __builtin_aarch64_lfloorudfdi_us (


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rn |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder


<s> unsigned MaxAlign = MFI . getMaxAlignment ( ) ; bool HasRedZone = Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) ; return ( IsLargeFrame || ! HasRedZone )


<s> else { emit_insn ( gen_safe_SET64 ( temp , high_bits ) ) ; temp2 = temp ; } emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , temp2 , GEN_INT ( shift_count ) ) ) ) ; if ( low_immediate != <NUM_LIT> ) emit_insn ( gen_rtx_SET ( op0 , gen_safe_OR64 (


<s> rtx cmp_op0 , cmp_op1 ; int is_sse = SSE_REG_P ( operands [ <NUM_LIT> ] ) || SSE_REG_P ( operands [ <NUM_LIT> ] ) ; if ( eflags_p ) { cmp_op0 = operands [ <NUM_LIT> ] ; cmp_op1 = operands [ <NUM_LIT> ] ; } else { cmp_op0 = operands [ <NUM_LIT> ] ; cmp_op1 = operands [ <NUM_LIT> ] ; } if ( is_sse ) { if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) if ( unordered_p ) return <STR_LIT> ; else return <STR_LIT> ; else if ( unordered_p ) return <STR_LIT> ; else return <STR_LIT> ; } gcc_assert ( STACK_TOP_P ( cmp_op0 ) ) ; stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) != <NUM_LIT> ; if ( cmp_op1 == CONST0_RTX ( GET_MODE ( cmp_op1 )


<s> if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT>


<s> static bool aarch64_macro_fusion_p (


<s> StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ArchFeatureName . empty ( ) ) return reportParseError ( <STR_LIT> ) ; selectArch ( ArchFeatureName


<s> static void vax_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += ( arg . promoted_size_in_bytes ( ) + <NUM_LIT> )


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedStore (


<s> std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { if ( isNullConstant ( TVal . getOperand ( <NUM_LIT> ) ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } } else if ( CTVal && CFVal ) { const int64_t TrueVal = CTVal -> getSExtValue ( ) ; const int64_t FalseVal = CFVal -> getSExtValue ( ) ; bool Swap = false ; if ( TrueVal == ~ FalseVal ) { Opcode = <STR_LIT> ; } else if ( TrueVal == - FalseVal ) { Opcode = <STR_LIT> ; } else if ( TVal . getValueType ( ) == <STR_LIT> ) { const uint32_t TrueVal32 = CTVal -> getZExtValue ( ) ; const uint32_t FalseVal32 = CFVal -> getZExtValue ( ) ; if ( ( TrueVal32 == FalseVal32 + <NUM_LIT> ) || ( TrueVal32 + <NUM_LIT> == FalseVal32 ) ) { Opcode = <STR_LIT> ; if ( TrueVal32 > FalseVal32 ) { Swap = true ; } } } else if ( ( TrueVal == FalseVal + <NUM_LIT> ) || ( TrueVal + <NUM_LIT> == FalseVal ) ) { Opcode = <STR_LIT> ; if ( TrueVal > FalseVal ) { Swap = true ; } } if ( Swap ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } if ( Opcode != <STR_LIT> ) { FVal = TVal ; } } ConstantSDNode * RHSVal = dyn_cast < ConstantSDNode > ( RHS ) ; if ( Opcode == <STR_LIT> && RHSVal && ! RHSVal -> isOne ( ) && ! RHSVal -> isNullValue ( ) && ! RHSVal -> isAllOnesValue ( ) ) { <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; if ( CTVal && CTVal == RHSVal && <ISA_LIT>CC == <STR_LIT> ) TVal = LHS ; else if ( CFVal && CFVal == RHSVal && <ISA_LIT>CC == <STR_LIT> ) FVal = LHS ; } else if ( Opcode == <STR_LIT> && RHSVal && RHSVal -> isOne ( ) ) { assert ( CTVal && CFVal && <STR_LIT> ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; if ( CTVal == RHSVal && <ISA_LIT>CC == <STR_LIT> ) { Opcode = <STR_LIT> ; TVal = LHS ; FVal = DAG . getConstant ( <NUM_LIT> , dl , FVal . getValueType ( ) ) ; } } SDValue CCVal


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>1 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex


<s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get (


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo


<s> SDValue Offset = Op -> getOperand ( <NUM_LIT> ) ; EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy


<s> static struct machine_function * moxie_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <NUM_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( isImm ) MI . addOperand ( MCOperand :: CreateImm ( simm13


<s> int _U_Qfgt ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_GT


<s> FunctionPass * llvm :: create<ISA_LIT>CodeEmitterPass ( <ISA_LIT>TargetMachine & TM , MachineCodeEmitter & MCE ) { return new Emitter < MachineCodeEmitter > (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned


<s> uint16x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( create<ISA_LIT>PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) addPass ( createGlobalMergePass ( TM , <NUM_LIT> ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>AddressTypePromotionPass


<s> static DecodeStatus decodeDirectBrTarget ( MCInst & Inst , unsigned Imm , uint64_t ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign (


<s> } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; recordSled ( CurSled , MI , SledKind


<s> static __inline qword si_shl ( qword a , qword b ) { vec_uint4 mask ; mask = ( vec_uint4 ) vec_sra ( vec_sl ( ( vec_uint4 ) ( b ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_andc ( vec_sl ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ,


<s> void <ISA_LIT>CodeEmitter :: emitLoadStoreMultipleInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; bool IsUpdating = ( MCID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MCID . getOpcode ( ) == <STR_LIT> ) { IsUpdating = true ; Binary |= <NUM_LIT> ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; <STR_LIT> Mode = <STR_LIT> ( MI . getOpcode ( ) ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( Mode ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg (


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo (


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) val


<s> pcmpeqh_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_pcmpeqh_s ( s , t


<s> Register <ISA_LIT>FunctionInfo :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg


<s> if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , reg_class_names [ ( int )


<s> unsigned getNEONVcvtImm32OpValue ( const MachineInstr & MI , unsigned Op ) const { return


<s> static inline uint8_t encodeAdvSIMDModImmType5 ( uint64_t Imm ) { return ( Imm


<s> T UImm = static_cast < T > ( Imm ) ; if ( <STR_LIT> ( UImm , RegSize ) ) return false ; SmallVector < <ISA_LIT>_IMM :: ImmInsnModel , <NUM_LIT> > Insn ; <ISA_LIT>_IMM :: expandMOVImm ( UImm , RegSize , Insn ) ; if ( Insn . size ( ) == <NUM_LIT> ) return false ; unsigned LowestBitSet = countTrailingZeros ( UImm ) ; unsigned HighestBitSet = Log2_64 ( UImm ) ; T NewImm1 = ( static_cast < T > ( <NUM_LIT> ) << HighestBitSet ) - ( static_cast < T > ( <NUM_LIT> ) << LowestBitSet ) ; T NewImm2 = UImm | ~ NewImm1 ; if ( ! <STR_LIT> ( NewImm2 , RegSize ) ) return false ; Imm1Enc = <STR_LIT> ( NewImm1 , RegSize ) ; Imm2Enc = <STR_LIT> ( NewImm2 , RegSize ) ; return true


<s> void mips_output_external ( FILE * file , tree decl , const char * name ) { default_elf_asm_output_external ( file , decl , name ) ; if ( TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { if ( ! TARGET_EXPLICIT_RELOCS && mips_in_small_data_p ( decl ) ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name


<s> assert ( m_pGOTPLT != NULL ) ; return *


<s> if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; for ( tree list = SH_ATTRIBUTES ( func ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( <STR_LIT> , get_attribute_name ( list ) ) ) return true ; return false


<s> MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV ->


<s> virtual const char * getPassName ( ) const { return


<s> static Target The<ISA_LIT>beTarget ; return


<s> bool <ISA_LIT>AsmParser :: processInstruction ( MCInst & Inst , const OperandVector & Ops ) { return false


<s> int <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src


<s> FunctionPass * llvm :: create<ISA_LIT>ProtectJTSupport (


<s> else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg ,


<s> if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( ( Op0 . getValueType ( ) == <STR_LIT> && ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget . isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ?


<s> emit_move_insn ( tmpreg , retreg ) ; insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , tmpreg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , retreg ) ) ; offset -= <NUM_LIT> ; } else if ( MMIX_CFUN_HAS_LANDING_PAD ) offset -= <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) { if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; total_allocated_stack_space += stack_chunk ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } emit_move_insn ( gen_rtx_REG ( DImode , <NUM_LIT> ) , gen_rtx_REG ( DImode , MMIX_rO_REGNUM ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , gen_rtx_REG ( DImode , <NUM_LIT> ) ) ; offset -= <NUM_LIT> ; } offset -= ( locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = ( stack_space_to_allocate > ( <NUM_LIT> - offset - <NUM_LIT> ) ? ( <NUM_LIT> - offset - <NUM_LIT> ) : stack_space_to_allocate ) ; mmix_emit_sp_add ( - stack_chunk ) ; total_allocated_stack_space += stack_chunk ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , gen_rtx_REG


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } assert ( checkAllSuperRegsMarked ( Reserved , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses (


<s> if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , OffReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , OffReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , TII -> get ( NewOpc ) ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( OffReg ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , TII -> get ( NewOpc ) ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( OffReg ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg ,


<s> for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex (


<s> unsigned TZ = countTrailingZeros ( ITState . Mask ) ; unsigned NewMask = <NUM_LIT> ; NewMask |= ITState . Mask & ( <NUM_LIT> << TZ ) ; NewMask |= ( Cond != ITState . Cond ) << TZ ; NewMask |= <NUM_LIT> << ( TZ - <NUM_LIT> ) ; ITState . Mask


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC =


<s> BaseTAI :: ConstantPoolSection = <STR_LIT> ; BaseTAI :: COMMDirectiveTakesAlignment = false ; BaseTAI :: InlineAsmStart = <STR_LIT> ; BaseTAI :: InlineAsmEnd = <STR_LIT> ; BaseTAI :: LCOMMDirective =


<s> return __builtin_aarch64_uqaddv16qi_uuu ( __a ,


<s> tree arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; tree permute_type ; permute_type = map_to_integral_tree_type ( lhs_type ) ; tree_vector_builder elts ( permute_type , VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < n_elts / <NUM_LIT> ; i ++ ) { elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , <NUM_LIT> * i + use_odd ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , <NUM_LIT>


<s> void collectValueRotInfo ( ) { ValueRots . clear ( ) ; for ( auto & BG : BitGroups ) { unsigned RLAmtKey = BG . RLAmt + ( BG . Repl32 ? <NUM_LIT> : <NUM_LIT> ) ; ValueRotInfo & VRI = ValueRots [ std :: make_pair ( BG . V , RLAmtKey ) ] ; VRI . V = BG . V ; VRI . RLAmt = BG . RLAmt ; VRI . Repl32 = BG .


<s> if ( std :: count ( AsmPieces . begin ( ) , AsmPieces . end ( ) , <STR_LIT> ) && std :: count ( AsmPieces . begin ( ) , AsmPieces . end ( ) , <STR_LIT> ) && std :: count ( AsmPieces . begin ( ) , AsmPieces . end ( ) , <STR_LIT> ) ) { if ( AsmPieces . size ( ) == <NUM_LIT> ) return true ; else if ( std :: count ( AsmPieces . begin ( ) , AsmPieces . end ( ) , <STR_LIT>


<s> enum rtx_code code = GET_CODE ( op ) ; if ( code != PLUS && code != SMIN && code != SMAX ) return false ; rtx concat = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( concat ) != VEC_CONCAT ) return false ; rtx select0 = XEXP ( concat , <NUM_LIT> ) ; rtx select1 = XEXP ( concat , <NUM_LIT> ) ; if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1


<s> iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( GET_MODE ( reg ) , dwarf_mem ,


<s> return ( __m128i ) __builtin_ia32_vpdpbuuds128 ( ( __v4si ) __W ,


<s> static poly_int64 ix86_return_pops_args ( tree fundecl , tree funtype , poly_int64 size ) { unsigned int ccvt ; if ( TARGET_64BIT ) return <NUM_LIT> ; ccvt = ix86_get_callcvt ( funtype ) ; if ( ( ccvt & ( IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) != <NUM_LIT> && ! stdarg_p ( funtype ) ) return size ; if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! ix86_keep_aggregate_return_pointer ( funtype ) ) { int nregs = ix86_function_regparm ( funtype , fundecl ) ; if ( nregs == <NUM_LIT> ) return GET_MODE_SIZE ( Pmode ) ; } return


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> bool <ISA_LIT>CodeGenPrepare :: isSupportedValue ( Value * V ) { if ( auto * I = dyn_cast < ICmpInst > ( V ) ) { if ( isa < PointerType > ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return true ; return EqualTypeSize ( I -> getOperand ( <NUM_LIT> ) ) ; } if ( isa < StoreInst > ( V ) || isa < GetElementPtrInst > ( V ) ) return true ; if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( ( isa < Constant > ( V ) && ! isa < ConstantExpr > ( V ) ) || isa < Argument > ( V ) ) return isSupportedType ( V ) ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( isa < SExtInst > ( V ) ) return false ; if ( auto * Cast = dyn_cast < CastInst > ( V ) ) return isSupportedType ( Cast ) || isSupportedType ( Cast -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) return false ; if ( ! isSupportedType ( V ) ) return false ; if ( generateSignBits ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true


<s> s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_aligned_integer ( INIT_ARRAY_ENTRY_BYTES ,


<s> MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 , CC ) , DAG . getNode ( Op .

getOpcode ( ) , dl , NewVT , LHS2 , RHS2 , CC ) ) ;


<s> float64_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> static unsigned AddLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { assert ( RC -> contains ( PReg


<s> } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , Imm ) && ( ! EncodingAlignment || isAligned ( * EncodingAlignment , Imm ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) ==


<s> bool <ISA_LIT>MCCodeEmitter :: isREXExtendedReg ( const MCInst & MI , unsigned OpNum ) const { return ( get<ISA_LIT>RegEncoding ( MI , OpNum ) >> <NUM_LIT>


<s> if ( flag_check_pointer_bounds ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; return VOIDmode ; } return BNDmode


<s> } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } if ( Subtarget . isPICStyleGOT ( ) || Subtarget . isPICStyleStubPIC ( ) ) return ; GlobalAddressSDNode * GA = nullptr ; int64_t Offset = <NUM_LIT> ; while ( <NUM_LIT> ) { if ( ( GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) ) { Offset += GA -> getOffset ( ) ; break ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += - C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ; } } return ; } const GlobalValue * GV = GA -> getGlobal ( ) ; if ( isGlobalStubReference ( Subtarget . ClassifyGlobalReference ( GV , DAG . getTarget ( ) ) ) ) return ; Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , GA -> getValueType ( <NUM_LIT> ) , Offset ) ; break ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result


<s> return DAG . getNode ( <STR_LIT> , DL , PtrVT , GotAddr ) ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ,

DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ;


<s> MCSymbol * <ISA_LIT>AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { const DataLayout & DL =


<s> } else cfun -> machine -> no_drap_save_restore = true ; frame_pointer_needed = false ; stack_realign = false ; crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> stack_alignment_estimated = incoming_stack_boundary ; if ( crtl -> preferred_stack_boundary > incoming_stack_boundary ) crtl -> preferred_stack_boundary = incoming_stack_boundary ; df_finish_pass ( true ) ; df_scan_alloc ( NULL ) ; df_scan_blocks ( ) ; df_compute_regs_ever_live ( true ) ; df_analyze ( ) ; if ( flag_var_tracking ) { df_ref ref , next ; for ( ref = DF_REG_USE_CHAIN ( HARD_FRAME_POINTER_REGNUM ) ; ref ; ref = next ) { next = DF_REF_NEXT_REG ( ref ) ; if ( ! DF_REF_INSN_INFO ( ref ) ) continue ; rtx_insn * insn = DF_REF_INSN ( ref ) ; while ( next && DF_REF_INSN ( next ) == insn ) next = DF_REF_NEXT_REG ( next ) ; if ( DEBUG_INSN_P ( insn ) ) { bool changed = false ; for ( ; ref != next ; ref = DF_REF_NEXT_REG (


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return ( ( <NUM_LIT> - MO . getImm ( ) ) & <NUM_LIT> ) | ( <NUM_LIT> - MO


<s> return false ; } getTargetStreamer ( ) . emitInst ( Value -> getValue ( ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; } Parser . Lex ( ) ; return


<s> if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; unsigned prfop = <STR_LIT> ( ) . fromString ( Tok . getString ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>64 ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>64 (


<s> if ( TREE_PUBLIC ( default_decl ) == <NUM_LIT> ) { char * ifunc_name = make_unique_name ( default_decl , <STR_LIT> , true ) ; symtab -> change_decl_assembler_name ( ifunc_alias_decl , get_identifier ( ifunc_name ) ) ; XDELETEVEC ( ifunc_name ) ; } resolver_name = make_unique_name ( default_decl , <STR_LIT> , false ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = <NUM_LIT> ; DECL_ARTIFICIAL ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; DECL_UNINLINABLE ( decl ) = <NUM_LIT> ; DECL_EXTERNAL ( decl ) = <NUM_LIT> ; DECL_EXTERNAL ( ifunc_alias_decl ) = <NUM_LIT> ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( <STR_LIT> , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; XDELETEVEC ( resolver_name ) ; return decl


<s> inline static unsigned encode<ISA_LIT>AluCode ( unsigned AluOp ) { unsigned const OP_ENCODING_MASK = <NUM_LIT> ; return AluOp


<s> if ( ( STI . isDarwinABI ( ) || STI . isAIXABI ( ) ) || STI . is<ISA_LIT>64 ( ) ) return ( STI . isELFv2ABI

( ) ? <NUM_LIT> : <NUM_LIT> ) * ( STI . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> const MILOHContainer & getLOHContainer (


<s> unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return


<s> StringRef Name = Tok . getString ( ) ; if ( Name . equals_insensitive ( <STR_LIT> ) ) { Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMatrixRegister ( <STR_LIT> , <NUM_LIT> , MatrixKind :: Array , S , getLoc ( ) , getContext ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseOperand ( Operands , false , false ) ) return MatchOperand_NoMatch ; } return MatchOperand_Success ; } unsigned Reg = matchRegisterNameAlias ( Name , RegKind :: Matrix ) ; if ( ! Reg ) return MatchOperand_NoMatch ; size_t DotPosition = Name . find ( '.' ) ; assert ( DotPosition != StringRef :: npos && <STR_LIT> ) ; StringRef Head = Name . take_front ( DotPosition ) ; StringRef Tail = Name . drop_front ( DotPosition ) ; StringRef RowOrColumn = Head . take_back ( ) ; MatrixKind Kind = StringSwitch < MatrixKind > ( RowOrColumn ) . Case ( <STR_LIT> , MatrixKind :: Row ) . Case ( <STR_LIT> , MatrixKind :: Col ) . Default ( MatrixKind :: Tile ) ; const auto & KindRes = parseVectorKind ( Tail , RegKind :: Matrix ) ; if ( ! KindRes ) { TokError ( <STR_LIT>


<s> HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasMMA = false ; HasROPProtect = false ; HasPrivileged = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasQuadwordAtomics = false ; HasDirectMove = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasStoreFusion = false ; HasAddiLoadFusion = false ; HasAddisLoadFusion = false ; HasArithAddFusion = false ; HasAddLogicalFusion = false ; HasLogicalAddFusion = false ; HasLogicalFusion = false ; HasSha3Fusion = false ; HasCompareFusion = false ; HasWideImmFusion = false ; HasZeroMoveFusion = false ; IsISA2_06 = false ; IsISA2_07 = false ; IsISA3_0 = false ; IsISA3_1 = false ; UseLongCalls = false ; SecurePlt = false ; VectorsUseTwoUnits = false


<s> MCInst <ISA_LIT>InstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode


<s> MachineInstr & MI = * MBBI ; int AddrIdx ; if ( IsDangerousLoad ( MI , & AddrIdx ) ) { SandboxLoadStore ( MBB , MBBI , MI , AddrIdx ) ; Modified = true ; } } return


<s> vld1q_s32 ( const int32_t * a ) { return __builtin_aarch64_ld1v4si ( ( const __builtin_aarch64_simd_si *


<s> return __builtin_aarch64_smax_nanpv4sf ( a , b


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != & MI ) || ! hasFallthrough ( * MBB ) ; if ( BMI != & MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> isUnconditionalBranch ( ) ) { MachineBasicBlock * NewDest = getDestBlock ( * BMI ) ; if ( isBlockInRange ( MI , * NewDest ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; changeBranchDestBlock ( * BMI , * DestBB ) ; int NewSize = insertInvertedConditionalBranch ( * MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , MI , * NewDest ) ; int OldSize = TII -> getInstSizeInBytes ( MI ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += ( NewSize - OldSize ) ; MI . eraseFromParent ( ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool Fail = TII -> analyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; assert ( ! Fail && <STR_LIT> ) ; ( void ) Fail ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock & NextBB = * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB . getNumber ( ) << '\n' ) ; unsigned & MBBSize = BlockInfo [ MBB -> getNumber ( ) ] . Size ; MBBSize += insertInvertedConditionalBranch ( * MBB , MBB -> end ( ) , MI . getDebugLoc ( ) , MI , NextBB ) ; MBBSize += insertUnconditionalBranch ( * MBB , * DestBB , MI . getDebugLoc ( ) ) ; MBBSize -= TII -> getInstSizeInBytes ( MI ) ; MI . eraseFromParent ( ) ; adjustBlockOffsets ( * MBB ) ; return true


<s> bool V2IsZero = ! V2IsUndef && <STR_LIT> ( V2 . getNode ( ) ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( OrigMask , Zeroable , V2IsZero , WidenedMask ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , OrigMask , Subtarget , DAG ) ) return Broadcast ; MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( is_contained ( WidenedMask , SM_SentinelZero ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } SmallVector < SDValue > Ops = { V1 , V2 } ; SmallVector < int > Mask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; if ( SDValue HOp = canonicalizeShuffleMaskWithHorizOp ( Ops , Mask , VT . getSizeInBits ( ) , DL , DAG , Subtarget ) ) return DAG . getBitcast ( VT , HOp ) ; V1 = DAG . getBitcast ( VT , Ops [ <NUM_LIT> ] ) ; V2 = DAG . getBitcast ( VT , Ops [ <NUM_LIT> ] ) ; assert ( NumElements == ( int ) Mask . size ( ) && <STR_LIT> <STR_LIT>


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT>


<s> assert ( MRI . getType ( Ptr ) . isPointer ( ) && <STR_LIT> ) ; auto Load = MIB . buildInstr ( Opc , { Ty } , { Ptr } ) ; Load . cloneMemRefs ( I ) ; constrainSelectedInstRegOperands ( * Load , TII , TRI , RBI ) ; Register SelectedLoadDst = Load -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumVecs ; ++ Idx ) { auto Vec = MIB . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( Idx ) } , { } ) . addReg ( SelectedLoadDst , <NUM_LIT> , SubReg + Idx ) ; selectCopy ( * Vec , TII , MRI


( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShufMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In


<s> if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = VT . getSimpleVT ( ) ; MVT ShufSVT = ShufVT . getVectorElementType ( ) ; int NumElems = ( int ) ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; bool IsUnary ; if ( ! getTargetShuffleMask ( Op . getNode ( ) , ShufVT , true , ShuffleOps , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt == SM_SentinelZero ) return ShufSVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , ShufSVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( Op ) , ShufSVT ) ; if ( Elt == SM_SentinelUndef ) return DAG . getUNDEF ( ShufSVT ) ; assert ( <NUM_LIT> <= Elt && Elt < ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue Src = ( Elt < NumElems ) ? ShuffleOps [ <NUM_LIT> ] : ShuffleOps [ <NUM_LIT> ] ; return getShuffleScalarElt ( Src , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Sub = Op . getOperand ( <NUM_LIT> ) ; uint64_t SubIdx = Op . getConstantOperandVal ( <NUM_LIT> ) ; unsigned NumSubElts = Sub . getValueType ( ) . getVectorNumElements ( ) ; if ( SubIdx <= Index && Index < ( SubIdx + NumSubElts ) ) return getShuffleScalarElt ( Sub , Index - SubIdx , DAG , Depth + <NUM_LIT> ) ; return getShuffleScalarElt ( Vec , Index , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { EVT SubVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned NumSubElts = SubVT . getVectorNumElements ( ) ; uint64_t SubIdx = Index / NumSubElts ; uint64_t SubElt = Index % NumSubElts ; return getShuffleScalarElt ( Op . getOperand ( SubIdx ) , SubElt , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; uint64_t SrcIdx = Op . getConstantOperandVal ( <NUM_LIT> ) ; return getShuffleScalarElt ( Src , Index + SrcIdx , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src


<s> return uint8_t ( Imm ) == Imm || ( ! IsInt8t

&& uint16_t ( Imm & ~ <NUM_LIT> ) == Imm ) ;


<s> Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) <<


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ; if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo


<s> switch ( Letter ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'I' : if ( isInt < <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'J' : if ( isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'L' : if ( isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'K' : if ( isUInt < <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'M' : if ( Value > <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'N' : if ( Value > <NUM_LIT> && isPowerOf2_64 ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'O' : if ( Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'P' : if ( isInt < <NUM_LIT> > ( - Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; } break ; } } if ( Result . getNode


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { assert ( LdSt . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { if ( ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; } else if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; } else return false ; unsigned Scale = <NUM_LIT> ; int64_t Dummy1 , Dummy2 ; if ( ! getMemOpInfo ( LdSt . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ) return false ; if ( LdSt . getNumExplicitOperands (


<s> bool isTypedVectorList ( ) const { if ( Kind != k_VectorList ) return false ; if ( VectorList . Count != NumRegs ) return false ; if ( VectorList . ElementKind != ElementKind ) return false ; return VectorList . NumElements ==


<s> SMLoc S ; bool Result = true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) Parser . Lex ( ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return true ; case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken ::


<s> SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) , Subtarget ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , Op . getNode ( ) , InChain ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first


<s> if ( ! Failed && Index < <NUM_LIT> && Map [ Index ] ) return std :: make_pair ( Map [ Index ] , RC ) ; } return std :: make_pair ( <NUM_LIT> ,


<s> cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & <NUM_LIT> ) && arg . type

!= NULL_TREE && arg_size > <NUM_LIT> ) ) ;


<s> else emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ; } for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; if ( layout . stdarg_save_size ) emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout .


<s> else { APPEND_STRING ( loongarch_abi_base_strings [ abi . base ] ) APPEND1 ( '/' ) APPEND_STRING ( loongarch_abi_ext_strings [ abi . ext ] ) APPEND1 ( '\0' ) return XOBFINISH (


<s> bool nds32_can_use_bitci_p ( HOST_WIDE_INT ival ) { return ( TARGET_ISA_V3 && ( ival < <NUM_LIT> ) && satisfies_constraint_Iu15 ( gen_int_mode ( ~ ival


<s> } else if ( TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; } else if ( VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_vector_value ( size , <NUM_LIT> , true , SPARC_FP_ARG_FIRST ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . else_blk ( ) ; if ( mode == BLKmode ) return function_arg_union_value ( size ,


<s> EmitMappingSymbol ( <STR_LIT> ) ; LastEMSInfo -> State =


<s> case Instruction :: Sub : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; Type * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits (


<s> case OPT_m3dnow : if ( ! value ) { target_flags &= ~ MASK_3DNOW_A ; target_flags_explicit |= MASK_3DNOW_A ; } return true ; case OPT_mmmx : if ( ! value ) { target_flags &= ~ ( MASK_3DNOW | MASK_3DNOW_A ) ; target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A ; } return true ; case OPT_msse : if ( ! value ) { target_flags &= ~ ( MASK_SSE2 | MASK_SSE3


<s> assert ( Kind == KindTy :: Token && <STR_LIT> ) ; return


<s> static unsigned computeLinkageSize ( const <ISA_LIT>Subtarget & STI ) { if ( STI . isAIXABI ( ) || STI . is<ISA_LIT>64 ( ) ) return ( STI . isELFv2ABI ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( STI . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> os << <STR_LIT> << <STR_LIT> ; os << '|' ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; -- i ) { if ( insn >> ( i - <NUM_LIT> ) & <NUM_LIT> ) os << <STR_LIT> ; else os << <STR_LIT> ; os << ( i % <NUM_LIT> == <NUM_LIT>


<s> } if ( global_options_set . x_rs6000_tune_index ) { fprintf ( file , <STR_LIT> , start , processor_target_table [ rs6000_tune_index ] . name ) ; start = <STR_LIT> ; } if ( PPC405_ERRATUM77 ) { fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; } switch ( rs6000_sdata ) { case SDATA_NONE : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_DATA : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n' , file ) ; } if ( ! ( rs6000_default_cpu && rs6000_default_cpu [ <NUM_LIT> ] ) && ! global_options_set . x_rs6000_cpu_index ) { fputs ( <STR_LIT> , asm_out_file ) ; if ( ( rs6000_isa_flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) fputs ( <STR_LIT>


<s> const MCExpr * getMemShiftAmount ( ) const { assert ( Mem . OffsetIsReg && Mem . OffsetRegShifted


<s> static __inline qword si_roti ( qword a , int b ) { return ( ( qword ) ( vec_rl ( ( vec_uint4 ) ( a ) , vec_splat ( ( vec_uint4 ) ( si_from_int ( b ) ) , <NUM_LIT> )


<s> void printHex64ImmOperand ( const MachineInstr * MI , int OpNum ) { O << <STR_LIT> << utohexstr ( MI -> getOperand ( OpNum ) . getImm


<s> rtx op0 = operands [ <NUM_LIT> ] , op1 = operands


<s> SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , A , ShAmt ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , B , ShAmt ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ; Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT , Bhi ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , AloBhi , ShAmt ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , AhiBlo , ShAmt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned Index , StringRef Str , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser , unsigned RealRegister = <STR_LIT> ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index =


<s> return ( ( __m128d ) vec_ld ( <NUM_LIT> , ( __v16qu *


<s> } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops )


<s> case VK_<ISA_LIT>_None : case VK_<ISA_LIT>_REFLONG : return false ; case VK_<ISA_LIT>_HI32 : case VK_<ISA_LIT>_LO32 : case VK_<ISA_LIT>_PC_HI32 : case VK_<ISA_LIT>_PC_LO32 : case VK_<ISA_LIT>_GOT_HI32 : case VK_<ISA_LIT>_GOT_LO32 : case VK_<ISA_LIT>_GOTOFF_HI32 : case VK_<ISA_LIT>_GOTOFF_LO32 : case VK_<ISA_LIT>_PLT_HI32 : case VK_<ISA_LIT>_PLT_LO32 : case VK_<ISA_LIT>_TLS_GD_HI32 : case VK_<ISA_LIT>_TLS_GD_LO32 : case VK_<ISA_LIT>_TPOFF_HI32 : case VK_<ISA_LIT>_TPOFF_LO32 : return


<s> if ( ! REG_P ( reg ) || insn == NULL ) return result ; for ( result . insn = insn ; result . insn != NULL ; result . insn = prev_nonnote_nondebug_insn_bb ( result . insn ) ) { if ( BARRIER_P ( result . insn ) ) return result ; if ( ! NONJUMP_INSN_P ( result . insn ) )


<s> SelectCode ( Upper . getNode ( ) ) ; Upper = Handle . getValue ( ) ; } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . isCortexA15 ( ) && get<ISA_LIT>Subtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( )


<s> else { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1


<s> if ( MatchAddress ( Addr , AM , false ) ) return false ; EVT VT = Addr . getValueType ( ) ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <STR_LIT> ) if ( AM . Base . Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <STR_LIT> ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity += <NUM_LIT> ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Disp && ( AM . Base . Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity += <NUM_LIT> ; if ( Complexity > <NUM_LIT> ) { getAddressOperands ( AM , Base , Disp , Index ) ; return true ; } return


<s> } else { BuildMI ( SplitEdgeBB , SplitEdgeBB . begin ( ) , DL , TII -> get ( <STR_LIT> ) ) . addDef ( MisspeculatingTaintReg ) . addUse ( MisspeculatingTaintReg )

. addUse ( <STR_LIT> ) . addImm ( CondCode ) ;


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrSubuOp


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn


<s> if ( ! tryAddingSymbolicOperand ( Insn + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: createImm ( Insn ) ) ; return MCDisassembler :: Success


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == <NUM_LIT> ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr


<s> return ( __m128 ) __builtin_ia32_mulss ( ( __v4sf ) __A ,


<s> if ( ID == & TargetTransformInfo :: ID

) return ( TargetTransformInfo * ) this ;


<s> return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresDifferentSrcAndDst : return Error ( IDLoc , <STR_LIT> ) ; case Match_Immz : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm1_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm3_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm4_0 : return Error ( RefineErrorLoc ( IDLoc , Operands ,


<s> if ( ! CE ) return false ; return CE -> getValue ( ) ==


<s> putc ( '\n' , file ) ; } fputs ( <STR_LIT> , file ) ; assemble_name ( file , buffer ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; ASM_OUTPUT_LABEL ( file , buffer ) ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; in_section = NULL ; switch_to_section ( function_section ( decl ) ) ; putc ( '.' , file ) ; ASM_OUTPUT_LABEL ( file , buffer ) ; data . function_descriptor = true ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data


<s> MIRBuilder . setInstr ( MI ) ; MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo (

) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ;


<s> static rtx push ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & <NUM_LIT> ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode ,


<s> <STR_LIT> CC = <STR_LIT> ( MIItBegin -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg (


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool isSVE = MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ; return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed ,

isSVE , FrameReg , PreferFP , ForSimm ) ;


<s> void Thumb1InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create ( <ISA_LIT>Subtarget & STI ) { if ( STI . in<ISA_LIT>16Mode ( ) ) return create<ISA_LIT>16InstrInfo ( STI ) ; return create<ISA_LIT>SEInstrInfo ( STI )


<s> else return <STR_LIT> ; } } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; return pa_output_lbranch ( operands [ <NUM_LIT> ] ,


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'c' : return C_RegisterClass


<s> } SDValue Load = DAG . getLoad ( MemVT , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getMemOperand ( ) ) ; assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( ExtOpcode , dl , Op . getValueType ( ) , Load ) ; } if ( NumElts <= <NUM_LIT> ) { unsigned NumBitsToLoad = <NUM_LIT> ; MVT TypeToLoad = <STR_LIT> ( NumBitsToLoad ) ; SDValue Load = DAG . getLoad ( TypeToLoad , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getMemOperand ( ) ) ; assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumBitsToLoad ) ; SDValue BitVec = DAG . getBitcast ( MaskVT , Load ) ; if ( NumElts == <NUM_LIT> ) return DAG . getNode ( ExtOpcode , dl , VT , BitVec ) ; MVT ExtVT = <STR_LIT> ( VT . getScalarType ( ) , <NUM_LIT> ) ; SDValue ExtVec = DAG . getNode ( ExtOpcode , dl , ExtVT , BitVec ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT>


<s> auto * RHSN1 = dyn_cast < ConstantSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! LHSN1 || LHSN1 != RHSN1 || ! RHSN1 -> isZero ( ) ) return SDValue ( ) ; SDValue Op1 = LHS -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = RHS -> getOperand ( <NUM_LIT> ) ; EVT OpVT1 = Op1 . getValueType ( ) ; EVT OpVT2 = Op2 . getValueType ( ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || OpVT1 != OpVT2 || Op2 . getOpcode ( )

!= <STR_LIT> || OpVT1 . getVectorElementType ( ) != VT ) return SDValue ( ) ;


<s> ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( ! LogicalShift && <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( - <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == N0 . getOpcode ( ) ) { unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NewShiftVal = ShiftVal + ShiftVal2 ; if ( NewShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; NewShiftVal = NumBitsPerElt - <NUM_LIT> ; } return DAG . getNode ( Opcode , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) { addExpr ( Inst , getImm ( )


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> if ( ! TARGET_64BIT ) return false ; return default_is_empty_record (


- ( args_so_farp -> regs + <NUM_LIT> ) ) * <NUM_LIT> ;


<s> bool <ISA_LIT>16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! Subtarget . in<ISA_LIT>16Mode ( ) )


<s> uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Size = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Size = <NUM_LIT> ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue


<s> int EdgeVal = ( * E . getCurrent ( ) ) . getValue


<s> static DecodeStatus DecodeCallTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ; return MCDisassembler :: Success


<s> break ; } case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) | ( 'U' << <NUM_LIT> ) ) ; break ; } I . eraseFromParent ( ) ; return true


<s> else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; else { rtx sum = XEXP ( op ,


<s> unsigned getMAIAssemblerDialect ( ) { return Parser . getContext ( ) . getAsmInfo ( )


<s> static inline bool isT2SOImmTwoPartVal ( unsigned Imm ) { unsigned V = Imm ; if ( getT2SOImmValSplatVal ( V ) != - <NUM_LIT> ) return false ; V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( V ) ) & V ; if ( V == <NUM_LIT> ) return false ; if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return true ; V = Imm ; if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; else if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) !=


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> ,

<STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer -> EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: create ( PICBase , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> EmitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT> ) ; } return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } MCSectionSubPair Current = OutStreamer -> getCurrentSection


<s> dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; } )


<s> return ( REG_P ( exp ) && VALID_AVX256_REG_OR_OI_MODE ( GET_MODE (


<s> const Value * SV = I -> getOperand ( <NUM_LIT> ) ; if ( TLI . supportSwiftError ( ) ) { if ( const Argument * Arg = dyn_cast < Argument > ( SV ) ) { if ( Arg -> hasSwiftErrorAttr ( ) ) return false ; } if ( const AllocaInst * Alloca = dyn_cast < AllocaInst > ( SV ) ) { if ( Alloca -> isSwiftError ( ) ) return false ; } } Address Addr ; if ( ! computeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr , I -> getType ( ) ) ) return false ; bool WantZExt = true ; MVT RetVT = VT ; const Value * IntExtVal = nullptr ; if ( I -> hasOneUse ( ) ) { if ( const auto * ZE = dyn_cast < ZExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( ZE -> getType ( ) , RetVT ) ) IntExtVal = ZE ; else RetVT = VT ; } else if ( const auto * SE = dyn_cast < SExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( SE -> getType ( ) , RetVT ) ) IntExtVal = SE ; else RetVT = VT ; WantZExt = false ; } } unsigned ResultReg = emitLoad ( VT , RetVT , Addr , WantZExt , createMachineMemOperandFor ( I ) ) ; if ( ! ResultReg ) return false ; if ( IntExtVal ) { Register Reg = lookUpRegForValue ( IntExtVal ) ; auto * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) { if ( RetVT == <STR_LIT> && VT <= <STR_LIT> ) { if ( WantZExt ) { MachineBasicBlock :: iterator I ( std :: prev ( FuncInfo . InsertPt ) ) ; ResultReg = std :: prev ( I ) -> getOperand ( <NUM_LIT>


<s> gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT &&