<s> rtx_insn * insn ; rtx scratch , tmp0 , tmp1 , tmp2 ; rtx ( * gen_divmod4_1 ) ( rtx , rtx , rtx , rtx ) ; rtx ( * gen_zero_extend ) ( rtx , rtx ) ; rtx ( * gen_test_ccno_1 ) ( rtx , rtx ) ; switch ( mode ) { case SImode : gen_divmod4_1 = signed_p ? gen_divmodsi4_1 : gen_udivmodsi4_1 ; gen_test_ccno_1 = gen_testsi_ccno_1 ; gen_zero_extend = gen_zero_extendqisi2 ; break ; case DImode : gen_divmod4_1 = signed_p ? gen_divmoddi4_1 : gen_udivmoddi4_1 ; gen_test_ccno_1 = gen_testdi_ccno_1 ; gen_zero_extend = gen_zero_extendqidi2 ; break ; default : gcc_unreachable ( ) ; } end_label = gen_label_rtx ( ) ; qimode_label = gen_label_rtx ( ) ; scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , operands [ <NUM_LIT> ] ) ; scratch = expand_simple_binop ( mode , IOR , scratch , operands [ <NUM_LIT> ] , scratch , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_test_ccno_1 ( scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp0 = gen_rtx_EQ ( VOIDmode , tmp0 , const0_rtx ) ; tmp0 = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp0 , gen_rtx_LABEL_REF ( VOIDmode , qimode_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp0 ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = qimode_label ; div = gen_divmod4_1 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( div ) ; emit_jump_insn ( gen_jump ( end_label ) ) ; emit_barrier ( ) ; emit_label ( qimode_label ) ; tmp0 = lowpart_subreg ( HImode , scratch , mode ) ; tmp1 = lowpart_subreg ( HImode , operands [ <NUM_LIT> ] , mode ) ; tmp2 = lowpart_subreg ( QImode , operands [ <NUM_LIT> ] , mode ) ; emit_insn ( gen_udivmodhiqi3 ( tmp0 , tmp1 , tmp2 ) ) ; if ( signed_p )


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) , OpVT = Op . getValueType ( ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . getVectorElementType ( ) . getSizeInBits ( ) == OpVT . getVectorElementType ( ) . getSizeInBits ( ) ) { return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT ,


<s> Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( <STR_LIT> ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( TRI -> getRegSizeInBits ( * PS -> RC ) - <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++


<s> if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) return true ; return


<s> static DecodeStatus DecodeLoadFP ( MCInst & Inst , unsigned insn

, uint64_t Address , const void * Decoder ) {


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique <

<ISA_LIT>Operand > ( k_Immediate , Ctx ) ;


<s> return StringSwitch < bool > ( Name . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> ,

true ) . Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> if ( ! issetmem ) { srcmem = offset_address ( srcmem , copy_rtx ( tmp ) , piece_size_n ) ; srcmem = adjust_address ( srcmem , mode , <NUM_LIT> ) ; if ( ! TARGET_64BIT && <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) { destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( destmem , srcmem ) ; } } else { rtx tmpreg [ <NUM_LIT> ] ; gcc_assert ( unroll <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { tmpreg [ i ] = gen_reg_rtx ( mode ) ; if ( i ) srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( tmpreg [ i ] , srcmem ) ; } for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , tmpreg [ i ] ) ; } } } else for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , value ) ; } tmp = expand_simple_binop ( iter_mode , PLUS , iter , piece_size , iter , true , OPTAB_LIB_WIDEN ) ; if ( tmp != iter ) emit_move_insn ( iter , tmp ) ; emit_cmp_and_jump_insns ( iter , size , LT , NULL_RTX , iter_mode , true , top_label ) ; if ( expected_size != - <NUM_LIT> ) { expected_size /= GET_MODE_SIZE ( mode ) * unroll ; if ( expected_size == <NUM_LIT> ) predict_jump ( <NUM_LIT> ) ; else if ( expected_size > REG_BR_PROB_BASE ) predict_jump ( REG_BR_PROB_BASE - <NUM_LIT> ) ; else predict_jump ( REG_BR_PROB_BASE - ( REG_BR_PROB_BASE + expected_size / <NUM_LIT> ) / expected_size ) ; } else predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; iter = ix86_zero_extend_to_Pmode ( iter ) ; tmp = expand_simple_binop ( Pmode , PLUS , destptr , iter , destptr , true , OPTAB_LIB_WIDEN ) ; if ( tmp != destptr ) emit_move_insn ( destptr , tmp ) ; if ( ! issetmem ) { tmp = expand_simple_binop ( Pmode , PLUS , srcptr , iter , srcptr , true


<s> void addAM2OffsetImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val


<s> unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , Reg , <NUM_LIT>


<s> int nargs = gimple_call_num_args ( stmt ) ; tree * args = ( nargs > <NUM_LIT> ? gimple_call_arg_ptr ( stmt , <NUM_LIT> ) : & error_mark_node ) ; switch ( fcode ) { BUILTIN_VALL ( UNOP , reduc_plus_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_PLUS_EXPR , args [ <NUM_LIT> ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smax_scal_ , <NUM_LIT> ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umax_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MAX_EXPR , args [ <NUM_LIT> ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smin_scal_ , <NUM_LIT> ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umin_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MIN_EXPR , args [ <NUM_LIT> ] ) ; break ; default : break ; } } } if ( new_stmt ) { gsi_replace ( gsi , new_stmt , true ) ; changed =


<s> Item -> IntValue = IntValue ; Item -> StringValue = std :: string ( StringValue ) ; return ; } Contents . push_back ( { AttributeType :: NumericAndText , Attribute , IntValue ,


<s> CurDAG -> RepositionNode ( N . getNode ( ) , M . getNode ( ) ) ; CurDAG -> ReplaceAllUsesWith ( N , M


<s> bool <ISA_LIT>AsmParser :: parsePrefix ( <ISA_LIT>MCExpr :: VariantKind & RefKind ) { MCAsmParser & Parser = getParser ( ) ; RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( getLexer ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; assert ( getLexer ( ) . is ( AsmToken :: Colon ) && <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } enum { COFF = ( <NUM_LIT> << MCObjectFileInfo :: IsCOFF ) , ELF = ( <NUM_LIT> << MCObjectFileInfo :: IsELF ) , MACHO = ( <NUM_LIT> << MCObjectFileInfo :: IsMachO ) } ; static const struct PrefixEntry { const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } uint8_t CurrentFormat ; switch ( getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ) { case MCObjectFileInfo :: IsMachO : CurrentFormat = MACHO ; break ; case MCObjectFileInfo :: IsELF : CurrentFormat = ELF ; break ; case MCObjectFileInfo :: IsCOFF : CurrentFormat = COFF ; break ; } if ( ~ Prefix -> SupportedFormats & CurrentFormat ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } RefKind = Prefix -> VariantKind ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex (


<s> const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpTy == <STR_LIT> ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; Op = DAG . getNode ( Op . getOpcode ( ) , dl , NewTy , Op .


<s> MachineInstr * SetRegister ( MachineInstr * I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc


<s> case <STR_LIT> : Signed = false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return false ; return <ISA_LIT>FastEmitStore ( VT ,


<s> unsigned <ISA_LIT>TTIImpl :: getAtomicMemIntrinsicMaxElementSize ( )


<s> extract = high_p ? gen_vec_extract_hi_v16hi : gen_vec_extract_lo_v16hi ; break ; case V16SImode : if ( unsigned_p ) unpack = gen_avx512f_zero_extendv8siv8di2 ; else unpack = gen_avx512f_sign_extendv8siv8di2 ; halfmode = V8SImode ; extract = high_p ? gen_vec_extract_hi_v16si : gen_vec_extract_lo_v16si ; break ; case V8SImode : if ( unsigned_p ) unpack = gen_avx2_zero_extendv4siv4di2 ; else unpack = gen_avx2_sign_extendv4siv4di2 ; halfmode = V4SImode ; extract = high_p ? gen_vec_extract_hi_v8si : gen_vec_extract_lo_v8si ; break ; case V16QImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv8qiv8hi2 ; else unpack = gen_sse4_1_sign_extendv8qiv8hi2 ; break ; case V8HImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv4hiv4si2 ; else unpack = gen_sse4_1_sign_extendv4hiv4si2 ; break ; case V4SImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv2siv2di2 ; else unpack = gen_sse4_1_sign_extendv2siv2di2 ; break ; default : gcc_unreachable ( ) ; } if ( GET_MODE_SIZE ( imode ) >= <NUM_LIT> ) { tmp = gen_reg_rtx ( halfmode ) ; emit_insn ( extract ( tmp , src ) ) ; } else if ( high_p ) { tmp = gen_reg_rtx ( V1TImode ) ; emit_insn ( gen_sse2_lshrv1ti3 ( tmp , gen_lowpart ( V1TImode , src ) , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_lowpart ( imode , tmp ) ; } else tmp = src ; emit_insn ( unpack ( dest , tmp ) ) ; } else { rtx ( * unpack ) ( rtx , rtx , rtx ) ; switch ( imode ) { case V16QImode : if ( high_p ) unpack =


<s> MemRefs . clear ( ) ; for ( auto & TS : TSE ) { MachineInstr * MI = TS . MI ; if ( MI -> memoperands_empty ( ) ) { MemRefs . clear (


<s> static DecodeStatus decodeImmZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler


<s> SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , User -> getValueType ( <NUM_LIT> ) , O0 . getNode ( ) , O1 . getNode ( ) ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType

( <NUM_LIT> ) , Cond , TrueRes , FalseRes ) ;


<s> unsigned L = ( insn >> <NUM_LIT> ) & <NUM_LIT> ; unsigned imm6 = ( insn >> <NUM_LIT> ) & <NUM_LIT> ; if ( L == <NUM_LIT> ) { if ( imm6 >> <NUM_LIT> == <NUM_LIT> ) esize = ESize8 ; else if ( imm6 >> <NUM_LIT> == <NUM_LIT> ) esize = ESize16 ; else if ( imm6 >> <NUM_LIT> == <NUM_LIT> ) esize = ESize32 ; else assert ( <NUM_LIT> && <STR_LIT> ) ; } else esize = ESize64 ; if ( LeftShift ) return esize == ESize64


<s> state -> time ++ ; state -> insns_left = state -> issue_rate ; state_transition ( state -> dfa_state ,


<s> void <ISA_LIT>LowOverheadLoops :: RevertWhile ( MachineInstr * MI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> )


<s> return __gnu_unwind_pr_common ( state , ucbp


<s> rtx_insn * insn ; unsigned i ; if ( ! ISA_HAS_MSA ) return false ; for ( i = <NUM_LIT> ; i < d -> nelt ; i ++ ) elts [ i ] = GEN_INT ( d -> perm [ i ] ) ; v = gen_rtvec_v ( d -> nelt , elts ) ; x = gen_rtx_PARALLEL ( VOIDmode , v ) ; if ( ! mips_const_vector_shuffle_set_p ( x , d -> vmode ) )


<s> auto * RetTy = cast < ScalableVectorType > ( II . getType ( ) ) ; bool IsSigned = II . getIntrinsicID ( ) == <STR_LIT> || II . getIntrinsicID ( ) == <STR_LIT> ; if ( auto * ScalarArg = getSplatValue ( UnpackArg ) ) { ScalarArg = Builder . CreateIntCast ( ScalarArg , RetTy -> getScalarType ( ) , IsSigned ) ; Value * NewVal = Builder . CreateVectorSplat ( RetTy -> getElementCount ( )


<s> if ( ! host_integerp ( arg , <NUM_LIT> ) || ( elt = tree_low_cst ( arg , <NUM_LIT> ) , elt


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveCpLocal ( unsigned RegNo ) { if ( Pic ) <ISA_LIT>TargetStreamer ::


<s> void <ISA_LIT>InstPrinter :: printExtendedRegister ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << getRegisterName ( MI -> getOperand ( OpNum ) .


<s> MCTargetStreamer * TS = OutStreamer -> getTargetStreamer ( ) ; assert ( TS &&


<s> ByteSized = Offset . getFixed ( ) ; VGSized = Offset . getScalable ( ) /


<s> else if ( TARGET_THUMB1 ) fprintf ( stream , <STR_LIT> ) ; else fprintf ( stream , <STR_LIT> ) ; } else fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_SOFT_FLOAT ? <STR_LIT> :


<s> static __inline __m64 _mm_mullo_pi32 ( __m64 a , __m64 b ) { return ( __m64 ) __builtin_arm_wmulwl ( ( __v2si ) a , ( __v2si ) b


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent ( ) ; return NextI ; } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . addReg ( StRt ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( LoadI ) . getImm ( ) : getLdStOffsetOp ( LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( StoreI ) . getImm ( ) : getLdStOffsetOp ( StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( Immr ) . addImm ( Imms ) ; } } ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs (


<s> Op -> BTIHint . Val = Val | <NUM_LIT> ; Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str


<s> uint8_t Cost = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) )


<s> PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( ) ) ) { MCOperand CalleeMCOp ; switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol


<s> if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg ,


<s> void rs6000_final_prescan_insn ( rtx_insn * insn , rtx [


<s> bool rs6000_legitimate_offset_address_p ( machine_mode mode , rtx x , bool strict , bool worst_case ) { unsigned HOST_WIDE_INT offset ; unsigned int extra ; if ( GET_CODE ( x ) != PLUS ) return false ; if ( ! REG_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; if ( ! INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return false ; if ( ! reg_offset_addressing_ok_p ( mode ) ) return virtual_stack_registers_memory_p ( x ) ; if ( legitimate_constant_pool_address_p ( x , mode , strict || lra_in_progress ) ) return true ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; extra = <NUM_LIT> ; switch ( mode ) { case V4HImode : case V2SImode : case V1DImode : case V2SFmode : return SPE_CONST_OFFSET_OK ( offset ) ; case DFmode : case DDmode : case DImode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; case TFmode : if ( TARGET_E500_DOUBLE ) return ( SPE_CONST_OFFSET_OK ( offset ) && SPE_CONST_OFFSET_OK ( offset + <NUM_LIT> ) ) ; case TDmode : case TImode : case PTImode : extra = <NUM_LIT> ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra =


<s> if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; return <ISA_LIT>MaterializeGV ( GV , LCREVT . getSimpleVT (


<s> rtx reg ; if ( GET_MODE ( addr ) == Pmode || GET_MODE ( addr ) == VOIDmode ) { reg = copy_addr_to_reg ( addr ) ; REG_POINTER ( reg ) = <NUM_LIT> ; return reg ; } else { gcc_assert ( GET_MODE ( addr ) == DImode && Pmode == SImode ) ; reg = copy_to_mode_reg ( DImode


<s> unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( CPTy ) ; if ( Align == <NUM_LIT> ) Align = MF .

getDataLayout ( ) . getTypeAllocSize ( CPTy ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> return ( __m128i ) __builtin_ia32_vpmacsswd ( ( __v8hi ) __A , ( __v8hi )


<s> if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , C ) ; else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , C ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = l , e = l +

NumLaneElts / <NUM_LIT> ; i != e ; ++ i ) {


<s> vec_st ( ( vec_uchar16 ) ( a ) , si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( b ) , ( vec_uint4 ) ( c ) ) ) ) , ( vector unsigned char


<s> IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec ,


<s> void llvm :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc dl , const TargetInstrInfo & TII , unsigned ScratchReg , int64_t NumBytes , MachineInstr :: MIFlag MIFlags ) { emitRegUpdate ( MBB , MI , dl , TII , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; uint32_t Binary = getAddrMode2OffsetOpValue ( MI , OpIdx + <NUM_LIT> ,


<s> if ( I == MBB . begin ( ) ) return false ; -- I ; } MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( isIndirectBranchOpcode ( LastOpc ) ) return true ; if ( ! isUnpredicatedTerminator ( I ) ) return false ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc )


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return


<s> else address = orig ; crtl -> uses_pic_offset_table = <NUM_LIT> ; if ( gotdata_op ) { if ( TARGET_ARCH64 ) insn = emit_insn ( gen_movdi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; else insn = emit_insn ( gen_movsi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; } else { pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && sparc_pic_register_p ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) return orig ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig ,


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( getRelaxedOpcode ( Inst . getOpcode ( ) , STI ) != Inst . getOpcode ( ) ) return true ; return


<s> if ( ! TL -> isLegalAddImmediate ( Offset ) ) return false ; if ( isThumb1 ) { if ( Base != NewBase ) { BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; } AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) ) . addReg ( NewBase , getKillRegState ( true ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } Base = NewBase ; BaseKill = true ; } bool isDef = ( isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode , Mode ) ; if ( ! Opcode ) return false ; bool Writeback = isThumb1 ; if ( Opcode == <STR_LIT> && isThumb1 ) for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) if ( Base == Regs [ I ] . first ) { Writeback = false ; break ; } MachineInstrBuilder MIB ; if ( Writeback ) { if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) ; if ( ! BaseKill ) UpdateBaseRegUses ( MBB , MBBI , dl , Base , NumRegs , Pred , PredReg ) ; } else { MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getKillRegState ( BaseKill ) ) ; } MIB . addImm ( Pred ) . addReg ( PredReg


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getFPImm (


<s> return ( __m128i ) __builtin_ia32_pminsd128_mask ( ( __v4si ) __A , ( __v4si )


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x'


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { return & Subtarget


<s> bool enablePostRAScheduler ( ) const override { return isGeneric ( ) || isCortexA53 ( ) || isCortexA57


<s> return isUImm < <NUM_LIT> , <NUM_LIT> >


<s> static DecodeStatus DecodeGPRwithAPSRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success


<s> return __builtin_mve_vmulq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) ,


<s> std :: stringstream stream ; stream << std :: hex << val ; return stream . str


<s> void <ISA_LIT>ConstantIslands :: doInitialJumpTablePlacement ( std :: vector < MachineInstr * > & CPEMIs ) { unsigned i = CPEntries . size ( ) ; auto MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; MachineBasicBlock * LastCorrectlyNumberedBB = nullptr ; for ( MachineBasicBlock & MBB : * MF ) { auto MI = MBB . getLastNonDebugInstr ( ) ; unsigned JTOpcode ; switch ( MI -> getOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++

) . addJumpTableIndex ( JTI ) . addImm ( Size ) ;


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; if ( SrcVT == <STR_LIT> ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; SrcReg =


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( NEONSelShuffleTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; } } if ( ST -> hasMVEIntegerOps ( ) ) { if ( Kind == TTI :: SK_Broadcast ) { static const CostTblEntry MVEDupTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( const auto * Entry = CostTableLookup ( MVEDupTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost * ST -> getMVEVectorCostFactor ( ) ; } } int BaseCost = ST -> hasMVEIntegerOps ( ) && Tp -> isVectorTy ( ) ? ST -> getMVEVectorCostFactor ( ) : <NUM_LIT> ; return BaseCost * BaseT :: getShuffleCost ( Kind , Tp , Index


<s> Ret . DefsSingleUse &= MRI -> hasOneNonDBGUse ( Ret . CopyDefs . second -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Ret . TrueDefs = std :: make_pair ( Def1 , Def2 ) ; } else { Ret . TrueDefs = std :: make_pair ( Def1 , nullptr ) ; Ret . CopyDefs . second = nullptr ; } } Ret . ContainedInBlock = <NUM_LIT> ; for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( MIParam . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { unsigned Opc = UseMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ret . FeedsISEL = <NUM_LIT> ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) Ret . FeedsBR = <NUM_LIT> ; Ret . FeedsLogical = isCRLogical ( UseMI ) ; if ( UseMI . getParent ( ) != MIParam . getParent ( ) ) Ret . ContainedInBlock = <NUM_LIT> ; } Ret . SingleUse = MRI -> hasOneNonDBGUse ( MIParam . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! Ret . IsNullary ) { Ret . ContainedInBlock &= ( MIParam . getParent ( ) == Ret . TrueDefs . first -> getParent ( ) ) ; if ( Ret . IsBinary ) Ret . ContainedInBlock &= ( MIParam . getParent ( ) == Ret . TrueDefs . second -> getParent ( ) ) ; } LLVM_DEBUG ( Ret . dump ( ) ) ; if ( Ret . IsBinary && Ret . ContainedInBlock && Ret . SingleUse ) { NumContainedSingleUseBinOps ++ ; if ( Ret . FeedsBR && Ret . DefsSingleUse ) NumToSplitBlocks ++ ; } return Ret


<s> MCAsmBackend * create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const llvm ::


<s> if ( ! Subtarget -> hasNEON ( ) || ! isLegalInterleavedAccessType ( SubVecTy , DL , UseScalable ) ) return false ; unsigned NumStores = getNumInterleavedAccesses ( SubVecTy , DL , UseScalable ) ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = cast < FixedVectorType > ( Op0 -> getType ( ) ) -> getNumElements ( ) ; auto * IntVecTy = FixedVectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = FixedVectorType :: get ( IntTy , LaneLen ) ; } LaneLen /= NumStores ; SubVecTy = FixedVectorType :: get ( SubVecTy -> getElementType ( ) , LaneLen ) ; auto * STVTy = UseScalable ? cast < VectorType > ( getSVEContainerIRType ( SubVecTy ) ) : SubVecTy ; Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = UseScalable ? STVTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) : STVTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * PredTy = VectorType :: get ( Type :: getInt1Ty ( STVTy -> getContext ( ) ) , STVTy -> getElementCount ( ) ) ; static const <STR_LIT> SVEStoreIntrs [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const <STR_LIT> NEONStoreIntrs [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc ; if ( UseScalable ) StNFunc = <STR_LIT> ( SI -> getModule ( ) , SVEStoreIntrs [ Factor - <NUM_LIT> ] , { STVTy } ) ; else StNFunc = <STR_LIT> ( SI -> getModule ( ) , NEONStoreIntrs [ Factor - <NUM_LIT> ] , { STVTy , PtrTy } ) ; Value * PTrue = nullptr ; if ( UseScalable ) { Optional < unsigned > PgPattern = getSVEPredPatternFromNumElements ( SubVecTy ->


<s> const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget


<s> std :: reverse ( RVLocs . begin ( ) , RVLocs


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) ) ) ; const MCExpr * Expr =


<s> if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermi2varv8si3 ; break ; case V16SImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vpermi2varv16si3 ; break ; case V4SFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermi2varv4sf3 ; maskmode = V4SImode ; } break ; case V8SFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermi2varv8sf3 ; maskmode = V8SImode ; } break ; case V16SFmode : if ( TARGET_AVX512F ) { gen = gen_avx512f_vpermi2varv16sf3 ; maskmode = V16SImode ; } break ; case V2DImode : if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermi2varv2di3 ; break ; case V4DImode : if ( TARGET_AVX512VL ) gen = gen_avx512vl_vpermi2varv4di3 ; break ; case V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vpermi2varv8di3 ; break ; case V2DFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermi2varv2df3 ; maskmode = V2DImode ; } break ; case V4DFmode : if ( TARGET_AVX512VL ) { gen = gen_avx512vl_vpermi2varv4df3 ; maskmode = V4DImode ; } break ; case V8DFmode : if ( TARGET_AVX512F ) { gen = gen_avx512f_vpermi2varv8df3 ; maskmode = V8DImode ; } break ; default : break ; } if ( gen == NULL ) return false ; if ( d ) { rtx vec [ <NUM_LIT> ] ; target = d -> target ; op0 = d -> op0 ; op1 = d -> op1 ; for ( int i = <NUM_LIT> ; i < d -> nelt ; ++ i ) vec [ i ] = GEN_INT ( d -> perm [ i ] ) ; mask = gen_rtx_CONST_VECTOR ( maskmode , gen_rtvec_v ( d


<s> void arm_register_target_pragmas ( void ) { targetm . target_option . pragma_parse = arm_pragma_target_parse


<s> MachineInstr * MI2 = & * NextMII ; unsigned RegDstMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegSrcMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! IsMovepSrcRegister ( RegSrcMI1 ) ) return false ; if ( ! IsMovepDestinationReg ( RegDstMI1 ) ) return false ; if ( MI2 -> getOpcode ( ) != Entry . WideOpc ( ) ) return false ; unsigned RegDstMI2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg


<s> case <STR_LIT> : return LPCC :: ICC_EQ ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_PL ; } return LPCC :: ICC_GT ; case <STR_LIT> : return LPCC :: ICC_UGT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_MI ; return LPCC :: ICC_LT ; case <STR_LIT> : return LPCC :: ICC_ULT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_MI ; } return LPCC :: ICC_LE ; case <STR_LIT> : return LPCC :: ICC_ULE ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_PL ; return LPCC :: ICC_GE ; case <STR_LIT> : return LPCC :: ICC_UGE ; case <STR_LIT> : return LPCC :: ICC_NE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> expand_bool_pixel = __bool_keyword ; rid_code = RID_MAX ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT || ( rid_code == RID_DOUBLE && TARGET_VSX ) || ( rid_code == rid_int128 ( ) && TARGET_VADDUQM ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) expand_bool_pixel = __pixel_keyword ; else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_pixel = __bool_keyword ; else if ( ident ) { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) expand_bool_pixel = __pixel_keyword ; else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_pixel = __bool_keyword ; } } else if ( TARGET_VADDUQM && ( ident == C_CPP_HASHNODE ( __int128_type ) || ident == C_CPP_HASHNODE ( __uint128_type ) ) ) expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; } } else if ( expand_bool_pixel && ident == C_CPP_HASHNODE ( __pixel_keyword ) ) { expand_this = C_CPP_HASHNODE ( __pixel_keyword ) ; expand_bool_pixel = <NUM_LIT> ; } else if ( expand_bool_pixel && ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_this = C_CPP_HASHNODE ( __bool_keyword ) ; expand_bool_pixel = <NUM_LIT> ; } return


<s> ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( PACStack :: MaskReg , RegState :: Define ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( flag ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( PACStack :: MaskReg , RegState :: Define ) . addUse ( PACStack :: CR ) . setMIFlag ( flag ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( PACStack :: MaskReg ) . addImm ( <NUM_LIT> ) . setMIFlag ( flag ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( PACStack :: MaskReg , RegState :: Define )


<s> else WideRes = getSETCCInGPR ( N -> getOperand ( <NUM_LIT> ) , N -> getOpcode ( ) == <STR_LIT> ? SetccInGPROpts :: SExtOrig : SetccInGPROpts :: ZExtOrig ) ; if ( ! WideRes ) return false ; SDLoc dl ( N ) ; bool Inputs32Bit = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ; bool Output32Bit = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ; NumSextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> :


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm

( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> if ( hasStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumb2Function ( ) && MFI . hasVarSizedObjects ( ) && MFI .

getLocalFrameSize ( ) >= <NUM_LIT> ) return true ;


<s> return ( cfun -> machine -> global_pointer != INVALID_REGNUM && cfun

-> machine -> frame . cprestore_size > <NUM_LIT> ) ;


<s> __arm_cdp ( const unsigned int __coproc , const unsigned int __opc1 , const unsigned int __CRd , const unsigned int __CRn , const unsigned int __CRm , const unsigned int __opc2 ) { return __builtin_arm_cdp ( __coproc , __opc1 , __CRd ,


<s> const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget >


<s> AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag , <NUM_LIT> ) ; switch ( item . Type ) { case AttributeItemType :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue , <NUM_LIT> ) ; break ; case AttributeItemType :: TextAttribute : Streamer . EmitBytes ( UppercaseString ( item . StringValue ) , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; break ; default : assert ( <NUM_LIT> &&


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>ExpandPseudoPass ( get<ISA_LIT>TargetMachine ( )


<s> void printU64ImmOperand ( const MachineInstr * MI


<s> SDNode * Res = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ; } SDValue Zero = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( SPOffset , DL , <STR_LIT> ) , DAG .

getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ;


<s> return MCInstBuilder ( Opcode ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI

-> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> DOP_ENTRY_HSD ( ps , inst , ty ) { <STR_LIT> ## _S , { <STR_LIT> ## _S , <STR_LIT> ## _S , \ <STR_LIT> ##


<s> return ArePtrs64bit ( ) ? <STR_LIT> :


<s> SDValue InTrans = DAG . getNode ( IntrData -> Opc0 , dl , VTs , Op . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , InTrans ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , dl , Op -> getValueType ( <NUM_LIT> ) , SetCC ) ; return DAG . getNode ( <STR_LIT> , dl , Op -> getVTList ( ) , Ret , SDValue ( InTrans . getNode ( ) , <NUM_LIT> ) ) ; } case ADX : { SDVTList CFVTs = DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue GenCF = DAG . getNode ( <STR_LIT> , dl , CFVTs , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Res = DAG . getNode ( IntrData -> Opc0 , dl , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , GenCF . getValue ( <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Res . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; SDValue Results [ ] = { SetCC , Store } ; return DAG . getMergeValues ( Results , dl ) ; } case COMPRESS_TO_MEM : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToCompress = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MVT VT = DataToCompress . getSimpleValueType ( ) ; MemIntrinsicSDNode * MemIntr = dyn_cast < MemIntrinsicSDNode > ( Op ) ; assert ( MemIntr && <STR_LIT> ) ; if ( isAllOnesConstant ( Mask ) ) return DAG . getStore ( Chain , dl , DataToCompress , Addr , MemIntr -> getMemOperand ( ) ) ; SDValue Compressed = getVectorMaskingNode ( DAG . getNode ( IntrData -> Opc0 , dl , VT , DataToCompress ) , Mask , DAG . getUNDEF ( VT ) , Subtarget , DAG ) ; return DAG . getStore ( Chain , dl , Compressed , Addr , MemIntr -> getMemOperand ( ) ) ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToTruncate = Op .


<s> unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && Subtarget . hasAVX ( ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; if ( MatchSizeInBits == <NUM_LIT> && BitWidth < <NUM_LIT> && ! Subtarget . hasInt256 ( ) ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; MatchSizeInBits = Match . getValueSizeInBits ( ) ; } MVT MaskSrcVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskSrcVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskSrcVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; SDValue BitcastLogicOp = DAG . getBitcast ( MaskSrcVT , Match ) ; Movmsk = getPMOVMSKB ( DL , BitcastLogicOp , DAG , Subtarget ) ; NumElts = MaskSrcVT . getVectorNumElements ( ) ; } assert ( ( NumElts <= <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; MVT CmpVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( BinOp == <STR_LIT> ) { SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , CmpVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , CmpVT , Movmsk ) ; Result = DAG . getNode ( <STR_LIT> , DL , CmpVT , Result , Mask ) ; return DAG . getZExtOrTrunc ( Result , DL , ExtractVT ) ; } SDValue CmpC ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CmpC = DAG . getConstant ( <NUM_LIT> , DL , CmpVT


<s> } else if ( AlignMask <= <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } else { assert ( CanUseBFC


<s> const Constant * getPromotedGlobalInit ( ) const { return


<s> if ( OverrideVectorInsertExtractBaseCost . getNumOccurrences ( ) > <NUM_LIT> ) return OverrideVectorInsertExtractBaseCost ; return


<s> FunctionPass * llvm :: create<ISA_LIT>StackTaggingPass ( bool


<s> SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC || CmpRHSC -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; const unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ; else return SDValue


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm2 ( SDValue N , SDValue & Imm ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst


<s> assert ( RegNo < N && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Regs [ RegNo ] ) ) ; return MCDisassembler


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) )


<s> return ggc_cleared_alloc < machine_function > (


<s> void DecodeVPERM2X128Mask ( unsigned NumElts , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { unsigned HalfSize = NumElts / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != <NUM_LIT>


<s> static __inline void si_hlgti ( qword a , unsigned int b ) { union { vector unsigned int v ; unsigned int i [ <NUM_LIT>


<s> return StackOffset :: getFixed ( MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( )


<s> LastOpcode = LSMOpcode ; unsigned Loc = MI2LocMap [ Op ] ; if ( Loc <= FirstLoc ) { FirstLoc = Loc ; FirstOp = Op ; } if ( Loc >= LastLoc ) { LastLoc = Loc ; LastOp = Op ; } } if ( NumMove <= <NUM_LIT> ) Ops . pop_back ( ) ; else { SmallPtrSet < MachineInstr * , <NUM_LIT> > MemOps ; SmallSet < unsigned , <NUM_LIT> > MemRegs ; for ( size_t i = Ops . size ( ) - NumMove , e = Ops . size ( ) ; i != e ; ++ i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI , AA ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( & * InsertPos ) || InsertPos -> isDebugInstr ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; Register FirstReg , SecondReg ; Register BaseReg , PredReg ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , FirstReg , SecondReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID


<s> O << ( int ) MI -> getOperand ( OpNo ) . getImm (


<s> if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineInstr * OffsetInst = getDefIgnoringCopies ( PtrAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; return selectExtendedSHL ( Root , PtrAdd -> getOperand ( <NUM_LIT> ) , OffsetInst -> getOperand ( <NUM_LIT>


<s> void printCallOperand ( const MachineInstr * MI , unsigned OpNo ) { printOp ( MI -> getOperand (


<s> return ( int16x8_t ) __builtin_neon_vmlalsv8qi ( __a ,


<s> static bool isSortedByValueNo ( ArrayRef < CCValAssign > ArgLocs ) { return std :: is_sorted ( ArgLocs . begin ( ) , ArgLocs . end ( ) , [ ] ( const CCValAssign & A , const CCValAssign


<s> int getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty ,


<s> __rv . __o = __builtin_neon_vld4v16qi ( ( const __builtin_neon_qi * )


<s> if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) )


<s> unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg


<s> const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) , getContext


<s> for ( const std :: pair < Register , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return


<s> if ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) { CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) ; unsigned Opc = Cmp . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; bool IllegalFPCMov = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! isScalarFPTypeInSSEReg ( VT ) ) IllegalFPCMov = ! hasFPCMov ( cast < ConstantSDNode > ( CC ) -> getSExtValue ( ) ) ; if ( ( is<ISA_LIT>LogicalCmp ( Cmp ) && ! IllegalFPCMov ) || Opc == <STR_LIT> ) { Cond = Cmp ; addTest = false ; } } if ( addTest ) { if ( Cond . getOpcode ( ) == <STR_LIT> ) Cond = Cond . getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { SDValue NewSetCC = LowerToBT ( Cond , <STR_LIT> , DL , DAG ) ; if ( NewSetCC . getNode ( ) ) { CC = NewSetCC . getOperand ( <NUM_LIT> ) ; Cond = NewSetCC . getOperand ( <NUM_LIT> ) ; addTest = false ; } } } if ( addTest ) { CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; Cond = EmitTest ( Cond , <STR_LIT> , DAG ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> ) { unsigned CondCode = cast < ConstantSDNode > ( CC ) -> getZExtValue ( ) ; if ( ( CondCode == <STR_LIT> || CondCode == <STR_LIT> ) && ( isAllOnes ( Op1 ) || isAllOnes ( Op2 ) ) && ( isZero ( Op1 ) || isZero ( Op2 ) ) ) { SDValue Res = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Cond ) ; if ( isAllOnes ( Op1 ) != ( CondCode == <STR_LIT> ) ) return DAG . getNOT ( DL , Res , Res . getValueType ( ) ) ; return Res


<s> AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> if ( oldFlags . m_IsaLevel == <NUM_LIT> ) { oldFlags = newFlags ; return true ; } if ( newFlags . m_IsaLevel > oldFlags . m_IsaLevel ) oldFlags . m_IsaLevel = newFlags . m_IsaLevel ; oldFlags . m_IsaRev = std :: max ( oldFlags . m_IsaRev , newFlags . m_IsaRev ) ; oldFlags . m_GprSize = std :: max ( oldFlags . m_GprSize , newFlags . m_GprSize ) ; oldFlags . m_Cpr1Size = std :: max ( oldFlags . m_Cpr1Size , newFlags . m_Cpr1Size ) ; oldFlags . m_Cpr2Size = std :: max ( oldFlags . m_Cpr2Size , newFlags . m_Cpr2Size ) ; oldFlags . m_Ases |= newFlags . m_Ases ; oldFlags . m_Flags1 |= newFlags . m_Flags1 ; if ( oldFlags . m_FpAbi == newFlags . m_FpAbi ) return true ; if ( isFpGreater ( newFlags . m_FpAbi , oldFlags . m_FpAbi ) ) { oldFlags . m_FpAbi = newFlags . m_FpAbi ; return true ; } if ( isFpGreater ( oldFlags . m_FpAbi , newFlags . m_FpAbi ) ) return true ; llvm :: StringRef oldAbiName = getFpAbiName ( oldFlags . m_FpAbi ) ; llvm :: StringRef newAbiName = getFpAbiName ( newFlags . m_FpAbi ) ; warning ( diag :: warn_<ISA_LIT>_fp_abi_incompatible ) << oldAbiName << newAbiName << pInput . name ( ) ; return


<s> void <ISA_LIT>FrameLowering :: registerStackRegions ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; SVEVecStackRegion * Pred = new SVEVecStackRegion


<s> ( void ) MaskTySize ; assert ( ( MaskTySize == <NUM_LIT> || MaskTySize == <NUM_LIT> ) && <STR_LIT> ) ; SmallBitVector UndefElts ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = RawMask . size ( ) ; unsigned NumEltsPerLane = <NUM_LIT> / ElSize ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Selector = RawMask [ i ] ; unsigned MatchBit = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; if ( ( M2Z & <NUM_LIT> ) != <NUM_LIT> && MatchBit != ( M2Z & <NUM_LIT> ) ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } int Index = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; if ( ElSize == <NUM_LIT> ) Index += ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; else Index += Selector &


<s> unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( OpFlags &


<s> if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset


<s> return isImmediate < <NUM_LIT> , <NUM_LIT>


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT>


<s> Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> )


<s> MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; case <STR_LIT>


<s> Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , <STR_LIT> ) ; if ( AM . Segment . getNode ( ) ) Segment = AM . Segment ; else Segment = CurDAG -> getRegister ( <NUM_LIT> ,


<s> Align = <NUM_LIT> ; } } else if ( Kind . isMergeableConst32 ( ) ) { if ( Align <= <NUM_LIT> ) { COMDATSymName = <STR_LIT> + scalarConstantToHexString ( C ) ; Align = <NUM_LIT> ; } } if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( <STR_LIT> , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( DL , Kind , C


<s> if ( GET_MODE_BITSIZE ( mode ) > <NUM_LIT> && TARGET_AVX128_OPTIMAL ) return cost * GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; return cost


<s> if ( <STR_LIT> ( Vec . getNode ( ) ) ) { NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , WideSubVec , DAG . getConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; Vec = ShiftRight ? DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , DAG . getConstant ( ShiftRight , dl , <STR_LIT> ) ) : Vec ; return ExtractSubVec ( Vec ) ; } if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getConstant ( SubVecNumElems , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; WideSubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , getZeroVector ( WideOpVT , Subtarget , DAG , dl ) , SubVec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , WideSubVec ) ; return ExtractSubVec ( Vec ) ; } if ( IdxVal + SubVecNumElems == NumElems ) { WideSubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , WideSubVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; SDValue ShiftBits = DAG . getConstant ( SubVecNumElems , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec ,


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS . write ( <STR_LIT> , <NUM_LIT> ) ; return true


<s> SDValue <ISA_LIT>TargetLowering :: lowerCos ( SDValue Op , SelectionDAG & DAG ) const { return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( C -> isNullValue ( ) && CC == <STR_LIT> ) { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Zext = Op . getOperand ( <NUM_LIT> ) ; if ( VT . bitsLT ( <STR_LIT> ) ) { VT = <STR_LIT> ; Zext = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned Log2b = Log2_32 ( VT . getSizeInBits ( ) ) ; SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Zext ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , VT , Clz , DAG . getConstant ( Log2b , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scc ) ; } if ( C -> isAllOnesValue ( ) || C

-> isNullValue ( ) ) return SDValue ( ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFnEnd ( SMLoc L ) { if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; resetUnwindDirectiveParserState (


<s> bool isElementTypeLegalForScalableVector ( Type * Ty ) const { if ( Ty -> isPointerTy ( ) ) return true ; if ( Ty -> isBFloatTy ( ) && ST -> hasBF16 ( ) ) return true ; if ( Ty -> isHalfTy ( ) || Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) return true ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty ->

isIntegerTy ( <NUM_LIT> ) ) return true ;


<s> PendingBA -> setLastFragment ( CF ) ; PendingBA = nullptr ; if ( isa_and_nonnull < MCDataFragment > ( CF ) ) OS . insert ( new MCDataFragment ( ) ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( AlignBoundary . value ( ) > Sec -> getAlignment ( ) )


<s> <ISA_LIT>_64RelType Type = getType64 ( Fixup . getKind ( ) , Modifier , IsPCRel ) ; if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Modifier , Type , IsPCRel ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU )


<s> for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( V2IsSplat


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) return false ; if ( Offset < <NUM_LIT> ) return false ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale =


<s> Parser . Lex ( ) ; if ( parseOptionalToken ( AsmToken :: RCurly ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateMatrixTileList ( <NUM_LIT> , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Parser . getTok ( ) . getString ( ) . equals_insensitive ( <STR_LIT> ) ) { Parser . Lex ( ) ; if ( parseToken ( AsmToken :: RCurly , <STR_LIT> ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: CreateMatrixTileList ( <NUM_LIT> , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } SMLoc TileLoc = getLoc ( ) ; unsigned FirstReg , ElementWidth ; auto ParseRes = ParseMatrixTile ( FirstReg , ElementWidth ) ; if ( ParseRes != MatchOperand_Success ) { Parser . getLexer ( ) . UnLex ( LCurly ) ; return ParseRes ; } const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned PrevReg = FirstReg ; unsigned Count = <NUM_LIT> ; SmallSet < unsigned , <NUM_LIT> > DRegs ; <ISA_LIT>Operand :: ComputeRegsForAlias ( FirstReg , DRegs , ElementWidth ) ; SmallSet < unsigned , <NUM_LIT> > SeenRegs ; SeenRegs . insert ( FirstReg ) ; while ( parseOptionalToken ( AsmToken :: Comma ) ) { TileLoc = getLoc ( ) ; unsigned Reg , NextElementWidth ; ParseRes = ParseMatrixTile ( Reg , NextElementWidth ) ; if ( ParseRes != MatchOperand_Success ) return ParseRes ; if ( ElementWidth !=


<s> void addMemImm8OffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> bool <ISA_LIT>TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits


<s> <ISA_LIT>JITInfo :: <ISA_LIT>JITInfo ( <ISA_LIT>TargetMachine & tm ) : TM ( tm ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; useGOT = <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return


<s> return ( __m128 ) __builtin_ia32_vfmsubps128_mask ( ( __v4sf ) __A , ( __v4sf ) __B , (


<s> <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument


<s> Inst . addOperand ( MCOperand :: createReg (


<s> unsigned SrcReg = <NUM_LIT> ; if ( cast < StoreInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; SrcReg = getRegForValue ( Op0 )


<s> Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : case <STR_LIT>


<s> tmpInst . setOpcode ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( AtRegNum ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . setLoc ( IDLoc ) ; Out . emitInstruction ( tmpInst , * STI ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( AtRegNum ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . setLoc ( IDLoc ) ; Out . emitInstruction ( tmpInst , * STI ) ; return MER_Success


<s> void addVectorIndexBOperands ( MCInst & Inst , unsigned N )


<s> } else if ( isa < StoreInst > ( SingleUser ) ) return getLoadStoreAddrMode ( HasVector , I -> getType ( ) ) ; } } else if ( auto * StoreI = dyn_cast < StoreInst > ( I ) ) { if ( auto * LoadI = dyn_cast < LoadInst > ( StoreI -> getValueOperand ( ) ) ) if ( LoadI -> hasOneUse ( ) && LoadI -> getParent ( ) == I -> getParent ( ) ) return getLoadStoreAddrMode ( HasVector , LoadI -> getType ( ) ) ; } if ( HasVector && ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ) { Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { User * LoadUser = * I -> user_begin ( ) ; if ( isa < InsertElementInst > ( LoadUser


<s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand ::


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * EVal ; Op = nullptr ; switch ( getLexer ( ) . getKind ( ) ) { default : break ; case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; unsigned RegKind ; if ( matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) { StringRef name = Parser . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( RegNo ) { default : Op = <STR_LIT> ( RegNo , RegKind , S , E ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Minus : case AsmToken


<s> dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; CreateLoadIns ( Builder , Acc , & VecLd0 ) ; CreateLoadIns ( Builder , Acc , & VecLd1 ) ; Value * Args [ ] = { VecLd0 , VecLd1 , Acc } ; Function * SMLAD = <STR_LIT> ( M , <STR_LIT> ) ; CallInst * Call = Builder . CreateCall ( SMLAD , Args ) ; return


<s> bool <ISA_LIT>TargetELFStreamer :: emitDirectiveCpRestore ( int Offset , function_ref < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer :: emitDirectiveCpRestore ( Offset , GetATReg , IDLoc


<s> static unsigned loongarch_save_libcall_count ( unsigned mask ) { for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P ( mask , n ) ) return CALLEE_SAVED_REG_NUMBER ( n


<s> bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Dst ) ; unsigned EltSize = Ty . getScalarSizeInBits ( ) ; if ( EltSize == <NUM_LIT> ) return false ; unsigned NumElts = Ty . getNumElements ( ) ; if ( isREVMask ( ShuffleMask , EltSize , NumElts , <NUM_LIT> ) ) { MatchInfo = ShuffleVectorPseudo ( <STR_LIT> , Dst , { Src } ) ; return true ; } return


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned LblOperand = Inst . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; Target = Addr +


<s> bool MVETailPredication :: TryConvert ( Value * TripCount ) { if ( ! IsPredicatedVectorLoop ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SetVector < Instruction * > Predicates ; auto getPredicateOp = [ ] ( IntrinsicInst * I ) { unsigned IntrinsicID = I -> getIntrinsicID ( ) ; if ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) return <NUM_LIT> ; return ( IntrinsicID == <STR_LIT> || isGather ( I ) ) ? <NUM_LIT> : <NUM_LIT> ; } ; for ( auto * I : MaskedInsts ) { Value * PredOp = I -> getArgOperand ( getPredicateOp ( I ) ) ; auto * Predicate = dyn_cast < Instruction > ( PredOp ) ; if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; auto * ActiveLaneMask = dyn_cast < IntrinsicInst > ( Predicate ) ; if ( ! ActiveLaneMask || ActiveLaneMask -> getIntrinsicID ( ) != <STR_LIT> ) continue ; Predicates . insert ( Predicate ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << *


<s> this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; if ( i > <NUM_LIT> ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , <NUM_LIT> ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == TFmode ) { if ( nargs == <NUM_LIT> ) emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , <NUM_LIT> , arg [ <NUM_LIT> ] , GET_MODE ( arg [ <NUM_LIT> ] ) , arg [ <NUM_LIT> ] , GET_MODE ( arg [ <NUM_LIT> ] ) ) ; else emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , <NUM_LIT> , arg [ <NUM_LIT> ] , GET_MODE ( arg [ <NUM_LIT> ] ) , arg [ <NUM_LIT> ] , GET_MODE ( arg [ <NUM_LIT> ] ) , arg [ <NUM_LIT> ] , GET_MODE ( arg [ <NUM_LIT> ] ) ) ; if ( ret_slot ) emit_move_insn ( operands [ <NUM_LIT> ] , ret_slot ) ; } else { rtx ret ; gcc_assert ( nargs == <NUM_LIT> ) ; ret = emit_library_call_value ( func_sym , operands [ <NUM_LIT> ] , LCT_NORMAL , GET_MODE ( operands [ <NUM_LIT> ] ) , <NUM_LIT> , arg [ <NUM_LIT> ] , GET_MODE ( arg [ <NUM_LIT> ] ) ) ; if ( ret != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ]


<s> int xstormy16_carry_plus_operand ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) < - <NUM_LIT> || INTVAL ( XEXP ( x


<s> void <ISA_LIT>FlagsCopyLoweringPass :: insertTest ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Pos , const DebugLoc & Loc , unsigned Reg ) { auto TestI = BuildMI ( MBB , Pos , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( Reg ) ; ( void ) TestI


<s> unsigned Vd = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; regs = regs >> <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ++ Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } return S


<s> if ( TT . isOSWindows ( ) && TT . getArch ( ) ==

Triple :: x86 ) addPass ( create<ISA_LIT>WinEHStatePass ( ) ) ;


<s> if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) return <NUM_LIT> ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; switch ( VT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT>


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> } if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) { if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ; return CSR_SRV464_TLS_PE_SaveList ; } bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) && ! Subtarget . isUsingPCRelativeCalls ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 ( )


<s> RegisterTarget < Triple :: xncm > X ( The<ISA_LIT>Target , <STR_LIT>


<s> Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; return


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) { PM . add ( createBasicTargetTransformInfoPass ( this ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass (


<s> bool <ISA_LIT>PostLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { const auto * LI = MI . getParent ( ) -> getParent (

) -> getSubtarget ( ) . getLegalizerInfo ( ) ;


<s> if ( <STR_LIT> ( Imm ) ) { MI . setDesc ( TII -> get ( LLIxL ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ( Reg ) ) ; return true ; } if ( <STR_LIT> ( Imm ) ) { MI . setDesc ( TII -> get ( LLIxH ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ( Reg ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm (


<s> int getVarArgsFrameIndex ( ) const { return


<s> switch ( ScalarBits ) { case <NUM_LIT> : { unsigned ScalarCost = getArithmeticInstrCost ( Opcode , Ty -> getScalarType ( ) ) ; unsigned Cost = ( VF * ScalarCost ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } case <NUM_LIT> : case <NUM_LIT> : return NumVectors ; default : break ; } } if ( Opcode == Instruction :: FRem ) { unsigned Cost = ( VF * LIBCALL_COST ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> && ScalarBits == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } } else { if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) return <NUM_LIT> ; if ( Opcode == Instruction :: FRem ) return LIBCALL_COST ; if ( Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) return ( ScalarBits >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: Or ) return


<s> if ( OpVT . getVectorElementType ( ) == <STR_LIT> ) return insert1BitVector ( Op , DAG , Subtarget ) ; assert ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && <STR_LIT> ) ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , false ) ) return Ld ; } } if ( auto * Ld = dyn_cast < LoadSDNode > ( peekThroughOneUseBitcasts ( SubVec2 ) ) ) { if ( SubVec2 == SubVec && <STR_LIT> ( Ld ) && areOnlyUsersOf ( SubVec2 . getNode ( ) , { Op , Vec } ) ) { return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec ) ; } } if ( SubVec . getOpcode ( ) == <STR_LIT> && SubVec == SubVec2 ) { return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec . getOperand ( <NUM_LIT> ) ) ; } } } if ( SubVecVT . is128BitVector ( ) ) return insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( SubVecVT . is256BitVector ( ) ) return insert256BitVector ( Vec , SubVec


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( Val ) ; if ( ! LT . second . isVector ( ) ) return


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; } setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT ,


<s> std :: pair < bool , SDNode * > Ret = selectNode ( Node ) ; if ( Ret . first ) return Ret . second ; switch ( Opcode ) { default : break ; case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : case <STR_LIT> : assert ( cast < MemSDNode > ( Node ) -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> <= cast < MemSDNode > ( Node ) -> getAlignment ( ) && <STR_LIT> ) ; break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT>


<s> const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , <NUM_LIT> ) > <NUM_LIT> ) return Sched :: Latency ; return Sched


<s> MIB . addReg ( <STR_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT>


<s> vmlsl_s16 ( int32x4_t a , int16x4_t b , int16x4_t c ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( MachineRegisterInfo :: reg_instr_iterator ri = MRI . reg_instr_begin ( <STR_LIT> ) , re = MRI . reg_instr_end ( ) ; ri != re ; ++ ri ) if (


<s> const <ISA_LIT>TargetLowering * TLI = static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering


<s> VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI . CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI . CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) , ABI . StackAddrSpace ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value *


<s> return BaseCost + FixedVTy -> getNumElements ( ) ; } if ( Opcode != Instruction :: FAdd ) return InstructionCost :: getInvalid ( ) ; auto * VTy = cast < ScalableVectorType > ( ValTy ) ; InstructionCost Cost = getArithmeticInstrCost ( Opcode , VTy -> getScalarType ( ) , CostKind ) ; Cost *= getMaxNumElements ( VTy -> getElementCount ( ) ) ; return Cost ; } if ( isa < ScalableVectorType > ( ValTy ) ) return getArithmeticReductionCostSVE ( Opcode , ValTy , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry CostTblNoPairwise [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; switch ( ISD ) { default : break ; case <STR_LIT> : if ( const auto * Entry = CostTableLookup ( CostTblNoPairwise , ISD , MTy ) ) return

( LT . first - <NUM_LIT> ) + Entry -> Cost ;


<s> SMLoc getStartLoc ( ) const { return StartLoc


<s> static DecodeStatus DecodetGPREvenRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void


<s> return ( REG_P ( exp ) && ( VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) || VALID_AVX512F_REG_OR_XI_MODE ( GET_MODE


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT>


<s> bool <ISA_LIT>FastISel :: SelectFPToSI ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; const Type * RetTy = I -> getType ( ) ; if ( ! isTypeLegal ( RetTy , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; const Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = <STR_LIT> ; else if ( OpTy -> isDoubleTy