<s> case MachineOperand :: MO_GlobalAddress : Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: CreateExpr (


<s> const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize (


<s> Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , <STR_LIT> ) ; unsigned SrcOddReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcOddReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg (


<s> static const char * nds32_cond_code_str ( int code ) { switch ( code ) { case NE : return


<s> FunctionPass * llvm :: create<ISA_LIT>DelaySlotFillerPass


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addDef ( <STR_LIT> , RegState :: Dead ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> unsigned getImmMinusOneOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ) const { return MI . getOperand ( Op ) . getImm


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , dl ,


<s> if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; EVT SclVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! SclVT . isScalarInteger ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Vec ; SmallVector < int , <NUM_LIT> > ShuffleMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( NumElts == SclVT . getSizeInBits ( ) && <STR_LIT> ) ; if ( NumElts > EltSizeInBits ) { assert ( ( NumElts % EltSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Scale = NumElts / EltSizeInBits ; EVT BroadcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclVT , EltSizeInBits ) ; Vec = DAG . getNode ( <STR_LIT> , DL , BroadcastVT , N00 ) ; Vec = DAG . getBitcast ( VT , Vec ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) ShuffleMask . append ( EltSizeInBits , i ) ; } else { SDValue Scl = DAG . getAnyExtOrTrunc ( N00 ,


<s> case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( BaseReg , <NUM_LIT> , S , E ) ) ; return MatchOperand_Success ; case AsmToken :: Plus : Parser . Lex ( ) ; break ; case AsmToken :: Minus : break ; } <ISA_LIT>Operand * Offset = <NUM_LIT> ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ; Offset = ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg

, Offset ) : <STR_LIT> ( BaseReg , Offset ) ) ;


<s> if ( VT . getSizeInBits ( ) == ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) && Idx == ( VT . getVectorNumElements ( ) / <NUM_LIT> ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == SubVT && isNullConstant ( Src . getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( Src . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Sub ) ; return true ; } } return


<s> IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasQuadwordAtomics = false ; HasDirectMove = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasStoreFusion = false ; HasAddiLoadFusion = false ; HasAddisLoadFusion = false ; HasArithAddFusion = false ; HasAddLogicalFusion = false ; HasLogicalAddFusion = false ; HasLogicalFusion = false ; HasSha3Fusion = false ; HasCompareFusion = false ; HasWideImmFusion = false ; HasZeroMoveFusion = false ; HasBack2BackFusion = false ; IsISA2_06 = false ; IsISA2_07 = false ; IsISA3_0 = false ; IsISA3_1 = false ; IsISAFuture = false ; UseLongCalls = false ; SecurePlt = false ; VectorsUseTwoUnits = false ; Use<ISA_LIT>PreRASchedStrategy = false


<s> bool isModuleDirectiveAllowed ( ) { return


<s> switch ( ( unsigned ) Kind ) { default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> (


<s> auto OpcodeN = N -> getOpcode ( ) ; auto OpcodeN0 = N0 . getOpcode ( ) ; if ( ! ( ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) || ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = N0 . getValueType ( ) ; if ( N0 . getResNo ( ) != <NUM_LIT> || InVT != <STR_LIT> || ! ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return SDValue ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; auto DivRemOpcode = OpcodeN0 == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue R = DAG . getNode ( DivRemOpcode , SDLoc ( N ) , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , R . getValue (


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Out ) . addReg ( DReg ) . addReg ( ToInsert ) . addImm ( Lane ) ; return Out


<s> if ( CPU == <STR_LIT> ) return <STR_LIT> ; if ( Subtarget -> hasV8Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isMClass ( ) && Subtarget -> hasThumb2DSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV4TOps ( ) ) return <STR_LIT> ; else return


<s> bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int flags ) { struct gcc_options func_options , func_options_set ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , <STR_LIT> ) == <NUM_LIT> ) return true ; tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , <NUM_LIT> , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == <NUM_LIT> ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl


<s> int Cost = <ISA_LIT>TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT>


<s> if ( * group_end ) can_issue_more = <NUM_LIT> ; if ( can_issue_more && ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; if ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 ) { nop = gen_group_ending_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more = <NUM_LIT> ; } else while ( can_issue_more > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } * group_end = true ; return <NUM_LIT> ; } if ( rs6000_sched_insert_nops < sched_finish_regroup_exact ) { int n_nops = rs6000_sched_insert_nops ; if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; if ( can_issue_more == issue_rate - <NUM_LIT> ) end = false ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } n_nops -- ; } can_issue_more ++ ; * group_end = ( end || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; if ( * group_end && end ) ( * group_count ) -- ; if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , *


<s> rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> , dl ,


<s> EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( <STR_LIT> , DL


<s> case MODE_SI : if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else return <STR_LIT> ; case MODE_HI : if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else return <STR_LIT> ; case MODE_DF : if ( TARGET_AVX && REG_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else return <STR_LIT> ; case MODE_SF : if ( TARGET_AVX && REG_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; else return <STR_LIT> ; case MODE_HF : case MODE_BF


<s> if ( Opc == <STR_LIT> ) return <STR_LIT> ; if ( Opc == <STR_LIT>


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> void \ read_only_private_data_section ( ) \ { \ if ( in_section != read_only_private_data ) \ { \ fprintf ( asm_out_file , <STR_LIT> , \ xcoff_private_data_section_name ) ; \ in_section =


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; unsigned DestReg ; auto RC = MRI . getRegClass ( SrcReg ) ; if ( Subtarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( Subtarget -> hasP8Vector ( ) && isVSFRCRegClass ( RC ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else { SrcReg = copyRegToRegClass ( & <STR_LIT> , SrcReg ) ; DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } updateValueMap ( I , DestReg


<s> SDValue SubVec = Src . getOperand ( <NUM_LIT> ) ; EVT SubVecVT = SubVec . getValueType ( ) ; if ( SubVec . getOpcode ( ) != <STR_LIT> || ! TLI . isTypeLegal ( SubVecVT ) || ! N -> getConstantOperandAPInt ( <NUM_LIT> ) . isMask ( SubVecVT . getVectorNumElements ( ) ) ) return SDValue ( ) ; EVT SetccVT = SubVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! TLI . isTypeLegal ( SetccVT ) || ! ( Subtarget . hasVLX ( ) || SetccVT . is512BitVector ( ) ) ) return SDValue ( ) ; if ( ! ( Subtarget . hasBWI ( ) || SetccVT . getScalarSizeInBits ( ) >= <NUM_LIT> ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( Src . getNumOperands ( ) , DAG . getConstant ( <NUM_LIT> , dl


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle (


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; B . addAttribute ( <STR_LIT> , <STR_LIT> ) ; F . removeFnAttrs ( B ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; } F . addFnAttrs ( B


<s> static bool loongarch_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return true


<s> return ! II -> getFastMathFlags ( ) . allowReassoc ( ) ; case <STR_LIT> : case <STR_LIT> : return ! II -> getFastMathFlags ( ) . noNaNs ( ) ; default : return false


<s> void addGPRMM16AsmRegMovePPairFirstOperands ( MCInst & Inst , unsigned N )


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : return earlySelectSHL ( I , MRI ) ; default : return


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI


<s> bool ValidateCalleeSavedStackSize = false ; ValidateCalleeSavedStackSize = HasCalleeSavedStackSize ; if ( ! HasCalleeSavedStackSize || ValidateCalleeSavedStackSize ) { assert ( MFI . isCalleeSavedInfoValid ( ) && <STR_LIT> ) ; if ( MFI . getCalleeSavedInfo ( ) . empty ( ) ) return <NUM_LIT> ; int64_t MinOffset = std :: numeric_limits < int64_t > :: max ( ) ; int64_t MaxOffset = std :: numeric_limits < int64_t > :: min ( ) ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; int64_t Offset = MFI . getObjectOffset ( FrameIdx ) ; int64_t ObjSize = MFI . getObjectSize ( FrameIdx ) ; MinOffset = std :: min < int64_t > ( Offset , MinOffset ) ; MaxOffset = std :: max < int64_t >


<s> return ( __m512i ) __builtin_ia32_cvtpd2qq512_mask ( ( __v8df ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8


<s> unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT ) && ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == MEM ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE (


<s> bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SPFI ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr


<s> return ( uint16x4_t ) __builtin_neon_vrsrau_nv4hi ( ( int16x4_t )


<s> case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case


<s> float64_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> void <ISA_LIT>MCInstLower :: LowerCPLOAD ( SmallVector < MCInst , <NUM_LIT> > & MCInsts ) { MCOperand GPReg = MCOperand :: CreateReg ( <STR_LIT> ) ; MCOperand T9Reg = MCOperand :: CreateReg ( <STR_LIT> ) ; MCOperand ZEROReg = MCOperand :: CreateReg ( <STR_LIT> ) ; StringRef SymName ( <STR_LIT> ) ; const MCSymbol * Sym = Ctx -> GetOrCreateSymbol ( SymName ) ; const MCSymbolRefExpr * MCSym ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , * Ctx ) ; MCOperand SymHi = MCOperand :: CreateExpr


<s> return create<ISA_LIT>MachObjectWriter ( OS , false , MachO :: CPU_TYPE_<ISA_LIT>


<s> MCELFStreamer :: EmitInstruction ( Inst , STI


<s> bool isSVEVectorList ( ) const { if ( Kind != k_VectorList ) return


<s> int regno , offset ; int mask = <NUM_LIT> ; HOST_WIDE_INT size ; rtx insn ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) mask |= <NUM_LIT> << regno ; insn = emit_insn ( gen_procedure_entry_mask ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; vax_add_reg_cfa_offset ( insn , <NUM_LIT>


<s> if ( frame_pointer_needed ) { delta = offsets -> soft_frame - offsets -> saved_args ; reg = THUMB_HARD_FRAME_POINTER_REGNUM ; } else { delta = offsets -> outgoing_args - offsets -> saved_args ; reg = SP_REGNUM ; } if ( TARGET_BACKTRACE ) delta -= <NUM_LIT> ; delta -= <NUM_LIT> ; addr = gen_rtx_REG ( SImode , reg ) ; if ( ( reg != SP_REGNUM && delta >= <NUM_LIT> ) || delta >= <NUM_LIT> ) { emit_insn ( gen_movsi ( scratch , GEN_INT ( delta ) ) ) ; emit_insn ( gen_addsi3 ( scratch , scratch , stack_pointer_rtx ) ) ; addr = scratch ; } else addr = plus_constant ( addr , delta ) ; emit_move_insn ( gen_frame_mem ( Pmode , addr ) , source ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNUM


<s> inline ShiftOpc getAM2ShiftOpc ( unsigned AM2Opc ) { return ( ShiftOpc ) ( ( AM2Opc >> <NUM_LIT> ) &


<s> return vabs_f64 ( __a ) <= vabs_f64 (


<s> return balanceFPOps ( ) ? std :: make_unique < A57ChainingConstraint >


<s> mips_start_ll_sc_sync_block ( ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; mips_end_ll_sc_sync_block ( )


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ; } SDLoc Dl ( N ) ; unsigned Opcode = N -> getOpcode


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI


<s> } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; OS << '[' ; Op . getExpr ( ) -> print ( OS , & MAI ) ; OS << ']'


<s> static bool shouldGuaranteeTCO ( CallingConv :: ID CC , bool GuaranteedTailCallOpt ) { return ( GuaranteedTailCallOpt && canGuaranteeTCO ( CC ) ) || CC == CallingConv

:: Tail || CC == CallingConv :: SwiftTail ;


<s> static SDValue combineZext ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const { return NumCycles ==


<s> assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( RegNum == <NUM_LIT> ) return - <NUM_LIT> ; Parser . Lex ( )


<s> SDLoc dl ( Op ) ; LLVMContext * Context = DAG . getContext ( ) ; static const uint32_t CV0 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Constant * C0 = ConstantDataVector :: get ( * Context , CV0 ) ; auto PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , PtrVT , <NUM_LIT> ) ; SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue Shuffle = DAG . getVectorShuffle ( <STR_LIT> , dl , Sub , Sub , { <NUM_LIT>


<s> assert ( ( ( unsigned long ) __P & <NUM_LIT> ) == <NUM_LIT> ) ; vec_st ( ( __v16qu ) __A , <NUM_LIT>


<s> bool CmpOnly = ! ST . hasArithmeticBccFusion ( ) ; if ( isArithmeticBccPair ( FirstMI , SecondMI , CmpOnly ) ) return true ; } if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseCryptoEOR ( ) && isCryptoEORPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAdrpAdd ( ) && isAdrpAddPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAddress ( ) && isAddressLdStPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseCCSelect ( ) && isCCSelectPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseArithmeticLogic ( ) && isArithmeticLogicPair ( FirstMI , SecondMI


<s> bool onOffset ( const MCExpr * Val , SMLoc OffsetLoc , StringRef ID , const InlineAsmIdentifierInfo & IDInfo , bool ParsingInlineAsm , StringRef & ErrMsg ) { PrevState = State ; switch ( State ) { default : ErrMsg = <STR_LIT> ; return true ; case IES_PLUS : case IES_INIT : case IES_LBRAC : if ( setSymRef ( Val , ID , ErrMsg ) ) return true ; OffsetOperator =


__artificial__ ) ) _mm_mfence ( void ) {


<s> if ( ShuffleMask [ Start + i ] >= <NUM_LIT> ) { if ( ShuffleMask [ Start + i ] % Length != i ) return - <NUM_LIT> ; MovIdx = ShuffleMask [ Start + i ] / Length ; break ; } } if ( MovIdx == - <NUM_LIT> ) return - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Length ; i ++ ) { if ( ShuffleMask [ Start + i ] >= <NUM_LIT> && ( ShuffleMask [ Start + i ] / Length != MovIdx || ShuffleMask [ Start + i ] % Length != i ) ) return - <NUM_LIT> ; } return MovIdx ; } ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) { int Elt = getMovIdx ( ShuffleMask , Part * QuarterSize , QuarterSize ) ; if ( Elt != - <NUM_LIT> ) { SDValue Input = Op -> getOperand ( <NUM_LIT> ) ; if ( Elt >= <NUM_LIT> ) { Input = Op -> getOperand ( <NUM_LIT> ) ; Elt -= <NUM_LIT> ; } SDValue BitCast = DAG . getBitcast ( <STR_LIT> , Input ) ; Parts [ Part ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BitCast , DAG . getConstant ( Elt , dl , <STR_LIT> ) ) ; } } if ( ! Parts [ <NUM_LIT> ] && ! Parts [ <NUM_LIT> ] && ! Parts [ <NUM_LIT> ] && ! Parts [ <NUM_LIT> ] ) return SDValue ( ) ; if ( ! Parts [ <NUM_LIT> ] || ! Parts [ <NUM_LIT> ] || ! Parts [ <NUM_LIT> ] || ! Parts [ <NUM_LIT> ] ) { SmallVector < int , <NUM_LIT> > NewShuffleMask ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) for ( int i = <NUM_LIT> ; i < QuarterSize ; i ++ ) NewShuffleMask . push_back ( Parts [ Part ] ? - <NUM_LIT> : ShuffleMask [ Part * QuarterSize + i ] ) ; SDValue NewShuffle = DAG . getVectorShuffle ( VT , dl , Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , NewShuffleMask ) ; SDValue BitCast = DAG . getBitcast ( <STR_LIT> , NewShuffle ) ; for ( int Part = <NUM_LIT> ; Part < <NUM_LIT> ; ++ Part ) if ( ! Parts [ Part ] ) Parts [ Part ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BitCast , DAG . getConstant ( Part , dl , <STR_LIT> ) ) ; } SDValue NewVec = DAG . getNode ( <STR_LIT> , dl


<s> if ( * bufptr == '_' ) found = bufptr ; while ( * bufptr && ! ISSPACE ( * bufptr ) ) ++ bufptr ; if ( * bufptr ) * bufptr = <NUM_LIT> ; if ( found ) * wrappers -> find_slot


<s> return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset ,


<s> if ( ! BVN -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget -> isLittle ( ) ) ) return false ; auto IsInlineConstant = [ ] ( const APInt & Imm ) { return Imm . isIntN ( <NUM_LIT> ) ; } ; if ( IsInlineConstant ( SplatValue ) ) return false ; APInt NegSplatValue = <NUM_LIT> - SplatValue ; if ( ! IsInlineConstant ( NegSplatValue ) ) return false ; SDLoc DL ( Node ) ; SDValue NegC = CurDAG -> FoldConstantArithmetic ( <STR_LIT> , DL , VT , { CurDAG ->

getConstant ( <NUM_LIT> , DL , VT ) , C } ) ;


<s> if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) && ! VT . is512BitVector ( ) ) return SDValue ( ) ; SDNode * N1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; APInt SplatVal ; if ( ! <STR_LIT> ( N1 , SplatVal ) || ! SplatVal . isOneValue ( ) ) return SDValue ( ) ; SDValue AllOnesVec = getOnesVector ( VT , DAG , SDLoc ( N ) ) ; unsigned NewOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpcode , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) ,


<s> const char * cond_code ; bool align_p = NDS32_ALIGN_P ( ) ; const char * align = align_p ? <STR_LIT> : <STR_LIT> ; if ( long_jump_p ) { int inverse_code = nds32_inverse_cond_code ( code ) ; cond_code = nds32_cond_code_str ( inverse_code ) ; if ( ta_implied_p && TARGET_16_BIT ) { snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , cond_code , suffix , align ) ; } else { snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , cond_code , suffix , align ) ; } } else { cond_code = nds32_cond_code_str (


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { bool is64 = getPointerSize ( )


<s> MCStreamer & OS = getStreamer ( ) ; const MCObjectFileInfo & OFI = * Context . getObjectFileInfo ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; MCSectionData & TextSectionData = MCA . getOrCreateSectionData ( * OFI . getTextSection ( ) ) ; MCSectionData & DataSectionData = MCA . getOrCreateSectionData ( * OFI . getDataSection ( ) ) ; MCSectionData & BSSSectionData = MCA . getOrCreateSectionData ( * OFI . getBSSSection ( ) ) ; TextSectionData . setAlignment ( std :: max ( <NUM_LIT> , TextSectionData . getAlignment ( ) ) ) ; DataSectionData . setAlignment ( std :: max ( <NUM_LIT> , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( <NUM_LIT> , BSSSectionData . getAlignment ( ) ) ) ; if ( T . isArch64Bit ( ) && ( Features & <STR_LIT> ) ) { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) , <NUM_LIT> , <STR_LIT> ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( <NUM_LIT> ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) , <NUM_LIT> , <STR_LIT> ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( Features & <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } emit<ISA_LIT>AbiFlags (


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * F )


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > Remove ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { LoLoop . Start , LoLoop . Dec , LoLoop . End , LoLoop . InsertPt } ; SmallVector < MachineInstr * , <NUM_LIT> > Chain = { Def } ; while ( ! Chain . empty ( ) ) { MachineInstr * MI = Chain . back ( ) ; Chain . pop_back ( ) ; MachineInstr * IT = nullptr ; if ( TII -> getPredicate ( * MI ) != <STR_LIT> ) { auto PrevMI = std :: prev ( MI -> getIterator ( ) ) ; auto NextMI = std :: next ( MI -> getIterator ( ) ) ; if ( PrevMI -> getOpcode ( ) == <STR_LIT> && TII -> getPredicate ( * NextMI ) == <STR_LIT> ) IT = & * PrevMI ; else return ; } if ( RDA -> isSafeToRemove ( MI , Remove , Ignore ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse (

) || MO . getReg ( ) == <NUM_LIT> ) continue ;


<s> case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineGatherScatter ( N , DAG ) ; case <STR_LIT> : return combineLockSub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTestM ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorCompare ( N , DAG , Subtarget ) ; } return SDValue


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else BuildMI ( MBB , I , DL , MCID , DestReg


<s> return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && aarch64_bitmask_imm ( INTVAL ( elt ) ,


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new NaCl<ISA_LIT>_32AsmBackend ( T , OSABI , CPU ) ; return new ELF<ISA_LIT>_32AsmBackend ( T , OSABI


<s> label = gen_label_rtx ( ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , ins ) , GEN_INT ( <NUM_LIT> ) , NE , NULL_RTX , SImode , <NUM_LIT> ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , plus_constant ( ins , <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) , NE , NULL_RTX , SImode , <NUM_LIT> ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , plus_constant ( ins , <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) , NE , NULL_RTX , SImode , <NUM_LIT> ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , plus_constant ( ins , <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) , NE , NULL_RTX , SImode , <NUM_LIT> ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_move_insn ( saved_rp , gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( frameaddr , - <NUM_LIT> ) ) ) ) ; emit_label ( label ) ; return


<s> if ( MI == MBB . end ( ) || EndbrOpcode != MI -> getOpcode ( ) ) { BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , TII -> get ( EndbrOpcode ) ) ; NumEndBranchAdded ++ ; return true ; } return false


<s> unsigned Register = GPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register


<s> static DecodeStatus DecodeGPRMM16ZeroRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldrex = <STR_LIT> ( M , Int ,


<s> <STR_LIT> VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return ; } case MachineOperand :: MO_Immediate : if ( AsmVariant == <NUM_LIT> ) O << '$' ; O << MO . getImm


<s> EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeFld , Get<ISA_LIT>RegNum ( ModRMReg ) ) , CurByte ,


<s> inline SDValue getI32Imm ( unsigned Imm , SDLoc DL ) { return CurDAG -> getTargetConstant ( Imm , DL


<s> unsigned NumBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SM . recordStackMap ( MI


<s> if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t


<s> llvm_unreachable ( <STR_LIT> ) ; } if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) { OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( i + <NUM_LIT> < RVLocs . size ( ) && RVLocs [ i + <NUM_LIT> ] . getLocReg ( ) == VA . getLocReg ( ) ) { SDValue NV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVals [ i + <NUM_LIT> ] ) ; OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , NV ) ; ++ i ; } } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVal , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] =


<s> return GET_CODE ( pat ) == SET && arith_reg_dest ( XEXP ( pat , <NUM_LIT> ) , SImode ) && negt_reg_operand ( XEXP ( pat ,

<NUM_LIT> ) , VOIDmode ) ? XEXP ( pat , <NUM_LIT> ) : NULL ;


<s> __builtin_ia32_aand64 ( ( long long * )


<s> int ImmsLow = LSBLow + Width - <NUM_LIT> ; int ImmsHigh = LSBHigh + Width - <NUM_LIT> ; MachineInstr * ExtDestMI = MergeForward ? MergeMI : I ; if ( ( ExtDestMI == Rt2MI ) == Subtarget -> isLittleEndian ( ) ) { BitExtMI1 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getBitExtrOpcode ( Rt2MI ) ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( LSBHigh ) . addImm ( ImmsHigh ) ; if ( RtMI -> getOpcode ( ) == getMatchingNonSExtOpcode ( RtMI -> getOpcode ( ) ) ) { BitExtMI2 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( ImmsLow ) ; } else { BitExtMI2 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getBitExtrOpcode ( RtMI ) ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( LSBLow ) . addImm ( ImmsLow ) ; } } else { if ( RtMI -> getOpcode ( ) == getMatchingNonSExtOpcode ( RtMI -> getOpcode ( ) ) ) { BitExtMI1 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( ImmsLow ) ; } else { BitExtMI1 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getBitExtrOpcode ( RtMI ) ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( LSBLow ) . addImm ( ImmsLow ) ; } BitExtMI2 = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getBitExtrOpcode ( Rt2MI ) ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addReg ( getLdStRegOp ( RtNewDest ) . getReg ( ) ) . addImm ( LSBHigh ) . addImm ( ImmsHigh ) ; } ( void ) BitExtMI1 ; ( void ) BitExtMI2 ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( BitExtMI1 ) -> print


<s> unsigned Offset = <NUM_LIT> ; for ( MachineBasicBlock & MBB : * MF ) { const Align Alignment = MBB . getAlignment ( ) ; unsigned AlignedOffset ; if ( Alignment == Align ( <NUM_LIT> ) ) AlignedOffset = Offset ; else AlignedOffset = alignTo ( Offset , Alignment ) ; BlockInfo [ MBB . getNumber ( ) ] = AlignedOffset ; auto BlockSize = computeBlockSize ( MBB ) ; if ( ! BlockSize ) return false ; Offset = AlignedOffset + *


<s> if ( ! Subtarget -> hasFPARMv8 ( ) ) return <STR_LIT> ; if ( ConstraintVT . isFloatingPoint ( ) ) return <STR_LIT> ; if ( ConstraintVT . isVector ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT

. getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ;


<s> Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; } } } if ( OffReg . getOpcode ( ) == <STR_LIT> && N . hasOneUse ( ) ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( OffReg , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { replaceDAGValue ( OffReg . getOperand ( <NUM_LIT> ) , NewMulConst ) ; ShAmt = PowerOfTwo ; } } ShImm = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( N


<s> switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_VANILLA : Type = A -> isExternal ( ) ? ( unsigned ) MachO :: <ISA_LIT>_RELOC_SECTDIFF : ( unsigned ) MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_HI16 : dbgs ( ) << <STR_LIT> ; Type = MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_HA16 : Type = MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_LO16 : Type = MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_LO14 : Type = MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF ; break ; default : dbgs ( ) << <STR_LIT> ; break ; } Value2 = Writer -> getSymbolAddress ( * SB , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; return ; } uint32_t OtherHalf = <NUM_LIT> ; switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_SECTDIFF : case MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF : break ; case MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF : if ( FixedValue & <NUM_LIT> ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> ) ) ; case MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF : OtherHalf = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; FixedValue &= <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF : OtherHalf = FixedValue & <NUM_LIT> ; FixedValue = ( ( FixedValue >> <NUM_LIT> ) + ( ( FixedValue


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & JmpMBB = * JmpI . getParent ( ) ; insertTest ( JmpMBB , JmpI . getIterator ( ) , JmpI . getDebugLoc ( ) , CondReg ) ; JmpI . getOperand ( <NUM_LIT> ) . setImm ( Inverted ? <STR_LIT> :


<s> unsigned Reg = QFPRegDecoderTable [ RegNo ] ; if ( Reg == ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return false ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal


<s> return MBB . computeRegisterLiveness ( & RI , <STR_LIT> , I , <NUM_LIT> ) ==


<s> bool <ISA_LIT>LegalizerInfo :: legalizeIntrinsic ( MachineInstr & MI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case


<s> assert ( NumV1Elements > <NUM_LIT> && <STR_LIT> ) ; if ( NumV2Elements == <NUM_LIT> ) return false ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : Mask . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) return true ; if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) SumV2Indices += i ; else if ( Mask [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) return true ; if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( Mask [ i ] >= <NUM_LIT> ) NumV1OddIndices += i % <NUM_LIT> ; if ( NumV2OddIndices < NumV1OddIndices ) return true ; } } } return false


<s> Offset /= OffsetStride ; } return Offset <= <NUM_LIT> && Offset


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; SDValue res ; SDNodeTreeBuilder b ( Op , & DAG ) ; MVT VectorEleType = VT . getVectorElementType ( ) ; if ( VectorEleType == <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) { res = b . AND ( getFullRegister ( A , DAG ) , b . NOT ( getFullRegister ( B , DAG ) ) ) ; } else if ( VectorEleType == <STR_LIT> && Op . getOpcode ( ) == <STR_LIT> ) { return A


<s> vec_ushort8 bv ; bv = vec_splat ( ( vec_ushort8 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ; mask = ( vec_ushort8 ) vec_sra ( vec_sl ( bv , vec_splat_u16 ( <NUM_LIT> ) ) , vec_splat_u16 ( <NUM_LIT> ) ) ; return ( ( qword ) ( vec_andc ( vec_sl ( ( vec_ushort8 ) ( a ) , bv ) , mask


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; if ( CallerCC == CallingConv :: C && <ISA_LIT>RegisterInfo :: hasSVEArgsOrReturn ( & MF ) ) CallerCC = CallingConv :: <ISA_LIT>_SVE_VectorCall ; bool CCMatch = CallerCC == CalleeCC ; if ( CallerCC == CallingConv :: Win64 && ! Subtarget -> isTargetWindows ( ) && CalleeCC != CallingConv :: Win64 ) return false ; for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) { if ( i -> hasByValAttr ( ) ) return false ; if ( i -> hasInRegAttr ( ) ) return false ; } if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return canGuaranteeTCO ( CalleeCC ) && CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset ; if ( ! ArgFlags . isSRet ( ) ) Offset = State . AllocateStack


<s> if ( ( OrigCallInst >> <NUM_LIT> ) == <NUM_LIT> ) { intptr_t Offset = ( ( intptr_t ) Target - ( intptr_t ) OrigCallAddr ) >> <NUM_LIT> ; if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset < ( <NUM_LIT> << <NUM_LIT> ) ) { OrigCallInst &= ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> ; OrigCallInst |= ( Offset & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) << <NUM_LIT> ; * OrigCallAddr = OrigCallInst ; } } if ( ( * StubCallAddr >> <NUM_LIT> ) == <NUM_LIT> ) StubCallAddr -= <NUM_LIT> ; else { assert ( ( * StubCallAddr >> <NUM_LIT> ) == <NUM_LIT> && <STR_LIT>


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMVEVPTOptimisationsPass ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : case TLSModel ::


<s> int pos = <NUM_LIT> ; int i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_or_fixed_reg_p ( i ) ) reg_alloc_order [ pos ++ ] = i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_or_fixed_reg_p ( i ) ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_dst ) ; i ++ , d ++ ) if ( d -> code == fcode ) { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; op2 = expand_normal ( arg2 ) ; mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; * expandedp = true ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> , d -> name ) ; return const0_rtx ; } if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( Pmode , op0 ) ; if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 , op2 ) ; if ( pat != <NUM_LIT> ) emit_insn ( pat ) ; return NULL_RTX


<s> if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && SelectMsub ( N , & DAG ) ) return


<s> MIB . addReg ( <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg (


<s> assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg1 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI .

getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> static tree ix86_make_bounds_constant ( HOST_WIDE_INT lb , HOST_WIDE_INT ub ) { tree low = lb ? build_minus_one_cst ( pointer_sized_int_node ) : build_zero_cst ( pointer_sized_int_node ) ; tree high = ub ? build_zero_cst ( pointer_sized_int_node ) : build_minus_one_cst ( pointer_sized_int_node ) ; gcc_assert ( ( lb == <NUM_LIT> && ub == - <NUM_LIT> ) || ( lb == - <NUM_LIT> && ub == <NUM_LIT> ) ) ; return build_complex ( NULL , low , high


<s> return ( __m256d ) __builtin_ia32_broadcastf64x2_256_mask ( ( __v2df ) __A , ( __v4df ) _mm256_undefined_pd ( ) , ( __mmask8 )


<s> static enum calling_abi ix86_function_abi ( const_tree fndecl ) { if ( ! fndecl ) return


<s> void <ISA_LIT>InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> return VT . isFixedLengthVector ( ) || VT . getSizeInBits ( ) . getKnownMinSize ( )


<s> if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitGPRel32Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer


<s> return ( __m128i ) __builtin_ia32_movdqa64_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 )


<s> static SDValue getUnpackh ( SelectionDAG & DAG , const SDLoc & dl , EVT VT , SDValue V1 , SDValue V2 ) { SmallVector < int , <NUM_LIT> > Mask ; createUnpackShuffleMask ( VT , Mask ,


<s> static DecodeStatus DecodeThumbBLXOffset ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned S = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned J1 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned J2 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand ::


<s> if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP (


<s> return ( vector unsigned int ) __builtin_altivec_vmrglw ( ( vector signed int


<s> bool MandarinPassConfig :: addInstSelector ( ) { addPass ( createMandarinISelDag ( getMandarinTargetMachine ( ) ) ) ; return


<s> const Function & F = * I -> getParent ( ) -> getParent ( ) ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( RV ) ) { CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( CI , <STR_LIT> , VA . getLocInfo ( ) != CCValAssign :: ZExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign ::


<s> is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_RELEASE ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_ACQUIRE ) ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , getEffectiveRelocModel ( RM ) , JIT ) , OL ) , TLOF ( llvm :: make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlign ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlign ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand


<s> unsigned getScratchReg ( ) { for ( int i = NumFPRegs - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( ! isLive ( i ) ) return i ; llvm_unreachable ( <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveReq ( StringRef Name , SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; SMLoc SRegLoc = getLoc ( ) ; unsigned RegNum = tryParseRegister ( ) ; bool IsVector = false ; if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { StringRef Kind ; RegNum = tryMatchVectorRegister ( Kind , false ) ; if ( ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; IsVector = true ; } if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) return Error ( SRegLoc , <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; auto pair = std :: make_pair ( IsVector , RegNum


<s> if ( ! VT . is128BitVector ( ) || N -> getNumOperands ( ) != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; ReplaceNode ( N , createDRegPairNode ( VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand (


<s> return ( uint32x4_t ) __builtin_aarch64_usubwv4hi ( ( int32x4_t )


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_failure_persistent ( void * const


<s> if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT>


<s> const TargetRegisterClass * RC = static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & <STR_LIT> : & <STR_LIT> ; return GlobalBaseReg = MF . getRegInfo ( )


<s> return ( __m64 ) __builtin_arm_wabsh ( ( __v4hi


<s> SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , RegSeq -> getValueType ( <NUM_LIT> ) , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue


<s> const MVT FloatTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : FloatTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT LongTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : LongTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> ,


<s> if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( is_contained ( WidenedMask , SM_SentinelZero ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; if ( canonicalizeShuffleMaskWithCommute ( Mask ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } if ( VT . is128BitVector ( ) ) return lower128BitShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ; if ( VT . is256BitVector ( ) ) return lower256BitShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ; if ( VT . is512BitVector ( ) ) return lower512BitShuffle ( DL , Mask , VT , V1


<s> if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> || ( ( IntWidth == <NUM_LIT>

|| IntWidth == <NUM_LIT> ) && ST -> hasBWI ( ) ) ;


<s> getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case


<s> static DecodeStatus DecodeMVE_MEM_3_pre ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeMVE_MEM_pre ( Inst , Val , Address , Decoder , fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) , DecodeMQPRRegisterClass ,


<s> static DecodeStatus decodeBDAddr64Disp12Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const MCDisassembler * Decoder ) { return decodeBDAddr12Operand ( Inst , Field , <STR_LIT>


<s> if ( insn_entry [ i ] . is_load ) { if ( GET_CODE ( body ) == SET ) { * special = SH_NOSWAP_LD ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC ) { * special =


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) || spillsCR ( MF ) || hasNonRISpills ( MF ) || ( hasSpills ( MF ) && ! isInt < <NUM_LIT> > ( StackSize ) ) ) { const TargetRegisterClass & GPRC = <STR_LIT> ; const TargetRegisterClass & G8RC = <STR_LIT> ; const TargetRegisterClass & RC = Subtarget . is<ISA_LIT>64 ( ) ? G8RC : GPRC ; const TargetRegisterInfo & TRI = * Subtarget . getRegisterInfo


<s> assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxLogAlign ; ++ a ) if

( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ;


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { unsigned NumBytes = <NUM_LIT> ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) { return ; } unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes


<s> inmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ <NUM_LIT> ] ; in = force_reg ( inmode , operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , <NUM_LIT> , neglab ) ; expand_float ( out , in , <NUM_LIT> ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , <NUM_LIT> ,


<s> i386_pe_declare_function_type ( f , name , TREE_PUBLIC ( decl ) ) ; if ( decl != NULL_TREE ) switch_to_section ( function_section ( decl ) ) ; ASM_OUTPUT_FUNCTION_LABEL ( f , name , decl


<s> if ( CC != CallingConv :: C && CC != CallingConv :: <ISA_LIT>_StdCall ) return ; unsigned ParamRegs = <NUM_LIT> ; if ( auto * M = MF -> getFunction ( ) -> getParent ( ) ) ParamRegs = M -> getNumberRegisterParameters ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < Args . size ( ) ; Idx ++ ) { Type * T = Args [ Idx ]


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , LocVT , LocInfo ) ) ; return true


<s> static __inline double si_to_double ( qword q ) { union { qword q ; double d [ <NUM_LIT> ] ; } x ; x . q = q


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e

; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; getStreamer ( ) . EmitIntValue


<s> const unsigned AddrReg = constrainOperandRegClass ( II , getRegForValue ( I -> getPointerOperand ( ) ) , II . getNumDefs ( ) ) ; const unsigned DesiredReg = constrainOperandRegClass ( II , getRegForValue ( I -> getCompareOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const unsigned NewReg = constrainOperandRegClass ( II , getRegForValue ( I -> getNewValOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const unsigned ResultReg1 = createResultReg ( ResRC ) ; const unsigned ResultReg2 = createResultReg ( & <STR_LIT> ) ; const unsigned ScratchReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addDef ( ResultReg1 ) . addDef ( ScratchReg ) . addUse ( AddrReg ) . addUse ( DesiredReg ) . addUse ( NewReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) ) . addDef ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) . addUse ( ResultReg1 ) . addUse ( DesiredReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResultReg2 ) . addUse ( <STR_LIT>

) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ;


<s> bool isFixed = MFI -> isFixedObjectIndex ( FI ) ; FrameReg = <STR_LIT> ; Offset += SPAdj ; if ( AFI -> isGPRCalleeSavedArea1Frame ( FI ) ) return Offset - AFI -> getGPRCalleeSavedArea1Offset ( ) ; else if ( AFI -> isGPRCalleeSavedArea2Frame ( FI ) ) return Offset - AFI -> getGPRCalleeSavedArea2Offset ( ) ; else if ( AFI -> isDPRCalleeSavedAreaFrame ( FI ) ) return Offset - AFI -> getDPRCalleeSavedAreaOffset ( ) ; bool hasMovingSP = MFI -> hasVarSizedObjects ( ) || ! hasReservedCallFrame ( MF ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( isFixed ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; Offset = FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getBaseRegister ( ) ; } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT>

) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ;


<s> if ( val & <NUM_LIT> ) val = ~ val ; first_one = val & - val ; tmp = val & ( val + first_one ) ; if ( tmp == <NUM_LIT> ) return true ; next_one = tmp & - tmp ; bits = clz_hwi ( first_one ) - clz_hwi ( next_one ) ; mask = val ^ tmp ; if ( ( mask >> bits ) != <NUM_LIT> || bits != ( bits & - bits ) ) return false ; return val == mask * bitmask_imm_mul [ __builtin_clz ( bits ) -


<s> } else { Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , getTargetNode ( N , PtrVT , DAG , MO_GOTOFF | <STR_LIT> ) , getTargetNode ( N , PtrVT , DAG , MO_GOTOFF | <STR_LIT> | MO_NC ) , getTargetNode ( N , PtrVT , DAG , MO_GOTOFF | <STR_LIT> | MO_NC ) , getTargetNode ( N , PtrVT , DAG , MO_GOTOFF | <STR_LIT> | MO_NC ) ) ; } return DAG . getNode ( <STR_LIT> , DL , PtrVT , GOTAddr , Offset ) ; } else if ( pagerandoBinTarget ) { SDValue POTOffset = DAG . getTargetGlobalAddress ( F , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue BaseAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Chain , POTValue , POTOffset ) ; SDValue Offset = DAG . getTargetGlobalAddress ( F , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , BaseAddr , Offset ) ; } else { SDValue GOTAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Chain , POTValue , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = getTargetNode ( N , PtrVT , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , PtrVT , DAG , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; SDValue TargetPCRel = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; Hi = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; Lo = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; ADRP = DAG . getNode ( <STR_LIT> ,


<s> assert ( ( N0 . getValueType ( ) == <STR_LIT> || N0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) return SDValue ( ) ; int NumMaskElts = ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ; if ( ! ResVT . isVector ( ) || NumMaskElts == <NUM_LIT> ) return SDValue ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , NumMaskElts ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; if ( CCVT . getSizeInBits ( ) != ResVT . getSizeInBits ( ) ) return SDValue ( ) ; assert ( DCI . isBeforeLegalize ( ) || DAG . getTargetLoweringInfo ( ) . isTypeLegal (


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this

) , JITInfo ( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode


<s> SMLoc FPUNameLoc = getTok ( ) . getLoc ( ) ; StringRef FPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = StringSwitch < unsigned > ( FPU ) . Default ( <STR_LIT> ) ; if ( ID == <STR_LIT> ) { Error ( FPUNameLoc , <STR_LIT> )


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2Base ( ) || ! Subtarget -> hasFP64 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; Register Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; Register Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; updateValueMap ( I , Result ) ; return true


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdpkru_u32 ( void ) { return __builtin_ia32_rdpkru


<s> if ( Subtarget -> hasNEON ( ) ) { if ( VT == <STR_LIT> ) return <STR_LIT> ; else if ( VT == <STR_LIT> ) return


<s> } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first

, RegsToPass [ i ] . second . getValueType ( ) ) ) ;


<s> static const MCInstrDesc & getInstDesc ( unsigned Opcode ) { return <ISA_LIT>Insts [ Opcode


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> bool hasSSE42orAVX ( ) const { return hasSSE42 ( ) || hasAVX (


<s> BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } } return true


<s> void addPKHASRImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> if ( Subtarget . hasSPE ( ) && VT == <STR_LIT> ) return <NUM_LIT> ; return <ISA_LIT>TargetLowering :: getNumRegisters ( Context


<s> return static_cast < <ISA_LIT>DCBasicBlock & > ( DCInstruction ::


<s> <ISA_LIT>GenInstrInfo :: MachineOutlinerInfo <ISA_LIT>InstrInfo :: getOutlininingCandidateInfo ( std :: vector < std :: pair <

MachineBasicBlock :: iterator , MachineBasicBlock :: iterator >> & RepeatedSequenceLocs ) const {


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( IndexVT == <STR_LIT> ) return SDValue ( ) ; MVT OrigVT = VT ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! IndexVT . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; PassThru = ExtendToType ( PassThru , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N ->


<s> B . setInstrAndDebugLoc ( MI ) ; auto Lane = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , MatchInfo . second ) ; B . buildInstr ( MatchInfo . first , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Lane } ) ; MI . eraseFromParent ( ) ; return true


<s> SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnes ( ) && CFVal -> isZero ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( CTVal -> isZero ( ) && CFVal -> isAllOnes ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; FVal = Other ; TVal = DAG . getNode ( <STR_LIT> , dl , Other . getValueType ( ) , Other , DAG . getConstant ( - <NUM_LIT> , dl ,


<s> assert ( ( Kind == k_Memory ) && <STR_LIT> ) ; return Mem .


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg


<s> __a = ( __vector signed char ) vec_splats ( __m1 ) ; __b = ( __vector signed char ) vec_splats ( __m2 ) ; __c = vec_subs ( __a , __b ) ; return ( __m64 ) ( ( __vector long long ) __c