<s> BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } ZERO = <STR_LIT> ; MOVE = <STR_LIT> ; } else { LL = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; MOVE = <STR_LIT> ; } unsigned Dest = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB . getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB . getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( MachineBasicBlock :: iterator ( I ) ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loop1MBB , BranchProbability :: getOne ( ) ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop1MBB -> normalizeSuccProbs ( ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB )


<s> FunctionPass * llvm :: create<ISA_LIT>VSXCopyPass ( )


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Size ; Entry . Ty = Entry . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; if ( NeedsAlign ) { Entry . Node = DAG . getConstant ( ~ ( Alignment -> value ( ) - <NUM_LIT> ) , DL , VT ) ; Entry . Ty = Entry . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; } Type * RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; EVT PtrVT = Op . getValueType ( ) ; SDValue Callee ; if ( NeedsAlign ) { Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <NUM_LIT> ) ; } else { Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <NUM_LIT> ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: PreserveAll , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( true ) ; std :: pair < SDValue , SDValue > pair = LowerCallTo ( CLI ) ; Chain = pair . second ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , VT , Chain ) ; if ( NeedsAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( ( Alignment -> value ( ) - <NUM_LIT> ) , DL , VT ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( ~ ( Alignment -> value ( ) - <NUM_LIT> ) , DL , VT ) ) ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , SDValue ( ) , DL ) ; SDValue Ops [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( Ops ,


<s> MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return true ; unsigned SecondLastOpc = <NUM_LIT> ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! getAnalyzableBrOpc ( SecondLastOpc ) ) return true ; } if ( ! SecondLastOpc || ( SecondLastOpc != <STR_LIT> && SecondLastOpc != <STR_LIT> && SecondLastOpc != <STR_LIT> ) ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst ->


<s> Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI =


<s> const <ISA_LIT>RegisterInfo * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( ! RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getStackRegister ( ) ; return getFrameIndexOffsetFromSP ( MF ,


<s> void Initialize ( const MachineFunction & MF ,


<s> BuildMI ( MBB , MIB . getInstr ( ) , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MIB -> setDesc ( TII . get ( MinusOne ? <STR_LIT> : <STR_LIT> ) ) ; MIB . addReg ( Reg


<s> bool Changed = false ; const <ISA_LIT>InstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) ==


<s> void insertRecoveryBlock ( MachineFunction & MF ) { DebugLoc DL3 = MF . begin ( ) -> begin ( ) -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( auto & reg : functionCallArgs ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( reg ) ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( getSlaveReg1 ( reg ) ) ; tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( ) , cmpInst ) ; tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( )


<s> RepMovsRepeats ( const uint64_t SizeVal , const MVT & AVT ) { const unsigned UBytes = AVT . getSizeInBits ( )


<s> AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; O <<


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> )


<s> bool IsZeroV1 = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsZeroV2 = <STR_LIT> ( V2 . getNode ( ) ) ; if ( IsZeroV1 && IsZeroV2 ) return getZeroVector ( ResVT , Subtarget , DAG , dl ) ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG . getUNDEF ( ResVT ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems / <NUM_LIT> , dl , <STR_LIT> ) ; V2 = DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , V2 , ZeroIdx ) ; V2 = DAG . getNode ( <STR_LIT> , dl , ResVT , V2 , ShiftBits ) ; if ( IsZeroV1 ) return V2 ; V1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Undef , V1 , ZeroIdx ) ; V1 = DAG . getNode ( <STR_LIT> , dl , ResVT , V1 , ShiftBits ) ; V1 = DAG . getNode ( <STR_LIT> , dl , ResVT


<s> static __inline qword si_fms ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , vec_sub ( ( ( vec_float4 ) { <NUM_LIT> } ) , ( vec_float4 )


<s> { MO_PLT , <STR_LIT> } , { MO_PIC_FLAG , <STR_LIT> } , { MO_PCREL_FLAG , <STR_LIT> } , { MO_GOT_FLAG , <STR_LIT> } , { MO_PCREL_OPT_FLAG , <STR_LIT> } , { MO_TLSGD_FLAG , <STR_LIT> } , { MO_TLSLD_FLAG , <STR_LIT> } , { MO_TPREL_FLAG ,

<STR_LIT> } , { MO_TLSGDM_FLAG , <STR_LIT> } , { MO_GOT_TLSGD_PCREL_FLAG , <STR_LIT> } , { MO_GOT_TLSLD_PCREL_FLAG , <STR_LIT> } , { MO_GOT_TPREL_PCREL_FLAG , <STR_LIT> } } ;


<s> return isInt < <NUM_LIT> > ( CN . getSExtValue ( ) ) &&

( ( CN . getSExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> const char * getPassName ( ) const override { return


<s> llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator End = std :: end ( ReduceTable ) ; std :: pair < llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator , llvm :: SmallVector < ReduceEntry

, <NUM_LIT> > :: const_iterator > Range = std :: equal_range ( Start , End , Opcode ) ;


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , floor_log2 ( nds32_isr_vector_size ) , false ) ; fprintf ( asm_out_file , <STR_LIT> , reset_handler_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , <NUM_LIT> , true ) ; fprintf ( asm_out_file , <STR_LIT> , ( strlen ( nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) == <NUM_LIT> ) ? <STR_LIT> : nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name )


<s> if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; return ! Subtarget ->


<s> SDValue CCVal = N -> getOperand ( <NUM_LIT> ) ; SDValue Cmp = N -> getOperand ( <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( CCVal ) && <STR_LIT> ) ; unsigned CC = cast < ConstantSDNode > ( CCVal ) -> getZExtValue ( ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; unsigned CmpOpc = Cmp . getOpcode ( ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) || ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT>


<s> const InlineAsmIdentifierInfo & getIdentifierInfo ( )


<s> assert ( OrigPHI -> getNumIncomingValues ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( Instruction & I : * OrigPHI -> getParent ( ) ) { auto PHI = dyn_cast < PHINode > ( & I ) ; if ( ! PHI ) continue ; if ( PHI == OrigPHI ) continue ; if ( PHI -> getNumIncomingValues ( ) != <NUM_LIT> ) continue ; int Idx = PHI -> getBasicBlockIndex ( EntryBB ) ; if ( Idx < <NUM_LIT> ) continue ; if ( ! match ( PHI -> getIncomingValue ( Idx ) , m_Zero ( ) ) ) continue ; Idx = PHI -> getBasicBlockIndex ( BackEdgeBB ) ; if ( Idx < <NUM_LIT> ) continue ; Value * EC ; if ( ! match ( PHI -> getIncomingValue ( Idx ) , m_Add ( m_Specific ( PHI ) , m_ElementCount ( m_Value ( EC )


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; } return


<s> callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_Ghc_SaveList ; if ( Is64Bit )


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( getTheARM64Target


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * LSBExpr ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( LSBExpr ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LSBExpr ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t LSB = CE -> getValue ( ) ; if ( LSB < <NUM_LIT> || LSB > <NUM_LIT> ) { Error ( E , <STR_LIT> ) ; return


<s> static const LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true


<s> if ( type && ! AGGREGATE_TYPE_P ( type ) ) alignment = TYPE_ALIGN ( TYPE_MAIN_VARIANT (


<s> emitBinary ( OutStreamer , <STR_LIT> , RS1


CallingConv :: Fast ? <NUM_LIT> : <NUM_LIT> ;


<s> __ev64_fs__ v ; v = __builtin_spe_evfscfsf ( ( __v2sf ) a ) ; return __ev_get_fs_internal ( ( __ev64_opaque__ ) v , pos


<s> EVT CopyVT = VA . getLocVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget . hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg (

) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT ,


<s> unsigned getVariadicFPRSize ( ) const


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return __arm_vcvtnq_m_u32_f32 ( __inactive ,


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return


<s> static void iq2000_print_operand_address ( FILE * file , machine_mode mode , rtx addr ) { if ( ! addr ) error ( <STR_LIT> ) ; else switch ( GET_CODE ( addr ) ) { case REG : if ( REGNO ( addr ) == ARG_POINTER_REGNUM ) abort_with_insn ( addr , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr ) ] ) ; break ; case LO_SUM : { rtx arg0 = XEXP ( addr , <NUM_LIT> ) ; rtx arg1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( arg0 ) != REG ) abort_with_insn ( addr , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; iq2000_print_operand_address ( file , mode , arg1 ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( arg0 ) ] ) ; } break ; case PLUS : { rtx reg = <NUM_LIT>


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken ::


<s> int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm


<s> <STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ; EVT CarryVT = Carry . getValueType ( ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getAllOnesConstant ( DL , CarryVT ) ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry . getValue ( <NUM_LIT> ) ) ; return getSETCC ( CC , Cmp . getValue ( <NUM_LIT> ) , DL ,


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT , DAG . getRegister ( is64Bit ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Base , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; unsigned char OperandFlags = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( is64Bit ) { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( )

, Offset , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; OptForSize = MF . getFunction ( ) . optForSize ( ) ; MLI = & getAnalysis <


<s> const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , false , IDLoc , Instructions


<s> ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! ( I -> isBarrier ( ) || ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg


<s> return true ; case ELF :: R_MIPS_CHERI_SETTAG : case ELF :: R_MIPS_CHERI_SETTAG_LOADADDR : case ELF :: R_MIPS_CHERI_LOCAL_CAPABILITY : case ELF :: R_MIPS_CHERI_GLOBALS_TABLE : llvm_unreachable ( <STR_LIT> ) ; return true ; case ELF :: R_MIPS_CHERI_CAPTABLEREL16 : return true ; case ELF :: R_MIPS_REL32 : case ELF :: R_MIPS_LITERAL : case ELF :: R_MIPS_CALL16 : case ELF :: R_MIPS_SHIFT5 : case ELF :: R_MIPS_SHIFT6 : case ELF :: R_MIPS_GOT_DISP : case ELF :: R_MIPS_GOT_HI16 : case ELF :: R_MIPS_GOT_LO16 : case ELF :: R_MIPS_INSERT_A : case ELF :: R_MIPS_INSERT_B : case ELF :: R_MIPS_DELETE : case ELF :: R_MIPS_CALL_HI16 : case ELF :: R_MIPS_CALL_LO16 : case ELF :: R_MIPS_SCN_DISP : case ELF :: R_MIPS_REL16 : case ELF :: R_MIPS_ADD_IMMEDIATE : case ELF :: R_MIPS_PJUMP : case ELF :: R_MIPS_RELGOT : case ELF :: R_MIPS_JALR : case ELF :: R_MIPS_TLS_DTPMOD32 : case ELF :: R_MIPS_TLS_DTPREL32 : case ELF :: R_MIPS_TLS_DTPMOD64 : case ELF :: R_MIPS_TLS_DTPREL64 : case ELF :: R_MIPS_TLS_GD : case ELF :: R_MIPS_TLS_LDM : case ELF :: R_MIPS_TLS_DTPREL_HI16 : case ELF :: R_MIPS_TLS_DTPREL_LO16 : case ELF :: R_MIPS_TLS_GOTTPREL : case ELF :: R_MIPS_TLS_TPREL32 : case ELF :: R_MIPS_TLS_TPREL64 : case ELF :: R_MIPS_TLS_TPREL_HI16 : case ELF :: R_MIPS_TLS_TPREL_LO16 : case ELF :: R_MIPS_GLOB_DAT : case ELF :: R_MIPS_PC21_S2 : case ELF :: R_MIPS_PC26_S2 : case ELF :: R_MIPS_PC18_S3 : case ELF :: R_MIPS_PC19_S2 : case ELF :: R_MIPS_PCHI16 : case ELF :: R_MIPS_PCLO16 : case ELF :: R_MIPS_COPY : case ELF :: R_MIPS_JUMP_SLOT : case ELF :: R_MIPS_NUM : case ELF :: R_MIPS_PC32 : case ELF :: R_MIPS_EH : case ELF :: R_MICROMIPS_26_S1 : case ELF :: R_MICROMIPS_GPREL16 : case ELF :: R_MICROMIPS_LITERAL : case ELF :: R_MICROMIPS_PC7_S1 : case ELF :: R_MICROMIPS_PC10_S1 : case ELF :: R_MICROMIPS_PC16_S1 : case ELF :: R_MICROMIPS_CALL16 : case ELF :: R_MICROMIPS_GOT_DISP : case ELF :: R_MICROMIPS_GOT_HI16 : case ELF :: R_MICROMIPS_GOT_LO16 : case ELF :: R_MICROMIPS_SUB : case ELF :: R_MICROMIPS_HIGHER : case ELF :: R_MICROMIPS_HIGHEST : case ELF :: R_MICROMIPS_CALL_HI16 : case ELF :: R_MICROMIPS_CALL_LO16 : case ELF :: R_MICROMIPS_SCN_DISP : case ELF :: R_MICROMIPS_JALR : case ELF :: R_MICROMIPS_HI0_LO16 : case ELF :: R_MICROMIPS_TLS_GD : case ELF :: R_MICROMIPS_TLS_LDM : case ELF ::


<s> if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = <NUM_LIT> ; else if ( IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) * num_insns_ptr = <NUM_LIT> ; else * num_insns_ptr


<s> default : return true ; case VK_<ISA_LIT>_ADDR : case VK_<ISA_LIT>_PCREL : case VK_<ISA_LIT>_GOT : case VK_<ISA_LIT>_GOTPC : case VK_<ISA_LIT>_GOTOFF : case VK_<ISA_LIT>_TPOFF : case VK_<ISA_LIT>_TLSGD : return false ; } } return true


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N , DAG


<s> if ( align_p ) strcat ( pattern , <STR_LIT> ) ; noreturn_p = find_reg_note ( insn , REG_NORETURN , NULL_RTX ) != NULL_RTX ; if ( noreturn_p ) { if ( TARGET_16_BIT ) strcat ( pattern , <STR_LIT> ) ; else strcat ( pattern ,


<s> uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> )


<s> int e = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) / <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; for ( int i = <NUM_LIT> ; i < e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( e + i ) , i


<s> bool <ISA_LIT>TTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , HardwareLoopInfo & HWLoopInfo ) { const <ISA_LIT>TargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , <NUM_LIT> > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( <NUM_LIT> * SchedModel . getIssueWidth ( ) ) ) return false ; } SmallPtrSet < const Value * , <NUM_LIT> > Visited ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo , Visited ) ) return false ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = <NUM_LIT> , FalseWeight = <NUM_LIT> ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( <NUM_LIT> ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } SmallVector < BasicBlock * , <NUM_LIT> > ExitBlocks ; L -> getExitBlocks ( ExitBlocks ) ; for ( auto & BB : ExitBlocks ) { for ( auto & PHI : BB -> phis ( ) ) { for ( int Idx = <NUM_LIT> , EndIdx = PHI . getNumIncomingValues ( ) ; Idx < EndIdx ; Idx ++ ) { const BasicBlock * IncomingBB = PHI . getIncomingBlock ( Idx ) ; const Value * IncomingValue = PHI . getIncomingValue ( Idx ) ; if ( L -> contains ( IncomingBB ) && memAddrUsesCTR ( IncomingValue , TM , Visited ) ) return false ; } } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . is<ISA_LIT>64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo .


<s> const Triple & TT = STI . getTargetTriple ( ) ; return TT . isOSBinFormatMachO


<s> assert ( Kind == Register && <STR_LIT> ) ; return Reg .


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( Subtarget . hasStandardEncoding ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ; return true


<s> MachineBasicBlock :: iterator J = I ; if ( ! DisableDelaySlotFiller ) D = findDelayInstr ( MBB , I ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , ++ J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( ++ J , & MBB , D ) ; unsigned structSize =


<s> copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ,


<s> return ( ( qword ) ( vec_rl ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8 ) ( si_from_int ( b ) ) , <NUM_LIT>


<s> if ( decl != NULL_TREE ) switch_to_section ( function_section ( decl ) ) ; ASM_OUTPUT_FUNCTION_LABEL ( f , name ,


<s> SMLoc ErrorLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseIdentifier ( Format ) ) return Error ( ErrorLoc , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; auto EntryRange = std :: equal_range ( std :: begin ( InsnMatchTable ) , std :: end ( InsnMatchTable ) , Format , CompareInsn ( ) ) ; if ( EntryRange . first == EntryRange . second ) return Error ( ErrorLoc , <STR_LIT> ) ; struct InsnMatchEntry * Entry = EntryRange . first ; assert ( Entry -> Format == Format ) ; for ( int i = <NUM_LIT> ; i < Entry -> NumOperands ; i ++ ) { MatchClassKind Kind = Entry -> OperandKinds [ i ] ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( StartLoc , <STR_LIT> ) ; Lex ( ) ; OperandMatchResultTy ResTy ; if ( Kind == MCK_AnyReg ) ResTy = parseAnyReg ( Operands ) ; else if ( Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20 ) ResTy = parseBDXAddr64 ( Operands ) ; else if ( Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20 ) ResTy = parseBDAddr64 ( Operands ) ; else if ( Kind == MCK_PCRel32 ) ResTy = parsePCRel32 ( Operands ) ; else if ( Kind == MCK_PCRel16 ) ResTy = parsePCRel16 ( Operands ) ; else { const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( Expr ) ) return Error ( StartLoc , <STR_LIT> ) ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; ResTy = MatchOperand_Success ; } if ( ResTy != MatchOperand_Success ) return true ; } MCInst Inst = MCInstBuilder ( Entry -> Opcode ) ; for ( size_t i = <NUM_LIT> ; i < Operands . size ( ) ; i ++ ) { MCParsedAsmOperand & Operand = * Operands


<s> const StringRef Base = BaseMember . first , Member = BaseMember . second ; if ( getParser ( ) . lookUpField ( SM . getType ( ) , DotDispStr , Info ) && getParser ( ) . lookUpField ( SM . getSymName ( ) , DotDispStr , Info ) && getParser ( ) . lookUpField ( DotDispStr , Info ) && ( ! SemaCallback || SemaCallback -> LookupInlineAsmField ( Base , Member , Info . Offset ) ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else { return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } End = SMLoc :: getFromPointer ( DotDispStr . data ( ) ) ; const char * DotExprEndLoc = DotDispStr . data ( ) + DotDispStr . size ( ) ; while ( Tok . getLoc ( ) . getPointer ( )


<s> unsigned ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) . addImm


<s> for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) )


<s> if ( <STR_LIT> . contains ( Reg ) ) return false ; if ( <STR_LIT> . contains ( Reg ) ) { RegToUseForCFI = getSubReg ( Reg , <STR_LIT> ) ; for ( int I = <NUM_LIT> ; CSR_<ISA_LIT>_AAPCS_SaveList [ I ] ; ++ I ) { if ( CSR_<ISA_LIT>_AAPCS_SaveList [ I ] ==


<s> if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { const unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgIn = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; InVals . push_back ( ArgIn ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString (


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget (


<s> SDValue Result = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mult , DL , VT ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( Shift , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( isAdd ? <STR_LIT> : <STR_LIT> , DL , VT , Result , N -> getOperand ( <NUM_LIT> ) ) ; return Result ; } ; auto combineMulMulAddOrSub = [ & ] ( int Mul1 , int Mul2 , bool isAdd ) { SDValue Result = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mul1 , DL , VT ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( Mul2 , DL , VT ) ) ; Result = DAG . getNode ( isAdd ? <STR_LIT> : <STR_LIT> , DL , VT , Result , N -> getOperand ( <NUM_LIT> ) ) ; return Result ; } ; switch ( MulAmt ) { default : break ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> , true ) ; case <NUM_LIT> : return combineMulShlAddOrSub ( <NUM_LIT> , <NUM_LIT> ,


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : return createMachOStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ; case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return create<ISA_LIT>WinCOFFStreamer ( Ctx , MAB , _Emitter


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == <NUM_LIT> ) return <NUM_LIT> ; if ( rs6000_tune != PROCESSOR_CELL ) return <NUM_LIT> ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) * PredCost = <NUM_LIT> ; if ( UOps ) return ItinData


<s> void addAbsMemOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> )


<s> if ( isa < StoreInst > ( U ) ) { Value * Ptr = U -> getOperand ( <NUM_LIT> ) ; if ( auto GEP = dyn_cast < GetElementPtrInst > ( Ptr )


<s> MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc (


<s> t = __ev_mwhsmf ( a , b ) ; return __ev_addsmiaaw ( t


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( createNEMESISPass (


<s> SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CP , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load


<s> if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , Reg , <STR_LIT> , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRSaveToReg ( MBB , It , Reg ) ; CallPt = MBB . insert ( It , CallMIB ) ; copyPhysReg ( MBB , It , DebugLoc ( ) , <STR_LIT> , Reg , true ) ; if ( ! AFI . isLRSpilled ( ) ) emitCFIForLRRestoreFromReg (


<s> case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i


<s> Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasPrefixInstrs = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv =


<s> TargetMBBInfo * MBBInfo = getMBBInfo ( MBB ) ; if ( ! MBBInfo -> Modified ) return ; MachineInstr * BrMI = MBBInfo -> BrInstr ; <STR_LIT> CC = MBBInfo -> BranchCode ; MachineInstrBuilder MIB = BuildMI ( * MBB , BrMI , MBB -> findDebugLoc ( BrMI ) , TII -> get ( GetCondBranchFromCond ( CC ) ) ) . addMBB ( MBBInfo -> TBB ) ; BrMI -> eraseFromParent ( ) ; MBBInfo -> BrInstr = MIB . getInstr ( ) ; MachineBasicBlock :: iterator UncondBrI = findUncondBrI ( MBB ) ; BuildMI ( * MBB , UncondBrI , MBB -> findDebugLoc ( UncondBrI ) , TII -> get ( <STR_LIT> ) ) .


<s> virtual MVT getScalarShiftAmountTy ( EVT


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank (


<s> __o = __builtin_aarch64_ld2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregoidi ( __o ,


<s> StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag ) ) return MatchOperand_NoMatch ; IFlags |= Flag


<s> if ( regno == <NUM_LIT> || ( regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387 ) || ( regno == FIRST_SSE_REG && TARGET_SSE ) ) return true ; if ( ! TARGET_64BIT && ( regno == FIRST_MMX_REG && TARGET_MMX ) ) return true ; return false


<s> SDValue Ops [ ] = { Dst , Src , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return true ; } uint64_t Mask0Imm , Mask1Imm ; SDValue And0 = N -> getOperand ( <NUM_LIT> ) ; SDValue And1 = N -> getOperand ( <NUM_LIT> ) ; if ( And0 . hasOneUse ( ) && And1 . hasOneUse ( ) && isOpcWithIntImmediate ( And0 . getNode ( ) , <STR_LIT> , Mask0Imm ) && isOpcWithIntImmediate ( And1 . getNode ( ) , <STR_LIT> , Mask1Imm ) && APInt ( BitWidth , Mask0Imm ) == ~ APInt ( BitWidth , Mask1Imm ) && ( isShiftedMask ( Mask0Imm , VT ) || isShiftedMask ( Mask1Imm , VT ) ) ) { if ( isShiftedMask ( Mask0Imm , VT ) ) { std :: swap ( And0 , And1 ) ; std :: swap ( Mask0Imm , Mask1Imm ) ; } SDValue Src = And1 -> getOperand ( <NUM_LIT> ) ; SDValue Dst = And0 -> getOperand ( <NUM_LIT> ) ; unsigned LSB = countTrailingZeros ( Mask1Imm ) ; int Width = BitWidth - APInt ( BitWidth , Mask0Imm ) . countPopulation ( ) ; SDLoc DL ( N ) ; unsigned ShiftOpc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; uint64_t LsrImm = LSB ; if ( Src -> hasOneUse ( ) && isOpcWithIntImmediate ( Src . getNode ( ) , <STR_LIT> , LsrImm ) && ( LsrImm + LSB ) < BitWidth ) { Src = Src -> getOperand ( <NUM_LIT> ) ; LsrImm += LSB ; } SDNode * LSR = CurDAG -> getMachineNode ( ShiftOpc , DL , VT , Src , CurDAG -> getTargetConstant ( LsrImm , DL , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> , DL , VT ) ) ; unsigned ImmR = ( BitWidth - LSB ) % BitWidth ; unsigned ImmS = Width - <NUM_LIT> ; SDValue Ops [ ] = { Dst , SDValue ( LSR , <NUM_LIT> ) , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return true ; } return


<s> UC . recordPersonality ( L ) ; if ( ! UC . hasFnStart ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return


<s> if ( VECTOR_MODE_P ( modev2 ) ) op0 = safe_vector_operand ( op0 , modev2 ) ; if ( VECTOR_MODE_P ( modev4 ) ) op2 = safe_vector_operand ( op2 , modev4 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , modev2 ) ) op0 = copy_to_mode_reg ( modev2 , op0 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , modei3 ) ) op1 = copy_to_mode_reg ( modei3 , op1 ) ; if ( ( optimize && ! register_operand ( op2 , modev4 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op2 , modev4 ) ) op2 = copy_to_mode_reg ( modev4 , op2 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op3 , modei5 ) ) op3 = copy_to_mode_reg ( modei5 , op3 ) ; if ( ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op4 , modeimm ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( d -> code == IX86_BUILTIN_PCMPESTRI128 ) { if ( optimize || ! target || GET_MODE ( target ) != tmode0 || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode0 ) ) target = gen_reg_rtx ( tmode0 ) ; scratch1 = gen_reg_rtx ( tmode1 ) ; pat = GEN_FCN ( d -> icode ) ( target , scratch1 , op0 , op1 , op2 , op3 , op4 ) ; } else if ( d -> code == IX86_BUILTIN_PCMPESTRM128 ) { if ( optimize || ! target || GET_MODE ( target ) != tmode1 || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ]

. predicate ( target , tmode1 ) ) target = gen_reg_rtx ( tmode1 ) ;


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( DstReg ) ; const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( WideTy . getSizeInBits ( ) >= NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; assert ( NarrowTy . isScalar ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue (

MI , MO ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ;


<s> } while ( GET_CODE ( worker ) == NOTE || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , <NUM_LIT> , <NUM_LIT> ) ; wpat1 = XVECEXP ( wpat , <NUM_LIT> , <NUM_LIT> ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , <NUM_LIT> , <NUM_LIT> ) , XEXP ( XVECEXP ( wsrc , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , lab , XEXP ( wpat1 , <NUM_LIT> ) ) ) ; INSN_CODE ( worker ) = - <NUM_LIT> ; diff = gen_rtx_MINUS ( Pmode , XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , <NUM_LIT> , <NUM_LIT> ) , gen_rtx_LABEL_REF ( Pmode , lab ) ) ; diff = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , diff ) , UNSPEC_PIC ) ; SET_SRC ( PATTERN ( mova ) ) = gen_rtx_CONST ( Pmode , diff ) ; INSN_CODE ( mova )


<s> if ( suffix == 'q' ) return TFmode ; return VOIDmode


<s> MCRegister getEnvironmentPointerRegister ( ) const { assert ( usesFunctionDescriptors ( ) && <STR_LIT> ) ; return Is<ISA_LIT>64 ? <STR_LIT> :


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << ( int32_t ) Op . getImm ( ) ; }


<s> if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isEHPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end (


<s> __inline__ static void sh_media_FPUTSCR ( float fg ) { __asm__ ( <STR_LIT> : : <STR_LIT> ( fg )


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( new <ISA_LIT>ELFObjectWriter ( true , OSType , ELF :: EM_<ISA_LIT>_64 ,


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum !=

<NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ;


<s> static DecodeStatus DecodeCPURegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ RegNo ]


<s> SDNode * <ISA_LIT>DAGToDAGISel :: QuadSRegs ( EVT VT , SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 ,


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved =


<s> if ( ! address_operand ( op [ arg_count ] , SImode ) ) { op [ arg_count ] = convert_memory_address ( Pmode , op [ arg_count ] ) ; op [ arg_count ] = copy_addr_to_reg ( op [ arg_count ] ) ; } op [ arg_count ] = gen_rtx_MEM ( SImode , op [ arg_count ] ) ; } else if ( insn_op -> mode == V1DImode && GET_MODE ( op [ arg_count ] ) == DImode ) op [ arg_count ] = gen_lowpart ( V1DImode , op [ arg_count ] ) ; else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ; } switch (


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && Subtarget . hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; MachineMemOperand * MMO = nullptr ; for ( auto * I : MI . memoperands ( ) ) if ( I -> isStore ( ) ) { MMO = I ; break ; } BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; if ( ! MI . killsRegister ( <STR_LIT> ) && ! checkCCKill ( MI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ; MBB -> addSuccessor (


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_SIZE ( inner ) ; if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno


<s> res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; TWO52 = ix86_gen_TWO52 ( mode ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ; emit_label (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( MO . isReg ( ) && MO . isUse ( ) && MO . isKill ( ) && getRegisterInfo ( ) . regsOverlap ( MO . getReg ( ) , RegNo ) ) MO . setIsKill ( false ) ; } ; int UseIndex = EndMI -> findRegisterUseOperandIdx ( RegNo , false , & getRegisterInfo ( ) ) ; if ( UseIndex != - <NUM_LIT> ) { EndMI -> getOperand ( UseIndex ) . setIsKill ( true ) ; IsKillSet = true ; for ( int i = <NUM_LIT> , e = EndMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( i != UseIndex ) clearOperandKillInfo ( * EndMI , i ) ; } MachineBasicBlock :: reverse_iterator It = * EndMI ; MachineBasicBlock :: reverse_iterator E = EndMI -> getParent ( ) -> rend ( ) ; It ++ ; MachineOperand * MO = nullptr ; for ( ; It != E ; ++ It ) { if ( It -> isDebugInstr ( ) ||


<s> if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , Subtarget , false ) ) return Ld ; } } if ( auto * Ld = dyn_cast < LoadSDNode > ( peekThroughOneUseBitcasts ( SubVec2 ) ) ) if ( SubVec2 == SubVec && <STR_LIT> ( Ld ) && SDNode :: areOnlyUsersOf ( { N , Vec . getNode ( ) } , SubVec2 . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec ) ; if ( SubVec . getOpcode ( ) == <STR_LIT> && SubVec == SubVec2 ) return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec . getOperand ( <NUM_LIT> ) ) ; if ( <STR_LIT> ( SubVec . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ; if ( ! Vec . getOperand ( <NUM_LIT> ) . isUndef ( ) && Vec . hasOneUse ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getUNDEF ( OpVT ) , SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , SubVec


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( getThe<ISA_LIT>64elTarget ( )


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) && ( MI . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> || MI . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ,


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N1 ) || cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; EVT VTy = N0 . getValueType ( ) ; if ( ! VTy . isVector ( ) ) return SDValue ( ) ; EVT EltTy = VTy . getVectorElementType ( ) ; if ( EltTy != <STR_LIT> && EltTy != <STR_LIT> && EltTy != <STR_LIT> ) return SDValue ( ) ; if ( VTy . getSizeInBits ( ) <


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI )


<s> void DecodeSHUFPSMask ( unsigned NElts , unsigned Imm , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( Imm % NElts ) ; Imm /= NElts ; } for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( Imm % NElts + NElts


<s> const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; } else if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } else { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT>


<s> static DecodeStatus DecodeBranchTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset


<s> void printzmmwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo ,


<s> MachineBasicBlock & JmpMBB = * JmpI . getParent ( ) ; insertTest ( JmpMBB , JmpI . getIterator ( ) , JmpI . getDebugLoc ( ) , CondReg ) ; JmpI . getOperand ( <NUM_LIT> ) . setImm ( Inverted ?


<s> Kd ( Kind ) , Supported ( HasFeature ) , DepOpIdx ( Index ) , OpSet1 ( First ) , OpSet2


<s> assert ( DestVT != <STR_LIT> && <STR_LIT> ) ; if ( ( ( DestVT != <STR_LIT> ) && ( DestVT != <STR_LIT> ) && ( DestVT != <STR_LIT> ) && ( DestVT != <STR_LIT> ) ) || ( ( SrcVT != <STR_LIT> ) && ( SrcVT != <STR_LIT> ) && ( SrcVT != <STR_LIT> ) && ( SrcVT != <STR_LIT> ) ) ) return <NUM_LIT> ; unsigned Opc ; unsigned Imm = <NUM_LIT> ; switch ( SrcVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : return emiti1Ext ( SrcReg , DestVT , IsZExt ) ; case <STR_LIT> : if ( DestVT == <STR_LIT> ) Opc = IsZExt ? <STR_LIT> : <STR_LIT> ; else Opc = IsZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; case <STR_LIT> : if ( DestVT == <STR_LIT> ) Opc = IsZExt ? <STR_LIT> : <STR_LIT> ; else Opc = IsZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; case <STR_LIT> : assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; Opc = IsZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; } if ( DestVT == <STR_LIT> || DestVT == <STR_LIT>


<s> for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , VecTys [ i ] , Expand ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; setOperationAction ( <STR_LIT> , VecTys [ i ] , Legal ) ; } } if ( ! TM . Options . UseSoftFloat ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( ! Subtarget -> isSingleFloat ( ) ) { if ( Has<ISA_LIT>64 ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> ,


<s> if ( VT == <STR_LIT> ) { int Align = <NUM_LIT> ; VAList = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Align - <NUM_LIT> , DL , PtrVT ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( - Align , DL , PtrVT ) ) ; NextPtr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else if ( VT == <STR_LIT> ) { NextPtr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; unsigned InternalOffset = <NUM_LIT> ; VAList = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG .

getConstant ( InternalOffset , DL , PtrVT ) ) ;


<s> } if ( NumSubs == <NUM_LIT> ) return Builder ( DAG , DL , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Subs ; for ( unsigned i = <NUM_LIT> ; i != NumSubs ; ++ i ) { SmallVector < SDValue , <NUM_LIT> > SubOps ; for ( SDValue Op : Ops ) { EVT OpVT = Op . getValueType ( ) ; unsigned NumSubElts = OpVT . getVectorNumElements ( ) / NumSubs ; unsigned SizeSub = OpVT . getSizeInBits ( ) / NumSubs ; SubOps . push_back ( extractSubVector ( Op , i * NumSubElts , DAG , DL , SizeSub ) ) ; } Subs . push_back ( Builder ( DAG , DL , SubOps ) ) ; } return DAG . getNode ( <STR_LIT> , DL ,


<s> std :: unique_ptr < PBQPRAConstraint > <ISA_LIT>Subtarget :: getCustomPBQPConstraints ( )


<s> unsigned R = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( ( R << <NUM_LIT> ) | SysM ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm (


<s> if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first ; } int BaseCost = ST -> hasMVEIntegerOps ( ) && ValTy -> isVectorTy ( ) ? ST -> getMVEVectorCostFactor ( ) : <NUM_LIT> ; return BaseCost * BaseT :: getCmpSelInstrCost ( Opcode , ValTy


<s> return emitAddSub_ri ( false , RetVT , LHSReg , LHSIsKill


<s> unsigned long live_regs_mask ; unsigned long l_mask ; unsigned high_regs_pushed = <NUM_LIT> ; bool lr_needs_saving ; func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) { if ( flag_stack_usage_info ) current_function_static_stack_size = <NUM_LIT> ; return ; } if ( IS_INTERRUPT ( func_type ) ) { error ( <STR_LIT> ) ; return ; } if ( is_called_in_ARM_mode ( current_function_decl ) ) emit_insn ( gen_prologue_thumb1_interwork ( ) ) ; offsets = arm_get_frame_offsets ( ) ; live_regs_mask = offsets -> saved_regs_mask ; lr_needs_saving = live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ; l_mask = live_regs_mask & <NUM_LIT> ; high_regs_pushed = bit_count ( live_regs_mask & <NUM_LIT> ) ; if ( crtl -> args . pretend_args_size ) { rtx x = GEN_INT ( - crtl -> args . pretend_args_size ) ; if ( cfun -> machine -> uses_anonymous_args ) { int num_pushes = ARM_NUM_INTS ( crtl -> args . pretend_args_size ) ; unsigned long mask ; mask = <NUM_LIT> << ( LAST_ARG_REGNUM + <NUM_LIT> ) ; mask -= <NUM_LIT> << ( LAST_ARG_REGNUM + <NUM_LIT> - num_pushes ) ; insn = thumb1_emit_multi_reg_push ( mask , <NUM_LIT> ) ; } else { insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , x ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_BACKTRACE ) { HOST_WIDE_INT offset = <NUM_LIT> ; unsigned work_register ; rtx work_reg , x , arm_hfp_rtx ; work_register = thumb_find_work_register ( live_regs_mask ) ; work_reg = gen_rtx_REG ( SImode , work_register ) ; arm_hfp_rtx = gen_rtx_REG ( SImode , ARM_HARD_FRAME_POINTER_REGNUM ) ; insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( l_mask ) { insn = thumb1_emit_multi_reg_push ( l_mask , l_mask ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; lr_needs_saving = false ; offset = bit_count ( l_mask ) * UNITS_PER_WORD ; } x = GEN_INT ( offset + <NUM_LIT> + crtl -> args . pretend_args_size ) ; emit_insn ( gen_addsi3 ( work_reg , stack_pointer_rtx , x ) ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; if ( l_mask ) { x = gen_rtx_REG ( SImode , PC_REGNUM ) ; emit_move_insn ( work_reg , x ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; emit_move_insn ( x , work_reg ) ; emit_move_insn ( work_reg , arm_hfp_rtx ) ; x = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; x = gen_frame_mem (


<s> __attribute__ ( ( __always_inline__ ) ) _MM_GET_FLUSH_ZERO_MODE ( void


<s> const <ISA_LIT>ElfTargetObjectFile & TLOFELF = static_cast < const <ISA_LIT>ElfTargetObjectFile & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFELF . getAttributesSection ( ) ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT>


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB ) { BuildCondBr ( MBB , TBB , DL , Cond ) ; BuildMI ( & MBB , DL , get ( UncondBrOpc ) ) . addMBB ( FBB ) ; return <NUM_LIT> ; } if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( UncondBrOpc ) ) . addMBB ( TBB ) ; else BuildCondBr ( MBB , TBB , DL , Cond ) ; return <NUM_LIT>


<s> auto ZextEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ SrcTy , DstTy ] ( const ZextEntry & El ) { return El . DstTy == DstTy && El . SrcTy == SrcTy ; } ) ; if ( ZextEntryIt != std :: end ( OpTable ) ) { const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } unsigned TransitRegTo = DstReg ; unsigned TransitRegFrom = SrcReg ; if ( ZextEntryIt -> MovOp ) { if ( ZextEntryIt -> NeedSubregToReg ) { TransitRegFrom = MRI . createVirtualRegister ( getRegClass ( LLT :: scalar ( <NUM_LIT> ) , DstReg , MRI ) ) ; TransitRegTo = TransitRegFrom ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( ZextEntryIt -> MovOp ) ) . addDef ( TransitRegTo ) . addReg ( SrcReg ) ; } if ( ZextEntryIt -> NeedSubregToReg ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( DstReg ) . addImm ( <NUM_LIT> ) . addReg ( TransitRegFrom ) . addImm ( <STR_LIT> ) ; } I . eraseFromParent ( ) ; return true ; } if ( SrcTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; unsigned AndOpc


<s> } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue InVec = N -> getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( VT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; return getOnesVector ( VT , DAG , SDLoc ( N ) ) ; } if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( VT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , VT . getVectorNumElements ( ) ) ) ; if ( IdxVal == <NUM_LIT> && InVec . hasOneUse ( ) ) { unsigned InOpcode = InVec . getOpcode ( ) ; if ( VT == <STR_LIT> && InVec . getValueType ( ) == <STR_LIT> ) { if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ; if ( ( unsigned ) M [ i ] != <NUM_LIT> * i + WhichResult ) return false ; } if ( VT . is64BitVector ( )


<s> <ISA_LIT>CallFrameOptimization ( ) : MachineFunctionPass


<s> unsigned Opc , Immr , Imms ; SDValue Opd0 ; if ( ! isBitfieldExtractOp ( CurDAG , N , Opc , Opd0 , Immr , Imms ) ) return false ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( Immr , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Imms , dl , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops64 ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , SDValue ( BFM ,


<s> unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , MRI . getRegClass ( DstReg ) -> getSize ( ) , false ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg


<s> Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data


<s> static bool mips_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return TARGET_SIBCALLS


<s> if ( ! isAAPCS_ABI ) return TargetLoweringObjectFileELF :: getStaticDtorSection ( Priority ) ; if ( Priority == <NUM_LIT> ) return StaticDtorSection ; std :: string Name = std :: string (


<s> void addNEONi32splatOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> CBucket . ChainSize = ( unsigned ) ( EleNum / ChainNum ) ; if ( CBucket . ChainSize * ChainNum != EleNum ) return false ; if ( SawChainSeparater ) { for ( unsigned i = <NUM_LIT> ; i < CBucket . ChainSize ; i ++ ) for ( unsigned j = <NUM_LIT> ; j < ChainNum ; j ++ ) if ( CBucket . Elements [ i ] . Offset != SE -> getMinusSCEV ( CBucket . Elements [ i + j * CBucket . ChainSize ] . Offset , CBucket . Elements [ j * CBucket . ChainSize ] . Offset ) ) return false ; } for ( unsigned i = <NUM_LIT> ; i < ChainNum ; i ++ ) CBucket . ChainBases . push_back ( CBucket . Elements [ i * CBucket . ChainSize ] ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) : DecodeVSTInstruction ( Inst , Insn , Address ,


<s> StringRef Layout , Mnemonic ; bool IsTbx ; if ( isTblTbxInstruction ( MI -> getOpcode ( ) , Layout , IsTbx ) ) { O << <STR_LIT> << ( IsTbx ? <STR_LIT> : <STR_LIT> ) << Layout << '\t' << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> ) << <STR_LIT> ; unsigned ListOpNum = IsTbx ? <NUM_LIT> : <NUM_LIT> ; printVectorList ( MI , ListOpNum , STI , O , <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( MI -> getOperand ( ListOpNum + <NUM_LIT> ) . getReg ( ) , <STR_LIT> ) ; printAnnotation ( O ,


<s> for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ;


<s> const DataLayout & DL = MMI -> getModule ( ) -> getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSize ( ) ; OutStreamer -> emitValueToAlignment ( PointerSize ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , PointerSize ) ; OutStreamer -> emitIntValue ( <NUM_LIT> ,


<s> default : break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf32 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf64 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get (


<s> unsigned A15SDOptimizer :: createInsertSubreg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned DReg , unsigned Lane , unsigned ToInsert ) { unsigned Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Out ) . addReg ( DReg ) . addReg ( ToInsert ) . addImm ( Lane ) ; return


<s> return ST -> hasSSE3 ( ) && ! NumElements . isScalable ( ) && NumElements . getFixedValue ( ) == <NUM_LIT>

&& ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ;


<s> return __builtin_fabs ( __a ) < __builtin_fabs (


<s> assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << ShAmt << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup


<s> return parseRegister ( Operands , RegGR , <STR_LIT> , <ISA_LIT>Operand


<s> DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false ; } bool DontMoveAcrossStore = true ; if ( ! I . isSafeToMove ( nullptr , DontMoveAcrossStore ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false ; } if ( & I != CmpMI && I . modifiesRegister ( <STR_LIT> , TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false


<s> FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx ,

* iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) {


<s> RegisterMCAsmInfoFn A ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget , create<ISA_LIT>AsmBackend


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> if ( FP_REGNUM_P ( REGNO ( dst ) ) ) return REG_P ( src ) && ! FP_REGNUM_P ( REGNO ( src ) ) ; return true


<s> if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return


<s> Size = <NUM_LIT> ; if ( IsMicro<ISA_LIT> ) { Result = readInstruction16 ( Bytes , Address , Size , Insn , IsBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R616 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>16 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( isFP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn ,


<s> SDValue Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cycles32 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; Results . push_back ( Cycles32 . getValue


<s> while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; SDLoc dl ( N ) ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering *

) new Thumb1FrameLowering ( Subtarget ) ) {


<s> vld1q_lane_p16 ( const poly16_t * __a , poly16x8_t __b , const int __c ) { return ( poly16x8_t ) __builtin_neon_vld1_lanev8hi ( ( const __builtin_neon_hi * ) __a , (


<s> unsigned __int128 __res = ( unsigned __int128 ) __X * __Y ; * __P = ( unsigned long long ) ( __res >> <NUM_LIT> ) ; return ( unsigned long


<s> bool HasZext = false ; while ( MachineInstr * MI = getDefIgnoringCopies ( Reg , MRI ) ) { unsigned Opc = MI -> getOpcode ( ) ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) || ! MRI . hasOneNonDBGUse ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; if ( Opc == TargetOpcode :: G_ANYEXT || Opc == TargetOpcode :: G_ZEXT || Opc == TargetOpcode :: G_TRUNC ) { if ( Opc == TargetOpcode :: G_ZEXT ) HasZext = true ; Register NextReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! NextReg . isValid ( ) || ! MRI . hasOneNonDBGUse ( NextReg ) ) break ; Reg = NextReg ; continue ; } Optional < uint64_t > C ; Register TestReg ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : case TargetOpcode :: G_XOR : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! VRegAndVal ) { std :: swap ( ConstantReg , TestReg ) ; VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; } if ( VRegAndVal ) { if ( HasZext ) C = VRegAndVal -> Value . getZExtValue ( ) ; else C = VRegAndVal -> Value . getSExtValue ( ) ; } break ; } case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_SHL : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( VRegAndVal ) C = VRegAndVal -> Value . getSExtValue ( ) ; break ; } } if ( ! C || ! TestReg . isValid ( ) ) break ; Register NextReg ; unsigned TestRegSize = MRI . getType ( TestReg ) . getSizeInBits ( ) ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : if ( ( * C >> Bit ) & <NUM_LIT> ) NextReg = TestReg ; break ; case TargetOpcode :: G_SHL : if ( * C <= Bit && ( Bit - * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit - * C ; } break ; case TargetOpcode :: G_ASHR : NextReg = TestReg ; Bit = Bit + * C ; if ( Bit >= TestRegSize ) Bit = TestRegSize - <NUM_LIT> ; break ; case TargetOpcode :: G_LSHR : if ( ( Bit + * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit + * C ; } break ; case TargetOpcode :: G_XOR : if ( ( * C >> Bit ) & <NUM_LIT> ) Invert = ! Invert ; NextReg = TestReg


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> auto Res = getNode ( <STR_LIT> , MaskVT , { TrueVal , AVL } ) ; if ( AllTrue ) return Res ; return DAG . getNOT ( DL , Res , Res .


<s> MVT getPointerRangeTy ( const DataLayout & DL , uint32_t AS = <NUM_LIT> ) const override { return <STR_LIT> (


<s> <ISA_LIT>GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( pSym ) ; assert ( got_entry !=


<s> unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode


<s> assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Len ) ) ; return ( Len << <NUM_LIT> ) | (


<s> return ( __m64 ) __builtin_arm_wpackwss ( ( __v2si ) __m1 ,


<s> void <ISA_LIT>InstrInfo :: AnalyzeCondBr ( const MachineInstr * Inst , unsigned Opc , MachineBasicBlock * & BB , SmallVectorImpl < MachineOperand > & Cond ) const { assert ( getAnalyzableBrOpc ( Opc ) && <STR_LIT> ) ; int NumOp = Inst -> getNumExplicitOperands ( ) ; BB = Inst -> getOperand ( NumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Opc ) ) ; for ( int i = <NUM_LIT> ; i < NumOp - <NUM_LIT> ; i ++

) Cond . push_back ( Inst -> getOperand ( i ) ) ;


<s> desired_align = GET_MODE_SIZE ( move_mode ) ; if ( TARGET_CPU_P ( PENTIUMPRO ) && ( alg == rep_prefix_4_byte || alg == rep_prefix_1_byte ) ) desired_align = <NUM_LIT> ; if ( optimize_size ) desired_align = <NUM_LIT> ; if ( desired_align < align )


<s> getAddrMode3OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( isHReg ( Reg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( isStackAligned ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> :


<s> argc ++ ; } } if ( have_retval ) switch ( argc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } else switch ( argc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ]


<s> SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , SVOp -> getMask ( ) ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Shuffle = combineTargetShuffle ( Op , DAG , DCI , Subtarget ) ) return Shuffle ; SmallVector < int , <NUM_LIT> > NonceMask ; NonceMask . push_back ( <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , NonceMask , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } return SDValue


<s> BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) { if ( ! BB -> empty ( ) && BB -> back ( ) . getDesc ( ) . isReturn ( ) ) { IP = BB -> end ( ) ; -- IP ; MachineBasicBlock :: iterator I2 = IP ; while ( I2 != BB -> begin ( ) && ( -- I2 ) -> getDesc ( ) . isTerminator ( ) ) IP = I2 ; BuildMI ( * BB , IP , dl , TII .

get ( <STR_LIT> ) ) . addReg ( InVRSAVE ) ;


<s> intptr_t diff = ( NewVal - StubAddr ) >> <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( diff ) ) { Insts . push_back ( BA_INST ( diff ) ) ; Insts . push_back ( NOP_INST ) ; } else { emitInstrForIndirectJump ( NewVal , <NUM_LIT> , Insts


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: WinEH ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString =


<s> return ( __m512 ) __builtin_ia32_vfmaddsubps512_mask3 ( ( __v16sf ) __A , ( __v16sf ) __B , (


<s> float16x8x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f16 ( val . val [ <NUM_LIT> ] , vcreate_f16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv8hf ( __o , temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv8hf ( __o , temp .


<s> EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start , getContext ( ) ) ; Symbol -> setVariableValue (


<s> for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tem = adjust_address_nv ( x , reg_mode , i * GET_MODE_SIZE ( reg_mode ) ) ; if ( reload_completed ) { if ( ! strict_memory_address_p ( reg_mode , XEXP ( tem , <NUM_LIT> ) ) ) tem = NULL_RTX ; else tem = simplify_gen_subreg ( reg_mode , x , BLKmode , i *


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFPOStackAlign ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; int64_t


<s> sh_treg_combine :: sh_treg_combine ( gcc :: context * ctx , bool split_insns , const char * name ) : rtl_opt_pass ( default_pass_data , ctx ) , m_split_insns ( split_insns ) , m_ccreg ( NULL_RTX ) { this -> name =


) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ;


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return ! strict ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , <NUM_LIT> ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( ( type != <NUM_LIT> && GET_CODE ( ind ) == POST_INC ) || ( type == <NUM_LIT> && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) return true ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && INTVAL ( XEXP ( ind , <NUM_LIT> ) ) > - <NUM_LIT> && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? <NUM_LIT> : <NUM_LIT> ) ) && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return TRUE ; return FALSE


<s> MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) SavedRegs . set ( <STR_LIT> [ I ] ) ; if ( ! MF . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; } if ( HasFP ) SavedRegs . set ( <STR_LIT> ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( <STR_LIT> ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( <STR_LIT> . contains ( Reg ) && SavedRegs .


<s> if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else Emit<ISA_LIT>MappingSymbol (


<s> d = ( SItype ) ( u >> ( sizeof ( SItype ) * <NUM_LIT> ) ) ; d *= <NUM_LIT> * ( ( ( UDItype ) <NUM_LIT> ) << ( ( sizeof ( SItype ) * <NUM_LIT> ) - <NUM_LIT> ) ) ; d += ( USItype ) ( u & ( ( ( ( UDItype ) <NUM_LIT> ) << ( sizeof ( SItype ) * <NUM_LIT> ) ) - <NUM_LIT> ) ) ; return


<s> return ( __m256i ) __builtin_ia32_pmovswb512_mask ( ( __v32hi ) __A ,


<s> static SDValue performMADD_MSUBCombine ( SDNode * ROOTNode , SelectionDAG & CurDAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ROOTNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; if ( Subtarget . has<ISA_LIT>64 ( ) ) return SDValue ( ) ; SDValue Mult = ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? ROOTNode -> getOperand ( <NUM_LIT> ) : ROOTNode -> getOperand ( <NUM_LIT> ) ; SDValue AddOperand = ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? ROOTNode -> getOperand ( <NUM_LIT> ) : ROOTNode -> getOperand ( <NUM_LIT> ) ; if ( ! Mult . hasOneUse ( ) ) return SDValue ( ) ; SDValue MultLHS = Mult -> getOperand ( <NUM_LIT> ) ; SDValue MultRHS = Mult -> getOperand ( <NUM_LIT> ) ; unsigned LHSSB = CurDAG . ComputeNumSignBits ( MultLHS ) ; unsigned RHSSB = CurDAG . ComputeNumSignBits ( MultRHS ) ; if ( LHSSB < <NUM_LIT> || RHSSB < <NUM_LIT> ) return SDValue ( ) ; APInt HighMask = APInt :: getHighBitsSet ( Mult -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) , <NUM_LIT> ) ; bool IsUnsigned = CurDAG . MaskedValueIsZero ( Mult -> getOperand ( <NUM_LIT> ) , HighMask ) && CurDAG . MaskedValueIsZero ( Mult -> getOperand ( <NUM_LIT> ) , HighMask ) && CurDAG . MaskedValueIsZero ( AddOperand , HighMask ) ; SDLoc DL ( ROOTNode ) ; SDValue TopHalf ; SDValue BottomHalf ; BottomHalf = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , AddOperand , CurDAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TopHalf = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , AddOperand , CurDAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue ACCIn = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BottomHalf , TopHalf ) ; bool IsAdd = ROOTNode -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = IsAdd ? ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) : (


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> void <ISA_LIT>LongBranch :: skipNonTerminators ( BlockPosition & Position , MBBInfo & Block ) { if ( Block . Alignment > Position . KnownBits ) { Position . Address += ( ( uint64_t ( <NUM_LIT> ) << Block . Alignment ) - ( uint64_t ( <NUM_LIT> ) << Position . KnownBits ) ) ; Position . KnownBits = Block . Alignment


<s> else emit_insn ( gen_load_tp_hard ( tp ) ) ; rtx reg = gen_reg_rtx ( SImode ) ; rtx offset = GEN_INT ( arm_stack_protector_guard_offset ) ; emit_set_insn ( reg , gen_rtx_PLUS ( SImode , tp , offset


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixOneOperandFPComparison ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { EncodedValue &= ~ ( <NUM_LIT> << <NUM_LIT>