<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT>


<s> static rtx vax_builtin_setjmp_frame_value ( void


<s> DiagnosticPredicate isSVEDataVectorRegOfWidth ( ) const { if ( Kind != k_Register || Reg . Kind != RegKind :: SVEDataVector ) return DiagnosticPredicateTy :: NoMatch ; if ( isSVEVectorReg < Class > ( ) && ( ElementWidth == <NUM_LIT> || Reg . ElementWidth == ElementWidth )

) return DiagnosticPredicateTy :: Match ;


<s> if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa


<s> MachineBasicBlock * <ISA_LIT>16TargetLowering :: emitFEXT_T8I816_ins ( unsigned BtOpc , unsigned CmpOpc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI -> getOperand ( <NUM_LIT> ) .


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , bool _is64Bit ) : <ISA_LIT>AsmBackend ( T , Triple :: NaCl , true , _is64Bit ) { State . SaveCount = <NUM_LIT> ; State . I = <NUM_LIT> ; State . RecursiveCall =


<s> return true ; case CONST_INT : return standard_sse_constant_p ( src , TImode ) ; } } else if ( MEM_P ( src ) ) { return ( REG_P ( dst ) && ( ! misaligned_operand ( src , TImode ) || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL ) ) ; } return


<s> <ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI ) : MCAsmBackend ( <STR_LIT> ) , STI ( STI ) , MCII ( T . createMCInstrInfo ( ) ) { AlignBoundary = assumeAligned ( <ISA_LIT>AlignBranchBoundary ) ; AlignBranchType =


<s> ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : case CCValAssign :: ZExt : Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; break ; case CCValAssign :: AExtUpper : assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; break ; } if ( RegsUsed . count ( VA . getLocReg ( ) ) ) { SDValue & Bits = llvm :: find_if ( RetVals , [ = ] ( const std :: pair < unsigned , SDValue > & Elt ) { return Elt . first == VA . getLocReg ( ) ; } ) ->


<s> static void ix86_register_float16_builtin_type ( void ) { if ( ! float16_type_node ) { ix86_float16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( ix86_float16_type_node ) = <NUM_LIT> ; SET_TYPE_MODE ( ix86_float16_type_node , HFmode ) ; layout_type ( ix86_float16_type_node ) ; } else ix86_float16_type_node


<s> void addPrefetchOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = ( Subtarget . hasP9Vector ( ) ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg

( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> if ( Imm == std :: numeric_limits < int32_t > :: min ( ) ) Imm = <NUM_LIT> ; Imm = ( ( Imm < <NUM_LIT> ? - Imm : Imm ) /

<NUM_LIT> ) | ( int ) isAdd << <NUM_LIT> ;


<s> assert ( CallToInline . getOperand ( <NUM_LIT> ) . isMetadata ( ) && <STR_LIT> ) ; uint64_t Offset = cast < ConstantInt > ( cast < ConstantAsMetadata > ( cast < MDTuple > ( CallToInline . getOperand ( <NUM_LIT> ) . getMetadata ( ) ) -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) -> getZExtValue ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; assert ( ! ( STI . is64Bit ( ) && STI . isTargetWindowsCoreCLR ( ) ) && <STR_LIT> ) ; const uint64_t StackProbeSize = TLI . getStackProbeSize ( MF ) ; uint64_t ProbeChunk = StackProbeSize


<s> PackedVT = <STR_LIT> ; } else { UnpackedVT = <STR_LIT> ; PackedVT = <STR_LIT> ; } auto RegNum = Regs . size ( ) ; for ( unsigned j = <NUM_LIT> , e = InSVT . getSizeInBits ( ) / OutSVT . getSizeInBits ( ) ; j < e ; j *= <NUM_LIT> , RegNum /= <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , UnpackedVT , Regs [ i ] ) ; for ( unsigned i = <NUM_LIT> ; i < RegNum / <NUM_LIT> ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , PackedVT , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ; } if ( OutVT == <STR_LIT> ) { Regs [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL ,

PackedVT , Regs [ <NUM_LIT> ] , Regs [ <NUM_LIT> ] ) ;


<s> SDValue N = IsBase ? AM . Base : AM . Index ; unsigned Opcode = N . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { N = N . getOperand ( <NUM_LIT> ) ; Opcode = N . getOpcode ( ) ; } if ( Opcode == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; unsigned Op0Code = Op0 -> getOpcode ( ) ; unsigned Op1Code = Op1 -> getOpcode ( ) ; if ( Op0Code == <STR_LIT> ) return expandAdjDynAlloc ( AM , IsBase , Op1 ) ; if ( Op1Code == <STR_LIT> ) return expandAdjDynAlloc ( AM , IsBase , Op0 ) ; if ( Op0Code == <STR_LIT> ) return expandDisp ( AM , IsBase , Op1 , cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ; if ( Op1Code == <STR_LIT> ) return expandDisp ( AM , IsBase , Op0 , cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) ; if ( IsBase && expandIndex ( AM , Op0 , Op1 ) ) return true ; } if ( Opcode == <STR_LIT> ) { SDValue Full = N . getOperand ( <NUM_LIT> ) ; SDValue Base = N . getOperand ( <NUM_LIT> ) ; SDValue Anchor = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset = ( cast < GlobalAddressSDNode > ( Full ) -> getOffset ( ) - cast < GlobalAddressSDNode > ( Anchor ) -> getOffset ( ) ) ; return expandDisp ( AM , IsBase , Base


<s> num_bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE


<s> static bool vr4130_true_reg_dependence_p ( rtx insn ) { note_stores ( PATTERN ( vr4130_last_insn ) , vr4130_true_reg_dependence_p_1 , & insn ) ; return insn ==


<s> for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( ! isSetCCr ( MI . getOpcode ( ) ) ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == <STR_LIT> ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI


<s> void <ISA_LIT>RegisterInfo :: resolveFrameIndex ( MachineInstr & MI , unsigned BaseReg , int64_t Offset ) const { int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } const MachineFunction * MF = MI . getParent ( )


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII .


<s> SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL ,


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack (


CommentStream ) << <STR_LIT> << ReferenceName ;


<s> static bool valid_bL_core_p ( unsigned int * core , unsigned int


<s> } if ( Subtarget . usesFunctionDescriptors ( ) && ! hasNest ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; } if ( isTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) && ! isPatchPoint ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; if ( isVarArg && Subtarget . is32BitELFABI ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r )


<s> ASSERT_SORTED ( OpcodeTable ) ; int Opc = Lookup ( OpcodeTable , array_lengthof ( OpcodeTable ) , Opcode ) ; assert ( Opc != - <NUM_LIT> &&


<s> unsigned getMemOffsetReg ( ) const { assert ( isMem ( ) && <STR_LIT> ) ; return Mem .


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm (


<s> return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT>


<s> Instruction * InsertAfter = Reduction . AccIntAdd ; for ( auto & Pair : PMACPairs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Pair . first -> Mul -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Pair . second -> Mul -> dump ( ) ) ; auto * VecLd0 = cast < LoadInst > ( Pair . first -> VecLd [ <NUM_LIT> ] ) ; auto * VecLd1 = cast < LoadInst > ( Pair . second -> VecLd [ <NUM_LIT> ] ) ; Acc = CreateSMLADCall ( VecLd0 , VecLd1 , Acc , InsertAfter ) ; InsertAfter = Acc ; } if ( Acc != Reduction . Phi ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; Reduction . AccIntAdd -> replaceAllUsesWith (


<s> else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , isImmutable ) ; return DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex (


<s> const unsigned FP = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> ) . addReg ( FP ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg , RegState :: Define ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg2 , RegState :: Define ) . addReg ( LabelReg , RegState :: Kill ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( RegSize ) . addReg ( LabelReg2 , RegState :: Kill ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <ISA_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) . addImm ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) . addImm ( <STR_LIT> ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB )


<s> LdDisp += MOV128SZ ; StDisp += MOV128SZ ; LMMOffset += MOV128SZ ; SMMOffset += MOV128SZ ; continue ; } if ( Size - MOV64SZ >= <NUM_LIT> && Is64Bit ) { Size = Size - MOV64SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV64SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV64SZ ; StDisp += MOV64SZ ; LMMOffset += MOV64SZ ; SMMOffset += MOV64SZ ; continue ; } if ( Size - MOV32SZ >= <NUM_LIT> ) { Size = Size - MOV32SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV32SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV32SZ ; StDisp += MOV32SZ ; LMMOffset += MOV32SZ ; SMMOffset +=


<s> type_suffix_index type ; if ( ! check_gp_argument ( nops + nimm , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; i +=


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> int includes_rshift_p ( rtx shiftop , rtx andop ) { unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; shift_mask >>= INTVAL ( shiftop )


<s> return ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand (


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -=


<s> if ( fncode == MMA_BUILTIN_DISASSEMBLE_ACC ) { new_decl = rs6000_builtin_decls [ MMA_BUILTIN_XXMFACC_INTERNAL ] ; new_call = gimple_build_call ( new_decl , <NUM_LIT> , src ) ; src = make_ssa_name ( vector_quad_type_node ) ; gimple_call_set_lhs ( new_call , src ) ; gimple_seq_add_stmt ( & new_seq , new_call ) ; } new_decl = rs6000_builtin_decls [ fncode + <NUM_LIT> ] ; tree dst_type = build_pointer_type_for_mode ( unsigned_V16QI_type_node , ptr_mode , true ) ; tree dst_base = build1 ( VIEW_CONVERT_EXPR , dst_type , dst_ptr ) ; for ( unsigned i = <NUM_LIT> ; i < nvec ; i ++ ) { unsigned index = WORDS_BIG_ENDIAN ? i : nvec - <NUM_LIT> - i ; tree dst = build2 ( MEM_REF , unsigned_V16QI_type_node , dst_base , build_int_cst ( dst_type , index * <NUM_LIT> ) ) ; tree dstssa = make_ssa_name ( unsigned_V16QI_type_node ) ; new_call = gimple_build_call ( new_decl , <NUM_LIT> , src , build_int_cstu ( uint16_type_node , i ) ) ; gimple_call_set_lhs ( new_call , dstssa ) ; gimple_seq_add_stmt ( & new_seq , new_call ) ; gimplify_assign ( dst , dstssa , & new_seq ) ; } pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( gsi , new_seq , true ) ; return true ; } new_decl = rs6000_builtin_decls [ fncode + <NUM_LIT> ] ; tree lhs , op [ MAX_MMA_OPERANDS ] ; tree acc = gimple_call_arg ( stmt , <NUM_LIT> ) ; push_gimplify_context ( true ) ; if ( ( attr & RS6000_BTC_QUAD ) != <NUM_LIT> ) { op [ <NUM_LIT> ] = make_ssa_name ( vector_quad_type_node ) ; for ( unsigned i = <NUM_LIT> ; i < nopnds ; i ++ ) op [ i ] = gimple_call_arg ( stmt , i ) ; gimplify_assign ( op [ <NUM_LIT> ] , build_simple_mem_ref ( acc ) ,


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> vpmaxq_s8 ( int8x16_t a , int8x16_t b ) { return __builtin_aarch64_smaxpv16qi ( a ,


<s> void EmitDataMappingSymbol ( ) { if ( LastEMS == EMS_Data ) return ; EmitMappingSymbol ( <STR_LIT> ) ; LastEMS =


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } LLVM_DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) . getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int64_t spOffset = MF . getFrameInfo ( ) .


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , const Triple & TT , const MCRegisterInfo & MRI , MachO :: CPUSubType<ISA_LIT> st ) :

<ISA_LIT>AsmBackend ( T , TT , true ) , MRI ( MRI ) , Subtype ( st ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( Op , DAG ) ; return getAddrLocal ( Op , DAG , Has<ISA_LIT>64


<s> static void MoveBelowOrigChain ( SelectionDAG * CurDAG , SDValue Load , SDValue Call , SDValue OrigChain ) { SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i


<s> AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> AFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb2 = AFI -> isThumbFunction ( ) ; Context = & funcInfo .


<s> SDLoc dl ( Op ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , OpVT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , dl , OpVT ) ; SDValue And = DAG . getNode ( <STR_LIT> , dl , OpVT , Op . getOperand ( <NUM_LIT> ) , One ) ; return DAG . getSetCC ( dl , VT , And , Zero , <STR_LIT> ) ; } if ( ! VT . isVector ( ) || VT . isScalableVector ( ) ) return SDValue ( ) ; if ( useSVEForFixedLengthVectorVT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return LowerFixedLengthVectorTruncateToSVE ( Op , DAG ) ; return SDValue (


<s> static int readVVVV ( struct InternalInstruction * insn ) { dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> vexSize == <NUM_LIT> ) insn -> vvvv = vvvvFromVEX3of3 ( insn -> vexPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vexSize == <NUM_LIT> ) insn -> vvvv =

vvvvFromVEX2of2 ( insn -> vexPrefix [ <NUM_LIT> ] ) ;


<s> SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; if ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) return Op ; SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , ZeroVec , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( )


<s> for ( Module :: const_iterator I = M -> getFunctionList ( ) . begin ( ) , E = M -> getFunctionList ( ) . end ( ) ; I != E ; ++ I ) { if ( I -> getName ( ) == <STR_LIT> ) { NaClReadTp = I ; break ; } } SDValue TlsReadTp ; if ( NaClReadTp == NULL ) TlsReadTp = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; else TlsReadTp = DAG . getGlobalAddress ( NaClReadTp , DL , PtrVT ) ; ArgListTy Args ; TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , PtrTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , TlsReadTp


<s> InChain = OverflowArea . getValue ( <NUM_LIT> ) ; SDValue RegSaveArea = DAG . getLoad ( <STR_LIT> , dl , InChain , RegSaveAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = RegSaveArea . getValue ( <NUM_LIT> ) ; SDValue CC = DAG . getSetCC ( dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue RegConstant = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT . isInteger ( ) ? <NUM_LIT> : <NUM_LIT> , <STR_LIT> ) ) ; SDValue OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , RegSaveArea , RegConstant ) ; if ( VT . isFloatingPoint ( ) ) OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , OurReg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue IndexPlus1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> , <STR_LIT> ) ) ; InChain = DAG . getTruncStore ( InChain , dl , IndexPlus1 , VT . isInteger ( ) ? VAListPtr : FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , CC , OurReg , OverflowArea ) ; SDValue OverflowAreaPlusN = DAG . getNode ( <STR_LIT> , dl , PtrVT , OverflowArea , DAG . getConstant (


<s> bool Filler :: findDelayInstr ( MachineBasicBlock & MBB , MachineBasicBlock :: instr_iterator Slot , MachineBasicBlock :: instr_iterator & Filler ) { SmallSet < unsigned , <NUM_LIT> > RegDefs ; SmallSet < unsigned , <NUM_LIT> > RegUses ; insertDefsUses ( Slot , RegDefs , RegUses ) ; bool SawLoad = false ; bool SawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugInstr ( ) )


<s> int Cost = BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ; Cost = vectorCostAdjustment ( Cost , Opcode , Val , nullptr ) ; if ( ST -> hasVSX ( ) && Val -> getScalarType ( ) -> isDoubleTy ( ) ) { if ( ISD == <STR_LIT> && Index == ( ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; return Cost ; } else if ( Val -> getScalarType ( ) -> isIntegerTy ( ) && Index != - <NUM_LIT> ) { if ( ST -> hasP9Altivec


<s> return ( __mmask8 ) __builtin_ia32_pcmpgtq256_mask ( ( __v4di ) __A , (


<s> unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , dl , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG , dl ) , Reg0 , Reg0 } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , Reg0 } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops ) ; return true ; } } return false ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm


<s> return makeLibCall ( DAG , Call , <STR_LIT> , Ops , false , SDLoc ( Op


<s> case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 ,


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( (


<s> MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; if ( Kind != MCSymbolRefExpr :: VK_None ) O << MCSymbolRefExpr :: getVariantKindName ( Kind ) ; if ( BE || Kind != MCSymbolRefExpr :: VK_None ) { O << <STR_LIT> ; Expr -> print ( O , &


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue (


<s> return :: isUNPCKHMask ( N -> op_begin ( ) , N -> getNumOperands ( )


<s> if ( Kind == k_Immediate && Imm . Val -> getKind ( ) == MCExpr :: ExprKind :: Constant ) { int64_t val = ( ( const MCConstantExpr * )


<s> Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_MINUS_ZERO ( * r ) ) return <NUM_LIT> ; if ( real_equal ( r , & value_fp0 ) ) return <NUM_LIT> ; return


<s> if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; unsigned EltSize = InputVector . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint64_t Offset = EltSize * cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue OffsetVal = DAG . getConstant ( Offset , TLI


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler


<s> unsigned Reg = MO . getReg ( ) ; switch ( Mode ) { default : return true ; case 'b' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; } O << TRI -> getName ( Reg


<s> inline vector signed int vec_vcmpgtsw ( vector signed int a1 , vector signed int a2 ) { return ( vector signed int ) __builtin_altivec_vcmpgtsw ( ( vector signed int ) a1 , ( vector


<s> bool hasSSBS ( ) const { return HasSSBS


<s> } else { unsigned Cond = static_cast < <ISA_LIT>Operand & > ( * Operands [ CondOp ] ) . getCondCode ( ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( Cond == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( Cond == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : { <ISA_LIT>Operand & op = static_cast < <ISA_LIT>Operand & > ( * Operands [ ImmOp ] ) ; if ( ! op . isSignedOffset < <NUM_LIT> , <NUM_LIT> > ( ) && isThumbTwo ( ) ) Inst . setOpcode ( <STR_LIT> ) ; break ; } case <STR_LIT> : { <ISA_LIT>Operand & op = static_cast < <ISA_LIT>Operand & > ( * Operands [ ImmOp ] ) ; if ( ! op . isSignedOffset < <NUM_LIT> , <NUM_LIT> > ( ) && isThumbTwo


<s> return __builtin_mve_vqmovunbq_sv4si ( __a ,


<s> EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl ,


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; unsigned Opc = I -> getOpcode ( ) ; if ( I -> isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; case <STR_LIT> : T2JumpTables . push_back ( I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) || I -> getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits =


<s> int Offset = getLdStOffsetOp ( * I ) . getImm ( ) ; int PairedOffset = getLdStOffsetOp ( * Paired ) . getImm ( ) ; bool PairedIsUnscaled = TII -> isUnscaledLdSt ( Paired -> getOpcode ( ) ) ; if ( IsUnscaled != PairedIsUnscaled ) { int MemSize = getMemScale ( * Paired ) ; if ( PairedIsUnscaled ) { assert ( ! ( PairedOffset % getMemScale ( * Paired ) ) && <STR_LIT> ) ; PairedOffset /= MemSize ; } else { PairedOffset *= MemSize ; } } MachineInstr * RtMI , * Rt2MI ; if ( Offset == PairedOffset + OffsetStride ) { RtMI = & * Paired ; Rt2MI = & * I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = & * I ; Rt2MI = & * Paired ; } int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( TII -> isUnscaledLdSt ( RtMI -> getOpcode ( ) ) ) { assert ( ! ( OffsetImm % getMemScale ( * RtMI ) ) && <STR_LIT> ) ; OffsetImm /= getMemScale ( * RtMI ) ; } MachineInstrBuilder MIB ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineOperand RegOp0 = getLdStRegOp ( * RtMI ) ; MachineOperand RegOp1 = getLdStRegOp ( * Rt2MI ) ; if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { unsigned Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . addOperand ( RegOp0 ) . addOperand ( RegOp1 ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * Paired ) ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs


<s> Value * <ISA_LIT>IREmitter :: visitOR ( const


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsi64_si32 ( __m64 __i ) { return ( ( int )


<s> return selectBDAddr ( <STR_LIT> , Addr , Base


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const


<s> for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T ,


<s> static inline unsigned GetCopOpc2 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> ,


<s> res = strstr ( arr [ <NUM_LIT> ] , str ) != NULL ; if ( res ) return res ; if ( arr [ <NUM_LIT> ] != NULL ) return strstr ( arr


<s> else Opcode = <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Offset . getValueType ( ) ) ) return SDValue ( ) ; EVT HwSrcVt = getSVEContainerType ( SrcVT ) ; SDValue InputVT = DAG . getValueType ( SrcVT ) ; if ( SrcVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue SrcNew ; if ( Src . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode


<s> HOST_WIDE_INT offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; HOST_WIDE_INT base_offset ; if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || mode == TImode ) base_offset = ( ( offset + <NUM_LIT> * GET_MODE_SIZE ( mode ) ) & ~ ( ( <NUM_LIT> * GET_MODE_SIZE


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseInvNum ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { const MCExpr * IdVal ; if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( )


<s> case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr ::

create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> return isTargetDarwin ( ) || ( ! isTargetWindows ( )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> const DataLayout * TD = TM . getDataLayout ( ) ; bool is<ISA_LIT>64 = TD -> getPointerSizeInBits ( ) == <NUM_LIT> ; <ISA_LIT>TargetStreamer & TS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( is<ISA_LIT>64 ) Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getCPUDirective ( )


<s> assert ( VT . isScalableVector ( ) && DAG . getTargetLoweringInfo ( )


<s> SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget -> hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask ,


<s> AU . addRequired < MachineModuleInfoWrapperPass >


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) { OS << formatHex ( ( Op . getImm ( ) << <NUM_LIT> ) |


<s> return sparc_function_arg_1 ( cum , mode ,


<s> mips_split_plus ( x , & given_base , & given_offset ) ; mips_get_cprestore_base_and_offset ( & required_base , & required_offset , load_p ) ; return given_base == required_base &&


<s> void <ISA_LIT>InstPrinter :: printVectorListFour ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI ->

getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> if ( isTargetELF ( ) && TM . isPositionIndependent ( ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mask_i64gather_epi32 ( __m128i src , int const * base , __m128i index , __m128i mask , const int scale ) { return ( __m128i ) __builtin_ia32_gatherdiv4si ( ( __v4si ) src , base , ( __v2di ) index ,


<s> static bool canGuaranteeTCO ( CallingConv :: ID CC ) { return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv ::

<ISA_LIT>_RegCall || CC == CallingConv :: HiPE || CC == CallingConv :: HHVM ) ;


<s> bool sh_is_nott_insn ( const rtx_insn * i ) { return i != NULL && GET_CODE ( PATTERN ( i ) ) == SET && t_reg_operand ( XEXP ( PATTERN ( i ) , <NUM_LIT>

) , VOIDmode ) && negt_reg_operand ( XEXP ( PATTERN ( i ) , <NUM_LIT> ) , VOIDmode ) ;


<s> SDValue N0 = peekThroughBitcasts ( Op . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( Op . getOperand ( <NUM_LIT> ) ) ; unsigned SHLAmt = N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( SHLAmt % <NUM_LIT> == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > Mask ( <NUM_LIT> , <NUM_LIT> ) ; std :: iota ( Mask . begin ( ) , Mask . end ( ) , <NUM_LIT> ) ; std :: rotate ( Mask . begin ( ) , Mask . begin ( ) + SHLAmt / <NUM_LIT> , Mask . end ( ) ) ; if ( SDValue Shuffle = DAG . getVectorShuffle ( <STR_LIT> , dl , DAG . getBitcast ( <STR_LIT> , N0 ) , DAG . getUNDEF ( <STR_LIT> ) , Mask ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shuffle ) ; } SDValue ArgVal = DAG . getBitcast ( <STR_LIT> , N0 ) ; SDValue SHLOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgVal , DAG . getConstant (


<s> void <ISA_LIT>VSXSwapRemoval :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const int InitialVectorSize ( <NUM_LIT> ) ; SwapVector . clear ( ) ; SwapVector . reserve (


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF


<s> comparison = reverse_condition ( comparison ) ; branch_expander = gen_branch_false ; default : ; } emit_insn ( gen_rtx_SET ( get_t_reg_rtx ( ) , gen_rtx_fmt_ee ( comparison , SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ; rtx_insn * jump = emit_jump_insn ( branch_expander ( operands [ <NUM_LIT>


<s> int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = <NUM_LIT> ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head =

regrename_chain_from_id ( head -> id ) ;


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; return performIntegerAbsCombine ( N , DAG


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! DAG . MaskedValueIsZero ( N1 , Mask17 ) || ! DAG . MaskedValueIsZero ( N0 , Mask17 ) ) return SDValue ( ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { DAG . getBitcast ( WVT , N0 )

, DAG . getBitcast ( WVT , N1 ) } , PMADDWDBuilder ) ;


<s> const MCExpr * AssemblerConstantPools :: addEntry ( MCStreamer & Streamer , const MCExpr * Expr ) { const MCSection * Section = Streamer . getCurrentSection ( ) . first ; return getOrCreateConstantPool ( Section ) . addEntry ( Expr ,


<s> if ( ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) || getImmFixupKind ( Desc . TSFlags ) != FK_PCRel_4 ) return false ; unsigned CurOp = <STR_LIT> ( Desc ) ; const MCOperand & Op = MI . getOperand ( CurOp ) ; if ( ! Op . isExpr ( ) ) return false ; const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr >


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAlignedMemoryOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addRegOperands ( Inst , <NUM_LIT> ) ;


<s> return __builtin_mve_vqshlq_m_r_sv4si ( __a ,


<s> if ( M != CodeModel :: Small && M != CodeModel :: Kernel ) return false ; if ( M == CodeModel :: Small && Offset < <NUM_LIT> * <NUM_LIT>


<s> } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } printExpr ( Op . getExpr (


<s> for ( unsigned Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( LoRegsToSave [ Reg ] ) { bool isKill = ! MRI . isLiveIn ( Reg ) ; if ( isKill && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameSetup ) ; SmallVector < unsigned , <NUM_LIT> > RegsToPush ; while ( HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { if ( HiRegsToSave [ * HiRegToSave ] ) { bool isKill = ! MRI . isLiveIn ( * HiRegToSave ) ; if ( isKill && ! MRI . isReserved ( * HiRegToSave ) ) MBB . addLiveIn ( * HiRegToSave ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( * CopyReg , RegState :: Define ) . addReg ( * HiRegToSave , getKillRegState ( isKill ) ) . add (


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT>


<s> static DecodeStatus DecodeSyncI ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * <NUM_LIT> : ( Size - <NUM_LIT> - i ) * <NUM_LIT> ; EmitByte ( ( Val >> Shift ) & <NUM_LIT> ,


<s> inline unsigned even128 ( bool Is32bit ) { return Is32bit ? subreg_hl32


<s> AU . addRequired < LoopInfo > ( ) ; AU . addPreserved < LoopInfo > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution >


<s> CCMask = CCMaskForCondCode ( Cond ) ; if ( CmpOp0 . getValueType ( ) . isFloatingPoint ( ) ) CCValid = <STR_LIT> ; else { IsUnsigned = CCMask & <STR_LIT> ; CCValid = <STR_LIT> ; CCMask &= CCValid ; adjustZeroCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; adjustSubwordCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; if ( preferUnsignedComparison ( DAG , CmpOp0 , CmpOp1 , CCMask ) ) IsUnsigned = true ; } SDLoc DL ( CmpOp0 )


<s> unsigned MaxAlign = std :: max ( FFI -> getMaxAlignment (

) , calculateMaxStackAlignment ( FFI ) ) ;


<s> unsigned HOST_WIDE_INT ival ; if ( GET_CODE ( x ) == CONST_DOUBLE && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr < <NUM_LIT> ; } return


<s> bool isUImm3 ( ) const { return isUImm < <NUM_LIT> > (


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler


<s> return true ; } ; auto MatchShift = [ & ] ( int Shift , int Scale , bool Left , SDValue V ) { for ( int i = <NUM_LIT> ; i != Size ; i += Scale ) { unsigned Pos = Left ? i + Shift : i ; unsigned Low = Left ? i : i + Shift ; unsigned Len = Scale - Shift ; if ( ! isSequentialOrUndefInRange ( Mask , Pos , Len , Low + ( V == V1 ? <NUM_LIT> : Size ) ) ) return SDValue ( ) ; } int ShiftEltBits = VT . getScalarSizeInBits ( ) * Scale ; bool ByteShift = ShiftEltBits > <NUM_LIT> ; unsigned OpCode = Left ? ( ByteShift ? <STR_LIT> : <STR_LIT> ) : ( ByteShift ? <STR_LIT> : <STR_LIT> ) ; int ShiftAmt = Shift * VT . getScalarSizeInBits ( ) / ( ByteShift ? <NUM_LIT> : <NUM_LIT> ) ; Scale = ByteShift ? Scale / <NUM_LIT> : Scale ; MVT ShiftSVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) * Scale ) ; MVT ShiftVT = <STR_LIT> ( ShiftSVT , Size / Scale ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>ISelDag ( * this , OptLevel ) ) ; if ( ! Subtarget . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass


<s> if ( MFI . isLRStoreRequired ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem : i += NumVals ; break ; case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i ) { Register Reg = cast < RegisterSDNode > ( Op .


<s> if ( ! Imm1Fn || ! Imm2Fn ) return false ; auto NewI = MIB . buildInstr ( Is64Bit ? <STR_LIT> : <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; for ( auto & RenderFn : * Imm1Fn ) RenderFn ( NewI ) ; for ( auto & RenderFn : * Imm2Fn )


<s> MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) , Reg ) . addReg ( Reg ) . addImm ( Val ) . setMIFlag (


<s> break ; case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) : <ISA_LIT>AsmBackend ( T , STI ) , MRI ( MRI ) , TT ( STI . getTargetTriple ( ) ) , Is64Bit ( TT . isArch64Bit ( ) ) { memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; OffsetSize = Is64Bit ? <NUM_LIT>


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( FixupKind ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> unsigned opcode = Op . getOpcode ( ) ; assert ( ( opcode == <STR_LIT> || opcode == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = ( opcode == <STR_LIT> ) ; EVT VT = <STR_LIT> ; EVT WideVT = <STR_LIT> ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != VT ) return Op ; SDValue ShiftAmt = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue HiLHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS , ShiftAmt ) ; SDValue HiRHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS , ShiftAmt ) ; SDValue Args [ ] = { HiLHS , LHS , HiRHS , RHS } ; SDValue MulResult = TLI . makeLibCall ( DAG , RTLIB :: MUL_I128 , WideVT , Args , <NUM_LIT> , isSigned , dl ) . first ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( isSigned ) { SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , BottomHalf , ShiftAmt ) ; TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , Tmp1 , <STR_LIT> ) ; } else { TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , DAG . getConstant


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) ; } MachineInstr * NewMI =


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { unsigned SType


<s> } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OS << '\x7' ; return


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv4sf (


<s> GPRPad = NumGPRs % ( ( align + <NUM_LIT> ) / <NUM_LIT> ) ; StackPad = StackOffset % align ; unsigned firstGPR = NumGPRs + GPRPad ; switch ( ObjectVT . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else NeededStackSize = <NUM_LIT> ; break ; case


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; uint64_t AndImm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N , <STR_LIT> , AndImm ) ) return false ; const SDNode * Op0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AndImm |= maskTrailingOnes < uint64_t > ( NumberOfIgnoredLowBits ) ; if ( AndImm & ( AndImm + <NUM_LIT> ) ) return false ; bool ClampMSB = false ; uint64_t SrlImm = <NUM_LIT> ; if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , SrlImm ) ) { Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true ; } else if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> ,


<s> BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get ( AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insertAfter ( MachineBasicBlock :: iterator ( MI ) , CallseqEnd ) ; return BB


<s> CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return PostRAScheduler && OptLevel >=


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return <STR_LIT>


<s> return ( uint16x8_t ) ( vabsq_f16 ( __a ) <=


<s> Arg1 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg1 , MinC ) , MinC , Arg1 ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg0 , MaxC ) , MaxC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg1 , MaxC ) , MaxC , Arg1 ) ; SmallVector < int , <NUM_LIT> > PackMask ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( unsigned Elt = <NUM_LIT> ; Elt != NumSrcEltsPerLane ; ++ Elt ) PackMask . push_back ( Elt + ( Lane * NumSrcEltsPerLane ) ) ; for ( unsigned Elt = <NUM_LIT> ; Elt != NumSrcEltsPerLane ; ++ Elt ) PackMask . push_back ( Elt + ( Lane * NumSrcEltsPerLane ) + NumSrcElts ) ; } auto * Shuffle = Builder . CreateShuffleVector ( Arg0 ,


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) S


<s> return ( AMSubMode ) ( ( AM5Opc >> <NUM_LIT>


<s> return getTM < <ISA_LIT>TargetMachine > (


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) { if ( ! OpRegCstraints -> contains ( Reg ) ) return false ; } else if ( ! OpRegCstraints -> hasSubClassEq ( MRI -> getRegClass ( Reg ) ) && ! MRI -> constrainRegClass ( Reg , OpRegCstraints ) ) return false ; } return true


<s> bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; const char * SymName = CLI . SymName ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size


<s> int getSEHRegNum ( unsigned i ) const { return getEncodingValue (


<s> const <ISA_LIT>FrameLowering * <ISA_LIT>FrameLowering :: create ( const <ISA_LIT>Subtarget


<s> unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveRegX ( Reg ,


<s> EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , true , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I ,


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( is64Bit ) PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; UseDataRegionDirectives = MarkedJTDataRegions ; ExceptionsType = ExceptionHandling :: DwarfCFI


<s> Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) || ( VT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ; unsigned NumSubElts = SplitSize / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , SplitSize ) ; SrcVec = Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( SrcVec , DL , SubVT ) : DAG

. getZeroExtendVectorInReg ( SrcVec , DL , SubVT ) ;


<s> PUT_MODE ( src , V2DImode ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == V2DImode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ; gcc_assert ( ( REG_P ( src ) && GET_MODE ( src ) == DImode ) || ( SUBREG_P ( src ) && GET_MODE ( src ) == V2DImode ) ) ; if ( REG_P ( src ) ) subreg = gen_rtx_SUBREG ( V2DImode , src , <NUM_LIT> ) ; else subreg = copy_rtx_if_shared ( src )


<s> const MCSection * FindAssociatedSection ( ) const { return getSubExpr ( ) -> FindAssociatedSection (


<s> void relaxInstruction ( const MCInst & Inst , MCInst &


<s> void setVarArgsGPRSize ( unsigned Size ) { VarArgsGPRSize =


<s> SDLoc DL ( N ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode (


<s> } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= <NUM_LIT> ) return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= <NUM_LIT> ) return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; else return Isload ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; } else if ( Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) { if ( Alignment >= <NUM_LIT> ) return Isload


<s> initialize<ISA_LIT>ReduceCRLogicalsPass ( * PassRegistry :: getPassRegistry ( )


<s> I != MBB . instr_end ( ) ; ++ I ) if ( I -> getDesc ( ) . hasDelaySlot ( ) ) { MachineBasicBlock :: instr_iterator J = I ; if ( ! CompatDelaySlotFiller && findDelayInstr ( MBB , I , J ) ) MBB . splice ( llvm :: next ( I ) , & MBB , J ) ; else BuildMI ( MBB , llvm :: next ( I ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; ++ FilledSlots ; Changed =


<s> static SDValue getUnpackh ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { SmallVector < int , <NUM_LIT> >


<s> case <NUM_LIT> : return false ; default : llvm_unreachable ( <STR_LIT> ) ; } uint32_t ExpStart = FracBits ; uint64_t FracMask = ( <NUM_LIT> << FracBits ) - <NUM_LIT> ; uint32_t Sign = Val . isNegative ( ) ; uint64_t Bits = Val . bitcastToAPInt ( ) . getLimitedValue ( ) ; uint64_t Fraction = Bits & FracMask ; int32_t Exponent = ( ( Bits >> ExpStart ) & ExpMask ) ; Exponent -= ExpMask >> <NUM_LIT> ; uint64_t A64FracStart = FracBits - <NUM_LIT> ; uint64_t A64FracMask = <NUM_LIT> ; if ( Fraction & ~ ( A64FracMask << A64FracStart


<s> assert ( ! getContext ( ) . getAsmInfo ( ) -> isLittleEndian


<s> bool FPIsUsed = false ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> + i ) ) { FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock *


<s> return __builtin_mve_vqsubq_n_uv8hi ( __a ,


<s> void Emit<ISA_LIT>MappingSymbol ( ) { if ( LastEMS == EMS_<ISA_LIT>


<s> static void emit_save_or_restore_local_in_regs ( rtx base , int offset , sorr_act_t action ) { if ( offset < - <NUM_LIT> || offset + <NUM_LIT> * UNITS_PER_WORD > <NUM_LIT> ) { base = emit_adjust_base_to_offset ( base , offset ) ; offset = <NUM_LIT>


<s> else { if ( stack_adjust ) live_regs_mask |= <NUM_LIT> << <NUM_LIT> ; sprintf ( instr , <STR_LIT> , conditional ) ; } } else if ( IS_INTERRUPT ( func_type ) ) sprintf ( instr , <STR_LIT> , conditional ) ; else sprintf ( instr , <STR_LIT> , conditional ) ; p = instr + strlen ( instr ) ; for ( reg = <NUM_LIT> ; reg <= SP_REGNUM ; reg ++ ) if ( live_regs_mask & ( <NUM_LIT> << reg ) ) { int l = strlen ( reg_names [ reg ] ) ; if ( first ) first = <NUM_LIT> ; else { memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; p += <NUM_LIT> ; } memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; memcpy ( p + <NUM_LIT> , reg_names [ reg ] , l ) ; p += l + <NUM_LIT> ; } if ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) { sprintf ( p , <STR_LIT> , first ? <STR_LIT> : <STR_LIT> , return_reg ) ; if ( IS_INTERRUPT ( func_type ) ) strcat ( p , <STR_LIT> ) ; } else strcpy ( p , <STR_LIT> ) ; } output_asm_insn ( instr , & operand ) ; if ( really_return && func_type != ARM_FT_INTERWORKED && ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ) { return <STR_LIT> ; } } if ( really_return ) { switch ( ( int ) ARM_FUNC_TYPE ( func_type ) ) { case ARM_FT_ISR : case ARM_FT_FIQ : sprintf ( instr , <STR_LIT> , conditional ) ; break ; case ARM_FT_INTERWORKED : gcc_assert ( arm_arch5 || arm_arch4t ) ; sprintf ( instr , <STR_LIT> , conditional ) ; break ; case ARM_FT_EXCEPTION : sprintf ( instr , <STR_LIT> , conditional ) ; break ; default : if ( IS_CMSE_ENTRY ( func_type


<s> bool <ISA_LIT>ConstantIslands :: findAvailableWater ( CPUser & U , unsigned UserOffset , water_iterator & WaterIter , bool CloserWater ) { if ( WaterList . empty ( ) ) return false ; unsigned BestGrowth = ~ <NUM_LIT> ; MachineBasicBlock * UserBB = U . MI -> getParent ( ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; const Align CPEAlign = getCPEAlign ( U . CPEMI ) ; unsigned MinNoSplitDisp = BBInfo [ UserBB -> getNumber ( ) ] . postOffset ( CPEAlign ) ; if ( CloserWater && MinNoSplitDisp > U . getMaxDisp ( ) / <NUM_LIT> ) return false ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI -> getParent ( ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * WaterBB ) << <STR_LIT> << Growth << '\n' ) ; if ( CloserWater && WaterBB == U . MI -> getParent ( ) ) return true ; if ( ! CloserWater && BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B ) break ; } return BestGrowth != ~


<s> } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget -> hasFullFP16 ( ) ) ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT , Custom ) ; if ( ! VT . isFloatingPoint ( ) ) setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( ! VT . isFloatingPoint ( ) && VT != <STR_LIT> && VT != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getVectorElementType ( ) != <STR_LIT> && ( VT . getVectorElementType ( ) != <STR_LIT> || Subtarget -> hasFullFP16 ( ) ) ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getScalarSizeInBits ( ) != <NUM_LIT> ) setOperationAction ( <STR_LIT>


<s> case RX_BUILTIN_MVFACMI : return rx_expand_int_builtin_0_arg ( target , gen_mvfacmi ) ; case RX_BUILTIN_MVTACHI : return rx_expand_void_builtin_1_arg ( op , gen_mvtachi , true ) ; case RX_BUILTIN_MVTACLO : return rx_expand_void_builtin_1_arg ( op , gen_mvtaclo , true ) ; case RX_BUILTIN_RMPA : if ( rx_allow_string_insns ) emit_insn ( gen_rmpa ( ) ) ; else error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target ) ; case RX_BUILTIN_MVTC : return rx_expand_builtin_mvtc ( exp ) ; case RX_BUILTIN_MVTIPL : return rx_expand_builtin_mvtipl ( op ) ; case RX_BUILTIN_RACW : return rx_expand_void_builtin_1_arg ( op , gen_racw , false ) ; case RX_BUILTIN_ROUND : return rx_expand_builtin_round ( op , target ) ; case RX_BUILTIN_REVW : return rx_expand_int_builtin_1_arg ( op , target , gen_revw , false ) ; case RX_BUILTIN_WAIT : emit_insn ( gen_wait ( ) ) ; return NULL_RTX ; default : internal_error ( <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_cvttpd2dq512_mask ( ( __v8df ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8 ) __U ,


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; const MCExpr * Expr = MO . getExpr ( ) ; const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( Expr ) ; bool IsPCRel = SRE -> getKind ( )

== MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_PCREL ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM


<s> case <NUM_LIT> : goto Search_IC ; case <NUM_LIT> : goto Search_PRCTX ; } case <NUM_LIT> : { Search_PRCTX : const <STR_LIT> * PRCTX = <STR_LIT> ( Encoding >> <NUM_LIT> ) ; if ( ! PRCTX || ! PRCTX -> haveFeatures ( STI . getFeatureBits ( ) ) ) return false ; NeedsReg = PRCTX -> NeedsReg ; switch ( Op2Val ) { default : return false ; case <NUM_LIT> : Ins = <STR_LIT> ; break ; case <NUM_LIT> : Ins = <STR_LIT> ; break ; case <NUM_LIT> : Ins = <STR_LIT> ; break ; } Name = std :: string ( PRCTX -> Name ) ; } break ; case <NUM_LIT> : { Search_IC : const <STR_LIT> * IC = <STR_LIT> ( Encoding ) ; if ( ! IC || ! IC -> haveFeatures ( STI . getFeatureBits ( ) ) ) return false ; NeedsReg = IC -> NeedsReg ; Ins = <STR_LIT> ; Name = std :: string ( IC -> Name ) ; } break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : { const <STR_LIT> * DC =


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const { return &


<s> bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr :

& getAnalysis < MachineDominatorTree > ( ) ;


<s> if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) ) && DstVT == SatVT && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ; if ( DstWidth < SatWidth ) return SDValue ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sext ( DstWidth ) , DL , DstVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sext ( DstWidth ) , DL , DstVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , Min , MaxC ) ; } else { SDValue MinC = DAG . getConstant ( APInt :: getAllOnesValue ( SatWidth ) . zext ( DstWidth ) , DL , DstVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt


<s> const int size = int_size_in_bytes ( arg . type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> || slotno == SPARC_FP_ARG_MAX - <NUM_LIT> ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_INT || ( ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT || ( arg . type && VECTOR_TYPE_P ( arg . type ) ) ) && ! ( TARGET_FPU && arg . named ) ) ) { const int size = ( arg . type && VECTOR_FLOAT_TYPE_P ( arg . type ) ) ? int_size_in_bytes ( arg . type ) : GET_MODE_SIZE ( arg . mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX -


<s> DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( ifunc_alias_decl ) = <NUM_LIT> ; t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( <STR_LIT> , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl


<s> SDLoc DL ( N ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Mask . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps


<s> static bool csky_far_jump_used_p ( void ) { rtx_insn * insn ; if ( cfun -> machine -> far_jump_used ) return true ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) { cfun -> machine ->


<s> static void emit_soft_tfmode_unop ( enum rtx_code code , rtx * operands ) { const char * func ; gcc_assert ( code == SQRT


<s> SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V ) return SDValue ( ) ; SDValue VMask = DAG . getBuildVector ( MaskVT , DL , VMaskOps ) ; VMask = DAG . getBitcast ( LogicVT , VMask ) ; V = DAG . getBitcast ( LogicVT , V ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , LogicVT , V , VMask ) ; return DAG . getBitcast (


<s> return isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask

[ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) { ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT>


<s> bool storeOfVectorConstantIsCheap ( EVT MemVT , unsigned NumElem , unsigned AddrSpace ) const override { return NumElem > <NUM_LIT>


<s> bool vectorizePreventedSLForwarding ( void ) { return ST -> hasSVE


<s> unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt


<s> for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p ->


<s> assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; unsigned NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; MIRBuilder . buildExtract ( NewRegs [ <NUM_LIT> ] , Arg . Reg , <NUM_LIT> ) ; MIRBuilder . buildExtract ( NewRegs [ <NUM_LIT> ] , Arg . Reg , <NUM_LIT> ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT>


<s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasSVE ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors ( ) ) return false ; return ! DataType -> getScalarType ( ) -> isIntegerTy ( <NUM_LIT> ) &&

isElementTypeLegalForScalableVector ( DataType -> getScalarType ( ) ) ;


<s> void emitARM64WinCFINop ( ) override { OS <<


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> case <STR_LIT> : case <STR_LIT> : { if ( N . getOperand ( <NUM_LIT> ) . getValueType ( ) == ShuffleVT && N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDValue N0 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpcode = N0 . getOpcode ( ) ; if ( TLI . isBinOp ( SrcOpcode ) && IsSafeToMoveShuffle ( N0 , SrcOpcode ) ) { SDValue Op00 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op01 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( IsMergeableWithShuffle ( Op00 ) || IsMergeableWithShuffle ( Op01 ) ) { SDValue LHS , RHS ; Op00 = DAG . getBitcast ( ShuffleVT , Op00 ) ; Op01 = DAG . getBitcast ( ShuffleVT , Op01 ) ; if ( N . getNumOperands ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( Opc , DL , ShuffleVT , Op00 , N . getOperand ( <NUM_LIT> ) ) ; RHS = DAG . getNode ( Opc , DL , ShuffleVT , Op01 , N . getOperand ( <NUM_LIT> ) ) ; } else { LHS = DAG . getNode ( Opc , DL , ShuffleVT , Op00 ) ; RHS = DAG . getNode ( Opc , DL , ShuffleVT , Op01 ) ; } EVT OpVT = N0 . getValueType ( ) ; return DAG . getBitcast ( ShuffleVT , DAG . getNode ( SrcOpcode , DL , OpVT , DAG . getBitcast ( OpVT , LHS ) , DAG . getBitcast ( OpVT , RHS ) ) ) ; } } } break ; } case <STR_LIT> : { unsigned InsertPSMask = N . getConstantOperandVal ( <NUM_LIT> ) ; unsigned ZeroMask = InsertPSMask & <NUM_LIT> ; if ( ZeroMask != <NUM_LIT> ) break ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDValue N0 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpcode = N0 . getOpcode ( ) ; if ( TLI . isBinOp ( SrcOpcode ) && N1 . getOpcode ( ) == SrcOpcode && IsSafeToMoveShuffle ( N0 , SrcOpcode ) && IsSafeToMoveShuffle ( N1 , SrcOpcode ) ) { SDValue Op00 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op10 = peekThroughOneUseBitcasts ( N1 . getOperand ( <NUM_LIT> )


<s> InFlag = Chain . getValue ( <NUM_LIT> ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; if ( G ) Callee = DAG . getGlobalAddress ( G -> getGlobal ( ) , Loc , PtrVT , <NUM_LIT> ) ; std :: vector < SDValue > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const uint32_t * Mask ; const TargetRegisterInfo * TRI = DAG . getSubtarget ( ) . getRegisterInfo ( ) ; Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , Loc , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , Loc , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , Loc , true ) , InFlag , Loc ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , Loc ,


<s> inline vector unsigned char vec_vpkshus ( vector signed short a1 , vector signed short a2 ) { return ( vector unsigned char ) __builtin_altivec_vpkshus ( ( vector signed

short ) a1 , ( vector signed short ) a2 ) ;


<s> O << '\n' ; PrintPICBaseSymbol ( ) ; O <<


<s> SDValue NV = performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; if ( NV . getNode ( ) ) N = NV . getNode ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; SDValue CCVal = N -> getOperand ( <NUM_LIT> ) ; SDValue Cmp = N -> getOperand ( <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( CCVal ) && <STR_LIT> ) ; unsigned CC = cast < ConstantSDNode > ( CCVal ) -> getZExtValue ( ) ; if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; unsigned CmpOpc = Cmp . getOpcode ( ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) return SDValue ( ) ; if ( ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) || ! Cmp -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; SDValue LHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; assert ( LHS . getValueType ( ) == RHS . getValueType ( ) && <STR_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isa < ConstantSDNode > ( LHS ) && cast < ConstantSDNode > ( LHS ) -> isNullValue ( ) ) std :: swap ( LHS , RHS ) ; if ( ! isa < ConstantSDNode > ( RHS ) || ! cast < ConstantSDNode > ( RHS ) -> isNullValue ( ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; SDValue BR ; if ( CC == <STR_LIT> ) BR = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Chain ,


<s> if ( ! d -> one_vector_p || d -> vec_flags == VEC_ADVSIMD ) return false ; if ( ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , nelt - <NUM_LIT> , - <NUM_LIT> ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ; return true


<s> case CallingConv :: C : case CallingConv :: Fast : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS :


<s> RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == nullptr ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) Ops . push_back ( DAG . getRegister ( RegsToPass [ I ] . first , RegsToPass [ I ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , ArrayRef < SDValue > ( & Ops [ <NUM_LIT>


<s> ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( TrapBB ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor (


<s> auto * ZII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame -> getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I !=

E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ;


<s> if ( ! ( Subtarget . hasAVX512 ( ) && Subtarget . hasBWI ( ) ) ) return ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v64s8 , v32s16 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v32s16 } , Legal


<s> const <ISA_LIT>FrameLowering & TFI = * getFrameLowering ( MF ) ; return TFI . hasFP


<s> union { qword q ; long long l [ <NUM_LIT> ] ; } x


<s> SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) { return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N0 ) , DAG . getBitcast ( <STR_LIT> , N1 ) ) ) ; } if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; SmallVector < APInt , <NUM_LIT> > SrcPartials ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps , & SrcPartials ) && SrcOps . size ( ) == <NUM_LIT> ) { unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue ZeroBits = DAG . getConstant ( <NUM_LIT> , dl , MaskVT ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , ZeroBits , <STR_LIT> ) ; } } } if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , DCI , Subtarget ) ) return FPLogic ; if ( DCI . isBeforeLegalizeOps ( ) )


<s> if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide ) ) return SDValue ( ) ; if ( ! ST . isThumb ( ) ) return SDValue ( N , <NUM_LIT> ) ; if ( Divisor . sgt ( <NUM_LIT> ) ) return SDValue


<s> return ( ( qword ) ( vec_add ( vec_mule ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b ) ) , ( vec_uint4


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true