<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , <STR_LIT> | Flags ) , getTargetNode ( N , Ty , DAG , <STR_LIT> | MO_NC | Flags ) , getTargetNode ( N ,

Ty , DAG , <STR_LIT> | MO_NC | Flags ) , getTargetNode ( N , Ty , DAG , <STR_LIT> | MO_NC | Flags ) ) ;


<s> unsigned getBackchainOffset ( MachineFunction & MF


<s> return real_equal ( r , & dconst0 ) &&


<s> SDLoc dl ( N ) ; const DataLayout & DL = CurDAG -> getDataLayout ( ) ; const TargetLowering * TLI = getTargetLowering ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && isWorthFoldingADDlow ( N ) ) { GlobalAddressSDNode * GAN = dyn_cast < GlobalAddressSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Base = N . getOperand ( <NUM_LIT> ) ; OffImm = N . getOperand ( <NUM_LIT> ) ; if ( ! GAN ) return true ; if ( GAN -> getOffset ( ) % Size == <NUM_LIT> ) { const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; Type * Ty = GV -> getValueType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) ) Alignment = DL . getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy


<s> bool <ISA_LIT>FastISel :: SelectLoad ( const Instruction * I ) { if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) -> getAlignment


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i + <NUM_LIT> ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i + <NUM_LIT> ) ) return false ; return true


<s> JCE . emitWordLE ( ( unsigned ) ( intptr_t ) Fn ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) Fn ) >> <NUM_LIT> ) ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) ; return JCE . finishGVStub ( F ) ; } JCE . startGVStub ( F , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> ) ; JCE . emitByte ( <NUM_LIT> + <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t


<s> if ( ARITHMETIC_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , <NUM_LIT> ) , reg_values ) ; rtx x1 = mips16e_collect_propagate_value ( XEXP ( x , <NUM_LIT> ) , reg_values ) ; return simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , x1 ) ; } if ( REG_P ( x ) && reg_values [ REGNO ( x ) ] && ! rtx_unstable_p ( reg_values [ REGNO ( x ) ] ) ) return reg_values [ REGNO ( x ) ] ; return


<s> static bool isNonZeroElementsInOrder ( const SmallBitVector Zeroable , ArrayRef < int > Mask , const EVT & VectorType , bool & IsZeroSideLeft ) { int NextElement = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Zeroable . size ( ) ; i < e ; i ++ ) { if ( Mask [ i ] == - <NUM_LIT>


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleMT ( ) { OS <<


<s> return new <ISA_LIT>NaClRewritePass (


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT>


<s> int32_t Imm8 = MI . getOperand ( OpIdx ) . getImm ( ) ; bool isAdd = Imm8 >= <NUM_LIT> ; if ( Imm8 < <NUM_LIT> ) Imm8 = - ( uint32_t ) Imm8 ; Imm8 /= <NUM_LIT> ; uint32_t Binary = Imm8 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; return


<s> SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1


<s> assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( Chain , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg ,

getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx


<s> int i ; i = __builtin_spe_mfspefscr ( ) ; i &= ~ mask


<s> if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , nullptr ) ; } } if ( ! Constraint . empty ( ) ) { std :: pair < unsigned , const TargetRegisterClass * > R ; R = parseRegForInlineAsmConstraint ( Constraint


<s> return ( strncmp ( DLL_IMPORT_PREFIX , symbol , strlen ( DLL_IMPORT_PREFIX ) )


<s> const AttributeSet & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . hasAttribute ( Idx , Attribute :: InReg ) ) InRegCount += ( TD -> getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: Fast : NestReg = <STR_LIT> ; break ; } SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr , Disp ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Disp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPtr , Addr ) ; const unsigned char MOV32ri = <NUM_LIT> ; const unsigned char N86Reg = TRI -> getEncodingValue ( NestReg ) & <NUM_LIT> ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( MOV32ri | N86Reg , <STR_LIT> ) , Trmp , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; const unsigned char JMP = <NUM_LIT> ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( JMP , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Disp , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { unsigned Opcode = Node -> getOpcode ( ) ; DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId (


<s> PreAnalyzeFormalArgumentsForF128 ( Ins ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear (


<s> mask = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= <NUM_LIT> << reg ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > <NUM_LIT> ) mask |= <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & <NUM_LIT> || thumb_force_lr_save ( ) ) mask |= ( <NUM_LIT> << LR_REGNUM ) ; if ( ( mask & <NUM_LIT> ) == <NUM_LIT> && ( ( mask & <NUM_LIT> ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( <NUM_LIT> << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= <NUM_LIT>


<s> AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; return AltMappings ; } case TargetOpcode :: G_BITCAST : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( <NUM_LIT> , <NUM_LIT> , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping FPRMapping ( <NUM_LIT> , <NUM_LIT> , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping GPRToFPRMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping FPRToGPRMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( GPRToFPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRToGPRMapping ) ) ; return AltMappings ; } case TargetOpcode :: G_LOAD :


<s> bool useAM3 = false ; bool needVMOV = false ; const TargetRegisterClass * RC ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3


<s> int Idx = ( ( int ) MIIdx - i + <NUM_LIT> ) % <NUM_LIT> ; MachineInstr * NextMI = LastMIs [ Idx ] ; if ( ! NextMI ) continue ; if ( TII -> canCauseFpMLxStall ( NextMI -> getOpcode ( ) ) ) { if ( i <= Limit1 ) return true ; } if ( i <= Limit2 && hasRAWHazard ( getDefReg ( MI ) , NextMI


<s> static SDValue lowerUINT_TO_FP_v2i32 ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget , const SDLoc & DL ) { if ( Op . getSimpleValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; assert ( N0 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; if ( Subtarget . hasAVX512 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue HalfWord = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfWordMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TWOHW = DAG . getConstantFP ( ( double ) ( <NUM_LIT> << <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue HI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWord ) ; SDValue LO = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , HalfWordMask ) ; SDValue fHI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) { continue ; } MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand ::


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( <STR_LIT> ( Cond . getNode ( ) ) ) { SmallVector < int , <NUM_LIT> > Mask ; if ( createShuffleMaskFromVSELECT ( Mask , Cond ) ) return DAG . getVectorShuffle ( VT


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LogicalShift = true ; ShiftLeft = true ; break ; } assert ( ( LogicalShift || ! ShiftLeft ) && <STR_LIT> ) ; Value * Vec = II . getArgOperand ( <NUM_LIT> ) ; Value * Amt = II . getArgOperand ( <NUM_LIT> ) ; auto * VT = cast < FixedVectorType > ( II . getType ( ) ) ; Type * SVT = VT -> getElementType ( ) ; int NumElts = VT -> getNumElements ( ) ; int BitWidth = SVT -> getIntegerBitWidth ( ) ; KnownBits KnownAmt = llvm :: computeKnownBits ( Amt , II . getModule ( ) -> getDataLayout ( ) ) ; if ( KnownAmt . getMaxValue ( ) . ult ( BitWidth ) ) { return ( LogicalShift ? ( ShiftLeft ? Builder . CreateShl ( Vec , Amt ) : Builder . CreateLShr ( Vec , Amt ) ) : Builder . CreateAShr ( Vec , Amt ) ) ; } auto * CShift = dyn_cast < Constant > ( Amt ) ; if ( ! CShift ) return nullptr ; bool AnyOutOfRange = false ; SmallVector < int , <NUM_LIT> > ShiftAmts ; for ( int I = <NUM_LIT> ; I < NumElts ; ++ I ) { auto * CElt = CShift -> getAggregateElement ( I ) ; if ( isa_and_nonnull < UndefValue > ( CElt ) ) { ShiftAmts . push_back ( - <NUM_LIT> ) ; continue ; } auto * COp = dyn_cast_or_null < ConstantInt > ( CElt ) ; if ( ! COp ) return nullptr ; APInt ShiftVal = COp -> getValue ( ) ; if ( ShiftVal . uge ( BitWidth ) ) { AnyOutOfRange = LogicalShift ; ShiftAmts . push_back ( LogicalShift ? BitWidth : BitWidth - <NUM_LIT> ) ; continue ; } ShiftAmts . push_back ( ( int ) ShiftVal . getZExtValue ( ) ) ; } auto OutOfRange = [ & ] ( int Idx ) { return ( Idx < <NUM_LIT> ) || ( BitWidth <= Idx ) ; } ; if ( llvm :: all_of ( ShiftAmts , OutOfRange ) ) { SmallVector < Constant * , <NUM_LIT> > ConstantVec ; for ( int Idx : ShiftAmts ) { if ( Idx < <NUM_LIT> ) { ConstantVec . push_back ( UndefValue :: get ( SVT ) ) ; }


<s> if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? <NUM_LIT> : <NUM_LIT> , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex (


<s> unsigned at = <NUM_LIT> ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( base << <NUM_LIT> ) | ( at << <NUM_LIT> ) | ( offset & <NUM_LIT> ) ) ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( base << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( ( offset + <NUM_LIT> ) & <NUM_LIT> ) ) ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> ) ; MCE . emitWordLE ( ( <NUM_LIT> << <NUM_LIT> ) | ( dst << <NUM_LIT> ) | ( at <<


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget . is64Bit ( ) ) { return Op ; } SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction

( ) , SSFI ) , false , false , <NUM_LIT> ) ;


<s> if ( TARGET_SSE4_1 ) { emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse4_1_pinsrd ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; } else if ( TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx tmp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } else { rtx tmp = assign_386_stack_local ( DImode , SLOT_TEMP ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode ,


<s> return ( __m128i ) __builtin_ia32_pmovsqb128_mask ( ( __v2di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , (


<s> return __ev_mwumiaa ( t , ( ( __ev64_s32__ )


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return <STR_LIT>


<s> bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < <NUM_LIT> ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return


<s> void addShifterOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <STR_LIT> ( getShiftExtendType ( ) ,


<s> unsigned <ISA_LIT>SEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . mayLoad ( ) ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return <NUM_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( dg ) ) ; return res


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MRI , STI ) ; return


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return *


<s> rtx op0 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; rtx op1 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( ISA_HAS_SEL && INTEGRAL_MODE_P ( GET_MODE ( operands [ <NUM_LIT> ] ) ) && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ <NUM_LIT> ] , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( temp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ <NUM_LIT> ] , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_IOR ( mode , temp , temp2 ) ) ) ; } else { if ( FLOAT_MODE_P ( GET_MODE ( operands [ <NUM_LIT> ] ) ) && ! ISA_HAS_SEL ) { operands [ <NUM_LIT> ] = force_reg ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = force_reg ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT>


<s> return TargetTriple . isOSBinFormatELF


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( QFRegs


<s> ret = simplify_const_unary_operation ( FLOAT_EXTEND , SFmode , val , BFmode ) ; if ( ret ) return ret ; ret = gen_reg_rtx ( SImode ) ; emit_move_insn ( ret , GEN_INT ( INTVAL ( op ) & <NUM_LIT>


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF


<s> rtx braf_base_lab = NULL_RTX ; const char * jump ; int far ; int offset = branch_dest ( insn ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ; rtx prev ; this . lab = gen_label_rtx ( ) ; if ( TARGET_SH2 && offset >= - <NUM_LIT> && offset - get_attr_length ( insn ) <= <NUM_LIT> ) { far = <NUM_LIT> ; jump = <STR_LIT> ; } else { far = <NUM_LIT> ; if ( flag_pic ) { if ( TARGET_SH2 ) jump = <STR_LIT> ; else jump = <STR_LIT> ; } else jump = <STR_LIT> ; } if ( GET_CODE ( ( prev = prev_nonnote_insn ( insn ) ) ) == INSN && INSN_CODE ( prev ) == CODE_FOR_indirect_jump_scratch ) { this . reg = SET_DEST ( XVECEXP ( PATTERN ( prev ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( REGNO ( this . reg ) == R0_REG && flag_pic && ! TARGET_SH2 ) jump = <STR_LIT> ; output_asm_insn ( jump , & this . lab ) ; if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; this . reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( jump , & this . lab ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } if ( far && flag_pic && TARGET_SH2 ) { braf_base_lab = gen_label_rtx ( ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( braf_base_lab ) ) ; } if ( far ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( this


<s> void <ISA_LIT>TargetStreamer :: emitObjectArch ( unsigned Arch ) { llvm_unreachable ( <STR_LIT>


<s> else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( hasAVX512 ( ) || ( hasAVX2 ( ) && hasFastGather ( ) ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) ) ScatterOverhead


<s> int NewMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] } ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; if ( NumV2Elements == <NUM_LIT> ) { int V2Index = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) - Mask . begin ( ) ; int V2AdjIndex = V2Index ^ <NUM_LIT> ; if ( Mask [ V2AdjIndex ] == - <NUM_LIT> ) { if ( V2Index < <NUM_LIT> ) std :: swap ( LowV , HighV ) ; NewMask [ V2Index ] -= <NUM_LIT> ; } else { int V1Index = V2AdjIndex ; int BlendMask [ <NUM_LIT> ] = { Mask [ V2Index ] - <NUM_LIT> , <NUM_LIT> , Mask [ V1Index ] , <NUM_LIT> } ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DAG ) ) ; if ( V2Index < <NUM_LIT> ) { LowV = V2 ; HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT>


<s> bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( ! callee_saved_reg_p ( regno ) && ( ! IN_RANGE ( regno , FIRST_VFP_REGNUM , LAST_VFP_REGNUM ) || TARGET_HARD_FLOAT ) ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ; if ( ! VOID_TYPE_P ( result_type ) ) { uint64_t to_clear_return_mask ; result_rtl = arm_function_value ( result_type , current_function_decl , <NUM_LIT> ) ; gcc_assert ( REG_P ( result_rtl ) ) ; to_clear_return_mask = compute_not_to_clear_mask ( result_type , result_rtl , <NUM_LIT> , & padding_bits_to_clear ) ; if ( to_clear_return_mask ) { gcc_assert ( ( unsigned ) maxregno < sizeof ( long long ) * __CHAR_BIT__ ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_return_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap


<s> MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; MCOp = MCOperand :: CreateImm ( * Val . bitcastToAPInt ( ) . getRawData ( ) ) ; break ; } case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand ::


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; LiveRegs . init ( & TII -> getRegisterInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( ( ( ! isGP64bit ( ) && isABI_O32 ( ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) )


<s> case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; case 'U' : if ( constraint [ <NUM_LIT> ] == 'p' && ( constraint [ <NUM_LIT> ] == 'l' || constraint [ <NUM_LIT> ] == 'a'


<s> bool isIncomingArgumentHandler ( ) const override { return true


<s> if ( Subtarget . hasPA ( ) && MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( ShouldSignWithAKey ( MF ) ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( ShouldSignWithAKey ( MF ) ? <STR_LIT> : <STR_LIT> ) )

. setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; for ( auto I = MachineBasicBlock :: iterator ( MI ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) { Ignore . insert ( & * I ) ; break ; } } bool SetFlags = RDA -> isSafeToDefRegAt ( MI , <STR_LIT> , Ignore ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get


<s> __arm_vldrhq_gather_shifted_offset ( float16_t const *


<s> if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand (


) Callee = LowerGlobalAddress ( Callee , DAG ) ;


<s> SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds ,

DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


_rdrand64_step ( unsigned long long * __P ) {


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; auto * CondBV = cast < BuildVectorSDNode > ( Cond ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> , Size = VT . getVectorNumElements ( ) ; i < Size ; ++ i ) { SDValue CondElt = CondBV -> getOperand ( i ) ; int M = i ; if ( CondElt . isUndef ( ) || isNullConstant ( CondElt ) ) M += Size ; Mask . push_back (


<s> CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT>

, <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( ! info ) info = rs6000_stack_info ( ) ; fprintf ( stderr , <STR_LIT> , ( ( current_function_decl && DECL_NAME ( current_function_decl ) ) ? IDENTIFIER_POINTER ( DECL_NAME ( current_function_decl ) ) : <STR_LIT> ) ) ; switch ( info -> abi ) { default : abi_string = <STR_LIT> ; break ; case ABI_NONE : abi_string = <STR_LIT> ; break ; case ABI_AIX : abi_string = <STR_LIT> ; break ; case ABI_ELFv2 : abi_string = <STR_LIT> ; break ; case ABI_DARWIN : abi_string = <STR_LIT> ; break ; case ABI_V4 : abi_string = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> , abi_string ) ; if ( TARGET_ALTIVEC_ABI ) fprintf ( stderr , <STR_LIT> ) ; if ( info -> first_gp_reg_save != <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , info -> first_gp_reg_save ) ; if ( info -> first_fp_reg_save != <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , info -> first_fp_reg_save ) ; if ( info -> first_altivec_reg_save <= LAST_ALTIVEC_REGNO ) fprintf ( stderr , <STR_LIT> , info -> first_altivec_reg_save ) ; if ( info -> lr_save_p ) fprintf ( stderr , <STR_LIT> , info -> lr_save_p ) ; if ( info -> cr_save_p ) fprintf ( stderr , <STR_LIT> , info -> cr_save_p ) ; if ( info -> vrsave_mask ) fprintf ( stderr , <STR_LIT> , info -> vrsave_mask ) ; if ( info -> push_p ) fprintf ( stderr , <STR_LIT> , info -> push_p ) ; if ( info -> calls_p ) fprintf ( stderr , <STR_LIT> , info -> calls_p ) ; if ( info -> gp_size ) fprintf ( stderr , <STR_LIT> , info -> gp_save_offset ) ; if ( info -> fp_size ) fprintf ( stderr , <STR_LIT> , info -> fp_save_offset ) ; if ( info -> altivec_size ) fprintf ( stderr , <STR_LIT> , info


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ; if ( ! CE ) return false ; Val = CE -> getValue ( ) ; } else if ( isGPRMem ( ) ) { if ( ! Memory . OffsetImm || Memory . OffsetRegNum ) return false ; if ( Memory . BaseRegNum != <STR_LIT> ) return false ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Val = CE -> getValue ( ) ; else return false ; } else return


<s> SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } unsigned LaneTmp2 = RegInfo . createVirtualRegister (


<s> bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed


<s> static bool rs6000_cannot_copy_insn_p ( rtx_insn * insn


<s> assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VecVT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = vecWidth / ElVT . getSizeInBits ( ) ; return Index / NumElemsPerChunk


<s> const <ISA_LIT>TargetMachine & getTargetMachine ( ) const { return TM


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; uint64_t AndImm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N , <STR_LIT> , AndImm ) ) return false ; const SDNode * Op0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; AndImm |= ( <NUM_LIT> << NumberOfIgnoredLowBits ) - <NUM_LIT> ; if ( AndImm & ( AndImm + <NUM_LIT> ) ) return false ; bool ClampMSB = false ; uint64_t SrlImm = <NUM_LIT> ; if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , SrlImm ) ) { Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true


<s> const MCInstrDesc & Desc = TII -> get ( Opcode ) ; unsigned MIFlags = Desc . TSFlags ; unsigned ReusableCCMask = <STR_LIT> ( MIFlags ) ; unsigned CompareFlags = Compare . getDesc ( ) . TSFlags ; if ( CompareFlags & <STR_LIT> ) ReusableCCMask &= <STR_LIT> ; if ( ReusableCCMask == <NUM_LIT> ) return false ; unsigned CCValues = <STR_LIT> ( MIFlags ) ; assert ( ( ReusableCCMask & ~ CCValues ) == <NUM_LIT> && <STR_LIT> ) ; bool MIEquivalentToCmp = ( ReusableCCMask == CCValues && CCValues == <STR_LIT> ( CompareFlags ) ) ; if ( ! MIEquivalentToCmp ) { SmallVector < MachineOperand * , <NUM_LIT> > AlterMasks ; for ( unsigned int I = <NUM_LIT> , E = CCUsers . size ( ) ; I != E ; ++ I ) { MachineInstr * MI = CCUsers [ I ] ; unsigned Flags = MI -> getDesc ( ) . TSFlags ; unsigned FirstOpNum ; if ( Flags & <STR_LIT> ) FirstOpNum = <NUM_LIT> ; else if ( Flags & <STR_LIT> ) FirstOpNum = MI -> getNumExplicitOperands ( ) - <NUM_LIT> ; else return false ; unsigned CCValid = MI -> getOperand ( FirstOpNum )


<s> if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && IndexReg != <STR_LIT> ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && IndexReg != <STR_LIT> ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && IndexReg != <STR_LIT> && IndexReg != <STR_LIT> ) || ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && IndexReg != <STR_LIT> && IndexReg != <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } } } return checkScale ( Scale , ErrMsg


<s> if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ; else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts


<s> break ; case FDSig : Parms = <STR_LIT> ; break ; case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer -> AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbolELF * Stub = cast < MCSymbolELF > ( OutContext . getOrCreateSymbol ( StringRef ( x ) ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . getOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer -> EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer -> EmitLabel ( Stub ) ; assert ( TM . getRelocationModel ( ) != Reloc :: PIC_ && <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( * STI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( * STI , Signature -> ParamSig ,


<s> vector_type_index function_resolver :: infer_vector_base_type ( unsigned int argno ) { type_suffix_index type = infer_vector_type ( argno ) ; if ( type == NUM_TYPE_SUFFIXES ) return NUM_VECTOR_TYPES ; if ( type == TYPE_SUFFIX_u32 || type == TYPE_SUFFIX_u64 ) return type_suffixes [ type ] . vector_type ; error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , <STR_LIT> , <STR_LIT> ) ; return NUM_VECTOR_TYPES


<s> reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( delta ) emit_insn ( gen_add3_insn ( this_rtx , this_rtx , GEN_INT ( delta ) ) ) ; if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( ( ( unsigned HOST_WIDE_INT ) vcall_offset ) + <NUM_LIT> >= <NUM_LIT> ) { emit_insn ( gen_add3_insn ( tmp , tmp , vcall_offset_rtx ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; } else { rtx loc = gen_rtx_PLUS ( Pmode , tmp , vcall_offset_rtx ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; if ( MACHOPIC_INDIRECT ) funexp = machopic_indirect_call_target ( funexp ) ; insn = emit_call_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_CALL ( VOIDmode , funexp , const0_rtx ) , gen_rtx_USE ( VOIDmode , const0_rtx ) , simple_return_rtx ) ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function (


<s> void printf128mem ( const MachineInstr *


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) .


<s> auto & TM = TPC . getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst >


<s> int reg = pcum -> reg ; machine_mode mode = arg . mode ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = pcum -> freg ; if ( reg < CSKY_NPARM_FREGS ) return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM + reg ) ; else return NULL_RTX ; } if ( reg < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode


<s> if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitArch ( ID ) ; return false


<s> } if ( ! Acc ) { Acc = Mul ; continue ; } Acc = Builder . CreateAdd ( Mul , Acc ) ; InsertAfter = cast < Instruction > ( Acc ) ; } if ( ! Acc ) Acc = R . is64Bit ( ) ? ConstantInt :: get ( IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) , <NUM_LIT> ) : ConstantInt :: get ( IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) , <NUM_LIT> ) ; IntegerType * Ty = IntegerType :: get ( M -> getContext ( ) , <NUM_LIT> ) ; for ( auto & Pair : R . getMulPairs ( ) ) { MulCandidate * LHSMul = Pair . first ; MulCandidate * RHSMul = Pair . second ; LoadInst * BaseLHS = LHSMul -> getBaseLoad ( ) ; LoadInst * BaseRHS = RHSMul -> getBaseLoad ( ) ; LoadInst * WideLHS = WideLoads . count ( BaseLHS ) ? WideLoads [ BaseLHS ] -> getLoad ( ) : CreateWideLoad ( LHSMul -> VecLd , Ty ) ; LoadInst * WideRHS = WideLoads . count ( BaseRHS ) ? WideLoads [ BaseRHS ] -> getLoad (

) : CreateWideLoad ( RHSMul -> VecLd , Ty ) ;


<s> DRECTVE_SECTION_FUNCTION \ SWITCH_TO_SECTION_FUNCTION void \ drectve_section ( void ) \ { \ if ( in_section != in_drectve ) \ { \ fprintf ( asm_out_file ,

<STR_LIT> , <STR_LIT> ) ; \ in_section = in_drectve ; \ } \ }


<s> MachineBasicBlock & MBB = * SetBI . getParent ( ) ; auto SetPos = SetBI . getIterator ( ) ; auto SetLoc = SetBI . getDebugLoc ( ) ; auto AdjustReg = [ & ] ( unsigned Reg ) { auto & OrigRC = * MRI -> getRegClass ( Reg ) ; if ( & OrigRC == & SetBRC ) return Reg ; unsigned NewReg ; int OrigRegSize = TRI -> getRegSizeInBits ( OrigRC ) / <NUM_LIT> ; int TargetRegSize = TRI -> getRegSizeInBits ( SetBRC ) / <NUM_LIT> ; assert ( OrigRegSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( TargetRegSize <= <NUM_LIT> && <STR_LIT> ) ; int SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( OrigRegSize < TargetRegSize && OrigRegSize < <NUM_LIT> ) { NewReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , SetPos , SetLoc , TII -> get ( <STR_LIT> ) , NewReg ) . addReg ( Reg ) ; if ( & SetBRC == & <STR_LIT> ) return NewReg ; Reg = NewReg ; OrigRegSize = <NUM_LIT> ; } NewReg = MRI -> createVirtualRegister ( & SetBRC ) ; if ( OrigRegSize < TargetRegSize ) { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewReg ) . addImm ( <NUM_LIT> ) . addReg ( Reg ) . addImm ( SubRegIdx [ OrigRegSize ] ) ; } else if ( OrigRegSize > TargetRegSize ) { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: EXTRACT_SUBREG ) , NewReg ) . addReg ( Reg ) . addImm ( SubRegIdx [ TargetRegSize ] ) ; } else { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg ) ; } return NewReg ; } ; unsigned & CondReg = CondRegs [ <STR_LIT> ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , <STR_LIT> ) ; unsigned ExtCondReg = AdjustReg ( CondReg ) ; unsigned ZeroReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , SetPos , SetLoc , TII -> get ( <STR_LIT> ) , ZeroReg ) ; ZeroReg = AdjustReg ( ZeroReg ) ; unsigned Sub ; switch ( SetBI . getOpcode ( ) ) { case <STR_LIT>


<s> const <ISA_LIT>RegisterInfo * ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( ) ; SDValue Glue , Chain ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DescAddr , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back (


<s> virtual unsigned getRelocationInfo ( ) const { return


<s> BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } else { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addUse


<s> if ( JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section ) { rtx body = PATTERN ( insn ) ; int elt = GET_CODE ( body ) == ADDR_DIFF_VEC ? <NUM_LIT> : <NUM_LIT> ; HOST_WIDE_INT size ; HOST_WIDE_INT modesize ; modesize = GET_MODE_SIZE ( GET_MODE ( body ) ) ; size = modesize * XVECLEN ( body , elt ) ; switch ( modesize )


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , Alignment , AddressSpace ) ; Cost += Factor * ( LT . first


<s> SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; OffsetInBytes += LoadSizeInBytes ; TotalBytesLoaded += LoadSizeInBytes ; Alignment = std :: min ( Alignment , LoadSizeInBytes ) ; } unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , Val ) ) ; return ; } } unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes ; SDValue Src = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , PtrTy , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; Chain = DAG . getMemcpy ( Chain , DL , Dst , Src , DAG . getConstant ( MemCpySize , DL , PtrTy ) , Alignment ,

false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; unsigned Rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; unsigned Imm = insn & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Imm


<s> return TargetFrameLowering :: noFramePointerElim ( MF ) || MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> static SDValue lowerV8F64Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getTargetConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG )


<s> bool WasOriginalRetVectorFloat ( unsigned ValNo )


<s> vld1q_p8 ( const poly8_t * __a ) { return ( poly8x16_t ) __builtin_neon_vld1v16qi ( ( const __builtin_neon_qi


<s> if ( ! isUndefUpperHalf ( Mask ) ) return SDValue ( ) ; int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( Mask . size ( ) / <NUM_LIT> ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) || ( HalfIdx1 % <NUM_LIT> == <NUM_LIT>

) || ( HalfIdx2 % <NUM_LIT> == <NUM_LIT> ) ) return SDValue ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } switch ( Opc2 ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const <ISA_LIT>FrameLowering * getFrameLowering


<s> bool <ISA_LIT>TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT


<s> if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; MVT HVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) /


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext &


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return


<s> void DecodePUNPCKLBWMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts


<s> static DecodeStatus DecodeLoadAllocTagArrayInstruction ( MCInst & Inst , uint32_t insn , uint64_t address , const void * Decoder ) { unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( insn ,


<s> return ( __m128d ) __builtin_ia32_divpd ( ( __v2df


<s> break ; default : break ; } if ( GET_CODE ( x ) == MINUS && ( XEXP ( x , <NUM_LIT> ) == got_register_rtx || sparc_pic_register_p ( XEXP ( x , <NUM_LIT> ) ) ) ) { rtx y = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ; } } return x


<s> bool <ISA_LIT>BaseTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt


<s> <STR_LIT> InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) HasCTRSet = true ; if ( isStore && NumStores < <NUM_LIT> && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO


<s> return sz == <NUM_LIT> || sz == <NUM_LIT> || sz == <NUM_LIT> || sz == <NUM_LIT> ||


<s> } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCStreamer & Streamer


<s> } break ; case <STR_LIT> : case <STR_LIT> : { if ( ( AddConstant >= <NUM_LIT> && CompConstant <= <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant >= <NUM_LIT> && CompConstant <= AddConstant + MaxUInt ) ) return true ; } break ; case <STR_LIT> : case <STR_LIT> : { if ( ( AddConstant > <NUM_LIT> && CompConstant < <NUM_LIT> ) || ( AddConstant < <NUM_LIT> && CompConstant >= <NUM_LIT> && CompConstant < AddConstant + MaxUInt ) || ( AddConstant >= <NUM_LIT> && CompConstant >= <NUM_LIT> && CompConstant >= AddConstant ) || ( AddConstant <= <NUM_LIT> && CompConstant < <NUM_LIT> && CompConstant < AddConstant ) ) return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT>


<s> auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread


<s> SDValue BasePtr = MSC -> getBasePtr ( ) ; <STR_LIT> IndexType = MSC -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool NeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; EVT VT = StoreVal . getSimpleValueType ( ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; EVT MemVT = MSC -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { VT = VT . changeVectorElementTypeToInteger ( ) ; ElementCount EC = VT . getVectorElementCount ( ) ; auto ScalarIntVT = <STR_LIT> ( <STR_LIT> / EC . getKnownMinValue ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ScalarIntVT , EC ) , StoreVal ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getScatterVecOpcode ( IsScaled , IsSigned , NeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , false , DAG ) ; SDValue Ops [ ] = { Chain , StoreVal , Mask ,


<s> int16x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t )


<s> case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += Scale ) { int StartIdx = - <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != Scale ; ++ j ) { int EltIdx = SVOp -> getMaskElt ( i + j ) ; if ( EltIdx < <NUM_LIT> ) continue ; if ( StartIdx < <NUM_LIT> ) StartIdx = ( EltIdx / Scale ) ; if ( EltIdx != ( int ) ( StartIdx * Scale + j ) ) return SDValue ( ) ; } MaskVec . push_back ( StartIdx ) ; } SDValue V1 = DAG . getNode ( <STR_LIT> , dl , NewVT , SVOp -> getOperand ( <NUM_LIT> ) ) ; SDValue V2 = DAG . getNode ( <STR_LIT> , dl


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler ::


<s> * no_add_attrs = true ; } else if ( ( is_attribute_p ( <STR_LIT> , name ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * type ) ) ) || ( ( is_attribute_p ( <STR_LIT> , name ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * type ) ) ) ) ) { warning ( OPT_Wattributes , <STR_LIT> ,


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> break ; } if ( It -> readsRegister ( CRBit , TRI ) ) SeenUse = true ; } if ( ! CRSetMI ) continue ; unsigned CRSetOp = CRSetMI -> getOpcode ( ) ; if ( ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) || ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) ) { InstrsToErase . push_back ( Br ) ; MBB . removeSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; } else { MachineBasicBlock :: iterator It = Br , Er = MBB . end ( ) ; for ( ; It != Er && ! SeenUse ; It ++ ) { if ( It -> isDebugInstr ( ) ) continue ; assert ( It -> isTerminator ( ) && <STR_LIT> ) ; InstrsToErase . push_back ( & * It ) ; } if ( ! MBB . isLayoutSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { ArrayRef < MachineOperand > NoCond ; TII -> insertBranch ( MBB , Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) , nullptr , NoCond , Br -> getDebugLoc ( ) ) ; } for ( auto & Succ : MBB . successors ( ) ) if ( Succ != Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) { MBB . removeSuccessor ( Succ ) ; break ; } } if ( ! SeenUse ) { for ( auto & SuccMBB : MBB . successors ( ) ) if ( SuccMBB -> isLiveIn ( CRBit ) || SuccMBB -> isLiveIn ( CRReg ) ) { SeenUse =


<s> if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) return ! PtrInOperand ? <STR_LIT> ( RegNo , Start , End ) : ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( isParsingInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd (


<s> for ( auto & MBB : MF ) { outs ( ) << <STR_LIT> ; outs ( ) <<


<s> return ( ( R . Reloc . Type == ELF :: R_CPU0_GOT16 ) && ! SD . isExternal (

) ) || ( R . Reloc . Type == ELF :: R_CPU0_HI16 ) ;


<s> return ( __m128i ) __builtin_ia32_vplzcntq_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_di ( )


<s> if ( NumLoads > <NUM_LIT> ) { VecTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy )


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> const EDInstInfo * <ISA_LIT>Disassembler :: getEDInfo ( ) const { return instInfo<ISA_LIT>


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> || Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType ( <NUM_LIT> ) ; int FI = MFI -> CreateFixedObject ( Op . getValueSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> , false ) ; SDValue InArgsAddr = DAG . getFrameIndex ( FI , ValTy


<s> BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , <ISA_LIT>Lowering -> getPointerTy ( ) ) .


<s> bool <ISA_LIT>Subtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( )


<s> static __inline qword si_ahi ( qword a , short b ) { return ( ( qword ) ( vec_add ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) )


<s> HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == <NUM_LIT> ) { if ( ! rtx_equal_p ( dest , op1 ) )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateModImm ( unsigned Bits , unsigned Rot , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_ModifiedImmediate ) ; Op -> ModImm .


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Base , Offset ; unsigned Opc ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore ( N , Opc_rr , Opc_ri , N -> getOperand ( IsIntr ? <NUM_LIT> : <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Scale ) ; SDValue Ops [ ] = { N -> getOperand ( IsIntr ? <NUM_LIT> : <NUM_LIT> ) , Base , Offset , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , DL , VT , SuperReg ) ) ; unsigned ChainIdx = NumVecs ; ReplaceUses ( SDValue ( N , ChainIdx ) ,


<s> if ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> vgetq_lane_u32 ( uint32x4_t __a , const int __b ) { return ( uint32_t ) __builtin_neon_vget_laneuv4si ( (


<s> static __inline qword si_ceq ( qword a , qword b ) { return ( ( qword ) ( vec_cmpeq ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b )


<s> SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * Subtarget -> getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( getPointerTy (


<s> if ( C . CCMask == <STR_LIT> || C . CCMask == <STR_LIT> || ( DAG . SignBitIsZero ( C . Op0 ) && DAG . SignBitIsZero ( C . Op1 ) ) ) C . ICmpType = <STR_LIT> ; else if ( C . CCMask & <STR_LIT> ) C . ICmpType = <STR_LIT> ; else C . ICmpType = <STR_LIT> ; C . CCMask &= ~ <STR_LIT> ; adjustForRedundantAnd ( DAG , DL , C ) ; adjustZeroCmp ( DAG , DL , C ) ; adjustSubwordCmp ( DAG , DL , C ) ; adjustForSubtraction ( DAG , DL , C ) ; adjustForLTGFR ( C ) ; adjustICmpTruncate ( DAG , DL , C ) ; } if ( shouldSwapCmpOperands ( C ) ) { std :: swap ( C . Op0 , C . Op1 ) ; C . CCMask = reverseCCMask ( C . CCMask ) ; } adjustForTestUnderMask ( DAG , DL , C )


<s> unsigned <ISA_LIT>TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , unsigned Depth ) const { if ( Op . getOpcode ( ) == <STR_LIT> ) return Op . getValueType ( ) . getScalarType ( ) .


<s> return ( __m256 ) __builtin_ia32_cvtudq2ps256_mask ( ( __v8si ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , (


<s> const PBQPRAGraph :: NodeMetadata :: AllowedRegVector * vRaAllowed = & G . getNodeMetadata ( node2 ) . getAllowedRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; if ( edge == G . invalidEdgeId ( ) ) { const LiveInterval & ld = LIs . getInterval ( Rd ) ; const LiveInterval & la = LIs . getInterval ( Ra ) ; bool livesOverlap = ld . overlaps ( la ) ; PBQPRAGraph :: RawMatrix costs ( vRdAllowed -> size ( ) + <NUM_LIT> , vRaAllowed -> size ( ) + <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; for ( unsigned j = <NUM_LIT> , je = vRaAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRaAllowed ) [ j ] ; if ( livesOverlap && TRI -> regsOverlap ( pRd , pRa ) ) costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] = std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) ; else costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] = haveSameParity ( pRd , pRa ) ? <NUM_LIT> : <NUM_LIT> ; } } G . addEdge ( node1 , node2 , std :: move ( costs ) ) ; return true ; } if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed , vRaAllowed ) ; } PBQPRAGraph :: RawMatrix costs ( G . getEdgeCosts ( edge ) ) ; for ( unsigned i = <NUM_LIT> , ie = vRdAllowed -> size ( ) ; i != ie ; ++ i ) { unsigned pRd = ( * vRdAllowed ) [ i ] ; PBQP :: PBQPNum sameParityMax = std :: numeric_limits < PBQP :: PBQPNum > :: min ( ) ; for ( unsigned j = <NUM_LIT> , je = vRaAllowed -> size ( ) ; j != je ; ++ j ) { unsigned pRa = ( * vRaAllowed ) [ j ] ; if ( haveSameParity ( pRd , pRa ) ) if ( costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] != std :: numeric_limits < PBQP :: PBQPNum > :: infinity ( ) && costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] > sameParityMax ) sameParityMax = costs [ i + <NUM_LIT> ] [ j + <NUM_LIT> ] ; } for ( unsigned j = <NUM_LIT> , je = vRaAllowed -> size (


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB ) { BuildCondBr ( MBB , TBB , DL , Cond ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT> ; } if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) )


<s> if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY_ATOMIC ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CRYPTO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_UPPER_REGS_DF ) != <NUM_LIT>


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ; <ISA_LIT>_MC :: initLLVMToSEHAndCVRegMapping ( X ) ; return X


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; unsigned Opt ; if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( ! hasV8Ops ( ) && ( Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> ) ) Opt = ~ <NUM_LIT> ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * MemBarrierID ; if ( getParser ( ) . parseExpression ( MemBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( MemBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Opt = <STR_LIT> + Val ; } else return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: CreateMemBarrierOpt ( ( <STR_LIT>


<s> assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; return CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; } assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm (


<s> case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( CurrGroupSize ) return <NUM_LIT> - CurrGroupSize ; return - <NUM_LIT> ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ; if ( resultingGroupSize < <NUM_LIT> ) return ( <NUM_LIT> - resultingGroupSize ) ; return -


<s> gcc_assert ( insn && ! REG_NOTES ( insn ) ) ; if ( mips_epilogue . cfa_restores ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = mips_epilogue . cfa_restores ; mips_epilogue . cfa_restores = <NUM_LIT> ; } return


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = <STR_LIT> ; unsigned ADDiu = <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < <NUM_LIT> > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( StackSize ) ; else assert ( <STR_LIT>


<s> return __extension__ ( __m64 ) ( __v2sf ) {


<s> if ( ! ( ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) || ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = N0 . getValueType ( ) ; if ( N0 . getResNo ( ) != <NUM_LIT> || InVT != <STR_LIT> || ! ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return SDValue ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; auto DivRemOpcode = OpcodeN0 == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue R = DAG . getNode ( DivRemOpcode , SDLoc ( N ) , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0


<s> return __builtin_ia32_cvttss2si ( ( __v4sf )


<s> assert ( sForm ( MI ) != <STR_LIT> ) ; const unsigned CmpOpcode = CmpInstr . getOpcode ( ) ; if ( ! isADDSRegImm ( CmpOpcode ) && !

isSUBSRegImm ( CmpOpcode ) ) return false ;


<s> O << '[' << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } if ( unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm


<s> if ( Subtarget -> isUsingPCRelativeCalls ( ) ) return false ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; const bool HasSPE = Subtarget -> hasSPE ( ) ; const TargetRegisterClass * RC ; if ( HasSPE ) RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; else RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Alignment ) ; unsigned Opc


<s> MachineOperand & <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfsOffsetOperand ( MachineInstr & LdSt ) const { assert ( LdSt . mayLoadOrStore ( ) && <STR_LIT> ) ; MachineOperand & OfsOp = LdSt . getOperand ( LdSt . getNumExplicitOperands ( ) - <NUM_LIT> ) ; assert ( OfsOp . isImm ( ) && <STR_LIT> ) ; return


<s> bool toc_relative_expr_p ( rtx op ) { int have_sym = <NUM_LIT>


<s> virtual bool isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return false


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregoiv8qi (


<s> bool <ISA_LIT>AsmParser :: expandLoadSingleImmToFPR ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmOp64 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ImmOp64 = convertIntToDoubleImm ( ImmOp64 ) ; uint32_t ImmOp32 = covertDoubleImmToSingleImm ( ImmOp64 ) ; unsigned TmpReg = <STR_LIT> ; if ( ImmOp32 != <NUM_LIT> ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; } if ( Lo_32 ( ImmOp64 ) == <NUM_LIT> ) { if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp32 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } MCSection * CS = getStreamer (


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT

&& OpIdx == - <NUM_LIT> && <STR_LIT> ) ;


<s> FeatureBits &= ~ <ISA_LIT>AssemblerOptions :: AllArchRelatedMask ; STI . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature (


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_stream_pi ( __m64 * __P , __m64 __A ) { __builtin_ia32_movntq ( ( unsigned long long * ) __P , ( unsigned long long ) __A


<s> Instruction * Load = tryCreateIncrementingGatScat ( I , Ptr , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = SelectInst :: Create ( Mask , Load , PassThru ) ; Builder . Insert ( Load ) ; } Root -> replaceAllUsesWith ( Load ) ; Root -> eraseFromParent


<s> const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TargetFlags = MO . getTargetFlags ( ) ; const Triple & TheTriple = Printer . TM . getTargetTriple ( ) ; if ( ! TheTriple . isOSBinFormatCOFF ( )


<s> case <STR_LIT> : return ! <ISA_LIT>InstrInfo :: hasExtendedReg ( * FirstMI ) ; case <STR_LIT> : case <STR_LIT> : return true ; } } if ( SecondMI . getOpcode ( ) == <STR_LIT> ) { if ( FirstMI == nullptr ) return true ; if ( FirstMI -> definesRegister ( <STR_LIT> ) ) switch ( FirstMI -> getOpcode ( ) ) { case <STR_LIT> : return ! <ISA_LIT>InstrInfo :: hasShiftedReg ( * FirstMI ) ; case <STR_LIT> : case <STR_LIT> : return ! <ISA_LIT>InstrInfo :: hasExtendedReg ( * FirstMI ) ; case <STR_LIT> : case


<s> MachineFunction & MF = * FirstMI . getParent ( ) -> getParent ( ) ; if ( ! RegClass || ! MF . getRegInfo ( ) . tracksLiveness ( ) ) return false ; auto RegToRename = getLdStRegOp ( FirstMI ) . getReg ( ) ; if ( ! getLdStRegOp ( FirstMI ) . isKill ( ) && ! any_of ( FirstMI . operands ( ) , [ TRI , RegToRename ] ( const MachineOperand & MOP ) { return MOP . isReg ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && MOP . isImplicit ( ) && MOP . isKill ( ) && TRI -> regsOverlap ( RegToRename , MOP . getReg ( ) ) ; } ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FirstMI << <STR_LIT> ) ; return false ; } auto canRenameMOP = [ ] ( const MachineOperand & MOP ) { return MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) && ! MOP . isTied ( ) ) ; } ; bool FoundDef = false ; std :: function < bool ( MachineInstr & , bool ) > CheckMIs = [ & ] ( MachineInstr & MI , bool IsDef ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> && Value <= <NUM_LIT>


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF )


<s> return isBareImm ( isInt < <NUM_LIT> >


<s> const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { return matchCPURegisterName ( Parser . getLexer ( ) . peekTok ( ) . getString ( ) ) == - <NUM_LIT> ? MatchOperand_ParseFail : MatchOperand_NoMatch ; } if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; if ( ! MCE


<s> MCSym = getCurExceptionSym ( ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( Op


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) { addExpr ( Inst ,


<s> ErrMsg = <STR_LIT> ; return true ; } IC . popOperator ( ) ; } else if ( ( PrevState == IES_PLUS || PrevState == IES_MINUS || PrevState == IES_OR || PrevState == IES_AND || PrevState == IES_LSHIFT || PrevState == IES_RSHIFT || PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE || PrevState == IES_LPAREN || PrevState == IES_LBRAC ) && CurrState == IES_MINUS ) { IC . pushOperand ( IC_IMM , - TmpInt ) ; } else { IC . pushOperand ( IC_IMM ,


<s> for ( MachineBasicBlock * S : MBB -> predecessors ( ) ) if ( S == PrevBB && ! TII -> AnalyzeBranch ( * PrevBB , TBB , FBB , Cond ) && ! TBB && ! FBB ) return S ; return nullptr


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) . getSimpleVT ( ) , DAG . getConstant ( <NUM_LIT> , Op . getValueType ( ) . getSimpleVT ( ) )


_mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static TargetLoweringObjectFile * createTLOF ( <ISA_LIT>TargetMachine & TM ) { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isTargetLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ; if ( Subtarget -> isTargetELF ( )

) return new TargetLoweringObjectFileELF ( ) ;


<s> Register <ISA_LIT>FunctionInfo :: getGlobalBaseReg ( MachineFunction & MF , bool IsForTls ) { if ( IsForTls ) UsesTlsViaGlobalReg = true ; else assert ( ! static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . useCheriCapTable ( ) && <STR_LIT> ) ; if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg


<s> OperandMatchResultTy parseAR32 ( OperandVector


<s> layout . register_save_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( current_function_stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = <NUM_LIT> ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( current_function_args_size <= <NUM_LIT> && current_function_args_size != - <NUM_LIT> ) { if ( layout . frame_size + INCOMING_FRAME_SP_OFFSET + current_function_args_size <= <NUM_LIT> ) layout .


<s> static void EmitBinary ( MCStreamer & OutStreamer , unsigned Opcode , MCOperand & RS1 , MCOperand & Src2 , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst Inst ; Inst . setOpcode ( Opcode ) ; Inst . addOperand ( RD ) ; Inst . addOperand ( RS1