<s> Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; SmallString < <NUM_LIT> > Key ; unsigned MinSVEVectorSize = <NUM_LIT> ; unsigned MaxSVEVectorSize = <NUM_LIT> ; Attribute VScaleRangeAttr = F . getFnAttribute ( Attribute :: VScaleRange ) ; if ( VScaleRangeAttr . isValid ( ) ) { std :: tie ( MinSVEVectorSize , MaxSVEVectorSize ) = VScaleRangeAttr . getVScaleRangeArgs ( ) ; MinSVEVectorSize *=


<s> if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . disp && parts . disp != const0_rtx ) cost -- ; if ( parts . seg != SEG_DEFAULT ) cost -- ; if ( ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) ) || ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) ) ) cost ++ ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && parts . index && ( ! REG_P ( parts . index ) || REGNO (

parts . index ) >= FIRST_PSEUDO_REGISTER ) && parts . base != parts . index ) cost ++ ;


<s> if ( name . startswith ( <STR_LIT> ) ) return true ; if ( name . startswith ( <STR_LIT> ) ) return true ; if ( name . startswith ( <STR_LIT>


<s> Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FinalStackPtr ) . addReg ( physSPReg ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; const unsigned XORMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( XORMIOpc ) ) , physSPReg , false


<s> if ( isLd && TID . mayStore ( ) ) return false ; if ( ! isLd ) { if ( TID . mayLoad ( ) ) return false ; if ( TID . mayStore ( ) ) return false ; } for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( )


<s> mnemonic = info . insn == simd_immediate_info :: MVN ? <STR_LIT> : <STR_LIT> ; shift_op = info . modifier == simd_immediate_info :: MSL ? <STR_LIT> : <STR_LIT> ; if ( lane_count == <NUM_LIT> ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX , mnemonic , UINTVAL ( info . value ) ) ; else if ( info . shift ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX <STR_LIT> , mnemonic , lane_count , element_char , UINTVAL ( info . value ) , shift_op , info . shift ) ; else snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX , mnemonic , lane_count , element_char , UINTVAL ( info . value ) ) ; } else { mnemonic = info . insn == simd_immediate_info ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) { if ( getRelocationModel ( ) == Reloc :: Default ) setRelocationModel ( Reloc


<s> case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } SDValue result


<s> unsigned Opcode = TII -> getLoadAndTest ( MI . getOpcode ( ) ) ; if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , Opcode ) ) return false ; auto MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( Opcode ) ) ; for ( const auto & MO : MI . operands ( ) )


<s> static bool tryToreplicateChunks ( uint64_t UImm , MachineInstr & MI , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const <ISA_LIT>InstrInfo * TII ) { typedef DenseMap < uint64_t , unsigned > CountMap ; CountMap Counts ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) ++ Counts [ getChunk ( UImm , Idx ) ] ; for ( CountMap :: const_iterator Chunk = Counts . begin ( ) , End = Counts . end ( ) ; Chunk != End ; ++ Chunk ) { const uint64_t ChunkVal = Chunk -> first ; const unsigned Count = Chunk -> second ; uint64_t Encoding = <NUM_LIT> ; if ( ( Count != <NUM_LIT> && Count != <NUM_LIT> ) || ! canUseOrr ( ChunkVal , Encoding ) ) continue ; const bool CountThree = Count == <NUM_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( Encoding ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && CountThree ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ; if ( CountThree ) { transferImpOps ( MI , MIB , MIB1 ) ; MI . eraseFromParent ( ) ; return true ; } for ( ShiftAmt += <NUM_LIT> ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } MachineInstrBuilder MIB2 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ; transferImpOps ( MI , MIB , MIB2 ) ; MI . eraseFromParent ( ) ; return


<s> assert ( PairedRegOp < <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = isPairedLdSt ( MI ) ? PairedRegOp : <NUM_LIT> ; return MI . getOperand ( Idx


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI


<s> if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Alignment . value ( ) ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( IsPositionIndependent ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( IsPositionIndependent ) { unsigned Opc = IsIndirect ? <STR_LIT> :


<s> void addFPR8asZPRRegOperands ( MCInst & Inst ,


<s> return parseIdentifier ( ) ; case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : if ( ! Parser . parseExpression ( ExprVal ) ) return <STR_LIT> ( ExprVal , Start , End ) ; LLVM_FALLTHROUGH ; default : return nullptr


<s> MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate (


<s> return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } if ( lang_GNU_C ( ) && VECTOR_BOOLEAN_TYPE_P ( type ) ) type = build_variant_type_copy ( type ) ; else type = build_distinct_type_copy ( type ) ; TYPE_ATTRIBUTES ( type ) = remove_attribute ( <STR_LIT> , copy_list ( TYPE_ATTRIBUTES ( type ) ) ) ; if ( ! VECTOR_BOOLEAN_TYPE_P ( type ) ) TYPE_INDIVISIBLE_P ( type ) = <NUM_LIT> ; * node = type ; return NULL_TREE


<s> unsigned TargetAlign = Target . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign -


<s> } src = DECL_RTL ( fpscr_values ) ; if ( no_new_pseudos ) { emit_move_insn ( scratch , XEXP ( src , <NUM_LIT> ) ) ; if ( index != <NUM_LIT> ) emit_insn ( gen_addsi3 ( scratch , scratch , GEN_INT ( index * <NUM_LIT> ) ) ) ; src = adjust_automodify_address ( src , PSImode , scratch , index * <NUM_LIT> ) ; } else src = adjust_address ( src , PSImode , index * <NUM_LIT> ) ; dst = get_fpscr_rtx ( ) ; emit_move_insn ( dst ,


<s> const MCOperand & Imm = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT>


<s> } break ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) if ( tryRxSBG ( Node , <STR_LIT> ) ) return ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( tryRISBGZero ( Node ) ) return ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) { splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; return ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode (


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; saved_size += <NUM_LIT> ; } if ( TARGET_HARD_FLOAT && TARGET_VFP ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += <NUM_LIT> ) { if ( ( ! df_regs_ever_live_p ( reg ) || call_used_regs [ reg ] ) && ( ! df_regs_ever_live_p ( reg + <NUM_LIT> ) || call_used_regs [ reg + <NUM_LIT> ] ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg ,


<s> if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const auto & WinEHXMMSlotInfo = <ISA_LIT>FI


<s> MachineBasicBlock * NewMBB = emitBlockAfter ( MBB ) ; NewMBB -> splice ( NewMBB -> begin ( ) , MBB , MI , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; return NewMBB


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createDPairNode ( SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( )


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT>


<s> vmlal_high_s8 ( int16x8_t a , int8x16_t b , int8x16_t c ) { int16x8_t result


<s> return DAG . getNode ( <STR_LIT> , DL


* <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue Glue ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , GOT , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , GOTOffset , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getTargetGlobalAddress ( Node -> getGlobal ( ) , DL , Node -> getValueType ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT>


<s> if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT> ) ) { SDValue S = V . getOperand ( Idx ) ; if ( EltVT . getSizeInBits ( ) == S . getSimpleValueType ( ) . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( V ) , EltVT , S ) ; } return SDValue (


<s> MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , DL , VT


<s> case HS : return LO ; case LO : return HS ; case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC : return


<s> void printMemOffs16 ( const MCInst * MI ,


<s> assert ( CurDAG -> getTargetLoweringInfo ( ) . getPointerTy ( CurDAG -> getDataLayout ( ) ) . getSizeInBits ( )


<s> int regno ; if ( ! REG_P ( x ) ) return <NUM_LIT> ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB1_REGNO_MODE_OK_FOR_BASE_P ( regno , mode ) ; return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> && ( regno == STACK_POINTER_REGNUM

|| regno >= FIRST_PSEUDO_REGISTER || x == hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( & MBB , DL , MCID ) ; for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) { if ( Cond [ i ] . isReg ( ) ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; else if ( Cond [ i ] . isImm ( ) ) MIB . addImm ( Cond [ i ] . getImm ( ) ) ; else assert ( false && <STR_LIT> ) ; } MIB . addMBB ( TBB


<s> unsigned Reg = CPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> if ( Subtarget . hasSSE2 ( ) && <STR_LIT> ( Op . getNode ( ) ) ) { if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasInt256 ( ) ) ) return Op ; if ( ! VT . is512BitVector ( ) ) return getOnesVector ( VT


<s> return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo -> getSlotSize (


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { if ( ! T . isOSBinFormatELF ( ) )


<s> else sprintf ( buffer , <STR_LIT> , inverted_p ? inverted_comp : comp , need_z_p ? <STR_LIT> : <STR_LIT> , op1 , op2 ) ; return buffer ; case <NUM_LIT> : case <NUM_LIT> : { const char * target = ( ( iq2000_branch_likely || length == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; char * c ; c = strchr ( buffer , '\0' ) ; if ( float_p ) sprintf ( c , <STR_LIT> , inverted_p ? comp : inverted_comp , target ) ; else sprintf ( c , <STR_LIT> , inverted_p ? comp : inverted_comp , need_z_p ? <STR_LIT> : <STR_LIT> ,


__artificial__ ) ) _mm_cvtsi32_si128 ( int __A ) {


<s> unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = MRI . createVirtualRegister ( RC ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg


<s> if ( ! SafeToClobberCPSR ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) { NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; } else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return false ; if ( isThumb1 ) { if ( Base != NewBase && Offset >= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; Base = NewBase ; BaseKill = false ; } AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) , true ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } Base = NewBase ; BaseKill = true ; } bool isDef = ( isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode , Mode ) ; if ( ! Opcode ) return false ; bool Writeback = isThumb1 ; if ( Opcode == <STR_LIT> && isThumb1 ) for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) if ( Base == Regs [ I ] . first ) { Writeback = false ; break ; } if ( isThumb1 && Writeback && ! BaseKill ) return false ; MachineInstrBuilder MIB ; if ( Writeback ) { if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill


<s> Result = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; } if ( Alignment && * Alignment > StackAlign ) Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , DAG . getConstant ( ~ ( Alignment -> value ( ) - <NUM_LIT> ) , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Result ) ; } else if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; for ( const auto & A : F . args ( ) ) { if ( A . hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; Register Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Size ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setHasWinAlloca ( true ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ; if ( Alignment ) { SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( ~ ( Alignment -> value ( ) - <NUM_LIT> ) , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addFrameIndex


<s> DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return


<s> static SDValue performSRLCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Ty != <STR_LIT> ) || ! Subtarget -> hasDSPR2 ( ) ) && ( Ty != <STR_LIT> ) ) return SDValue ( ) ; return performDSPShiftCombine ( <STR_LIT> , N ,


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) ==


<s> else if ( size == INIT_ARRAY_ENTRY_BYTES && aligned_p && text_segment_operand ( x , VOIDmode ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> , asm_out_file ) ; return


<s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return


<s> OperandMatchResultTy parseBDAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , BDMem


<s> } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * GVSym ; else O << '(' << * GVSym << ')' ; printOffset ( MO . getOffset ( ) , O ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const MCSymbol * SymToPrint ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) , true ) ; } SymToPrint = StubSym . getPointer ( ) ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * SymToPrint ; else O << '(' << * SymToPrint << '(' ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> << * MF -> getPICBaseSymbol ( ) << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' << * MF -> getPICBaseSymbol ( ) ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O


) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> return MCDisassembler :: Fail ; } Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler ::


<s> void <ISA_LIT>InstrInfo :: getNoop ( MCInst & NopInst ) const { NopInst . setOpcode (


<s> return ( uint16x4_t ) __builtin_neon_vpadaluv8qi ( ( int16x4_t ) __a , (


<s> bool hasCn<ISA_LIT> ( ) const { return ( STI . getFeatureBits ( ) [


<s> Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDLoc ( Node ) ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * Subtarget -> getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F =


<s> return ; } if ( TARGET_MIPS16 ) { mips_emit_move ( temp , mips_cprestore_slot ( temp , true ) ) ; mips_emit_move ( pic_offset_table_rtx ,


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_64BIT ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_64BIT ) ? CODE_FOR_htm_mtspr_di


<s> av = ( vec_int4 ) ( a ) ; return ( ( qword ) ( vec_perm ( av , vec_sra ( av , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT>

, <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ;


<s> ArgInfos . push_back ( AInfo ) ; OrigArgIndices . push_back ( i ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Ins ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; if ( F . isVarArg ( ) ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetVarArgRegs ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; int VaArgOffset ; unsigned RegSize = <NUM_LIT> ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( CCInfo . getCallingConv ( ) ) - ( int ) ( RegSize * ( ArgRegs . size ( ) - Idx ) ) ; } MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( RegSize , VaArgOffset , true ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSize ) { MIRBuilder . getMBB ( ) . addLiveIn ( ArgRegs [ I ] ) ; MachineInstrBuilder Copy = MIRBuilder . buildCopy ( LLT :: scalar ( RegSize * <NUM_LIT> ) , Register ( ArgRegs [ I ] ) ) ; FI = MFI . CreateFixedObject ( RegSize , VaArgOffset , true ) ; MachinePointerInfo MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineInstrBuilder FrameIndex = MIRBuilder . buildFrameIndex ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT> ) , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , RegSize , Align ( RegSize ) ) ; MIRBuilder . buildStore ( Copy , FrameIndex , * MMO ) ; } } return true


<s> return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G3


<s> return ( uint64x2_t ) __builtin_neon_vsubwuv2si ( ( int64x2_t


<s> static DecodeStatus DecodeTS1AMI64 ( MCInst & MI , uint64_t insn , uint64_t Address , const void * Decoder ) { return DecodeCAS ( MI , insn , Address , Decoder , false ,


<s> bool SrcIsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; bool IsZExt = isa < ZExtInst > ( I ) ; if ( const auto * Arg = dyn_cast < Argument > ( I -> getOperand ( <NUM_LIT> ) ) ) { if ( ( IsZExt && Arg -> hasZExtAttr ( ) ) || ( ! IsZExt && Arg -> hasSExtAttr ( ) ) ) { if ( RetVT == <STR_LIT> && SrcVT != <STR_LIT> ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) . addImm ( <STR_LIT> ) ; SrcReg = ResultReg ; } unsigned UseReg = lookUpRegForValue ( I ) ; if ( UseReg ) MRI . clearKillFlags ( UseReg ) ; updateValueMap ( I , SrcReg ) ; return true ; } } unsigned ResultReg = emitIntExt ( SrcVT , SrcReg , RetVT ,


<s> unsigned int nds32_debugger_regno ( unsigned int regno ) { if ( NDS32_IS_FPR_REGNUM ( regno ) ) return


<s> void setSRetReturnReg ( Register Reg


<s> break ; default : gcc_unreachable ( ) ; } for ( i = <NUM_LIT> ; i < n ; i ++ ) { op0 = gen_reg_rtx ( SImode ) ; emit_move_insn ( op0 , gen_lowpart ( SImode , ops [ i + i ] ) ) ; op1 = gen_reg_rtx ( V4SImode ) ; op0 = gen_rtx_VEC_MERGE ( V4SImode , gen_rtx_VEC_DUPLICATE ( V4SImode , op0 ) , CONST0_RTX ( V4SImode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( op1 , op0 ) ) ; op0 = gen_reg_rtx ( mode ) ; emit_move_insn ( op0 , gen_lowpart ( mode , op1 ) ) ; emit_insn ( gen_load_even ( op0 , force_reg ( inner_mode , ops [ i + i + <NUM_LIT> ] ) , const1_rtx ) ) ; ops [ i ] = gen_reg_rtx ( first_imode ) ; emit_move_insn ( ops [ i ] , gen_lowpart ( first_imode , op0 ) ) ; } for ( i = j = <NUM_LIT> ; i < n ; i += <NUM_LIT> , j ++ ) { op0 = gen_reg_rtx ( first_imode ) ; emit_insn ( gen_interleave_first_low ( op0 , ops [ i ] , ops [ i + <NUM_LIT> ] ) ) ; ops [ j ] = gen_reg_rtx ( second_imode ) ; emit_move_insn ( ops [ j ] , gen_lowpart ( second_imode , op0 ) ) ; } switch ( second_imode ) { case V4SImode : for ( i = j = <NUM_LIT> ; i < n / <NUM_LIT> ; i += <NUM_LIT> , j ++ ) { op0 = gen_reg_rtx ( second_imode ) ; emit_insn ( gen_interleave_second_low ( op0 , ops [ i ] , ops [ i + <NUM_LIT> ] ) ) ; ops [ j ] = gen_reg_rtx ( third_imode ) ; emit_move_insn ( ops [ j ] , gen_lowpart ( third_imode , op0 ) ) ; } second_imode = V2DImode ; gen_interleave_second_low = gen_vec_interleave_lowv2di ; case V2DImode : op0 = gen_reg_rtx ( second_imode ) ; emit_insn ( gen_interleave_second_low ( op0 , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( target , gen_lowpart (


<s> static SDValue LowerCTPOP ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget ,


<s> case GPRRegClassID : case tGPR_and_tcGPRRegClassID : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT>


<s> <ISA_LIT>ExSectionTuple * exTuple = it -> second . get ( ) ; LDSection * const text = exTuple -> getTextSection ( ) ; LDSection * const exIdx = exTuple -> getExIdxSection ( ) ; if ( ( text -> kind ( ) == LDFileFormat :: Ignore ) || ( text -> kind ( ) == LDFileFormat :: Folded ) ) { exIdx -> setKind ( LDFileFormat :: Ignore ) ; <STR_LIT> deadIt = it ++ ; exMap -> erase ( deadIt ) ; continue ; } RegionFragment * textFrag = findRegionFragment ( * text ) ; RegionFragment * exIdxFrag = findRegionFragment ( * exIdx ) ; exTuple -> setTextFragment ( textFrag ) ; exTuple -> setExIdxFragment ( exIdxFrag ) ; if ( exIdxFrag == NULL ) { <STR_LIT> deadIt = it ++


<s> return __builtin_mve_vhaddq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> SDValue <ISA_LIT>TargetLowering :: LowerBSWAP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op .


<s> AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis


<s> rtx set = gen_rtx_SET ( Pmode , src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && MEM_P ( dest ) && ( ! CONST_INT_P ( XEXP ( dest , <NUM_LIT> ) ) || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) && ! xstormy16_below100_operand ( dest

, mode ) && ! REG_P ( src ) && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ;


<s> return parseAddress ( Operands , <STR_LIT> ,


<s> if ( ScaleLog <= <NUM_LIT> || ScaleLog >= <NUM_LIT> || Mask != ( <NUM_LIT> << ScaleLog ) ) return true ; EVT VT = N . getValueType ( ) ; SDLoc DL ( N ) ; SDValue Eight = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue NewMask = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , DL , VT , X , Eight ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , Srl , NewMask ) ; SDValue ShlCount = DAG . getConstant ( ScaleLog , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , And , ShlCount ) ; InsertDAGNode ( DAG , N , Eight ) ; InsertDAGNode ( DAG , N , Srl ) ; InsertDAGNode ( DAG , N


<s> void addSysCROperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> { <STR_LIT> :: fixup_csky_addr32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_pcrel_imm16_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_uimm16_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_imm26_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_imm18_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } } ; assert ( Infos . size ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; if ( FirstTargetFixupKind <= Kind && Kind < FirstLiteralRelocationKind ) return Infos [ Kind ] ; else if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; else return MCAsmBackend :: getFixupKindInfo ( FK_NONE


<s> } else { if ( helper_use_relative_reloc ( * rsym , pParent ) ) { got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; Relocation & rel_entry = helper_DynRela_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_AARCH64_RELATIVE , pParent ) ; rel_entry . setAddend ( <ISA_LIT>Relocator :: SymVal ) ; pParent . getRelRelMap ( ) . record ( pReloc , rel_entry ) ; } else { helper_DynRela_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_AARCH64_GLOB_DAT , pParent ) ; got_entry -> setValue ( <NUM_LIT> ) ; } } return * got_entry


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; if ( isa < BuildVectorSDNode > ( Op1 ) ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Op1 ) ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; unsigned SVTBits = SVT . getSizeInBits ( ) ; ConstantSDNode * CND = cast < ConstantSDNode > ( Op1 ) ; const APInt & C = APInt ( SVTBits , CND -> getAPIntValue ( ) . getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) return SDValue ( ) ; if ( ShAmt == <NUM_LIT> ) return Op0 ; SDValue Splat = DAG . getConstant ( C , VT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) ,


<s> unsigned RegLo = TRI -> getSubReg ( Reg . getReg ( ) , <STR_LIT> ) ; unsigned RegHi = TRI -> getSubReg ( Reg . getReg ( ) , <STR_LIT> ) ; MIB . addReg ( RegLo , Flags | getKillRegState (


<s> if ( Depth == <NUM_LIT> ) return SDValue ( ) ; SDValue V = SDValue ( N , <NUM_LIT> ) ; EVT VT = V . getValueType ( ) ; unsigned Opcode = V . getOpcode ( ) ; if ( const ShuffleVectorSDNode * SV = dyn_cast < ShuffleVectorSDNode > ( N ) ) { int Elt = SV -> getMaskElt ( Index ) ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? SV -> getOperand ( <NUM_LIT> ) : SV -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getValueType ( ) . getSimpleVT ( ) ; unsigned NumElems = ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( ShufVT . getVectorElementType ( ) ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N ->


<s> inline vector signed short vec_vavgsh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vavgsh ( ( vector signed short )


<s> if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; Peephole<ISA_LIT>64 (


<s> return new <ISA_LIT>FastTileConfig (


<s> auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL


<s> SDValue ResNode ; SDValue HiPart ; DebugLoc dl = Op . getDebugLoc ( ) ; bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; unsigned char OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if (


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI ==

ABI_DARWIN ) && flag_pic ) return true ;


<s> } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_TPREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_PCREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_PCREL ; const MachineInstr * MI = MO . getParent ( ) ; const MachineFunction * MF = MI -> getMF ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; unsigned MIOpcode = MI -> getOpcode ( ) ; assert ( ( Subtarget -> isUsingPCRelativeCalls ( ) || MIOpcode != <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget -> isUsingPCRelativeCalls ( ) ) { if ( MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> ) { RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx


<s> for ( unsigned int i = <NUM_LIT> ; i < <ISA_LIT>GOT0Num ; ++ i ) new <ISA_LIT>GOTEntry ( <NUM_LIT>


<s> bool <ISA_LIT>FastISel :: SelectStore ( const Instruction * I ) { Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; unsigned SrcReg = <NUM_LIT> ; if ( cast < StoreInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isLoadTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( )


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugValue


<s> if ( ( Ty != <STR_LIT> ) && ( Ty != <STR_LIT> ) ) return SDValue ( ) ; return performDSPShiftCombine ( <STR_LIT> , N , Ty ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( MAI ,


<s> if ( TT . isOSBinFormatMachO ( ) ) return make_unique <


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) return *


<s> if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Amt ) ; } return SDValue (


<s> if ( is<ISA_LIT>64 ( ) ) return <NUM_LIT> ; return isAIXABI ( ) ?


<s> switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : case PLUS : case MINUS : case COMPARE : case NEG : case NOT : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MULT : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { int cycles = <NUM_LIT> ; unsigned HOST_WIDE_INT i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; while ( i ) { i >>= <NUM_LIT> ; cycles ++ ; } return COSTS_N_INSNS ( <NUM_LIT> ) + cycles ; } return COSTS_N_INSNS ( <NUM_LIT> ) + <NUM_LIT> ; case SET : return ( COSTS_N_INSNS ( <NUM_LIT> ) + <NUM_LIT> * ( ( GET_CODE ( SET_SRC ( x ) ) == MEM ) + GET_CODE ( SET_DEST ( x ) ) == MEM ) ) ; case CONST_INT : if ( outer == SET ) { if ( ( unsigned HOST_WIDE_INT ) INTVAL ( x ) < <NUM_LIT> ) return <NUM_LIT> ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT>


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ; } return


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> ) , Subtarget , DAG , SDLoc ( N ) ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; } } return SDValue


<s> vrev32q_p16 ( poly16x8_t a ) { return __builtin_shuffle ( a , ( uint16x8_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & Ctx_ , bool IsLittle ) : MCII ( mcii ) , Ctx ( Ctx_ ) , IsLittleEndian


<s> auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel ) ; SM . recordStackMap ( * MILabel , MI ) ; assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII ; while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII -> getOpcode ( ) == TargetOpcode

:: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ;


<s> case V8HImode : case V4SImode : case V2DImode : case V1TImode : case TImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; rtx d ; srcmode = mode_for_size ( size , MODE_INT , <NUM_LIT> ) ; switch ( srcmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } if ( pos & ( size - <NUM_LIT> ) ) return false ; if ( SUBREG_P ( src ) ) { unsigned int srcpos = SUBREG_BYTE ( src ) ; if ( srcpos > <NUM_LIT> ) { rtx extr_ops [ <NUM_LIT> ] ; extr_ops [ <NUM_LIT> ] = gen_reg_rtx ( srcmode ) ; extr_ops [ <NUM_LIT> ] = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; extr_ops [ <NUM_LIT> ] = GEN_INT ( size ) ; extr_ops [ <NUM_LIT> ] = GEN_INT ( srcpos * BITS_PER_UNIT ) ; if ( ! ix86_expand_pextr ( extr_ops ) ) return false ; src = extr_ops [ <NUM_LIT> ] ; } else src = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; } if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx


<s> assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned SrcKill = getKillRegState ( I -> getOperand


<s> return ( poly8x8_t ) __builtin_neon_vld1_lanev8qi ( ( const __builtin_neon_qi * ) __a , ( int8x8_t )


<s> if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory .


<s> void printQuadRegOff ( const MachineInstr * MI , int opNum


<s> case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; default : return false


<s> else Opc = isSub ? getSUBriOpcode ( Is64BitStackPtr , Offset ) : getADDriOpcode ( Is64BitStackPtr , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = Is64BitTarget ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64BitTarget ) : getADDrrOpcode ( Is64BitTarget ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset = <NUM_LIT> ; continue ; } } uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64BitTarget ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = isSub ? ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg ,

getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ;


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) &&


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask


<s> MapRegToId RegToId ; MapIdToReg IdToReg ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( <ISA_LIT>FI && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; collectInvolvedReg ( MF , RegToId , IdToReg , TRI ) ; if ( RegToId . empty ( ) ) return false ; MachineInstr * DummyOp = nullptr ; if ( BasicBlockScopeOnly ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; DummyOp = MF . CreateMachineInstr ( TII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ; } unsigned NbReg = RegToId . size ( ) ; bool Modified = false ; InstrToInstrs * ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , true , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> void \ sbss_section ( ) \ { \ if ( in_section != in_sbss ) \ { \ fprintf ( asm_out_file

, <STR_LIT> , SBSS_SECTION_ASM_OP ) ; \ in_section = in_sbss ; \ } \ }


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( JT ) , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ,


<s> return create<ISA_LIT>MachObjectWriter ( OS , true , MachO :: CPU_TYPE_<ISA_LIT>_64 , MachO


<s> bool hasDFPPackedConversion ( ) const { return HasDFPPackedConversion


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> return ( uint64x2_t ) __builtin_neon_vcombinedi ( ( int64x1_t ) __a , (


<s> return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue (


<s> if ( x == <NUM_LIT> ) return false ; } else x = PATTERN ( x ) ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( global_reg_mentioned_p_1 ( *


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) || TT . isOSWindows ( ) || TT . isOSNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT>


<s> OperandMatchResultTy parseADDR128 ( SmallVectorImpl < MCParsedAsmOperand *


<s> return by_pieces_ninsns ( size , align , MOVE_MAX_PIECES + <NUM_LIT> , op ) < ( ! speed_p ? <NUM_LIT> : ( align >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; case STORE_BY_PIECES : case


<s> CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= RemoveUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= HandleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= FixUpImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= OptimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= UndoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [


<s> add_vector_labels ( file , <STR_LIT> ) ; if ( is_fast_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ; if ( is_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT>


<s> SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; MVT castType = getFullRegisterType ( VT ) ; SDValue transA = DAG . getNode ( <STR_LIT> , dl , castType , A ) ; SDValue transB = DAG . getNode ( <STR_LIT> , dl , castType , B ) ; SDValue res


<s> return SSE_REGNO_P ( regno ) && GET_MODE_SIZE


<s> rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx src ; if ( VAL_14_BITS_P ( disp ) ) src = gen_rtx_MEM ( word_mode , plus_constant ( basereg , disp ) ) ; else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmpreg , delta ) ; if ( TARGET_DISABLE_INDEXING )


<s> } SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; } if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDValue In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; if ( Subtarget . hasHighWord ( ) ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { const SMLoc consumedToken = consumeToken ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return true ; } else


<s> if ( TARGET_P9_VECTOR ) return <NUM_LIT> ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode

& Mode , RegClassVector & CriticalPathRCs ) const {


<s> else gcc_unreachable ( ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( offset , <NUM_LIT> , <NUM_LIT> ) ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( GET_CODE ( offset ) == PLUS && GET_CODE ( XEXP ( offset , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( offset , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TOCREL && CONST_INT_P ( XEXP ( offset , <NUM_LIT> ) ) ) { rtx tocrel_unspec = XEXP ( offset , <NUM_LIT> ) ; if ( TARGET_ELF ) sprintf ( insn_template , <STR_LIT> , insn_str ) ; else if ( TARGET_XCOFF ) sprintf ( insn_template , <STR_LIT> , insn_str ) ; else gcc_unreachable ( ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( tocrel_unspec , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XEXP ( offset , <NUM_LIT> ) ; output_asm_insn ( insn_template ,


<s> std :: string getNextReturnSiteMagicPrivate


<s> Value * <ISA_LIT>IREmitter :: visitAND (


<s> static unsigned computeReturnSaveOffset ( const <ISA_LIT>Subtarget & STI ) { if ( STI . isDarwinABI ( ) ) return STI . is<ISA_LIT>64


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! isX87Instruction ( * MI ) ) continue ; if ( ! ( MI -> mayRaiseFPException ( ) || MI -> mayLoadOrStore ( ) ) || isX87ControlInstruction ( * MI ) ) continue ; MachineBasicBlock :: iterator AfterMI = std :: next ( MI ) ; if ( AfterMI != MBB . end ( ) && isX87Instruction ( * AfterMI ) && ! isX87NonWaitingControlInstruction ( * AfterMI ) ) continue ; BuildMI ( MBB , AfterMI , MI -> getDebugLoc ( )


<s> static DecodeStatus DecodeDDDDRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; MI -> eraseFromParent ( ) ; return exitMBB


<s> static inline bool isLEASimpleIncOrDec ( MachineInstr & LEA ) { unsigned SrcReg = LEA . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; unsigned DstReg = LEA . getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>FunctionInfo :: shouldSignReturnAddress ( ) const { return shouldSignReturnAddress ( llvm :: any_of ( MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) , [ ] ( const auto & Info ) { return Info


<s> if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> ) ; return false


<s> assert ( ( Kind == RegisterList || Kind == DPRRegisterList || Kind == SPRRegisterList )


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , Flag , MFI . getObjectSize ( FI


<s> int i ; if ( dest_start < src_start ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , dest_start + i ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , src_start + i ) ; output_asm_insn ( <STR_LIT> , ops ) ; } } else { for ( i = <NUM_LIT> ; i


<s> static inline int is_multilib_enabled ( struct loongarch_abi abi ) { return enabled_abi_types [ abi . base ] [ abi . ext


<s> Value * <ISA_LIT>IREmitter :: visitFMINC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout += <STR_LIT> ; dataLayout +=


<s> Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> RegIdx . Tok . Data = Str . data ( ) ; Op -> RegIdx . Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : { <ISA_LIT>MCExpr :: VariantKind RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_ABS && <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_SABS ) { if ( ! RefKind ) { if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( SignedValue < <NUM_LIT> ) SignedValue = ~ SignedValue ; Value = static_cast < uint64_t > ( SignedValue ) ; } else Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( ! IsResolved ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS ) { switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G3 : SignedValue = SignedValue >> <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : Value = Value >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : Value = Value >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G3 : Value = Value >> <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( RefKind & <ISA_LIT>MCExpr :: VK_NC ) { Value &= <NUM_LIT> ; } else if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS ) { if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup .


<s> for ( i = <NUM_LIT> , num_regs = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { gcc_assert ( ! IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) ; if ( arm_current_function_pac_enabled_p ( ) ) { gcc_assert ( ! ( saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ) ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; emit_insn ( gen_aut_nop ( ) ) ; emit_jump_insn ( simple_return_rtx ) ; } else if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { if ( IS_CMSE_ENTRY ( arm_current_func_type (


<s> unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( OR ) , RA ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) , SP ) . addReg ( SP ) . addReg ( OffsetReg ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( JR


<s> int RegNo = ( int ) ( UseIdx + <NUM_LIT> ) - UseMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( UseClass , UseIdx ) ; int UseCycle ; if ( Subtarget . isCortexA8 ( ) ) { UseCycle = RegNo / <NUM_LIT> + <NUM_LIT> ; if ( RegNo % <NUM_LIT> ) ++ UseCycle ; } else if ( Subtarget . isCortexA9 ( ) ) { UseCycle = RegNo ; bool isSStore =


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getT2AddrModeImm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Reg , Imm8 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO .


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; return known_eq ( cfun -> machine -> frame . frame_size ,


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return CE -> getValue ( ) >= - ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) )

&& CE -> getValue ( ) < ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) ;


<s> return __builtin_aarch64_sminv2df ( __a ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr16MM ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable (


<s> } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , Name , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned Opt = Mapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT>


<s> FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs , NumFPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant


<s> RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = &


<s> unsigned Major , Minor , Micro ; TT . getOSVersion ( Major , Minor , Micro ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> + RegNo


<s> assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr


<s> int sp_adjust ; if ( ! reload_completed ) return <NUM_LIT> ; if ( cfun -> machine -> attr_naked_p && ! flag_ret_in_naked_func ) return <NUM_LIT> ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && (

cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return <NUM_LIT> ;


<s> void addFPImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( getFPImm ( ) .


<s> for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty


<s> return SupportsCU ? generateCompactUnwindEncodingImpl ( Instrs )


<s> vqmovun_high_s16 ( uint8x8_t a , int16x8_t b ) { uint8x16_t result = vcombine_u8 ( a , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) )


<s> static SDValue CreateFPCmp ( SelectionDAG & DAG , const SDValue & Op ) { if ( Op . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( ! LHS . getValueType ( ) . isFloatingPoint ( ) ) return Op ; SDValue RHS = Op .


<s> break ; case <STR_LIT> : { APInt KnownZero2 , KnownOne2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; KnownZero &= KnownZero2 ; KnownOne &= KnownOne2 ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarType ( ) . getSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case


<s> SmallVector < SDValue , <NUM_LIT> > Uniques ( V -> op_begin ( ) , V -> op_end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue Op = Uniques [ i ] ; if ( Op . isUndef ( ) ) continue ; Mask [ i ] = i ; if ( <STR_LIT> ( Op ) ) continue ; for ( unsigned j = i + <NUM_LIT> ; j != NumElts ; ++ j ) if ( Op == Uniques [ j ] ) { HasRepeatedElts = true ; Mask [ j ] = i ; Uniques [ j ] = DAG . getUNDEF ( VT . getScalarType ( ) ) ; } } if ( ! HasRepeatedElts ) return SDValue ( ) ; SDLoc DL ( V


<s> static inline bool isAdvSIMDModImmType1 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ getReg ( )


<s> unsigned Opc = MI . getOpcode ( ) ; assert ( Opc == TargetOpcode :: G_ASHR || Opc == TargetOpcode :: G_LSHR ) ; unsigned NewOpc = Opc == TargetOpcode :: G_ASHR ? <STR_LIT> : <STR_LIT> ; MachineIRBuilder MIB ( MI )


<s> DebugLoc dl = I == MBB -> end ( ) ? DebugLoc ( ) : I -> getDebugLoc ( ) ; if ( isAtTop ( RegNo ) ) return ; unsigned STReg = getSTReg ( RegNo ) ; unsigned RegOnTop = getStackEntry ( <NUM_LIT> ) ; std :: swap ( RegMap [ RegNo ] , RegMap [ RegOnTop ] ) ; if ( RegMap [ RegOnTop ] >= StackTop ) report_fatal_error ( <STR_LIT> ) ; std :: swap ( Stack [ RegMap [ RegOnTop ] ] , Stack [ StackTop - <NUM_LIT> ] ) ; BuildMI ( * MBB , I , dl , TII ->

get ( <STR_LIT> ) ) . addReg ( STReg ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T ,


<s> break ; case FK_GPRel_4 : Type = ELF :: R_CPU0_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_32 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_LO16 ; break ; case <STR_LIT>


<s> } if ( EffectivelyUnsigned && CmpVal <= Low ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal < Low ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( CmpVal == Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( Mask == Low + High ) { if ( CCMask == <STR_LIT> && CmpVal ==


<s> unsigned NumElems = SVOp -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; unsigned NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , true , DAG ) ; unsigned OpSrc ; if ( ! NumZeros ) return false ; if ( ! isShuffleMaskConsecutive ( SVOp , NumZeros , NumElems , <NUM_LIT> , NumElems , OpSrc ) ) return false ; isLeft = true


<s> unsigned <ISA_LIT>OutgoingValueHandler :: assignCustomValue ( CallLowering :: ArgInfo & Arg , ArrayRef < CCValAssign > VAs , std :: function < void ( ) > * Thunk ) { const CCValAssign & VALo = VAs [ <NUM_LIT> ] ; const CCValAssign & VAHi = VAs [ <NUM_LIT> ] ; assert ( VALo . getLocVT ( ) == <STR_LIT> && VAHi . getLocVT ( ) == <STR_LIT> && VALo . getValVT ( ) == <STR_LIT> && VAHi . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; auto Unmerge = MIRBuilder . buildUnmerge ( { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) } , Arg . Regs [ <NUM_LIT> ] ) ; Register Lo = Unmerge . getReg ( <NUM_LIT> ) ; Register Hi = Unmerge . getReg ( <NUM_LIT> ) ; Arg . OrigRegs . assign ( Arg . Regs . begin ( ) , Arg . Regs . end ( ) ) ; Arg . Regs = { Lo , Hi } ; if ( ! STI . isLittle ( ) ) std :: swap ( Lo , Hi ) ; if ( Thunk ) { * Thunk = [ = ] ( ) { MIRBuilder . buildCopy ( VALo . getLocReg ( )


<s> if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ; if ( Reg != Base && ! MemRegs . count ( Reg ) ) AddedRegPressure . insert ( Reg ) ; } } if ( MemRegs . size ( ) <= <NUM_LIT> ) return true ; return AddedRegPressure . size ( ) <= MemRegs . size


<s> bool hasMOVBE ( ) const { return HasMOVBE


<s> return ( unsigned int ) __builtin_loongarch_cpucfg ( (


<s> bool isU1Imm ( ) const { return isImm ( <NUM_LIT> ,


<s> return AddCombineTo64bitMLAL ( N , DCI


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; if ( IsStore ) * IsStore = true ; return true ; case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; if ( IsStore ) * IsStore = true ; return true


<s> MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned scratch = RegInfo . createVirtualRegister ( <STR_LIT> ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg (


<s> bool KillFwdDefMI = ! SeenIntermediateUse && IsForwardingOperandKilled ; if ( KilledDef && KillFwdDefMI ) * KilledDef = DefMI ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; bool HasImmForm = instrHasImmForm ( MI . getOpcode ( ) , IsVFReg , III , PostRA ) ; if ( HasImmForm && transformToImmFormFedByAdd ( MI , III , ForwardingOperand , * DefMI , KillFwdDefMI ) ) return true ; if ( HasImmForm && transformToImmFormFedByLI ( MI , III ,

ForwardingOperand , * DefMI ) ) return true ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsr_u64 ( unsigned long long __X ) { return ( __X & ( __X - <NUM_LIT> )


<s> uint16_t DestEncoding = TRI -> getEncodingValue ( DestReg ) ; uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned NumRegs = Indices . size ( ) ; int SubReg = <NUM_LIT> , End = NumRegs , Incr = <NUM_LIT> ; if ( forwardCopyWillClobberTuple ( DestEncoding , SrcEncoding , NumRegs ) ) { SubReg = NumRegs - <NUM_LIT> ; End = - <NUM_LIT> ; Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder & MIB = BuildMI ( MBB , I , DL , get ( Opcode


<s> if ( Op . getValueType ( ) == <STR_LIT> && ( ! hasHardQuad || ! TLI . isTypeLegal ( OpVT ) ) ) { const char * libName = TLI . getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: SINTTOFP_I32_F128 : RTLIB :: SINTTOFP_I64_F128 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( OpVT ) ) return


<s> bool <ISA_LIT>AsmParser :: ParseOperand (


<s> int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_Select , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_Select , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { VectorType * NewMaskTy = VectorType :: get ( MaskTy -> getVectorElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy , <NUM_LIT> , MaskTy ) ; } if ( ! ST -> hasAVX512 ( ) ) return Cost + LT . first * <NUM_LIT> ; return Cost +


<s> void <ISA_LIT>InstPrinter :: printU4ImmOperand ( const MCInst * MI , int OpNum


<s> const MCSymbolRefExpr * Ref = static_cast < const MCSymbolRefExpr * > ( Expr ) ; const StringRef DefSymbol = Ref -> getSymbol ( ) . getName ( ) ; if ( DefSymbol . startswith ( <STR_LIT> ) ) { int RegNum = - <NUM_LIT> ; APInt IntVal ( <NUM_LIT> , - <NUM_LIT> ) ; if ( ! DefSymbol . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) ) RegNum = matchRegisterByNumber ( IntVal . getZExtValue ( ) , is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; else RegNum = matchRegisterName ( DefSymbol . substr ( <NUM_LIT> ) , is<ISA_LIT>64 ( ) ) ; if ( RegNum > - <NUM_LIT> ) { Parser . Lex ( ) ; <ISA_LIT>Operand * op = <STR_LIT> ( RegNum , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( ( <STR_LIT> ) RegisterKind ) ; Operands . push_back ( op ) ; return true ; } } } else if ( Expr -> getKind ( ) == MCExpr :: Constant ) { Parser . Lex ( ) ; const MCConstantExpr * Const = static_cast < const MCConstantExpr * > ( Expr ) ; <ISA_LIT>Operand * op = <STR_LIT> ( Const , S , Parser . getTok ( ) . getLoc ( ) ) ; Operands . push_back ( op ) ; return


<s> if ( FnSecName != <STR_LIT> ) { EHSecName += FnSecName ; } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , FnSection . getUniqueID ( ) , nullptr , & FnSection ) ; assert ( EHSection &&


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , & Subtarget , DAG , dl ) ; SDValue Ops [ ] = { VMask , Base , Scale


<s> } } for ( MachineBasicBlock :: iterator I = SourceRegion . BranchBlock -> getFirstNonPHI ( ) , E = SourceRegion . BranchBlock -> end ( ) ; I != E ; ++ I ) { if ( ! canMoveToBeginning ( * I , * SourceRegion . BranchTargetBlock ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; SourceRegion . MustMoveUp = true ; } if ( ! canMoveToEnd ( * I , * TargetRegion . BranchBlock ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; SourceRegion . MustMoveDown = true ; } } return ( SourceRegion . MustMoveUp && SourceRegion . MustMoveDown )


<s> SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> unsigned FixupKind = IsCrossSection ? FK_PCRel_4 : Fixup . getKind ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT>


<s> obstack_grow ( & m_string_obstack , name ,


<s> return getTM < <ISA_LIT>TargetMachine


<s> void EmitAdjustRSP ( MCContext & Ctx , MCStreamer & Out , long Offset ) { const MCExpr * Disp = MCConstantExpr :: Create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler ::


<s> if ( ! TARGET_DLLIMPORT_DECL_ATTRIBUTES || GET_CODE (


<s> if ( ! Subtarget . hasVector ( ) ) return true ; assert ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ; Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( ! isUInt < <NUM_LIT> > ( Offset ) && ( MemAccessTy -> isFloatingPointTy ( ) || MemAccessTy -> isVectorTy ( ) )


<s> for ( auto * BB : MBB -> successors ( ) ) if (

BB -> isLiveIn ( <STR_LIT> ) ) return true ;


<s> bool CC_<ISA_LIT>O32_FP64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { llvm_unreachable (


<s> if ( Flag ) { EFlags = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , * Flag ) ; Chain = EFlags . getValue ( <NUM_LIT> ) ; } else EFlags = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ; SDValue CC = getSETCC ( Cond , EFlags , DL , DAG ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , OpInfo . ConstraintVT , CC ) ; return Result


&& window_list -> num_loads >= MAX_LOAD ) || ( group == disp_store && window_list -> num_stores >= MAX_STORE ) ) return BIG ;


<s> unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; unsigned LdrOpc ; if ( Subtarget -> isTargetILP32 ( ) ) { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } else { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> | OpFlags ) ; if ( ! Subtarget -> isTargetILP32 ( ) ) return ResultReg ; unsigned Result64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( Result64 ) . addImm ( <NUM_LIT> ) . addReg (

ResultReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ;